elinnos-sv-v9-merged

Fine-tuned Qwen2.5-7B-Instruct model specialising in SystemVerilog RTL and verification for Elinnos IP blocks, including I2C master IP artifact generation.

Capabilities

1. Bidirectional translation — Verilog/SystemVerilog/Pulse HDL ↔ console logs
2. Pulse HDL tool debugging — structured JSON debug reports
3. SystemVerilog simulation output prediction (xrun)
4. SystemVerilog code generation (IEEE 1800-2017)
5. Pulse HDL bug repair
6. xrun bug repair
7. Native tool-calling
8. I2C protocol checker log summarisation
9. I2C master IP artifact generation (RTL + TB, APB/AHB host interface)

Model Details

Field	Value
Base model	Qwen2.5-7B-Instruct
Fine-tune method	QLoRA 4-bit NF4 → merged
LoRA rank	64
LoRA alpha	192
Max sequence length	16384
Training data	Merged replay buffers (v1–v8) + i2cm_production (330 samples)

Quick Start

from transformers import AutoModelForCausalLM, AutoTokenizer
import torch

model_id = "elinnos/elinnos-sv-v9-merged"
tokenizer = AutoTokenizer.from_pretrained(model_id)
model = AutoModelForCausalLM.from_pretrained(
    model_id, dtype=torch.bfloat16, device_map="auto"
)

messages = [
    {"role": "system", "content": "You are Elinnos, a hardware design assistant."},
    {"role": "user",   "content": "Write rtl/master/i2cm_defines.vh for I2C master IP i2cm."}
]
text = tokenizer.apply_chat_template(messages, tokenize=False, add_generation_prompt=True)
inputs = tokenizer(text, return_tensors="pt").to(model.device)
out = model.generate(**inputs, max_new_tokens=2048, temperature=0.1)
print(tokenizer.decode(out[0][inputs.input_ids.shape[-1]:], skip_special_tokens=True))

Scripts

Script	Purpose
inference.py	Interactive / single-prompt inference
evaluate.py	Full evaluation with BLEU, chrF, ROUGE-L, coverage metrics
run_batch_compare.py	Batch run: saves ground_truth.txt vs model_responses.txt
train_i2cm_dedicated.py	Dedicated i2cm fine-tune script
train_8bit_lora_merged.py	General LoRA fine-tune script