neural_ddr/ddr5_bridge.py

"""
Step 6: DDR5Bridge -- compose the verified units into a DDR5 logical interface
backed by the host's real RAM.

Write:  byte -> neural ECC parity -> 12-bit codeword stored in host RAM
Read:   12-bit codeword -> neural ECC decode (corrects a single-bit flip) -> byte

`inject_fault` flips a bit in stored memory to emulate a DRAM disturbance; the
neural ECC unit corrects it on read. That is the DDR5 on-die-ECC guarantee,
presented on a machine that need not have DDR5 at all.
"""
from __future__ import annotations
from . import ecc


class DDR5Bridge:
    def __init__(self, size: int, enc_net, dec_net):
        self.size = size
        self.enc = enc_net
        self.dec = dec_net
        self.mem = [0] * size                     # host RAM: 12-bit ECC codewords

    def write(self, addr: int, byte: int) -> None:
        byte &= 0xFF
        par = ecc.enc_run(self.enc, byte)         # verified neural parity
        d = [(byte >> k) & 1 for k in range(8)]
        cw = [0] * 12
        for i, pos in enumerate(ecc.DATA_POS):
            cw[pos - 1] = d[i]
        for i, j in enumerate(ecc.PAR_POS):
            cw[j - 1] = par[i]
        self.mem[addr] = sum((1 << k) for k, b in enumerate(cw) if b)

    def read(self, addr: int) -> int:
        return ecc.dec_run(self.dec, self.mem[addr])   # verified neural correct+decode

    def inject_fault(self, addr: int, bitpos: int) -> None:
        self.mem[addr] ^= (1 << bitpos)           # emulate a single-bit disturbance