source stringclasses 1
value | dataset stringclasses 2
values | id stringlengths 7 9 | file stringlengths 12 40 | task_type stringclasses 2
values | content stringlengths 36 3.73k | metadata dict |
|---|---|---|---|---|---|---|
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_300 | Prob100_fsm3comb_ifc.txt | code_completion |
module TopModule (
input in,
input [1:0] state,
output reg [1:0] next_state,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob100_fsm3comb_ifc.txt",
"file_size": 100
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_301 | Prob048_m2014_q4c_prompt.txt | code_completion |
Implement a simple D flip flop with active high synchronous reset (reset
output to 0).
module TopModule (
input clk,
input d,
input r,
output logic q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob048_m2014_q4c_prompt.txt",
"file_size": 164
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_302 | Prob014_andgate_prompt.txt | code_completion |
Create a module that implements an AND gate.
module TopModule (
input a,
input b,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob014_andgate_prompt.txt",
"file_size": 105
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_303 | Prob116_m2014_q3_prompt.txt | code_completion |
Consider the function f shown in the Karnaugh map below. d is don't-care,
which means you may choose to output whatever value is convenient.
Implement this function.
x[1]x[2]
x[3]x[4] 00 01 11 10
00 | d | 0 | d | d |
01 | 0 | d | 1 | 0 |
11 | 1 | 1 | d | d |
10 |... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob116_m2014_q3_prompt.txt",
"file_size": 395
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_304 | Prob005_notgate_prompt.txt | code_completion |
Create a module that implements a NOT gate.
module TopModule (
input in,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob005_notgate_prompt.txt",
"file_size": 94
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_305 | Prob022_mux2to1_ifc.txt | code_completion |
module TopModule (
input a,
input b,
input sel,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob022_mux2to1_ifc.txt",
"file_size": 71
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_306 | Prob075_counter_2bc_ifc.txt | code_completion |
module TopModule (
input clk,
input areset,
input train_valid,
input train_taken,
output logic [1:0] state
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob075_counter_2bc_ifc.txt",
"file_size": 121
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_307 | Prob144_conwaylife_prompt.txt | code_completion |
The "game" is played on a two-dimensional grid of cells, where each cell
is either 1 (alive) or 0 (dead). At each time step, each cell changes
state depending on how many neighbours it has:
(1) 0-1 neighbour: Cell becomes 0.
(2) 2 neighbours: Cell state does not change.
(3) 3 neighbours: Cell becomes 1.
(4) 4... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob144_conwaylife_prompt.txt",
"file_size": 1182
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_308 | Prob147_circuit10_prompt.txt | code_completion |
This is a sequential circuit. The circuit consists of combinational logic
and one bit of memory (i.e., one flip-flop). The output of the flip-flop
has been made observable through the output state.
Read the simulation waveforms to determine what the circuit does, then implement it.
time clk ... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob147_circuit10_prompt.txt",
"file_size": 3734
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_309 | Prob052_gates100_ifc.txt | code_completion |
module TopModule (
input [99:0] in,
output out_and,
output out_or,
output out_xor
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob052_gates100_ifc.txt",
"file_size": 94
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_310 | Prob119_fsm3_ifc.txt | code_completion |
module TopModule (
input clk,
input in,
input areset,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob119_fsm3_ifc.txt",
"file_size": 77
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_311 | Prob050_kmap1_ifc.txt | code_completion |
module TopModule (
input a,
input b,
input c,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob050_kmap1_ifc.txt",
"file_size": 69
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_312 | Prob148_2013_q2afsm_ifc.txt | code_completion |
module TopModule (
input clk,
input resetn,
input [3:1] r,
output [3:1] g
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob148_2013_q2afsm_ifc.txt",
"file_size": 86
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_313 | Prob114_bugs_case_ifc.txt | code_completion |
module TopModule (
input [7:0] code,
output reg [3:0] out,
output reg valid
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob114_bugs_case_ifc.txt",
"file_size": 86
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_314 | Prob078_dualedge_ifc.txt | code_completion |
module TopModule (
input clk,
input d,
output reg q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob078_dualedge_ifc.txt",
"file_size": 62
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_315 | Prob015_vector1_ifc.txt | code_completion |
module TopModule (
input [15:0] in,
output [7:0] out_hi,
output [7:0] out_lo
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob015_vector1_ifc.txt",
"file_size": 87
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_316 | Prob091_2012_q2b_prompt.txt | code_completion |
Consider the state machine shown below:
A (0) --1--> B
A (0) --0--> A
B (0) --1--> C
B (0) --0--> D
C (0) --1--> E
C (0) --0--> D
D (0) --1--> F
D (0) --0--> A
E (1) --1--> E
E (1) --0--> D
F (1) --1--> C
F (1) --0--> D
Assume that a one-hot code is used with the state assignment y[5:0] =
000... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob091_2012_q2b_prompt.txt",
"file_size": 664
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_317 | Prob025_reduction_ifc.txt | code_completion |
module TopModule (
input [7:0] in,
output parity
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob025_reduction_ifc.txt",
"file_size": 57
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_318 | Prob071_always_casez_ifc.txt | code_completion |
module TopModule (
input [7:0] in,
output reg [2:0] pos
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob071_always_casez_ifc.txt",
"file_size": 64
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_319 | Prob024_hadd_prompt.txt | code_completion |
Create a half adder. A half adder adds two bits (with no carry-in) and
produces a sum and carry-out.
module TopModule (
input a,
input b,
output sum,
output cout
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob024_hadd_prompt.txt",
"file_size": 176
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_320 | Prob046_dff8p_prompt.txt | code_completion |
Create 8 D flip-flops with active high synchronous reset. The flip-flops
must be reset to 0x34 rather than zero. All DFFs should be triggered by
the negative edge of clk.
module TopModule (
input clk,
input [7:0] d,
input reset,
output reg [7:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob046_dff8p_prompt.txt",
"file_size": 262
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_321 | Prob031_dff_prompt.txt | code_completion |
Create a single D flip-flop.
module TopModule (
input clk,
input d,
output reg q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob031_dff_prompt.txt",
"file_size": 93
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_322 | Prob009_popcount3_ifc.txt | code_completion |
module TopModule (
input [2:0] in,
output [1:0] out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob009_popcount3_ifc.txt",
"file_size": 60
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_323 | Prob044_vectorgates_prompt.txt | code_completion |
Build a circuit that has two 3-bit inputs that computes the bitwise-OR of
the two vectors, the logical-OR of the two vectors, and the inverse (NOT)
of both vectors. Place the inverse of b in the upper half of out_not
(i.e., bits [5:3]), and the inverse of a in the lower half.
module TopModule (
input [2:0] a,
inp... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob044_vectorgates_prompt.txt",
"file_size": 415
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_324 | Prob088_ece241_2014_q5b_prompt.txt | code_completion |
The following diagram is a Mealy machine implementation of the 2's
complementer. Implement in Verilog using one-hot encoding. Resets into
state A and reset is asynchronous active-high.
A --x=0 (z=0)--> A
A --x=1 (z=1)--> B
B --x=0 (z=1)--> B
B --x=1 (z=0)--> B
module TopModule (
input clk,
input areset,
... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob088_ece241_2014_q5b_prompt.txt",
"file_size": 346
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_325 | Prob017_mux2to1v_prompt.txt | code_completion |
Create a 2-1 multiplexer. When sel=0, choose a. When sel=1, choose b.
module TopModule (
input [99:0] a,
input [99:0] b,
input sel,
output [99:0] out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob017_mux2to1v_prompt.txt",
"file_size": 164
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_326 | Prob041_dff8r_ifc.txt | code_completion |
module TopModule (
input clk,
input [7:0] d,
input reset,
output reg [7:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob041_dff8r_ifc.txt",
"file_size": 89
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_327 | Prob136_m2014_q6_ifc.txt | code_completion |
module TopModule (
input clk,
input reset,
input w,
output z
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob136_m2014_q6_ifc.txt",
"file_size": 73
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_328 | Prob074_ece241_2014_q4_ifc.txt | code_completion |
module TopModule (
input clk,
input x,
output z
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob074_ece241_2014_q4_ifc.txt",
"file_size": 58
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_329 | Prob072_thermostat_ifc.txt | code_completion |
module TopModule (
input mode,
input too_cold,
input too_hot,
input fan_on,
output heater,
output aircon,
output fan
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob072_thermostat_ifc.txt",
"file_size": 135
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_330 | Prob125_kmap3_ifc.txt | code_completion |
module TopModule (
input a,
input b,
input c,
input d,
output reg out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob125_kmap3_ifc.txt",
"file_size": 84
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_331 | Prob036_ringer_ifc.txt | code_completion |
module TopModule (
input ring,
input vibrate_mode,
output ringer,
output motor
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob036_ringer_ifc.txt",
"file_size": 91
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_332 | Prob050_kmap1_prompt.txt | code_completion |
Implement the circuit described by the Karnaugh map below.
a
bc 0 1
00 | 0 | 1 |
01 | 1 | 1 |
11 | 1 | 1 |
10 | 1 | 1 |
module TopModule (
input a,
input b,
input c,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob050_kmap1_prompt.txt",
"file_size": 221
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_333 | Prob097_mux9to1v_prompt.txt | code_completion |
Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses
b, etc. For the unused cases (sel=9 to 15), set all output bits to '1'.
module TopModule (
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [15:0] d,
input [15:0] e,
input [15:0] f,
input [15:0] g,
input [15:0] h,
input [1... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob097_mux9to1v_prompt.txt",
"file_size": 377
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_334 | Prob003_step_one_ifc.txt | code_completion |
module TopModule (
output one
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob003_step_one_ifc.txt",
"file_size": 36
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_335 | Prob130_circuit5_prompt.txt | code_completion |
This is a combinational circuit. Read the simulation waveforms to
determine what the circuit does, then implement it.
time a b c d e q
0ns x x x x x x
5ns x x x x x x
10ns x x x x x x
15ns a b 0 d e b
20ns a b 1 d e e
25ns a b 2 d e a
30ns a b 3 d e d
... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob130_circuit5_prompt.txt",
"file_size": 750
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_336 | Prob057_kmap2_prompt.txt | code_completion |
Implement the circuit described by the Karnaugh map below.
ab
cd 00 01 11 10
00 | 1 | 1 | 0 | 1 |
01 | 1 | 0 | 0 | 1 |
11 | 0 | 1 | 1 | 1 |
10 | 1 | 1 | 0 | 0 |
module TopModule (
input a,
input b,
input c,
input d,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob057_kmap2_prompt.txt",
"file_size": 278
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_337 | Prob039_always_if_ifc.txt | code_completion |
module TopModule (
input a,
input b,
input sel_b1,
input sel_b2,
output out_assign,
output reg out_always
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob039_always_if_ifc.txt",
"file_size": 122
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_338 | Prob018_mux256to1_ifc.txt | code_completion |
module TopModule (
input [255:0] in,
input [7:0] sel,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob018_mux256to1_ifc.txt",
"file_size": 76
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_339 | Prob013_m2014_q4e_ifc.txt | code_completion |
module TopModule (
input in1,
input in2,
output logic out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob013_m2014_q4e_ifc.txt",
"file_size": 68
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_340 | Prob070_ece241_2013_q2_ifc.txt | code_completion |
module TopModule (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob070_ece241_2013_q2_ifc.txt",
"file_size": 102
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_341 | Prob023_vector100r_prompt.txt | code_completion |
Given a 100-bit input vector [99:0], reverse its bit ordering.
a
module TopModule (
input [99:0] in,
output reg [99:0] out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob023_vector100r_prompt.txt",
"file_size": 134
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_342 | problems.txt | code_completion | Prob001_zero
Prob002_m2014_q4i
Prob003_step_one
Prob004_vector2
Prob005_notgate
Prob006_vectorr
Prob007_wire
Prob008_m2014_q4h
Prob009_popcount3
Prob010_mt2015_q4a
Prob011_norgate
Prob012_xnorgate
Prob013_m2014_q4e
Prob014_andgate
Prob015_vector1
Prob016_m2014_q4j
Prob017_mux2to1v
Prob018_mux256to1
Prob019_m2014_q4f
Pr... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/problems.txt",
"file_size": 2814
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_343 | Prob079_fsm3onehot_ifc.txt | code_completion |
module TopModule (
input in,
input [3:0] state,
output reg [3:0] next_state,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob079_fsm3onehot_ifc.txt",
"file_size": 100
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_344 | Prob101_circuit4_ifc.txt | code_completion |
module TopModule (
input a,
input b,
input c,
input d,
output q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob101_circuit4_ifc.txt",
"file_size": 78
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_345 | Prob100_fsm3comb_prompt.txt | code_completion |
The following is the state transition table for a Moore state machine
with one input, one output, and four states. Use the following state
encoding: A=2'b00, B=2'b01, C=2'b10, D=2'b11.Implement only the state
transition logic and output logic (the combinational logic portion) for
this state machine. Given the current ... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob100_fsm3comb_prompt.txt",
"file_size": 754
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_346 | Prob122_kmap4_prompt.txt | code_completion |
Implement the circuit described by the Karnaugh map below.
ab
cd 00 01 11 10
00 | 0 | 1 | 0 | 1 |
01 | 1 | 0 | 1 | 0 |
11 | 0 | 1 | 0 | 1 |
10 | 1 | 0 | 1 | 0 |
module TopModule (
input a,
input b,
input c,
input d,
output reg out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob122_kmap4_prompt.txt",
"file_size": 276
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_347 | Prob121_2014_q3bfsm_ifc.txt | code_completion |
module TopModule (
input clk,
input reset,
input x,
output reg z
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob121_2014_q3bfsm_ifc.txt",
"file_size": 77
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_348 | Prob015_vector1_prompt.txt | code_completion |
Build a combinational circuit that splits an input half-word (16 bits,
[15:0] ) into lower [7:0] and upper [15:8] bytes.
module TopModule (
input [15:0] in,
output [7:0] out_hi,
output [7:0] out_lo
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob015_vector1_prompt.txt",
"file_size": 210
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_349 | Prob130_circuit5_ifc.txt | code_completion |
module TopModule (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output reg [3:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob130_circuit5_ifc.txt",
"file_size": 129
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_350 | Prob062_bugs_mux2_prompt.txt | code_completion |
Find the bug and fix this 8-bit wide 2-to-1 mux.
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output out );
assign out = (~sel & a) | (sel & b);
endmodule
module TopModule (
input sel,
input [7:0] a,
input [7:0] b,
output reg [7:0] out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob062_bugs_mux2_prompt.txt",
"file_size": 304
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_351 | Prob082_lfsr32_ifc.txt | code_completion |
module TopModule (
input clk,
input reset,
output reg [31:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob082_lfsr32_ifc.txt",
"file_size": 73
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_352 | Prob043_vector5_ifc.txt | code_completion |
module TopModule (
input a,
input b,
input c,
input d,
input e,
output [24:0] out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob043_vector5_ifc.txt",
"file_size": 98
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_353 | Prob114_bugs_case_prompt.txt | code_completion |
This combinational circuit is supposed to recognize 8-bit keyboard
scancodes for keys 0 through 9. It should indicate whether one of the 10
cases were recognized (valid), and if so, which key was detected. If the
8-bit input is 8'h45, 8'h16, 8'h1e, 8'h26, 8'h25, 8'h2e, 8'h36, 8'h3d,
8'h3e, or 8'h46, the 4-bit output w... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob114_bugs_case_prompt.txt",
"file_size": 587
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_354 | Prob090_circuit1_prompt.txt | code_completion |
This is a combinational circuit. Read the simulation waveforms to
determine what the circuit does, then implement it.
time a b q
0ns 0 0 0
5ns 0 0 0
10ns 0 0 ... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob090_circuit1_prompt.txt",
"file_size": 1217
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_355 | Prob156_review2015_fancytimer_ifc.txt | code_completion |
module TopModule (
input wire clk,
input wire reset,
input wire data,
output wire [3:0] count,
output reg counting,
output reg done,
input wire ack
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob156_review2015_fancytimer_ifc.txt",
"file_size": 166
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_356 | Prob027_fadd_ifc.txt | code_completion |
module TopModule (
input a,
input b,
input cin,
output cout,
output sum
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob027_fadd_ifc.txt",
"file_size": 86
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_357 | Prob049_m2014_q4b_prompt.txt | code_completion |
Implement a D flip flop, positive edge triggered, with an asynchronous
reset "ar".
module TopModule (
input clk,
input d,
input ar,
output logic q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob049_m2014_q4b_prompt.txt",
"file_size": 161
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_358 | Prob118_history_shift_prompt.txt | code_completion |
Build a 32-bit global history shift register, including support for
rolling back state in response to a pipeline flush caused by a branch
misprediction. When a branch prediction is made (predict_valid = 1),
shift in predict_taken from the LSB side to update the branch history for
the predicted branch. (predict_history... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob118_history_shift_prompt.txt",
"file_size": 1228
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_359 | Prob078_dualedge_prompt.txt | code_completion |
A dual-edge triggered flip-flop is triggered on both edges of the clock.
However, FPGAs don't have dual-edge triggered flip-flops, and always
@(posedge clk or negedge clk) is not accepted as a legal sensitivity
list. Build a circuit that functionally behaves like a dual-edge
triggered flip-flop.
module TopModule (
... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob078_dualedge_prompt.txt",
"file_size": 361
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_360 | Prob147_circuit10_ifc.txt | code_completion |
module TopModule (
input clk,
input a,
input b,
output q,
output state
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob147_circuit10_ifc.txt",
"file_size": 85
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_361 | Prob094_gatesv_ifc.txt | code_completion |
module TopModule (
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob094_gatesv_ifc.txt",
"file_size": 119
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_362 | Prob004_vector2_prompt.txt | code_completion |
Build a circuit that reverses the byte order of a 32-bit vector.
module TopModule (
input [31:0] in,
output [31:0] out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob004_vector2_prompt.txt",
"file_size": 129
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_363 | Prob003_step_one_prompt.txt | code_completion |
Build a circuit with no inputs and one output. That output should always
drive 1 (or logic high).
module TopModule (
output one
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob003_step_one_prompt.txt",
"file_size": 136
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_364 | Prob064_vector3_ifc.txt | code_completion |
module TopModule (
input [4:0] a,
input [4:0] b,
input [4:0] c,
input [4:0] d,
input [4:0] e,
input [4:0] f,
output [7:0] w,
output [7:0] x,
output [7:0] y,
output [7:0] z
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob064_vector3_ifc.txt",
"file_size": 196
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_365 | Prob018_mux256to1_prompt.txt | code_completion |
Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed
into a single 256-bit input vector. sel=0 should select in[0], sel=1
selects bits in[1], sel=2 selects bits in[2], etc.
module TopModule (
input [255:0] in,
input [7:0] sel,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob018_mux256to1_prompt.txt",
"file_size": 271
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_366 | Prob012_xnorgate_prompt.txt | code_completion |
Create a module that implements an XNOR gate.
module TopModule (
input a,
input b,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob012_xnorgate_prompt.txt",
"file_size": 106
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_367 | Prob141_count_clock_ifc.txt | code_completion |
module TopModule (
input clk,
input reset,
input ena,
output reg pm,
output reg [7:0] hh,
output reg [7:0] mm,
output reg [7:0] ss
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob141_count_clock_ifc.txt",
"file_size": 149
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_368 | Prob062_bugs_mux2_ifc.txt | code_completion |
module TopModule (
input sel,
input [7:0] a,
input [7:0] b,
output reg [7:0] out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob062_bugs_mux2_ifc.txt",
"file_size": 93
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_369 | Prob105_rotate100_ifc.txt | code_completion |
module TopModule (
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob105_rotate100_ifc.txt",
"file_size": 112
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_370 | Prob027_fadd_prompt.txt | code_completion |
Create a full adder. A full adder adds three bits (including carry-in)
and produces a sum and carry-out.
module TopModule (
input a,
input b,
input cin,
output cout,
output sum
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob027_fadd_prompt.txt",
"file_size": 193
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_371 | Prob020_mt2015_eq2_ifc.txt | code_completion |
module TopModule (
input [1:0] A,
input [1:0] B,
output z
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob020_mt2015_eq2_ifc.txt",
"file_size": 68
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_372 | Prob117_circuit9_prompt.txt | code_completion |
This is a sequential circuit. Read the simulation waveforms to determine
what the circuit does, then implement it.
time clk a q
0ns 0 1 x
5ns 1 1 4
10ns 0 1 4
15ns 1 1 4
20ns 0 1 4
25ns 1 1 4
30ns 0 1 4
35ns 1 1 4
40ns 0 1 4
45ns 1 0 4
50n... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob117_circuit9_prompt.txt",
"file_size": 546
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_373 | Prob106_always_nolatches_prompt.txt | code_completion |
Suppose you're building a circuit to process scancodes from a PS/2
keyboard for a game. Given the last two bytes of scancodes received, you
need to indicate whether one of the arrow keys on the keyboard have been
pressed. This involves a fairly simple mapping, which can be implemented
as a case statement (or if-elseif... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob106_always_nolatches_prompt.txt",
"file_size": 777
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_374 | Prob153_gshare_prompt.txt | code_completion |
Build a gshare branch predictor with 7-bit pc and 7-bit global history,
hashed (using xor) into a 7-bit index. This index accesses a 128-entry
table of two-bit saturating counters. The branch predictor should contain
a 7-bit global branch history register. The branch predictor has two sets
of interfaces: One for doing... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob153_gshare_prompt.txt",
"file_size": 2712
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_375 | Prob002_m2014_q4i_ifc.txt | code_completion |
module TopModule (
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob002_m2014_q4i_ifc.txt",
"file_size": 36
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_376 | Prob085_shift4_prompt.txt | code_completion |
Build a 4-bit shift register (right shift), with asynchronous positive
edge triggered areset, synchronous active high signals load, and enable.
(1) areset: Resets shift register to zero.
(2) load: Loads shift register with data[3:0] instead of shifting.
(3) ena: Shift right (q[3] becomes zero, q[0] is shifted... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob085_shift4_prompt.txt",
"file_size": 609
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_377 | Prob024_hadd_ifc.txt | code_completion |
module TopModule (
input a,
input b,
output sum,
output cout
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob024_hadd_ifc.txt",
"file_size": 73
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_378 | Prob022_mux2to1_prompt.txt | code_completion |
Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When
sel=1, choose b.
module TopModule (
input a,
input b,
input sel,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob022_mux2to1_prompt.txt",
"file_size": 160
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_379 | Prob153_gshare_ifc.txt | code_completion |
module TopModule (
input clk,
input areset,
input predict_valid,
input [6:0] predict_pc,
output predict_taken,
output [6:0] predict_history,
input train_valid,
input train_taken,
input train_mispredicted,
input [6:0] train_history,
input [6:0] train_pc
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob153_gshare_ifc.txt",
"file_size": 281
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_380 | Prob040_count10_prompt.txt | code_completion |
Build a decade counter that counts from 0 through 9, inclusive, with a
period of 10. The reset input is active high synchronous, and should
reset the counter to 0.
module TopModule (
input clk,
input reset,
output reg [3:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob040_count10_prompt.txt",
"file_size": 238
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_381 | Prob146_fsm_serialdata_ifc.txt | code_completion |
module TopModule (
input clk,
input in,
input reset,
output [7:0] out_byte,
output done
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob146_fsm_serialdata_ifc.txt",
"file_size": 102
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_382 | Prob102_circuit3_prompt.txt | code_completion |
This is a combinational circuit. Read the simulation waveforms to
determine what the circuit does, then implement it.
time a b c d q
0ns 0 0 0 0 0
5ns 0 0 0 0 0
10ns 0 0 0 0 0
15ns 0 0 0 0 0
20ns 0 0 0 1 0
25ns 0 0 1 0 0
30ns 0 0 1 1 0
35ns 0 1 0 0 0
... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob102_circuit3_prompt.txt",
"file_size": 639
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_383 | Prob026_alwaysblock1_prompt.txt | code_completion |
Build an AND gate using both an assign statement and a combinational
always block.
module TopModule (
input a,
input b,
output out_assign,
output reg out_alwaysblock
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob026_alwaysblock1_prompt.txt",
"file_size": 180
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_384 | Prob058_alwaysblock2_ifc.txt | code_completion |
module TopModule (
input clk,
input a,
input b,
output out_assign,
output reg out_always_comb,
output reg out_always_ff
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob058_alwaysblock2_ifc.txt",
"file_size": 136
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_385 | Prob121_2014_q3bfsm_prompt.txt | code_completion |
Given the state-assigned table shown below, implement the finite-state
machine. Reset should synchronous active high reset the FSM to state 000.
Present state y[2:0] | Next state y[2:0] x=0, Next state y[2:0] x=1 | Output z
000 | 000, 001 | 0
001 | 001, 100 | 0
010 | 010, 001 | 0
011 | 001, 010 | 1
100 | ... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob121_2014_q3bfsm_prompt.txt",
"file_size": 411
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_386 | Prob106_always_nolatches_ifc.txt | code_completion |
module TopModule (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob106_always_nolatches_ifc.txt",
"file_size": 122
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_387 | Prob089_ece241_2014_q5a_ifc.txt | code_completion |
module TopModule (
input clk,
input areset,
input x,
output z
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob089_ece241_2014_q5a_ifc.txt",
"file_size": 74
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_388 | Prob037_review2015_count1k_ifc.txt | code_completion |
module TopModule (
input clk,
input reset,
output reg [9:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob037_review2015_count1k_ifc.txt",
"file_size": 72
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_389 | Prob092_gatesv100_prompt.txt | code_completion |
You are given a 100-bit input vector in[99:0]. We want to know some
relationships between each bit and its neighbour:
(1) out_both: Each bit of this output vector should indicate whether
both the corresponding input bit and its neighbour to the left are '1'.
For example, out_both[98] should indicate if in[98] a... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob092_gatesv100_prompt.txt",
"file_size": 1239
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_390 | Prob095_review2015_fsmshift_ifc.txt | code_completion |
module TopModule (
input clk,
input reset,
output shift_ena
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob095_review2015_fsmshift_ifc.txt",
"file_size": 70
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_391 | Prob032_vector0_prompt.txt | code_completion |
Build a circuit that has one 3-bit input, then outputs the same vector,
and also splits it into three separate 1-bit outputs. Connect output o0
to the input vector's position 0, o1 to position 1, etc.
module TopModule (
input [2:0] vec,
output [2:0] outv,
output o2,
output o1,
output o0
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob032_vector0_prompt.txt",
"file_size": 304
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_392 | Prob103_circuit2_ifc.txt | code_completion |
module TopModule (
input a,
input b,
input c,
input d,
output q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob103_circuit2_ifc.txt",
"file_size": 78
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_393 | Prob138_2012_q2fsm_prompt.txt | code_completion |
Consider the state machine shown below:
A (0) --1--> B
A (0) --0--> A
B (0) --1--> C
B (0) --0--> D
C (0) --1--> E
C (0) --0--> D
D (0) --1--> F
D (0) --0--> A
E (1) --1--> E
E (1) --0--> D
F (1) --1--> C
F (1) --0--> D
Reset resets into state A and is synchronous active-high.
Write complete... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob138_2012_q2fsm_prompt.txt",
"file_size": 695
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_394 | Prob076_always_case_prompt.txt | code_completion |
Create a 6-to-1 multiplexer. When sel is between 0 and 5, choose the
corresponding data input. Otherwise, output 0. The data inputs and
outputs are all 4 bits wide.
module TopModule (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob076_always_case_prompt.txt",
"file_size": 358
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_395 | Prob044_vectorgates_ifc.txt | code_completion |
module TopModule (
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob044_vectorgates_ifc.txt",
"file_size": 136
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_396 | Prob102_circuit3_ifc.txt | code_completion |
module TopModule (
input a,
input b,
input c,
input d,
output q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob102_circuit3_ifc.txt",
"file_size": 78
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_397 | Prob053_m2014_q4d_prompt.txt | code_completion |
Implement in Verilog the following circuit: A D flip-flop takes as input
the output of a two-input XOR. The flip-flop is positive edge triggered
by clk, but there is no reset. The XOR takes as input 'in' along with the
output 'out' of the flip-flop.
module TopModule (
input clk,
input in,
output logic out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob053_m2014_q4d_prompt.txt",
"file_size": 319
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_398 | Prob042_vector4_ifc.txt | code_completion |
module TopModule (
input [7:0] in,
output [31:0] out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob042_vector4_ifc.txt",
"file_size": 61
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_399 | Prob021_mux256to1v_ifc.txt | code_completion |
module TopModule (
input [1023:0] in,
input [7:0] sel,
output [3:0] out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob021_mux256to1v_ifc.txt",
"file_size": 82
} |
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