source stringclasses 1
value | dataset stringclasses 2
values | id stringlengths 7 9 | file stringlengths 12 40 | task_type stringclasses 2
values | content stringlengths 36 3.73k | metadata dict |
|---|---|---|---|---|---|---|
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_400 | Prob116_m2014_q3_ifc.txt | code_completion |
module TopModule (
input [4:1] x,
output logic f
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob116_m2014_q3_ifc.txt",
"file_size": 57
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_401 | Prob120_fsm3s_ifc.txt | code_completion |
module TopModule (
input clk,
input in,
input reset,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob120_fsm3s_ifc.txt",
"file_size": 76
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_402 | Prob063_review2015_shiftcount_prompt.txt | code_completion |
Build a four-bit shift register that also acts as a down counter. Data is
shifted in most-significant-bit first when shift_ena is 1. The number
currently in the shift register is decremented when count_ena is 1. Since
the full system doesn't ever use shift_ena and count_ena together, it
does not matter what your circu... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob063_review2015_shiftcount_prompt.txt",
"file_size": 543
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_403 | Prob142_lemmings2_ifc.txt | code_completion |
module TopModule (
input clk,
input areset,
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob142_lemmings2_ifc.txt",
"file_size": 162
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_404 | Prob108_rule90_ifc.txt | code_completion |
module TopModule (
input clk,
input load,
input [511:0] data,
output reg [511:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob108_rule90_ifc.txt",
"file_size": 95
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_405 | Prob028_m2014_q4a_ifc.txt | code_completion |
module TopModule (
input d,
input ena,
output logic q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob028_m2014_q4a_ifc.txt",
"file_size": 64
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_406 | Prob036_ringer_prompt.txt | code_completion |
Suppose you are designing a circuit to control a cellphone's ringer and
vibration motor. Whenever the phone needs to ring from an incoming call
(input ring), your circuit must either turn on the ringer (output ringer
= 1) or the motor (output motor = 1), but not both. If the phone is in
vibrate mode (input vibrate_mod... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob036_ringer_prompt.txt",
"file_size": 470
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_407 | Prob034_dff8_ifc.txt | code_completion |
module TopModule (
input clk,
input [7:0] d,
output reg [7:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob034_dff8_ifc.txt",
"file_size": 74
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_408 | Prob093_ece241_2014_q3_prompt.txt | code_completion |
For the following Karnaugh map, give the circuit implementation using one
4-to-1 multiplexer and as many 2-to-1 multiplexers as required, but using
as few as possible. You are not allowed to use any other logic gate and
you must use _a_ and _b_ as the multiplexer selector inputs, as shown on
the 4-to-1 multiplexer bel... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob093_ece241_2014_q3_prompt.txt",
"file_size": 951
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_409 | Prob146_fsm_serialdata_prompt.txt | code_completion |
In many (older) serial communications protocols, each data byte is sent
along with a start bit and a stop bit, to help the receiver delimit bytes
from the stream of bits. One common scheme is to use one start bit (0), 8
data bits, and 1 stop bit (1). The line is also at logic 1 when nothing
is being transmitted (idle)... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob146_fsm_serialdata_prompt.txt",
"file_size": 1080
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_410 | Prob049_m2014_q4b_ifc.txt | code_completion |
module TopModule (
input clk,
input d,
input ar,
output logic q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob049_m2014_q4b_ifc.txt",
"file_size": 76
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_411 | Prob054_edgedetect_prompt.txt | code_completion |
For each bit in an 8-bit vector, detect when the input signal changes
from 0 in one clock cycle to 1 the next (similar to positive edge
detection). The output bit should be set the cycle after a 0 to 1
transition occurs.
module TopModule (
input clk,
input [7:0] in,
output reg [7:0] pedge
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob054_edgedetect_prompt.txt",
"file_size": 302
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_412 | Prob019_m2014_q4f_prompt.txt | code_completion |
Implement the following circuit in Verilog. Two inputs (in1 and in2) go
to an AND gate, but the in2 input to the AND gate has a bubble. The
output of the AND gate is connected to 'out'.
module TopModule (
input in1,
input in2,
output logic out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob019_m2014_q4f_prompt.txt",
"file_size": 256
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_413 | Prob101_circuit4_prompt.txt | code_completion |
This is a combinational circuit. Read the simulation waveforms to
determine what the circuit does, then implement it.
time a b c d q
0ns 0 0 0 0 0
5ns 0 0 0 0 0
10ns 0 0 0 0 0
15ns 0 0 0 0 0
20ns 0 0 0 1 0
25ns 0 0 1 0 1
30ns 0 0 1 1 1
35ns 0 1 0 0 1
... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob101_circuit4_prompt.txt",
"file_size": 639
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_414 | Prob056_ece241_2013_q7_ifc.txt | code_completion |
module TopModule (
input clk,
input j,
input k,
output reg Q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob056_ece241_2013_q7_ifc.txt",
"file_size": 73
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_415 | Prob109_fsm1_prompt.txt | code_completion |
Consider the follow Moore machine with the diagram described below:
B (1) --0--> A
B (1) --1--> B
A (0) --0--> B
A (0) --1--> A
Write Verilog implementing this state machine. It should asynchronously
reset into state B if reset if high.
module TopModule (
input clk,
input in,
input areset,
output ou... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob109_fsm1_prompt.txt",
"file_size": 326
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_416 | Prob111_fsm2s_prompt.txt | code_completion |
This is a Moore state machine with two states, two inputs, and one
output. Implement this state machine in Verilog. Reset is an active-high
synchronous reset to state OFF.
OFF (out=0) --j=0--> OFF
OFF (out=0) --j=1--> ON
ON (out=1) --k=0--> ON
ON (out=1) --k=1--> OFF
module TopModule (
input clk,
input... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob111_fsm2s_prompt.txt",
"file_size": 367
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_417 | Prob117_circuit9_ifc.txt | code_completion |
module TopModule (
input clk,
input a,
output reg [2:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob117_circuit9_ifc.txt",
"file_size": 68
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_418 | Prob119_fsm3_prompt.txt | code_completion |
The following is the state transition table for a Moore state machine
with one input, one output, and four states. Implement this state
machine. Include a positive edge triggered asynchronous reset that resets
the FSM to state A.
state | next state in=0, next state in=1 | output
A | A, B ... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob119_fsm3_prompt.txt",
"file_size": 550
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_419 | Prob073_dff16e_ifc.txt | code_completion |
module TopModule (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output reg [15:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob073_dff16e_ifc.txt",
"file_size": 115
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_420 | Prob029_m2014_q4g_prompt.txt | code_completion |
Implement in Verilog the following circuit: A two-input XNOR (connected
to 'in1' and 'in2) has an output connected to the input of a two-input
XOR. The second input of the XOR is 'in3.' The output of the XOR is
'out'.
module TopModule (
input in1,
input in2,
input in3,
output logic out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob029_m2014_q4g_prompt.txt",
"file_size": 301
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_421 | Prob154_fsm_ps2data_ifc.txt | code_completion |
module TopModule (
input clk,
input [7:0] in,
input reset,
output [23:0] out_bytes,
output done
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob154_fsm_ps2data_ifc.txt",
"file_size": 110
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_422 | Prob137_fsm_serial_prompt.txt | code_completion |
In many (older) serial communications protocols, each data byte is sent
along with a start bit and a stop bit, to help the receiver delimit bytes
from the stream of bits. One common scheme is to use one start bit (0), 8
data bits, and 1 stop bit (1). The line is also at logic 1 when nothing
is being transmitted (idle)... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob137_fsm_serial_prompt.txt",
"file_size": 868
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_423 | Prob005_notgate_ifc.txt | code_completion |
module TopModule (
input in,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob005_notgate_ifc.txt",
"file_size": 48
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_424 | Prob060_m2014_q4k_prompt.txt | code_completion |
Implement a shift register with four D flops. Reset is active-low
synchronous resettable.
module TopModule (
input clk,
input resetn,
input in,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob060_m2014_q4k_prompt.txt",
"file_size": 169
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_425 | Prob039_always_if_prompt.txt | code_completion |
Build a 2-to-1 mux that chooses between a and b. Choose b if both sel_b1
and sel_b2 are true. Otherwise, choose a. Do the same twice, once using
assign statements and once using a procedural if statement.
module TopModule (
input a,
input b,
input sel_b1,
input sel_b2,
output out_assign,
output reg out_al... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob039_always_if_prompt.txt",
"file_size": 329
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_426 | Prob068_countbcd_ifc.txt | code_completion |
module TopModule (
input clk,
input reset,
output [3:1] ena,
output reg [15:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob068_countbcd_ifc.txt",
"file_size": 93
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_427 | Prob142_lemmings2_prompt.txt | code_completion |
The game Lemmings involves critters with fairly simple brains. So simple
that we are going to model it using a finite state machine. In the
Lemmings' 2D world, Lemmings can be in one of two states: walking left
(walk_left is 1) or walking right (walk_right is 1). It will switch
directions if it hits an obstacle. In pa... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob142_lemmings2_prompt.txt",
"file_size": 1373
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_428 | Prob051_gates4_ifc.txt | code_completion |
module TopModule (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob051_gates4_ifc.txt",
"file_size": 93
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_429 | Prob151_review2015_fsm_ifc.txt | code_completion |
module TopModule (
input clk,
input reset,
input data,
output reg shift_ena,
output reg counting,
input done_counting,
output reg done,
input ack
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob151_review2015_fsm_ifc.txt",
"file_size": 166
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_430 | Prob041_dff8r_prompt.txt | code_completion |
Create 8 D flip-flops with active high synchronous reset setting the
output to zero. All DFFs should be triggered by the positive edge of clk.
module TopModule (
input clk,
input [7:0] d,
input reset,
output reg [7:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob041_dff8r_prompt.txt",
"file_size": 234
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_431 | Prob155_lemmings4_ifc.txt | code_completion |
module TopModule (
input clk,
input areset,
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob155_lemmings4_ifc.txt",
"file_size": 193
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_432 | Prob048_m2014_q4c_ifc.txt | code_completion |
module TopModule (
input clk,
input d,
input r,
output logic q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob048_m2014_q4c_ifc.txt",
"file_size": 75
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_433 | Prob105_rotate100_prompt.txt | code_completion |
Build a 100-bit left/right rotator, with synchronous load and left/right
enable. A rotator shifts-in the shifted-out bit from the other end of the
register, unlike a shifter that discards the shifted-out bit and shifts
in a zero. If enabled, a rotator rotates the bits around and does not
modify/discard them.
(1) lo... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob105_rotate100_prompt.txt",
"file_size": 772
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_434 | Prob150_review2015_fsmonehot_prompt.txt | code_completion |
Given the following Moore state machine with 3 input (d, done_counting,
ack) and 3 outputs (shift_ena, counting, done). Unless otherwise stated in
the diagram below, assume outputs are 0 and inputs are don't cares.
state (output) --input--> next state
-------------------------------------------
S () ... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob150_review2015_fsmonehot_prompt.txt",
"file_size": 2138
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_435 | Prob154_fsm_ps2data_prompt.txt | code_completion |
We want a finite state machine that will search for message boundaries
when given an input byte stream. The algorithm we'll use is to discard
bytes until we see one with in[3]=1. We then assume that this is byte 1
of a message, and signal the receipt of a message once all 3 bytes have
been received (done). The FSM sho... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob154_fsm_ps2data_prompt.txt",
"file_size": 2236
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_436 | Prob055_conditional_ifc.txt | code_completion |
module TopModule (
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output reg [7:0] min
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob055_conditional_ifc.txt",
"file_size": 114
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_437 | Prob096_review2015_fsmseq_prompt.txt | code_completion |
Build a finite-state machine that searches for the sequence 1101 in an
input bit stream. When the sequence is found, it should set
start_shifting to 1, forever, until reset. Reset is active high
synchronous.
module TopModule (
input clk,
input reset,
input data,
output start_shifting
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob096_review2015_fsmseq_prompt.txt",
"file_size": 299
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_438 | Prob132_always_if2_prompt.txt | code_completion |
Fix any and all bugs in this code:
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving );
always @(*) begin
if (cpu_overheated)
shut_off_computer = 1;
en... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob132_always_if2_prompt.txt",
"file_size": 586
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_439 | Prob038_count15_prompt.txt | code_completion |
Build a 4-bit binary counter that counts from 0 through 15, inclusive,
with a period of 16. The reset input is active high synchronous, and
should reset the counter to 0.
module TopModule (
input clk,
input reset,
output reg [3:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob038_count15_prompt.txt",
"file_size": 245
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_440 | Prob032_vector0_ifc.txt | code_completion |
module TopModule (
input [2:0] vec,
output [2:0] outv,
output o2,
output o1,
output o0
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob032_vector0_ifc.txt",
"file_size": 101
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_441 | Prob011_norgate_prompt.txt | code_completion |
Create a module that implements a NOR gate.
module TopModule (
input a,
input b,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob011_norgate_prompt.txt",
"file_size": 104
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_442 | Prob020_mt2015_eq2_prompt.txt | code_completion |
Create a circuit that has two 2-bit inputs A[1:0] and B[1:0], and
produces an output z. The value of z should be 1 if A = B, otherwise z
should be 0.
module TopModule (
input [1:0] A,
input [1:0] B,
output z
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob020_mt2015_eq2_prompt.txt",
"file_size": 220
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_443 | Prob059_wire4_prompt.txt | code_completion |
Create a module with 3 inputs and 4 outputs that behaves like wires that
makes these connections:
a -> w
b -> x
b -> y
c -> z
module TopModule (
input a,
input b,
input c,
output w,
output x,
output y,
output z
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob059_wire4_prompt.txt",
"file_size": 240
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_444 | Prob140_fsm_hdlc_ifc.txt | code_completion |
module TopModule (
input clk,
input reset,
input in,
output disc,
output flag,
output err
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob140_fsm_hdlc_ifc.txt",
"file_size": 106
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_445 | Prob134_2014_q3c_prompt.txt | code_completion |
Given the state-assigned table shown below, implement the logic functions
Y[0] and z.
Present state input y[2:0] | Next state Y[2:0] when x=0, Next state Y[2:0] when x=1 | Output z
000 | 000, 001 | 0
001 | 001, 100 | 0
010 | 010, 001 | 0
011 | 001, 010 | 1
100 | 011, 100 | 1
module TopModule (
in... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob134_2014_q3c_prompt.txt",
"file_size": 393
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_446 | Prob061_2014_q4a_prompt.txt | code_completion |
Consider an n-bit shift register circuit. Inputs E are for enabling
shift, R for value to load, L is asserted when it should load, and w is
the input to the first stage of the shift register. Write a Verilog
module named top_module for one stage of this circuit, including both the
flip-flop and multiplexers.
module T... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob061_2014_q4a_prompt.txt",
"file_size": 407
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_447 | Prob152_lemmings3_prompt.txt | code_completion |
The game Lemmings involves critters with fairly simple brains. So simple
that we are going to model it using a finite state machine. In the
Lemmings' 2D world, Lemmings can be in one of two states: walking left
(walk_left is 1) or walking right (walk_right is 1). It will switch
directions if it hits an obstacle. In pa... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob152_lemmings3_prompt.txt",
"file_size": 2175
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_448 | Prob086_lfsr5_ifc.txt | code_completion |
module TopModule (
input clk,
input reset,
output reg [4:0] q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob086_lfsr5_ifc.txt",
"file_size": 72
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_449 | Prob115_shift18_prompt.txt | code_completion |
Build a 64-bit arithmetic shift register, with synchronous load. The
shifter can shift both left and right, and by 1 or 8 bit positions,
selected by "amount." Assume the right shit is an arithmetic right shift.
Signals are defined as below:
(1) load: Loads shift register with data[63:0] instead of shifting.
... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob115_shift18_prompt.txt",
"file_size": 768
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_450 | Prob072_thermostat_prompt.txt | code_completion |
A heating/cooling thermostat controls both a heater (during winter) and
an air conditioner (during summer). Implement a circuit that will turn on
and off the heater, air conditioning, and blower fan as appropriate. The
thermostat can be in one of two modes: heating (mode = 1) and cooling
(mode = 0). In heating mode, t... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob072_thermostat_prompt.txt",
"file_size": 861
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_451 | Prob065_7420_ifc.txt | code_completion |
module TopModule (
input p1a,
input p1b,
input p1c,
input p1d,
output p1y,
input p2a,
input p2b,
input p2c,
input p2d,
output p2y
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob065_7420_ifc.txt",
"file_size": 154
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_452 | Prob061_2014_q4a_ifc.txt | code_completion |
module TopModule (
input clk,
input w,
input R,
input E,
input L,
output reg Q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob061_2014_q4a_ifc.txt",
"file_size": 95
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_453 | Prob110_fsm2_ifc.txt | code_completion |
module TopModule (
input clk,
input j,
input k,
input areset,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob110_fsm2_ifc.txt",
"file_size": 87
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_454 | Prob089_ece241_2014_q5a_prompt.txt | code_completion |
You are to design a one-input one-output serial 2's complementer Moore
state machine. The input (x) is a series of bits (one per clock cycle)
beginning with the least-significant bit of the number, and the output
(Z) is the 2's complement of the input. The machine will accept input
numbers of arbitrary length. The cir... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob089_ece241_2014_q5a_prompt.txt",
"file_size": 534
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_455 | Prob149_ece241_2013_q4_prompt.txt | code_completion |
A large reservior of water serves several users. In order to keep the
level of water succificently high, three sensors are placed vertically at
5-inch intervals. When the water level is above the highest sensor s[3],
the input flow rate should be zero. When the level is below the lowest
sensor s[1], the flow rate shou... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob149_ece241_2013_q4_prompt.txt",
"file_size": 1476
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_456 | Prob068_countbcd_prompt.txt | code_completion |
Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is
encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit,
etc. For digits [3:1], also output an enable signal indicating when each
of the upper three digits should be incremented. Include a synchronous
active-high reset.
module ... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob068_countbcd_prompt.txt",
"file_size": 406
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_457 | Prob136_m2014_q6_prompt.txt | code_completion |
Consider the state machine shown below:
A (0) --0--> B
A (0) --1--> A
B (0) --0--> C
B (0) --1--> D
C (0) --0--> E
C (0) --1--> D
D (0) --0--> F
D (0) --1--> A
E (1) --0--> E
E (1) --1--> D
F (1) --0--> C
F (1) --1--> D
Implement this state machine in Verilog.
module TopModule (
input clk,... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob136_m2014_q6_prompt.txt",
"file_size": 362
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_458 | Prob008_m2014_q4h_prompt.txt | code_completion |
The module assigns the output port to the same value as the input port
combinationally.
module TopModule (
input in,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob008_m2014_q4h_prompt.txt",
"file_size": 138
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_459 | Prob123_bugs_addsubz_prompt.txt | code_completion |
The following adder-subtractor with zero flag doesn't work. Fix the
bug(s).
synthesis verilog_input_version verilog_2001
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
);
always @(*) begin
case (do_su... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob123_bugs_addsubz_prompt.txt",
"file_size": 597
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_460 | Prob031_dff_ifc.txt | code_completion |
module TopModule (
input clk,
input d,
output reg q
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob031_dff_ifc.txt",
"file_size": 62
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_461 | Prob023_vector100r_ifc.txt | code_completion |
module TopModule (
input [99:0] in,
output reg [99:0] out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob023_vector100r_ifc.txt",
"file_size": 66
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_462 | Prob067_countslow_prompt.txt | code_completion |
Build a decade counter that counts from 0 through 9, inclusive, with a
period of 10. The reset input is active high synchronous, and should
reset the counter to 0. We want to be able to pause the counter rather
than always incrementing every clock cycle, so the "slowena" input if
high indicates when the counter should... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob067_countslow_prompt.txt",
"file_size": 422
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_463 | Prob127_lemmings1_ifc.txt | code_completion |
module TopModule (
input clk,
input areset,
input bump_left,
input bump_right,
output walk_left,
output walk_right
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob127_lemmings1_ifc.txt",
"file_size": 131
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_464 | Prob094_gatesv_prompt.txt | code_completion |
You are given a four-bit input vector in[3:0]. We want to know some
relationships between each bit and its neighbour:
(1) out_both: Each bit of this output vector should indicate whether
both the corresponding input bit and its neighbour to the left (higher
index) are '1'. For example, out_both[2] should indica... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob094_gatesv_prompt.txt",
"file_size": 1241
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_465 | Prob066_edgecapture_ifc.txt | code_completion |
module TopModule (
input clk,
input reset,
input [31:0] in,
output reg [31:0] out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob066_edgecapture_ifc.txt",
"file_size": 94
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_466 | Prob025_reduction_prompt.txt | code_completion |
Parity checking is often used as a simple method of detecting errors when
transmitting data through an imperfect channel. Create a circuit that
will compute a parity bit for a 8-bit byte (which will add a 9th bit to
the byte). We will use "even" parity, where the parity bit is just the
XOR of all 8 data bits.
module ... | {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob025_reduction_prompt.txt",
"file_size": 370
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_467 | Prob060_m2014_q4k_ifc.txt | code_completion |
module TopModule (
input clk,
input resetn,
input in,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob060_m2014_q4k_ifc.txt",
"file_size": 77
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_468 | Prob109_fsm1_ifc.txt | code_completion |
module TopModule (
input clk,
input in,
input areset,
output out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob109_fsm1_ifc.txt",
"file_size": 77
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_469 | Prob066_edgecapture_prompt.txt | code_completion |
For each bit in a 32-bit vector, capture when the input signal changes
from 1 in one clock cycle to 0 the next. "Capture" means that the output
will remain 1 until the register is reset (active high synchronous
reset).
module TopModule (
input clk,
input reset,
input [31:0] in,
output reg [31:0] out
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob066_edgecapture_prompt.txt",
"file_size": 315
} |
verilog_eval_v2 | dataset_code-complete-iccad2023 | veval_470 | Prob113_2012_q1g_ifc.txt | code_completion |
module TopModule (
input [4:1] x,
output logic f
);
| {
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob113_2012_q1g_ifc.txt",
"file_size": 57
} |
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