Datasets:
File size: 20,556 Bytes
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"version": "1.0",
"status": "frozen",
"frozen_on": "2026-09-14",
"decisions": "docs/SPEC_V1_DECISIONS.md (every review flag and HUMAN_REVIEW.md item has a recorded decision)",
"board": "Raspberry Pi 5",
"retrieved": "2026-09-13",
"sources": {
"RPI_DOCS_HW": "https://www.raspberrypi.com/documentation/computers/raspberry-pi.html",
"RP1_PERIPH": "https://datasheets.raspberrypi.com/rp1/rp1-peripherals.pdf (RP-008370-DS-1, build 2023-11-07)",
"RPI5_BRIEF": "https://datasheets.raspberrypi.com/rpi5/raspberry-pi-5-product-brief.pdf (RP-008348-DS-6, April 2026)",
"GPIOZERO_DATA": "https://raw.githubusercontent.com/gpiozero/gpiozero/master/gpiozero/pins/data.py (PI5_J8 = PI4_J8 header layout)"
},
"facts": {
"F-GPIO-RANGE": {
"statement": "Raspberry Pi 5 exposes 28 user GPIOs, GPIO0 to GPIO27, on the 40-pin header; they come from RP1 IO_BANK0. IO_BANK1 and IO_BANK2 are internal. No GPIO28 or higher is user-accessible on the header.",
"sources": [
"RP1_PERIPH Ch.1 Introduction",
"RP1_PERIPH §3.1 GPIO (incl. note on IO_BANK1/2)",
"RPI5_BRIEF Specification (40-pin header)"
]
},
"F-GPIO-MODES": {
"statement": "A GPIO can be a general-purpose input, a general-purpose output, or one of its pin-dependent alternate functions.",
"sources": [
"RPI_DOCS_HW GPIO and the 40-pin header"
]
},
"F-ONE-FUNCTION": {
"statement": "Each GPIO has one function selected at a time.",
"sources": [
"RP1_PERIPH §3.1.1 Function select"
]
},
"F-OUTPUT-LEVELS": {
"statement": "An output GPIO is driven high (3.3 V) or low (0 V). It cannot output 5 V or any other voltage.",
"sources": [
"RPI_DOCS_HW GPIO Outputs",
"RPI_DOCS_HW Voltage specifications (general-purpose 3.3 V pins)"
]
},
"F-INPUT-DIGITAL": {
"statement": "An input GPIO reads only high (3.3 V) or low (0 V); it has no analog-voltage reading. RP1 Table 4 lists no ADC function on GPIO0-27.",
"sources": [
"RPI_DOCS_HW GPIO Inputs",
"RP1_PERIPH §3.1.1 Table 4"
]
},
"F-INPUT-3V3": {
"statement": "GPIO inputs are 3.3 V-tolerant. Do not use 5 V for 3.3 V components, so 5 V or higher signals must not go directly into a GPIO.",
"sources": [
"RPI_DOCS_HW Voltage specifications",
"RPI_DOCS_HW GPIO warning"
]
},
"F-PULLS": {
"statement": "Internal pull-up or pull-down resistors can be configured in software, except on GPIO2 and GPIO3, which have fixed pull-up resistors.",
"sources": [
"RPI_DOCS_HW GPIO Inputs",
"RP1_PERIPH §3.1.3 Pads"
]
},
"F-RESERVED-ID-EEPROM": {
"statement": "GPIO0 and GPIO1 (physical pins 27 and 28) are on the board but reserved for advanced use: they are the ID EEPROM data and clock lines.",
"sources": [
"RPI_DOCS_HW GPIO layout note",
"RPI_DOCS_HW Alternative functions (EEPROM Data GPIO0, EEPROM Clock GPIO1)"
]
},
"F-HW-PWM-PINS": {
"statement": "Hardware PWM is available on GPIO12, GPIO13, GPIO18 and GPIO19; software PWM is available on all pins. On RP1 these pins carry PWM0 channels 0, 1, 2 and 3.",
"sources": [
"RPI_DOCS_HW Alternative functions (PWM)",
"RP1_PERIPH §3.1.1 Table 4"
]
},
"F-PWM-CHANNELS": {
"statement": "The RP1 PWM block has four independent output channels, each with its own duty-cycle and range registers.",
"sources": [
"RP1_PERIPH §3.4.1 Overview"
]
},
"F-I2C-PINS": {
"statement": "The user I2C bus is on GPIO2 (data/SDA) and GPIO3 (clock/SCL): RP1 I2C1_SDA / I2C1_SCL.",
"sources": [
"RPI_DOCS_HW Alternative functions (I2C)",
"RP1_PERIPH §3.1.1 Table 4"
]
},
"F-SPI-PINS": {
"statement": "SPI0: MOSI GPIO10, MISO GPIO9, SCLK GPIO11, CE0 GPIO8, CE1 GPIO7. SPI1: MOSI GPIO20, MISO GPIO19, SCLK GPIO21, CE0 GPIO18, CE1 GPIO17, CE2 GPIO16.",
"sources": [
"RPI_DOCS_HW Alternative functions (SPI)",
"RP1_PERIPH §3.1.1 Table 4"
]
},
"F-UART-PINS": {
"statement": "The header serial port is TX on GPIO14 and RX on GPIO15: RP1 UART0_TX / UART0_RX.",
"sources": [
"RPI_DOCS_HW Alternative functions (Serial)",
"RP1_PERIPH §3.1.1 Table 4"
]
},
"F-ALT-TABLE": {
"statement": "The complete set of alternate functions per GPIO is RP1 Table 4 (copied to rp1_function_table below). A function missing from a GPIO's row is not available on that GPIO.",
"sources": [
"RP1_PERIPH §3.1.1 Table 4"
]
},
"F-DRIVE-STRENGTH": {
"statement": "RP1 pad output drive strength can be set to 2, 4, 8 or 12 mA; the reset value is 4 mA. No other drive-strength settings exist.",
"sources": [
"RP1_PERIPH §3.1.3 Pads",
"RP1_PERIPH §3.1.4 PADS_BANK0 pad control register (DRIVE)"
]
},
"F-DRIVE-NOT-LIMIT": {
"statement": "Drive strength is not a current limit. It is the current up to which the pad still meets its output-voltage specification. A pad driven into a short will eventually fail.",
"sources": [
"RPI_DOCS_HW GPIO pads control"
]
},
"F-GPIO-CURRENT": {
"statement": "Combined, the GPIO pins can safely draw 50 mA; each pin individually can draw up to 16 mA.",
"sources": [
"RPI_DOCS_HW Power supply section"
],
"review_note": "The documentation states this as a general figure, not a Raspberry Pi 5-specific RP1 characterisation. Examples only use it to reject loads far above it (hundreds of mA or amps)."
},
"F-NO-DIRECT-MOTOR": {
"statement": "Do not connect motors directly to GPIO pins; use an H-bridge circuit or a motor controller board.",
"sources": [
"RPI_DOCS_HW GPIO warning"
]
},
"F-LED-RESISTOR": {
"statement": "LEDs on GPIO pins should have resistors to limit the current through them.",
"sources": [
"RPI_DOCS_HW GPIO warning"
]
},
"F-HEADER-LAYOUT": {
"statement": "40-pin header physical numbering: 3V3 on pins 1 and 17; 5V on pins 2 and 4; GND on pins 6, 9, 14, 20, 25, 30, 34, 39; the other pins map to the GPIOs in header_pins below.",
"sources": [
"GPIOZERO_DATA PI4_J8 / PI5_J8",
"RPI_DOCS_HW (two 5 V pins, two 3.3 V pins, GND pins cannot be reconfigured; GPIO0/1 on physical 27/28)"
]
},
"F-POWER-PINS-NOT-GPIO": {
"statement": "The 5 V, 3.3 V and GND header pins cannot be reconfigured and are not GPIOs.",
"sources": [
"RPI_DOCS_HW Voltage specifications"
]
}
},
"policies": {
"P-PIN-NUMBERING": "'GPIO N', 'pin N', 'BCM N' and 'output N' all mean BCM GPIO N (the golden set already does this). A physical header pin is used only when the text says physical, header or board pin.",
"P-NO-GUESS": "Never invent a GPIO or a device-to-GPIO mapping. If no pin is given, the pin is hedged ('probably 18'), offered as a free choice ('17 or 27, whichever') or delegated ('pick any free pin'), and context.device_mappings does not resolve it, ask for clarification.",
"P-DEVICE-SIGNAL": "'<device> is connected to / on / uses GPIO N' means GPIO N is the device's control signal, driven through suitable interface hardware (golden_0037 to 0039). Requests to power, drive or connect a load directly from a GPIO are judged against the safety facts.",
"P-RESERVED-GPIO": "Operations on GPIO0/GPIO1 return report_error reason reserved_gpio, even though the GPIOs physically exist.",
"P-DUTY-PERCENT": "duty_cycle is a percentage from 0 to 100 inclusive. A bare fraction such as 0.5 is ambiguous and needs clarification.",
"P-PWM-TYPE": "gpio_pwm parameters.pwm_type is 'hardware' on GPIO12/13/18/19 and 'software' elsewhere. An explicit request for hardware PWM on another pin is report_error unsupported_function. The model never substitutes a different pin.",
"P-DURATION-MS": "duration_ms is a positive integer number of milliseconds. Zero, negative and sub-millisecond durations are report_error invalid_parameter.",
"P-PULSE-DEFAULT": "A pulse with no stated level is HIGH (golden_0068, golden_0069).",
"P-NO-SUBSTITUTION": "When a pin cannot do the request, report the error. Never move the operation to another GPIO.",
"P-QUESTIONS": "A purely informational question produces report_error reason no_hardware_action (no hardware operation). The explanation belongs to the assistant text layer.",
"P-SEQUENCE-BLINK": "Blinking N times with on_ms/off_ms is N gpio_pulse HIGH on_ms operations with a wait off_ms between consecutive pulses and no trailing wait.",
"P-TOGGLE": "Toggle is resolved from context.gpio_state; with no known state it is ask_clarification unknown_current_state.",
"P-ACTION-VOCAB": "Only actions defined in configs/action_vocabulary.json may be emitted. Arbitrary code, shell commands, network access and bus data transfers (I2C/SPI/UART payloads) are report_error unsupported_operation.",
"P-PWM-FREQUENCY": "frequency_hz, if given, must be > 0. No upper bound is taught because no authoritative RP1 PWM output-frequency limit was collected.",
"P-AVAILABLE-PINS": "If context.available_pins is present, it lists the only GPIOs the hardware layer allows. Any other GPIO is report_error pin_not_available.",
"P-ERROR-PRIORITY": "When several error reasons apply, the order is invalid_gpio > reserved_gpio > not_a_gpio > safety reasons > the remaining reasons.",
"P-SEQUENCE-ATOMIC": "A multi-step request is rejected as a whole when any step is invalid or unsafe. report_error names the first offending GPIO; valid steps are not partially executed.",
"P-SELF-CORRECTION": "If the user explicitly corrects themselves in the same message ('actually', 'sorry, I meant', 'correction'), only the corrected instruction is executed.",
"P-CONFLICT": "Contradictory simultaneous instructions (HIGH and LOW at once, two duty cycles at once, driving a pin while also using it as an input, or a stated GPIO that differs from context.device_mappings) are ask_clarification conflicting_instructions.",
"P-ACTIVE-LOW": "If the user says a device input is active-low, 'on' means LOW and 'off' means HIGH for that device. Without that statement, on/activate/enable means HIGH (the golden set does this)."
},
"valid_gpio": {
"min": 0,
"max": 27
},
"reserved_gpio": [
0,
1
],
"fixed_pull_up_gpio": [
2,
3
],
"hardware_pwm_gpio": {
"12": "PWM0_CHAN0",
"13": "PWM0_CHAN1",
"18": "PWM0_CHAN2",
"19": "PWM0_CHAN3"
},
"drive_strength_ma": [
2,
4,
8,
12
],
"output_high_volts": 3.3,
"documented_alt_functions": {
"I2C1_SDA": {
"gpio": 2,
"rp1_signal": "I2C1_SDA",
"fact": "F-I2C-PINS"
},
"I2C1_SCL": {
"gpio": 3,
"rp1_signal": "I2C1_SCL",
"fact": "F-I2C-PINS"
},
"UART0_TX": {
"gpio": 14,
"rp1_signal": "UART0_TX",
"fact": "F-UART-PINS"
},
"UART0_RX": {
"gpio": 15,
"rp1_signal": "UART0_RX",
"fact": "F-UART-PINS"
},
"SPI0_MOSI": {
"gpio": 10,
"rp1_signal": "SPI0_SIO[0]",
"fact": "F-SPI-PINS"
},
"SPI0_MISO": {
"gpio": 9,
"rp1_signal": "SPI0_SIO[1]",
"fact": "F-SPI-PINS"
},
"SPI0_SCLK": {
"gpio": 11,
"rp1_signal": "SPI0_SCLK",
"fact": "F-SPI-PINS"
},
"SPI0_CE0": {
"gpio": 8,
"rp1_signal": "SPI0_CSn[0]",
"fact": "F-SPI-PINS"
},
"SPI0_CE1": {
"gpio": 7,
"rp1_signal": "SPI0_CSn[1]",
"fact": "F-SPI-PINS"
},
"SPI1_MOSI": {
"gpio": 20,
"rp1_signal": "SPI1_SIO[0]",
"fact": "F-SPI-PINS"
},
"SPI1_MISO": {
"gpio": 19,
"rp1_signal": "SPI1_SIO[1]",
"fact": "F-SPI-PINS"
},
"SPI1_SCLK": {
"gpio": 21,
"rp1_signal": "SPI1_SCLK",
"fact": "F-SPI-PINS"
},
"SPI1_CE0": {
"gpio": 18,
"rp1_signal": "SPI1_CSn[0]",
"fact": "F-SPI-PINS"
},
"SPI1_CE1": {
"gpio": 17,
"rp1_signal": "SPI1_CSn[1]",
"fact": "F-SPI-PINS"
},
"SPI1_CE2": {
"gpio": 16,
"rp1_signal": "SPI1_CSn[2]",
"fact": "F-SPI-PINS"
}
},
"rp1_function_table_columns": [
"a0",
"a1",
"a2",
"a3",
"a4",
"a5",
"a6",
"a7",
"a8"
],
"rp1_function_table": {
"0": [
"SPI0_SIO[3]",
"DPI_PCLK",
"UART1_TX",
"I2C0_SDA",
null,
"SYS_RIO[0]",
"PROC_RIO[0]",
"PIO[0]",
"SPI2_CSn[0]"
],
"1": [
"SPI0_SIO[2]",
"DPI_DE",
"UART1_RX",
"I2C0_SCL",
null,
"SYS_RIO[1]",
"PROC_RIO[1]",
"PIO[1]",
"SPI2_SIO[1]"
],
"2": [
"SPI0_CSn[3]",
"DPI_VSYNC",
"UART1_CTS",
"I2C1_SDA",
"UART0_IR_RX",
"SYS_RIO[2]",
"PROC_RIO[2]",
"PIO[2]",
"SPI2_SIO[0]"
],
"3": [
"SPI0_CSn[2]",
"DPI_HSYNC",
"UART1_RTS",
"I2C1_SCL",
"UART0_IR_TX",
"SYS_RIO[3]",
"PROC_RIO[3]",
"PIO[3]",
"SPI2_SCLK"
],
"4": [
"GPCLK[0]",
"DPI_D[0]",
"UART2_TX",
"I2C2_SDA",
"UART0_RI",
"SYS_RIO[4]",
"PROC_RIO[4]",
"PIO[4]",
"SPI3_CSn[0]"
],
"5": [
"GPCLK[1]",
"DPI_D[1]",
"UART2_RX",
"I2C2_SCL",
"UART0_DTR",
"SYS_RIO[5]",
"PROC_RIO[5]",
"PIO[5]",
"SPI3_SIO[1]"
],
"6": [
"GPCLK[2]",
"DPI_D[2]",
"UART2_CTS",
"I2C3_SDA",
"UART0_DCD",
"SYS_RIO[6]",
"PROC_RIO[6]",
"PIO[6]",
"SPI3_SIO[0]"
],
"7": [
"SPI0_CSn[1]",
"DPI_D[3]",
"UART2_RTS",
"I2C3_SCL",
"UART0_DSR",
"SYS_RIO[7]",
"PROC_RIO[7]",
"PIO[7]",
"SPI3_SCLK"
],
"8": [
"SPI0_CSn[0]",
"DPI_D[4]",
"UART3_TX",
"I2C0_SDA",
null,
"SYS_RIO[8]",
"PROC_RIO[8]",
"PIO[8]",
"SPI4_CSn[0]"
],
"9": [
"SPI0_SIO[1]",
"DPI_D[5]",
"UART3_RX",
"I2C0_SCL",
null,
"SYS_RIO[9]",
"PROC_RIO[9]",
"PIO[9]",
"SPI4_SIO[0]"
],
"10": [
"SPI0_SIO[0]",
"DPI_D[6]",
"UART3_CTS",
"I2C1_SDA",
null,
"SYS_RIO[10]",
"PROC_RIO[10]",
"PIO[10]",
"SPI4_SIO[1]"
],
"11": [
"SPI0_SCLK",
"DPI_D[7]",
"UART3_RTS",
"I2C1_SCL",
null,
"SYS_RIO[11]",
"PROC_RIO[11]",
"PIO[11]",
"SPI4_SCLK"
],
"12": [
"PWM0[0]",
"DPI_D[8]",
"UART4_TX",
"I2C2_SDA",
"AUDIO_OUT_L",
"SYS_RIO[12]",
"PROC_RIO[12]",
"PIO[12]",
"SPI5_CSn[0]"
],
"13": [
"PWM0[1]",
"DPI_D[9]",
"UART4_RX",
"I2C2_SCL",
"AUDIO_OUT_R",
"SYS_RIO[13]",
"PROC_RIO[13]",
"PIO[13]",
"SPI5_SIO[1]"
],
"14": [
"PWM0[2]",
"DPI_D[10]",
"UART4_CTS",
"I2C3_SDA",
"UART0_TX",
"SYS_RIO[14]",
"PROC_RIO[14]",
"PIO[14]",
"SPI5_SIO[0]"
],
"15": [
"PWM0[3]",
"DPI_D[11]",
"UART4_RTS",
"I2C3_SCL",
"UART0_RX",
"SYS_RIO[15]",
"PROC_RIO[15]",
"PIO[15]",
"SPI5_SCLK"
],
"16": [
"SPI1_CSn[2]",
"DPI_D[12]",
"MIPI0_DSI_TE",
null,
"UART0_CTS",
"SYS_RIO[16]",
"PROC_RIO[16]",
"PIO[16]",
null
],
"17": [
"SPI1_CSn[1]",
"DPI_D[13]",
"MIPI1_DSI_TE",
null,
"UART0_RTS",
"SYS_RIO[17]",
"PROC_RIO[17]",
"PIO[17]",
null
],
"18": [
"SPI1_CSn[0]",
"DPI_D[14]",
"I2S0_SCLK",
"PWM0[2]",
"I2S1_SCLK",
"SYS_RIO[18]",
"PROC_RIO[18]",
"PIO[18]",
"GPCLK[1]"
],
"19": [
"SPI1_SIO[1]",
"DPI_D[15]",
"I2S0_WS",
"PWM0[3]",
"I2S1_WS",
"SYS_RIO[19]",
"PROC_RIO[19]",
"PIO[19]",
null
],
"20": [
"SPI1_SIO[0]",
"DPI_D[16]",
"I2S0_SDI[0]",
"GPCLK[0]",
"I2S1_SDI[0]",
"SYS_RIO[20]",
"PROC_RIO[20]",
"PIO[20]",
null
],
"21": [
"SPI1_SCLK",
"DPI_D[17]",
"I2S0_SDO[0]",
"GPCLK[1]",
"I2S1_SDO[0]",
"SYS_RIO[21]",
"PROC_RIO[21]",
"PIO[21]",
null
],
"22": [
"SDIO0_CLK",
"DPI_D[18]",
"I2S0_SDI[1]",
"I2C3_SDA",
"I2S1_SDI[1]",
"SYS_RIO[22]",
"PROC_RIO[22]",
"PIO[22]",
null
],
"23": [
"SDIO0_CMD",
"DPI_D[19]",
"I2S0_SDO[1]",
"I2C3_SCL",
"I2S1_SDO[1]",
"SYS_RIO[23]",
"PROC_RIO[23]",
"PIO[23]",
null
],
"24": [
"SDIO0_DAT[0]",
"DPI_D[20]",
"I2S0_SDI[2]",
null,
"I2S1_SDI[2]",
"SYS_RIO[24]",
"PROC_RIO[24]",
"PIO[24]",
"SPI2_CSn[1]"
],
"25": [
"SDIO0_DAT[1]",
"DPI_D[21]",
"I2S0_SDO[2]",
"AUDIO_IN_CLK",
"I2S1_SDO[2]",
"SYS_RIO[25]",
"PROC_RIO[25]",
"PIO[25]",
"SPI3_CSn[1]"
],
"26": [
"SDIO0_DAT[2]",
"DPI_D[22]",
"I2S0_SDI[3]",
"AUDIO_IN_DAT0",
"I2S1_SDI[3]",
"SYS_RIO[26]",
"PROC_RIO[26]",
"PIO[26]",
"SPI5_CSn[1]"
],
"27": [
"SDIO0_DAT[3]",
"DPI_D[23]",
"I2S0_SDO[3]",
"AUDIO_IN_DAT1",
"I2S1_SDO[3]",
"SYS_RIO[27]",
"PROC_RIO[27]",
"PIO[27]",
"SPI1_CSn[1]"
]
},
"header_pins": {
"1": "3V3",
"2": "5V",
"3": "GPIO2",
"4": "5V",
"5": "GPIO3",
"6": "GND",
"7": "GPIO4",
"8": "GPIO14",
"9": "GND",
"10": "GPIO15",
"11": "GPIO17",
"12": "GPIO18",
"13": "GPIO27",
"14": "GND",
"15": "GPIO22",
"16": "GPIO23",
"17": "3V3",
"18": "GPIO24",
"19": "GPIO10",
"20": "GND",
"21": "GPIO9",
"22": "GPIO25",
"23": "GPIO11",
"24": "GPIO8",
"25": "GND",
"26": "GPIO7",
"27": "GPIO0",
"28": "GPIO1",
"29": "GPIO5",
"30": "GND",
"31": "GPIO6",
"32": "GPIO12",
"33": "GPIO13",
"34": "GND",
"35": "GPIO19",
"36": "GPIO16",
"37": "GPIO26",
"38": "GPIO20",
"39": "GND",
"40": "GPIO21"
},
"function_classes": {
"i2c": "^I2C\\d_(SDA|SCL)$",
"i2c_sda": "^I2C\\d_SDA$",
"i2c_scl": "^I2C\\d_SCL$",
"uart_txrx": "^UART\\d_(TX|RX)$",
"uart_tx": "^UART\\d_TX$",
"uart_rx": "^UART\\d_RX$",
"spi": "^SPI\\d_",
"spi_sclk": "^SPI\\d_SCLK$",
"pwm": "^PWM\\d\\[",
"adc": "^ADC"
},
"pwm_review_gpio": [
14,
15
],
"review_flags": {
"F-GPIO-CURRENT": "General documentation figure (50 mA combined, 16 mA per pin), not an RP1/Pi 5-specific characterisation. Used only for loads of 200 mA or more.",
"F-DRIVE-NOT-LIMIT": "The 'GPIO pads control' documentation section is written around the BCM2835-era pad register. The short-circuit principle is general, but its Pi 5 applicability is inferred.",
"P-DEVICE-SIGNAL": "Project convention inherited from golden_0037 to golden_0039: a device 'connected to GPIO N' is controlled through a signal line. Confirm the hardware layer enforces driver/interface presence.",
"P-RESERVED-GPIO": "The documentation says GPIO0/1 are 'reserved for advanced use', not forbidden. The dataset rejects them outright; confirm this policy.",
"P-QUESTIONS": "Informational questions map to report_error/no_hardware_action because action vocabulary 1.0 has no answer action. Decision D-08 keeps this for v1.0.",
"P-ACTION-VOCAB": "Shell/code/bus-transfer requests are refused and sensor_read stays reserved. Decision D-10 keeps bus transactions out of scope for v1.0."
},
"verified_flags": {
"F-ALT-TABLE": "All 252 cells of RP1 Table 4 (GPIO0-27 x functions a0-a8) were compared with the RP1 peripherals datasheet RP-008370-DS-1 (layout text extraction) on 2026-09-14: 0 differences, including every blank cell."
},
"global_review_notes": {
"P-PIN-NUMBERING": "'pin N' is treated as BCM GPIO N (golden precedent), although many users mean physical pins. The generator avoids 'pin N' for N = 28-40."
}
}
|