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| Loading weights: 0%| | 0/310 [00:00<?, ?it/s] |
| Loading weights: 100%|██████████| 310/310 [00:00<00:00, 5940.23it/s] |
| [e2_l1_tulu_r16_s18] step 50/5000 loss 1.0501 (40s) |
| [e2_l1_tulu_r16_s18] step 100/5000 loss 1.0289 (76s) |
| [e2_l1_tulu_r16_s18] step 150/5000 loss 1.0420 (110s) |
| [e2_l1_tulu_r16_s18] step 200/5000 loss 1.1205 (145s) |
| [e2_l1_tulu_r16_s18] step 250/5000 loss 0.9948 (180s) |
| [e2_l1_tulu_r16_s18] step 300/5000 loss 1.0022 (215s) |
| [e2_l1_tulu_r16_s18] step 350/5000 loss 1.0425 (250s) |
| [e2_l1_tulu_r16_s18] step 400/5000 loss 0.9580 (285s) |
| [e2_l1_tulu_r16_s18] step 450/5000 loss 0.9727 (319s) |
| [e2_l1_tulu_r16_s18] step 500/5000 loss 1.0200 (355s) |
| [e2_l1_tulu_r16_s18] step 550/5000 loss 0.9228 (389s) |
| [e2_l1_tulu_r16_s18] step 600/5000 loss 0.9754 (425s) |
| [e2_l1_tulu_r16_s18] step 650/5000 loss 1.0223 (459s) |
| [e2_l1_tulu_r16_s18] step 700/5000 loss 1.0071 (494s) |
| [e2_l1_tulu_r16_s18] step 750/5000 loss 0.9754 (529s) |
| [e2_l1_tulu_r16_s18] step 800/5000 loss 0.8946 (564s) |
| [e2_l1_tulu_r16_s18] step 850/5000 loss 0.9852 (598s) |
| [e2_l1_tulu_r16_s18] step 900/5000 loss 0.9844 (634s) |
| [e2_l1_tulu_r16_s18] step 950/5000 loss 0.8784 (668s) |
| [e2_l1_tulu_r16_s18] step 1000/5000 loss 0.9400 (704s) |
| [e2_l1_tulu_r16_s18] step 1050/5000 loss 0.9024 (738s) |
| [e2_l1_tulu_r16_s18] step 1100/5000 loss 0.9607 (774s) |
| [e2_l1_tulu_r16_s18] step 1150/5000 loss 1.0802 (808s) |
| [e2_l1_tulu_r16_s18] step 1200/5000 loss 0.9640 (844s) |
| [e2_l1_tulu_r16_s18] step 1250/5000 loss 1.0832 (878s) |
| [e2_l1_tulu_r16_s18] step 1300/5000 loss 0.9690 (913s) |
| [e2_l1_tulu_r16_s18] step 1350/5000 loss 0.9051 (948s) |
| [e2_l1_tulu_r16_s18] step 1400/5000 loss 1.0841 (983s) |
| [e2_l1_tulu_r16_s18] step 1450/5000 loss 1.0020 (1017s) |
| [e2_l1_tulu_r16_s18] step 1500/5000 loss 0.9594 (1053s) |
| [e2_l1_tulu_r16_s18] step 1550/5000 loss 1.0853 (1087s) |
| [e2_l1_tulu_r16_s18] step 1600/5000 loss 1.0010 (1123s) |
| [e2_l1_tulu_r16_s18] step 1650/5000 loss 0.9333 (1157s) |
| [e2_l1_tulu_r16_s18] step 1700/5000 loss 0.9730 (1192s) |
| [e2_l1_tulu_r16_s18] step 1750/5000 loss 0.9431 (1226s) |
| [e2_l1_tulu_r16_s18] step 1800/5000 loss 0.8889 (1262s) |
| [e2_l1_tulu_r16_s18] step 1850/5000 loss 0.9933 (1296s) |
| [e2_l1_tulu_r16_s18] step 1900/5000 loss 0.9249 (1332s) |
| [e2_l1_tulu_r16_s18] step 1950/5000 loss 0.9687 (1366s) |
| [e2_l1_tulu_r16_s18] step 2000/5000 loss 1.0066 (1402s) |
| [e2_l1_tulu_r16_s18] step 2050/5000 loss 0.9809 (1436s) |
| [e2_l1_tulu_r16_s18] step 2100/5000 loss 0.9041 (1472s) |
| [e2_l1_tulu_r16_s18] step 2150/5000 loss 0.8932 (1506s) |
| [e2_l1_tulu_r16_s18] step 2200/5000 loss 1.0108 (1542s) |
| [e2_l1_tulu_r16_s18] step 2250/5000 loss 1.0660 (1576s) |
| [e2_l1_tulu_r16_s18] step 2300/5000 loss 1.0613 (1612s) |
| [e2_l1_tulu_r16_s18] step 2350/5000 loss 1.0258 (1646s) |
| [e2_l1_tulu_r16_s18] step 2400/5000 loss 0.9109 (1681s) |
| [e2_l1_tulu_r16_s18] step 2450/5000 loss 1.0285 (1716s) |
| [e2_l1_tulu_r16_s18] step 2500/5000 loss 0.9564 (1751s) |
| [e2_l1_tulu_r16_s18] step 2550/5000 loss 0.8992 (1785s) |
| [e2_l1_tulu_r16_s18] step 2600/5000 loss 0.9870 (1821s) |
| [e2_l1_tulu_r16_s18] step 2650/5000 loss 0.9620 (1855s) |
| [e2_l1_tulu_r16_s18] step 2700/5000 loss 0.9531 (1891s) |
| [e2_l1_tulu_r16_s18] step 2750/5000 loss 1.0031 (1925s) |
| [e2_l1_tulu_r16_s18] step 2800/5000 loss 1.0479 (1960s) |
| [e2_l1_tulu_r16_s18] step 2850/5000 loss 1.0537 (1995s) |
| [e2_l1_tulu_r16_s18] step 2900/5000 loss 0.9278 (2030s) |
| [e2_l1_tulu_r16_s18] step 2950/5000 loss 0.9956 (2065s) |
| [e2_l1_tulu_r16_s18] step 3000/5000 loss 0.9019 (2100s) |
| [e2_l1_tulu_r16_s18] step 3050/5000 loss 0.9179 (2135s) |
| [e2_l1_tulu_r16_s18] step 3100/5000 loss 0.9233 (2170s) |
| [e2_l1_tulu_r16_s18] step 3150/5000 loss 0.9674 (2204s) |
| [e2_l1_tulu_r16_s18] step 3200/5000 loss 0.9901 (2240s) |
| [e2_l1_tulu_r16_s18] step 3250/5000 loss 0.8812 (2274s) |
| [e2_l1_tulu_r16_s18] step 3300/5000 loss 0.9200 (2310s) |
| [e2_l1_tulu_r16_s18] step 3350/5000 loss 0.9594 (2344s) |
| [e2_l1_tulu_r16_s18] step 3400/5000 loss 1.0258 (2380s) |
| [e2_l1_tulu_r16_s18] step 3450/5000 loss 0.9718 (2414s) |
| [e2_l1_tulu_r16_s18] step 3500/5000 loss 0.9499 (2450s) |
| [e2_l1_tulu_r16_s18] step 3550/5000 loss 1.0424 (2484s) |
| [e2_l1_tulu_r16_s18] step 3600/5000 loss 1.0418 (2520s) |
| [e2_l1_tulu_r16_s18] step 3650/5000 loss 0.9962 (2554s) |
| [e2_l1_tulu_r16_s18] step 3700/5000 loss 0.9409 (2590s) |
| [e2_l1_tulu_r16_s18] step 3750/5000 loss 0.9634 (2624s) |
| [e2_l1_tulu_r16_s18] step 3800/5000 loss 1.0045 (2659s) |
| [e2_l1_tulu_r16_s18] step 3850/5000 loss 0.9141 (2694s) |
| [e2_l1_tulu_r16_s18] step 3900/5000 loss 0.9767 (2729s) |
| [e2_l1_tulu_r16_s18] step 3950/5000 loss 0.9655 (2763s) |
| [e2_l1_tulu_r16_s18] step 4000/5000 loss 0.9799 (2799s) |
| [e2_l1_tulu_r16_s18] step 4050/5000 loss 1.0493 (2833s) |
| [e2_l1_tulu_r16_s18] step 4100/5000 loss 0.9135 (2869s) |
| [e2_l1_tulu_r16_s18] step 4150/5000 loss 0.9350 (2903s) |
| [e2_l1_tulu_r16_s18] step 4200/5000 loss 0.8662 (2939s) |
| [e2_l1_tulu_r16_s18] step 4250/5000 loss 0.9192 (2973s) |
| [e2_l1_tulu_r16_s18] step 4300/5000 loss 0.8805 (3008s) |
| [e2_l1_tulu_r16_s18] step 4350/5000 loss 1.0368 (3043s) |
| [e2_l1_tulu_r16_s18] step 4400/5000 loss 0.9694 (3078s) |
| [e2_l1_tulu_r16_s18] step 4450/5000 loss 0.9542 (3112s) |
| [e2_l1_tulu_r16_s18] step 4500/5000 loss 1.0562 (3148s) |
| [e2_l1_tulu_r16_s18] step 4550/5000 loss 0.9045 (3182s) |
| [e2_l1_tulu_r16_s18] step 4600/5000 loss 0.9823 (3218s) |
| [e2_l1_tulu_r16_s18] step 4650/5000 loss 0.9715 (3252s) |
| [e2_l1_tulu_r16_s18] step 4700/5000 loss 0.8694 (3287s) |
| [e2_l1_tulu_r16_s18] step 4750/5000 loss 0.8949 (3322s) |
| [e2_l1_tulu_r16_s18] step 4800/5000 loss 0.9236 (3357s) |
| [e2_l1_tulu_r16_s18] step 4850/5000 loss 0.9922 (3391s) |
| [e2_l1_tulu_r16_s18] step 4900/5000 loss 0.9311 (3427s) |
| [e2_l1_tulu_r16_s18] step 4950/5000 loss 0.9530 (3461s) |
| [e2_l1_tulu_r16_s18] step 5000/5000 loss 0.9014 (3496s) |
| [e2_l1_tulu_r16_s18] DONE in 3497s -> runs/e2_l1_tulu_r16_s18 |
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