author: Matt R.

subject: Re: Hyperthreading thread priorities

text:
"Yousuf Khan" <[email]> wrote in message news:<cu_Tc.403418$[email]>...

http://developer.intel.com/technology/itj/2002/volume06issue01/art01_hyper/p06_execution_engine.htm

QUOTE:
If there are uops for both logical processors in the uop queue, the
allocator will alternate selecting uops from the logical processors
every clock cycle to assign resources [...]

The schedulers choose uops regardless of whether they belong to one
logical processor or the other. [...]

The memory instruction queue and general instruction queues send uops
to the five scheduler queues as fast as they can, alternating between
uops for the two logical processors every clock cycle, as needed.
[...]

Retirement logic will retire uops for one logical processor, then the
other, alternating back and forth.[...]

Once stores have retired, the store data needs to be written into the
level-one data cache. Selection logic alternates between the two
logical processors to commit store data to the cache.
(End of quote)

This looks to me as if both threads always have the same priority
within the P4. That would explain some issues where two threads with
different OS priorities (realtime and idle) recieved an equal amount
of CPU time. This situations occured to me several times with the
WinXP scheduler when there were only two threads needing the CPU and
no other with which the scheduler could rotate. When there are two
threads ready to run then those two are executed by WinXP, no matter
which priority they have. Unless there is a third or fourth one with
which the scheduler can alternate both threads recieve an equal amount
of CPU time. This looks to me as if there is no priority within the
cpu itself.

btw: AFAIK, Power5 does its priority switching for threads by decoding
different amounts of instructions for the two threads.

Regards,

Matt


author: Peter Boyle

subject: Re: Hyperthreading thread priorities

text:
On Thu, 26 Aug 2004, Nick Maclaren wrote:

Bad example.

That is just a plain incorrect threaded code. The only temporal
relationship between threads is that that the programmer imposes.

So if thread A requires another thread, B, to check the counter
for overflow between updates, it should use a condition variable
+ mutext pair ping pong to arrange so.

In a user space pthreads implentation (i.e. one kernel thread)
this sort of thing can happen very easily because it may well
only cswitch during the pthreads calls.

I've written a fairly large SMP programme O(50) threads,
50k lines, massive amounts of multi-threaded I/O (4 GigE links saturated).
It works fine and portably across Solaris, AIX and Unix.

Best,

Peter

Peter Boyle	[email]


subject: Re: Hyperthreading thread priorities

text:
On Thu, 26 Aug 2004, Nick Maclaren wrote:

Arghh... sorry Nick I'm replying to your post twice...

Where I think there is a real problem is things like hard realtime.

Where there is no synchronisation, and shouldn't be, between two
independent threads, one of high prio and one of low prio.

If the high prio thread can be prevented from making a guaranteed
deadline by a low prio one that is clearly bad. Just think of
the accounting done for minimum interrupt latency calculations
being thrown out of the window by a spinning thread consuming resources.

(I'm assuming something - if a HT CPU handles an interrupt, are
both threads interrupted, or just one. I assume one since there
is one architected register set saved and restored by ISR's.)

If I was an RTOS guy I would avoid HT like the plague.

Peter

Peter Boyle	[email]


author: Joe Seigh

subject: Re: Hyperthreading thread priorities

text:
Yousuf Khan wrote:
I was under the impression it was done with out of order execution and
the normal mechanism for prioritizing out of order instructions was used
with tagging or some other mechanism to keep track of what belonged to
what thread.

Joe Seigh


author: Yousuf Khan

subject: Re: Hyperthreading thread priorities

text:
Matt R. <[email]> wrote:
http://developer.intel.com/technology/itj/2002/volume06issue01/art01_hyper/p06_execution_engine.htm

Thanks, you were able to dig down through Intel's website better than me.

This sounds reasonable, and my original understanding was that each logical
processor is more or less equal priority, but I had read somewhere there was
an internal priority for one logical processor over the other.

    Yousuf Khan


author: Ken Hagan

subject: Re: Hyperthreading thread priorities

text:
Matt R. wrote:
amount

Presumably exactly the same thing would happen on a dual processor
system and it must be a truly ancient topic of conversation amongst
people who design OS schedulers.

At some level, it is clearly less than perfect, but is it a problem
in practice? Is it worth the time and effort to fix? (I imagine it is
somewhat easier to fix for a single hyperthreaded processor than for
a true dual processor.)

decoding

Ah. Presumably at least one person thought "yes" and "yes". Is anyone
here able to report how much effort it was?


author: Stefan Monnier

subject: Re: Hyperthreading thread priorities

text:
Yes, I think it's a problem because, as opposed to the SMP case, in the
multithreaded-CPU case, threads use each other's resources (well, it's also
true for SMP, but to a lesser extent).  So if you stop the lower-priority
thread, the higher-priority will (well: may) run faster.

        Stefan


subject: Re: Hyperthreading thread priorities

text:
Stefan Monnier wrote:

I've proposed that you exploit this feature by running cooperating threads
and allowing that to keep the threads in sync with each other without
having to have the scheduler intervene.  Unfortunately, you can't depend
of this being around, so it's not worth expending any effort to write code
to exploit it.   But it does allow you to write good advertising copy.

Joe Seigh


author: Nick Maclaren

subject: Re: Hyperthreading thread priorities

text:
In article <[email]>,
Peter Boyle  <[email]> wrote:

And I am merging them back again :-)

I agree with that, and quite a lot of HPC comes close to that, as
does a fair amount of other work.

That is too simplistic.  There is absolutely nothing unreasonable
about designing an application that relies on thread A executing
at least as fast as thread B, provided that it is documented and
checked.  The fault of most systems is that they don't provide the
facilities to do that cleanly.

Precisely.

You assume too much, sirrah!  If that were so, how do you think
that the CPU could handle machine checks and other "Oh, My God"
interrupts?  I can't tell you whether only THOSE interrupts stop
both CPUs, whether ALL do, or whether the FLIH starts off by
deciding whether to stop the whole CPU, but one of those must be
the case.

After all, you can switch from HT mode to single CPU mode in an
interrupt handler (because that is how system calls are implemented).

Right.

No, that is plain dogmatism.  There are MANY reasons to want to
avoid mutexes and other such locking mechanisms.  As with real-time
systems, it is perfectly reasonable for parallel aplications to
insist that each thread can run in parallel, document that and check
it.  A very large number of HPC applications are like that, though
they typically rely on the parallel environment to do the checking.

Remember that a mutex can be a hundred or more times slower than a
simple data location update, and forcing an efficiency loss of that
magnitude into a performance-critical section is unreasonable.
The logic that I described is perfectly correct, and has a negligible
failure probability if its assumptions are valid.

The problem with Hyperthreading is that it potentially breaks those
assumptions, under circumstances that the documentation implies it
will not.  Therefore the problem is not with the code but with the
architecture.

Regards,
Nick Maclaren.


subject: Re: Hyperthreading thread priorities

text:
Joe Seigh <[email]> wrote:

Maybe registers aren't atomic within the processor level, but perhaps things
such as ALUs and FPUs?

    Yousuf Khan


subject: Re: Hyperthreading thread priorities

text:
"Ken Hagan" <[email]> wrote in message news:<cgkd0e$h69$1$[email]>...

OS priorities for thread are for the good of distinguishing the
distribution of computation power for different threads. High priority
should always provide as much computation power to the thread as
possible. If that's not guaranteed the scheduler is doing a bad job
imho.

In practise, I have heard some people complaining that on a system
with HTT enabled they could not run a game (say: high priority) and an
encoding task (idle priority) at the same time because the frame rates
for the game were dropping dramatically compared to the same system
with HTT disabled. The reason was simply that the encoding task
(although having low priority) stole too much CPU calculations from
the game thread.


subject: Re: Hyperthreading thread priorities

text:
In article <[email]>,
Stefan Monnier <[email]> writes:
|> > At some level, it is clearly less than perfect, but is it a problem
|> > in practice?
|>
|> Yes, I think it's a problem because, as opposed to the SMP case, in the
|> multithreaded-CPU case, threads use each other's resources (well, it's also
|> true for SMP, but to a lesser extent).  So if you stop the lower-priority
|> thread, the higher-priority will (well: may) run faster.

Scheduling issues can also cause some tightly-coupled programs to
fail, or run like complete drains, even when they are in some
sense 'correct'.

Consider thread A, which is updating a location (say a counter)
like crazy, but is specified to do work between updates.  Thread B
is the counter overflow handler, and checks and resets it using an
unlocked compare technique, with a retry if it gets updated in the
middle of its action.  If A gets too much more priority than B, it
is possible for B to fail to reset the counter, thus causing an
overflow.

There are a zillion variations on this sort of thing, which is one
of the reasons that tuning tightly-coupled SMP programs is so hard
and so system-dependent.

Regards,
Nick Maclaren.


author: Terje Mathisen

subject: Re: Hyperthreading thread priorities

text:
Nick Maclaren wrote:

This came up a few months ago, I suggested using this technique to
implement a shared 64-bit counter on a 32-bit platform.

The only requirement for correctness is that the separate overflow
update thread _must_ run before the low-end counter can wrap around twice.

The proper way would be to make the update thread realtime (highest
possible) priority, and then let it sleep for 10 to 25% of the minimum
possible wraparound time.

Right.


author: Bill Wang

subject: icons

text:
I have successfully changed the icons in program manager to different
ones than the MS shipped ones.  But somehow, I couldn't quite
figure out why they turned into the default <dos> icons when I used
<esc>-<alt> to switch to other processes.  There got to be a problem
somewhere.  Thanks in advance for any enlights on the matter.


author: Patrick Deupree

subject: Re: icons

text:
In article <[email]> [email] (Bill Wang) writes:

OK.  Here's the story.  When you're running a DOS application, you're
using an Icon built into the Windows binaries for a DOS application.
Any Icon you create for the Program manager only applies to the program
manager.  The program itself decides what the icon will be when that
application is minimized.

Now, in the case of Windows programs, you'll be able to change that
icon whenever Whitewater finally finishes the Resource Toolkit for
Windows 3.0.  As for Dos applications, you're stuck with the DOS icon
and there's really nothing that can be done about it.

Patrick


author: Risto Lankinen

subject: Re: icons

text:
[email] (Bill Wang) writes:

Hi!

Windows' Program Manager probably expects full path names for the icon
files you've written on the File..Properties..etc line.  What possibly
happens is that when ProgMan regains control, the program being used
meanwhile had changed directory and the icon files were no longer present
in the 'relative' path.  In that case, the 'first available' icon is
displayed, which is just the PROGMAN.EXE's own DOS screen icon.

Terveisin: Risto Lankinen


author: Ronald S. Woan

subject: Re: icons

text:
In article <[email]>, [email]
(Bill Wang) writes:
Bill> I have successfully changed the icons in program manager to different
Bill> ones than the MS shipped ones.  But somehow, I couldn't quite
Bill> figure out why they turned into the default <dos> icons when I used
Bill> <esc>-<alt> to switch to other processes.  There got to be a problem
Bill> somewhere.  Thanks in advance for any enlights on the matter.

Changing the icons in the program manager does nothing to the program
itself. Progarm manager maintains its own application/icon references,
so when you used switch or iconize, in general, with the application
running you will get the program's inherent icon (here defaulting to
the generic DOS) at the bottom of the screen.

					Ron

+-----All Views Expressed Are My Own And Are Not Necessarily Shared By------+
+------------------------------My Employer----------------------------------+
+ Ronald S. Woan       [email] or [email] +
+ other email addresses             Prodigy: XTCR74A Compuserve: 73530,2537 +


author: Russell Poffenberger

subject: Re: icons

text:
In article <[email]> [email] (Risto Lankinen) writes:

The icon shown for an application in a group under the program manager is under
control of the program manager. Selecting an icon under the properties section
tells progman to display that icon. Once the application is invoked, then
minimized, progman no longer has any control over it. For an application to
show an icon (other than the default DOS icon) when minimized, it must be a
windows application that has an icon built into its resource. Non-windows
applications cannot do this, and there is no way (to my knowledge) to tell
windows to use a different icon in this case.

Russ Poffenberger               DOMAIN: [email]
Schlumberger Technologies       UUCP:   {uunet,decwrl,amdahl}!sjsca4!poffen
1601 Technology Drive		CIS:	72401,276
San Jose, Ca. 95110             (408)437-5254


author: David Wright

subject: Re: icons

text:
In article <[email]> [email] (Russell Poffenberger) writes:
#
#..... ...  For an application to
#show an icon (other than the default DOS icon) when minimized, it must be a
#windows application that has an icon built into its resource. Non-windows
#applications cannot do this, and there is no way (to my knowledge) to tell
#windows to use a different icon in this case.

Wrong, fortunately.  For example, on my system Kermit now shows a very
non-standard icon when minimised.

Get hold of icon editor icon12, posted about a month ago (this group or
comp.binaries.ibm.pc, I forget) and now no doubt on Simtel etc..
Make your icon, select your application, select Properties, in that select
change icon.  Then put the full path name of your icon file in as the icon
file name.   That's all there is to it - even I could do it!
Now if I could just learn how to draw a *proper* frog .... :-)

Regards,          "None shall be enslaved by poverty, ignorance or conformity"
        David Wright             STL, London Road, Harlow, Essex  CM17 9NA, UK
[email]  <or> ...uunet!mcsun!ukc!stl!dww  <or> PSI%234237100122::DWW
<or> /g=David/s=Wright/org=STC Technology Ltd/prmd=STC plc/admd=Gold 400/co=GB


author: Russ Poffenberger

subject: Re: icons

text:
In article <[email]> [email] (David Wright) writes:

Unfortunately this does not work except to change the icon presented in the
program manager ONLY. Once the application is launched, then minimized, only
a true windows application will show anything other than the default DOS icon.

Russ Poffenberger               DOMAIN: [email]
Schlumberger Technologies       UUCP:   {uunet,decwrl,amdahl}!sjsca4!poffen
1601 Technology Drive		CIS:	72401,276
San Jose, Ca. 95110             (408)437-5254


author: RS

subject: new Asus notebook group on Yahoo

text:
Have just created "Asus Barebones Notebooks" at

http://ca.groups.yahoo.com/group/asus_bare_notebook

Anyone else interested in Asus barebones notebooks, please join and/or
contribute !

Thanks !

-RS-


subject: Re: new Asus notebook group on Yahoo

text:
Anybody know how to open up an Asus  L8400 (L84B)so that the HDD can be
changed? It's not a bare-bones model, so the manual of course does not show
how to do that.

Also, please drop by, visit, join the Asus Barebones Notebook Group at:

http://ca.groups.yahoo.com/group/asus_bare_notebook

-RS-

"RS" <[email]> wrote in message
news:0doac.29126$wg1.6456@edtnps84...


subject: Re: new Asus notebook group on Yahoo

text:
Just an update to say that I have uploaded some hardware photos to the group
and also a spreadsheet file to the "Files" section ...

Cheers,

-RS-

"RS" <[email]> wrote in message
news:0doac.29126$wg1.6456@edtnps84...


author: Mark T.B. Carroll

subject: Toshiba P105 power connector type?

text:
I'm looking for a auto/air power adaptor that will work with my Toshiba
Satellite P105-S6197. But, what type of power connector tip does it use?
One of the S<integer> ones? I can't work it out. Different types don't
look different enough to me, but I want to make sure I buy something
that fits physically as well as electronically, given the typical price
of these adaptors.

Mark.


author: Barry Watzman

subject: Re: Toshiba P105 power connector type?

text:
What is the voltage?

I had a Toshiba A105-S2712 for which no tip was officially listed, but I
found that it was a 19 volt supply and I did find a tip that worked, but
I had a VERY large selection of Targus adapter tips to play with.

Here's the voltage on many of the Targus power tips (save this post,
this information is about as hard to come by as plans for a nuclear bomb):

1	-	+16.00 volts
3	-	+18.00 volts
4	-	+12.00 volts
6	-	+15.00 volts
7	-	+16.50 volts
8	-	+ 8.40 volts
5	-	-12.00 volts (tip negative)
10	-	+ 2.95 volts
11	-	+ 6.00 volts
12	-	+10.00 volts
15	-	-10.60 volts (tip negative)
16	-	+ 5.50 volts
17	-	+ 8.50 volts
18	-	+ 9.40 volts
19	-	+16.60 volts
20	-	+13.00 volts
21	-	+19.00 volts
24	-	+19.55 volts
25	-	+18.25 volts
26	-	+19.50 volts
27	-	+15.00 volts
28	-	+22.00 volts
34	-	+ 7.00 volts
36	-	+18.26 volts
38	-	+24.00 volts
44	-	+18.90 volts
47	-	+13.00 volts
48	-	+18.20 volts
57	-	+ 4.10 volts
58	-	+20.00 volts

Keep in mind that at or close to 20 volts, even a 5% tolerance (which
you have, easily) is about a full volt.

Mark T.B. Carroll wrote:


subject: Re: Toshiba P105 power connector type?

text:
Barry Watzman <[email]> writes:

15V, I think, and 5A. (I forget the polarity off-hand.)
Maybe it's an S6 then!

(snip)
(snip)

Ooooh. I had no idea there was a relationship between tip and voltage.
At least Google Groups will now remember all this for us. (-:

Mark.


subject: Re: Toshiba P105 power connector type?

text:
Barry Watzman <[email]> writes:

(snip)

Great, thanks! I shall purchase accordingly. (-:

Mark.


subject: Re: Toshiba P105 power connector type?

text:
All Toshiba laptops using 15 volt power units use the same plug, and I
think for Targus it is the #6 tip.  I do a lot of laptop service work,
and for almost all purposes, you can use any 15 volt Toshiba adapter
with any Toshiba 15 volt laptop, although I try to stay "in range" in
terms of current (but lots of times I've used a 3 amp supply for a
laptop that nominally had a 5 amp requirement ... and never had a
problem) (but most of the time there is no battery in the laptops that I
am working on).  15V at 5A is 75 watts.  As a practical matter, you
might get buy with a 60 watt supply in a pinch, but if you are buying
one new, I'd look for a 75 or 90-watt supply.

Mark T.B. Carroll wrote:


author: Anthony Murdoch

subject: Why does windows lockup when things are loaded into EMS ??

text:
Hi netters,

I am sure that there is probably a simple answer to this problem, but I
have never seen it discussed anywhere.  Whenever I start windows 3 in
enhanced mode after loading something into EMS (in particular PCSA
drivers, but it has happened with other stuff) windows gets to the opening
screen, bombs out to DOS, and quite soon after, the machine locks up.

Windows will work in standard or real modes, it happens if I use qemm or
himem/emm386, it happens on a number of different machine from 386sx's to
a 25MHz i486, and it happens on both DOS 4.01 and DOS 5.  Any idea's.

BTW, we are still using PCSA v3 - we hope to move to Pathworks v4 at the
end of the year (yay :)  but I don't think this is really a PCSA problem.

ant

  V   ant                       "I killed Laura Palmer"
 \o/  [email]
 -O-  Anthony Murdoch           Prentice Centre
 /0\  Phone (07) 36 54078       University of Qld


author: Aengus Lawlor

subject: Re: Why does windows lockup when things are loaded into EMS ??

text:
In article <ant.684123963@brolga>, [email] (Anthony Murdoch)
says:
[stuff deleted]
I think it's a PCSA problem! And it has been fixed in Pathworks 4.0. I never
had problems with other applications using EMS, but I don't use many. And
I'm more than a little disappointed that PCSA/Pathworks still doesn't support
XMS as well as or even instead of EMS. (You don't want to run PCSA on an XT
so any reasonable PCSA node is technically capable of XMS). If you want an
example of how slow EMS memory really is, load LAT into EMS, and try scroll
pages of data. It feels like 9600 baud!

Aengus


author: [redacted]

text:
Pathworks v4.0 will indeed put an end to the Windows 3.0 hangups caused
by loading DEC's software into EMS. However, there is one component
that will still crash Windows if it is loaded into EMS. So, remove the
EMSLOAD part of its line. I can't recall for sure now, but I think
that dlldepca.exe is the one.
Steven R. Meyer - Stanford Linear Accelerator Center
SLACVX.SLAC.STANFORD.EDU


author: Chris Carlson

subject: 8100/110 + AppleShare 4.0.2 = DOES NOT WORK!!

text:
Folks,

AppleShare 4.0.2 will *NOT* work with the new PowerMac 8100/110!

I called Apple and they confirmed this.  The PowerMac 8100/110 requires at
least System 7.5.  Apple confirms that AppleShare 4.0.2 will not run on
System 7.5, and if it does run, then it'll run very flaky and they will
not support it.

It seems that Apple is very compartmentalized and one group may not know
what another group is doing.  The hardware group released the 8100/110
without checking with the AppleShare group to test if AppleShare 4.0.2 will
run on it.

Apple does not officially know if it will release a fix to AppleShare 4.0.2
to allow it to run on the 8100/110, and I've heard no word from other
sources.  My guess is that the native release of AppleShare,
so far scheduled for summer 1995, will run on the 8100/110.

Once again, do not purchase the 8100/110 to run AppleShare!!  It is
confirmed that AppleShare 3.X will not run on it either.  Be aware before you
make your purchasing decisions.

We're lucky enough to catch it before we buy a large number of 8100/110s
for fileservers.

Any thoughts, comments, and discussions are welcome!

Chris Carlson
Macintosh Network Admin
Booz Allen & Hamilton
[email]
[email]


author: Randy Shackelford

subject: Re: 8100/110 + AppleShare 4.0.2 = DOES NOT WORK!!

text:
In article <3dvau3$[email]>, [email] (Chris Carlson)
writes:

Egad, Appleshare 3.0.3 runs fine under 7.5, why is this I wonder?


author: Wayne Morris

text:
Randy Shackelford ([email]) wrote:
: In article <3dvau3$[email]>, [email] (Chris Carlson)
: writes:
: > AppleShare 4.0.2 will *NOT* work with the new PowerMac 8100/110!
: >
: > I called Apple and they confirmed this.  The PowerMac 8100/110 requires at
: > least System 7.5.  Apple confirms that AppleShare 4.0.2 will not run on
: > System 7.5, and if it does run, then it'll run very flaky and they will
: > not support it.

: Egad, Appleshare 3.0.3 runs fine under 7.5, why is this I wonder?
: --

Is it true that Apple is about to release a "native" version of
AppleShare for the PPC in January, along with a few other
products?  This may be the best solution.

How many concurent users will the PowerMac 8100/110 nicely
support?  We need to purchase a file server for 40 Macs and were
hoping that a 6100/60 with the "native" software would handle it
nicely!

Where can I find some more data on servers to make a good
decision?

-------------------------------------------------------------------
Wayne Morris                    	[email]
Technology Coordinator			[email]
Bowness High School                     4627 - 77 St. N.W.
Calgary, Alberta                        T3B 2N6
Canada.                                 (403) 286-5092
-------------------------------------------------------------------


text:
In article <[email]>,
Wayne Morris <[email]> wrote:

Apple told me that AppleShare 3.X has a better chance of running on 7.5
than AppleShare 4.X.  But Apple does not encourage you to do so, and it
will not support any version of AppleShare running on 7.5.

The last release date I heard about native AppleShare is summer of 1995.
But this not official, and this may be pushed back.

The *best* platform to run a non-native version of AppleShare is still
a 68040 Macintosh.  Check out the December 1994 issue of MacUser.
Page 110 has a comparision of PowerPC and 68040 Workgroup Servers.  The
PowerPC servers were as much as 50% SLOWER than the 040 servers!!!
And this is tested in an environment of 30-40 clients.

Don't forget that it's not just the fileserving software that needs to
be native, it's also the AppleTalk stack and the filing system that
Macs use to keep track of files on disk that need to be native to work
fast.

So, the best platform now to run AppleShare is still a 040 Mac.  We can
get some Quadra 650s... perfect for the task.  When AppleShare and NetWare
for the Mac go native in summer, you'd better believe that we'll be
upgrading to fast PowerMacs with PCI buses.

Chris Carlson
Macintosh Network Admin
Booz Allen & Hamilton


author: Tony Herr

text:
In article <3dvau3$[email]> Chris Carlson, [email]
writes:
at

Figures. I ordered one of these for use as a file server and of course it
shows up today, right after I read this post. I couldn't find any
specific reference to AppleShare 4.0.2 not working with System 7.5 on
AppleLink so I'm going to try it out anyway.
----------------------------------------------------
Tony Herr - Computer Resource Specialist - DoD #1351
Bay Tree Bookstore - University of California


author: Dima

subject: Please HELP: timing problems on Virtex-4FX

text:
Hello,

I am working with the ML410 board and the V4FX60 FPGA. For the past
week and a half, I've been having problems meeting timing and I just
can't figure out why. In my design, I need to use DDR2 and the APU
controller as well as the FPU core. I also need two OPB peripherals:
the RS232 and the SystemACE. These are the clocking requirements for
my design:

CPU: 266 MHz
PLB: 100 MHz
OPB: 100 MHz
DDR2: 100 MHz controller (on PLB), 200 MHz memory (DDR2-400)
FCB: 266 MHz (fabric co-processor bus)
FPU: 133 MHz (on FCB)

All of these are within the documented limits for the cores and this
speed grade FPGA (-11). These are the steps I follow to get to this
design:

1. Start with BSB wizard and generate a 300 MHz CPU / 100 MHz PLB
design with all the above mentioned IPs, except the FCB and the FPU.
2. This design does synthesize, map, place and route, although PAR
complains that timing constraints are not met for the DDR2 clocks. I
talked with Xilinx about this and they assured me this is OK (they
know about this issue). Everything works fine at this point, although
I am not too happy with Xilinx's lack of explanation for this timing
issue.
3. Next, I modify the design to generate a CLKFX from one of the two
DCMs to make the 266 MHz CPU clock. I also uncheck the
CPMC405SYNCBYPASS option in the PPC405 configuration so that non-
integer CPU-PLB ratios are allowed. I update the frequency in the
software settings.
4. Finally, I bring in the FCB and the APU-FPU cores. I tie the FCB to
the processor clock, and use a CLKFX output on one of the DCMs to
generate the 133 MHz clock for the APU-FPU core. I enable APU support
in the PPC405 processor core.
5. When I build this system, I get 3 timing constraints not met: 1 for
the DDR2 (as seen previously, but according to Xilinx not to worry
about, and 2 new ones). The 2 new failing constraints are the CPU 266
MHZ clock and the FPU 133 MHZ clock. I tried executing my software on
this faulty hardware and it works sometimes, but not always. I do get
DCM lock though.

This is how I have my two DCMs configured:

dcm_0 (DFS low, DLL low)
--------------------------------------
RST: net_gnd
CLKIN: dcm_clk_s (from sys_clk_pin, 100 MHz)
CLKFB: sys_clk_s (100 MHz)
CLK0: sys_clk_s (PLB and OPB clock, 100 MHz, BUFG)
CLKDV: ddr2_cal_clk (50 MHz, BUFG)
CLK2X: dcm_0CLK2X (cascade to next DCM, 200 MHz, BUFG)
CLKFX: apu_fpu_clk_s (FPU clock, 133 MHz, BUFG)
LOCKED: dcm_0_lock (to next DCM)

dcm_1 (DFS high, DLL high)
--------------------------------------
RST: dcm_0_lock (from previous DCM)
CLKIN: dcm_0CLK2X (from previous DCM, 200 MHz)
CLKFB: clk_200mhz_s (200 MHz)
CLK0: clk_200mhz_s (DDR2 clock, 200 MHz, BUFG)
CLK90: ddr2_dev_clk_90_s (DDR2 clock, 200 MHz, BUFG)
CLKFX: proc_clk_s (CPU clock, 266 MHz, BUFG)
LOCKED: dcm_1_lock (to reset_block)

Like I said, I can't think of why this would not meet timing! Is it
harder to route a 266 MHz CPU clock than a 300 Mhz design? What can I
do to mitigate this? I tried various options in synthesis, map, PAR,
and the Xplorer script. But I think it probably is something in my
configuration of the DCMs, because it should work as I am not asking
for a very high frequency.

Any help would be very greatly appreciated (I would hate to go back to
a working 200 MHz design because of this).

Thanks

Dmitriy Bekker


subject: Re: Please HELP: timing problems on Virtex-4FX

text:
Hi Ben,

Ahh yes, of course. I have pasted the failing paths right below this
message. Unfortunatly, I couldn't attach the log file directly, so
please excuse the poor formatting. I reran the build this time without
the MGT protector core. Also, I implemented the workaround in AR 24326
which suppresses the DDR2 failing constraint. This note explains why
it is safe to suppress the DDR2 timing failure. I am a lot more
comfortable with this explanation than simply to ignore it.
Nevertheless, the design still fails wiht proc_clk_s and apu_fpu_clk_s
not meeting timing.

I also implemented a very basic design with only a few components:
CPU, PLB BRAM, and OPB RS232. I changed the CPU frequency to 266.67
MHz by only modifying CLKFX on dcm_0 (this one only has a single DCM
since no DDR2). I changed CLKFX to be M=8 and D=3 (instead of the
original M=3, D=1 for 300 MHz). Even this basic design still fails
timing! I have pasted the failing path for this design as well (see
below).

Do you have a suggestion on how I should configure the DCMs for a
266-133 CPU-FPU ratio? Even a working basic design, without any memory
(like DDR2) would help. These frequencies are within the limits and I
am sure Xilinx must have tested this exact configuration to find the
maximum allowable frequency (which is 275 MHz for the CPU -11 grade
and 137.5 MHz for the FPU). If you have any suggestions here, I will
try them. I am running out of ideas. I opened up a webcase today as
well to see if I can get help from that avenue.

The failing paths are pasted in below. Thanks for your help.

- Dmitriy

================================================================================
DESIGN 1 with DDR2 (apu_fpu_clk_s)
================================================================================
Timing constraint: TS_system_i_dcm_0_dcm_0_CLKFX_BUF = PERIOD
TIMEGRP
"system_i_dcm_0_dcm_0_CLKFX_BUF" TS_sys_clk_pin / 1.33333333 HIGH 50%;

 423953 items analyzed, 50 timing errors detected. (48 setup errors, 2
hold errors)
 Minimum period is   9.606ns.
--------------------------------------------------------------------------------
Slack:                  -1.053ns (requirement - (data path - clock
path skew + uncertainty))
  Source:               system_i/apu_fpu_0/apu_fpu_0/
gen_apu_fpu_sp_full.netlist/rs_fir_l1[31].r (FF)
  Destination:          system_i/apu_fpu_0/apu_fpu_0/
gen_apu_fpu_sp_full.netlist/fpu_fetch_state_2 (FF)
  Requirement:          3.750ns
  Data Path Delay:      4.227ns (Levels of Logic = 7)
  Clock Path Skew:      -0.053ns
  Source Clock:         system_i/proc_clk_s rising at 3.750ns
  Destination Clock:    system_i/apu_fpu_clk_s rising at 7.500ns
  Clock Uncertainty:    0.523ns

  Clock Uncertainty:          0.523ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2
+ PE
    Total System Jitter (TSJ):  0.000ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.311ns
    Phase Error (PE):           0.367ns

  Maximum Data Path: system_i/apu_fpu_0/apu_fpu_0/
gen_apu_fpu_sp_full.netlist/rs_fir_l1[31].r to system_i/apu_fpu_0/
apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_state_2
    Location             Delay type         Delay(ns)  Physical
Resource
                                                       Logical
Resource(s)
    -------------------------------------------------
-------------------
    SLICE_X28Y200.YQ     Tcko                  0.307   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/instruction(1)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/rs_fir_l1[31].r
    SLICE_X34Y189.F2     net (fanout=12)       1.127   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/instruction(0)
    SLICE_X34Y189.COUT   Topcyf                0.491   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc0_subchain(1)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_dec_prod_0_and00001
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc0_cch[2].cmux
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc0_cch[1].cmux
    SLICE_X34Y190.CIN    net (fanout=1)        0.000   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc0_subchain(1)
    SLICE_X34Y190.COUT   Tbyp                  0.076   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc1_subchain(1)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc0_cch[0].cmux
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc1_cch[1].cmux
    SLICE_X34Y191.CIN    net (fanout=1)        0.000   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc1_subchain(1)
    SLICE_X34Y191.COUT   Tbyp                  0.076   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc2_subchain(1)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc1_cch[0].cmux
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc2_cch[1].cmux
    SLICE_X34Y192.CIN    net (fanout=1)        0.000   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc2_subchain(1)
    SLICE_X34Y192.XB     Tcinxb                0.339   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_dec_chain(3)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc2_cch[0].cmux
    SLICE_X37Y193.G4     net (fanout=6)        0.724   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_dec_chain(2)
    SLICE_X37Y193.Y      Tilo                  0.165   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_state_0_mux0001_map12
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_state_2_mux000125_sw0
    SLICE_X36Y196.G4     net (fanout=1)        0.438   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/n4862
    SLICE_X36Y196.Y      Tilo                  0.166   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_state(2)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_state_2_mux000125
    SLICE_X36Y196.F4     net (fanout=1)        0.135   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_state_2_mux0001_map11
    SLICE_X36Y196.CLK    Tfck                  0.183   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_state(2)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_state_2_mux000176
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_state_2
    -------------------------------------------------
---------------------------
    Total                                      4.227ns (1.803ns logic,
2.424ns route)
                                                       (42.7% logic,
57.3% route)

--------------------------------------------------------------------------------
Slack:                  -1.037ns (requirement - (data path - clock
path skew + uncertainty))
  Source:               system_i/apu_fpu_0/apu_fpu_0/
gen_apu_fpu_sp_full.netlist/rs_fir_l1[31].r (FF)
  Destination:          system_i/apu_fpu_0/apu_fpu_0/
gen_apu_fpu_sp_full.netlist/fpu_fetch_state_3 (FF)
  Requirement:          3.750ns
  Data Path Delay:      4.211ns (Levels of Logic = 6)
  Clock Path Skew:      -0.053ns
  Source Clock:         system_i/proc_clk_s rising at 3.750ns
  Destination Clock:    system_i/apu_fpu_clk_s rising at 7.500ns
  Clock Uncertainty:    0.523ns

  Clock Uncertainty:          0.523ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2
+ PE
    Total System Jitter (TSJ):  0.000ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.311ns
    Phase Error (PE):           0.367ns

  Maximum Data Path: system_i/apu_fpu_0/apu_fpu_0/
gen_apu_fpu_sp_full.netlist/rs_fir_l1[31].r to system_i/apu_fpu_0/
apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_state_3
    Location             Delay type         Delay(ns)  Physical
Resource
                                                       Logical
Resource(s)
    -------------------------------------------------
-------------------
    SLICE_X28Y200.YQ     Tcko                  0.307   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/instruction(1)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/rs_fir_l1[31].r
    SLICE_X34Y189.F2     net (fanout=12)       1.127   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/instruction(0)
    SLICE_X34Y189.COUT   Topcyf                0.491   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc0_subchain(1)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_dec_prod_0_and00001
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc0_cch[2].cmux
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc0_cch[1].cmux
    SLICE_X34Y190.CIN    net (fanout=1)        0.000   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc0_subchain(1)
    SLICE_X34Y190.COUT   Tbyp                  0.076   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc1_subchain(1)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc0_cch[0].cmux
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc1_cch[1].cmux
    SLICE_X34Y191.CIN    net (fanout=1)        0.000   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc1_subchain(1)
    SLICE_X34Y191.COUT   Tbyp                  0.076   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc2_subchain(1)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc1_cch[0].cmux
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc2_cch[1].cmux
    SLICE_X34Y192.CIN    net (fanout=1)        0.000   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc2_subchain(1)
    SLICE_X34Y192.XB     Tcinxb                0.339   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_dec_chain(3)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc2_cch[0].cmux
    SLICE_X36Y197.G3     net (fanout=6)        0.819   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_dec_chain(2)
    SLICE_X36Y197.XMUX   Tif5x                 0.477   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_state_3_mux0001_map1
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_state_3_mux0001171
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_state_3_mux000117_f5
    SLICE_X37Y197.G4     net (fanout=1)        0.303   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_state_3_mux0001_map7
    SLICE_X37Y197.CLK    Tgck                  0.196   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_state(3)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_state_3_mux000126
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_state_3
    -------------------------------------------------
---------------------------
    Total                                      4.211ns (1.962ns logic,
2.249ns route)
                                                       (46.6% logic,
53.4% route)

--------------------------------------------------------------------------------
Slack:                  -1.015ns (requirement - (data path - clock
path skew + uncertainty))
  Source:               system_i/apu_fpu_0/apu_fpu_0/
gen_apu_fpu_sp_full.netlist/rs_fir_l1[1].r (FF)
  Destination:          system_i/apu_fpu_0/apu_fpu_0/
gen_apu_fpu_sp_full.netlist/fpu_fetch_state_2 (FF)
  Requirement:          3.750ns
  Data Path Delay:      4.189ns (Levels of Logic = 6)
  Clock Path Skew:      -0.053ns
  Source Clock:         system_i/proc_clk_s rising at 3.750ns
  Destination Clock:    system_i/apu_fpu_clk_s rising at 7.500ns
  Clock Uncertainty:    0.523ns

  Clock Uncertainty:          0.523ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2
+ PE
    Total System Jitter (TSJ):  0.000ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.311ns
    Phase Error (PE):           0.367ns

  Maximum Data Path: system_i/apu_fpu_0/apu_fpu_0/
gen_apu_fpu_sp_full.netlist/rs_fir_l1[1].r to system_i/apu_fpu_0/
apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_state_2
    Location             Delay type         Delay(ns)  Physical
Resource
                                                       Logical
Resource(s)
    -------------------------------------------------
-------------------
    SLICE_X28Y201.YQ     Tcko                  0.307   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/instruction(31)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/rs_fir_l1[1].r
    SLICE_X34Y190.F1     net (fanout=5)        1.165   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/instruction(30)
    SLICE_X34Y190.COUT   Topcyf                0.491   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc1_subchain(1)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_dec_prod_2_and00001
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc0_cch[0].cmux
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc1_cch[1].cmux
    SLICE_X34Y191.CIN    net (fanout=1)        0.000   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc1_subchain(1)
    SLICE_X34Y191.COUT   Tbyp                  0.076   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc2_subchain(1)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc1_cch[0].cmux
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc2_cch[1].cmux
    SLICE_X34Y192.CIN    net (fanout=1)        0.000   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc2_subchain(1)
    SLICE_X34Y192.XB     Tcinxb                0.339   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_dec_chain(3)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_idc2_cch[0].cmux
    SLICE_X37Y193.G4     net (fanout=6)        0.724   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_dec_chain(2)
    SLICE_X37Y193.Y      Tilo                  0.165   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_state_0_mux0001_map12
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_state_2_mux000125_sw0
    SLICE_X36Y196.G4     net (fanout=1)        0.438   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/n4862
    SLICE_X36Y196.Y      Tilo                  0.166   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_state(2)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_state_2_mux000125
    SLICE_X36Y196.F4     net (fanout=1)        0.135   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_state_2_mux0001_map11
    SLICE_X36Y196.CLK    Tfck                  0.183   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_state(2)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_state_2_mux000176
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_state_2
    -------------------------------------------------
---------------------------
    Total                                      4.189ns (1.727ns logic,
2.462ns route)
                                                       (41.2% logic,
58.8% route)

--------------------------------------------------------------------------------
Hold Violations: TS_system_i_dcm_0_dcm_0_CLKFX_BUF = PERIOD
TIMEGRP         "system_i_dcm_0_dcm_0_CLKFX_BUF" TS_sys_clk_pin /
1.33333333 HIGH 50%;
--------------------------------------------------------------------------------
Hold Violation:         -0.083ns (requirement - (clock path skew +
uncertainty - data path))
  Source:               system_i/apu_fpu_0/apu_fpu_0/
gen_apu_fpu_sp_full.netlist/rs_fir_l1[30].r (FF)
  Destination:          system_i/apu_fpu_0/apu_fpu_0/
gen_apu_fpu_sp_full.netlist/fpu_fetch_id_class.fpu_maj (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.454ns (Levels of Logic = 1)
  Positive Clock Path Skew: 0.014ns
  Source Clock:         system_i/proc_clk_s rising at 3.750ns
  Destination Clock:    system_i/apu_fpu_clk_s rising at 7.500ns
  Clock Uncertainty:    0.523ns

  Clock Uncertainty:          0.523ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2
+ PE
    Total System Jitter (TSJ):  0.000ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.311ns
    Phase Error (PE):           0.367ns

  Maximum Data Path: system_i/apu_fpu_0/apu_fpu_0/
gen_apu_fpu_sp_full.netlist/rs_fir_l1[30].r to system_i/apu_fpu_0/
apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_id_class.fpu_maj
    Location             Delay type         Delay(ns)  Physical
Resource
                                                       Logical
Resource(s)
    -------------------------------------------------
-------------------
    SLICE_X28Y200.XQ     Tcko                  0.283   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/instruction(1)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/rs_fir_l1[30].r
    SLICE_X29Y200.F4     net (fanout=3)        0.275   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/instruction(1)
    SLICE_X29Y200.CLK    Tckf        (-Th)     0.104   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_id_class.fpu_maj
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_if_fpu_maj1
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_id_class.fpu_maj
    -------------------------------------------------
---------------------------
    Total                                      0.454ns (0.179ns logic,
0.275ns route)
                                                       (39.4% logic,
60.6% route)
--------------------------------------------------------------------------------
Hold Violation:         -0.039ns (requirement - (clock path skew +
uncertainty - data path))
  Source:               system_i/apu_fpu_0/apu_fpu_0/
gen_apu_fpu_sp_full.netlist/rs_fir_l1[26].r (FF)
  Destination:          system_i/apu_fpu_0/apu_fpu_0/
gen_apu_fpu_sp_full.netlist/fpu_fetch_id_class.fpu_maj (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.515ns (Levels of Logic = 1)
  Positive Clock Path Skew: 0.031ns
  Source Clock:         system_i/proc_clk_s rising at 3.750ns
  Destination Clock:    system_i/apu_fpu_clk_s rising at 7.500ns
  Clock Uncertainty:    0.523ns

  Clock Uncertainty:          0.523ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2
+ PE
    Total System Jitter (TSJ):  0.000ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.311ns
    Phase Error (PE):           0.367ns

  Maximum Data Path: system_i/apu_fpu_0/apu_fpu_0/
gen_apu_fpu_sp_full.netlist/rs_fir_l1[26].r to system_i/apu_fpu_0/
apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_id_class.fpu_maj
    Location             Delay type         Delay(ns)  Physical
Resource
                                                       Logical
Resource(s)
    -------------------------------------------------
-------------------
    SLICE_X30Y200.XQ     Tcko                  0.283   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/instruction(5)
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/rs_fir_l1[26].r
    SLICE_X29Y200.F3     net (fanout=9)        0.336   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/instruction(5)
    SLICE_X29Y200.CLK    Tckf        (-Th)     0.104   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_id_class.fpu_maj
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_fetch_if_fpu_maj1
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_fetch_id_class.fpu_maj
    -------------------------------------------------
---------------------------
    Total                                      0.515ns (0.179ns logic,
0.336ns route)
                                                       (34.8% logic,
65.2% route)
--------------------------------------------------------------------------------

================================================================================
DESIGN 1 with DDR2 (proc_clk_s)
================================================================================
Timing constraint: TS_system_i_dcm_1_dcm_1_CLKFX_BUF = PERIOD
TIMEGRP
"system_i_dcm_1_dcm_1_CLKFX_BUF"
TS_system_i_dcm_0_dcm_0_CLK2X_BUF /
1.33333333 HIGH 50%;

 1029 items analyzed, 34 timing errors detected. (34 setup errors, 0
hold errors)
 Minimum period is   5.958ns.
--------------------------------------------------------------------------------
Slack:                  -0.736ns (requirement - (data path - clock
path skew + uncertainty))
  Source:               system_i/reset_block/reset_block/
Rstc405resetcore (FF)
  Destination:          system_i/ppc405_0/ppc405_0/PPC405_ADV_i (CPU)
  Requirement:          1.250ns
  Data Path Delay:      1.528ns (Levels of Logic = 0)
  Clock Path Skew:      -0.108ns
  Source Clock:         system_i/sys_clk_s rising at 10.000ns
  Destination Clock:    system_i/proc_clk_s rising at 11.250ns
  Clock Uncertainty:    0.350ns

  Clock Uncertainty:          0.350ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2
+ PE
    Total System Jitter (TSJ):  0.000ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.236ns
    Phase Error (PE):           0.231ns

  Maximum Data Path: system_i/reset_block/reset_block/Rstc405resetcore
to system_i/ppc405_0/ppc405_0/PPC405_ADV_i
    Location                         Delay type         Delay(ns)
Physical Resource

Logical Resource(s)
    -------------------------------------------------------------
-------------------
    SLICE_X19Y169.XQ                 Tcko                  0.291
system_i/RSTC405RESETCORE

system_i/reset_block/reset_block/Rstc405resetcore
    PPC405_ADV_X0Y1.RSTC405RESETCORE net (fanout=1)        0.437
system_i/RSTC405RESETCORE
    PPC405_ADV_X0Y1.CPMC405CLOCK     Tppcdck_RSTCORE       0.800
system_i/ppc405_0/ppc405_0/PPC405_ADV_i

system_i/ppc405_0/ppc405_0/PPC405_ADV_i
    -------------------------------------------------------------
---------------------------
    Total                                                  1.528ns
(1.091ns logic, 0.437ns route)

(71.4% logic, 28.6% route)

--------------------------------------------------------------------------------
Slack:                  -0.701ns (requirement - (data path - clock
path skew + uncertainty))
  Source:               system_i/reset_block/reset_block/
Rstc405resetchip (FF)
  Destination:          system_i/ppc405_0/ppc405_0/PPC405_ADV_i (CPU)
  Requirement:          1.250ns
  Data Path Delay:      1.499ns (Levels of Logic = 0)
  Clock Path Skew:      -0.102ns
  Source Clock:         system_i/sys_clk_s rising at 10.000ns
  Destination Clock:    system_i/proc_clk_s rising at 11.250ns
  Clock Uncertainty:    0.350ns

  Clock Uncertainty:          0.350ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2
+ PE
    Total System Jitter (TSJ):  0.000ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.236ns
    Phase Error (PE):           0.231ns

  Maximum Data Path: system_i/reset_block/reset_block/Rstc405resetchip
to system_i/ppc405_0/ppc405_0/PPC405_ADV_i
    Location                         Delay type         Delay(ns)
Physical Resource

Logical Resource(s)
    -------------------------------------------------------------
-------------------
    SLICE_X19Y172.YQ                 Tcko                  0.291
system_i/RSTC405RESETCHIP

system_i/reset_block/reset_block/Rstc405resetchip
    PPC405_ADV_X0Y1.RSTC405RESETCHIP net (fanout=1)        0.558
system_i/RSTC405RESETCHIP
    PPC405_ADV_X0Y1.CPMC405CLOCK     Tppcdck_RSTCHIP       0.650
system_i/ppc405_0/ppc405_0/PPC405_ADV_i

system_i/ppc405_0/ppc405_0/PPC405_ADV_i
    -------------------------------------------------------------
---------------------------
    Total                                                  1.499ns
(0.941ns logic, 0.558ns route)

(62.8% logic, 37.2% route)

--------------------------------------------------------------------------------
Slack:                  -0.664ns (requirement - (data path - clock
path skew + uncertainty))
  Source:               system_i/apu_fpu_0/apu_fpu_0/
gen_apu_fpu_sp_full.netlist/fpu_ldst_store_phase2 (FF)
  Destination:          system_i/apu_fpu_0/apu_fpu_0/
gen_apu_fpu_sp_full.netlist/rs_ardr_l1[29].r (FF)
  Requirement:          3.750ns
  Data Path Delay:      3.818ns (Levels of Logic = 2)
  Clock Path Skew:      -0.256ns
  Source Clock:         system_i/apu_fpu_clk_s rising at 0.000ns
  Destination Clock:    system_i/proc_clk_s rising at 3.750ns
  Clock Uncertainty:    0.340ns

  Clock Uncertainty:          0.340ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2
+ PE
    Total System Jitter (TSJ):  0.000ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.311ns
    Phase Error (PE):           0.184ns

  Maximum Data Path: system_i/apu_fpu_0/apu_fpu_0/
gen_apu_fpu_sp_full.netlist/fpu_ldst_store_phase2 to system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/rs_ardr_l1[29].r
    Location             Delay type         Delay(ns)  Physical
Resource
                                                       Logical
Resource(s)
    -------------------------------------------------
-------------------
    SLICE_X29Y204.YQ     Tcko                  0.291   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_ldst_store_phase2
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_ldst_store_phase2
    SLICE_X29Y204.F1     net (fanout=36)       0.678   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_ldst_store_phase2
    SLICE_X29Y204.X      Tilo                  0.165   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_ldst_store_phase2
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_ldst_use_direct1
    SLICE_X51Y202.BX     net (fanout=32)       2.259   system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/fpu_ldst_use_direct
    SLICE_X51Y202.CLK    Tdick                 0.425   system_i/
fcb_v10_0_FCMAPURESULT<2>
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/
fpu_ldst_st_sngl.sdm_m5.mm[29].cmux
                                                       system_i/
apu_fpu_0/apu_fpu_0/gen_apu_fpu_sp_full.netlist/rs_ardr_l1[29].r
    -------------------------------------------------
---------------------------
    Total                                      3.818ns (0.881ns logic,
2.937ns route)
                                                       (23.1% logic,
76.9% route)

--------------------------------------------------------------------------------

================================================================================
DESIGN 2 with no DDR2 (proc_clk_s)
================================================================================
Timing constraint: TS_system_i_dcm_0_dcm_0_CLKFX_BUF = PERIOD
TIMEGRP
"system_i_dcm_0_dcm_0_CLKFX_BUF" TS_sys_clk_pin / 2.66666667 HIGH 50%;

 3 items analyzed, 3 timing errors detected. (3 setup errors, 0 hold
errors)
 Minimum period is   5.438ns.
--------------------------------------------------------------------------------
Slack:                  -0.562ns (requirement - (data path - clock
path skew + uncertainty))
  Source:               system_i/reset_block/reset_block/
Rstc405resetcore (FF)
  Destination:          system_i/ppc405_0/ppc405_0/PPC405_ADV_i (CPU)
  Requirement:          1.250ns
  Data Path Delay:      1.514ns (Levels of Logic = 0)
  Clock Path Skew:      -0.040ns
  Source Clock:         system_i/plb_bram_if_cntlr_1_port_BRAM_Clk
rising at 10.000ns
  Destination Clock:    system_i/proc_clk_s rising at 11.250ns
  Clock Uncertainty:    0.258ns

  Clock Uncertainty:          0.258ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2
+ PE
    Total System Jitter (TSJ):  0.000ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.235ns
    Phase Error (PE):           0.140ns

  Maximum Data Path: system_i/reset_block/reset_block/Rstc405resetcore
to system_i/ppc405_0/ppc405_0/PPC405_ADV_i
    Location                         Delay type         Delay(ns)
Physical Resource

Logical Resource(s)
    -------------------------------------------------------------
-------------------
    SLICE_X18Y74.XQ                  Tcko                  0.307
system_i/RSTC405RESETCORE

system_i/reset_block/reset_block/Rstc405resetcore
    PPC405_ADV_X0Y0.RSTC405RESETCORE net (fanout=1)        0.407
system_i/RSTC405RESETCORE
    PPC405_ADV_X0Y0.CPMC405CLOCK     Tppcdck_RSTCORE       0.800
system_i/ppc405_0/ppc405_0/PPC405_ADV_i

system_i/ppc405_0/ppc405_0/PPC405_ADV_i
    -------------------------------------------------------------
---------------------------
    Total                                                  1.514ns
(1.107ns logic, 0.407ns route)

(73.1% logic, 26.9% route)

--------------------------------------------------------------------------------
Slack:                  -0.426ns (requirement - (data path - clock
path skew + uncertainty))
  Source:               system_i/reset_block/reset_block/
Rstc405resetsys (FF)
  Destination:          system_i/ppc405_0/ppc405_0/PPC405_ADV_i (CPU)
  Requirement:          1.250ns
  Data Path Delay:      1.378ns (Levels of Logic = 0)
  Clock Path Skew:      -0.040ns
  Source Clock:         system_i/plb_bram_if_cntlr_1_port_BRAM_Clk
rising at 10.000ns
  Destination Clock:    system_i/proc_clk_s rising at 11.250ns
  Clock Uncertainty:    0.258ns

  Clock Uncertainty:          0.258ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2
+ PE
    Total System Jitter (TSJ):  0.000ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.235ns
    Phase Error (PE):           0.140ns

  Maximum Data Path: system_i/reset_block/reset_block/Rstc405resetsys
to system_i/ppc405_0/ppc405_0/PPC405_ADV_i
    Location                        Delay type         Delay(ns)
Physical Resource

Logical Resource(s)
    ------------------------------------------------------------
-------------------
    SLICE_X19Y74.YQ                 Tcko                  0.291
system_i/RSTC405RESETSYS

system_i/reset_block/reset_block/Rstc405resetsys
    PPC405_ADV_X0Y0.RSTC405RESETSYS net (fanout=1)        0.437
system_i/RSTC405RESETSYS
    PPC405_ADV_X0Y0.CPMC405CLOCK    Tppcdck_RSTSYS        0.650
system_i/ppc405_0/ppc405_0/PPC405_ADV_i

system_i/ppc405_0/ppc405_0/PPC405_ADV_i
    ------------------------------------------------------------
---------------------------
    Total                                                 1.378ns
(0.941ns logic, 0.437ns route)

(68.3% logic, 31.7% route)

--------------------------------------------------------------------------------
Slack:                  -0.426ns (requirement - (data path - clock
path skew + uncertainty))
  Source:               system_i/reset_block/reset_block/
Rstc405resetchip (FF)
  Destination:          system_i/ppc405_0/ppc405_0/PPC405_ADV_i (CPU)
  Requirement:          1.250ns
  Data Path Delay:      1.378ns (Levels of Logic = 0)
  Clock Path Skew:      -0.040ns
  Source Clock:         system_i/plb_bram_if_cntlr_1_port_BRAM_Clk
rising at 10.000ns
  Destination Clock:    system_i/proc_clk_s rising at 11.250ns
  Clock Uncertainty:    0.258ns

  Clock Uncertainty:          0.258ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2
+ PE
    Total System Jitter (TSJ):  0.000ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.235ns
    Phase Error (PE):           0.140ns

  Maximum Data Path: system_i/reset_block/reset_block/Rstc405resetchip
to system_i/ppc405_0/ppc405_0/PPC405_ADV_i
    Location                         Delay type         Delay(ns)
Physical Resource

Logical Resource(s)
    -------------------------------------------------------------
-------------------
    SLICE_X19Y75.XQ                  Tcko                  0.291
system_i/RSTC405RESETCHIP

system_i/reset_block/reset_block/Rstc405resetchip
    PPC405_ADV_X0Y0.RSTC405RESETCHIP net (fanout=1)        0.437
system_i/RSTC405RESETCHIP
    PPC405_ADV_X0Y0.CPMC405CLOCK     Tppcdck_RSTCHIP       0.650
system_i/ppc405_0/ppc405_0/PPC405_ADV_i

system_i/ppc405_0/ppc405_0/PPC405_ADV_i
    -------------------------------------------------------------
---------------------------
    Total                                                  1.378ns
(0.941ns logic, 0.437ns route)

(68.3% logic, 31.7% route)

--------------------------------------------------------------------------------


text:
Hi Ben,

Certainly. These are the filing paths from the timing report:

Failing path 1: 266 MHz CPU clock (proc_clk_s)
Constraint: TS_dcm_1_dcm_1_CLKFX_BUF = PERIOD TIMEGRP
"dcm_1_dcm_1_CLKFX_BUF" TS_dcm_0_dcm_0_CLK2X_BUF / 1.33333333 HIGH 50%
-----------------------------------------------------------------------------
Check   Worst Case  Best Case     Timing     Timing
                Slack       Achievable     Errors      Score
-----------------------------------------------------------------------------
SETUP    -0.703ns     5.859ns          24          4342
HOLD       0.380ns                            0
0
-----------------------------------------------------------------------------

Failing path 2: 133 MHz FPU clock (apu_fpu_clk_s)
Constraint: TS_dcm_0_dcm_0_CLKFX_BUF = PERIOD TIMEGRP
"dcm_0_dcm_0_CLKFX_BUF" TS_sys_clk_pin / 1.33333333 HIGH 50%
-----------------------------------------------------------------------------
Check   Worst Case  Best Case     Timing     Timing
                Slack       Achievable     Errors      Score
-----------------------------------------------------------------------------
SETUP    -0.698ns     8.896ns          28          8584
HOLD       0.013ns                            0
0
-----------------------------------------------------------------------------

Failing path 3: 200 MHz DDR2 clock (clk_200mhz_s)
Constraint: TS_dcm_1_dcm_1_CLK0_BUF = PERIOD TIMEGRP
"dcm_1_dcm_1_CLK0_BUF" TS_dcm_0_dcm_0_CLK2X_BUF HIGH 50%
-----------------------------------------------------------------------------
Check   Worst Case  Best Case     Timing     Timing
                Slack       Achievable     Errors      Score
-----------------------------------------------------------------------------
SETUP   -0.596ns    6.192ns           177        30754
HOLD      0.387ns                             0
0
-----------------------------------------------------------------------------

The cascading DCMs are mainly for DDR2 clock and its clk_90
counterpart. This is the way they come out of BSB wizard. But path 3
does fail from the start (DDR2 clock). It comes out failing from the
BSB wizard without me changing anything in the design.

(1) The design is not full at all. I am only using 20% of the slices
now.
(2) I am using the latest version of EDK (9.1i with SP1)
(3) I am using the latest apu-fpu core (v3.0)

I found it odd that even without the apu-fpu core, my CPU net fails
when I try to clock it at 266 MHz instead of 300 MHz. All I did there
was change the CLKFX multiplier and divider values (and uncheck
CPMC405SYNCBYPASS)! Is there something I am missing here?

I am also using the MGT protector core, which runs off proc_clk_s.
Would that impact the timing? I will try without it.I did notice it
LOCed one of my DCMs.

Thanks

Dmitriy


author: Ben Jones

text:
Hi Dmitriy,

"Dima" <[email]> wrote in message
news:[email]...

Thanks for the detailed information. Perhaps you could also post some of the
failing paths from the timing report? Otherwise we're all a bit in the dark.

Cascading DCMs in the way you've described does tend to increase jitter on
the resulting clock nets, which can often eat into your timing budget. A few
questions:

 (1) How full is your device?
 (2) Which version of EDK are you using; and, in particular:
 (3) ...which version the apu-fpu core?

Cheers,

    -Ben-


text:
Hi Dmitriy,

Thanks, that's very useful. It's clear that the failing paths are inside the
apu_fpu core.

Well according to the report you attached, the timing analyser believes that
the clocks are properly aligned, and that's good enough for me. However, you
can see that the "clock uncertainty" is pretty high at >0.5ns - that's more
than 10% of the cycle budget. However, this alone doesn't explain why the
design is failing timing.

Not this exact configuration, but it certainly runs at 275 CPU : 137.5 FPU
in V4FX-11. I know this, because I'm the guy who design, implemented and
tested this core. :)

Looking at the details of the report, there are a couple of things I
wouldn't expect. Firstly there's a massive net delay up front which suggests
that the fetch-stage instruction register is getting placed sub-optimally.
Secondly, there's at least one extra level of logic more than there should
be on this critical path. The fact that the offending net names are suffixed
with "_mapNN" suggests that the mapper has rearranged some of this logic and
managed to make it worse. I've seen similar happenings before.

Therefore... what options are you passing to MAP? In case you didn't know,
there is a .opt file in your EDK project's /etc directory that specifies
this. By default, it does *not* use timing-driven mapping, which is highly
recommended. There are a few other options which may help or hinder you
here: -global_opt and -logic_opt are the ones that spring to mind. Just add
(or remove) the options in the .opt file under the "Program map" heading,
one option per line.

I know there is a script called "Xplorer" which will try out these different
options for you automatically.  Seems to me like an admission that the tools
don't work properly, but it's not just FPGA tools that exhibit this sort of
unpredicable speed-optimization-may-slow-things-down problem - C compilers
are just as bad! But if you get desparate, you could try that.

Once again, I hope you can get this sorted soon...

Cheers,

         -Ben-


text:
Hi Dmitriy,

"Dima" <[email]> wrote in message
news:[email]...

Well, those are the failing timespecs, certainly! More useful would be the
paths themselves, from the TRACE report (.twr file), telling you the source
and destination nets of the worst N paths in each timing group (where N is
by default 3, I think). The clock uncertainty and skew are also reported
there.

Looking again at your clocking architecture, I'm not sure that the DCM
configuration you're using will guarantee a rising-edge alignment between
the 266MHz and 133MHz clocks - which is a requirement for the apu_fpu core.

I haven't used the DDR2 core in the latest release but I understand you've
been advised that this warning can be safely ignored? Doesn't sound ideal
though. :-\

Excellent, thanks. The reason I wanted to check was that required clocking
configuration changed considerably (as you might or might not have noticed)
between v2.1 and v3.0 of the FPU core.

Yes, that's weird. I was about to ask what other logic you had running off
proc_clk_s, but...

Good idea. Otherwise, the only things that are running off proc_clk_s are
(a) the FCB bus interface, which is mostly just wires, and (b) the CPU
itself, which just has minimum clock pulse widths (1.818ns in the
configuration you're using, I believe).

Hope you get to the bottom of this soon...

Cheers,

        -Ben-


author: Jon Slaughter

subject: Re: captchas

text:
"Geoff Berrow" <[email]> wrote in message
news:[email]...

No, its people like you that I hurl insults at.

Instead of being constructive you guys always try to find any way to shoot
down an idea. "Lets do this?" "No, It won't work because theres a 0.0001%
that this will happen" or some bs like that. In this case its "Its no good
because 0.1% of the population cannot use it well".

You guys (You, Jerry, and David) are the type of people that always find
fault with anything. You gotta bitch and complain because thats all your
good at.

The fact is that you guys are just looking for somethign to bitch at and I'm
not going to let you take it out on me. You don't like my ideas... then
thats fine... but shut the fuck up about it. Don't try and make me out to be
an idiot cause you can't come up with your own ideas. Just keep your mouth
shut... no one asks you to reply.  Its one thing to critize and to try and
help and its another to critize because your just an asshole and you get
your kicks out if it.


author: Jerry Stuckle

subject: Re: captchas

text:
Jon Slaughter wrote:

No, I don't find fault with everything.  There are a lot of good things
I support.

I just find fault with stupid ideas - like yours.  But like most morons,
you're unable to recognize the real-world faults in your idea.

Fortunately, *real programmers* don't suffer from perfectionalism.  They
can recognize there may be faults in their ideas.


author: Jim Carlock

subject: Re: captchas

text:
"Jerry Stuckle" wrote...
: Fortunately, *real programmers* don't suffer from perfectionalism.
: They can recognize there may be faults in their ideas.

The perfect programmer is an illusion painted by an artsy individual.

What's wrong with your time? Or is it my time?


subject: Re: captchas

text:
Jim Carlock wrote:

Who said anything about a "perfect programmer"?  There is no such thing.

I was talking about *real programmers* vs.
I-wanna-be-a-programmer-but-don't want to study'  folks.


author: Paul Beer

subject: Re: PERFORMANCE TWEAK FOR 95 (nfs)

text:
[email] wrote:

<snip>

 Steve, there's no point making this more complex than need be, you might get
bamboozled or nervous!  I don't know anyting about hex either, but as far as
changing that registry entry goes, all you have to do is open the little
namecache & pathcache boxes by double-clicking them, and change the entries to
what they're supposed to be.  You can edit the numbers just like editing text;
use your cursor & backspace or del keys to make the changes.  If you're not sure
just choose cancel to put it back the way it was.  The numbers don't quite
behave like a normal row of numbers or text, but still easy to edit them how you
wish.

Paul


author: eli m

subject: Remove space from input

text: Hi, I have a program where the input involves space sometimes and i want to remove  the spaces from the input. For example: if they type in hello world, then it would receive helloworld. How would i do this? Thanks in advance.


subject: Re: Remove space from input

text:
On Sunday, March 17, 2013 1:06:48 PM UTC-7, Andy Champ wrote:

Can you provide an example please? Sorry, i am a noob.


author: James Kanze

subject: Re: Remove space from input

text:
On Sunday, 17 March 2013 18:12:57 UTC, eli m  wrote:

	std::string word;
	while ( input >> word ) {
		output << word;
	}

will copy the input to the output, removing all spaces.  Or

	std::string results;
	std::string word;
	while ( input >> word ) {
		results += word;
	}

will result in the input, without spaces, in results.

--
James


subject: Re: Remove space from input

text:
On Saturday, March 16, 2013 6:53:59 PM UTC, eli m wrote:

Just use >> on strings, and then concatenate them.

--
James


author: Öö Tiib

subject: Re: Remove space from input

text:
On Saturday, 16 March 2013 20:53:59 UTC+2, eli m  wrote:

You 'find_first_of' space and then 'erase' it until there are none.


subject: Re: Remove space from input

text:
Just use >> on strings, and then concatenate them.
Can you explain in more detail please?


author: Andy Champ

subject: Re: Remove space from input

text:
On 17/03/2013 18:12, eli m wrote:
If you read strings from your input stream using operator>> the
whitespace between the strings is not included in the strings.

If you then join the strings together you will have removed the whitespace.

"abc      def     ghi" becomes the three strings "abc" "def" "ghi" which
when concatenated are "abcdefghi"

Andy


author: Jeanette

subject: Network question (file transfer)

text:
Could anybody help me with the following problem?

We have two pc's at our home: a 486DX2 with a 14k4 modem and a 386SX
with a  slow 2400 baud modem.

We'd like to connect the 2 pc's, so that Eudora/Agent files can be
downloaded by the fast computer and transferred to the other computer,
and vice versa.

We now have a serial link-cable between the 2, but apparently that's
not enough. We need some software, I guess, but which?

We did try to copy the files manually from one comuter to the other,
i.e. downloaded mail files from Eudora, and then copied the in.toc and
mbx. files on a floppy disk and loaded that in the other computer.
Same thing with Agent newsarticles (idx. and dat. files) but it does
not seem to work. Neither the mail, nor newsgroup files appear in the
other computer.

Does anybody know a solution for these problems? Either one will do.
I mean, if this connection between the 2 pc's doesn't give us access
to each others pc, then it would be nice to be able to work with
floppies.

Any advice on will be greatly appreciated! If you can help, please
post reply to our email address.

Thanks

Jeanette


author: JDS

subject: Palm Tungsten E and Battery Question?

text:
I own a 3ish year old.  Seems lately like battery charges disappear a lot
faster than they used to.  I charge with USB PC cable and/or AC adapter.

Dos the battery deteriorate in time?  Can I replace it?  Do-it-yourself or
Palm mail in or?


author: Iguana

subject: Re: Palm Tungsten E and Battery Question?

text:
JDS wrote:

Yes. For Li-ion & Li-polymer batteries it doesn't matter so much if you
use them or not, they deteriorate in time, capacity drops in some
percentage.

Only if you are skilled with small screwdrivers, soldering iron and
such. You need to be VERY carefull when opening the TE's case not to
break plastic clips or not to scratch the edges of the case.

Probably some 3rd party services do that, too. Decision is yours, based
on your skill and experience. You have a few web sites selling the
batteries, and some of them have instructions online with photos how to
take apart PDA's and exchange the batteries.

Take a look here for Palm TE:
http://www.gethightech.com/Merchant2/merchant.mv?Screen=CTGY&Store_Code=GHT&Category_Code=_TungEBat

Or here for Palm TT family:
http://www.gethightech.com/Merchant2/merchant.mv?Screen=CTGY&Store_Code=GHT&Category_Code=_tungsten_takeapart


author: Guy Bannis

text:
In article <43c4002a$0$3036$[email]>,
 "JDS" <[email]> wrote:

Try an "In-Cradle" Reset

An in-cradle reset will reset the charging circuitry in a rechargeable
device. This is helpful if your device turns off as soon as you turn it
on, or if it doesn't seem to be charging when you connect it to a power
source.
The charger can be any type of cradle or cable that charges your device.
The important bit is to make sure the power adapter is plugged in and
supplying power to your device during the reset.

   1. Connect your device securely to its charging cradle or cable, and
connect the cradle/cable to a power source.
   2. Use an unfolded paper clip, or the reset tool at the tip of your
stylus.
   3. Gently press the RESET button inside the hole on the back panel of
your device (where's the reset hole?).
   4. All data on your device should be retained. If you do lose data
after a soft reset, you may have a more serious issue with your hardware
that requires a repair.
   5. After a soft reset, a logo screen appears, followed shortly by a
Preferences screen asking you to set time and date.

Other suggestions from Palm at:
http://kb.palmone.com/SRVS/CGI-BIN/WEBCGI.EXE?New,Kb=PalmSupportKB,ts=Pal
m_External2001,Case=obj(887)#incradle


text:
In article <drt8jq$9vl$[email]>,
 Iguana <Iguana^[email]> wrote:

Before you worry about that, have you tried an "in-cradle hard reset"?

http://kb.palmone.com/SRVS/CGI-BIN/WEBCGI.EXE?New,Kb=PalmSupportKB,ts=Pal
m_External2001,Case=obj(887)


text:
Thanks.

Done.  I assume using the USB  to PC cable connection would suffice?
Battery reads 100% now.  I'll see what the depletion timing is - better or
same.

Device did not have a turn off right away problem and it did seem to charge
when connected (lightning bolt) but it sure has been draining fast.

JDS

"Guy Bannis" <[email]> wrote in message
news:[email]...
lot
or


text:
In article <43c41ea3$0$32504$[email]>,
 "JDS" <[email]> wrote:

(snip)

I'd do the in-cradle reset with the AC adapter. The unit should recharge
much more quickly than through USB.


author: Dennis Mews

subject: RiscPC battery

text:
Every time I switch on my (newly awakened) RiscPC, the clock
is about 4 hours slow. Is there a battery somewhere?


author: druck

subject: Re: RiscPC battery

text:
On 15 May 2005 Dennis Mews <[email]> wrote:

Its a rechargeable battery, which may fail eventually. If it hasn't been used
for a while, try leaving the machine on for 24 hours to make sure it is fully
charged, and then see what the accuracy is.

---druck


author: Dave Plowman (News

subject: Re: RiscPC battery

text:
In article <[email]>,
   druck <[email]> wrote:

They are remarkably long lived. I've got two RPCs - one used every day and
one only once in a while and neither - despite the oldest being some 7
years old - has needed the battery replaced.


subject: Re: RiscPC battery

text:
In message <[email]>
          druck <[email]> wrote:

Thanks Dave, that seems to have fixed it.


author: Simon Challands

subject: Re: RiscPC battery

text:
In message <[email]>
          "Dave Plowman (News)" <[email]> wrote:

Wonder what the previous owner of mine had done to it, then. It was going
when I got the machine about 5 or 6 years ago (i.e. clock would reset, but
most CMOS settings stayed). The replacement is one of my two bits of
soldering on the motherboard; I'm amazed it still works.


author: Shahram Najm @ ETC

subject: [Q] re rexec

text:
Can someone please tell me why the network function 'rexec' sends
the plaintext password and not the encrypted one?

This is a question posed by Stevens in his network prog book.

Thank v much in adv.

_________________________________________________________________
Shahram Najm                          [email]
Mentor Graphics Corporation (UK)      Tel:   +44 344 867555 x2271
BRACKNELL, Berkshire, England.         #include <std.disclaimer>
_________________________________________________________________


author: Barry Margolin

subject: Re: [Q] re rexec

text:
In article <[email]> [email] writes:

Unless the client and server machines use the same passwd file (either they
share an NIS server or passwd files are automatically copied between them)
the user's password is likely to be encrypted with different salts on the
two machines.  In this case, the encrypted passwords won't match, so it
won't be possible to verify the password.

Also, it doesn't increase security much to send the encrypted password.  If
someone captures the packet with the password, he just has to resend
whatever he captured in order to masquerade as you.  At best, it would mean
that the user could only get in via rexec, since he still wouldn't know a
paintext password to supply to an interactive login.


author: Michael Salmon

subject: Re: [Q] re rexec

text:
In article <[email]>
[email] (Shahram Najm @ ETC) writes:
|> Can someone please tell me why the network function 'rexec' sends
|> the plaintext password and not the encrypted one?

The encrypted password is (in most systems) globally readable hence if
you allow encrypted passwords in you protocol then all that is required
is for someone to read the passwd file, find the entry for root and use
that in his rexec call. Even generating the encrypted password requires
a salt which is stored in the passwd file and hence probably not
available (after all thats why NIS exists). Encryption is probably a
good idea but then you need to have an RSA type scheme to be effective.


author: Marcus J. Ranum

subject: Re: [Q] re rexec

text:
[email] writes:

	Because the rexec protocol was designed by someone who
didn't care about security.

mjr.


author: Vernon Schryver

subject: Re: [Q] re rexec

text:
In article <[email]> [email] writes:

Easy.  It's the same reason the passwords for the vastly more common
telnet and rlogin are in the clear:  Encrypted by which algorithm?  Using
what key?  How is that key distributed?  What about having to pay Public
Key Partners royalties for using the now obvious solutions?  What about
getting permission from the U.S. government to ship the resulting system
out of the U.S.?

Some of those nontrivial questions are why there are things like Kerberos.

Look in sci.crypt where those issues are discussed endlessly.

You obviously couldn't just send the second field of a UNIX /etc/passwd,
and expect any system to think that means you know any authenticating
secrets.

Vernon Schryver    [email]


author: [redacted]

subject: Re: [Q] re rexec

text:
In article <26nd05$[email]> [email] (Marcus J. Ranum) writes:

Remind me never to buy a secure system from you.  Since the poster
refers to 'the' encrypted password, he can only mean one thing -
the one-way encrypted password that Unix does the comparison on.
The reason this is not used by rexec is obvious - because to get
the plaintext password you have to snoop it off the wire, while to
get the encrypted one you just read it out of /etc/password.
Don't lose sight of the wood for the trees eh?


author: marco sala

subject: continue to read from file

text:
Hi

I have a little problem. For my degree thesis I have to read a file which contains floating numbers. The size is huge (like ~1 GB) so Matlab can't read in a variable all of the number

my file it's like this

 -9
 -8
 -7
 -6
 *********************
 1.00000020
 2.00000000
 3.00000000
 4.00000000
 *********************
 5.00000000
 6.00000000
 7.00000000
 8.00000000
 *********************
 0.00000000
 0.00000200
 0.00000020
 0.00000020
 *********************
 0.00000000
 0.00000200
 0.00000020
 0.00000020
 *********************
 0.00000000
 0.00000200
 0.00000020
 0.00000020
 *********************
 9.00000000
 10.00000000
 11.00000000
 12.00000000
 *********************

I have 4 elements then ****** then 4 elements ect...

There is a command that can read the first 4 elements then position in the other 4 and go on like this?

I try fscanf textread but no one work!

thanks


author: Sebastiaan

subject: Re: continue to read from file

text:
I find it hard to beleive that you cannot store the contents of a 1GB text-file in your memory if you do it properly. This is a very simple, but robuust program that reads all the numbers of a file, and ignores all non-numbers (and assumes in this case that you have a multiple of 4 amount of numbers):

fid = fopen('testfile.txt','r');

% Reserve memory
A = zeros(100,1);

Index = 0;
tline = fgetl(fid);
while ischar(tline)
    number = str2double(tline);
    if ~isnan(number)
        Index = Index + 1;
        A(Index) = strread(tline, '%f');
    end
    tline = fgetl(fid);
end

fclose(fid);
A = A(1:Index);
A = reshape(A, 4, Index/4);
disp(A)

If it is slow, increase the allocation for A.

Sebastiaan


author: dpb

subject: Re: continue to read from file

text:
marco sala wrote:
...
...
...

try textscan instead--it's 'commentstyle' parameter allows to specify a
comment character (and why they didn't upgrade textread at the same time
is beyond me... :( )...


author: Steven Lord

subject: Re: continue to read from file

text:
"dpb" <[email]> wrote in message
news:havb3r$fcj$[email]...

The first note on the reference page for TEXTREAD may explain it:

http://www.mathworks.com/access/helpdesk/help/techdoc/ref/textread.html

"textread is not recommended.  Use textscan to read data from a text file."


subject: Re: continue to read from file

text:
Steven Lord wrote:
...

??? Undefined function or variable 'textscan'.

may explain _my_ frustration... :(


subject: Re: continue to read from file

text:
dpb wrote:

...since it would seem to have been trivial given other specific
single-character comments were supported and it was an enhancement I'd
suggested/asked for several well over 10 years ago now while still
working and had wherewithal to afford support...


author: Donald Mullican

subject: Bell sound when pressing enter in a TEdit field

text:
Every time I press enter in this field I get this aggravating bell sound.
I've searched through the associated code, and don't see anything that
should be causing it. Anyone seen this before? Any ideas how to stop it?

Thanks,
   Donald Mullican


author: Dave Krajcar

subject: Re: Bell sound when pressing enter in a TEdit field

text:
I used to have a similar problem in many apps, not just delphi ones.  My son
helped me stumble onto the solution....If I brougth up the audio properties
windows dialog box and muted the microphone input device, the sounds went
away. Not sure why, but glad they are gone!
-D
"Donald Mullican" <[email]> wrote in message
news:G7Sv7.109845$[email]...


author: Carlo Kok

text:
"Donald Mullican" <[email]> wrote in message
news:G7Sv7.109845$[email]...

On keypress event:

if key=#13 then key := #0;


author: Mean Mr Mustard

subject: Are Apple Notebooks Made in the USA ?

text:
I am looking to purchase a new notebook computer and would prefer an
Apple system due to the superior architecture, reliability and
service.  However, I am also opposed to outsourcing and will not buy
anything made outside the US and Canada unless it is impossible find
otherwise.  Now I haven't been able to confirm where Apple has these
notebooks produced, but a brief search on Google hinted at Made in
China.

Is this the case? If so, I will pass on Apple and just go with a Dell
inorder to save a few bucks.


author: Jim Nason

subject: Re: Are Apple Notebooks Made in the USA ?

text:
On 2004-09-02 21:42:38 -0400, [email] (Mean Mr Mustard) said:

Good luck finding a laptop or any computer wholly made in the US.  If
and when you find one, let us know.   I am sure you will find parts
made in the US and final assembly may be done hear.  I havent' seen a
hard drive manufacutred in the US in 7 or 8 years for example.

Jim


author: Paul Frankenstein

text:
In article <[email]>,
Mean Mr Mustard <[email]> wrote:
* I am looking to purchase a new notebook computer and would prefer an
* Apple system due to the superior architecture, reliability and
* service.  However, I am also opposed to outsourcing and will not buy
* anything made outside the US and Canada unless it is impossible find
* otherwise.  Now I haven't been able to confirm where Apple has these
* notebooks produced, but a brief search on Google hinted at Made in
* China.
*
* Is this the case? If so, I will pass on Apple and just go with a Dell
* inorder to save a few bucks.

Nice attempted troll. For the record, the Dell laptop I bought a few weeks
ago was made in Malaysia. I'm not sure that ANYONE makes laptops in the US
anymore.

p


author: Edward J. Neth

text:
Apple notebooks are made by Quanta and Compal, which are two of Dell's
biggest suppliers.
My iBook came from Taiwan;  a brand-new Dell D800, from Malaysia, by way of
Compal, which also makes the wide-screen Apple PowerBooks for Apple.

"Mean Mr Mustard" <[email]> wrote in message
news:[email]...


author: Ogden Johnson III

text:
[email] (Mean Mr Mustard) wrote:

Trolling, trolling, trolling on the bounding main ...

Go away, troll.  The inclusion of misc.survivalisim in your
cross-posted newsgroups shows that this is not a serious inquiry,
but just a troll to start a flame war.


author: Gnarlodious

text:
Entity Mean Mr Mustard spoke thus:

No, Taiwan.

Hope you enjoy your new Apple laptop! Although you could still argue that
Taiwan is part of China...


author: AnToNio

text:
Mean Mr Mustard <[email]> wrote:

Do you really think that you can find any product that is not at least
partly and more often fully made outside the US????

You're really a very naive American!


author: Ian Stirling

text:
In misc.survivalism Mean Mr Mustard <[email]> wrote:

You will have to search really, really, really hard to find any
item of electronics with components solely from the USA.
Not only things like semiconductors are mostly made in asia, but
LCD panels, and many passive components.
To such an extent that I would be astounded if any laptop available
in the US is not built with a sizable fraction of imported components.
I would be utterly astonished if someone had gone to the herculean
lengths needed to US source everything, as, for example, AIUI, the US
does not really make notebook LCDs at the moment.


author: Eugene

text:
Paul Frankenstein wrote:

Of course it all depends on how you define "made"
I've forgotten the legal terms now, but you can have parts made all over the
world and shipped here and then assembled and call it made in the USA.

Working for a reseller for a few years we saw a high number of failures of
Apple gear, higher than Compaq, HP, IBM (didn't sell/service Dell since
they deal direct)


author: Georg Schwarz

text:
Gnarlodious <[email]> wrote:

aka ROC, which happens to stand for Republic of China.

anyone claiming differently should check their history or geography
books.


author: Steve Hix

text:
In article <[email]>,
 [email] (Georg Schwarz) wrote:

How about asking residents of Taiwan.

*They* don't seem to think they belong to to PRC.


author: Matthew Russotto

text:
In article <[email]>,
Georg Schwarz <[email]> wrote:

My AlBook was assembled in Shanghai (People's Republic of China),
which sidesteps that quite nicely.

History and current events shows that Taiwan and China don't share a
government, which means that politically, one is not part of the
other, despite the rather odd diplomatic fictions the two maintain.

Geography shows that Taiwan is an island.


author: Wes Groleau

text:
Steve Hix wrote:

But they _do_ like to say they are Chinese.


text:
In article <[email]>,
 Wes Groleau <[email]> wrote:

They are.


author: SG

subject: Re: Amiga NewsReaders (was Re: Internet Explorer?)

text:
"Karl Thomas" wrote:

Like I said, the an 060 beats that Mac 603e in the CPU test, if you
had a clue you'd know thats an integer test, not FPU.  My 060
severely trounces your PowerMac 6100/60 (the 060 being an
insignificant 45% faster) in the same benchmark.  4.54 to 3.13.

And I've already pointed out the plainly bogus speeddoubler claims,
saying it allows (RISC) PowerMacs emulate (CISC) 68K at one for one
speeds.  A miracle product if there ever was one, since CISC
instructions are generally more complex than RISC instructions, hence
the name.  H&P knows better than to insult the Amiga user base with
such claims, their 1:3 claim is entirely believable, and born out by
experience.

Funny, I've never heard you claim that PMacs can emulate CISC x86 at
one for one speeds?  Ever wonder why not?  Maybe because its a silly
notion?

Is that right?  Do you actually know something I don't?  Doubtful.

http://blittersoft.com/cgi-bin/2/webc.cgi/~bsoft/Fusion_PPC.html?sid=9XNHV6OCoK3YBX5

You'd better hope it gets cancelled, because upon release, the entire
Mac platform will become a perfectly preemptively multitasking little
window under a far more advanced OS.  Its already happened once, so
it shouldn't be too much of an adjustment for you the second time.
Ooops, twice actually, I forgot about Be.

-Steve.


author: Paul

subject: Simple code doens't work

text:
The following code gives this message:
Compile error:
Sub or function not defined
I know its something simple to fix but can't think what.  Does something
need referencing?

Private Sub cmdWebSite_Click()
    Dim strWebSite
    strWebSite = ShellExecute(Me.hWnd, "Open", "http://www.homepage.com",
"", App.Path, 1)
End Sub

Thanks
Paul


author: Dale Atkin

subject: Re: Simple code doens't work

text:
Have you defined the sub or function :)

Public Declare Function ShellExecute Lib "shell32.dll" Alias "ShellExecuteA"
(ByVal hwnd As Long, ByVal lpOperation As String, ByVal lpFile As String,
ByVal lpParameters As String, ByVal lpDirectory As String, ByVal nShowCmd As
Long) As Long

Dale


author: Tom Shelton

subject: Re: Simple code doens't work

text:
"Paul" <[email]> wrote in message
news:agcq8e$i4$[email]...

Can you show your declare for the ShellExecute API call?

Tom Shelton


author: Veign

subject: Re: Simple code doens't work

text:
One thing (good practice) is to declare your variable as an explicit
variable type;
Dim strWebSite as String

And
Do you declare the ShellExecute API?? Like;
Private Declare Function ShellExecute Lib "shell32.dll" Alias
"ShellExecuteA" (ByVal hwnd As Long, ByVal lpOperation As String, ByVal
lpFile As String, ByVal lpParameters As String, ByVal lpDirectory As String,
ByVal nShowCmd As Long) As Long


author: Doug Ross

subject: Re: Simple code doens't work

text:
ShellExecute isn't built in to VB, it's an API function in shell32.dll.  You
need the declare in the declarations section of the form or [class] module:

Public Declare Function ShellExecute Lib "shell32.dll" Alias "ShellExecuteA"
(ByVal hWnd As Long, ByVal lpOperation As String, ByVal lpFile As String,
ByVal lpParameters As String, ByVal lpDirectory As String, ByVal nShowCmd As
Long) As Long

Also, I recommend using SW_SHOWDEFAULT for the last parameter.  This way the
browser shows up as the user left it.

Public Const SW_SHOWDEFAULT As Long = 10&

You also don't need App.Path in there, and the function does not return a
string, it returns a Long error code.  Try this:

Call ShellExecute(Me.hWnd, "open", "http://www.homepage.com", vbNullString,
vbNullString, SW_SHOWDEFAULT)

or, if you really care:

Dim lRet As Long
lRet = ShellExecute(...)
If (lRet...) Then
End If

"Paul" <[email]> wrote in message
news:agcq8e$i4$[email]...


subject: Re: Simple code doens't work

text:
oops!
i did declare the API but commented it out for some reason!
all works now!

thanks
paul

"Veign" <[email]> wrote in message
news:uCnoOvrJCHA.3980@tkmsftngp10...
String,
"http://www.homepage.com",


author: Nick Palmius

subject: Re: Simple code doens't work

text:
"Doug Ross" <4@2.0> wrote in message news:wCmW8.1200$f5.71755@news...
You
module:
"ShellExecuteA"
As
the
vbNullString,

If lRet > 32 Then
    'Error
    'FYI

Kind Regards
   Nick Palmius


author: Ernesto Aides

subject: TEXT control

text:
Inside a process, I need to take all controls and put them in other
position... I can do it with loop i#  = firstfield() to lastfield()...
this works fine.
In addition, I need to know a type of the Control (i#), if the control is
TEXT, I need to put the attrib right...
how i can know that inside the loop ?

T.I.A.

Ernesto Aides
Ashdod - Israel


author: Angel L. Bermudez

subject: Re: TEXT control

text:
Ernesto, see below

angel

"Ernesto Aides" <[email]> wrote in message
news:[email]...

If you mean move a control to another possition on the screen,
Yes you can do this. Prop:sPos and Prop:yPos can be changed in a loop.

I do not undertstand what you are adking here..


author: Simon Burrows

subject: Re: TEXT control

text:
Hi Ernesto

loop i#  = firstfield() to lastfield()
  if i#{Prop:Type} = Create:Text
    i#{Prop:Right} = true
  end
end