What, exactly, is the Swedish Academy? Or rather – what was it?
Until 12 April, the academy, which chooses the winners of the Nobel prize for literature, was a royal academy founded in 1786 by the so-called “theatre king”, Gustav III.
But after its head, the permanent secretary Sara Danius, was ousted that day, and with only 11 of its 18 members left, the institution has nearly ceased to exist, brought down by allegations of sexual abuse, in-fighting and subterfuge. It is almost Shakespearean.
An editorial in Dagens Nyheter, the biggest-selling Swedish daily paper, compared the tragedy in the country’s most prestigious cultural organ with the final scenes of Hamlet. Unscrupulous duels with poisonous swords, poison-smeared goblets, everyone dies. Perhaps Fortinbras will march on stage – disguised as the current Swedish king, Carl XVI Gustaf – to deliver the final lines that look to a hopeful future. What has happened in the normally peaceful kingdom of Sweden?
It started with a number of women who came forward to a Dagens Nyheter reporter, Matilda Gustavsson, last November. They spoke of harassment and sexual abuse, allegedly committed by Jean-Claude Arnault, the husband of academy member Katarina Frostenson. In some cases, the abuse was said to have taken place in apartments belonging to the academy. Arnault’s strategy, the women claimed, had been to use his close relationship with the institution, which also funded a club called the Forum that he co-owns with Frostenson. He denies all the allegations.
Dagens Nyheter’s coverage shook Sweden’s cultural world. State prosecutors opened an investigation, and they say that, while some allegations are not being considered because of Sweden’s statute of limitations or lack of evidence, the investigation is ongoing. The academy hired a law firm to investigate its links to Arnault (who is referred to as “the cultural profile” in Swedish media).
The maelstrom has hurt not only the Swedish Academy, but also the only thing that really gives the organisation its glory: the Nobel prize for literature.
The academy’s investigators reportedly said that “the cultural profile” had leaked the names of seven prize-winners – something Arnault’s lawyers have denied. In a blunt statement, the Swedish Nobel Foundation wiped away any remaining confidence in the academy, saying it had been “seriously damaged” and raising concerns that the prize’s reputation may be tarnished.
The law firm’s investigation also allegedly recommended that the Swedish Academy should file a police report to allow the authorities to investigate suspicions of financial irregularities, but the institution has reportedly refused to do so, revealing splits within the committee.
Danius announced she was leaving, following several members who had already gone. A remaining academician called some of them “sore losers”.
Members of the Swedish Academy were once referred to as “the 18 best and brightest” – mirroring the popular belief that they represented the highest standards among poets, writers and intellectuals. Today, there are only 11 left and public support for Danius is huge, while confidence in the remaining members is at rock bottom. It seems a dark and cruel irony that a man has been accused of sexual misconduct, but a woman has taken the fall.
What now? Ironically, the only remaining hope seems to be that the Swedish king will enter the stage like a deus ex machina. He has already made his intentions clear: to change the academy’s statutes so that members can resign properly if they wish to do so. At the moment, the only possible ways out are exclusion or death.
Such a change would been seen as severe punishment. The academy’s lifelong membership has enabled some to maintain a mythologised self-image. They have been able to say and do anything without repercussion. If the king removes their status, the magic surrounding the demi-gods of Parnassus would disappear and they would be transformed into the flawed and mortal members of a dull committee.
What happened on 12 April is of historic importance. The origin of this collapse is the women’s allegations of sexual misconduct, with echoes of the New York Times revelations about Harvey Weinstein which launched the #MeToo movement. Their allegations have brought one of the world’s most renowned cultural institutions to ruin.
The disenchantment, today, is total.
Björn Wiman is culture editor of the Swedish newspaper Dagens Nyheter


A RESOLUTION on marriages of convenience was also agreed. Ministers said they would try to ensure the key elements of the non-binding accord were transposed into national law before 1 January 1999.
OPPOSITION from Spain prevented agreement on an EU-wide definition of ‘organised crime’. Madrid felt the text provided too limited a definition. This was a set-back to the EU’s battle against cross-border crime, with governments failing to meet a deadline to agree a definition before the end of the year. Luxembourg Justice Minister Marc Fischbach expressed his disappointment, saying: “We have to come up with a common definition if we want to fight against organised crime.”
MINISTERS discussed plans to draw up an EU-wide convention on driving offences. The aim would be to prevent motorists who had been banned from driving in a member state other than their own from retaining their driving licences. Problems arose over whether the home state could implement and in some cases increase penalties imposed abroad. Ministers agreed that they would try to resolve these difficulties as soon as possible.
THE Council reached political agreement on allowing the fledgling police agency Europol to gather information on the illegal trade in child pornography.


text:
GST No: 10-665-485
Selected stories from one of New Zealand's most well known authors, Ian Wedde. Largely written in the years between 1970 and 1980, the collection includes the award winning Dick Seddon's Great Dive.
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Copyright 2017 Victoria University Press.

domain: library


text:
Your house is not a very simple building made from stone and cement. It is a location where you share your pleasure and feelings together with your loved ones. Lots of men and women believe it as a fantastic investment to invest for house remodeling. It may add great value to your house, while enhancing the look too. Kitchen remodeling, bathroom remodeling, flooring, roofing and painting are some of the remodeling jobs that may increase your home's value. These jobs are complicated jobs, so choosing a home remodeling contractor is unavoidable. Deciding on the correct contractor can help you get your house improvement remodeling work done with wonderful ease.
Hiring home remodeling professionals can add to the initial cost of this project, but it can save a lot of stress and money in the long run. They can have vast experience, which can help you find many pitfalls. It's however critical to discover a highly qualified builder, who will supply the ideal remodeling services. It is possible to ask for referrals from the friends and family, to be able to decide on the best contractor.
An seasoned professional relieves you from the strain of home remodeling process to a excellent extent. Home remodeling is a totally organized work requiring a lot of imagination. An unorganized remodeling work might double your cost, time and effort. A trusted contractor accomplishes the job properly and finishes it on time.
The contractor first creates a sketch of the remodeling work and gets the approval. If you wish to remodel your toilet, the contractor provides you a few layouts. You are able to opt for the style that is appropriate for your budget and preference. The builder employs various professionals such as interior designers, painters etc to transform your old bathroom into a stylish one.
If you want to create a unique appearance to your house, you can then employ a house remodeling contractor that allows you to select custom cabinetry, doors and windows. But, it may drive up the cost of your renovation project. If you wish to conserve money, but like to make a splendid look, you are able to decide on an experienced builder that offers many different standard and semi custom made choices.
You may opt for the products that match your wallet then ask the builder to include embellishments to get the personalized appearance.

domain: design


text:
Considering how much of our country’s government revolves around voting and elections, everyone should vote because they all have an opinion. In American democracy, we respect our right to choose who’s in office and revel in the fact that we have a say in what’s going on in the political world.
It makes sense for all Americans, including high school seniors, to go and vote for the upcoming elections. However, some seniors aren’t 18 yet and they can’t register to vote.
As seniors who will be graduating soon, as well as becoming young adults, voting is very important to us because our voices matter. We can bring change to our government by using our voices.
Cindy Lean, currently a student at Edison said, “If I had the chance then I would take it because I would like to avoid having a President like Trump who doesn’t think twice before saying something. The fact that he uttered the words ‘Chinese Virus’ was irresponsible and immature. It fueled a lot of racism towards the Chinese population. To avoid having a President like this, I wouldn’t let go of the chance to vote if I ever get it. Although I wanted to vote, but wasn’t able to; my desire to vote wasn’t as strong as it is now. ”
Students like Cindy are very upset that they aren’t able to vote and feel hopeless with our current President. “When my classmates were able to register to vote I honestly wasn’t particularly bothered about it because although I wasn’t given the opportunity to, I found myself supporting the same person as my classmates did. However, at the same time, I did wish that I could be counted to offer my support to this candidate who I wanted as a future President,” Lean said.
Another student of Edison, Armando Gomez revealed, “Not being able to vote does affect me as an American citizen as it is my right. The right for American citizens to decide for themselves, the future of the United States is what the founding fathers fought for.”
There are so many Americans who can go out and vote, however they choose to stay home. Some so many young students would like to vote, but can’t because of their age or because they had difficulties registering. It is unsettling to see Americans who get a say in who takes office in their government not voting.
“I don’t hold anything against them but do believe they should take at least some consideration in doing so. It is our responsibility to be aware of what is going on in our nation and be well informed to decide to improve upon our nation,” said Gomez.
“Not being able to vote affects me as an American citizen because we are currently stuck with President Trump who has made many decisions that I considered wrong. I was always against the idea of him becoming President due to his actions and the way he does things. To at least have a possibility of electing a president that I believe is fit to run this country I feel like voting is essential which is why this affected me as an American citizen. The fact that I can’t vote means I can’t put my approval to a person who I want as president and the possibility of having a president who I don’t agree with is increasingly higher,” Cindy Lean said.
As Americans, it is our right to vote and it is a very important part of us. Even though many Americans don’t want to go out and vote, graduating seniors are very eager to take their place. It is just upsetting they aren’t able to do so because of not being of age as well as having difficulty registering to vote.

domain: sociology


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Activity: Academic Talks or Presentations › Oral presentation › Research
This panel proposes to address questions concerning the familiar practices and concepts of citizenship raised by increased migration from South Asia to Australia, with reference to their current research in diaspora studies and readings of Asian Australian literature. Referring to the inadequacies and limitations of the state centred distribution paradigm of Australian citizenship that transnationalism and the Asian diaspora in Australia have exposed, and to the seemingly more inclusive concept of multi-cultural citizenship, the panelists will discuss literary representations of tensions within citizenship that might have effects on legal interpretations and categories, noting as case studies particular challenges to or questionings of the practices and policies of citizenship. Issues that may be covered include grievances caused by national exclusions, the status of refugees and statelessness, neo-racist hostility, the restrictions of immigration law, the socio-economic integration of migrants. The approach will be interdisciplinary and will draw on the well established intersection between legal and literary studies insofar as these interface with Citizenship Studies, in focusing on how literary representations can point to the re/framing of questions of citizenship in relation to legal frameworks.
27 Jan 2017
European Association for Studies of Australia Conference: Australia-South Asia: Contestations and Remonstrances

domain: literature


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Thursday, August 09, 2012
When democracy and ethics conflict ...
It happens surprisingly often that rules designed to prevent corruption can, if applied too legalistically and without common sense, seriously interfere with the normal functioning of democracy.
The "predetermination rule" which the government has just rightly scrapped, was designed to make sure that councillors who had to make a decision on an issue attempted to keep an open mind in advance of the vote.
The problem was that it all too often meant that a candidate for election as a councillor who tried to be honest with his or her voters about a key issue in the ward risked finding if elected that the council solicitor told him or her not to attend or vote at the meeting where that issue will be decided because those comments have "prejudged" the issue.
Another good example was the "Standards Board" system of local government ethics which the present government rightly scrapped earlier this year.
The problem with it was that a system designed to prevent councillors from abusing their position to enrich themselves or their families and friends had grown into a frankenstein monster which regularly prevented councillors from putting forward the cases they had been elected to support and which their electorates wanted them to support.
I have previously listed some of the cases where this happened on this blog but here are a couple:
In November 2005, some 26 members of Cumbria County council were advised to withdraw from a debate about nuclear issues. The legal advice was that not just councillors who themselves work at Sellafield or had close relatives who do, but any councillor who even had a friend who works at Sellafield might be “prejudiced.” As Tim Knowles, a Labour councillor, rightly pointed out, “Virtually everybody in West Cumbria has a friend working at Sellafield.” And “West Cumbria needs to be represented on what is a key issue for its wellbeing.”
As I wrote myself at the time, those of us who live in a community where 17,000 jobs depend directly or indirectly on civil nuclear power, might well be influenced in our views on nuclear issues. But isn’t that exactly the sort of interest which democracy is supposed to reflect ?
Similarly when there was a proposal in to build hundreds of houses on a former school playing field in St Albans, which was a matter of intense interest in the ward concerned, the most recently-elected councillor for the ward was advised by the solicitor to the council not to attend the meeting at which the planning application was to be determined because she was also secretary of the local residents' association which was campaigning against the plans.
Thanks to the present government's reforms neither of these problems would happen today, but this week we have another example of a clash between democracy and principles designed to prevent a conflict of interest.
There have been rules for centuries designed to limit the participation in politics of serving judges and police officers. There are good reasons for these rules, but they nevertheless represent a serioius check on the democratic rights of the individuals affected. Society should think carefully before extending those limits - by, for instance adding magistrates to the list of people affected - which in my opinion ought to be the reponsibility of the legislature and not the judiciary.
That view is apparently not shared by one of the most senior judges in England and Wales, who has put the cat among the pigeons with an unexpected ruling that sitting Justices of the Peace cannot put their names forward to be Police and Crime commissioners unless they resign as magistrates.
For thirty years, until very recently, magistrates have formed a significant part of the existing Police Authorities whose powers the Police and Crime Commissioners will take over when they are elected on 15th November.
Admittedly, there are people who have argued against this because they believe that the relationship between the police and magistrates should not be too close. The counter argument was that the experience of magistrates was relevant to the functioning of the police authorities and that magistrates therefore brought useful knowledge to those bodies.
Similarly the experience of having served as a magistrate could be very relevant to someone's ability to do the job of Police and Crime Commissioner, and the electorate, should be able to pick such people for the job.
When parliament passed the law under which Police and Crime Commissioners will be established, they carefully specified various groups of office-holders who will not be eligible to stand for the post without resigning their current positions, and magistrates were not among them. That, most people would have expected, made the position clear. But the Senior Presiding Judge for England and Wales, the Rt. Hon Lord Justice Goldring, has ruled otherwise, issuing a circular which demands that “Magistrates who wish to stand for election, upon announcement of their intention to do so, should resign immediately.”
Sam Chapman wrote in his excellent blog, Top of the Cops that
"Judges are disqualified from being elected as PCCs, but the law does not prevent Magistrates from standing, so Lord Justice Goldring has decided that he will stop them from standing."
This looks perilously close to deciding to implement the law which he thinks parliament should have passed rather than the act which has actually been put on the statute book. As Sam continues, Lord Justice Goldring's view about a non-political judiciary "seems so extreme as to in itself constitute a political statement."
Incidentally this will not affect the situation in Cumbria where, although the Conservative candidate to be Police and Crime Commissioner served as a JP for many years, most recently in Barrow, he has already stepped down from that office.

domain: news


LEWISTON - On Monday, January 23, 2023 at approximately 11:01 a.m., fire crews responded to the 0100 block of 24th Street in East Lewiston for a structure fire.
According to a press release from the Lewiston Fire Department, initial reports to 911 stated that an explosion was heard and that there was a house on fire. While enroute, crews could see a large column of black smoke coming from the area.
Fire units arrived on scene within four minutes of dispatch and found the single-story home to be fully engulfed. After being advised that everyone was out of the home, fire crews fought the fire from the outside with large hose lines. Because of the large amount of fire, crews had to call in a backhoe from the city street department to assist with spreading out debris outside the home and assisting crews with opening up a portion of the home so the fire could be knocked down.
One occupant of the home was burned and was treated by paramedics on scene before being transported to a local hospital.
According to the release from the LFD, due to the amount of damage, the structure and its contents are considered a total loss. The fire cause of the fire is being listed as undetermined.
A total of 26 personnel responded to the fire which included the Lewiston Fire Department, Clarkston Fire Department and Clearwater Paper Fire Department. Off duty personnel were also called back to the stations for additional staffing and they responded to 4 emergencies while crews were fighting the fire.
The Red Cross was called in to assist those who were living in the home.


Catalytic converters are drivers that transform the hazardous exhausts that are produced by an interior burning engine right into far less hazardous and ozone-friendly fumes. They were commonly embraced in America in 1975 after the EPA applied a variety of policies governing the fuel performance as well as emissions criteria for cars and trucks and also trucks. Catalytic converters are often found on all sorts of engines today, from lawnmowers to forklifts to buses and also trains. A catalytic converters main task is to turn carbon monoxide gas, nitrogen oxides, and also unburnt hydrocarbons right into carbon dioxide, nitrogen, oxygen, and also WATER. Felines work best when they are hot, with an reliable operating temperature level of 750 ° Celsius ( regarding 1400 ° Fahrenheit).
Although the heat is what causes them to function efficiently, it is additionally what triggers their death. Catalytic converters can also get blocked gradually, which will eventually injure the performance of your lorry. It is not unusual to change one or several felines on vehicles that are ten years old or older. There are 2 kinds you can get: global fit or direct-fit replacement. Universal fit catalytic converters come in a selection of dimensions and also are intended to be welded into location. Direct-fit catalytic converters are nearly the same, with the exception that these cat’s are intended to be bolted right into location. To make clear, the direct-fit catalytic converters replace an whole area of the exhaust system, which means that it was made specifically for your vehicle, versus the universal fit catalytic converters which are created to be produced and also bonded into place. So while the universal fit catalytic converters are occasionally less expensive, the direct-fit catalytic converters will be less complicated to mount.
Over the last 4 years, Mazda has actually been toiling in their secret research laboratories. They have actually managed to establish a brand-new sort of catalytic converter that utilizes 70-90% much less platinum, rhodium and also palladium in the building and construction of their cats. These rare-earth elements are what makes the chemical reactions take place and also are also the major factor they are so expensive. The possibility for expense savings is big with this new innovation and also Mazda anticipates to be suitable their vehicles with the new pet cats by 2010. Nissan has additionally just recently revealed that they too have the innovation for more affordable catalytic converters, but they just assert a 50% decrease in the precious metals. The core of the brand-new modern technology is making use of nano-sized ceramic bits with the precious metal installed in them. This allows for even more area so the driver can be more effective. Absolutely nothing has been stated regarding exactly how well the driver flows exhaust gases, which is an important spec for efficiency vehicles. The even more easily the exhaust gases flow out the tail pipes, the much more horse power as well as torque your engine can make, and also that the engine will also be more responsive. Keep your eyes on the information for even more updates about this interesting reducing side modern technology.
know more about catalytic converter recycling here.


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Europe's Jihadists What the Paris Attacks Tell Us about IS Strategy - Spiegel Online By SPIEGEL Staff On the ... and, in recent days, they ... interest in international ... When he was released in September 2012 ... joined the ... 11/29/2015 - 1:19 pm | View Link
Pro-Islamic State militants seize Libyan university: Residents CAIRO: Militants claiming loyalty to Islamic State have seized the university in the central Libyan city of Sirte, residents said on Thursday, days after a video showed ... after the group released a video showing the execution of 21 Egyptian Christians ... 02/19/2015 - 1:03 pm | View Link
Libyan civil war hid rise of ISIS The killings prompted Egyptian airstrikes on Islamic State strongholds in Libya and spurred calls for more active international involvement in ... s video of the slaughter of the Egyptian Copts, released on Monday, concluded with the promise to conquer ... 02/17/2015 - 2:00 pm | View Link
More arrests in U.S. Consulate attack, Libyan official says Libyan authorities have made more arrests in connection with the attack on the U.S. Consulate that left the U.S. ambassador and three others dead, the president of Libya's parliament said Sunday. Mohamed al-Magariaf, the head of Libya's General National ... 09/16/2012 - 6:00 pm | View Link
International Criminal Court staff released by Libyan authorities AN AUSTRALIAN LAWYER and her Lebanese-born interpreter, along with their two male colleagues from the International Criminal Court, have been released by Libyan authorities after almost a month of detention. The four ICC staff members were detained in ... 07/2/2012 - 1:00 pm | View Link
Libyan lawyer says ICC staff to be released CAIRO (AP) — The Libyan prosecutor leading the case against slain dictator Moammar Gadhafi's son has said that two International Criminal Court staffers detained for 26 days will be released Monday ... placed ICC defense lawyer Melinda Taylor and ... 07/2/2012 - 5:22 am | View Link
Libyan Army/Militias | Libya Analysis UNSMIL changes do little to alter Libya’s political and security conundrums The UN’s new envoy to Libya, Martin Kobler, may be trying to do CPR on the moribund UN ... 11/30/2015 - 1:57 pm | View Website
Home | LasVegasNow | KLAS-TV Homeowners urged to protect pipes. As overnight temperatures drop in Las Vegas, homeowners should take steps to ensure their homes are ready for the cold. 11/30/2015 - 12:46 pm | View Website
Ironclad: Egypt Involved in Benghazi Attacks By Walid Shoebat, Ben Barrack and Keith Davies. A Libyan intelligence document has been produced that directly implicates Egypt’s Muslim Brotherhood president ... 11/30/2015 - 12:17 pm | View Website
U.S. News | National News ABC News reports on United States politics, crime, education, legal stories, celebrities, weather, the economy and more 11/30/2015 - 4:46 am | View Website
International News | World News Get the latest international news and events from Asia, Europe, the Middle East, and more. See world news photos and videos at ABCNews 11/30/2015 - 4:39 am | View Website
Democratic presidential candidate Hillary Clinton will mark the 60th anniversary of the Montgomery Bus Boycott as she speaks Tuesday at the historic Alabama church that the Rev. Martin Luther King Jr. pastored during the successful fight against bus segregation.
Earlier, U. S. Rep. Terri Sewell, the lone Democrat and African American member of Alabama's congressional delegation, told the crowd "old battles have become new again."
Sewell cited the Alabama case that led to a U.
Texas Tech has fired three defensive assistant coaches, all of them former players with the Red Raiders.
Mike Smith was co-defensive coordinator and defensive line coach, Kevin Curtis coached the secondary and Trey Haverty handled outside linebackers.
Workers unload the fuselage of AirAsia QZ8501, which crashed into the Java Sea last year. Antara Photo Agency / Reuters Indonesian investigators have determined what brought down the AirAsia passenger plane that crashed into the Java Sea nearly nearly a year ago, killing all 162 people on board. Indonesia AirAsia Flight 8501 crashed as a result of technical failures and the crew’s response to them, according to a report published Tuesday by Indonesia’s National Transportation Safety Committee.

domain: politics


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Supplements to help child gain weight
If your child is underweight and you are looking for ways to help them gain weight, there are a few things you can try.
First, make sure that your child is eating a balanced diet that includes plenty of protein, healthy fats, fruits, vegetables, and whole grains.
You can also try increasing their caloric intake by adding healthy, calorie-dense snacks to their diet, such as nut butters, avocado, yogurt, and cheese.
Additionally, you can encourage your child to be physically active, as regular exercise can help boost their appetite and metabolism.
It’s also important to consult with a healthcare provider, who can provide personalized advice and recommend any necessary supplements.
Be the first to comment

domain: health


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MyBand, MyBar, MySpace
Thursday, January 17, 2008
Ever read about some unknown band playing at The Camp with a funny name that sounds interesting enough to check out? All you have to do is hit MySpace.
Starting a Limp Bizkit cover band, but aren't sure how to promote yourself cheap and easily find places to play? Most would tell you to get your band on MySpace ASAP. And speaking of cheap and easy, MySpace even makes life easier for the venues, making interaction with bands (and potential customers) a snap.
"In a town like Cape I think it helps out a lot," said James VanDike, guitarist and keyboard player for the Otto Modest. "In bigger cities I think there's enough advertising through newspapers and publications and that's where most of the information comes from. But in smaller places I think it helps out a lot."
MySpace has become the global juggernaut of social networking Web sites. And locally bands and bars are using it to reach out to customers and fans and generally make live easier in the live music business.
"When I first got into this, all the bands were on MySpace even then," said Jennifer Cabaniss, booking manager for Schock's Pub in Scott City. "It's just amazing how quick networking is through MySpace. It's nothing for me to hear from five to 10 bands a day now when, before, I would spend hours on the phone every day."
Many other local clubs, bars and places of interest can be found on MySpace, including Buckner's, Double Nickel II in Sikeston, Mo., and the Show Me Center. At Port Cape Girardeau's page you can preview new Yacht Club regulars Whiskey Creek and then post a comment about how awesome you think they are. But Bob Camp, manager of The Camp (one club that is noticeably absent from the site), said that although it is a great tool, MySpace doesn't have as much power, ultimately, as talent.
"It gives you an opportunity to hear what a band sounds like, but it can't tell you whether or not they will draw a crowd," Camp said. "It doesn't take away from the process, and I do use it. I'll probably get one eventually. But bands that have something going on will still get crowds -- MySpace doesn't change that."
But it's not just about the music -- it's about the money, too. And as Paul Schock, owner of Schock's Pub, points out, MySpace is a global advertising opportunity for free (act now and they throw in infinite networking possibilities at no extra charge).
"There is no question it is a great promotional tool, and it has definitely helped business. Not only can we get in contact with bands easier, but other venues and customers will contact us now online," Schock said. "Some people will go online looking for clubs and bands that they like and, because we can post specials and events online, I think people are finding out about us more."
Seemingly every local band -- even those with "official" Web sites -- now has a MySpace page. Fill bassist Wes Ables said the site is much like "six degrees of MySpace Bacon for bands."
Local music scene veteran John Thurman has even set up a MySpace page to promote local music, myspace.com/capemusicscene. Thurman's page lists local bands in alphabetical order, along with contact information.
Moodminder singer/guitarist Danny Callaway says so many bands gather at the site because, simply put, it simplifies everything for the little guy.
"It provides us with all the necessary tools to book and promote shows, sell music and merchandise in addition to communicate with fans all for no charge," Callaway said. "The advantage of being in an indie rock group is that I can do what I want, when I want. And yet, technically, Moodminder still possesses the ability to reach millions of potential fans, just like many of those crappy bigwig-corporate owned 'do as your to told' bands."
And MySpace's networking capabilities have bands claiming the site has played a big role in expanding their fan base.
"It has far and above increased my fans," said singer/guitarist Kris Baronovic of Warchalking. "I've got fans now in places of the country and in the world that I've never seen or ever even heard of, but they like my music and they send me messages and I mail them records."
"We have people all the time who come out to shows and tell us they saw us on MySpace and wanted to check us out," Ables said. "Our crowds are much better than before ?-- there's a huge difference."
MySpace is also great place for bands to sell music. Mainstream acts Arctic Monkeys and Queens of the Stone Age have prereleased albums on MySpace with great success, and local bands like Drivin' Rain can get their music to fans just as easily.
"The music biz types are in trouble all the way around because of the internet and MySpace," said Timexx Nasty, Drivin' Rain front man. "Bands such as mine use the Internet now. We can lay out our own CDs, record our own CDs, print our own CDs, and send them out worldwide. This cuts out the need to pay some recording company thousands to do it for you."

domain: entertainment


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You know the expression “they are fighting like dogs and cats”. Dogs and cats will always be the most loving fre-enemies. They will always tease and piss each other but in fact, they won’t stand to live without each other.
If you are a pet owner for both dogs and cats, you will know how hard it is to keep both of them living peacefully with the other under the same roof.
This is an extraordinary rescue story, it is about a cat who was saved from drowning by a dog!
The stunning Labrador, who is, in fact, a lifeguard, is well trained for rescuing drowning people and he is very clever at that job. But in this special situation, he saved a cat that was drowning and took her into his safety net and then delivered her to the ground!
Dogs are great rescue and protective animals, but have you seen a dog rescuing a cat before? For me, it is my first time to see that and I’m amazed!
The cat accidently fell into the river and she had a tiny hope for life, she was ready to face her final fate. But everything has changed when, out of sudden, a heroic dog showed up at the scene and saved her!
Watch the video, see the whole rescue and I’m pretty sure you will be amazed the same way I’m right now!
It is not a usual video that you can see every day but it is a great evidence that the relationship between dogs and cats, human’s most beloved pets, will always find its way!
Share this amazing story with your family and friends on Facebook!

domain: pet


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Forever Lost 09 Jun About the artwork Post-apocalyptic concept art by Daniel Conway, United Kingdom. Love Coolvibe? Please share! Tweet Posted in: Concept art Tags: apocalypse, Daniel Conway, girl Related Posts Love this post? Please share! Download full-size image
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domain: artistic


CA2457843C - Programmable even-number clock divider circuit with duty cycle correction and optional phase shift - Google PatentsProgrammable even-number clock divider circuit with duty cycle correction and optional phase shift
- Publication number
- CA2457843C CA2457843C CA 2457843 CA2457843A CA2457843C CA 2457843 C CA2457843 C CA 2457843C CA 2457843 CA2457843 CA 2457843 CA 2457843 A CA2457843 A CA 2457843A CA 2457843 C CA2457843 C CA 2457843C
- Grant status
- Patent type
- Prior art keywords
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se
PROGRAN~~ABLE EVEN-NUMBER CLOCK DIVIDER CIRCUIT
WITH DUTY CYCLE CORRECTION AND OPTIONAL PHASE SHIFT
FIELD OF THE INVENTION
The invention relates to clocking circuits for digital systems. More specifically, the present invention relates to a variable even-number clock divider circuit having duty cycle correction and optional phase shift.
BACKGROUND OF THE INVENTION
Digital circuits such as board level systems and integrated circuit (IC) devices, including programmable logic devices (PLDs) and microprocessors, use clocking signals for a variety of reasons. For example, synchronous systems use global clock signals to synchronize various r circuits across the board or IC device.
However, as the complexity of digital, circuits increases, clocking schemes for synchronous systems become 2o more complicated. Many complex digital circuits such as PLDs and microprocessors have multiple clock signals at different frequencies. For example, in some microprocessors, internal circuits are clocked by a first' clock signal at a first frequency while input/output (I/0) circuits are clocked by a second clock signal at a second frequency. Typically, the second frequency is slower than the first frequency.
Multiple clock generating circuits can be used to generate the multiple clock signals. However, clock 3o generating circuits typically consume a large amount of device or board space. Therefore, most systems use one clock generating circuit to generate a first clock signal and a specialized circuit to derive other clock signals from the first clock signal. For example, clock dividers are used to generate one or more clock signals of lower clock frequencies from an input clock signal.
Fig. 1A shows a conventional clock divider 100 that receives an input clock signal ICLK and generates a divided-by-two clock signal CLKD2, a divided-by-four clock signal CLKD4, a divided-by-eight clock signal CLKD8, and a divided-by-sixteen clock signal CLKD16. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) Clock divider 100 comprises a 4-bit counter 110.
Input clock signal ICLK is applied to the clock terminal of Zo 4-bit counter 110. 4-Bit counter 110 drives clock signals CLKD2, CLKD4, CLKD8, and CLKD16 on output terminals 00, 01, 02, and 03, respectively. Output terminals 00 through 03 provide the least significant bit through the most significant bit of 4-bit counter 110, respectively.
Fig. 1B is a timing diagram for clock divider 100. As can easily be seen from Fig. 1B, if input clock signal ICLK
has a clock period P, then divide-by-two clock signal CLKD2 has a clock period of 2P. Similarly, divide-by-four clock signal CLKD4 has a period of 4P, and so forth. Thus, the 2o frequency of clock signal CLKD2 is half the frequency of input clock signal ICLK, the frequency of clock signal CLKD4 is one-fourth the frequency of signal ICLK, and so forth.
Including a clock divider in an IC device typically carries a timing penalty, whether or not the clock divider is in use. Fig. 2A shows a first clock driver circuit in an IC where a clock divider is not included. The clock driver circuit 200 includes a driver 201 that accepts an input clock signal from clock pad 202, and applies the 3o signal to clock tree 203. Fig. 2B shows a second clock driver circuit 210, which includes an optional clock divider 204. The designer can either include clock divider 204 in the circuit, or bypass the clock divider, under the control of multiplexer 205.
Fig. 2B clearly shows that whether or not the clock divider is included in the clock path, there is an additional delay D210 in the circuit of Fig. 2B compared to that of Fig. 2A. If the clock divider is bypassed, there is added delay in the bypass line and a propagation delay through the multiplexer 205. If the clock divider is included in the circuit, there are the added propagation delays of both the multiplexer and the clock divider. In either case, the total delay through the clock driver s circuit is increased.
If a clock divider such as that shown in Fig. 1 is placed into the clock driver circuit of Fig. 2B, the result is a clock tree driven by a flip-flop (from 4-bit counter 110 of Fig. 1) through a multiplexer (e.g., multiplexer 205 Io of Fig. 2B). Clearly, neither a flip-flop nor an unbuffered multiplexer have the drive capability to drive a large clock tree--the resulting clock signal would be unacceptably slow and have a very high skew. Therefore, multiplexer 205 is typically buffered, for example, as 1s shown in Figs. 3A and 3B.
Fig. 3A shows a prior art Clock driver circuit 320 that includes an inverting clock divider 314. Multiplexer 205 has been replaced by multiplexing circuit 325, which implements the logical equivalent of multiplexer 205 with 2o the input signal from the clock divider inverted by inverter 306.
One implementation of multiplexing circuit 325, designated 325A in Fig. 3A, includes a tristate driver 326, to which the output of inverting clock divider 314 is 2s applied, and passgate 327, to which the bypass clock signal is applied. By controlling the tristate control signal of tristate driver 326 and the passgate control signals of passgate 327, either the divided Clock signal or the bypass clock signal is selected. Note, however, that the bypass 3o clock signal is still not buffered in this embodiment, so another buffer (not shown) may be inserted after passgate 327 for heavily-loaded clock signals.
Fig. 3B shows a prior art clock driver circuit 330 that includes a non-inverting clock divider 324.
35 Multiplexer 205 has been replaced by multiplexing circuit '335, which implements the logical equivalent of multiplexer 205 with an output signal buffered through buffer 30,9.
One implementation of multiplexing circuit 335, designated 335A in Fig. 3B, includes a first tristate driver 336, to which the output of non-inverting clock divider 324 is applied, and a second tristate driver 337, to which the bypass clock signal is applied. By controlling the tristate control signals of tristate drivers 336 and 337, either the divided clock signal or the bypass clock signal is selected. The selected clock signal is then inverted and buffered by inverter 339.
However, the clock driver circuits shown in Figs. 3A and 3B have implicit additional delays that can be significant. The additional delay D320 added by the clock divider in Fig. 3A is the delay through clock divider 314 plus the delay through tristate driver 326. The additional delay D330 added by the clock divider in Fig. 3B is the delay through the clock divider 324 plus the delay through tristate driver 336 and inverter 339.
Delay through a clock driver circuit is an important parameter for IC designers. Using circuits similar to those shown in Figs. 3A and 3B, the additional delay due to the presence of a clock divider can be significant, e.g., about 500 picoseconds. Like most timing parameters, this delay is typically specified as a worst-case value, to ensure operation of the device under worst-case conditions. Therefore, even when the clock divider is bypassed, the specifications for the device are based on the worst case scenario, i.e., the delay when the clock divider is included. Therefore, the additional delay on the clock path due to the presence of a clock divider not only delays the clock signal, it also makes the IC device appear to be slower than it really is.
For these and other reasons, it is advantageous to provide a clock divider circuit having a reduced delay.
SUMMARY OF THE INVENTION
In one aspect of the invention, there is provided a clock divider circuit, comprising: a clock input terminal; a clock output terminal; a state machine having an input terminal coupled to the clock input terminal, and further having set and reset output terminals; a keeper circuit having an output terminal coupled to the clock output terminal; a pullup circuit having a data input terminal coupled to the clock input terminal, a control input terminal coupled to the set output terminal of the state machine, and an output terminal coupled to the clock output terminal; and a pulldown circuit having a data input terminal coupled to the clock input terminal, a control input terminal coupled to the reset output terminal of the state machine, and an output terminal coupled to the clock output terminal.
Embodiments of the invention provide a novel clock divider circuit that adds very little additional delay to the clock driver containing the circuit. Further, according to one 4a embodiment, the clock divider circuit of the invention provides the capability to divide by any even number, rather than being limited to powers of two as are many clock dividers. The delay through the clock divider circuit is the same, regardless of which even number is selected as the divisor.
In one embodiment of the invention, a clock divider circuit includes a state machine that receives the input clock signal and generates set and reset control signals.
The set and reset control signals are used to control set and reset passgates, respectively, selectively providing the input clock signal to the gate terminals of a pullup and a pulldown, respectively, on the output node. The set and reset control signals are also provided to a keeper l5 circuit that maintains a value placed on the output node.
An advantage of this circuit is that the delays typical of prior art clock dividers (D-flip-flop delays, multiplexer delays, and so forth) are shifted from the clock path to the path including the set and reset control 2o signals. Therefore, these delays are not on the clock path, i.e., not on the.critical path for the clock divider circuit.
Another advantage is that by controlling the functionality of the state machine, any even number (up to 25 the capacity built into the state machine) can be selected as the divisor for the clock divider circuit. Therefore, the clock divider circuit of the invention provides additional flexibility compared to many known clock dividers .
3o In one embodiment, a phase bit is provided. The phase bit allows the user to either start the clock divider circuit at the first rising edge of the input clock or to delay the clock divider circuit for a predetermined number of clock cycles.
35 In another embodiment, the clock divider circuit is designed to complete the last high pulse (e.g., to Clock in the most recent data value) if the user miscounts the number of clock cycles and mistakenly resets the clock in the middle of the clocking process.
According to another aspect of the invention, a clock driver circuit includes an input buffer, a bypass passgate, and a tristateable clock divider circuit. Rather than using a multiplexes circuit to select between the bypass signal and the output of the clock divider circuit, the clock divider circuit can, be tristated. Thus, when the clock divider circuit is tristated and the bypass passgate 1o is on, the bypass signal is passed to the Clock driver circuit output. When the clock divider CirCUit is active (not tristated) and the bypass passgate is off, the divided clock signal is passed to the Clock driver circuit output.
Thus, the additional delay added by the multiplexes circuit used in conventional Clock divider circuits is omitted.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention is illustrated by way of example, and not by way of limitation, in the following 2o figures, in which like reference numerals refer to similar elements.
Fig. 1A is a block diagram of a conventional clock divider.
Fig. 1B is a timing diagram for the Clock divider of Fig. 1A.
Fig. 2A is a block diagram of a Conventional clock driver circuit notlincluding a Clock divider.
Fig. 2B is a block diagram of a conventional clock driver circuit including an optional Clock divider.
3o Fig. 3A is a block diagram of a conventional Clock driver circuit including an inverting clock divider.
Fig. 3B is a block diagram of a conventional Clock driver Circuit including a non-inverting Clock divider.
Fig. 4 is a block diagram of a first driver circuit including a tristateable Clock divider according to a first embodiment of the invention.
Fig. 5 is a block diagram of a clock divider circuit according to a second embodiment of the invention.
Fig. 6 is a timing diagram showing the operation of the Clock divider circuit of Fig. 5 in divide-by-2 mode.
Fig. 7 is a timing diagram showing the operation of the clock divider circuit of Fig. 5 in divide-by-6 mode.
Fig. 8 is a block diagram of an enable signal generator circuit that can be used with the clock divider circuit of Fig. 5.
1o Fig. 9 is a block diagram of a decoder circuit that can be used with the clock divider circuit of Fig. 5.
Fig. 10 (comprising Figs. 10A arid 10B) is a block diagram of a state machine that can be used with the clock divider circuit of Fig. 5.
Fig. 11 is a block diagram of a first sub-cell of the state machine of Fig. 20, Fig. 12 is a block diagram of a second sub-cell of the state machine of Fig. 10.
Fig. 23 is a block diagram of a set filter circuit 2o that can be used with the clock divider circuit of Fig. 5.
Fig. 14 is a block diagram of a reset filter circuit that can be used with the clock divider circuit of Fig. 5.
Fig. 15 is a block diagram of a keeper circuit that can be used with the clock divider circuit of Fig. 5.
DETAILED DESCRIPTION OF THE DRAWINGS
In the following description, numerous specific details are set forth to provide a more thorough understanding of the present invention. However, it will 3o be apparent to one skilled in the art that the present invention may be practiced without these specific details.
Fig. 4 shows a clock driver circuit 440 that includes a clock pad 402, an input buffer 401, a bypass passgate PassB, and a clock divider circuit 434. Unlike prior art clock driver circuits, clock driver circuit 440 does not include a multiplexer to select between the output of clock divider circuit 434 and a bypass clock signal. Instead, clock divider circuit 434 is internally tristateable. When clock divider circuit 434 is tristated (i.e., at high impedance) and passgate PassB is on, the bypass clock signal is passed to the clock tree 403. When clock divider circuit 434 is active and passgate PassB is off, the divided Clock signal is passed to clock tree 403.
Circuit 434A in Fig, 4 shows one implementation of tristateable clock divider 434. In this embodiment of the invention, the tristateable clock driver circuit includes a 1o state machine 436, a pullup circuit PUckt, a pulldown circuit PDckt, and a keeper circuit 439.
S State machine 436 receives clock divider input clock signal CKIN and generates set and reset'COntrol signals (QS
and QR, respectively). When control signal QS is low, a rising edge on input clock CKIN is passed to node "S", and hence to output signal CKOUT. When Control signal QR is low, a rising edge on input Clock CKIN is passed to node "R", and hence to a falling edge on output signal CKOUT.
Nodes S and R are preferably initialized to low and high 2o values, respectively, by way of a pulldown and pullup (not shown) gated by a reset signal (also not shown). State machine 436 keeps track of where input signal CKIN is in the "divided" Clock Cycle, and generates the appropriate voltage levels on QS and QR to drive the output clock signal high and low at the appropriate times. For example, when the divisor is six, each of control signals QS and QR
pulses low for one CKIN Clock Cycle in every six.
In one embodiment, the state machine accommodates only one divisor. In other embodiments, the state machine is 3o programmable, and accommodates a plurality of divisors.
In some embodiments, the state machine and clock divider~circuit form a portion of a programmable logic device (PLD) such as a field programmable gate array (FPGA) or a complex programmable logic device (CPLD). In one such embodiment, the state machine is implemented using user-Controlled programmable logic to perform a specific function in a particular design, and supports only one divisor, In another embodiment, the clock divider and state machine circuits are implemented in dedicated logic (i.e., not using the user-controlled logic blocks). This dedicated logic, however, can be designed to be programmable. For example, in some embodiments a clock divider circuit is implemented in dedicated logic in a programmable logic device. The clock divider circuit includes a state machine that is configurable to support any of several divisors. In one such embodiment, where the 1o PLD is a CPLD, the state machine is controlled by logic values stored in FLASH memory using the typical programming process for the CPLD. In this embodiment, the logic values are included in the CPLD configuration data file. In another such embodiment, where the PLD is an FPGA, the state machine is controlled by logic values stored in SRAM
cells during the normal configuration process for the FPGA.
In this embodiment, the logic values are loaded as part of a configuration bitstream.
Returning to Fig. 4, set control signal QS controls 2o set passgate PassS, which selectively provides input clock signal CKIN to pullup PU. In the embodiment of Fig. 4, set passgate PassS is coupled to the input terminal of inverter INVS, which drives the gate of pullup PU. Reset control signal QR controls reset passgate PassR, which selectively provides input clock signal CKIN to pulldown PD.
In the pictured embodiment, pullup PU is a PMOS
transistor, passgate PassS is a CMOS passgate controlled by set control signal QS and the same signal inverted by inverter 437, passgate PassR is a CMOS passgate controlled 3o by reset control signal QR and the same signal inverted by inverter 438, and pulldown PD is an NMOS transistor. In other embodiments, other types of transistors and/or other circuits are used to implement pullup PU, pulldown PD, and passgates PassS and PassR. For example, passgates PassS
and PassR can be implemented as NMOS transistors, PMOS
transistors, tristate drivers, and so forth, while pullup PU can be implemented as an NMOS transistor if inverter INVS is omitted.
Set passgate PassS, inverters 437 and INVS, and pullup PU collectively comprise pullup circuit PUckt. Reset passgate PassR, inverter 43~, and pulldown PD collectively comprise pulldown circuit PDckt.
Pullup PU and pulldown PD are coupled in series between power high (VCC) and ground (GND). The node between pullup PU and pulldown PD is coupled to the output terminal CKOUT of the clock divider.
The set S and reset R control signals are also provided to a keeper circuit 439, which is coupled to output terminal CKOUT. Keeper circuit 439 provides a weak output signal KOUT that reinforces the signal on output terminal CKOUT, such that the voltage level of the signal remains stored on the node when both pullup PU and pulldown PD are off. One embodiment of keeper circuit 439 is described in detail below, with relation to Fig. 15.
However, keeper circuits are well known in the art, and any 2o keeper circuit can be used in clock driver 434A, as long as it is weak enough to be overridden by both pullup PU and pulldown PD. For example, a weak cross-coupled latch with two inverters can be used as a weak keeper, with one of the inverters also driving signal CKOUT. This embodiment does not require signals S, R, and CDEN as inputs to the weak keeper.
Set and reset control signals QS and ~R are preferably mutually exclusive. That is, preferably state machine 436 does not allow signals QS and QR to be active at the same 3o time. Therefore, pullup PU and pulldown PD are never both on at the same time, and there is no current flow between VCC and GND, nor transitory contention over which transistor will control the value on the CKOUT output terminal, as can occur in the conventional clock divider circuits shown in Figs. 3A and 3B.
Note that the delay through clock driver circuit 434A
for a rising clock edge includes only the delay through passgate PassS, inverter INVS, and pullup PU. The delay through clock driver circuit 434A for a falling clock edge includes only the delay through passgate PassR and pulldown PD. Therefore, the clock delay of clock driver circuit 440 is significantly shorter than the clock delay through, for example, clock driver circuits 320 and 330 of Figs. 3A and 3B.
The novel circuit configuration of Fig. 4 has an additional advantage. In conventional clock drivers, the 1o clock signal follows the same path through the driver for both falling and rising edges of the clock. Therefore, the circuit cannot be optimized for both edges; instead, some compromise must be reached that provides acceptable performance on both edges of the clock. However, in the circuit shown in Fig. 4, the pullup PU and pulldown PD are separately controlled. Therefore, the controlling transistors can each be optimized for the corresponding clock edge. In other words, a rising edge on output clock signal CKQUT is controlled by passgate PassS, inverter 2o INVS, and pullup PU, while a falling edge on output clock signal CKOUT is controlled by passgate PassR and pulldown PD. Therefore, passgate PassS, inverter INVS, and pullup PU can be optimized to improve the performance of the rising edge of the output clock CKOUT, while passgate PassR
and pulldown PD can be optimized to improve the performance of the falling edge of the output clock CKOUT. This optimization can be achieved, for example, through well-known methods involving circuit simulations performed on a computer.
3o For all of these reasons, the clock delay through clock driver circuit 434A is significantly lower than the delay through conventional clock driver circuits. As mentioned above, the delay added to a clock driver circuit using a conventional clock divider is typically about 500 picoseconds. However, when the same manufacturing technology is used, the delay added when using clock divider 434A can be as little as 90 picoseconds.
Programmable Clock Divider Figs. 5 and 8-15 collectively provide a detailed schematic diagram of a programmable clock divider circuit 500 according to one embodiment of the invention. Figs. 6 and 7 provide two exemplary timing diagrams for clock divider circuit 500, in divide-by-2 mode and divide-by-6 mode, respectively. The operation of this embodiment is now described with reference to Figs. 5-15.
Zo Signals used in clock divider circuit 500 include the following:
CKIN Input clock signal to the clock divider Circuit.
CKOUT Output clock signal (e. g., divided clock).
CDRST Resets (and disables) the clock divider circuit i5 when high; releases (and enables) the clock divider circuit when low.
CDEN Overrides other Control signals. When high, enables the clock divider: turns off the bypass circuit BPC; enables the keeper circuit 560 to follow the S and R
ao control signals and keep the CKOUT value stable; and releases the reset filter to the control of the RST signal.
V~hen low, disables the clock divider: turns on the bypass circuit BPC; tristates the keeper circuit 560; and turns off both pullup PU and pulldown PD. In one embodiment, 25 signal CDEN is a value stored in a configuration memory cell, e.g., a FLASH memory Cell in a CPLD or an SRAM
configuration memory cell in an FPGA.
CDDIV Input signals (CDDIVO, CDDIV1, and CDDIV2) that select a divisor for the programmable clock divider. In 30 one embodiment, control signals CDDIVO-CDDIV2 are values stored in configuration memory cells, e.g., FLASH memory cells in a CPLD or SRAM configuration memory cells in an FPGA.
CDP Provides optional phase shift. When high, the 35 clock divider output signal CKOUT rises on the first rising edge of the input clock signal CKIN after CDRST goes low.
When low, the clock divider output signal is delayed by one output clock cycle (i.e., .one CKOUT cycle). For example, if the clock divider is configured to divide by 4, then the CKOUT signal rises on the fifth rising edge of the CKIN
signal after CDRST goes low.
PUINIT This initialization signal is an input signal that goes high only during power-up of the PLD. It is primarily used to initialize flip-flops throughout the PLD.
The clock divider circuit of Fig. 5 comprises a programmable control circuit 501, a pullup circuit PUC, a pulldown circuit PDC, a keeper circuit 560, and a bypass circuit BPC.
Fig. 6 is a timing diagram showing the operation of the clock divider circuit of Fig. 5 in divide-by-2 mode.
As long as clock divider reset signal CDRST is high, signals QS, QR, S, and R remain at their reset values (low, high, low, and high, respectively). Programmable control circuit 501 decodes input signals CDDIV[2:Q~ and derives the divisor of two. When Clock divider reset signal CDRST
goes low, signal S goes high on the next rising edge of CKIN. Signal S then goes low again on the next falling 2o edge of CKIN. Keeper signal KOUT remains high when signal S goes low, so signal CKOUT stays high after signal S goes low.
Signal R then goes high on the next rising edge of CKIN (because the state machine has set signal QR low) and pulls CKOUT low. Signal R then goes low again on the next falling edge of CKIN. Keeper signal KOUT remains low when signal R goes low, so signal CKOUT stays.low after signal R
goes low. This Cycle repeats until Clock divider reset signal CDRST goes high. If the clock divider is reset 3o while signal CKOUT is high, the high pulse on signal CKOUT
Fig. 7 is a timing diagram showing the operation of the Clock divider circuit of Fig. 5 in divide-by-6 mode.
The timing diagram is similar to that of Fig. 6, except that signals QS and QR go low only every sixth Clock cycle instead of every other clock cycle, and the signals dependent upon QS and QR occur less frequently in consequence.
Bypass Circuit Bypass circuit BPC provides a way of bypassing and disabling the clock divider function of the Clock divider circuit. Passgate PassB is situated between input clock terminal CKIN and output clock terminal CKOUT. In the pictured embodiment, passgate PassB is a CMOS passgate, , 2o with the PMOS control terminal coupled to CDEN~and the NMOS
control terminal coupled to the inverse signal generated by inverter 544. When clock divider enable signal CDEN is high, the passgate is off. When Clock divider enable signal CDEN is low, the passgate is on.
Programmable Control Circuit In the embodiment of Fig. 5, programmable control Circuit 501 comprises synchronized reset generator 510, a decoder 520, and a state machine 530.
2o Synchronized reset 510 provides an appropriately delayed version of the clock divider reset signal CDRST.
The number of CKIN clock cycles by which the reset signal is delayed is Controlled by the three control signals CDDIVO-CDDIV2.
One embodiment of synchronized reset 510 is shown in Fig. 8. Synchronized reset 510 Comprises 16 set flip-flops 801-816 coupled in series. The Q outputs of the even-number flip-flops are provided to an 8-to-1 multiplexes 820, which is Controlled by control signals CDDIVO-CDDIV2.
-3o In the pictured embodiment, the CDDIV values Correspond to the divide-by value (devisor) of the clock divider as shown in Table 1.
The output of multiplexer 820 is a signal that mirrors the clock divider reset signal CDRST, but is delayed by a selected number of CKIN clock cycles. The output of multiplexes 820 drives the "0" data terminal of 2-to-1 multiplexes 821. The "1" input terminal is driven lay the CDRST signal, and one of the two inputs is selected by control signal CDP, which is described above.
2o The output of multiplexes 821 is stored in set flip-flop 817, which drives NAND-gate 823. The set terminal of flip-flop 817 is driven by signal PUINIT, which is described above. The other input to NAND-gate 823 is reset control signal R, from pulldown circuit PDC. NAND-gate 823 is NANDed with the inverse of signal PUINIT (which goes high only during power-up to initialise all flip-flops on the PLD) to generate reset signal SYNRST.
The R input to NAND-gate 823 provides an additional capability. If the clock divider is reset while signal 3o CKOUT is high, the feedback from the reset control signal R
ensures that the last clock cycle on signal CKOUT is completed.
Fig. 9 shows one embodiment of decoder 520. The pictured embodiment includes NOR-gates 901-913, NAND-gates 920-939, and inverters 950-957. Decoder 520 decodes signals CDDIVO-CDDIV2 and generates from these signals control signals DIV2-DIV14 and SMX_6to16, which form a bus labeled "DIV" in Figs. 9 and 5. The decoder also generates from signals CDDIVO-CDDIV2 control signals OFF2-OFF16, which form a bus labeled "OFF" in Figs. 9 and 5. All of these signals are used to control state machine 530.
Decoding tables for decoder 520 are provided in Tables 2A
and 2B, where a "1" is high, a "0" is low, and an "x" is a don't-care value.
Additionally, in decoder 520 another reset signal, RST, is generated from clock divider enable signal CDEN and reset signal SYNRST. This reset signal is used to reset the set and reset filters in the pullup and pulldown circuits, respectively.
~5 CDEN 2 1 0 SMX 6to16 14 12 10 _8 _6 4 2 0 x x x 0 0 0 0 0 0 0 0 CDDIV OFF
CDEI~T 2 1 0 16 14 12 10 8 6 4 2 0 x x x 0 0 0 0 0 0 0 0 ~.0 1 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 l 1 0 0 0 0 0 Fig. 10 (comprising Figs. 10A and 10B) is a block 2o diagram of one embodiment of state machine 530. State machine 530 is controlled by the DIV and OFF buses from decoder 5~0, and provides the ~S and QR control signals to the set and reset filters in the pullup and pulldown circuits (respectively). State machine 530 comprises seven ~5 serially connected sub-cells (logic blocks 531a-f and 532), as shown in Fig. 10. Signals DIV14-DIV2 control the serial connections between the blocks, via multiplexers a-q and t-u. When the clock divider is enabled (i.e., when CDEN is high), exactly one of DIV signals DTV14-DIV2 is high (see 3o Table 2A). Therefore, all but one of the sub-cells passes values from left to right along the chain. The selected sub-cell places its QS and QR values on the chain.
For example, when the divisor is 6, signal DIVE is high. Therefore, sub-cell 531f is the sub-cell that places 35 signal ~S onto the chain via its DS6 terminal. Similarly, the value QR6FB is placed onto the dly6 (Ddelay6) terminal, and signal QR2 is placed on the DR6 terminal, of sub-cell 531f. The selected QS and QR values are then passed to flip-flops 5'33 and 534, respectively. The set control signal QS is supplied by flip-flop 533. The reset control signal QR is supplied by multiplexer 535, which selects among the values QR6dly, QR4dly, and QR2 based on the values of signals SMX_6to16, DIV4, and DIV2.
The delay chain (the chain from Ddelayi to Qdelayi across the sub-cells of the state machine) provides an automatic duty cycle correction capability. This circuitry ensures that the low pulse on the QR signal always occurs 1o midway between low pulses on the QS signal. (See, for example, the timing diagram in Fig. 7.) As will be seen in Fig. 11, the delay on the delay chain through each sub-cell is half that of the delay on the chains from DSi to QSi, and from DRi to QRi. Further, the delay chain contributes to the formation of the QR contr~1 signal. Therefore, the duty cycle of the divided clock signal is always 50%.
Fig. 11 is a block diagram of a first sub-cell 531 of the state machine of Fig. 10. Sub-cell 531 comprises reset flip-flops 2202-1202, set flip-flops 1110-1112, and NOR-2o gates 1120-1123. Signal DSi is passed through flip-flop 1101, NOR-gate 1120 (if signal QS2B is low), flip-flop 1202, and NOR-gate 1123 (if signal QS2B is low) to output terminal QSi. Signal Ddelayi is passed through flip-flop 1110 to output terminal Qdelayi. Signal DRi is passed through flip-flop 1112 'to NOR-gate 1121, and is also fed back to output terminal QRiFB. When signal QR2B is low, NOR-gate 1121 passes the inverted output of flip-flop 1112 to flip-flop 1111, and hence to NOR-gate 1122, which has signal QR2B as its other input. NOR-gate 1122 provides output signal QRi.
Fig. 12 is a block diagram of a second sub-cell 532 of the state machine of Fig. 10. Sub-cell 532 is similar to sub-cell 531, except that the signal QR4DLY is the output of flip-flop 1222.
Fig. 13 is a block diagram of set filter circuit 541.
As can be seen in Fig. 5, the set filter circuit controls the pullup PU on the clock output signal CKOUT. The set filter circuit accepts control signal QS from the state machine and uses the QS signal to filter clock pulses on input clock signal CKIN. In other words, based on the value of signal QS, pulses on signal CKIN are or are not passed on to signal S.
In the pictured embodiment, set filter circuit 541 comprises NOR-gate 1301, inverter 1302, passgate 1303, and pulldown PD1. Passgate 1303 is placed between input terminal CKIN and output terminal S. NOR-gate 1301 accepts 1o signals QS and RST as inputs and provides signal GNS, which controls the NMOS terminal of passgate 1303. Signal GNS
also drives inverter 1302, which controls the PMOS terminal of passgate 1303 and also controls pulldown PD1. Pulldown PD1 is coupled between output terminal S and ground GND.
Fig. 14 is a block diagram of reset filter circuit 551. As can be seen in Fig. 5, the reset filter circuit controls the pulldown PD on the clock output signal CKOUT.
The reset filter circuit accepts control signal QR from the state machine and uses the QR signal to filter clock pulses on input clock signal CKIN. In other words, based on the value of signal QR, pulses on signal CKIN are or are not passed on to signal R.
In the pictured embodiment, reset filter circuit 551 comprises NOR-gates 1402 and 1402, HAND-gate 1406, inverters 1404 and 1405, passgate 1403, pullup PU2, and pulldown PD2. Passgate 1403 is placed between input terminal CKIN and output terminal R.~ NOR-gate 1401 accepts signals QR and RST as inputs and provides signal GNR, which controls the NMOS terminal of passgate 1403. Signal GNR
3o also drives inverter 1405, which controls the PMOS terminal of passgate 1403, and also drives a first input of NOR-gate 1402. NOR-gate 1402 controls pulldown PD2, which is coupled between output terminal R and ground GND. NAND-gate 1406 accepts signals CDEN and RST as inputs and provides signal PPUB. Signal PPUB controls pullup PU2, which is coupled between output terminal R and power high VCC. Signal PPUB also drives inverter 1404, which provides the second input to NOR-gate 1402.
Fig. 15 is a block diagram of keeper circuit 560.
Keeper circuit 560 comprises pullups PU3 and PU4, and pulldowns PD4 and PD3, serially coupled between power high VCC and ground GND. Output terminal KOUT is coupled between pullup PU4 and pulldown PD4. Clock divider enable signal CDEN drives pulldown PD3 directly, and pullup PU3 through inverter 1501. Thus, when signal CDEN is low, both 1o pullup PU3 and pulldown PD3 are off, and the signal at output terminal KOUT is tristated. Pullup PU4 and pulldown PD4 are both driven by signal SB. Signals SB and RB are provided by cross-coupled NOR-gates 1502 and 1503, respectively. The other input to NOR-gate 1502 is the S
~.5 signal from set filter 541. The other input to NOR-gate 1503 is the R signal from reset filter 551.
In the various embodiments of this invention, novel structures have been described for clock driver circuits and clock divider circuits. The various embodiments of the 2o structures and methods of this invention that are described above are illustrative only of the principles of this invention and are not intended to limit the scope of the invention to the particular embodiments described. For example, in view of this disclosure those skilled in the 25 art can define other state machines, keeper circuits, passgates, inverters, pullups, pulldowns, tristateable clock dividers, buffers, multiplexers, and so forth, and use these alternative features to create a method, circuit, or system according to the principles of~this invention.
3o Thus, the invention. is limited only by the following claims.
a clock input terminal;
a clock output terminal;
a state machine having an input terminal coupled to the clock input terminal, and further having set and reset output terminals;
a keeper circuit having an output terminal coupled to the clock output terminal;
a pullup circuit having a data input terminal coupled to the clock input terminal, a control input terminal coupled to the set output terminal of the state machine, and an output terminal coupled to the clock output terminal; and a pulldown circuit having a data input terminal coupled to the clock input terminal, a control input terminal coupled to the reset output terminal of the state machine, and an output terminal coupled to the clock output terminal.
a passgate coupled between the clock input terminal and a passgate output terminal, the passgate having a first gate terminal coupled to the set output terminal of the state machine; and a pullup coupled between power high and the clock output terminal, the pullup having a gate terminal coupled to the passgate output terminal.
the pullup circuit further comprises a first inverter;
the pullup is a PMOS transistor; and the gate terminal of the pullup is coupled to the passgate output terminal through the first inverter.
the pullup circuit further comprises a second inverter; and the passgate is a CMOS passgate having a second gate terminal coupled to the set output terminal of the state machine through the second inverter.
a passgate coupled between the clock input terminal and a passgate output terminal, the passgate having a first gate terminal coupled to the reset output terminal of the state machine; and a pulldown coupled between the clock output terminal and ground, the pulldown having a gate terminal coupled to the passgate output terminal.
the pulldown circuit further comprises an inverter;
the pulldown is an NMOS transistor; and the passgate is a CMOS passgate having a second gate terminal coupled to the reset output terminal of the state machine through the inverter.
Priority Applications (3)
|Application Number||Priority Date||Filing Date||Title|
|US09942230 US6445228B1 (en)||2001-08-28||2001-08-28||Programmable even-number clock divider circuit with duty cycle correction and optional phase shift|
|PCT/US2002/026279 WO2003021785A3 (en)||2001-08-28||2002-08-16||Programmable even-number clock divider circuit with duty cycle correction and optional phase shift|
|Publication Number||Publication Date|
|CA2457843A1 true CA2457843A1 (en)||2003-03-13|
|CA2457843C true CA2457843C (en)||2005-11-22|
Family Applications (1)
|Application Number||Title||Priority Date||Filing Date|
|CA 2457843 Active CA2457843C (en)||2001-08-28||2002-08-16||Programmable even-number clock divider circuit with duty cycle correction and optional phase shift|
Country Status (5)
|US (3)||US6445228B1 (en)|
|EP (1)||EP1428318B1 (en)|
|JP (1)||JP3830940B2 (en)|
|CA (1)||CA2457843C (en)|
|WO (1)||WO2003021785A3 (en)|
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|US6856171B1 (en) *||2003-06-11||2005-02-15||Lattice Semiconductor Corporation||Synchronization of programmable multiplexers and demultiplexers|
|US6917662B2 (en) *||2003-09-11||2005-07-12||International Business Machines Corporation||Programmable low-power high-frequency divider|
|DE10355698B4 (en) *||2003-11-28||2005-10-27||Infineon Technologies Ag||Flip-flop with multiple operating mode|
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Also Published As
|Publication number||Publication date||Type|
|US5036217A (en)||High-speed low-power flip-flop|
|Zilic et al.||Using BDDs to Design ULMs for FPGAs|
|US4931748A (en)||Integrated circuit with clock generator|
|US6617893B1 (en)||Digital variable clock divider|
|Larsson||High-speed architecture for a programmable frequency divider and a dual-modulus prescaler|
|US5943488A (en)||Method and apparatus to generate mask programmable device|
|US6297684B1 (en)||Circuit and method for switching between digital signals that have different signal rates|
|US6252526B1 (en)||Circuit and method for fast parallel data strobe encoding|
|US5045811A (en)||Tuned ring oscillator|
|US5155380A (en)||Clock switching circuit and method for preventing glitch during switching|
|US6608513B2 (en)||Flip-flop circuit having dual-edge triggered pulse generator|
|US5497263A (en)||Variable delay circuit and clock signal supply unit using the same|
|US6009139A (en)||Asynchronously programmable frequency divider circuit with a symmetrical output|
|US6333959B1 (en)||Cross feedback latch-type bi-directional shift register in a delay lock loop circuit|
|US5914996A (en)||Multiple clock frequency divider with fifty percent duty cycle output|
|US5764714A (en)||Latching inputs and enabling outputs on bidirectional pins with a phase locked loop (PLL) lock detect circuit|
|US6314550B1 (en)||Cascaded programming with multiple-purpose pins|
|US6320418B1 (en)||Self-timed pipelined datapath system and asynchronous signal control circuit|
|US5023484A (en)||Architecture of high speed synchronous state machine|
|US6369624B1 (en)||Programmable phase shift circuitry|
|US7301824B1 (en)||Method and apparatus for communication within an integrated circuit|
|US5508648A (en)||Differential latch circuit|
|US6906562B1 (en)||Counter-based clock multiplier circuits and methods|
|US5317601A (en)||Clock distribution system for an integrated circuit device|
|US4903223A (en)||Programmable logic device with programmable word line connections|


HP Automatic Transmission Coolers with Fan 26,000 GVW
JEGS 60388 High-Performance Transmission Cooler Features:
- 26,000 GVW
- 500 cfm Fan (5.6 Amp Draw)
- Compact unit 11 1/4 in. x 18 1/2 in. x 3 3/4 in.
- -6 AN Union connections
- 11 in. diameter Fan can be used as a pusher or puller
- The Fan in this kit is assembled as a pusher. The location of your unit is very important for proper airflow. To convert your fan to a puller you will need to reverse the fan blade and also the wiring connection. see instructions for more details.
Will this work on a 2014 Camaro ss?
Will this be more than capable of cooling tyranny fluid when I put a 3500 stall in my 4l60e or should I go higher!?
will this fit the ram 1500 2016 ecodiesel??
Can this cooler be used as a stand alone trans cooler to eliminate my running through my radiator I have a 5.0 mustang with a C4 auto in a jeep
can this be used remote location not in radiator area.such as laying flat toward the ground
Can this be used for engine oil?
Will this work on a 1999 chevy Silverado 2500?
WARNING: Motor vehicles contain fuel, oils and fluids, battery posts, terminals and related accessories which contain lead and lead compounds and other chemicals known to the State of California to cause cancer, birth defects and other reproductive harm. These chemicals are found in vehicles, vehicle parts and accessories, both new and as replacements. When being serviced, these vehicles generate used oil, waste fluids, grease, fumes and particulates, all known to the State of California to cause cancer, birth defects, and reproductive harm.
WARNING: Some dust created by power sanding, sawing, grinding, drilling, and other construction activities contains chemicals known to the State of California to cause cancer and birth defects or other reproductive harm. Some examples of these chemicals are: lead from lead-based paints, crystalline silica from bricks and cement and other masonry products, and arsenic and chromium from chemically treated lumber. Your risk from exposure to these chemicals varies, depending on how often you do this type of work. To reduce your exposure, work in a well-ventilated area and with approved safety equipment, such as dust masks that are specially designed to filter out microscopic particles.
WARNING: The wires of these products contain chemicals known to the State of California to cause cancer and birth defects or other reproductive harm. Wash hands after handling.


text:
Thank you for your interest in the birthplace of Pope Benedict XVI.
"If we patiently walk on, believing, a new day can come out of this darkness for us too. And God‘s bright world, the lost world of images and sounds, will be given us as if new: a new morning in God‘s good creation."
(Joseph Ratzinger, Dogma and Annunciation, p. 330)
The special exhibition “Your face, Lord, do I seek.“ with works by Michael Triegel is open until 4. October 2021
Dr. Franz Haringer


In two separate Feb. 4 incidents, shots were fired and arrests were made by the Griffin Police Department.
In the first incident, officers were dispatched to the intersection of Lane Street and North Avenue at 5:27 p.m. in response to a shots fired call. According to the police report, two suspects - Jamail Riggins, 27, and Terry White, 26, - sped from the scene in a 1993 Dodge Dynasty. A minor child was also in the vehicle. A chase ensued and ended at Fairmont Homes, where Riggins reportedly fled on foot before being apprehended by Griffin police officers Mike Greene and Matt Clanton.
Confiscated were 48.92 gross grams of marijuana broken up and bagged in small bags, $860 in cash, and a .380-caliber semi-automatic pistol. Charges included possession of marijuana; possession of marijuana with the intent to sell; possession of a weapon during the commission of a crime; carrying a pistol without a license; and cruelty toward a child.
In the second incident, officers responded at 6:05 p.m. to a shots fired call in the area of Eighth and Tinsley streets. A foot chase by officer Chip Johns led to the arrest of Thadeas Jamar McCrary, 19. Three other suspects were also arrested. They were Kiedrick Kiev Menton, 18, Dremarcus Deante Barkley, 17, and Keevon Dontrece Pope, 18.
According to witnesses, the four suspects went to 550 N. Eighth St. and asked for Lamar Carr. When they were told Carr was not at home, witnesses alleged the suspects made threats, fired shots, and continued to fire shots after leaving the house.
The suspects were charged with firing a weapon; obstruction of an officer; carrying a weapon; and making terroristic threats.


text:
Looking for something to do that is relaxing and enjoyable to start out your week twice a month? The West Allis Public Library has much to offer the community, and among those offerings are the free Leisure Timers programs which occur on the second and fourth Mondays of the month,(except for Holiday weeks).
Leisure Timers programs are for adults who enjoy viewing films and slides and listening to talks relating to travel, history, and other subjects of interest. Presentations begin at 10:00 a.m. and last for about an hour. Below is the upcoming calendar for the remainder of the year:
August 27: Paula Friedman from the Wisconsin Humanities Council presents "Life's Topsy-Turvy Journey: Stages and Ages in Literature and Film" (Slides)
September 10: Tony Busalacchi presents "Berlin Today" (Slides)
September 24: "The Perfect English Village" (British Heritage Collection) (DVD)
October 8: Janet and Carl Klein present "Thailand: Travels, Temples, and More!" (Talk & Video)
October 22: "Penguins: The Birds that Wanted to Be Fish" (DVD)
November 12: Allan Heninger presents "South Dakota, Wyoming, Southeastern Montana: Various Landmarks and Sites" (Slides)
December 10: "Alaska's Wild Denali" (Denali National Park) (DVD)
(No programs on November 26 and December 24 due to Holidays)
ALL ARE WELCOME!!
Your link to the biggest stories in the suburbs delivered Thursday mornings.
Enter your e-mail address above and click "Sign Up Now!" to begin receiving your e-mail newsletter Get the Newsletter!
- Help clients plan and prepare for a retirement that is both financially and emotionally successful
- Support Group for Divorced and Separated
- 16U Franklin Flame Fastpitch Wounded Warrior Fundraiser
- 2014 Franklin Lioness Craft Fair Set for Oct. 25; Proceeds Support Scholarships for MATC Students
- SM Historical Society "Decorating for the Holidays" Seminar
- A Nostalgic Afternoon
- Julius Jr. Experience Comes to Greendale at Southridge Mall on Sept. 20
- U.S. News & World Report ranks Alverno College highest in the state in its “Strong Commitment to Teaching” category for the fifth consecutive year
- Oak Creek Public Library Fall Preschool Story Time
- SM Football Boosters Holding 1st Annaul Rocktoberfest


text:
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"Came out great as is... but five words. Two tablespoons of instant coffee. Mix it in with the cocoa, put a warm brownie in a bowl, ice cream on top and it will make you want to slap yo' mamma!"

domain: food