|Numéro de publication||US5146564 A|
|Type de publication||Octroi|
|Numéro de demande||US 07/306,325|
|Date de publication||8 sept. 1992|
|Date de dépôt||3 févr. 1989|
|Date de priorité||3 févr. 1989|
|État de paiement des frais||Payé|
|Autre référence de publication||CA1322612C, DE68926954D1, DE68926954T2, EP0380845A2, EP0380845A3, EP0380845B1|
|Numéro de publication||07306325, 306325, US 5146564 A, US 5146564A, US-A-5146564, US5146564 A, US5146564A|
|Inventeurs||Michael B. Evans, Rueysen Lin, Brian F. Rost, R. Stephen Polzin|
|Cessionnaire d'origine||Digital Equipment Corporation|
|Exporter la citation||BiBTeX, EndNote, RefMan|
|Citations de brevets (15), Citations hors brevets (2), Référencé par (27), Classifications (6), Événements juridiques (6)|
|Liens externes: USPTO, Cession USPTO, Espacenet|
The present application discloses certain aspects of a computing system that is further described in the following U.S. patent applications filed concurrently with the present application: Arnold et al., METHOD AND APPARATUS FOR INTERFACING A SYSTEM CONTROL UNIT FOR A MULTIPROCESSOR SYSTEM WITH THE CENTRAL PROCESSING UNITS, Ser. No. 07/306,837 filed Feb. 3, 1989; Gagliardo et al., METHOD AND MEANS FOR INTERFACING A SYSTEM CONTROL UNIT FOR A MULTI-PROCESSOR SYSTEM WITH THE SYSTEM MAIN MEMORY, Ser. No. 07/306,326 filed Feb. 3, 1989, abandoned, continued in Ser. No. 07/646,522 filed Jan. 28, 1991; D. Fite et al., METHOD AND APPARATUS FOR RESOLVING A VARIABLE NUMBER OF POTENTIAL MEMORY ACCESS CONFLICTS IN A PIPELINED COMPUTER SYSTEM, Ser. No. 07/306,767 filed Feb. 3, 1989; D. Fite et al., DECODING MULTIPLE SPECIFIERS IN A VARIABLE LENGTH INSTRUCTION ARCHITECTURE, Ser. No. 07/307,347 filed Feb. 3, 1989; D. Fite et al., VIRTUAL INSTRUCTION CACHE REFILL ALGORITHM, Ser. No. 07/306,831 filed Feb. 3, 1989; Murray et al., PIPELINE PROCESSING OF REGISTER AND REGISTER MODIFYING SPECIFIERS WITHIN THE SAME INSTRUCTION, Ser. No. 07/306,833 filed Feb. 3, 1989; Murray et al., MULTIPLE INSTRUCTION PREPROCESSING SYSTEM WITH DATA DEPENDENCY RESOLUTION FOR DIGITAL COMPUTERS, Ser. No. 07/306,773 filed Feb. 3, 1989; Murray et al., PREPROCESSING IMPLIED SPECIFIERS IN A PIPELINED PROCESSOR, Ser. No. 07/306,846 filed Feb. 3, 1989; D. Fite et al., BRANCH PREDICTION, Ser. No. 07/306,760 filed Feb. 3, 1989; Fossum et al., PIPELINED FLOATING POINT ADDER FOR DIGITAL COMPUTER, Ser. No. 07/306,343 filed Feb. 3, 1989, and issued as U.S. Pat. No. 4,994,996 on Feb. 19, 1991; Grundmann et al., SELF TIMED REGISTER FILE, Ser. No. 07/306,445 filed Feb. 3, 1989, now U.S. Pat. No. 5,107,462; Beaven et. al., METHOD AND APPARATUS FOR DETECTING AND CORRECTING ERRORS IN A PIPELINED COMPUTER SYSTEM, Ser. No. 07/306,828 filed Feb. 3, 1989 and issued as U.S. Pat. No. 4,982,402 on Jan. 1, 1991; Flynn et al., METHOD AND MEANS FOR ARBITRATING COMMUNICATION REQUESTS USING A SYSTEM CONTROL UNIT IN A MULTI-PROCESSOR SYSTEM, Ser. No. 07/306,871 filed Feb. 3, 1989; E. Fite et al. CONTROL OF MULTIPLE FUNCTION UNITS WITH PARALLEL OPERATION IN A MICROCODED EXECUTION UNIT, Ser. No. 07/306,832 filed Feb. 3, 1989, now U.S. Pat. No. 5,067,069; Webb, Jr. et al., PROCESSING OF MEMORY ACCESS EXCEPTIONS WITH PRE-FETCHED INSTRUCTIONS WITHIN THE INSTRUCTION PIPELINE OF A VIRTUAL MEMORY SYSTEM-BASED DIGITAL COMPUTER, Ser. No. 07/306,866 filed Feb. 3, 1989, and issued as U.S. Pat. No. 4,895,825 on Jan. 15, 1991; Hetherington et al., METHOD AND APPARATUS FOR CONTROLLING THE CONVERSION F VIRTUAL TO PHYSICAL MEMORY ADDRESSES IN A DIGITAL COMPUTER SYSTEM, Ser. No. 07/306,544 filed Feb. 3, 1989; Hetherington, WRITE BACK BUFFER WITH ERROR CORRECTING CAPABILITIES, Ser. No. 07/306,703 filed Feb. 3, 1989, and issued as U.S. Pat. No. 4,995,041 on Feb. 19, 1991; Flynn et al., METHOD AND MEANS FOR ARBITRATING COMMUNICATION REQUESTS USING A SYSTEM CONTROL UNIT IN A MULTI-PROCESSOR SYSTEM, Ser. No. 07/306,871 filed Feb. 3, 1989; Chinnasway et al., MODULAR CROSSBAR INTERCONNECTION NETWORK FOR DATA TRANSACTIONS BETWEEN SYSTEM UNITS IN A MULTI-PROCESSOR SYSTEM, Ser. No. 07/306,336 filed Feb. 3, 1989, and issued as U.S. Pat. No. 4,968,977 on Nov. 6, 1990; Polzin et al., METHOD AND APPARATUS FOR INTERFACING A SYSTEM CONTROL UNIT FOR A MULTI-PROCESSOR SYSTEM WITH INPUT/OUTPUT UNITS, Ser. No. 07/306,862 filed Feb. 3, 1989, and issued as U.S. Pat. No. 4,965,793 on Oct. 23, 1990; Gagliardo et al., MEMORY CONFIGURATION FOR USE WITH MEANS FOR INTERFACING A SYSTEM CONTROL UNIT FOR A MULTI-PROCESSOR SYSTEM WITH THE SYSTEM MAIN MEMORY, Ser. No. 07/306,404 filed Feb. 3, 1989, now U.S. Pat. No. 5,043,874; and Gagliardo et al., METHOD AND MEANS FOR ERROR CHECKING OF DRAM-CONTROL SIGNALS BETWEEN SYSTEM MODULES, Ser. No. 07/306,836 filed Feb. 3, 1989, abandoned, continued in Ser. No. 07/582,493 filed Sep. 14, 1990.
This invention relates generally to an interface between functional components of a computer system and, more particularly, to an interface between a system control unit of a multiprocessor computer system and an associated service processing unit.
In the field of computer systems, it is common practice for the operation of the computer to be monitored and controlled by an operator working at an operators console. To effect proper control over the computer system, the operator must have the ability to access the system main memory, I/O, and be able to interrupt the operation of any selected CPU. Further, operators access to the memory and I/O units is of particular importance during a system error. In order to determine the cause of the system error, the operator must have access to the memory and I/O units so that they may be examined and the error determined.
A system control unit (SCU) is employed to manage all inter unit communications. The SCU links multiple CPUs to the main memory and to the I/O through a series of independent interfaces. Similarly the SCU is also linked to the operator console through an interface that must be capable of efficiently and reliably handling the data transfers therebetween. The reliability of this interface is of particular importance to ensure that when the operator is determining the cause of a system error, he does not have to contend with additional errors introduced by the interface.
To provide an efficient, reliable interface between a system control unit and a service processing unit, the flow of data between a receive buffer of the system control unit and a transmit buffer of the service processing unit is controlled by: delivering a buffer request handshaking signal from the service processing unit to the system control unit; delivering a buffer grant handshaking signal from the system control unit to the service processing unit in response to receiving the buffer request handshaking signal and the system control unit receive buffer being available to receive data; and delivering the data from the service processing unit transmit buffer to the system control unit receive buffer in a series of consecutive clock cycles.
In a second aspect of the present invention, the flow of data between a receive buffer of a service processing unit and a transmit buffer of a system control unit is controlled by: delivering a buffer full handshaking signal from the service processing unit to the system control unit in response to the service processing unit receive buffer having data contained therein and being unavailable to receive data; delivering a transmit frame handshaking signal from the system control unit to the service processing unit in response to the absence of the buffer full handshaking signal; and delivering the data from the system control unit transmit buffer to the service processing unit receive buffer in a series of consecutive clock cycles.
Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:
FIG. 1 is a top level diagram of a computer system;
FIG. 2 is a general block diagram of the system control unit to, service processing unit interface;
FIG. 3 is a top level block diagram of the service processing unit portion of the service processing unit to system control unit interface;
FIG. 4 is a detailed block diagram of the service processing unit, portion of the service processing unit to system control unit interface;
FIG. 5 is a flowchart of the operations performed by the interface in response to a service processing unit transmission to the system control unit; and
FIG. 6 is a flowchart of the operations performed by the interface in response to a system control unit transmission to a service processing unit.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that it is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Turning now to the drawings and referring first to FIG. 1, there is shown a top level block diagram of a multiprocessing computer system 10 which includes a plurality of central processing units (CPU1-CPU4) 11, 12, 13, 14. The CPUs require access to a shared common main memory 16, as well as, input/output units (I/O) 18. The I/O 18 allows the computer system 10, in general, and the CPUs, in particular, to communicate with the external world. For example, the I/O 18 includes such well known devices as disc and tape drives, communication devices, printers, plotters, workstations, etc.
To take full advantage of the multiple CPUs, the system is configured to allow CPU1-CPU4 to operate in parallel. This parallel operation presents some problems in the form of access conflicts to the shared memory 16 and I/O 18. A system control unit (SCU) 20 is employed to manage these inter-unit communications. The SCU 20 links CPU1-CPU4 to the main memory 16 and to the I/O 18 through a series of independent interfaces. Data requests are received by the SCU 20 from each of the units which, owing to the parallel nature of the CPU operation, occur at unscheduled times, and in particular, at the same time. These requests for data transfer are scheduled according to an arbitration algorithm and processed through the appropriate interface to/from the identified unit.
Inside the CPUs, the execution of an individual instruction is broken down into multiple smaller tasks These tasks are performed by dedicated, separate, independent functional units that are optimized for that purpose.
Although each instruction ultimately performs a different operation, many of the smaller tasks into which each instruction is broken are common to all instructions. Generally, the following steps are performed during the execution of an instruction: instruction fetch, instruction decode, operand fetch, execution, and result store. Thus by the use of dedicated hardware stages, the steps can be overlapped, thereby increasing the total instruction throughput.
The data path through the pipeline includes a respective set of registers for transferring the results of each pipeline stage to the next pipeline stage. These transfer registers are clocked in response to a common system clock. For example, during a first clock cycle, the first instruction is fetched by hardware dedicated to instruction fetch. During the second clock cycle, the fetched instruction is transferred and decoded by instruction decode hardware, but, at the same time, the next instruction is fetched by the instruction fetch hardware. During the third clock cycle, each instruction is shifted to the next stage of the pipeline and a new instruction is fetched. Thus, after the pipeline is filled, an instruction will be completely executed at the end of each clock cycle.
This process is analogous to an assembly line in a manufacturing environment. Each worker is dedicated to performing a single task on every product that passes through his or her work stage. As each task is performed the product moves closer to completion. At the final stage, each time the worker performs his assigned task a completed product rolls of the assembly line.
To accomplish this pipelining of instructions, the CPUs are partitioned into at least three functional units: an execution unit, an instruction unit, and a memory access unit. As its name suggests, the execution unit is ultimately responsible for the actual execution of the instructions. The instruction unit prefetches instructions, decodes opcodes to obtain operand and result specifiers, fetches operands, and updates the program counter.
The memory access unit performs the memory related functions of the CPU. For example, the memory access unit maintains a high-speed cache. The cache stores a copy of a small portion of the information stored in main memory 16 and is employed to increase processing speed by reducing memory access time. The main memory 16 is constructed of lower cost and slower memory components. If the CPU were required to access main memory 16 during each memory reference, the overall speed of the CPU would be reduced to match the main memory speed since the CPU could not execute the instruction until the memory reference had returned the desired data. Accordingly, the cache is constructed of high-speed, high-cost semiconductor memory components, but owing to its high cost, the cache contains considerably fewer storage locations than does main memory. These relatively few high-speed storage locations are used to maintain that portion of main memory which will be most frequently used by the CPU. Therefore, only those memory references which are not maintained in the cache result in access to the main memory 16. Thus, the overall speed of the CPU is improved.
It should be noted that the memory maintained in the cache changes as the program proceeds. For example, the memory locations which are frequently referenced at the beginning of the program may not be accessed in later stages of the program. Conversely, memory locations used frequently by the middle portion of the program may be of little use to the beginning or ending portions of the program. Thus, it can be seen that the contents of the cache needs frequent updates from the main memory 16 and there is a need for efficient communication between the cache and the SCU 20.
The SCU 20 also links the various system units to a service processor unit (SPU) 30 which performs traditional console functions. The SPU 30 has responsibility for status determination and control of the overall operation of the processing system. In particular, the SCU 20 provides the SPU 30 with means for communicating with the plurality of CPUs and provides access to all storage elements within the CPUs. The SPU 30 initiates memory access functions, including reads and writes, as well as, I/O reads and writes. Further, the SPU is also capable of initiating interrupts to any or all of the CPUs.
Efficient communication between all system units ported into the SCU 20 is critical to optimize parallel operation of the computer system 10. I/O can reference memory, the CPUs can reference memory, and the CPUs can reference I/O, but the bulk of the traffic is between the CPUs and the memory. The SCU 20 is the central switching station for all of the message packets throughout the system.
Efficient communication between the SPU and the SCU is similarly critical. System operators working at control consoles, interact with the computer system through the SPU to SCU interface. Thus, to ensure that these operators have reliable, fast access to the CPUs, I/O, and main memory, proper operation of the interface is crucial.
Referring now to FIG. 2, the interface between the SCU 20 and the SPU 30 and the corresponding interface signals are shown. It should be noted that while each of the signals is represented by a single line, the signals are actually transmitted as differential pairs to reduce noise coupling. Further, because the interface employs series terminated emitter coupled logic, none of the lines are bidirectional. The interface includes separate lines in each direction for transmitting the same type of signals. For example, the interface includes eight lines for transmitting data from the SPU to the SCU and eight lines for transmitting data from the SCU to the SPU. Each set of these eight lines allows a full byte of data (8 bits) to be transmitted in a single clock cycle. Also, the data lines are represented by the vector notation [7:0], indicating that the single line represents eight parallel data lines.
While these eight lines are generally referred to as data lines, this is for purposes of convenience only. In addition to providing a data path between the SCU and SPU, the data lines are also capable of delivering the address for memory and I/O reads and writes Further, the data lines can also imbed, within a packet transfer, a command field, as well as, a mask field for data writes. Finally, the data lines can also carry interrupts from the SPU to the SCU and error correction codes therebetween.
The data bus, being only 8-bits wide, can, of course, only transfer a single byte of information within a single clock cycle. However, a data transfer typically involves a quadword of data (8-bytes). Thus, in order to transfer a quadword of data over the 8-bit data bus, one byte of data is transmitted during each clock cycle for eight consecutive clock cycles. Further, since the address is also delivered over this same 8-bit bus and the addressable memory for the instant computer system requires 32-bits to define the complete memory area, the address must be delivered in four consecutive clock cycles. Additionally, the command signal is similarly delivered over this same 8-bit bus, requiring an additional clock cycle to complete the data transfer. Likewise, for write operations from the SPU to the SCU an 8-bit mask field is required to identify those bytes which are valid bytes to be written. Accordingly, a complete transfer of data between the SPU and SCU requires a total of fourteen clock cycles.
The interface configures a memory read/write operation into a fourteen clock cycle packet consisting of the address, data, command, and mask bits arranged according to TABLE I.
TABLE I______________________________________MEMORY READ/WRITE PACKETclock bits bitscycle 7:4 3:0______________________________________0 don't care cmd[3:0]1 addr[29:26] addr[13:10]2 addr[5:2] addr[9:6]3 addr[33:30] addr[21.18]4 addr[25:22] addr[17.14]5 mask[7:4] mask[3:0]6 data[35:32] data[3:0]7 data[39:36] data[7:4]8 data[43:40] data[11:8]9 data[47:44] data[15:12]10 data[51:48] data[19:16]11 data[55:52] data[23:20]12 data[59:56] data[27:24]13 data[63:60] data[31:28]______________________________________
In a memory read-write operation, the data bus is cycled fourteen times, beginning at cycle 0 with the upper 4-bits unspecified and the lower 4-bits containing a 4-bit command field. Thereafter, in cycle 1, transmission of the 32-bit address is begun by delivering bits 29:26 and 13:10. The information contained in the remaining twelve cycles are evident from an examination of TABLE I.
As discussed previously, in addition to memory read and write operations, the interface also performs I/O read and write operations. Like the memory packet transfer, the I/O transfer is also accomplished in fourteen clock cycles. The organization of the transfer packet is altered over that shown in TABLE I and corresponds to the format shown in TABLE II.
TABLE II______________________________________I/O READ/WRITE PACKETclock bits bitscycle 7:4 3:0______________________________________0 don't care cmd[3:0]1 addr[29:26] addr[13:10]2 addr[5:2] addr[9:6]3 addr/mask[33:30] addr[21:18]4 addr[25:22] addr[17:14]5 must be zero must be zero6 don't care data[3:0]7 don't care data[7:4]8 don't care data[11:8]9 don't care data[15:12]10 don't care data[19:16]11 don't care data[23:20]12 don't care data[27:24]13 don't care data[31:28]______________________________________
TABLES III and IV respectively represent the organization of an error correction code (ECC) packet transfer and an interrupt command packet transfer.
TABLE III______________________________________ECC COMMAND PACKETclock bits bitscycle 7:4 3:0______________________________________0 don't care cmd[3:0]1 addr[29:26] addr[13:10]2 addr[5:2] addr[9:6]3 addr[33:30] addr[21:18]4 addr[25:22] addr[17:14]5 don't care don't care6 addr[29:26] addr[13:10]7 addr[5:2] addr[9:6]8 addr[33:30] addr[21:18]9 addr[25:22] addr[17:14]10 mdp1syn[7:4] mdp0syn[7:4]11 mdp1syn[3:0] mdp0syn[3:0]12 mdp1syn[15:12] mdp0syn[15:12]13 mdp1syn[11:8] mdp0syn[11:8]______________________________________
The address field of the ECC command packet contains the high order 32-bits of the 34-bit address where an ECC error was detected. The syndrome field contains the 32 bit error syndrome for the failed address. This error syndrome allows the SPU to perform double bit detection and single bit correction on data that was previously transferred over the SCU to SPU interface and received a bit error.
TABLE IV______________________________________INTERRUPT COMMAND PACKETclock bits bitscycle 7:4 3:0______________________________________0 ID[3:0] cmd[3:0]1 don't care don't care2 don't care don't care3 don't care don't care4 don't care don't care5 don't care don't care6 don't care don't care7 don't care don't care8 don't care don't care9 don't care don't care10 don't care don't care11 don't care don't care12 don't care don't care13 don't care don't care______________________________________
Within the interrupt command packet, the 4-bit ID field indicates which of the four CPUs is to be interrupted upon receipt of this packet. Bit 4 corresponds to CPU0, bit 5 corresponds to CPU1, bit 6 corresponds to CPU2, and bit 7 corresponds to CUP3. If, for example, the data presented at bits 7:4 of clock cyclo 0 is 0001, then CPUO is to be interrupted according to the command field.
Within the four tables, the command field is consistently shown as a 4-bit field transmitted as the lower 4-bits in the 0 clock cycle. Depending upon the direction of the transfer, the command field codes assume different definitions. Command code transmitted from the SPU to the SCU performs a different function than the same code transmitted from the SCU to the SPU. For example, the command field definitions for an SCU to SPU transfer are represented in TABLE V.
TABLE V______________________________________SCU to SPU COMMANDScode command______________________________________0000 READ REGISTER0001 WRITE REGISTER0010 RETURN MEMORY READ0011 RETURN I/O READ0100 RETURN READ ERROR0101 WRITE ERROR REGISTER0110 READ LOCK DENIED______________________________________
READ REGISTER is a command issued by the SCU when it desires to read a console register that is physically located in the console subsystem. This command uses the I/O read/write packet format shown in TABLE II.
WRITE REGISTER is a command issued by the SCU when the SCU wishes to write to a console register that is physically located in the console subsystem. Like the READ REGISTER command the I/O read write packet format shown in TABLE II is used.
RETURN MEMORY READ is a command issued by the SCU when the SCU returns read data that was requested via a previous read request that referenced memory space. This command uses the memory packet format shown in TABLE I.
RETURN I/O READ is a command issued by the SCU similar to the RETURN MEMORY READ except that the data request referenced I/O space rather than memory space. This command uses the I/O read write packet format shown in TABLE II.
RETURN READ ERROR is a command issued by the SCU to notify the SPU that read data that was requested via a previous read request encountered an error condition. This command is valid whether the previous read request referenced I/O or memory. An error condition can result, for example, from a reference to a memory location that does not exist. This command uses the memory packet format shown in TABLE I.
WRITE ERROR REGISTER is a command issued by the SCU to report an ECC incident to the SPU. This command used the ECC command packet format shown in TABLE III to return the address where the error was detected and a syndrome for correcting the error.
READ LOCK DENIED is a command issued by the SCU to notify the SPU that a read lock request that referenced memory spaced encountered an existing lock. Thus, the requested data will not be returned. This command uses the memory packet format shown in TABLE I.
Alternatively, the command field definitions for an SPU to SCU transfer are represented in TABLE VI.
TABLE VI______________________________________SPU to SCU COMMANDScode command______________________________________0000 MEMORY READ REQUEST0001 MEMORY WRITE0010 MEMORY READ LOCK REQUEST0011 MEMORY WRITE UNLOCK0100 I/O READ REQUEST0101 I/O WRITE0110 REGISTER RETURN READ0111 INTERRUPT TRX1000 INTERRUPT TTX1001 INTERRUPT SRX1010 INTERRUPT STX1011 INTERUPT PF1100 CONSOLE HALT1101 KEEP ALIVE1110 CONSOLE SPARE INTERRUPT1111 CONSOLE SPARE INTERRUPT______________________________________
MEMORY READ REQUEST is a command issued by the SPU to retrieve data from a valid memory address in main memory. This command uses the memory packet format shown in TABLE I.
MEMORY WRITE is a command issued by the SPU to write data to a valid memory address in main memory. This command uses the memory packet format shown in TABLE I.
MEMORY READ LOCK REQUEST is a command issued by the SPU to read lock a valid memory address. This command uses the memory packet format shown in TABLE I.
MEMORY WRITE UNLOCK is a command issued by the SPU to write unlock a valid memory address in main memory. This command uses the memory packet format shown in TABLE I.
I/O READ REQUEST is a command issued by the SPU to read a valid I/O address. This command uses the I/O read write packet format shown in TABLE II.
I/O WRITE is a command issued by the SPU to write data to a valid I/O address. This command uses the I/O read write packet format shown in TABLE II.
REGISTER RETURN READ is a command issued by the SPU when the SPU is responding to a previous READ REGISTER REQUEST from the SCU. The SPU issues this command and presents the requested data using the I/O read write packet format shown in TABLE II.
INTERRUPT TRX is a command issued by the SPU to interrupt one or more selected CPUs in response to a console terminal receive. This command uses the interrupt packet format shown in TABLE IV.
INTERRUPT TTX is a command issued by the SPU to interrupt one or more selected CPUs in response to a console terminal transmit. This command uses the interrupt packet format shown in TABLE IV.
INTERRUPT SRX is a command issued by the SPU to interrupt one or more selected CPUs in response to a console storage receive. This command uses the interrupt packet format shown in TABLE IV.
INTERRUPT STX is a command issued by the SPU to interrupt one or more selected CPUs in response to a console storage transmit. This command uses the interrupt packet format shown in TABLE IV.
INTERRUPT PF is a command issued by the SPU to interrupt one or more selected CPUs in response to an impending power failure. This command uses the interrupt packet format shown in TABLE IV.
CONSOLE HALT is a command issued by the SPU to interrupt one or more selected CPUs to halt the operation of that CPU. This command uses the interrupt packet format shown in TABLE IV.
KEEP ALIVE is a command issued by the SPU to interrupt one or more selected CPUs to prevent a "keep alive" time out from occurring This command uses the interrupt packet format shown in TABLE IV.
The remaining command codes 1110 and 1111 are available for use as console interrupt commands.
Referring once again to FIG. 2, in addition to the eight parallel data lines, the interface includes a single data parity line for each group of eight data lines transferred in each direction. The data parity is odd and is synchronously read along with each byte of data. Thus, the 14-byte transfer results in fourteen data parity bits being sampled, one at each clock cycle.
In order to synchronize the operation of the SCU and SPU, a common clock signal is used. Preferably, the SCU clock signal is delivered over the interface to synchronize all data transfers therebetween.
Both the SPU and the SCU possess three handshaking signals to facilitate the transfer of data between the units. In order to reduce the possibility of delivering data to a unit that is unprepared to receive that data, handshaking communication between the two units is implemented. Accordingly, each unit has three handshaking signals and a parity signal on their three handshaking signals. For example, the SPU includes a 14-byte buffer for receiving and temporarily storing a 14-byte data transfer. Until the SPU can assimilate the data in this buffer, it cannot receive additional data transfers. Accordingly, the SPU asserts its BUFFER FULL handshaking signal as long as its buffer remains full and unavailable for further data. The SCU monitors the BUFFER FULL signal and does not initiate additional data transfer until the BUFFER FULL signal is deasserted. Once the SPU buffer becomes available, the SCU asserts a TRANSMIT FRAME handshaking signal to advise the SPU that, for the next fourteen clock cycles, valid data will be present on the SCU to SPU data lines.
Data transfers in the opposite direction, from the SPU to the SCU, are similarly effected. When the SPU is prepared to transmit data to the SCU, the SPU generates a BUFFER REQUEST handshaking signal which the SCU ultimately responds to by delivering its BUFFER GRANT handshaking signal. This BUFFER GRANT signal is only delivered when the SCU has freed its 14-byte input buffer to receive data from the SPU.
The single line handshaking parity signals delivered by both the SPU and SCU are generated synchronously with each individual handshaking signal. Without these parity signals the risk of erroneous data transfer is increased. By providing the odd parity signal with each handshaking signal, the reliability of data transfer is greatly enhanced.
Referring now to FIG. 3, a top level block diagram of the SPU portion of the SPU to SCU interface is shown. A control state machine 40 effects overall control of the SPU portion of the interface. A 14×8 receive and transmit buffer 42, 44 are respectively connected to receive the 14-byte data transfer from the SCU and to transmit the 14-byte data transfer to the SCU. The 8-bit data input lines are connected through a demultiplexer 46 to the receive buffer 42. The select lines to the demultiplexer 46 are controlled by the state machine 40 to increment through byte locations 0-13 on corresponding clock cycles 0-13. In this manner the fourteen buffer locations are consecutively filled with the 14-bytes of data.
The outputs of the receive buffer 42 are connected to an array of 64-bit registers 48 that, depending upon the value of the command code, receive the actual data bits 0:63. The command that the SCU intends for the SPU to execute ultimately determines which of the registers in the array of registers 48 is loaded with the data bits.
As each byte of data is received from the SCU, it is not only delivered to the receive buffer 42, but it is also routed to parity checking hardware 50 that combines the 8-bit data signal and the data parity signal to determine if any errors occurred during the transmission. The results of the parity checking hardware 50 is communicated to the state machine 40. A parity error causes the state machine 40 to generate the parity error handshaking signal.
The transmit buffer 44 is connected to the array of registers 48 through a multiplexer 52. The select inputs to the multiplexer 52 are controlled by the state machine 40 to select one of the array of registers 48. Which register is selected is a function of the operation desired by the SPU. Thus, the SPU initiates the data transfer by delivering a control signal to the state machine 40 indicating which register to select via the multiplexer 52.
This loading of the transmit buffer 44 under control of the state machine 40 does not result in the transmit buffer 44 being immediately delivered to the SCU. Rather, the state machine 40 initiates the actual data transfer to the SCU only in response to receiving the BUFFER GRANT handshaking signal from the SCU. In the clock cycle immediately following the BUFFER GRANT signal, the state machine 40 begins producing sequential control signals 0-13 during the next 14 clock cycles. These sequential signals are delivered to the select input of a multiplexer 54 so that the transmit buffer is sequentially unloaded over the next fourteen clock cycles.
In addition to each byte of data being delivered to the SCU, the data is also delivered to parity signal generating logic 56. The parity logic 56 produces the data parity signal that is delivered to the SCU synchronously with the corresponding byte of data.
As discussed previously, data transfer between the SPU and the SCU is synchronized on the SCU clock signal. Accordingly, the SCU clock signal is delivered over the interface and connected to the clock inputs of the receive and transmit buffers 42, 44 and parity logic 50, 56.
Referring now to FIG. 4, a detailed block diagram of the SPU portion of the SPU to SCU interface is shown. The transmit buffer 44 has fourteen 8-bit lines all connected to a multiplexer 54. (The number of bits, carried by respective parallel conductors of a line, are indicated by the numeral 8 next to the double slash symbol "//" intersecting the line.) The multiplexer 54 includes eight 14:1 multiplexers 54-1 through 54-8. The multiplexer 54-1 receives the zero bit input from each of the fourteen buffers. Similarly, multiplexers 54-2 through 54-8 respectively receive bits 1 through 7 of each of the buffers 1 through 13.
The state machine 40 has a 4-bit input line connected to the select input of each of the multiplexers 54-1 through 54-8. In this manner, the state machine 40 is able to select all eight bits of any of the fourteen buffers. For example, to deliver the contents of buffer(1), the state machine 40 delivers the 4-bit signal 0001. The select inputs for each of the multiplexers 54-1 through 54-8 deliver their input line 1, which corresponds to bits 0 through 8 of buffer(1). Therefore, in order for the state machine 40 to consecutively deliver each of the fourteen 8-bit buffers, the select addresses 0000 through 1110 are consecutively delivered in fourteen clock cycles to sequentially deliver the contents of buffer(0) through buffer(13).
The single bit output of each of the multiplexers 54-1 through 54-8 are ganged together and form the 8-bit data signal delivered to the SPU.
As discussed in FIG. 3, this 8-bit data signal is also delivered to the parity generating logic 56. This parity generating logic 56 includes an array of XOR gates to provide a signal that ensures that the number of data bits that are asserted in combination with the parity output signal constitutes an odd number. For example, an 8-bit data signal of 00000011 has an even number of asserted bits (2). Therefore, the parity bit must also be asserted so that an odd number of bits are asserted (3).
This array of XOR gates includes four 2-input XOR gates 50-1 through 50-4 connected to the eight data lines. The outputs of XOR gates 50-1, 50-2 are connected to the inputs of a XOR gate 50-5. Similarly, the outputs of XOR gates 50-3, 50-4 are connected to the inputs of a XOR gate 50-6. The outputs of the two XOR gates 50-5, 50-6 are connected to the two inputs of XOR gate 50-7, which outputs the data parity signal. In this manner, an odd number of asserted data bits results in the data parity signal not being asserted.
Additionally, it should be remembered that a parity signal is also delivered with the three handshaking signals: BUFFER FULL; BUFFER REQUEST; and PARITY ERROR. Accordingly, the parity generating logic 50 also includes an XOR gate 50-8 which has three inputs connected to the three handshaking signals. Correspondingly, XOR gate 50-8 output is asserted when an even number of the handshaking signals are similarly asserted.
The receive buffer 42 is preferably capable of receiving the fourteen cycles of data and consecutively placing that data in each of its fourteen 1-byte buffers. In order to accomplish this, a demultiplexer 46 is disposed intermediate the data input and the fourteen 1-byte buffers. The demultiplexer 46 includes eight 1:14 demultiplexers 46-1 through 46-8.
The inputs to the demultiplexers 46-1 through 46-8 are data bits 0 through 7 respectively. The fourteen output lines from each of the demultiplexers 46-1 through 46-8 are connected to their corresponding bit position in the fourteen data buffers. For example, demultiplexer 46-1 receives data bit 0. The demultiplexer 46-1 output bits 0-13 are connected to the 0 bit position of buffer(0) through buffer(13) respectively. Similarly, demultiplexer 46-2 receives data bit(1). The demultiplexer 46-1 output bits 0 through 13 are connected to bit position 1 in each of the buffers 0 through 13 respectively.
The select lines to each of the demultiplexers 46-1 through 46-8 are connected to the state machine 40 through a 4-bit line. In this manner, the state machine 40 selects any one of the receive buffers 0-13 to receive the data currently on the data lines. For example, if the state machine 40 desires to load buffer(1) with the data currently present on the data lines, it delivers the 4-bit signal 0001 to the select inputs of the demultiplexers 46-1 through 46-8. This signal on the select lines causes the demultiplexers 46-1 through 46-8 to deliver their input on their output line 1, which is connected to bit position 1 of receive buffer(1).
The state machine 40, during normal operation, consecutively delivers select addresses 0000-1101 to the demultiplexer 46 in fourteen consecutive clock cycles. Thus, the data delivered by the SCU in these same fourteen consecutive clock cycles is loaded into receive buffers 0-13 respectively.
In addition to the data lines being connected to the demultiplexer 46, they are also delivered to the parity checking logic 50. This parity checking logic 50 is substantially similar to the parity generating logic 56. The parity checking logic 50 includes an array of exclusive XOR gates 56-1 through 56-8 that receive the eight data inputs and the data parity of the SCU. These inputs are consecutively combined in the two input exclusive XOR gates to arrive at a signal that is asserted when the number of data and the parity bits are odd and unasserted when the number of data bits asserted and the parity bit are even. When the signal is odd, it indicates that a parity error has occurred. This signal is transmitted to the state machine 40 so that the SPU will begin an error recovery process.
The SCU portion of the SPU to SCU interface is substantially similar in structure to the SPU portion of the interface. Accordingly, the hardware configuration of the SCU portion of the interface is not shown or discussed herein. The difference between the SPU and SCU interface portions lies in the functional implementation of the transfer protocol. This difference, however, is not related to hardware configuration, but is dependent upon the functional implementation of the state machines. Thus, the differences between the SPU and SCU interface portions are most evident and more easily described by flowcharts of procedures followed by the respective state machines. Flowcharts of the data transfer protocols are shown and discussed in conjunction with FIGS. 5 and 6.
Referring now to FIG. 5, a more complete understanding of the operation of the SPU to SCU interface and the interaction of the interface signals may be had by reference to the flowchart representing operation of the overall system and, in particular, the state machine 40. In particular, FIG. 5 discloses the logic flowchart for an SPU transmission to the SCU. Operation begins at block 100 and branches in two directions simultaneously. The two branches represent the simultaneous operation of the state machines present in the SPU and the SCU.
At block 102 the SPU begins by asserting its BUFFER REQUEST handshake signal. At the same time in block 104 the SCU is sampling the BUFFER REQUEST line and as long as that BUFFER REQUEST handshake signal is deasserted, control loops back on to itself and can only advance in response to the BUFFER REQUEST signal being asserted. Therefore, since the SPU asserted the BUFFER REQUEST in block 102, control passes from block 104 to block 106 where the SCU determines if its receive buffer is currently available to receive the 14-byte data packet. As long as the buffer remains unavailable control loops back on to itself until such time as the BUFFER is emptied and this empty status is communicated to the SCU state machine.
Concurrently, the SPU samples the BUFFER GRANT handshaking signal and while that BUFFER GRANT signal remains unasserted the control loops back onto itself and can only advance in response to the BUFFER GRANT signal being asserted. Accordingly, in block 108, once the SCU receive buffer becomes available, control passes to block 110 and the BUFFER GRANT handshaking signal is asserted.
Asserting the BUFFER GRANT signal causes control to pass from block 108 to block 112 where the SPU deasserts the BUFFER REQUEST signal that was originally asserted in block 102.
In the SCU, control has passed to block 114 to where the SCU continually samples the BUFFER REQUEST line, and as long as that line remains asserted, the SCU takes no further action. However, when the SPU deasserts the BUFFER REQUEST signal in block 110, the SCU passes control to block 116 and begins sampling data on the bus.
At blocks 118, 120 the SPU consecutively places each byte of data on the bus for fourteen consecutive cycles. During those 14 consecutive cycles the SCU samples data on the bus at block 116. At the end of the 14th clock cycle the control blocks 120, 122 respectively stop the SPU from placing additional data on the bus and prevent the SCU from sampling additional data on the bus.
Thereafter, in block 124, the SCU checks to determine whether the received data is subject to a parity error. If there is no parity error, control transfers to block 126 where the process effectively ends. On the other hand, if a parity error is detected, control transfers to block 128 and the state machine asserts the parity error handshaking signal. Thereafter, control similarly transfers to block 126 where the process ends for the SCU.
In order for the SPU to be certain that the data transferred properly without parity errors, the control routine pauses at block 130 for two clock cycles while the SCU determines if a parity error is detected in block 124. At the end of this two clock cycle period control transfers to block 132 and the SPU samples the parity error handshaking signal line. The two clock cycle delay is sufficient to allow the parity error checking logic to determine if such a parity error exists. Assuming no parity error exists, then control transfers from block 132 to block 126 where the process also ends for the SPU. On the other hand, assuming a parity error is detected by the SCU, the SPU responds by setting an error flag in block 134 and subsequently transferring control to block 126 to end the SPU process. Ultimately, the parity error is communicated back to the SCU.
Referring now to FIG. 6, the operation of the SPU to SCU interface during an SCU transmission to the SPU is shown by way of a flowchart. The process begins at block 150 and like the process describe in conjunction with FIG. 5, control transfers in two directions corresponding to the SCU and SPU operation. In this scenario, the SPU effectively does nothing until the SCU indicates that it is about to send the desired data. At block 152, the SPU simply continually samples the TRANSMIT FRAME handshaking signal and as long as that signal is deasserted control does not pass further. At the same time, the SCU is also waiting until the SPU frees up its receive buffer to receive the desired data packet. At block 154, the SCU samples the BUFFER FULL handshaking signal and as long as that BUFFER FULL signal is asserted, indicating that the SPU BUFFER is currently unavailable, the SCU loops on itself waiting for the BUFFER FULL signal to become deasserted.
Once the SPU frees up its receive buffer and deasserts the BUFFER FULL handshaking signal, control passes to block 156 where the SCU asserts the TRANSMIT FRAME handshaking signal indicating that in the current clock cycle the SCU will begin transmitting the data packet for the next consecutive fourteen cycles. Asserting the TRANSMIT FRAME signal causes control to pass from block 152 to block 158 of the SPU control routine where the SPU begins sampling data on the bus for the next 14 consecutive cycles. Likewise, for the next 14 consecutive cycles the SCU in blocks 160 and 162 consecutively places those 14 blocks on the data bus.
As the 14th and last byte of the data packet is transmitted by the SCU, control respectively passes from blocks 162, 164 to blocks 166, 168 of the SCU and SPU control routines respectively. At block 166, the SCU simply waits for two clock cycles while the SPU, in block 168, checks to determine if a parity error exists in the transmitted packet of data. If a parity error is detected by the SPU, control transfers to block 170 where the PARITY ERROR handshaking signal and the BUFFER FULL signal are asserted. Conversely, the absence of a PARITY ERROR signal causes control of the transfer to block 172 where the SPU asserts the BUFFER FULL signal. In either case, control then transfers to the block 174 where SPU operation effectively ends for this data transfer.
After the two clock cycle wait at block 166, control transfers to block 176 and the SCU immediately samples the PARITY ERROR handshaking signal. If the parity error handshaking signal has been asserted in block 170 then control transfers to block 178 where the error flag is set and control subsequently passes to the block 174 where SCU operation ends for this data transfer. Alternatively, if the parity error signal was not set in block 170, then control passes from block 166 to block 174 where the process ends for the SCU.
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|Classification aux États-Unis||710/57|
|Classification internationale||G06F15/16, G06F13/42, G06F15/177|
|16 mars 1989||AS||Assignment|
Owner name: DIGITAL EQUIPMENT CORPORATION, A CORP. OF MA, MASS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:EVANS, MICHAEL B.;LIN, RUEYSEN;ROST, BRIAN F.;AND OTHERS;REEL/FRAME:005030/0760
Effective date: 19890306
|7 mars 1996||FPAY||Fee payment|
Year of fee payment: 4
|28 févr. 2000||FPAY||Fee payment|
Year of fee payment: 8
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Owner name: COMPAQ INFORMATION TECHNOLOGIES GROUP, L.P., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DIGITAL EQUIPMENT CORPORATION;COMPAQ COMPUTER CORPORATION;REEL/FRAME:012447/0903;SIGNING DATES FROM 19991209 TO 20010620
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Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., TEXAS
Free format text: CHANGE OF NAME;ASSIGNOR:COMPAQ INFORMATION TECHNOLOGIES GROUP, LP;REEL/FRAME:015000/0305
Effective date: 20021001
|4 févr. 2004||FPAY||Fee payment|
Year of fee payment: 12


text:
* Quart Mason Jar
* Card stock
* Optional: Laminator & Laminating sheets.
* Mason Jar Label Templates:
Strip Left Click-n-Fill
Strip right Click-n-Fill
Graphics are from my CC38: Sewing clipart set.
Open a portrait sheet in your print program.
Import the templates.
Import your chosen background and graphics.
Print on highest setting.
Laminate and cut the mason jar labels out.
Glue the left and right strips together where indicated on the template.
Wrap around the strips around the jar and glue or tape in the back.
Glue or tape the front medallion on the front of the jar.
Glue or tape the jar lid label on the top.
Fill with goodies and it's ready to go! I am including this jar with a basket of fabrics and patterns for a little lady who is wanting to learn to sew.

domain: hobby


text:
The benefits of falling prices for airline fuel will not lead to cuts in fares at WestJet Airlines Ltd., senior executives of the airline say.
"Our plan is not to pass any of it on," WestJet chief executive Gregg Saretsky said Tuesday on a conference call with analysts and reporters.
"This is a supply and demand business and we price according to supply and demand. If demand stays robust we continue the pricing strategy we've had in effect and we will take the opportunity to improve our bottom line."
Mr. Saretsky made his comments after WestJet reported a 6-per-cent jump in final profit last year – to $284-million or 70 cents a share, from $268.7-million or 52 cents a year earlier.
He added that the fuel price is volatile so the airline is not planning massive price reductions.
"I love that answer," RBC Dominion Securities Inc. analyst Walter Spracklin said on the call in response to Mr. Saretsky's comment.
WestJet returned some of the largesse to its shareholders, raising its quarterly dividend to 14 cents a share from 12 cents.
The full impact of lower fuel prices is not evident in WestJet's fourth-quarter or year-end financial results and the reduction is offset by the drop in the value of the Canadian dollar that is caused by that same drop in the price of oil.
The drop in the Canadian dollar offsets about one-third of the drop in the cost of aviation fuel, WestJet officials said.
Fuel costs fell to 81 cents a litre in the fourth quarter from 92 cents a year earlier. But fuel will drop even more dramatically in the first quarter, WestJet forecast, hitting between 63 and 65 cents a litre.
"Given that fuel has been the airline's largest cost item [approximately 30 per cent], the year-over-year impact of the fuel price drop on profitability is substantial," analyst Cameron Doerksen, who follows the company for National Bank, said in a note to clients Tuesday.
The drop in oil prices that is now roiling the Alberta economy has had little impact on demand among travellers, Mr. Saretsky said.
The airline's expansion eastward and to transborder destinations as well as two transatlantic routes means WestJet is much less dependent on business out of its Calgary hub than it was a decade ago, he said.
"Western Canada is bigger than just the province of Alberta," he said.
WestJet does plan to offer periodic fare reductions to attempt to fill the 20 per cent of seats on average that are sitting empty on its planes, he said.
The uncertainty about where the price of oil is going – demonstrated by its sudden rise in recent days – and similar volatility in the value of the Canadian dollar are good reasons for WestJet to hold the line on overall fares, said Robert Kokonis, president of consulting firm AirTrav Inc.
"They have to fill those airplanes," Mr. Kokonis said. "If they can help to stimulate the market keeping fares low that will keep the capacity filled and keep it filled at a reasonable degree of profitability," he said.
Ancillary revenues, such as those from charging travellers fees for their first checked bags, are rising.
They amounted to $13.89 a passenger in the fourth quarter, up 38 per cent from $10.09 a year earlier.

domain: news


text:
A pops Including Capital is basically a national education financing available with the U.S. Services of Studies (DOE) inside the Head Mortgage Program.
Your ple the fresh established man was a keen undergraduate college student and you can enlisted no less than half-time in an experienced system. For many who meet the requirements, a line of credit happens right to their, maybe not he or she. Definition you are guilty of paying the mortgage.
The money to your loan are designed to make it convenient to invest having college or university, otherwise change and you may career college can cost you, which aren’t found in other school funding.
The fresh new Mother or father In addition to financial is sold with a fixed appeal speed away from 7.6% and you will an enthusiastic origination fee away-out of cuatro.248% (because ). If you were to think they tunes a tiny higher, it’s. Interest rates towards the regulators funding simply zero denial payday loans lead lenders simply had an excellent 13% boost in for the last 12 months.
The most Mom Also loan amount you can acquire is similar into cost of attendance (which is dependent on the school), without any other financial assistance your child obtained.
When you’re served with the borrowed funds number you are eligible for, contemplate there is the option to have fun with every, particular, otherwise none from it.
Just how long is Mommy And currency getting?
You’re permitted borrow cash to possess a father Also mortgage for your date your student is actually in this university.
That said, you will need to over and you will submit the new Moms and dad And application for the loan per university seasons.
Can be Mom Together with loans be forgiven?
- You otherwise man die
- You become totally and you can permanently handicapped, otherwise
- The loan comes out within the case of bankruptcy, when you would need to satisfy specific conditions to get the capital used in a personal bankruptcy.
- If your man cannot complete their system since the college closed
- In case your qualification to discover the financial was improperly certified because of the the institution or even improperly formal due to identity theft & fraud & con, otherwise
- In the event the man withdrew out of school, still college or university failed to spend a refund out of currency that it was required to purchase
‘s the daddy otherwise mother And you will financial recognized?
Zero, Mother Plus money aren’t recognized. Meaning you’re responsible for expenses every focus on the investment into the the big big date the bucks is largely paid.
How will you get a father And additionally resource?
If you’re searching to have applying for a father Too because the financing, to begin with your (and your boy) should do is fully gone this new FAFSA.
Once you’ve done and you can inserted the fresh FAFSA, you’ll tune in to right from this new school’s school funding office. Might offer subsequent recommendations on the way to request a beneficial parent And additionally financial.
Particular universities require you to request a pops And you can money during the the fresh , while some are certain to get your bargain myself on the school.
If you are provided capital, you’re had a need to signal a direct Plus Mortgage Expertise Promissory See, which explains the latest conditions and terms of one’s resource. At the same time will act as the new court contract to repay the financing.
It is critical to note that the process can differ aside-off college to school, thus take note of the resources you can get away-away from each institution.
What are the official certification conditions getting a parent Into the introduction to help you mortgage?
Locate a father In addition to financing, you’ll want a reliable guy which is good eager college student student enlisted at the very least 1 / 2 from-big date on the an eligible school. The federal government talks of mom just like the psychological or adoptive father or mother (if you don’t, occasionally, the new stepparent).
- You’re a beneficial Your.S. citizen or licensed noncitizen.
- Possible have indicated monetary you want.
- You are not for the important for the one federal studies fund.
- You can fulfill almost every other standard certification conditions.
Concurrently, you can not have an adverse credit history. Should you get a dad Also mortgage, a credit assessment was did. If your borrowing from the bank efficiency that have a poor history, the loan application is declined.
But not,, in such a circumstance, you actually have choice. When you yourself have extenuating points that you could document, you will be able to desire the decision.
And you can, for people who score a keen endorser which not have an adverse credit score, you may be able to qualify for a father Just like the well because the funding. An enthusiastic endorser takes an equivalent character because a good cosigner, which means that, he could be responsible for settling the loan in the experience you maybe not repay it.
What are the interest levels?
The current interest for the a parent On the other hand to help you financial is eight.6% as there are a keen origination commission regarding 4.248% (at the time of ). I nterest costs for this loan is simply repaired towards the lifetime of the financial, that’s one another good and bad advancement.
This new bad news: the speed into a dad As well as financing is over most recent costs along with other individual lenders whom render individual student education loans. In reality, multiple personal lenders have to offer mother or father money closer to help you 6% getting consumers who have good credit information.
Moms and dad As well as finance was that choice available to let safeguards the expense out-of college or university. However they are not the only solution.
In the event the kid has fatigued almost all their almost every other federal monetary aid and you will scholarship alternatives you can attempt a private student loan. Simply do private student loans offer aggressive (and regularly off) cost, the commission agreements was so much more versatile.
Devote some time to seem doing and attempt certain costs and you will costs. Personal loan providers have a large range from financial methods to fit a good function.
Unclear the place to start? Have a look at prominent picks to find the best loan providers that have private scholar and you may parent fund.

domain: finance


text:
Home Page Tabs
Congressman Ami Bera, M.D. and the 46-member New Democrat Coalition today unveiled the American Prosperity Agenda, a comprehensive policy document aimed at fostering a new era of middle-class prosperity in the United States.
Congressman Ami Bera, M.D. today made the following statement regarding Israeli Prime Minister Benjamin Netanyahu’s address before a Joint Meeting of the Congress:
Today the U.S. House of Representatives failed to vote on a real solution to keep the Department of Homeland Security (DHS) open and instead brought up a stop-gap, temporary measure that failed 224-203. Congressman Ami Bera, M.D. made the following statement:
In The News
The U.S. Supreme Court’s decision in the Hobby Lobby case is a serious step backward for women’s health.
Rep. Ami Bera, D-Elk Grove, and a Republican House colleague from North Carolina, Mark Meadows, introduced a bill Thursday that would extend visas for U.S.-educated foreign doctors to ease a shorta
Now that the historic elections in the world’s largest democracy are complete and India has ushered in a new leadership, we must keep in mind the importance of the United States-India relationship,
Rep. Ami Bera, D-Elk Grove, called Thursday for the resignation of Gen.
U.S. Rep. Jerry McNerney (D-Stockton) and colleagues that represent Sacramento County on May 20 voted for the bipartisan Water Resources Reform and Development Act (WRRDA) of 2013.


text:
- 1 of 1 copy available at Evergreen Indiana.
0 current holds with 1 total copy.
|Location||Call Number / Copy Notes||Barcode||Shelving Location||Status||Due Date|
|Greenwood PL - Greenwood||FICTION Bond Body #9 (Text)||36626103972659||2nd Floor New Adult||Available||-|
- ISBN: 9781945002120
- Physical Description: 170 pages ; 23 cm
- Publisher: [United States] : Stephanie Bond, Inc.,
"A sexy mystery"--Cover.
Round and round we go… Carlotta Wren is still reeling over her parents’ return after a ten-year absence. After putting her life on hold for so long, she’s not sure how to move forward. Her new reality isn’t exactly what she thought it would be, especially considering the altered circumstances of the three men in her life. Until we all fall down… But her best gal pal Hannah is always there to cheer her up, and Hannah has taken up a quirky new sport—roller derby! The matches are a colorful spectacle of bodies maneuvering to score, but the fun stops cold when a dead body rolls onto the scene. Carlotta believes the accident is anything but—especially when skaters’ bodies begin to pile up—in and out of the ring! Could Hannah be next?
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|Subject:||Corpse removals > Fiction.
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Romantic suspense fiction.

domain: library


text:
Saturday, November 16, 2013
We just arrived back in Arizona after the 5 week trip to the states from Alaska.
It was pretty intense with lots of road travel and socializing.
I started out by attending Art Is You in Stamford, Connecticut which put me on the east coast, my former stomping grounds.
I had been wanting to take a class from Michael DeMeng for years, in fact had one canceled here in Arizona that I had signed up for a few years back. He does have online classes too.
I ended up taking two of his classes to make up for that missed one.
What you see here is some of my "Good Brushes Gone Bad" projects.
I learned a lot about some really cool paint applications and new materials that I'm itching to expand on ( notice the baby being birthed beneath the eye)
That eye was from some Bollywood CD trash that I found in India)
This one seemed very Alaskan totemic don't you think?
The face in the middle was from my Uruguay Haul last year and I'd been saving that little stub of a pencil for a long, long time.
Those little paw thingies radiating out from the face are the bottom half of some plastic squeeze toy.
That's the kind of fun you can have in a Micahel DeMeng class!
I used one of my old lampwork dog bead attempts in this one. he always seemed rather Simpsonesque to me.
Using another one of my relaxing babies and a anenomonic lampwork piece I made this cover for this tin in the "Teeny Tiney Shriney" class. I still need to paint where I connected the glass to the top.
I loved learned his technique of coloring mica to make it look really old.
I forget what he called it -"Dead Guy Under Ice" or something to that effect.
I used a lighthouse from a Beech Cliff sardine can to harken back to my Maine roots and since it was my first job at the cannery and all.
I took Cat Kerr's "Tube Soldered Pendants" class and it was my first foray into playing with solder.
I filled the tubes with glass stringer nubs from my lampworking.
It was great to finally meet Cat after years of blogging and she had been a participant of my ill-fated Candace, the traveling doll escapade.
We grieved a bit at the loss of our dear Candace who went missing right before she was to be returned to me after a year of travel 'round the world.
I also took a class with Seth Apter of mixed media fame.
Learned a lot about layering and glazes that I'll be able to put to use. This class was called
"52 Pick Up" which was going to be a mini journal of 52 playing cards that are painted and collaged.
This is front and back cover- reflecting a bit of Indian theme it turns out.
The most challenging class was with Richard Salley and Jessica Jordan as I have only a couple of day long metal smithing classes under my belt. This was also made in one day.
I'm pleased to know that they will be providing workshops during the gem show in Tucson in February.
Little did I realize that the influence of Michael DeMeng would translate so directly into my lampwork upon my return home. I had used murrini on the ends of headpins before but when I used Donna Millard's murrini that I had picked up when I saw her in Alaska these magnificent eyeballs appeared!
I warmed up to the torch making some more matchsticks and have been trying to come up with some batches to list so that I can fill my shop once again.
I am taking custom orders and that's why you might not be seeing so much new stuff appearing quite yet. I am working on it!
After my CT workshop I flew to Dayton and met my bead buddy and jewelry artist extraordinaire Nikki of LoveRoot. She has a new facebook page by the way and is already sharing some of her magic in tutes and such. Go Nikki!
We had a great lunch together, her and her man and mine and she gave me some uber cool handcrafted vodka for my birthday. It just so happened to be her birthday when we met that day.
I gave her some beads of course. I still have some of the vodka left and perhaps she still has some beads left.
From there we set out for the Michigan cottage that has been recently reacquired into my husband's family and hung out with his two sisters and some cousins for several days.
We then drove up and through Canada and down into New England ending up at my Mom's place where my brother and his family from Bali were still staying.
We got to celebrate our respective birthdays a day apart, my brother and I and also did Halloween with his young children
Don't I look older now?...this is right after my birthday
After that we had a whirlwind trip in a southerly direction meeting up with folks at every turn.
We did six states in one day once. All in all I saw 3 sister in laws, 1 brother in law,
1 bro, 2 sis's, 1 mom, 1 aunt, 4 cousins ( one I hadn't seen in 40 years) 3 old high school friends, 1 junior high school friend that I hadn't seen in 40 years, 2 art workshop/ blog friends, one new bead buddy and another Etsy customer. 2 old Alaskan friends, 2 nephews and one niece.
I apologize to those of you that I had hoped to visit along the way but nearing the end of the trip we were getting anxious to head to the barn. Next time, OK?
I only misplaced/left behind one hairbrush and one set of sunglasses and only lost one earring ( one of my own) gained quite a few pounds with the impossibility of avoiding wheat and gluten on the trip which I hope to wear off quickly now that I'm ensconced in Studio South.
I have two new paintings of my brother's to hang in our house here and one of Michael DeMeng's own teeny tiney shrinies for my collection.
Always a little overwhelmed as to where to begin. I missed creating after several weeks without and felt envious when I saw what you all were doing.
Best thing I can do right now is to go melt some glass!


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Traffic Ticket Labour Day Report In Hamilton Ontario
The Hamilton Police Department released a statement indicating that they saw a reduction in the number of tickets issued over the Labour Day long weekend compared to the Civic Holiday in August.
The number of speeding tickets issued during the Labour Day long weekend totalled at 251, a significant decrease from the 375 handed out over the Civic Holiday long weekend. This prompted the police service to publicly thank drivers in the Hamilton area via social media.
Numbers for overall traffic violations were also down. All in all, 298 tickets for offences such as distracted or dangerous driving or driving under the influence were issued over the September 1st long weekend, compared to the 425 issued early in the previous month.
These improvements come shortly after the introduction of a handful of new safe driving programs aimed at reducing speeding and aggressive as well as distracted driving. One of these programs, namely the Vision Zero program, is specifically geared towards minimizing pedestrian and cycling deaths.
In addition to the implementation of these new safe driving programs, the city council has recently made a number of changes to their traffic laws. The month of June saw the reduction of live traffic lanes on Aberdeen Avenue from four to two, where as in July, a maximum speed of 40 km/h was placed on minor and collector roadways in and around residential neighbourhoods.
These programs and changes are in response to the 700 complaints the City of Hamilton claims to receive annually regarding speeding and aggressive driving in residential roadways.


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Toronto Gas Prices Are About To Be The Lowest They've Been Since Last Spring
If you have any weekend travel plans, you might want to wait until Friday to fill up your tank. According to gas analysist Dan McTeague, the GTA will see prices at the pump that have not been this low since March 2019. Toronto gas prices will be going down by two cents on Friday, and another one cent on Saturday.
UPDATE: McTeague revealed on Thursday night that a "last minute rally on the energy markets erased any intra day losses." This means that gas prices will drop to 112.9 on Friday, but will not drop the extra cent on Saturday.EARLIER: However, it's not just the GTA that will be seeing this decrease in fuel. McTeague revealed that Ottawa, Barrie, London, Kitchener-Waterloo, Peterborough, and Niagara are also all expected to be included in the price drop.
So if you need some gas, hold off on filling up those tanks until Friday or Saturday. Currently, most prices are sitting at around 114.9 c/l, which will drop to 112.9 c/l by Friday, Dan McTeague told Narcity. However, not all station prices will be the same. In fact, some fuel spots might be lower than this initial price.
Yet, this reflects the choice of the station's independent owner to drop the prices, and does not correlate with the wholesale price of gas, McTeague told Narcity over the phone. This means that most pumps across the province will have the wholesale retailer price, which is currently 114.9 c/l.
My 2 cents worth: Wait until Friday to fill up as #gasprices will FALL 2 cents a litre @ the ⛽ for #Toronto #GTHA… https://t.co/kwaFHYZx8F— Dan McTeague (@Dan McTeague) 1579732115
By Saturday, Ontarians could be seeing prices as low as 111.9 c/l, which will make any travel plans you had a little cheaper.
"My 2 cents worth: Wait until Friday to fill up as #gasprices will fall 2 cents a litre," McTeague stated in a tweet.
You should because on Saturday we will drop another cent or two to prices we haven’t seen since March of last year 😉 https://t.co/nwYX9JY9ow— Dan McTeague (@Dan McTeague) 1579785113
If you're wondering how big of a drop in fuel costs this weekend will really see, McTeague revealed that the numbers have not been this low since March 6, 2019.
According to GasBuddy's Average Retail Price chart, it confirms that gas prices have skyrocketed over the past few months, with its highest peak being between April and May of last year.
[rebelmouse-image 25966203 photo_credit="Gasbuddy" expand=1 original_size="706x364"]
Thankfully, Ontarians will be able to take a step back into last spring this weekend and enjoy the cheaper gas prices that come with it.


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FAME foundation was established to solicit, encourage and advance the social, emotional and economic wellbeing of women and girls as well as formulate programmes within the framework of national development plan with a view to enhancing the participation of women and advocate for gender parity in the society.
FAME foundation firmly believe that the entire nation, businesses, communities and groups can benefit from the implementation of programs and policies that adopt the notion of women empowerment.
FAME Foundation Calls for an End to Female Genital Mutilation
In commemoration of the International Day of Zero Tolerance for Female Genital Mutilation, FAME Foundation, a not-for-profit organization set up for the empowerment and development of women and girls in Nigeria and Africa, calls on all nations to outlaw all harmful behaviors that affect women and girls, especially female genital mutilation, and to take all necessary precautions, such as enforcing relevant laws, raising public awareness, and allocating adequate resources to safeguard women and girls against this type of violence.
We demand specific protection and support for girls and women who have experienced female genital mutilation as well as for those who are vulnerable, such as migrant and refugee women.
The term “female genital mutilation” (FGM) refers to all practices that result in the partial or complete removal of the external female genitalia or other harm to the female genital organs for non-medical purposes.
FGM is regarded as a violation of girls’ and women’s human rights on a global scale. It represents a severe kind of discrimination against women and indicates entrenched gender inequality.
It violates children’s rights because it almost always involves minors. Additionally, when the surgery results in death, it violates a person’s right to life as well as their rights to physical integrity, safety, and health as well as their right to be free from torture and other cruel, inhumane, or humiliating treatment.
On this day, governments, member states, civil society organizations, development partners, activists, and other relevant stakeholders can raise awareness, renew commitments, and reiterate that female genital mutilation is an unacceptable harmful practice and a violation of women’s and girls’ fundamental human rights.
The International Day of Zero Tolerance for Female Genital Mutilation takes place on February 6, 2023, annually.

domain: sociology


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HOM HO1 Marius Cotton Modal Boxer Brief
Product code: 70220
Those little multicolour tiles on the men's underwear short remind us of tiny pieces of stained glass against a background of dark navy. A male maxi trunk underpant that's wonderfully comfortable.
- 3.5cm waistband is subtly branded
- Lined pouch has a horizontal opening
- Signature ribbon set left on waistline
- Luxury fabric is nicely breathable
47% cotton 47% modal 6% elastane

domain: design


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Growth from lawlessness
The Notorious Georges: Crime and Community in British Columbia’s Northern Interior, 1909 – 1925
by Jonathan Swainger
Vancouver: UBC Press, 2023
$32.95 / 9780774869416
Reviewed by Steven Brown
The potential real estate value of land around the confluence of the Nechako and Fraser Rivers was recognized in the early years of the twentieth century. This was largely due to the proposed Grand Trunk Pacific Railway (GTP) line that would be coming through the area connecting from Prince Rupert on the north Pacific coast to points east as far away as Ontario. The only catch was that one of four Lheidli T’enneh First Nations reserves situated south of the banks of the Nechako and west of the Fraser occupied a large part of the area. The railway survey ran right through the reserve. Lheidli from the Band’s own website means, in the Carrier language, “The People From the Confluence of the River.” “T’enneh” literally means, “The People.”
The fact of the reserve being where it was didn’t stop white settlement. It didn’t matter that the the Lheidli T’enneh had occupied the region for millennia. The perception was the current situation would be resolved in development’s favour at some point. A section of land immediately west of the reserve, Fort George, had originally been the site of a fur trading post established by Simon Fraser in 1807. Agricultural initiatives gradually grew up around it. Much later South Fort George, the regions first bona fide white settlement, grew up around A.G. Hamilton’s general store which opened for business in 1906. It was south of the reserve and directly south of the the Hudson’s Bay Company outpost whose patch of ground bordered the southern edge of the reserve.
British Columbia, established as Canada’s sixth province in 1871, included the vast area of the central interior. Except for the native population, the region had been sparsely populated by white settlers. The railway coming towards the river confluence and the two Georges was likely to provide many opportunities for business and growth. Rivalry grew intense between residents of the communities over which location would be the sight of the new GNP station. As things turned out neither would be. The railway after protracted negotiations offered the Lheidli T’enneh a hundred and twenty-five thousand dollars to vacate their reserve which their chief “reluctantly” accepted and the train station was to be erected in the newly created city of Prince George on the site of the former reserve.
The Notorious Georges is about the rivalry of the two Georges and about the founding of Prince George. It’s also about the drive to tame a wild land with organized townsites and laws, rules, and regulations that needed to be adhered to—civilization as opposed to lawless wilderness. It’s published by UBC Press for the Osgoode Society for Canadian Legal History and is an addition to UBC Press’s Law and Society series. Scholar and University of Northern British Columbia history professor Jonathan Swainger states his intention in his introduction was to write an accessible and engaging work that seeks a wider audience than might be typical for a piece of scholarly research. In this he has admirably succeeded. There’s a lot of compelling history about the region as there is about all of British Columbia and a lot of it is not widely known. Anyone coming to this book has made a good start.
Before the arrival of the railway, the two Georges had developed unsavory reputations. The halls of the provincial government were far away in Victoria and Vancouver, there was no local law enforcement, liquor flowed freely, there was gambling, and a house of prostitution was never far away. The fallout from incidents of obnoxious behaviour and street brawling, things that while not in reality anything worse or more common than some of what went on in many other BC communities before the First World War stuck fast to the Georges as the population grew. An exacerbating factor was the “devil-may-care exploits” of some of the early movers and shakers in the communities who equated self-interest with the public good as well as rival newspapers in Fort George and South Fort George that sensationalized incidents out of proportion to fact.
In those days British Columbia was unreservedly a white man’s province and racist attitudes to anyone who wasn’t white were the norm. If you were Indigenous, Chinese or black (and Prince George did have a small black community), or, worst of all, a “half-breed,” you were a tolerated and, perhaps, in some way, useful non-entity but there was no question about your status in the community. Unsurprisingly, whatever skullduggery or bad behaviour was laid at the door of the non-entities was being perpetrated almost wholly by white men. As the author states, “Simply put, the whole of British Columbia was a boozy, truculent and unapologetically racist place well into the 1930s.”
In 1911, the Lheidli T’enneh began their removal to a habitation named Shelley up the Fraser River from their former reserve which itself had only been established in 1883. The site of Prince George was subsequentially laid out. Incorporation followed in 1915. Charles M. Hays, president of the Grand Trunk Pacific, was determined to cut Fort George and South Fort George out of any big financial benefit from the establishment of the railway. He wanted the railway to be the chief beneficiary of commerce. Positioning his station in a brand new townsite would go a long way to ensuring that. However, expectations that the new railway would be a money maker didn’t pan out. Insufficient traffic bankrupted the GNP in 1919. The line was taken over by Canadian National Railway.
Law enforcement. Yes. This was another perception that developed, that the law needed to be here. The British Columbia Provincial Police (disbanded 1950) had been around since 1858. South Fort George gained one BCPP constable in 1910, the same year the provincial Liquor Act became law. No one in the area had obtained a license but the market for liquor didn’t go away. The Northern Hotel when it opened in South Fort George managed to secure a liquor license and sported a ninety-four foot bar with twelve bartenders. The place was usually packed. The hotel burned down but was rebuilt.
The first constable in South Fort George, Frederick Gosby, didn’t last long. He couldn’t get paid what he felt he was worth and quit to become a fisheries inspector. Another lone constable was brought in but didn’t last long either before a promotion sent him to Hazelton. The size of the police force doubled to two men after that. A temporary jail had been constructed on the Hudson’s Bay Company land. Sheds borrowed from the approaching railway project were used as “detention” sheds in both Fort George and South Fort George.
Newly incorporated Prince George established its own police force. This didn’t deter the BCPP from having a presence too which generated confusion as to who was to do what. The BCPP represented provincial government authority and their members in Prince George aside from office work did very little actual policing. The war reduced the number of people needing policing and the number of police. The reduction in police numbers was halted by the introduction in 1917 of prohibition in British Columbia. Prohibition wasn’t much loved by the populace and not much adhered to whenever possible but the job of the police was to enforce the law. Prohibition, having created more problems than it solved, was repealed in 1921. The provincial government took over the liquor business, instituting a monopoly. If you bought liquor in British Columbia by law it had to come through the government who collected a tax on every bottle.
The author takes deep dives into the primary sources of the local newspapers of the time for a great deal of his material, The Fort George Tribune, the “combative” Fort George Herald in South Fort George and the Prince George Citizen, detailing the rocky road of Prince George governance and of policing as affected by men with local authority who often were amateurs or just plain incompetent. Mayoralty was for one year terms which wasn’t an aid to progress or stability. There was the war and the global Spanish Flu epidemic, 70% of whose victims in the Prince George area were First Nations.
Distance from the centres of power in the province resulted in what the author calls a sense of “mulishness” in the attitude of Prince George to those centres of power. The feeling was one of a lack of respect and of being dictated to by people who thought they knew what was best for the locals on the far away, not-especially-important frontier. There was upset over the fine government building that had been built in Prince Rupert in 1921 and the same not being planned for Prince George. This mulishness continued but the city endured. It’s quite a story and quite a complicated one. Dr. Swainger has done a masterful job organizing a mountain of material into a coherent and very interesting saga.
In my own deficient knowledge of BC history, for instance, I was unaware there’d been sternwheelers on the upper Fraser River and connected bodies of water as far north as Takla Lake north of Vanderhoof all the way down to Soda Creek south of Quesnel, as well freight laden “scows” piloted by doughty males steering with long poles. It sounds potentially perilous as well as terribly grand and romantic. I was shocked.
“Books have ruined my life,” jokes Steven Brown. A professional in the book trade for years he’s managed to retain a deep and abiding passion for good books and first rate literature. He was born in Saskatchewan and grew up in Ontario and British Columbia. Vancouver is home these days. His reviews have appeared in Canadian newspapers, a literary review or two and he has donated reviews to good causes. [Editor’s note: Steven has reviewed books by Bruce McLellan, Gail Anderson-Dargatz, Patrik Sampler, Taslim Burkowicz, and Rhonda Waterfall.]
The British Columbia Review
Interim Editors, 2023-24: Trevor Marc Hughes (non-fiction), Brett Josef Grubisic (fiction)
Publisher: Richard Mackie
Formerly The Ormsby Review, The British Columbia Review is an online book review and journal service for BC writers and readers. The Advisory Board now consists of Jean Barman, Wade Davis, Robin Fisher, Barry Gough, Hugh Johnston, Kathy Mezei, Patricia Roy, Maria Tippett, and Graeme Wynn. Provincial Government Patron (since September 2018): Creative BC. Honorary Patron: Yosef Wosk. Scholarly Patron: SFU Graduate Liberal Studies. The British Columbia Review was founded in 2016 by Richard Mackie and Alan Twigg.
“Only connect.” – E.M. Forster

domain: history