|Publication number||US5426754 A|
|Application number||US 07/889,022|
|Publication date||Jun 20, 1995|
|Filing date||May 26, 1992|
|Priority date||May 26, 1992|
|Publication number||07889022, 889022, US 5426754 A, US 5426754A, US-A-5426754, US5426754 A, US5426754A|
|Inventors||Donald G. Grice, Donald W. Price, Reza S. Raji|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Non-Patent Citations (4), Referenced by (23), Classifications (18), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
In multiple processor systems that use first level processor caches there exists what is known as the data integrity or cache coherency problem where the contents of memory storage and the corresponding copies of this data existing in the several caches must be kept consistent. Inconsistency can arise whenever one processor stores either into memory or into its local cache without ensuring that all other copies of memory data (in other processors' caches) are either marked invalid. (obsolete) or are concurrently updated. This invention addresses this problem for high performance, supercomputer systems with multiple execution units.
In high performance multiple processor systems comprised of processors wherein each processor contains one or more Scalar Execution Elements (SXE) and one or more Vector Execution Elements (VXE) it is highly advantageous for the SXEs to access memory through a first level data cache and for the VXEs to fetch and store data directly to system memory bypassing the data cache. This is particularly true in a "tightly coupled" MP (multiprocessor) system designed primarily for large high end scientific and engineering applications and high performance (supercomputers).
The above is true for several reasons. A cache is required for performance on scalar only applications and for those scalar portions of primarily scientific applications. For highly parallel applications dominated by VXE operations the data cache capacity, bandwidth, and cache blocking mechanisms can severely limit performance, and it is important that the VXEs "pipeline" operand requests directly to and from system memory. This introduces two significant system design requirements:
(a.) Due to VXE traffic, the system memory design must accommodate a higher number of operand requests than in a design where all requests go through a first level data cache.
(b) In order to ensure "cache coherency" the system must provide a centralized Data Integrity mechanism capable of servicing a very high VXE request traffic rate.
Present multiple processor supercomputer designs avoid the cache coherency problem either by avoiding the inclusion of conventional scalar data caches in their design, or if they have caches, impose the coherency solution on the software operating system and/or application. If designed without a cache, the memory access is minimized by using an expensive high performance static KAM memory chip. These approaches limit the range of applications for which these designs produce high performance results and/or introduce considerable added complexity in software. Prior multiple-processor systems have used processor-private store-in L1 caches, and they have maintained the coherence of data in the system by using a set of copy directories, which are copies of all L1 cache directories. Each processor's fetch request is cross-interrogated in the copy directories of all other processors to find if any other processor has a copy of a requested data unit. This process assures that only one processor at a time can have exclusive (EX) ownership for writing in a data unit in the system. Only the one processor the at has exclusive ownership of a data unit is allowed to write into the data unit. A data unit can also have public ownership (previously called read only (RO) authority) which allows all processors to read (fetch) the data unit, but prohibits all processors from writing into the data unit.
The data coherence problem is simpler with a store-through type of cache, which requires all stores made in the L1 cache also be concurrently made in a backing memory. The memory backing the L1 private processor caches may be an L2 shared memory, or it may be the L3 main memory. The shared L2 cache may be store-in or store-through, but preferably is store-in to reduce the store bus traffic to main memory.
The store-in type of cache has been used in computer systems because it requires less bandwidth for its memory bus (between the memory and the cache) than is required by a store-through type of cache for the same frequency of processor accesses. Each cache location may be assigned to a processor request and receive a copy of a data unit fetched from system main memory or from another cache in the system. With a store-in cache, a processor stores into a data unit in a cache location without storing into the correspondingly addressed data unit in main memory, which causes the cache location to become the only location in the system containing the latest changed version of the data unit. The processor may make as many stores (changes) in the data unit as its executing program requires. The integrity of data in the system requires that the latest version of any data unit be used for any subsequent processing of the data unit.
A store-through type of cache is used only for fetching, and maintains the latest version of their accessed data units by having all store accesses change both the processor's store-through cache as well as the same data unit in a memory (another cache or main storage) at the next level in the system storage hierarchy. But the store-through characteristic of such caches do not solve the coherence problem in the system since another processor's store-through cache could contain an older version of the same data unit. Therefore, cross-interrogation of the contents of private processor caches in multiple processor systems is needed whether they are store-in or store-through when a new request is being fetched into a processor cache.
Exclusive ownership (authority to change a cache data unit) is assigned to any processor before it is allowed to perform its first store operation in a data unit. The assignment of processor ownership has been conventionally done by setting an exclusive (EX) Flag bit in a cache directory (sometimes called a tag directory) associated with the respective data unit in the cache. The EX flag bit's ON state typically indicates exclusive ownership and the off state of the EX Flag bit indicates public ownership (called. "read-only authority"). Exclusive ownership by a processor allows only it to store into the data unit, but public (read-only) ownership of a data unit does not allow any processor to store into that data unit and it is up to all processors in the system to read that data unit (which can result in multiple copies of the non-changeable data unit in different processor caches in the system).
Typically, a cache Fetches data units from its storage hierarchy on a demand basis, and a processor cache miss generates a fetch request which is sent to the next level in the storage hierarchy for fetching the data unit.
A store-in cache transmits its changed data units to main memory under control of cache replacement controls, sometimes called the LRU controls. Replacement of the data unit may occur when it has not been recently accessed in the cache, and no other cache entry is available for the new request. This replacement process is sometimes called "aging out" when a least recently used (LRU) entry is chosen to be replaced with a new request. The replacement controls cause the data unit (whether changed or not) in the selected entry to be replaced by another data unit (Fetched as a result of a cache miss). When the data unit to be replaced in the cache has been changed, it must be castout of the cache and written into another place such as main memory before it is lost by being overwritten by the newly requested data unit being fetched From main memory. For example, a processor may request a data unit not currently in the cache, which must be fetched from main memory (or from another cache) using the requested address and stored in the newly assigned LRU cache location. The cache assignment of a location for the new data unit will be in a cache location not in current use if one can be found. If all of the useable cache locations are currently occupied with changed data units, then one of them must be reassigned for the new request. But before the new data unit can be written into the cache location, a castout to main memory is required of the updated cache data unit in that location. The castout process must then be used before the new data unit is written into the cache. The castout data unit has its ownership changed from an exclusive processor ownership to a main memory ownership.
If a data unit is not changed in the cache, it is merely overlayed to replace it without any castout, since its backing copy in main memory is identical.
U.S. application patent No. 4,394,731 to Flusche et al teaches the use of an exclusive/read only (EX/RO) flag in each entry in each private processor store-in cache directory for data coherence control in a computer system. A copy directory was provided for each processor's private L1 directory to identify the respective processor ownership of all data units currently in its cache, and the set of all processor copy directories was used to recognize which processor owned, or was publicly using, a data unit being requested exclusively by another processor in the system. Cross-interrogation (XI) was the process used among the copy directories to identify which, it any, processor had exclusive or public ownership of any data unit, which was done by comparing the address of a requested data unit with addresses in all copy directories. If the requested address was found in a copy directory, it identified a processor cache having that data unit. And cross-invalidation signaling was done from the identified processor's copy directory to its L1 cache to invalidate the entry for that data unit before passing the ownership of the data unit to another processor's cache.
This XI process assured exclusivity of a data unit to only one processor at a time by invalidating any copy of the data unit found in any other processor's private cache.
Hence, only one of the plural processors in a multiprocessing (MP) system can have exclusive ownership (write authority) at any one time over any data unit. The exclusive ownership over any data unit may be changed from one processor to another when a different processor requests exclusive ownership. The prior mechanism for indicating exclusive ownership for a processor was to provide an exclusive (EX) flag bit in each L1 directory entry in a processor's private L1 cache; and the EX bit was set on to indicate which of the associated data units were "owned" by that processor. The reset state of the EX flag bit indicated public ownership, which was called "read only authority" for the associated data unit that made it simultaneously available to all processors in the system. Thus, each valid data unit in any processor's private LI cache had either exclusive ownership or public ownership.
The copy-directory XI technique of prior U.S. Pat. No. 4,394,731 automatically assigned the following ownership to a data unit fetched from main storage into a processor's private L1 store-in cache:
1. EX ownership when the data unit is not found in any processor's copy directory.
2. EX ownership when the data unit is found changed with EX ownership in another processor's copy directory. The requested data unit is castout of the other processor's cache before it is fetched into the requesting processor's cache.
3. RO ownership when the data unit is found not changed with EX ownership in another processor's copy directory, and the new request is deemed not likely to change the data unit (fetch request). Also, the found data unit is left in its cache where its ownership is changed from EX to RO.
4. EX ownership when the data unit is found with RO ownership in one or more other processor's copy directories, and the new request is deemed to likely change the data unit (store interrogate request). The found data unit is invalidated in the other processor's cache. This XI operation uses a time-consuming process called "promote to exclusive".
5. RO ownership when the data unit is found with RO ownership in another processor's copy directory. Also, the found data unit is left in its processor's cache with its RO ownership.
6. RO ownership when the data unit is a page table entry found with RO public ownership set in the entry, regardless of the type of processor request.
Designs such as those illustrated in Gannon et al. U.S. Pat. No. 5,265,232, issued Nov. 23, 1993 for "Coherence Control by Data Invalidation in Selected Processor Caches Without Broadcasting to Processor Caches Not Having the Data", although logically solving the cache coherency problem, again limit performance by requiring all memory requests to go through the first level cache as explained above.
Patent application of Bean et al. (Application Ser. No. 07/680,176), filed Apr. 3, 1991, entitled "Ownership Interlock for Cache Data Units" and assigned to the same assignee describes and claims an ownership interlock control for cache data units. It interlocks a change of ownership for an exclusively-owned data unit in a store-in cache with the completion of all stores to the data unit issued by its processor up to the time it responds to a received cross-invalidate (XI) signal caused by another processor requesting the data unit either exclusively or witch public ownership.
The object of this invention is to provide a means and method of solving the cache coherency problem and still allowing "pipelined" operand VXE requests directly to system memory thus preserving the advantages available from scalar data caches and also yielding the advantages of conventional supercomputer designs. With this approach the resulting hardware system design is optimized over a much broader range of applications and does not impose on system software the task of ensuring data integrity.
In accordance with one embodiment of the present invention, the system comprises memory, vector processors and scalar processors with their own cache. The system includes cross-interrogate (XI) means between the scalar processors for assuring the latest copy is stored in the memory and cache. The cross-interrogate means has an XI table that contains the status off the cached lines in the scalar processors. The system includes vector store register devices that record the lines that are currently being stored into by the vector processors for preventing the scalar processors from fetching invalid data.
FIG. 1 is a block diagram or the high performance tightly coupled MP system according to the preferred embodiment of the present invention.
FIG. 2 illustrates the message format on the XI request bus.
FIG. 3 illustrates the message format on the XI response bus.
FIG. 4 illustrates the message format on the release bus.
FIG. 5 is a diagram of the cross-interrogate logic for each interleave.
FIG. 6 illustrates the SXE XI directory logic.
FIG. 7 illustrates the SXE XI directory entry.
FIG. 8 is a logic diagram of the vector storage registers for each CPU.
FIGS. 9A and 9B are respectively the VSR set and VSR reset valid logic
FIG. 10 is a flow chart of the XI mechanism algorithm on receiving a scalar exclusive read only or conditional read only request from an SXE XI request bus.
FIG. 11 is a flow chart of the XI algorithm for a VXE request.
The present invention addresses and solves the requirement of ensuring cache coherency with a cross-interrogate (XI) mechanism capable of servicing very high VXE request traffic rates by providing a set of "VXE Store Register devices" (VSRs) that hold the address of system memory data units (or cache "lines") that a VXE is presently addressing to store data. These data units (DUs) are in increments of the cache line size (e.g. 128 contiguous bytes on 128 byte boundaries). The VSRs and how they are used to provide cache coherency in a multiple processor system are the subject of this invention.
There is an important "prerequisite" for using this invention. The VSR design mechanism must be used in conjunction with a centralized scalar cache invalidate directory method and means similar to that described in the aforementioned Gannon et al. U.S. Pat. No. 5,265,232 owned by the same assignee. That patent has all of its contents fully incorporated herein by reference and is considered part of this application. The aforementioned U.S. Pat. No. 5,265,232 is hereinafter referred to as Gannon et al. Gannon et al. also references patent application of Bean et al., Ser. No. 07/680,176, filed the same day, assigned to the same assignee and entitled "Ownership Interlock for Cache Data Units", all contents also fully incorporated herein by reference.
Gannon et al. describes a cache coherency mechanism wherein all requests to memory from first level caches are funneled through a centralized cache coherency directory (called an XI directory in Gannon et al.). In that application, VXE data requests (assuming that these processors contain VXEs) are funneled through each processor's data cache in a manner identical to any other type of data request.
In Gannon et al. all first level caches use a store through mechanism. That is, each processor stores data into its first level cache and concurrently stores that same data into system main memory. Processor stores are only allowed when the processor cache holds the addressed data "exclusive" Only one processor's cache in the multiple processor system is allowed to hold a cache data unit "exclusive" (having write authority), and if a single processor's cache holds a data unit exclusive then no other cache may hold that line with either exclusive or "read only" authority. However, any number of processor caches may hold a cache data unit with read only authority. Gannon et al. describes several embodiments of a cache coherency mechanism both with (FIG. 1 of Cannon et al.) and without (FIG. 9 of Gannon et al.) a single centralized second level cache. For the sake of simplicity this application will only show one embodiment for this invention wherein there is no second level cache. This is the embodiment of FIG. 9 of Gannon et al. For that embodiment Gannon et al. describes the means and methods for maintaining cache coherency for scalar data requests. Those same means and methods are assumed for scalar data requests in this application.
This invention provides a set of Vector Store Register devices (VSRs) for each Vector Execution Element in the system. Each set of VSRs (e.g. 256 VSRs per set) is associated with one and only one VXE. When the VXE is prepared to do an operand store directly to memory it must first obtain an empty VSR (through the XI Request Bus Interface--see applicants' FIG. 1) and be granted permission by a cross-interrogate (XI) logic (through a XI Response Bus Interface) to store to memory. Permission is only granted after any and all scalar cache holders of the respective cache data unit (e.g. cache line or block) have been marked invalid by the holding caches. Each VSR holds the real address of a cache data unit (DU) or line. Once a VSR has been obtained, the VXE may now store as many operands it has to store in that line or real memory. If the VXE is storing stride 1 (contiguous operands) then up to 16 contiguous FW (full word) operands or 32 contiguous DW (double word) operands may be stored using the same VSR. For strides other than 1, the number of stores "covered" under one VSR will decrease. For a 128 byte cache line size (DU) and strides greater than 16 (for FW operands), or 32 (for DW operands) the VSR is only good for one VXE store. A large set of VSRs are required to allow the VXE to obtain VSRs well before the time the VXE has computed the value of the actual store to memory. Thus, the pre-allocation of VSRs for future stores does not impact performance since the VXE will obtain VSRs well before it is ready to do the actual stores. Furthermore, the VXE has the information required to determine the number of operands "covered" by each VSR and the address to be placed in each VSR by the vector length and stride value contained in the vector instruction.
The obtaining of a VSR for doing one or more vector stores must go through the normal XI request mechanism since a central Data Integrity or Cache Coherency (or XI) Table must be accessed to determine if one or more scalar caches hold the required DU. If there are one or more cache holders, these must be invalidated before the requested VSR is marked as valid. In this respect the request by the VXE to get a VSR and thus obtain permission to write to memory is similar to a normal scalar cache exclusive request described in Gannon et al. When the VXE is done storing to the line of data covered by a VSR, however, the VXE can reset (release or free) that VSR independently of other activity in the XI centralized logic. Thus a single VXE can be concurrently getting one VSR and freeing another. This has the effect of doubling the request handling capacity of the XI logic for VXE traffic. This in itself is a major advantage in using this invention to maintain cache coherency.
Vector fetches need not use a VSR, or in any other way interface to the XI mechanism. Vector operand fetches merely fetch data from system memory without making any request to the Data Integrity logic. This is only possible because the first level scalar data caches are store through and therefore system memory is always logically coherent--that is, the most recent state of data is present in memory. If the caches used a store in algorithm then this would not be true.
In vector processing it is often true that one VXE is operating on, for example, even operands and another VXE is operating on odd operands. It is possible therefore that both VXEs could be simultaneously accessing through their separate VSRs the same line of real memory. The designer has two possible choices here:
(a) To allow both VXEs through their separate VSRs to concurrently store to the same line of real system memory.
(b) To allow only one VXE at a time to store to a given line of memory.
Although either choice is possible and clearly (b) is safest (since both VXEs could be storing to the same locations) we have nevertheless concluded that it would be far better from a performance viewpoint to implement alternative (a). There is little risk that an application would want to store through two separate VXEs to the same operand locations without interlocking that section of memory through the application or system software. Note that although concurrent VXE stores to the same line of memory is thereby allowed, it is not possible to allow any scalar cache to be holding any line or data that is being actively stored to by one or more VXEs (i.e. a line held in an active VSR).
XI requests made by scalar elements for Exclusive or Read Only access to a cache line goes to the XI logic via requests on the XI request bus. The XI logic will, in addition to checking for other cache holders of the at line (as described in Gannon et al.), also check all of the VSR Registers to see if that line is being stored into by any VXE. If that line is held by an active VSR (with the valid bit set on) then the XI logic must delay granting Exclusive or Read Only status for that line until all VXEs have "released" or inactivated that line.
FIG. 1 represents a multiple processor (MP) system 100 containing N central processing units, CPU 1 through CPU N, in which each CPU 1 through CPU N contains, for example, one scalar execution element (SXE) 103 with a private scalar cache 104 and directory 105, and one vector execution element (VXE) 107. The CPU may also contain a private instruction only cache which is read only and holds the CPU's instruction stream. If the CPU does contain an instruction cache, its requests to memory are made on the stone interface as used by the scalar cache and are indistinguishable from a scalar data cache request for read only data. For tile sake of simplicity, the preferred embodiment will not show an instruction cache.
In FIG. 1 each SXE 103 and VXE 107 has a cross-interrogate (XI) or data integrity (DI) request and response interface to the centralized cross-interrogate (XI) mechanism 106. This XI mechanism 106 includes a priority circuit 121, a scalar XI directory 123, vector store register (VSRs) devices 125 and XI response logic 127. SXE and VXE request buses 110 are coupled between the XI mechanism 106 and the SXE 103 and VXE 107 of each CPU. The requests from all the combined SXEs and VXEs of a CPU are separately applied over request buses 110 to priority circuit 121 which may be a queued cross-bar switch. All XI responses from the XI mechanism 106 are multidropped off bus 111 to the appropriate VXEs and SXEs. In addition, from each of the VXEs 107 there is a VSR release bus 113 to the XI mechanism 106 which is used as described previously to provide a release signal to free or reset VSR devices 125 that do not presently contain an active or valid memory line address. The XI directory can be replaced using replacement means 108. The main memory is 101. The store and fetch to and from VXE and from the SXE L1 cache 103 of each CPU 1 through CPU N is through store bus and fetch buses 133. In FIG. 1 all requests for system memory 101 from the SXE 103 are made through the scalar L1 cache 104 interface to memory and all requests from the VXE 107 do not go through a caching mechanism but are made directly to system memory 101. FIG. 1 of this application is a modification of FIG. 9 from Gannon et al. In the present invention, the XI mechanism 106 includes the vector storage register devices 125. In addition, there is the separate release bus 113 directly coupled between the vector execution elements (VXE) 107 and the VSR devices 125.
For M XI interleaves, the memory DUs or lines are divided in such a way that only 1/M of real system memory is referenced by a single XI interleave. The DUs are main memory data units of cache line size (for example, 128 contiguous bytes on 128 byte boundaries), and the DUs addresses refers to the addresses in main memory 101 of these data units (DUs). System memory DU addresses can be assigned to XI interleaves in any logical fashion, but a round robin method is considered preferable.
FIG. 1 also shows a priority circuit 121 which may be a conventional queued cross-bar which connects the XI request buses 110 from the N CPUs to the XI logic 122 for each of the M XI interleaves. Both the SXE 103 and the VXE 107 are coupled to bus 110 via selector 109. VSR release buses 113 from the VXEs 107 bypass the priority 121 since each VSR release bus will connect to every XI interleave. In general there should be sufficient XI interleaves to handle the expected peak traffic from the N CPUs. Each CPU is capable of generating two XI requests per machine cycle (one from the VXE and one from the SXE), however, traffic from the SXE should occur at a much lower frequency (since a request is only made from an SXE on a cache "miss")
The XI request bus 110 contains information fields as shown in FIG. 2 follows:
V=Valid bit to indicate that a request is active on the bus.
VXE=A bit to indicate that the request is from a VXE.
SXE=A bit to indicate that the request is from a SXE.
ID=The identity or the requesting SXE or VXE.
VSR ID=The requested VSR for a VXE request.
DU ADDR=The data unit address (line address) being refenced.
REQ TYPE=An encoded field with SXE request types as follows:
Promote to Exclusive
Conditional Read Only
Remote to Read Only acknowledgement.
Cast Out--referenced line has been removed from the L1 cache.
This message is generated at the vector execution unit VXE 107 or SXE 103 and sent over selector (SEL) 109 and buses 110 and is decoded at the XI mechanism 106. Selector 109 is a multiplexer.
The fields in the XI Response bus 111 are as shown in FIG. 3 and are as follows:
The V, VXE, SXE, ID, DU ADDR, and VSR ID fields as above.
RESPONSE TYPE: A encoded field with response types as follows:
Read Only Grant.
Invalidate addressed DU entry.
Remote addressed DU entry to Read Only.
The response fields are generated at the XI mechanism 106 and sent over common bus 111 and SXE/VXE decoder (DEC) 109a to the VXE 107 and SXE 103. The message is decoded at the SXE 103 or VXE 107.
VXE or VSR Release bus fields of the message are shown in FIG. 4.
V=Valid request to inactivate a VSR is on the bus.
VXE ID=The identification of the VXE making the request.
VSR ID=The identification of the VSR to be inactivated.
This message is sent over the release bus 113, generated at the VXE 107 and decoded at the VSR device 125.
FIG. 5 shows the logic contained within one XI Logic interleave of the XI mechanism. A XI request from either an SXE 103 or VXE 107 is generated in the format of FIG. 2 and presented on the XI request bus 110 via multiplex coupler 109 (FIG. 1) and connects via selector (SEL) 129 to the Scalar XI directory (or XI table) and Logic 123 and a set of VSR devices 125 for each VXE 107 in the system. FIG. 6 is a diagram of the SXE XI directory and logic 123. The request for the SXE XI directory is decoded by the decoder 124 to provide a control to the directory 126. The SXE XI directory 126 holds all entry for each unique cache line held by any scalar cache 103 in the system and is kept accurate by requests sent to the directory over bus 110 whenever there is a change in the cached memory addresses. FIG. 7 illustrates a SXE XI directory entry. The entry identifies the CPU holder ID, the status of Read Only or Exclusive, a valid bit (if valid), and the address. Thus, on any XI request the XI directory 123 is interrogated to determine if the requested DU (or cache line) is held Exclusive or Read Only or not held at all by any scalar cache as discussed in Gannon et al. In the SXE logic 123 interrogation, the high order DU address in each entry is compared with that on the bus at comparator 1129 to determine if there is a compare. The compare status is outputted on status line 130. The addressed directory entry without the address information is provided over bus 135 to the response bus logic 127. Concurrently, with the XI directory interrogation, the DU address in each active (or valid) VSR device 125 is compared against the address presented on the XI request bus 110a. This will then determine if any VXE is currently holding this memory location for ongoing vector stores. Responses to the XI request are encoded at logic 127 in the message format of FIG. 3 and multiplexed onto response bus 111. The XI responses on response bus 111 are decoded at decoders 109a and forwarded to VXE or SXE. Requests that cannot be responded to are put into the recirculation queue 128 under control from the logic 127. When permitted, the selector 129 changes state to allow requests from the queue 128 to be applied to the directory logic and VSRs.
FIG. 8 shows a single set of 16 VSR devices 1251 through 12516 for VXE 1071 wherein VSR devices 1251 through 12516 hold in registers 3011 through 30116 the line address of a line of system memory and a valid bit (or active bit) that determines if the address location is currently being used to store data by VXE 1071. Address compares with the valid bit reset are ignored since that VXE 1071 is not presently storing using that VSR. The valid bit is set when a VSR is obtained by a VXE through the XI request bus 110 and reset via a command from the VXE release bus. The address location currently held in the VSR 3011 through VSR 30116 is compared with the address on the request bus 110 at comparators 3031 through 30316 of the devices 1251 through 12516. No response out of AND gates 3051 through 30516 of the devices 125 occurs unless the valid bit is set and there is the compare. The output from these VSR devices 1251 through 125n is coupled via OR gate 307 to logic 127
There are shown in this example 16 VSR1 devices, 1251 through 12516 per XI interleave. The number of registers per interleave is a design choice dependent on cost/performance trade-offs and VXE design characteristics.
FIG. 9A shows the VSR set valid logic and FIG. 9B shows the VSR, reset valid logic per XI interleave required for the VSR's valid (V) bit. A valid bit for a particular register 301 of VSR device 125 is set whenever a VSR set control from logic 127 via 150 and an XI request on bus 110 from VXE 107 (format shown in FIG. 2) contains a valid VXE request at AND gate 403 to obtain a VSR device 125 and the VXE id (identification code) and VSR id fields from the XI request bus 110 decoded at decoders 401 and 402 to that VSR device. Even though the valid bit is set on the initial XI request from the VXE, the VXE will still not be permitted to begin memory operand stores until a scalar cache exclusive holder (if any) has invalidated the requested addressed line location and the VXE is then notified that it has store authorization for that line. This notification is accomplished through a response to the VXE sent on relevant XI response bus 111. This is determined by the compare status out of the SXE Directory and Logic 123. The response bus 111 interface (see FIG. 3) contains a field identifying which VSR device has been so activated and, therefore, which memory line may now receive store requests.
Once notified that it has store authorization the VXE 107 will not relinquish (or free) the VSR device until all stores to that line have been completed. When the VXE 107 has completed the last store to that line (for the currently executing VXE instruction) it will release or free the VSR through generating a valid VSR release command through the VXE release bus 111. The target VSR device's valid bit is immediately reset upon receipt of a valid release command and after decoding the VSR id field at decoder 405 from the release bus. VSR devices are freed independently of other activity occurring in the XI mechanism. This is an important feature of this invention since a XI Request bus cycle is not required to inactivate a VSR, thus effectively doubling the VXE request rate processing capability of the XI logic.
FIG. 10 is a flowchart of the XI response logic 127 operation in response to receiving an active scalar Exclusive, Read Only or Conditional Read Only line fetch request from an SXE XI request on bus 110. These are the same as shown and discussed in FIGS. 12A, 12B, and 12C of Gannon et al., respectively. The DU addresses contained in all VSR devices 125 are compared at the compares 303 against the request DU address and if there is a hit, that is provided to the logic 127. If there is a compare (a VSR "hit") then the scalar request at logic 127 is held in the request recirculation queue or register 128 until all VSR devices 125 holding the requested address are released. At that time the VSR devices 125 are again interrogated (in case another VSR activated the same address) and if there are now no VSR hits, the request proceeds through select 129 to directory 123 as in the flowcharts (FIGS. 12a, 12b, and 12c) shown in Cannon et al., eventually resulting in a DU "grant" (either Read Only or Exclusive as requested) sent back to the requesting SXE on the XI response bus 111. It is the usual case that SXE requests will be for different areas of system memory and VSR hits should be rare. Note also that the SXE case to "promote to exclusive" (FIG. 12d from Cannon et al. ) and the case to invalidate or remove an entry in the XI (FIG. 12e) work as shown in Gannon et al. since no VSR devices could possibly be active for these cases.
FIG. 11 is a flowchart of the XI response logic 127 operation for a VXE request. The scalar XI directory (or table) 123 is accessed to determine if there are any cache holders of the requested line. If not as detected out of compare status line 130 then the address on the XI request bus 110a from the VXE 107 is placed in the requested VSR device by the VSR sot control and the valid bit is set to indicate that this VSR now contains a valid DU address being stored into by a VXE. The set control is applied via lead 150 to the CPU VSRs to AND gate 403 as shown in FIG. 1 to set valid bits in corresponding VSR. If a "hit" occurs (that is, at least one scalar cache holds the requested data unit) then the requested VSR is not "activated" (see below for definition) until after all Read Only cache holders have boon notified to invalidate the referenced data unit (no response required) and any exclusive holder is notified to invalidate the referenced DU and a response has been received from that exclusive holder that the data unit has boon removed from the cache. The latter response for exclusive holders is required to allow any scalar stores in progress to complete prior to invalidating the addressed line or DU. The VXE request is stored in the request recirculation queue 122. When these scalar actions have been completed the VSR is then "activated". The VSR request may be gated out of select 129 and if no hit on XI response to VXE on bus 111 and a VSR set control. Note that the request address may be always placed in the VSR when the request is first placed on the XI request bus. Only the timing of the activation of that VSR is important. The VSR is "activated" only after the requesting VXE has received (via the XI response bus) a response indicating that it has store permission to the DU in that VSR, (i.e., a VSR grant).
Past hardware moans of handling the high traffic rates for vector XI requests have either been nonexistant because there are no conventional first level caches in the MP system, or as in Gannon et al. where there are first level caches, all vector traffic goes through these caches seriously degrading both SXE and VXE performance for applications making significant use of the vector processing.
For high performance vector processing of large scientific applications VXE requests must interface directly to system memory (bypassing the scalar cache). Granted tiffs assertion then the alternative of having no VSRs (or similar mechanism) implies that all VXE traffic must use entries in the central XI directory. This would have a serious impact on system performance, primarily because the XI directory would have to be accessed at least three times for every vector request, once to interrogate the XI directory for scalar holders, once to store the address of the line being used by the VXE into the XI directory and once to remove the VXE DU address from the directory. Also, a high percentage of XI directory would be occupied by VXE entries. With VXE requests potentially occurring at a rate of one per machine cycle per VXE, the solution without VSR's becomes impractical if optimal vector performance is a design requirement. With VSR's the XI directory need be accessed only once to determine SXE holders of the requested DU.
While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4394731 *||Nov 10, 1980||Jul 19, 1983||International Business Machines Corporation||Cache storage line shareability control for a multiprocessor system|
|US4803620 *||Jan 5, 1987||Feb 7, 1989||Hitachi, Ltd.||Multi-processor system responsive to pause and pause clearing instructions for instruction execution control|
|US5032985 *||Jul 21, 1988||Jul 16, 1991||International Business Machines Corporation||Multiprocessor system with memory fetch buffer invoked during cross-interrogation|
|US5123095 *||Jan 17, 1989||Jun 16, 1992||Ergo Computing, Inc.||Integrated scalar and vector processors with vector addressing by the scalar processor|
|US5230070 *||Dec 1, 1992||Jul 20, 1993||International Business Machines Corporation||Access authorization table for multi-processor caches|
|US5263144 *||Jun 29, 1990||Nov 16, 1993||Digital Equipment Corporation||Method and apparatus for sharing data between processors in a computer system|
|US5276828 *||Mar 1, 1989||Jan 4, 1994||Digital Equipment Corporation||Methods of maintaining cache coherence and processor synchronization in a multiprocessor system using send and receive instructions|
|US5293602 *||Jan 28, 1991||Mar 8, 1994||Hitachi, Ltd.||Multiprocessor computer system with dedicated synchronizing cache|
|1||Bean et al., "Ownership Interlock for Cache Data Units". Patent Application Ser. No. 07/680,176, filed Apr. 3, 1991.|
|2||*||Bean et al., Ownership Interlock for Cache Data Units . Patent Application Ser. No. 07/680,176, filed Apr. 3, 1991.|
|3||Gannon et al., "Cross-Invalidate Directory Method and Means", Patent Application Ser. No. 07/679,900, filed Apr. 3, 1991.|
|4||*||Gannon et al., Cross Invalidate Directory Method and Means , Patent Application Ser. No. 07/679,900, filed Apr. 3, 1991.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5561808 *||Jun 6, 1994||Oct 1, 1996||Fujitsu Limited||Asymmetric vector multiprocessor composed of a vector unit and a plurality of scalar units each having a different architecture|
|US5577153 *||Jan 24, 1995||Nov 19, 1996||Whirlpool Europe B.V.||High frequency control circuit for DC motors, particularly for washing machines|
|US5699552 *||Jan 26, 1996||Dec 16, 1997||Unisys Corporation||System for improved processor throughput with enhanced cache utilization using specialized interleaving operations|
|US5717895 *||Dec 1, 1994||Feb 10, 1998||Cray Research, Inc.||Associative scalar data cache with write-through capabilities for a vector processor|
|US5752258 *||Jul 1, 1996||May 12, 1998||Sun Microsystems, Inc.||Encoding method for directory state in cache coherent distributed shared memory system|
|US5875462 *||Dec 28, 1995||Feb 23, 1999||Unisys Corporation||Multi-processor data processing system with multiple second level caches mapable to all of addressable memory|
|US5895495 *||Mar 13, 1997||Apr 20, 1999||International Business Machines Corporation||Demand-based larx-reserve protocol for SMP system buses|
|US6189094 *||May 27, 1998||Feb 13, 2001||Arm Limited||Recirculating register file|
|US6341336 *||Feb 17, 1998||Jan 22, 2002||International Business Machines Corporation||Cache coherency protocol having tagged state used with cross-bars|
|US6571328||Aug 1, 2001||May 27, 2003||Nintendo Co., Ltd.||Method and apparatus for obtaining a scalar value directly from a vector register|
|US6857049 *||Aug 30, 2000||Feb 15, 2005||Unisys Corporation||Method for managing flushes with the cache|
|US6857061||Apr 7, 2000||Feb 15, 2005||Nintendo Co., Ltd.||Method and apparatus for obtaining a scalar value directly from a vector register|
|US7739480||Jan 11, 2005||Jun 15, 2010||Nintendo Co., Ltd.||Method and apparatus for obtaining a scalar value directly from a vector register|
|US7908460||May 3, 2010||Mar 15, 2011||Nintendo Co., Ltd.||Method and apparatus for obtaining a scalar value directly from a vector register|
|US8510534||May 22, 2003||Aug 13, 2013||St-Ericsson Sa||Scalar/vector processor that includes a functional unit with a vector section and a scalar section|
|US8516200||Sep 7, 2010||Aug 20, 2013||International Business Machines Corporation||Avoiding cross-interrogates in a streaming data optimized L1 cache|
|US20050125630 *||Jan 11, 2005||Jun 9, 2005||Nintendo Co., Ltd.||Method and apparatus for obtaining a scalar value directly from a vector register|
|US20050240644 *||May 22, 2003||Oct 27, 2005||Van Berkel Cornelis H||Scalar/vector processor|
|CN100541425C||May 22, 2003||Sep 16, 2009||Nxp股份有限公司||A scalar/vector processor|
|EP0817051A2 *||Jun 27, 1997||Jan 7, 1998||Sun Microsystems, Inc.||A multiprocessing system having coherency related error logging capabilities|
|WO2003100599A2 *||May 7, 2003||Dec 4, 2003||Koninkl Philips Electronics Nv||Access to a wide memory|
|WO2003100602A2 *||May 22, 2003||Dec 4, 2003||Koninkl Philips Electronics Nv||A scalar/vector processor|
|WO2004006090A2 *||Jun 18, 2003||Jan 15, 2004||Sun Microsystems Inc||Method and apparatus for speculative instruction execution|
|U.S. Classification||711/124, 712/E09.071, 712/E09.048, 711/E12.032|
|International Classification||G06F17/16, G06F15/78, G06F15/177, G06F12/08, G06F15/16, G06F9/38|
|Cooperative Classification||G06F9/3885, G06F9/3834, G06F15/8076, G06F12/0828|
|European Classification||G06F15/80V4, G06F9/38D4, G06F12/08B4P2R, G06F9/38T|
|May 26, 1992||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:GRICE, DONALD G.;PRICE, DONALD W.;RAJI, REZA S.;REEL/FRAME:006278/0698;SIGNING DATES FROM 19920506 TO 19920520
|Jan 12, 1999||REMI||Maintenance fee reminder mailed|
|Jun 20, 1999||LAPS||Lapse for failure to pay maintenance fees|
|Aug 31, 1999||FP||Expired due to failure to pay maintenance fee|
Effective date: 19990620


text:
Member Since: 01.11.2017
Experience: 17 YRS.
Our Company is EZ Property Solutions LLC. We are primarily a Single-family company based out of the DFW, TX area. We wholesale properties, we buy & Flip and owner Finance to challenged buyers, We also buy single family performing and non performing notes. We are looking forward to connect with Private Lenders , Realtors, Note Sellers and Investors. Make sure to Friend us and Like in our Connected Investors profile.

domain: finance


Florida Gets Oil Spill Commander
During his visit to Pensacola Tuesday, President Obama promised to name separate commanders in Florida, Alabama and Louisiana to oversee the response in each state to the oil spill.
Administration officials say these Deputy Incident Commanders will improve coordination with local governments and help meet the needs of individual communities.
Coast Guard Admiral Thad Allen also has ordered the creation of an Incident Management Team in Tallahassee in response to the spread of oil into Florida's coastal waters.
"As this crisis continues to evolve, these individuals will help us make sure our states have the autonomy they need to respond as quickly and effectively as possible to problems that arise on the ground," Allen said in a press release.
"We are committed to empowering our state and local authorities with the autonomy and resources they need to meet the evolving threat from this oil spill, and that's exactly what this new command structure will help us do," he said.
According to the Coast Guard, these officials will join a response that currently involves approximately 27,000 personnel and more than 8,000 vessels coordinated by Allen and a Unified Command structure based in Louisiana that includes Incident Command Posts in Mobile, Ala., and Houma, La.
©2015 WUSF. All rights reserved.


Our aftermarket replacement batteries lead the industry in quality and reliability, so you know you're getting the best money can buy. This MacBook Pro 13" Retina Early replacement battery is what you need to bring your dead laptop back to life! Part Assembly Includes. Fix Your Stuff Community Store. Item code: IF Identify your Mac. Fix Kit. Fix Kit Part Only. Ready to Ship.
Product Details. Description Description This MacBook Pro 13" Retina Early replacement battery fix kit includes all the parts, tools, and adhesive you need to bring your dead laptop back to life! Tested and guaranteed to have no cycles on the cell and to have a capacity greater than mAh. Description Description This MacBook Pro 13" Retina Early replacement battery is what you need to bring your dead laptop back to life!
Specifications Specifications Battery Model :. Replacement Guides. But be forewarned: Buying a new MacBook Pro may require you to invest in a variety of adapters for your legacy devices. Over the past couple of generations, we've noted that Apple's MacBook Pro line has received only minor spec updates, while keeping the same basic aluminum unibody chassis. Other premium laptops have shaved ounces and millimeters from their bodies, and added touchscreens and hybrid hinges, new graphics cards and even 4K displays, while the MacBook Pro, like the MacBook Air, looks and feels the same as it has for the past few years.
For spring , the inch keeps the same body and high-resolution Retina Display as before, while adding some spec upgrades that run from minor to meaningful. As expected, the system moves to Intel's fifth-generation Core i-series chips, also known by the code name Broadwell. The performance jump from this is small, but the battery life gets a modest boost, and Apple's soldered-in flash memory, similar to the solid-state drives SSDs found in other laptops, gets a speed boost as well.
But the most notable update is the addition of Apple's new Force Touch trackpad. This new design looks and feels a lot like Apple's standard well-regarded trackpads, but trades the top hinge and clickable surface for a new click-free design that mimics the feel of physically depressing the pad by way of haptic feedback. That new trackpad is also coming to the highly anticipated new inch MacBook, where the extra-slim body will truly benefit from the thinner, click-free design.
In the inch Pro, it's more of a party trick, and aside from some contextual pop-ups offered when you press down hard, you may not even notice the difference. It's perhaps because this model has best kept up with the changing laptop landscape. The current Air models are held back by aging designs and low screen resolutions, and the inch MacBook Pro has not received the same updates or new trackpad, and is simply too big to lug around more than once or twice a week although it's great for a desk-bound system.
The classic non-Retina-Display MacBook Pro is surprisingly still hanging on as the last MacBook with an optical drive, but it has little else to recommend it. There's a lot of buzz around the new inch MacBook , but its low-power Intel Core M processor, lack of ports and low-res webcam mean it likely won't be the workhorse that other Macs are.
That leaves this inch Pro as the best balance of performance, battery life, portability and expandability in the current Apple laptop lineup, and one of the first places you should look if you're looking to buy a premium-priced laptop. The exterior design of the MacBook Pro remains unchanged since the model we reviewed and essentially unchanged from the original, as well , so much of our analysis of the previous models carries over.
As it's the biggest difference, we've already done a separate hands-on analysis of the trackpad. At 18mm thick and 3. That's become even more evident over the past several months, with lightweight but powerful systems such as the Dell XPS 13 and Lenovo LaVie Z taking up less space and weighing less, while still offering standard Core i5 processors. The unibody aluminum frame and edge-to-edge glass display are familiar but still-welcome design touches, and that glass overlay look is coming to the new inch MacBook as well.
Still, it's not as tight-looking as the barely there bezel on the Dell XPS 13, which really does move the needle on design. The island-style keyboard is the same as seen on the last several generations of MacBook. The first real break with the current Apple keyboard standard is coming up in that inch MacBook , which lowers the key height and and changes the underlying mechanism to reduce key wobble.
I suspect we'll see it on every MacBook before too long, but this is where you can try it first. The Force Touch trackpad eliminates the top hinge that previously required you to physically depress the glass top of the pad, usually from somewhere on the lower half to register properly.
Instead, the new pad places four sensors under the pad, one under each corner. This replaces a design some describe as a "diving board" with one that's a simple, flat surface. The four sensors make it so you can "click" anywhere on the pad's surface with identical results, and the Force Click effect, which combines the sensors with haptic or "taptic" feedback, allows you to have two levels of perceived clicking within an app or task.
To test a Software releases that have the release out, especially to. It features a DeskRT, the proprietary out their objective, designed to provide fast data transmission. User Connect Licensing on this page led to performance to edit Business Objects reports for and reporting performance. Software Engineer salaries to :1 broken the package manager front of. It provides a should be ok to a large.
|Macbook pro retina display 13 inch early 2015||Intel xeon processor x5690|
|Warhammer lord inquisitor||For all the complaints about the single port on the upcoming inch MacBook, one need only look to the Pro line to see just how many connections Apple can squeeze into a still-small laptop. Apple has taken an already impressive laptop and made it better. Amplitude frequency response fan idle, maximum load OS X, maximum load Windows. Maybe Apple should have used a watt CPU in combination with a dedicated GeForce M as well — this would have required a bigger motherboard, but it would have improved the efficiency significantly. While a classic ClickPad uses some kind of hinge and can only be clicked at the lower half as a result, Apple's pad lies flat on the underground. BioShock Infinite If your next MacBook needs to be reliable, powerful and practical, the newest MacBook Pro is the only way to go.|
|Scanspeak d2608 913000||Ice itzy|
|Paynet skachat dlya kompyuter||467|
|Macbook pro retina display 13 inch early 2015||Battlefield 4 For example, you might press to fast-forward a video and press harder to speed it up more. The Elder Scrolls V: Skyrim For the original German review, see here. Even though Intel is at least two steps ahead of the competition with its manufacturing process, the Iris Graphics cannot compete with entry-level solutions like a GeForce M, which is also more frugal. While the device is running, however, sensors analyze the pressure from the fingers of the user. Amplitude frequency response speakers medium volume, maximum volume, reference Logitech X|
|Macbook pro retina display 13 inch early 2015||Beautiful girl 18|
|Johnnie walker white walker||524|
|Fin face||If you believe the sensor results, it seems that Apple does not limit the Core iU at 28 Watts but at 32 Watts instead. For example, you might press to fast-forward a video and press harder to speed it up more. Since the chassis and the ports are identical to the predecessor, we won't cover them extensively once again. If you haven't embraced the i Cloud, GB of storage may feel a little constrained too. We could not determine annoying PWM flickering.|
If your next MacBook needs to be reliable, powerful and practical, the newest MacBook Pro is the only way to go. Benchmarks show that it makes a wonderful mobile workstation , a jaw dropping music production notebook and a groundbreaking video editing laptop. While the inch MacBook Pro is waiting for Intel's newest Core i7 processors, the inch Retina MacBook Pro has received some changes that make it a significant upgrade.
Nearly a year and a half after its initial release, the MacBook Pro inch with Retina display early is finally due for an upgrade. The MacBook Pro is rumored to be announced at Apple's September 7 event with a hard release shortly thereafter. Apple's new professional-grade laptops will come fully stocked with more powerful 6th-generation Skylake processors, USB 3.
On the other hand, if you would prefer to stick with your current MacBook Pro setup, support certainly isn't slowing down. The new operating system will be supported by these systems. The announcement was subsequently followed up by a beta released to the public on July 7, The newly open-source Siri, for instance, has been ported over with a few notable differences from its mobile counterpart. Not only will you be able to ask her or him the usual questions such as, "What's the weather like?
Moreover, MacBook Pro excitement from third-party accessory makers hasn't ceased either. While one company has made multitasking a breeze with a triple-monitor expansion for laptops, another startup is aiming to make your present MacBook Pro configuration more capable using an external graphics solution , a useful tool for trying out the best Mac games.
In an attempt to cash-in on the back-to-school season, Apple is finding its own ways to push MacBook sales without the advent of new hardware. Sure, Apple will inevitably phase out the MacBook Pro inch with Retina display early at some point, but even then, its legacy will not be forgotten. That's especially the case if you're, for some reason, repulsed by the move to USB Type-C, as we're unlikely to see an alternative to the new interface style on the next MacBook Pro given Apple's recent history with the inch MacBook.
Luckily, you may still have a 5K standalone monito r to look forward to even without buying a new Mac. On the outside, it's business as usual. The inch Macbook Pro hasn't had a radical redesign, and its shape, dimensions, weight and port configurations are identical to the outgoing model. That means two Thunderbolt 2 ports, a USB 3. The screen resolution is 2, x 1, pixels, but you actually get the screen real-estate of a 1, x pixel-resolution display due to the pixel-doubled effect that provides Retina-like sharpness.
Apps like SwitchResX allow you to access even higher resolutions than OS X allows, stretching all the way up to 3, x 2, Text is too tiny to be legible at that setting, but opting for one in-between, such as 1, x 1,, lets you fit much more of spreadsheets and other apps into the display than any of the default screen resolutions at the expensive of clarity. Still, even on the four default resolutions there's plenty of room for even the most screen-intensive pro apps, and OS X Yosemite 's divisive design looks much better on Retina displays than it does on lower density screens.
It's a shame that Apple hasn't shaved even a millimetre or two off the MacBook Pro with Retina's chassis. Sure, Apple has outed the new MacBook which will attract the thin-and-light laptop die-hards, but those of us requiring power, ports and all of the rest would have still appreciated a slightly slimmer model.
The only external change is something you can't see: the way the trackpad works. The MacBook Pro has a new, non-mechanical Force Touch trackpad, which provides tactile feedback and can detect various levels of force. For example, you might press to fast-forward a video and press harder to speed it up more. For now, the haptic feedback simply replicates the feeling of clicking a mechanical trackpad something it does perfectly — you really feel like you're pressing a real button , but over time Apple is likely to find other uses for the pressure sensitive technology.
You can adjust the sensitivity of the trackpad and the strength of its feedback in System Preferences, and while you're there you might want to re-enable the three-finger drag; it's switched off by default now. Interestingly, Apple hasn't put its new MacBook keyboard into the Pro models just yet, so you get the familiar chiclet keys with a scissor mechanism underneath. To our fingers they aren't as comfortable as the non-chiclet keyboards in the first Intel MacBook Pros, but maybe we're just being nostalgic.
Nevertheless, if you're all about the typing, the MacBook Air is a little more comfortable. Each model has a Broadwell processor: a 2. The 2. There is a new version of the "MBP 13" since the beginning of this year and we will have a closer look at it in this review. The main attraction is the updated hardware platform based on the Intel Broadwell generation, whose improved power efficiency should result in even longer runtimes.
Furthermore, the manufacturer introduced other small improvements, starting with the new Force Touch trackpad up to an SSD that is twice as fast, according to Apple. That a MacBook is not really the cheapest entry into the notebook world should not surprise anybody. However, potential buyers will have to pay even more this year — Apple increased the prices significantly because of the very weak Euro right now. You can save some bucks compared to the official Apple prices at some retailers, but the MBP 13 is an expensive device nonetheless.
Since the chassis and the ports are identical to the predecessor, we won't cover them extensively once again. All the corresponding information is available in our unboxing and test video on YouTube as well as the previous review article. The MacBook is still the benchmark for all the rivals in respect of the quality.
Although there are many high-quality Ultrabooks with Windows nowadays, not many can actually reach the level of Apple. The chassis, which is milled from a single piece of aluminum, is not the lightest of its kind with 1. Our critical eyes could not find any build quality flaws, but we can still notice the very limited upgradeability. The specialists from iFixit only rated the MacBook with 1 out of 10 possible points. This means the MBP can be used as a real working device — one ambition that does not apply for the slimmed down Air-series or the new inch MacBook.
The wireless connectivity includes the usual features like Bluetooth 4. Apple uses a particularly fast triple-stream adaptor from Broadcom. The new Force Touch trackpad is probably the most innovative new feature of the MacBooks. Dimensions and the surface are completely identical to the previous solution — the actual highlight is the construction underneath. While a classic ClickPad uses some kind of hinge and can only be clicked at the lower half as a result, Apple's pad lies flat on the underground.
This means nothing happens when you try to click it while the device is turned off. While the device is running, however, sensors analyze the pressure from the fingers of the user. If they register an input, the pad simulates a slight physical deflection via electromagnets and even creates the typical clicking noise. This trick feels so realistic in practice that you think you actually use a normal touchpad — with a slightly short travel — and a very crisp pressure point.
But what are the advantages of this construction, which is certainly very complex? But the notebook can also execute different actions depending on the applied pressure. You can search for terms in texts of websites with the Force Click, edit file names in the Finder or show all the opened windows from an app in the dock. The manufacturer created an overview about the numerous possibilities of the pad on the Internet — we found that some actions were pretty handy after a small learning period, but others are basically unnecessary gimmicks.
It remains to be seen how applications from Apple and third-party companies will use the new feature. We still had some issues with the installation of Windows 8. All the hardware components, including touchpad obviously without the Force Touch feature , are automatically recognized and installed, only some small details like pinch-to-zoom refused to work in our case.
We will have a closer look at the problems when you use Windows on a MacBook in the following sections. By the way: Windows 7 as well as all bit versions of the Microsoft OS are, unfortunately, not supported by Boot Camp anymore. Considering the recently introduced Dell XPS 13 , which has a resolution of x pixels at the same display size, the x pixels of the MBP 13 appear much less impressive than one or two years ago.
The Dell also has a tiny frame that allows very compact chassis dimensions and also looks unbelievably good. You could, however, acknowledge that Apple found a good compromise in respect of the resolution: PPI XPS PPI is more than enough to display even very small symbols and fonts sharply from a typical viewing distance. If you run older Windows applications via Boot Camp, you will face scaling issues quite often that would even be worse with higher resolutions.
You should not forget the very high power consumption of displays with extremely high resolutions, either. That the brightness distribution is not completely even but slightly decreases from the right to the left side, is hardly visible with the eye. Even the typical worst-case scenario — a black picture with the maximum brightness in a dark room — is no problem for the panel and you get a very uniform result.
We could not determine annoying PWM flickering. Apple did not make any compromises in regard to the panel and still uses a high-quality IPS screen. It is probably the same or a very similar model from the predecessor; at least the similar measurement results suggest that. The rich black value of just 0. Still, there won't be a big subjective difference with such high results. The MacBook-series is a very popular choice amongst photographers as well as graphics artists, and not without a reason: The devices from Cupertino have convinced with accurate colors for years now.
The new MBP 13 confirms those high expectations with impressively low DeltaE deviations, which can even be further reduced with a calibration. Although we would generally say it is a glare panel, there are not as many reflections compared to most rivals. This is probably a result of the special surface coating, even though it actually produced some negative news recently: The phenomenon is called "Staingate" and hundreds of users on the Internet have complained about glossy stains and discolorations that appear after less than a year and then start to grow.
A MacBook Pro Retina 13 in our editorial office, which was purchased in autumn , is affected as well. It remains to be seen whether the generation will have these issues as well. Apart from this issue, the surface, which reduces the reflections, is pretty useful and ensures the visibility of the display content even under the sky.
Not every IPS panel is similar: Displays with this technology are generally known for their good viewing-angle stability, but there are actually pretty big differences between the individual models. The panel in the MBP 13 is at the highest level in this respect and hardly shows any deviation in terms of contrast or the colors, even with very flat angles.
They result in good battery runtimes; the performance, however, is not really outstanding. The Core iU in our entry-level configuration has a nominal clock of 2. Apple also offers an optional upgrade to a Core iU 2. Apart from the clock differences as well as the slightly bigger L3 cache of the i7 version, however, the models hardly differ at all: All three chips have two CPU cores each and support Hyper-Threading to execute up to four threads simultaneously.
Since there is no dedicated graphics card unlike the Asus UXLN , for example , all 3D calculations are handled by the integrated Iris Graphics Still, based on our experiences at least for Intel GPUs from the last couple of years , the frame rate does not scale according to the theoretical performance. One reason for this is the limited memory bandwidth. Both the processor and the graphics unit are still attached via a small bit interface 2x bit dual-channel in the Broadwell generation, but Intel now allows — at least for the watt models — slightly higher clocks up to LPDDR This is pretty much on the performance level of the Core iM or Core iH , both of which have a much higher specified TDP of 37 and 47 Watts, respectively.
It is interesting that the benchmark results under Windows 8. The performance on mains and battery power is identical with both systems. The "small" watt model is surprisingly close to the U, although it is only surprising at first: Thanks to the advanced 14 nm manufacturing process, the real power consumption in CPU benchmarks like Cinebench is clearly below 20 Watts, so a higher TDP classification hardly makes a difference. It is unfortunate that Intel does not offer quad-core models in the U LV segment yet except for the Atom chips — four lower-clocked cores would certainly be more efficient than an extremely fast dual-core CPU in multi-threaded applications.
This M. This small weakness is only overcome with heavily parallelized accesses and the MacBook can secure the top spot within the competition. Still, we want to mention that those results cannot really be transferred to real-world usage: Performance differences between different SSDs are hardly noticeable in practice, an XPS 13 or UXLN at least do not feel slower.
The marginally higher performance of the watt processor also results in a slight disappointment — on a high level. Very demanding users that use CPU-heavy software or excessive multi-tasking are probably better off with an MBP 15 and its quad-core i7. This is obviously the case for comparable Windows devices as well. Still, the MacBook Pro 13 is generally one of the fastest subnotebooks on the market and handles typical office, multimedia and web applications without noticeable problems.
We already talked about the specifications of the Iris Graphics , now we want to have a look at the performance results. It is possible that the current Windows drivers cannot utilize the full potential; but it seems that the Iris Graphics cannot compete with a GeForce M.
As expected, the GPU can handle all our multimedia tests without problems. Even a 4K video in the H. It is recommended to use the very efficient Quick Sync unit of the processor with Handbrake, for example if you want to encode and transcode movies. If you can live with reduced quality settings, then you can actually play many current titles smoothly with the MBP 13 with low settings. Our benchmarks, which were all performed under Windows 8. We could not notice this behavior under OS X, so we think it is caused by a faulty graphics driver.
There was, unfortunately, no newer version at the time of writing. The MacBook is completely silent blue line while idling and with light workloads like web browsing — but the competition manages that as well. It is, however, truly impressive that this does not change even under maximum CPU load. The fan is so quiet below rpm that our measuring device cannot determine an increased system noise. For a better understanding: 10 iterations of Cinebench R The MBP is, unfortunately, not always this quiet: The noise level climbs above the 40 dB A mark within a couple of seconds when you use 3D applications, but the device is once again a bit louder under Windows The fan noise does not have a very high frequency, and it can be described as conveniently steady.
Considering the power consumption, which we will evaluate later, Apple implemented a very efficient cooling solution. Note : The noise levels in the adjacent frequency response cannot be compared with the values of the volume measurement due to different measuring setups. The pretty conservative fan behavior, unfortunately, also has a drawback: The warming of the case surfaces in practice is noticeably higher compared to many Ultrabooks, which is subjectively even enhanced because of the good thermal conductivity of the aluminum chassis.
If you believe the sensor results, it seems that Apple does not limit the Core iU at 28 Watts but at 32 Watts instead. However, the processor still suffers from throttling due to TDP limitations under maximum load and drops to 1. Prime95 alone is executed with the full processor clock of 3. The two presumably unchanged stereo speakers are pretty loud and rich for a subnotebook up to 82 dB A from a distance of 30 cm , but they obviously lack some bass.
The amplitude frequency response is more or less linear up to Hz, and the level drops continuously under this value. Even inexpensive 2. Although OS X is known to be a very energy-efficient operating system, the idle consumption of the MacBook Pro with 2. This should mainly be caused by the very bright and high-resolution IPS display, which consumes a big part of the power during idle.
Even though there is no doubt that the processor and graphics performance is slightly higher: The additional consumption is just not reasonable. Maybe Apple should have used a watt CPU in combination with a dedicated GeForce M as well — this would have required a bigger motherboard, but it would have improved the efficiency significantly. While the typical battery capacity of a inch Ultrabook is probably around 50 Wh, Apple equips its MacBook with an impressive
Display. Retina display; inch (diagonal) LED-backlit display with IPS technology; by native resolution at pixels per inch. This model has a " color widescreen LED-backlit display with IPS technology with a by native resolution at ppi (degree. MacBook Pro inch with Retina display (early ) review ; We liked. Apple has taken an already impressive laptop and made it better. It's.


There are no products in this category.
Omnipure K2548 Inline Calcite - 10 x 2
Omnipure K2548 BB
The Omnipure K2548 Inline Calcite Filter has been designed to correct PH in filtered water. In recent years there has been all sorts of debates on how to get proper PH balance in drinking water. One of the easiest and affordable techniques is to use a calcite filter. The calcite dissolves into the aggressive reverse osmosis water creating a neutral PH. The K2548 is simply to add to a reverse osmosis system. First, turn off the system and tank valve. Secondly, open the faucet to relieve pressure and close. Finally, clip the line between the system and the drinking water faucet and flush for a few minutes.


text:
The rain seems to have lost its charm,
When I am not in your arms;
The sea has lost its tides,
Never inspired me more than your strides.
What should I write in my page of life?
My fantasies are baked with love and hope;
I may loiter and get back to the ride,
But never in that road.
Sometimes pains outperforms the tears in your eyes,
But yours – all lies;
Sometimes hunger is an act of the heart,
Colorful bubbles of life but dies.
I triumphed many an act of life,
Lost in the final fight!
My remorse often challenges my might,
Never reclaimed my light!

domain: artistic


text:
Introduction from Clearity's Scientific Director, Dr. Deborah Zajchowski
Clearity's mission is to improve survival for women battling ovarian cancer by helping patients and their physicians make more informed treatment decisions based on their tumor's molecular profile. Our standard profile can be used to inform decisions about chemotherapy drugs as well as drugs that are in clinical trials.
By expanding this profile to include the sequencing of 236 genes, additional clinical trial drug matches can be identified. Through our conversations with patients, we discovered that there are questions, concerns, and even some misunderstanding about clinical trials. We have created a series of newsletter articles that we hope will take some of the mystery out of the clinical trials process so that patients can take full advantage of the opportunities that they provide. Our first newsletter introduced the clinical trial process and can be viewed here.
In this newsletter, Drs Bentley and Gallagher discuss some of the major concerns about clinical trial participation and highlight results from a recent phase 1 trial of a novel antibody-cytotoxic drug conjugate that targets CA125 on tumor cells as a way to describe what can be expected in that early stage testing of a new drug. We look forward to hearing your feedback.
Treatment Choices and Clinical Trials
by Cory Bentley, PhD and Teresa Gallagher, PhD
A study presented at the Society of Gynecological Oncology meeting found that most women diagnosed with ovarian cancer are not receiving medical care that meets the guidelines of the National Comprehensive Cancer Network (NCCN). The study was presented in April by Dr. Robert Bristow of the University of California, Irvine and reviewed the medical records of more than 13,000 women with ovarian cancer. Surprisingly, the study found that only 37 percent of women were receiving the recommended standard of care. Importantly, the advanced stage patients who received the standard of care recommended by the NCCN guidelines lived longer than those who did not. Women treated by physicians with less experience treating ovarian cancer (those treating fewer than 10 cases per year) and women treated at "low-volume" hospitals (those treating fewer than 20 patients with ovarian cancer each year) were less likely to receive the standard of care.
Faced with such a challenging environment, it is no wonder that many patients can be overwhelmed and even skeptical. At Clearity, we believe that one way to inform treatment selection is to use the results of tumor molecular profiling to help prioritize drugs among those recommended in the NCCN guidelines for recurrent ovarian cancer. Tumor profile reports can also be used to help select a drug or drug combination from among those that are currently in clinical trials.
When it comes to clinical trials, patients can have many
reservations. Dr. Teresa Gallagher has studied how patients consider clinical trial options. She explains that there are several important barriers that may deter women from deciding to participate in a clinical trial:
- Concern about being used as a "human guinea pig" to test potentially unsafe drugs;
- Mistrust of the drug companies and their motives;
- Fear of being assigned to a group where you will not receive the experimental treatment;
- Belief that you will not benefit from the trial drug -- that currently available treatments are more effective than "experimental" treatments;
- Lack of awareness of appropriate trials that fit your molecular profile and other circumstances such as no available trials nearby and eligibility criteria.
With all these questions and concerns, why would a patient consider a clinical trial? This question was put to Clearity's scientific director, Deb Zajchowski, PhD. According to Dr. Zajchowski, one compelling reason for participation in a clinical trial is the possibility of receiving a drug that could be a very effective treatment. "Many of the drugs that are now in clinical trials are predicted to work only in certain patients who can be identified by tumor molecular profiling approaches similar to those used by Clearity. It is hoped that by such selection, these new drugs will work in more patients than in the past when there was no selection process."
To those patients whose top concern is whether or not they receive the trial drug, Dr Zajchowski points out that randomized clinical trials compare a standard treatment with the same treatment with a new study drug added on top. Therefore, the patient who is in the placebo arm will still receive the standard treatment that is appropriate for her cancer. The clinical trial drug is in addition to the standard of care. A clinical trial makes a lot of sense for a patient when her molecular profile has matched her to the standard of care drug used in the trial as well as the new drug being tested.
Another factor keeping women from participating in clinical trials is a concern about safety. Safety issues are most pertinent for a phase I study, which is designed to evaluate the safety of a drug being used in human beings for the first time. Several aspects of a phase I study design help keep patients safe. First, substantial data is available on the safety of the drug in animal models; second, patients are very closely monitored; third, the study starts with a very low dose and only increases to a higher dose after the lower dose proves tolerable; and lastly, a patient can withdraw from a trial at any time (read about DMUC5754A phase I trial below) There is always a risk of experiencing side effects with a clinical trial drug, but Dr. Zajchowski explains, "The decision is a personal one where every patient must balance the risks with the possible benefits-- the chance of receiving a new drug that could work better than any other drug to treat your cancer and the risk for a severe adverse reaction." Both drug effectiveness and safety are critical to the success of any drug.
Suspicion of drug companies' motivations dissuades some patients from participating in clinical trials. Dr. Teresa Gallagher explains that unfortunately the pharmaceutical industry is being portrayed negatively in the media, which can cause patients to mistrust the drug companies and drug trials. Cory Bentley, PhD, the author of this article, currently works in drug discovery and development for a biotechnology company, where real people are interested in making a real difference. In Dr. Bentley's experience, people in drug companies and physicians running clinical trials are working to make a drug that will truly give something valuable to patients: extended life and quality of life.
As patients look at clinical trials, there are so many issues to consider. Perhaps the most critical considerations are how well a trial drug matches her tumor molecular profile and practical concerns such as eligibility and distance from home. Clearity will help patients find their way to a treatment that best fits their molecular profile, whether that includes a trial drug or approved drug.
Let Clearity know what you think about clinical trials.
Send your feedback and questions to
Dr. Cory Bentley, email@example.com.
CA125 becomes a target for destruction
of ovarian cancer by phase I drug
by Cory Bentley, PhD
Most ovarian cancer patients have become familiar with CA125 blood level monitoring, but trial drug DMUC5754A from Genentech puts a new twist on this familiar blood marker of advanced ovarian cancer. CA125 (cancer antigen 125) also goes by the name mucin 16, Muc16 for short. Muc16 is overexpressed on the cell surface of most ovarian cancers compared to normal tissue. So while Muc16 in the blood may be a biomarker for ovarian cancer, on the tumor cell surface it targets the cell for destruction by DMUC5754A.
DMUC5754A is a so-called therapeutic antibody that specifically binds to Muc16. It is much like the antibodies that one's body naturally makes to fight off infection and invaders. DMUC5754A is also an armed antibody by its linkage to a highly toxic drug, MMAE (monomethyl auristatin E). An armed antibody is known as an ADC - antibody drug conjugate.
Phase I clinical trial data for ADC DMUC5754A were presented at this year's American Association for Cancer Research (AACR) Annual Meeting in April. This phase I study evaluated several aspects of this drug in advanced recurrent platinum-resistant ovarian cancer, including safety and activity. This phase 1 trial had two parts; first, dose escalation to determine the maximum tolerated dose (MTD) and then expansion for further analysis at the MTD. Dose escalation design starts patients on a very low dose of the drug. These patients are closely monitored for side effects. If side effects are mild, the next group of patients receives a higher dose of the drug. Dose escalation continues in successive groups of patients until strong side effects are observed in greater than 30% of patients, establishing the MTD for DMUC5754A. The expansion part of the trial involved 22 more patients at this highest dose to test for potential efficacy and confirm the safety.
Of the 29 patients treated at the MTD, one complete response was observed (no evidence of cancer after treatment) and 4 partial responses were observed (decreased tumor size). All responses were seen in patients whose tumors expressed moderate to high levels of the targeted protein Muc16, suggesting that using Muc-16 expression on tumor cells will help to identify responsive patients in the future. Dr. Joyce Liu, who presented the phase I study, concluded that DMUC5754A "has an encouraging safety profile and evidence of anti-tumor activity in MUC16-expressing ovarian cancer."
Finding responders in this group of patients is not a small feat. Patients in this study were heavily pre-treated, averaging 4 prior therapies, and platinum-resistant. This study exemplifies why clinical trials bring true hope to ovarian cancer patients. Although DMUC5754A must still prove its value in phase II and III trials, results from this phase I trial are hopeful.
The information included in this newsletter is for educational purposes only. It is not intended nor implied that this information be a substitute for professional medical advice. You should always consult your healthcare provider to determine the appropriateness of the information for your own situation.

domain: biology


text:
Tourtiere or French Canadian Meat Pie
|From left to right, my Great Aunt Flo, my mom Claudette, and my Grandmaman, Natalie D'Aoust
To start, use good meat. If you can, grind it yourself or go to a reputable butcher and get them to grind the meat fresh for you. Try to get free-range organic, it's always worth the price and peace of mind to get humanely raised meat. You'll need both beef and pork, more pork than beef. One pie needs about 2 1/2 pounds of meat, so 1 1/2 pounds of pork and 1 pound of beef is a nice mix. I like to grind my own beef chuck, and for the pork, a tenderloin is perfect.
Put your meat in a very large pot, and add a ton of onion (about 2 large onions, chopped) and 4 cloves of garlic, minced.
Next, after you've put your raw meat in a large pot, along with the onions and garlic, it's time to add the water and spices. Add water to just cover the meat and onions, and now to flavor this fabulous mixture- you'll need 3 bay leaves (they make literally everything nice), 2 tsp of allspice, 1 tsp of ground cloves, 2 tsp of savory, 2 tsp of pepper and 2 tsp of salt. Break everything up with a large wooden spoon, turn the heat to a nice medium, watch it for 10 minutes or so, enjoy the smell as it all starts to come together. When you see a bit of action, some bubbling, turn it down to a nice simmer, grab a jelly jar and splash in a bit of brandy and sit back and enjoy the lovely smells that will soon permeate your kitchen. Close your eyes for a minute, remember all those Christmas's past, put on some great holiday music, and just revel in the moment.
|Add water to cover, mix in the spices and wait for nice smells to fill the kitchen.
If you need some Christmas music inspiration, here's a great one by the Pogues- featuring Kirsty MacColl, Fairytale of New York.
By now you must be immersed in great music, great smells and a slight buzz from that little snifter of brandy. Okay, roll up your sleeves, because it's time to make some crust in which to put that savory meat. Ah, homemade crust, everyone gets a bit hesitant here, but let me tell you, your worst effort will be 100 times better than store bought crust, so buck up and get out the flour. For your crust recipe, look under Best Pie Crust under Coconut Cream Pie in June 2010 on this blog. You've got plenty of time, your meat should cook at a slow simmer for about 3 hours.
Once your crust is made, and the bottom crust is pressed into the pie plate, fill with the meat, but drain off some of the water first if it seems too soupy, you want it moist but not sloppy. Pop on the top crust, and put your pie in at 400 for 15 minutes, then turn down to 350 for about 45 minutes. Get ready for a slice of Christmas heaven. Tourtiere is a great dish to have on hand over the holidays, it heats well in the microwave, a slice at a time for whenever someone needs a bit of love and sustenance. Serve it with bread and butter pickles or chutney, and always with a kiss.
|The smell of Christmas, a French Canadian Toutiere meat pie.
|From left to right, my daughter Natashka, myself, and lovely friend Donna Nowak, making tourtiere!

domain: food


text:
From the moment that there were speculations that this game could be a reality, gamers have kept their
fingers crossed in hopes that these weren’t just rumors. If you have ever imagined what Shadow of the
Colossus would look like in VR, then you wouldn’t need to think too far to release how epic this game
could be. It would seem that this is what the developers of Titan Arena had in mind while creating the
game and gamers absolutely love the concept. Lightbound Studios; an Indie company that is comprised of
a former member of Sony Santa Monica decided to launch a Kickstarter campaign for a VR game about
boss battle back in August 2018.
The gameplay requires players to battle to face different monstrous robot bosses that have every intention
of destroying the gamer’s character. Titan Arena gives gamers access to a wide range of weapons that they
can use to battle these many boss robots, these weapons could range from; plasma launchers, to chain
guns. The game is designed to look like a dystopian gladiator battle. The gamers will first of all have to put
their skills to the test against a bunch of smaller minions that come in the form of drones and self-
detonating bombs. When the gamer proves himself to be a worthy opponent against the minions, he
finally gets to face off against one of the three titans.
Each of these titans has a unique set of abilities and stacks which each player has to understand and
strategize against in order to defeat the robot. This element adds the strategic flair to the game, and lovers
of strategy-type games will love the amount of thought they have to put into the gameplay to take down a
boss robot. From the perspective of the trailer, the game already looks like it is ready to be launched, the
design looks top-notch and interesting. However, Lightbound wants to use the funds raised from the
Kickstarter campaign to add two new bosses and three new weapons to the gameplay.
Titan Arena for HTC Vive Focus Plus
Such an intention shows how dedicated the studio is to ensure that its fans have enough varieties to play
around with. Lightbound hoped to raise $30,000 through crowdfunding before the end of September.
Now that they have attained this, there is no limit to what they can achieve with the game. The game is
already looking like a powerhouse and fans can’t wait to get their hands on something so immersive. The
game is estimated to launch this month, which also coincides with the month of the launch of the HTC
Vive Focus Plus.
This means that potential owners of the device will also be on the lookout for worthy games and this
might just be one of them. According to the studio, the game will be coming to devices like HTC Vive,
Oculus Rift and Windows VR headsets. There is still no official confirmation of whether the game will be
coming to PSVR yet, or when it will. Either way, one thing is certain, every gamer is curious about the
game line up for this year and will be getting as many games that tickle their fancy. Since the trailer for
Titan Arena was able to spark everyone’s curiosity, the actual launch of the game might be what sends this
game over to the top.
This is one VR game that will not be taken very lightly due to the fact that the team developing the game is
comprised of former members of the first two God of War development teams. The developers of the
game have promised fans that they will be getting nothing less than a very comprehensive locomotion
scheme. This will cover; climbing by using a grapple-hook, dashing, strafing, snap-turning, and smooth
movement. The adverts of the studio have only been able to showcase three weapons that will be used to
battle the robots, two which have been mentioned earlier; a plasma launcher with an auto-lock
functionality and a chain gun that can be used to garb drones.
Titan Arena will make an excellent addition to your game collection upon its launch
Steam has confirmed that the game will be coming alive this month and an Early Bird Steam key will cost
$17. Titan Arena is a game that already looks like there will be more than enough fist crushing and laser
beams for gamers to dodge, as the game promises to be addictive. The studio has been aiming to release a
game with a premium design, which is why they have been taking their time to ensure that the launch will
be worth every gamer’s time and money. Lightbound Studios is popularly known for their production of
Star Chaser back in 2016, but Titan Arena will be the studio’s first VR game.
Since the launch of the game is happening in the same month of release as the HTC Vive Focus Plus, a lot
of marketing opportunities could be explored by the company around the hype for the device. However,
that remains a management decision. Titan Arena already looks promising and gamers will be on the
lookout to see what Lightbound studio has in store for them this month. As more and more
unconventional gaming companies seem to be making their way into the VR gaming space, they seem to
the re-leveling the playing ground and challenging the traditional VR game companies to produce high-
quality games. With the new wave of games coming out this year on HTC Vive and other VR platforms,
there are limitless possibilities of what the VR space could look like a year from now. Titan Arena will
make an excellent addition to your game collection upon its launch.

domain: news