|Publication number||US6731002 B2|
|Application number||US 09/992,602|
|Publication date||May 4, 2004|
|Filing date||Nov 13, 2001|
|Priority date||May 4, 2001|
|Also published as||US20020163070|
|Publication number||09992602, 992602, US 6731002 B2, US 6731002B2, US-B2-6731002, US6731002 B2, US6731002B2|
|Inventors||Kang Rim Choi|
|Original Assignee||Ixys Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (37), Non-Patent Citations (2), Referenced by (57), Classifications (34), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims priority to U.S. Provisional Patent Application No. 60/288,854, filed on May 4, 2001, which is incorporated by reference herein for all purposes.
This invention relates to electronic devices, and more particularly to a packaged high frequency (or radio frequency (RF)) power semiconductor device with either a direct-bonded metal substrate or a plastic package, or both.
The use of semiconductor transistors for RF applications has increased dramatically over the years as heat dissipation, size, dependability, and other improved characteristics have made such transistors well-suited for many applications. Such semiconductor transistors are used in electrical circuits which operates at 1 MHz or greater, typically at 25 MHz or even 500 MHz or greater. In some of such electrical circuits, the transistors are part of the power conversion circuit and are required to act as the switching element, in frequencies greater than 1 MHz, as in advance switch mode power supplies, resonant converters, DC to DC converters, and the like. For these applications, a lower cost RF type package is preferably used to provide a competitive solution in comparison to the lower frequency prior art applications.
These RF power transistors are typically housed in packages (“RF packages”) to form RF power devices. The RF packages provide mechanical support and a means for dissipating heat for integrated circuits. Mechanical support is necessary to facilitate handling and prevent breakage of the integrated circuit during installation or operation of the device. Heat dissipating characteristics of the RF packages are particularly important for RF power devices which have high power outputs. RE devices typically output from 1 to 1,000 Watts during their normal operations.
The packages for such high power transistors must be capable of dissipating the relatively high quantities of heat generated by the transistor to maintain the transistor at a suitable operating temperature, i.e., a temperature which will not adversely affect the operating characteristics of the transistor. Heat decreases the performance and operating life of the transistor. Moreover, heat generated at the collector-base junction can create a temperature buildup which may eventually cause the device to short-circuit. Another important characteristic for such packages is that they provide for good electrical grounding of the transistor with a minimum of parasitic inductance.
A semiconductor die of the RF power device may be mounted on a thermally conductive pad which acts as an internal heatsink (i.e., a component provided as a part of the power device) and dissipates the heat generated by the power device. In order to prevent electrical losses, however, the thermally conductive pad must also be electrically insulating. Hence, a thermally conducting, electrically insulating material is used for the mounting pad. Beryllia (beryllium oxide—BeO) and alumina (aluminum oxide—Al2O3) are commonly used materials for the mounting pad.
Of the two, beryllia is used more extensively due to its superior thermal conductivity over alumina. However, BeO is highly toxic material, and extreme care must be exercised in handling it. Beryllia can be hazardous to the human respiratory system when in the powder form, as the BeO pad is machined or polished. Proper equipment and safeguards are needed to insure that it is handled safely and that improper contact with humans is avoided. In fact, the United States military has prohibited the use of BeO except under exceptional circumstances. Therefore, among other improvements, it would be desirable to eliminate or reduce usage of Beryllia in fabricating RF power devices.
The invention provides a packaged power semiconductor device having electrical isolation between the potential of a die inside the package and a metal back side of the package. A power semiconductor die is mounted on a direct-bonded copper (“DBC”) substrate. The die may be mounted using solder or other die-attach means. A lead of the package is also soldered to the DBC substrate. In some embodiments, all leads are soldered to connecting pads on the DBC substrate.
In one embodiment, a radio frequency power device includes a substrate including a first conductive layer, a second dielectric layer, and a third conductive layer. The first conductive layer is bonded to the second dielectric layer, and the second dielectric layer is bonded to the third conductive layer. The first and third conductive layers are electrically isolated from each other. A semiconductor die is bonded to the first conductive layer of the substrate. A plastic package encloses and protects the semiconductor die. A plurality of leads extend outwardly from the plastic package. The leads have blade-like shapes.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.
FIG. 1 illustrates a cross sectional view of a conventional RF power device.
FIG. 2 illustrates a top plan view of an RF power device using a BeO substrate.
FIG. 3 illustrates a top plan view of a high frequency RF power device according to one embodiment of the present invention.
FIG. 4 illustrates a top plan view of a high frequency RF power device with dimensions according to one embodiment of the present invention.
FIG. 5 illustrates a cross sectional view of a high frequency RF power device according to one embodiment of the present invention.
FIG. 6A illustrates a top plan view of a high frequency RF power device with the plastic package delayered according to one embodiment of the present invention.
FIG. 6B illustrates a cross sectional view of a high frequency RF power device with the plastic package delayered according to one embodiment of the present invention.
FIG. 7 illustrates a top plan view of a direct bonded metal substrate according to one embodiment of the present invention.
FIG. 8 illustrates a cross sectional view of a direct bonded metal substrate according to one embodiment of the present invention.
FIG. 9 illustrates a cross sectional view of a high frequency RF device coupled to a heatsink according to one embodiment of the present invention.
FIG. 10 illustrates a process of manufacturing a direct bonded substrate according to one embodiment of the present invention.
FIG. 11 illustrates a process of manufacturing a high frequency RF device according to one embodiment of the present invention.
FIG. 12 illustrates an exploded view of the components and devices used to manufacture the high frequency RF device according to one embodiment of the present invention.
Embodiments of the present invention use direct bonded metal substrates and plastic packages for high frequency or radio frequency (RF) power devices, thereby providing a simplified construction of an RF power device package for mass production, reduced costs, reduced thermal fatigue problem associated with multilayered packages, reduced thermal resistance of the package, reduced thermal fatigue effect, and the like.
As used herein, the term “direct bonded metal substrate” refers to substrate comprising a dielectric layer and a conductive layer bonded to each other by heating them to a temperature between the eutectic and melting temperatures of the conductive layer. The conductive layers may be copper, aluminum, or the like. The dielectric layer may be aluminum nitride, alumina, or other ceramic materials. Examples of the direct bonded metal substrate includes a direct bonded copper (DCB) or direct copper bonded (DBC) substrate, a direct aluminum bonded (DAB) substrate, and the like. Generally, the direct bonded metal substrate has two conductive layers with a dielectric layer provided therebetween. A more detail description of the direct bonded metal substrate will be provided later.
FIGS. 1 and 2 illustrate a conventional RF power device 100. The device has a semiconductor die 102 provided over a ceramic mounting substrate or pad 104. Beryllia is used for the mounting pad due to its superior thermal conductivity characteristics. The beryllia pad 104 is metalized to provide a bonding layer 106 in order to bond the die 102 to the mounting pad 104. A plurality of leads 108 are soldered or brazed to the edges of the ceramic pad 104, as indicated by solder 110. A plurality of wires are bonded to portions of the die and the plurality of leads to provide electrical coupling between these two parts of the RF power device. A ceramic cap 114 is placed over the semiconductor die, and the edges of the cap 114 are bonded to the leads 108 with solder 116, thereby providing a hermetic package.
As seen from FIG. 2, the leads 108 are configured to be wide and thin due to the “skin effect” in high frequency current. For example, a width 120 of the lead ranges from about 0.1 to 0.2 inch (2.54-5.08 mm) depending on the size of the RF power device, and a width 122 of the lead ranges from about 0.125 to 0.346 inch (3.18-8.79 mm). The thickness of the leads generally ranges from about 0.003 to 0.02 inch (0.08-0.51 mm), preferably about 0.006 inch (0.15 mm). The leads 108 are configured to have a “tape-like shape” or “blade-like shape” described above to provided increased surface area for the leads. At high frequencies (e.g., over 50 MHz) a substantial amount of the electrical current flows in outer edges (or skin) of the conductor. The magnetic fields generated by the alternating current tend to push the current towards the outside of the conductor. The current squeezes more and more tightly against the surface of the conductor at higher and higher frequencies. As used herein, the term “tape-like shape” or “blade-like shape” describes an object having a width that is significantly greater than its thickness to handle the skin effect.
The devices, such as the RF power device 100, are expensive, costing about $100, due to the use of the beryllia pad 104 and ceramic cap 114. Generally, use of ceramic material increases the cost of the device, particularly if a beryllia substrate is used. Its toxic nature requires extra care in handling and manufacturing the RF power device. For example, many countries including the United States of America require all products containing beryllia be marked as containing BeO, as indicated by a marking 124 (FIG. 2). Industries have continued using beryllia for the mounting pad 104 because of its superior thermal conductivity over aluminum nitride or alumina, particularly for high frequency RF power device with blade-like leads and operating at or above 50 MHz.
In addition, the use of the ceramic cap 114 increases the costs of manufacturing since each RF power device needs to be custom made individually. Therefore, unlike plastic packages, multiple RF power devices cannot be packaged with a plurality of ceramic caps 114 in a single process. Other disadvantages of the conventional power device 100 will become apparent as embodiments of the present invention are described below.
As used herein, the term “high frequency RF device” or “high frequency RF power device” refers to RF power device operating at or above 50 MHz, preferably over 80 MHz. Generally, high frequency RF device is provided with leads having blade-like shapes to handle the “skin effect” described above. Generally, the high frequency RF power device operates at high voltage (e.g., VDS of 500 V or greater) and outputs high power (e.g., 300 Watts or greater).
FIGS. 3-5 illustrate a high frequency RF power device 200 having a plastic package 202 and a direct bonded metal substrate (not shown) according to one embodiment of the present invention. The device 200 includes the plastic package 202 and a plurality of leads 204-214 having blade-like shapes with the leads extending outwardly from opposing sides of the package. The device 200 is designed to operate at 400 to 1500 volts (VDS), generate current (IDS) of 5 to 15 amperes, and output of 250 to 1000 Watts. The device 200 is design to operate at frequencies up to 100 MHz in one implementation, or up to 200 MHz in another implementation, or greater in yet another implementation. In one embodiment, the device 200 is a discrete device having a single semiconductor die enclosed within the package having a main surface area of about 0.2 to 1 square inch (5.08-25.4 mm).
Referring to FIGS. 4 and 5, the dimensions of the device 200 varies according to different embodiments of the present invention. For example, the package 202 has a length 216 ranging from about 0.5 to 1 inch (12.70-25.4 mm) and a width 218 ranging from about 0.5 to 1 inch (12.70-25.4 mm). The package has a thickness 219 ranging from 0.1 to 0.15 inch (2.54-3.81 mm). In the present embodiment, the package 202 has a length 216 of about 0.91 inch (23.11 mm), a width 218 of about 0.83 inch (21.08 mm) and a thickness 219 of about 0.125 inch (3.18 mm).
The device includes three types of leads, all having blade-like shapes in one embodiment of the present invention. The leads of first type, the leads 204, 208, 210, and 214, are coupled to source regions of the semiconductor die (not shown) within the package 202. Each lead has a width 220 ranging from about 0.1 to 0.17 inch (2.54-4.32 mm). The lead of second type, the lead 206, is coupled to a drain region and has a width 222 ranging from about 0.125 to 0.346 inch (3.18-8.79 mm). The lead of third type, the lead 212, is coupled to a gate and has a width 224 ranging from about 0.085 to 0.306 inch (2.16-7.77 mm). These leads 204-214 generally have a thickness 226 ranging from about 0.1 to 0.15 inch (2.54-3.81 mm). In one embodiment, the leads 204, 208, 210, and 214 have the width 220 of about 0.162 inch (4.11 mm). The lead 206 has the width 222 of about 0.346 inch (8.79 mm). The lead 212 has the width 224 of about 0.306 inch (7.77 mm). All of these leads have substantially the same thickness 226 of about 0.006 inch (0.15 mm). Accordingly, in this embodiment, the ratio of width to thickness for the leads 204, 208, 210, and 214 with the smallest width is 27, i.e., the width is 27 times greater than the thickness. In other embodiments, the ratio of width to thickness is greater (e.g., 30, 35, or 40) or smaller (e.g., 20, 15, or 10) than 27.
FIG. 6A depicts a top plan view of the device 200 with the plastic package 202 delayered as indicated by the dotted line. FIG. 6B depicts a cross sectional view of the device 200 with the plastic package 202 delayered as indicated by the dotted line. As shown, in FIG. 6B, the backside of the package 202 is flushed to the backside of the DBC substrate according to one embodiment of the present invention. FIG. 7 depicts a top plan view of a direct bonded metal substrate 228 of the device 200, and FIG. 8 depicts a cross sectional view of the direct bonded metal substrate 228, according to one embodiment of the present invention. The direct bonded metal substrate 228 has a first conductive (front side) layer 230 that is bonded to a second dielectric layer 232, typically of ceramic material, that is in turn bonded to a third conductive (backside) layer 234 (FIG. 8). The dielectric layer 232 generally has an outer edge 236, which extends beyond outer edges 238 and 240 of the first and third conductive layers, to provide better electrical isolation of the two conductive layers. The direct bonded metal substrate may be a DBC or DAB substrate. The direct bonded metal substrates provide superior thermal conductivity due to its “eutectic bond” between the conductive layers and the dielectric layer. Accordingly, in many instances, non-beryllia substrates (e.g., AlN and Al2O3) may be used for high frequency RF power devices without significantly comprising the requisite thermal conductivity.
In the present exemplary embodiment, the substrate is a DBC substrate with alumina as the dielectric layer 232. The dielectric layer could be other material, such as aluminum nitride, beryllia (BeO), or other insulating material compatible with direct bonded metal substrate fabrication. One or both of the copper layers may be tinned or plated. Each layer of the copper layer is about 0.0118 inch (0.30 mm) thick, and the alumina layer is about 0.0248 inch (0.630 mm) thick, making the DBC substrate about 0.0484 inch (1.230 mm) thick overall. However, these thickness are given as examples only and thicker or thinner layers could be used. In one embodiment, due to the toxic nature of beryllia, aluminum nitride and alumina are the materials of choice for the dielectric layer.
The first conductive layer 230, e.g., a copper layer, is patterned to have a plurality of conductive islands or blocks 242-252 that are separated by the ceramic layer 232 provided below (FIG. 7). Referring to FIG. 6, a bonding portion 254 of the lead 204 is bonded to the block 242; a bonding portion 256 of the lead 206 is bonded to the block 244; a bonding portion 258 is bonded to the block 246; a bonding portion 260 of the lead 210 is bonded to the block 248; a bonding portion 262 of the lead 212 is bonded to the block 250; and a bonding portion 264 of the lead 214 is bonded to the block 252. These bonding portions of the leads are soldered to the respective blocks of the first conductive layer 230. A semiconductor die 266 with one or more transistors defined thereon is bonded to the block 244. Various conductive regions, such as, gate, source, and drain regions, are electrically coupled to the leads via wires 268 extending from the die to the leads. In one embodiment, the wires 268 are aluminum wires but other conductive wires may be used. Bonding the leads to the blocks of the first conductive layer 230, as shown in FIG. 6, facilitates manufacturing of a plurality of the devices 200 in a single assembly process, as will be described in more detail later. In addition, the solder bonding the leads to the blocks provides more stable joining of the leads to the package 202, than merely bonding the leads to the edges of the ceramic cap as in the conventional device 100 in FIG. 1.
The power device 200 with a DBC substrate 228 tends to provide greater structural integrity. The substrate or pad, on which the semiconductor die, is provided is less likely to crack because the composite DBC structure provides support for the ceramic layer. Cracking of the semiconductor die is also reduced because the thermal expansion coefficient of copper more closely matches that of silicon than does the thermal expansion coefficient of typical ceramics.
Furthermore, using a bare ceramic substrate for power devices generally increases costs. To manufacture the conventional power device 100, a die attach pad is usually provided to attach the die to a ceramic substrate. This is often done by silk-screening a metal-glass frit onto the ceramic substrate and firing the frit. The metal in the frit is usually an expensive noble metal, and the screening and firing process results in additional yield loss.
The backside copper layer 234 also improves the thermal performance of the power device 200. The temperature in the vicinity of the die (“underneath” the die) tends to be higher than the temperature at the edge of the ceramic layer 232. Although the extent of this heat gradient depends on many factors, the backside copper layer 234 effectively spreads the heat across the entire ceramic layer, thereby reducing the formation of a hot-spot underneath the die. More effective heat distribution also reduces heat-related stress and resultant cracking of the substrate and/or die, thus improving reliability.
Additionally, the direct-bonding process, described below, intimately attaches the copper to the ceramic (i.e., creates a “eutectic bond” between the copper and ceramic) and provides excellent thermal conduction from one layer to the other. This thermal conduction provided by the copper layer 234 is better than that typically provided by contacting a bare ceramic substrate to a heatsink. The relatively high thermal resistance of the ceramic impedes lateral heat spreading, so that each microscopic contact point with the heatsink becomes a hot-spot. In contrast, the heat-conductivity of the backside copper layer 234 provides good lateral heat conduction and reduces the consequences of localized contact with the heatsink. Moreover, the backside copper layer allows the RF power device 200 to be soldered to a heatsink, thermally coupling the entire area of the backside layer to a heatsink 260, as shown in FIG. 9.
Even if the back side of a ceramic substrate were coated with frit and fired, the thermal performance would not equal that of the DBC packaged device, such as the power device 200, as the metal-glass matrix of the fired frit does not conduct heat as well at the copper layer of the DBC packaged device.
FIG. 10 depicts a method 300 for forming the direct bonded metal substrate 228, e.g., a DBC substrate, according to one embodiment of the present invention. A detailed description of manufacturing the direct bonded metal substrate according to one embodiment is provided in U.S. Pat. No. 4,483,810, which is incorporated by reference for all purposes.
Generally, the method involves placing a conductive or metal substrate on a dielectric or ceramic substrate and heating them to a temperature between the eutectic temperature and the melting temperature of the conductive substrate. For example, a metal substrate, e.g., copper, is placed on a ceramic substrate (step 302). A thin oxide layer may be formed over the copper substrate on the side facing the ceramic substrate or on the both sides. The copper and ceramic substrates are placed in a carrier, preferably of silicon carbide or graphite core with a silicon carbide coating, and inserted into a furnace. The copper and ceramic substrates are preheated (step 304). The preheat step is typically performed in a first zone within the furnace to gradually ramp up the temperature of the substrates. The first zone may include a plurality of sub-zones in one embodiment. The temperature within the first zone is kept at no more than about 960° C. in one embodiment of the present invention.
The copper and ceramic substrates are heated to a temperature between eutectic and melting temperatures of copper (step 306). Generally, the substrates are moved into a second zone within the furnace during this step. In one embodiment, the peak temperature within the second zone is less than 1083° C., preferably about 1071° C., to raise the temperatures of the substrates to above the eutectic temperature of copper, which is about 1065° C. As a result a eutectic melt is formed between the copper substrate and the ceramic substrate.
The substrates are cooled to a predetermined temperature to solidify the eutectic melt (step 308). Generally, the substrates are moved to a third zone within the furnace. The solidification of the eutectic melt does not occur instantaneously, and the bonding process is not completed until the temperature drops well below the eutectic temperature, usually about 100° C. below the eutectic temperature. The cooling process generally involves two or more steps to gradually ramp down the temperature during a period of about 20 minutes. The resulting product is a direct bonded copper substrate, such as the DBC substrate 228 (step 310).
FIG. 11 shows an assembly process 400 for attaching leads and dice to direct bonded metal substrates, e.g., DBC substrates, in a single soldering operation according to one embodiment of the present invention. The process 400 does not use a ceramic cap nor a ceramic base or pad with preattached leads to package the power devices. Rather, the power devices, e.g., the device 200, according to the present embodiment uses a DBC substrate as the only ceramic part of the device. The semiconductor die and DBC substrate are encapsulated in plastic by an injection molding process. Use of non-beryllia substrates, a single soldering operation (or assembly process), and a plastic molding process according to the process 400 significantly reduces the manufacturing cost of the high RF power devices. For example, a high frequency power device, such as the device 200, that is manufactured using the process 400 may be sold at about $10-20. In contrast, the conventional RF device 100 (FIG. 1) is being sold at about $100.
FIG. 12 provides an exploded view of the components and devices used for the process 400 according to one embodiment of the present invention. A graphite assembly boat 502, 502′, a plurality of DCB or DBC substrates 504, 504′, a plurality of solder preforms 506, 506′, a lead frame 508, 508′, a graphite chip aligner 510, 510′, a plurality of solder preforms 512, 512′, and a plurality of semiconductor chips or dice 514, 514′ are used to manufacturing a plurality of high frequency RF power devices, such as devices 200, according to the process 400. The numerals without the primes depict top plan views of the components and devices, whereas the numerals with the primes depict side views of the components and devices used in the process 400.
Referring back to FIG. 11, the DBC substrates 504 are placed in machined pockets in the graphite assembly boat 502 (step 402). In other embodiment, the assembly boat may be of material other than graphite. The solder preforms 506 are placed over the DBC substrates on opposite sides 516 and 518 of the substrates (step 404). The lead frame 508 is placed in a separate machined pocket of the assembly boat to align the bonding portions 520 and 522 of the lead frame to corresponding portions of the patterned die-side copper layer of the DBC substrate (step 406). That is, the sides 516 and 518 of the DBC substrates are aligned to the bonding portions 520 and 522. The chip aligner tool 510 is placed over the assembly boat, further holding the leads in proper alignment to the DBC substrate (step 408). The solder preforms 512 are placed within a plurality of openings 524 (step 410). The power semiconductor dice 514 are placed over the solder preforms 512 and in the opening 524 of the chip aligner tool, thereby aligning the chips to the DBC substrate (step 412). The resulting assembly is then heated to melt the solder preforms 506 and 512, thereby concurrently soldering the lead frame and power semiconductor dice to the DBC substrates (step 414). The solder process is typically carried out in a single pass in a reflow belt furnace in a reducing atmosphere, thus eliminating the need for a solder flux, as is known in the art, but other furnaces or heat sources could be used. The chips are wirebonded to the leads to provide proper electrical connections (step 416). The resulting product, a plurality of devices held together by the lead frame, is placed in an injection molding tool to encapsulate each device with a plastic package (step 418). The product is cut and trimmed to form individual devices as shown in FIGS. 3-5 (step 420).
In other embodiments, the chip could be attached to the DBC substrate in one operation and the leads attached in another, such as using a high-temperature solder or braze, or eutectic die attach, for the chip attach, and another solder, spot-weld, or similar operation for the lead attach. DBC substrates could be attached to lead frames, and these subassemblies could be shipped to an assembly facility, where the semiconductor dice would be attached and the wire-bonding and encapsulation performed. Normally, the first attachment process, whether it be used to attach the leads or the dice, results in an attachment that is reliable at the temperature of the second attachment process.
While the invention has been particularly shown and described with reference to a specific embodiment thereof, it will be understood by those skilled in the art that the foregoing and other changes in the form and details may be made therein without departing from the spirit or scope of the invention. Therefore, the scope of this invention should not be limited to the embodiments described above, and should instead be defined by the following claims.
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|US20110181383 *||Mar 30, 2011||Jul 28, 2011||Lotfi Ashraf W||Micromagnetic Device and Method of Forming the Same|
|U.S. Classification||257/735, 257/E23.106, 257/E23.092, 257/692|
|International Classification||H01L23/373, H01L23/433, H01L23/66|
|Cooperative Classification||H01L2924/181, H01L24/48, H01L24/49, H01L2924/01013, H01L2224/49111, H01L2224/45124, H01L2924/30107, H01L2924/09701, H01L23/66, H01L2924/15153, H01L2924/01322, H01L24/45, H01L2224/48247, H01L2924/14, H01L23/4334, H01L2924/16152, H01L2224/48091, H01L2924/01004, H01L23/3735, H01L2924/15165, H01L2223/6644, H01L2924/16787, H01L2924/01014, H01L2224/73265|
|European Classification||H01L23/373L, H01L23/66, H01L23/433E|
|Nov 13, 2001||AS||Assignment|
Owner name: IXYS CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHOI, KANG RIM;REEL/FRAME:012329/0315
Effective date: 20011101
|Sep 26, 2007||FPAY||Fee payment|
Year of fee payment: 4
|Sep 23, 2011||FPAY||Fee payment|
Year of fee payment: 8
|Oct 27, 2015||FPAY||Fee payment|
Year of fee payment: 12


text:
Interested in talking with us about your project or idea?
Why Woodys Lawn and Landscape?
Since opening our doors in 1992, Woodys Lawn and Landscape has been helping clients throughout Lincoln transform their yards into incredible outdoor living spaces. We specialize in creating innovative landscape and hardscape designs, in-ground sprinkler system installation and repair, and all the lawn care services you need throughout the year!
From custom fertilizer applications to mowing and weeding, we do it all! See what our lawn maintenance services can do for your yard all year long.
Want to turn your backyard into the ultimate hangout area? We can help by designing and building an incredible living space like outdoor kitchens, decks, and coverings such as pergolas!
Keep your lawn looking great throughout the summer with the installation of a sprinkler system! We’ll construct the perfect hassle-free solution to watering your yard that perfectly fits your needs.

domain: agronomy


Steven Chaitman wrote: "When you write/blog about movies, there are two non-verbally accepted truths: 1.) It's never too early give Oscar predictions (just ask our own Julian Stark about that one) and 2.) There's no unacceptable time to evaluate the year's best movies."
Our Season is a South Korean fantasy drama film set to release in theatres this December. Read all about the movie's release date, cast and more here.
Read our My Man is Cupid Episode 3 Preview to know whether Sang-hyuk will find who Baek-ryun really is.


Stand out with this incredible Maxton Design Front Racing Splitter V.3 for your BMW Series 4 F32 M-Pack & M-Performance. (Years: 2013 - 2019)
Fits: BMW 4 F32 M-PACK & M-Performance 2013 - 2019
COMPLETE SET CONTAINS:
- SPLITTER / FRONT BUMPER LIP SPOILER
- Mounting kit
If you want to get a slick high-end front splitter, the Maxton Design offer is where you should be looking. The brands assortment is filled with neat splitters, diffusers, bumpers, side skirts, and spoilers. These components serve not only as visual upgrades, but as aerodynamic ones, too. They can be added to an exceptional selection of different vehicles including BMW 4 F32 M-Pack/M-Performance. With this model in mind we have come up with many interesting tuning elements. The one that stands out, however, is this V.3 racing front splitter.
What is special about this V.3 racing front splitter for BMW 4 F32 M-Pack/M-Performance?
- it enhances aerodynamics
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- it’s delivered fit to be installed right away
The advanced V.3 racing splitter for BMW 4 F32 M-Pack/M-Performance is made of ABS (CNC) plastic. The material is well known in the automotive industry and it is often employed in the production of standard car outfitting parts, as well as, showy optical tuning components. It shows stand-out damage-resistance, and durability. The ABS applied by Maxton Design is TUV certified and the products made with its use are going to serve you for a long time without losing their slick looks.
This V.3 racing front splitter for BMW 4 F32 M-Pack/M-Performance is an item that bolsters aerodynamics in a significant manner. It directly causes an increase in the pressure exerted on the front axle by the air passing under the bumper. The result of this is notably boosted traction and stability. The splitter also makes the bodywork appear optically lower which gives your machine a sharp sports car look. This item consists of steel tie bars and an aesthetic splitter which is produced out of ABS (CNC). The original V.3 racing front splitter dedicated to BMW 4 F32 M-Pack/M-Performance will become an amazing decorative addition that draws the looks off all the tuning enthusiasts.
Images of products are only for information purposes and can change due to continuous product development. Prices, images and product description are subject to change without notice. Not responsible for typographical errors.


text:
Insights Daily Current Affairs, 26 June 2017
Paper 2 Topic: Bilateral, regional and global groupings and agreements involving India and/or affecting India’s interests.
Prime Minister Modi and Prime Minister Costa launch unique Start-up portal
Prime Minister Modi and Prime Minister Costa recently launched a unique startup Portal – the India-Portugal International StartUp Hub (IPISH) – in Lisbon.
What you need to know about IPISH?
This is a platform initiated by Startup India and supported by Commerce & Industry Ministry and Startup Portugal to create a mutually supportive entrepreneurial partnership.
- IPISH hosts a range of tools and will provide information on the start-up hotspots of Bangalore, Delhi and Lisbon; and on associated subjects, such as policy, taxation, and visa options. It will develop a Go-To-Market Guide to support start-ups.
- IPISH is expected to help in mutual capacity building, and enable connections between start-ups, investors, and incubators from relevant sectors. It is also expected to establish a network of honorary ambassadors based in India and Portugal to guide start-ups from both countries.
There are strong complementarities between India and Portugal in the start-up sector. Portugal has one of the highest rates of business creation in Europe and has emerged as one of the most vibrant European eco-systems for entrepreneurship. Lisbon is also hosting the Web Summit – a key annual international technology conference – for 3 years from 2016 onwards.
Paper 3 Topic: Indian Economy and issues relating to planning, mobilization of resources, growth, development and employment.
States’ fiscal deficit soars to Rs 4.93 trillion in FY16
RBI has released second edition of it’s statistical publication titled ‘Handbook of Statistics on States 2016-17‘.
- The publication follows the ‘one-indicator-one table’ approach and covers all sub-national statistics on socio- demographics, state domestic product, agriculture, industry, infrastructure, banking and fiscal indicators across the states over a period ranging from 1950-51 to 2016-17.
- It also offers data on state-wise availability of power, per capita availability of power, installed capacity of power, and power requirement, length of national highways, roads and state highways, and railheads.
Highlights of the report:
- Led by the most populous Uttar Pradesh and the largest Rajasthan, the gross fiscal deficits of all the states skyrocketed to Rs 4,93,360 crore in fiscal 2016 from Rs 18,790 crore in FY1991.
- Uttar Pradesh had a fiscal deficit of a paltry Rs 3,070 crore in FY91, which zoomed to Rs 64,320 crore in FY16 and but is projected to improve to Rs 49,960 crore in FY17.
- Rajasthan, which had a gross fiscal deficit of Rs 540 crore in FY91, saw it soaring to Rs 67,350 crore in FY16 and is projected to decline to Rs 40,530 crore in FY17.
- Maharashtra, one of the most urbanised and industrialised states, had a gap of Rs 1,020 crore in FY91 but the same jumped to Rs 37,950 crore in FY16 which is projected to improve to Rs 35,030 crore in FY17.
- Gujarat, which had seen rapid industrialisation during the period of data analysis, had only Rs 1,800 crore in fiscal deficit in FY91 but the same had jumped to Rs 22,170 crore in FY16 and is projected to further deteriorate in FY17 to Rs 24,610 crore.
- Reflecting its improved finances on the back of rising investments following better law and order situation, Bihar is slated to improve its finances with fiscal deficit of Rs 16,010 crore in FY17 against Rs 28,510 crore in FY16. The state which had for long been the badland of the nation had Rs 15,90 crore deficit in FY91.
- West Bengal, despite having high debt levels, has been improving its finances with its fiscal deficit projected to improve to Rs 19,360 crore in FY17 from Rs 25,180 crore a year ago and a healthy Rs 1,630 crore in FY91.
Sources: the hindu.
Paper 2 Topic: Welfare schemes for vulnerable sections of the population by the Centre and States and the performance of these schemes; mechanisms, laws, institutions and bodies constituted for the protection and betterment of these vulnerable sections.
Kanyashree Scheme For Girls In Bengal Wins UN Award
The West Bengal government is among the winners to receive the prestigious UN Public Service Award for its initiative to combat child marriage and ensure education to the girl child in the state. The West Bengal government was among the 12 institutions from 11 countries that were recognised by the world body on UN Public Service Day, commemorated on June 23rd.
- India was named first in the Asia-Pacific group for the category: ‘Reaching the Poorest and Most Vulnerable through Inclusive Services and Participation’.
West Bengal has been awarded for the ‘Kanyashree Prakalpa‘ initiative that sought to reduce the high child marriage rates and low female education rates in the state. Through the initiative, cash was deposited into the bank account of girls for every year they remained in school and were unmarried. This initiative led to a “drastic reduction in child marriage, increase in female education and female empowerment.”
UN Public Service Awards:
The UN Public Service Awards are given by the world body to institutions from across the world for their innovation and excellence in providing public services. It highlights the pivotal role of public services in the implementation of the Sustainable Development Goals (SDGs). The Awards aim at discovering innovations in governance; reward excellence in the public sector; motivate public servants to further promote innovation; enhance professionalism in the public service; raise the image of public service; enhance trust in government; and collect and disseminate successful practices for possible replication.
The UN Public Service Day is celebrated every year to recognise public service innovations and excellence that have led to more effective and inclusive public service delivery contributing to the achievement of the SDGs in countries worldwide.
Sources: the hindu.
Paper 2 Topic: Statutory, regulatory and various quasi-judicial bodies.
EC disqualifies Minister in M.P.
The Election Commission has disqualified Narottam Mishra, Minister in the Madhya Pradesh government from membership of any State legislature and contesting polls for the next three years for filing wrong accounts of election expenditure.
What you need to know about the issue?
Powers of election commission to disqualify:
Membership of the minister was revoked under section 10A of the Representation of the People Act, 1951, to be read with Sections 77 and 78 of the Act. This relates to providing wrong information to the Commission on expenses incurred during the polls.
Advisory Jurisdiction & Quasi-Judicial Functions of Election Commission:
Under the Constitution, the Commission also has advisory jurisdiction in the matter of post election disqualification of sitting members of Parliament and State Legislatures. Further, the cases of persons found guilty of corrupt practices at elections which come before the Supreme Court and High Courts are also referred to the Commission for its opinion on the question as to whether such person shall be disqualified and, if so, for what period. The opinion of the Commission in all such matters is binding on the President or, as the case may be, the Governor to whom such opinion is tendered.
- The Commission has the power to disqualify a candidate who has failed to lodge an account of his election expenses within the time and in the manner prescribed by law. The Commission has also the power for removing or reducing the period of such disqualification as also other disqualification under the law.
Sources: the hindu.
Paper 2 Topic: Government policies and interventions for development in various sectors and issues arising out of their design and implementation.
Yettinahole hits a hurdle in coffee land
The ongoing land acquisition for the Yettinahole drinking water project has hit a hurdle with some farmers unhappy with the price chart fixed by the district committee and are refusing to part with land. Though the Karnataka Cabinet approved direct acquisition as a special case to speed up the process, this could mean a slowdown.
Karnataka Neeravari Nigam Ltd. (KNNL) is currently acquiring land in Sakleshpur taluk and coffee estate owners are unhappy with the prices fixed under the Right to Fair Compensation and Transparency in Land Acquisition, Rehabilitation and Resettlement Act.
About Yettinahole project:
The Yettinahole project envisages to pump about 24 tmc ft of water from Yettinahole, a tributary of River Netravathi.
- It involves construction of dams and reservoir, pumping of water, flowing of water with gravitational force and finally filling of lakes.
- As per the project, 24 tmc ft of water from Yettinahole and a couple of other tributaries of Netravathi River will be drawn by constructing minor dams.
- The project envisages diverting the water to drought prone Chikkaballapur, Tumkur and Bangalore rural districts.
- The total cost of the project is Rs 8,323 crore.
Sources: the hindu.
Paper 3 Topic: Awareness in the fields of IT, Space, Computers, robotics, nano-technology, bio-technology and issues relating to intellectual property rights.
NASA’s CHESS to study interstellar clouds
NASA is launching a sounding rocket CHESS to study vast interstellar clouds and know about the earliest stages of star formation.
Deep in space between distant stars, space is not empty. Instead, there drifts vast clouds of neutral atoms and molecules, as well as charged plasma particles called the interstellar medium — that may, over millions of years, evolve into new stars and even planets. These floating interstellar reservoirs are the focus of the NASA-funded CHESS sounding rocket mission, which will check out the earliest stages of star formation.
What you need to know about CHESS?
The Colorado High-resolution Echelle Stellar Spectrograph will measure light filtering through the interstellar medium, which provides crucial information for understanding the lifecycle of stars.
- CHESS will train its eye at Beta Scorpii — a hot, brightly shining star in the Scorpius constellation well-positioned for the instrument to probe the material between the star and our own solar system.
- This is the third flight for the CHESS payload in the past three years, and the most detailed survey yet.
Sources: the hindu.
Facts for Prelims:
Places in News- Lisbon:
PM Modi recently paid a visit to Lisbon, Portugal.
Location: Lisbon is the capital and the largest city of Portugal. It is continental Europe’s westernmost capital city and the only one along the Atlantic coast. Lisbon lies in the western Iberian Peninsula on the Atlantic Ocean and the River Tagus.
Metro rail tunnels under Hooghly set a record:
The Kolkata Metro Rail Corporation (KMRC) has completed the construction of India’s first set of underwater transportation tunnels. The two tunnels, 16.1 metres apart, with a diameter of 5.5 metres each, link the two banks of the Hooghly river — Howrah Maidan and Sealdah on one side with Kolkata on the other. The tunnels are at a depth of 13 metres below the riverbed, and 30 metres from the land surface.

domain: news


|Publication number||US5194813 A|
|Application number||US 07/760,544|
|Publication date||Mar 16, 1993|
|Filing date||Sep 16, 1991|
|Priority date||Sep 16, 1991|
|Also published as||CA2065123A1, CA2065123C, EP0533621A2|
|Publication number||07760544, 760544, US 5194813 A, US 5194813A, US-A-5194813, US5194813 A, US5194813A|
|Inventors||Kenneth H. Hannah, Ronald R. Plante|
|Original Assignee||Hannah Kenneth H, Plante Ronald R|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Referenced by (28), Classifications (7), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to a device for testing and diagnosing the ignition system of an internal combustion engine. In particular, this invention relates to a hand held portable ignition tester.
Modern automobile engines have become more complex in recent years. In particular, automobile engines can have either a conventional ignition system or a non-distributor ignition system. In either case, if the engine is not operating properly it is necessary to evaluate whether the spark plugs of an engine are firing properly.
Most conventional ignition systems generate a high voltage negative pulse to the spark plug. Since electrons are negative, it is easier to repel them from the centre electrode to cause a spark. Non-distributor type designs, i.e. electronic ignition systems, use a high voltage positive pulse to cause the spark plug to fire.
When an ignition coil is pulsed, the secondary voltage will rise with respect to the polarity of the system. The spark will not disturb this rise in voltage until the spark potential has been reached. At this point, the spark plug undergoes a step change in terminal resistance suddenly presenting a low resistance path to ground. This will cause the energy in the coil secondary to discharge and rapidly collapse the voltage. The energy will jump across the gap causing a spark which ignites the fuel-air mixture. The effect of the spark is the generation of an initial high amplitude, high frequency, counter-voltage spark burst.
It is well known that electromagnetic emissions are generated by the ignition wires during normal operation of an engine. It is also well known that by sampling the electromagnetic emissions, ignition information can be obtained for evaluating the operation of the engine. Prior art devices are either triggered by the electromagnetic emissions or measure the amplitude of the emissions to provide spark information.
Many prior art devices merely sense the level or amplitude of high voltage along the ignition wires. The basic operating theory of these devices is that the coil voltage will only climb as high as required to cause the spark plug to fire. When the plug does fire, coil energy is released, clamping any further voltage rise. As engine speed increases, the corresponding increase in cylinder compression will require more voltage for the spark plug to fire.
Neon type testers use this theory by relating the brightness of the neon tube directly to voltage in the ignition wire. The neon tube will appear brighter with increases in engine speed. Oscilloscopes will visually display on a screen the higher voltage required for the spark plug to fire. Both of these devices translate the signal level amplitude of the ignition wires and correlate the amplitude to the potential for a spark.
In the case of the neon type tester, a certain degree of skill and training is required in order to properly interpret the brightness of the neon light as it relates to the spark condition of the ignition system. For the do-it-yourself mechanic, such device would be generally unsuitable without practice. Further, the brightness of such devices is poor making these devices unsuitable for outdoor use. Oscilloscopes are generally too expensive for the do-it-yourself mechanic.
The prior art devices generally measure or detect only an increase in voltage for a sparking potential of the ignition system. These devices are generally not suited for all conditions of spark. Merely because the ignition system has sufficient voltage to generate a spark does not necessarily mean that a spark will in fact occur.
Other devices attempt to determine whether a spark has occurred by measuring or detecting a current in the ignition wire. If the spark plug is operating or firing in a normal manner, there will be a pulsating current flow through the associated ignition wire. By detecting this current, the device indicates a spark condition.
In normal operation of an engine, these devices will detect a spark. However, this type of device will not properly diagnose a condition where the spark plug is wet. Such condition occurs when the engine is choked during start-up. In this case, the voltage increases, yet current will flow through the conductive fuel mixture thereby indicating a spark condition even though the spark plug has not fired.
The disadvantages of the prior art may be overcome by providing an ignition tester which detects a spark condition by sampling the electromagnetic emissions generated by the ignition of the engine and decoding the frequency and amplitude of the voltage pulses.
The invention provides a tester which will detect a voltage increase for spark condition and then detect a high frequency burst indicating a spark.
The invention provides a probe which will not distort the high frequency spark burst.
According to one aspect of the invention a spark ignition analyzer is provided comprising, a probe having a first and second pick-up responsive to a voltage from an ignition wire, a high tension detector means for detecting an absolute voltage increase from the first pick-up and triggering a first signal for a predetermined time period, and a spark detector means for detecting a high frequency voltage fluctuation from the second pick-up and triggering a second signal for a predetermined time period. The combination of signals is used to analyze the ignition system of an engine.
According to another aspect of the invention, a spark ignition analyzer is disclosed comprising,
a probe having a first and second pick-up responsive to a voltages from an ignition wire of an engine, with the second pick-up sensitive to high frequencies,
a high tension detector means for detecting an absolute voltage increase from the first pick-up and after detecting the voltage increase generating a first pulse with a first period,
a first signal means responsive to the first pulse and adapted to signal for a predetermined time period, and
a spark detector means for detecting a high frequency voltage fluctuation from the second pick-up within a second period immediately after the first period and after detecting the voltage fluctuation generating a second pulse,
a second signal means responsive to the second pulse and adapted to signal to the end of the predetermined time period,
whereby the combination of signals provides analytical information of the state of operation of the engine.
The high tension detector means includes a polarity detection means for determining the polarity of the voltage increase from the first pick-up and generating a corresponding positive or negative signal adapted to condition the spark detector means to detect a corresponding voltage decrease. The high tension detection means comprises a first transistor means for amplifying a negative voltage and a second transistor means for amplifying a positive voltage. The first transistor means is operably connected to a first RS latch and the second transistor means operably connected to a second RS latch, with the first RS latch adapted to trigger a first timer means to initiate the first time period and to generate the negative signal, and with the second RS latch adapted to trigger the first timer means to initiate the first time period and to generate the positive signal.
The spark detector means comprises
a third transistor means for amplifying a negative voltage from the second pick-up and operable after receiving the negative signal, and
a fourth transistor means for amplifying a positive voltage from the second pick-up and operable after receiving the positive signal,
a second timer means for generating the second period and
a lagging edge trigger,
the second timer means initiating when the first pulse decreases to a zero voltage and enabling the lagging edge trigger for the second period. The trigger is responsive to a voltage decrease from either the third or fourth transistor means, and if detected, generating the second pulse.
The apparatus may optionally have a polarity identification means for determining the polarity of the ignition system of the engine. The identification means comprises a third RS latch operably connected to a third signal means and adapted to signal upon receiving the negative signal and a fourth RS latch operably connected to a fourth signal means and adapted to signal upon receiving the positive signal.
Still further, the analyzer may include a switch for switching between a spark mode to spark malfunction mode, a fifth RS latch operably connected to the lagging edge trigger and a non-inverted output of the second timer whereby a second pulse is generated if a voltage fluctuation is not detected.
Still further, the analyzer may be operated in combination with a booster lead operably connected between a spark plug and ignition wire of the engine. The lead has a low potential gap for increasing the apparent gap of the spark plug.
Still further, the analyzer may be operated in combination with an electrical probe connected to ground and systematically grounding each spark plug.
In drawings which illustrate embodiments of the invention,
FIG. 1 is a front view of the preferred embodiment,
FIG. 2 is a block diagram of the circuit of the preferred embodiment of FIG. 1,
FIG. 3 is an illustration of a simplified waveform of an ignition voltage,
FIG. 4 is a detailed circuit diagram of the preferred embodiment of FIG. 1,
FIG. 5 is a partial sectional view of the probe of the embodiment of FIG. 1,
FIG. 6 is a detailed circuit diagram of a Spark Malfunction mode,
FIG. 7 is a detailed circuit diagram a coil polarity with memory mode,
FIG. 8 is an illustration of a booster lead, and
FIG. 9 is an illustration of short circuit stick.
The invention is generally illustrated as 10 on FIG. 1. The spark ignition analyzer comprises a body 10, a cover 12, a lead 14 connected to the body and a probe 16.
Body 10 is formed from two half shells to encase the circuitry contained therein and joined by suitable means. Body 10 is moulded to present a narrow section 16 for wrapping lead 14 thereabouts for storage thereof. Body 10 has a receptacle 18 in one end for retaining probe 16 for storage. Cover 12 will cover body 10 to enclose probe 16 and lead 14 for storage.
High tension LED 20 and spark LED 22 are mounted on body 10 at an end opposite receptacle 18. Clear memory button 24 is also mounted near LEDs 20 and 22. Function button 26 is mounted adjacent to memory button 24. The body 10 can have markings or other indicia near each component for identification purposes.
The probe of the present invention is illustrated in detail in FIG. 5. The probe comprises a body 30 having a high tension pick-up 32. At one end of the high tension pick-up is a solid spark pick-up 34 which has a diameter greater than that of the high tension pick-up 32. Clip 33 is mounted on body 30 and is biased towards body 30 to provide a clamping force therebetween allowing the probe to grip an ignition wire.
The end of body 30 has a fibre washer 36 to insulate the body which is grounded from the pick-ups. Likewise, spark pick-up 34 is provided with a fibre washer 38. Optionally, the entire probe may be coated with an insulating material to reduce the high tension induction onto the tester and to reduce electrostatic induction to the circuitry.
The circumferential surface of high tension pick-up 32 is electrically connected to the High Tension Detector as illustrated in FIG. 2. The spark pick-up 34 is electrically connected to the Spark Detector co-axially through the center of pick-up 32.
High tension pick-up 32 is a conventional inductive coil pick-up, having a secondary winding. A voltage conducted through ignition wire 28 will induce a voltage in the secondary winding of pick-up 32.
Spark pick-up 34 is an inductive coil having a high sensitivity to the high frequencies commonly generated by a spark and a low sensitivity to resonant coil frequencies.
Passive components can be inserted into the probe circuitry to match impedance of the main circuitry, if the probe dimensions are tailored for a specific requirement.
FIG. 3 illustrates a simplified waveform the voltage of a typical ignition spark. When an ignition coil is pulsed at T0, the secondary voltage will rise with respect to the polarity of the system. The spark will not disturb this rise in voltage until the spark potential has been reached. At this point T1, the spark plug undergoes a step change in terminal resistance suddenly presenting a low resistance path to ground. This will cause the energy in the coil secondary to discharge and rapidly collapse the voltage. The energy will jump across the gap causing a spark which ignites the fuel-air mixture. There is an initial voltage increase lasting between 10 to 100 microseconds. This voltage collapses rapidly through zero with a series of high frequency opposite pulses lasting 0.1 to 1 microsecond. A short time period T2 is selected to detect the high frequency burst.
FIG. 2 illustrates the block diagram of the operation of the present invention. Probe 16 is connected to the ignition wire 28. An ignition coil's pulse, secondary voltage passing through ignition wire 28 will rise in a direction, either positive or negative, with the polarity of the system.
With reference to FIG. 2, the first stage of the circuitry generally comprises a Bilateral High Tension Detector which detects the initial voltage increase or first pulse and a Bilateral Spark Detector which has a high sensitivity to the spark frequencies and a low sensitivity to resonant coil frequencies.
Detection of the first pulse by the Bilateral High Tension Detector will enable the First Pulse Detector to trigger a timer to drive the high tension LED 20 for a period of time. The Bilateral High Tension Detector will pass the first pulse but will not be affected by the subsequent pulses while the timer is enabled.
The First Pulse Detector will identify the polarity of the first pulse as being either positive or negative. A signal is generated from the First Pulse Detector to the Polarity Select Logic which will then send a signal to the Bilateral Spark Detector whereby the Spark Detector polarity will be opposite of the polarity of the first pulse.
At T1, the first pulse is collapsing causing the voltage to pass through zero voltage and trigger the Zero Crossing Sample Timer. The Zero Crossing Sample Timer will enable the operation of the Lagging Edge Trigger for a short time period T2 of approximately two microseconds. The Lagging Edge Trigger will detect the falling or lagging edge of the second pulse. The second pulse must occur within the Zero Crossing Sample Timer period and be short enough to collapse within this time reference. In other words, the combination of the Zero Crossing Sample Timer and Lagging Edge Trigger measures the time period of the second pulse. The presence of a Lagging Edge Trigger pulse will determine if the spark has been fired. If detected, a signal will be generated to illuminate the spark LED 22 the remainder of the timer period.
With reference to FIG. 4, a detailed circuit diagram is illustrated. T1 is the negative High Tension Detector and T2 is the positive High Tension Detector. The voltage from the probe is fed into the Bilateral High Tension Detector. The output of the negative detector is fed into NOR 1 which is the signal inverter to standardize the voltage for the next portion of the circuit. NOR 1 generates an output Vn.
Vn is fed into the First Pulse Detector. NAND 1 and NAND 2 are arranged as an RS latch. Vn is inputted into the set of this latch, the NAND 2 input. The output of the first pulse latch is used to trigger monostable timer A which in turn activates the reset of the latch through NAND 1 input. By enabling the reset after the trigger pulse, the toggle of the initial Vn thereby terminates further pulses for the remainder of the monostable timer A period. The output of NAND 2 will exhibit the first pulse negative signal (F.P.N.).
NAND 3 and NAND 4 are likewise arranged as an RS latch. The Vp is input to the set of the latch. NAND 3 and NAND 4 will act in the manner identical to NAND 1 and NAND 2 except that the output of NAND 3 will be the first pulse positive signal (F.P.P.). The output of the first pulse latch either F.P.N. or F.P.P. is supplied to NAND 5 to supply a common trigger pulse to monostable timer A. The output of NAND 5 is also supplied to the monostable trigger B.
As an added feature, a second trigger is provided (C11, R16 and D1) which will cause the high tension LED 22 to flash when the tester is turned on.
Monostable timer A will supply a single pulse to drive the high tension LED circuitry. The monostable timer in the present embodiment is set to approximately 4.0 milliseconds by selecting the value R19 and C13.
The time period for the pulse is a selection between the LED effective intensity and the pulse width saturation. At 4.0 milliseconds, the monostable timer A will meet approximately 15,000 pulses per minute which many engines will not exceed this value.
The high tension latch, NOR 5 and NOR 6 is arranged as an RS latch. The output of NOR 6 drives the high tension transistor T5 and the output of NOR 5 controls the reset input to the spark latch.
NOR 4 will provide the monostable pulse to the reset of the high tension latch. The output of NOR 4 normally is a complimentary monostable pulse which continually resets the high tension latch of the High Tension Detector during the monostable timer off periods.
The high tension driver, T5 acts a sink to the high tension LED. R22 limits the current to the LED to less than 20 milliamps.
T3 is the negative spark detector and T4 is the positive detector of the Bilateral Spark Detector. The output of T4 is fed into NOR 2 to standardize the voltage for the next portion of the circuit.
NAND 6 and NAND 7 form the polarity logic circuit to the Bilateral Spark Detector. NAND 6 and NAND 7 are always active and are used as a protective measure to insure accurate spark detection when testing distributor type systems during a wet plug condition when there is conductive fouling at the gap of the spark plug.
In a distributor type system, the coil energy is discharged suddenly with a step change of the rotor gap of the distributor. The step change causes the spark to produce a high amplitude, same polarity voltage spike which usually occurs very close to the zero crossing of the first pulse. NAND 6 and NAND 7 will allow the spike to pass only when the spike occurs very shortly after the zero crossing of the first pulse and is the same polarity as the first pulse. The Pulse Width Detector is able to detect this spark spike as a result.
The F.P.N. signal is applied to the F.P.N. delay circuit comprising C7, R14 and D3. The F.P.N. signal will go low and block any signal from T3. The combination of C7 and R14 will hold the NAND 6 low beyond the sampling time of the second pulse.
Equally, the F.P.P. delay circuit comprising C8, R13 and D4 has the same values as F.P.N. delay circuit and operates in the same manner. The output of either NAND 6 or NAND 7 is inputted into NAND 8 which accepts either signal to indicate and provide a common spark pulse.
The Lagging Edge Trigger circuit comprising C9, R17 and D5 is a passive differentiator to supply a negative trigger pulse to the next gate at the falling or lagging edge of the common spark signal, the output of NAND 8.
The monostable spark timer B, is triggered at the zero crossing of the first pulse. Monostable timer B is set to approximately 2 microseconds and provides the sampling time for the second pulse.
Spark gate NOR 3 supplies a set of pulse to the spark latch provided that the lagging edge of the second pulse falls within the sampling time of the spark monostable timer B.
The spark latch, NOR 7 and NOR 8 is also arranged as an RS latch. The output of NOR 7 drives the spark transistor T6.
Voltage to the circuit is provided by batteries B1 which are connected in series with a function switch.
The values of the components are as follows:
______________________________________Component Value Component Value______________________________________R1 220 k C1 0.01 microR2 470 k C2 0.01 microR3 470 k C3 0.001 microR4 220 k C4 0.001 microR5 1 k C5 0.001 microR6 1 k C6 0.001 microR7 1 k C7 0.001 microR8 10 k C8 0.001 microR9 10 k C9 0.001 microR10 1 k C10 0.001 microR11 100 C11 0.01 microR12 100 C12 100 picoR13 10 k C13 0.01 microR14 10 k C14 0.01 microR15 1 k C15 10.000 microR16 10 k C16 10 picoR17 1 k C17 10 picoR18 10 kR19 470 kR20 10 kR21 10 k D1 SignalR22 27 D2 SignalR23 10 k D3 SignalR24 27 D4 Signal D5 Signal (1N914 or equiv.)T1 2N2907 or equiv. NOR MC74HC02ANT2 2N2222 or equiv. NAND MC74HC00ANT3 2N2907 or equiv. TIMER MC74HC4234ANT4 2N2222 or equiv. (or equiv.)T5 2N2222 or equiv.T6 2N2222 or equiv.______________________________________
Optionally, bypass capacitors of approximately 0.001 micro may be added to most of the CMOS inputs to shield the circuitry from stray electromagnetic emissions.
In operation, the combination of LED 20 and 22 flashing will indicate the spark condition which can be used to diagnose the problem in the ignition system. The possible combination for the LEDS are as follows:
______________________________________HIGH TENSION SPARK COMMENT______________________________________Not Flashing Not Flashing no high tension voltageFlashing Not Flashing high tension voltage, but no sparkFlashing Flashing spark plug firing normallyIntermittent Not Flashing intermittent highFlashing tension voltage, no sparkFlashing Intermittent intermittent spark FlashingIntermittent Intermittent intermittent highFlashing Flashing tension voltage causing intermittent spark______________________________________
As illustrated in FIG. 2, the invention is provided with a memory mode. The memory will cause the LEDS to remain steady until the Clear Memory button is pushed. This will permit a single operator to install the probe onto an ignition wire and then crank the ignition from the driver's seat. After turning the engine over, the operator can then go to the device and see the response obtained. This eliminates the need for a second person to be present to either turn the ignition or watch the response of the device.
The diagnostic results can be further simplified by providing a chart on the body of the device to indicate the possible results. The basic trouble-shooting chart would be as follows:
______________________________________High Tension Spark Result______________________________________0 0 total ignition failure reset button ignition switch connections1 0 wet or fouled plug lay off the choke/hold choke open1 1 ignition system normal/lack of fuel keep choke on until engine starts______________________________________
The basic model of a spark ignition analyzer has been described in detail. However, it is apparent that other optional features can be added to enhance the capabilities of the analyzer.
With reference to FIG. 6, a spark malfunction mode can be added to the circuit. Switch 39 is inserted between R23 and NOR 7 to switch between a spark mode and a spark malfunction mode. The spark malfunction mode is used to observe intermittent spark misses. Rather than trying to observe a missed flash of the spark LED 22, LED 22 is caused to flash if a spark is missed in the spark malfunction mode.
Between switch 39 and NOR 3, the spark malfunction mode is inserted, as illustrated in FIG. 6. NOR 10 and NOR 11 form a spark malfunction latch. The input of NOR 10 is a reset which allows the circuit to have a memory mode. The values of components of the malfunction mode are as follows:
______________________________________Component Value Component Value______________________________________R25 10 k C18 0.001 microR26 2.2 k C19 0.001 micro C20 0.001 microD6 Signal (1N914 or equiv.)D7 Signal (1N914 or equiv.)NOR 9/10/11 MC74HC02AN______________________________________
NOR 9 provides the spark malfunction pulse. NOR 3 produces a spark set pulse in the manner described above. NOR 9 will not produce a pulse should a spark pulse be present. QB is the non-inverting output of the Zero Crossing Sample Timer (monostable timer B) which fed to one input of NOR 9. QB is conditioned by a passive differentiator (C20/R26/D7) which enables the operation of NOR 9 at the end of QB and for only a short time period. A spark pulse should have been received by NOR 9 during such period of time. If one is not received a spark malfunction pulse is generated causing spark LED 22 to flash.
The spark pulse is never longer than the period of time of QB. The spark pulse must be extended to overlap with the delayed sample time of QB. C18/C19/R25/D6 achieve the desired overlap effect.
A coil polarity circuit could also be included. Such a coil polarity circuit is illustrated in FIG. 7. LED 40 indicates a negative coil and LED 42 indicates a positive coil. This circuit is useful to ensure that the primary coil connections have been properly wired to produce maximum output voltage. The values of components of the coil polarity circuit are as follows:
______________________________________Component Value Component Value______________________________________R27 10 k T7 2N2222 or equiv.R28 10 k T8 2N2222 or equiv.NOR 12 MC74HC02AN______________________________________
The High Tension pulse is fed into the input of NOR 12. The output of NOR 12 is fed to both reset inputs of the polarity latches. NAND 9 and NAND 10 form the negative polarity latch and NAND 11 and NAND 12 form the positive polarity latch. A set pulse from the F.P.N will trigger the negative latch and a set pulse from the F.P.P. will trigger the positive latch.
The spark analyzer of the present invention could also be used with a booster lead as illustrated in FIG. 8. The lead is a length of ignition wire 48 having a male receptacle 46 at one end and a female receptacle 50 at the opposite end. Receptacle 46 is provided with a slot 52 to allow compression of the end to be inserted into the boot end of a standard ignition wire 44. Similarly, receptacle 50 has a slot 54 to permit expansion of the end to fit over the end of a spark plug. Receptacle 50 is not provided with an insulation cover allowing electrical contact with the spark plug.
As is apparent, the booster lead is installed onto an engine by removing the ignition wire 44 from the spark plug and connecting the booster lead in series with the ignition wire and the spark plug.
The booster lead has a low potential gap adding a gap to the existing spark plug. Greater voltage will be required for the voltage to bridge both gaps. If a no spark or an intermittent spark condition persists when testing with the booster lead, then there is a high tension problem in the engine. If the spark condition improves, then the spark plug is fouled.
The spark analyzer of the present invention could still further be used with a short circuit stick as illustrated in FIG. 9. At one end of the stick is an alligator clamp 56, electrically connected to a lead 60, electrically connected to a probe 64. The handle 62 insulates the user from electrical contact.
In use, the stick is clamped to a suitable ground. The user successively shorts out each spark plug while monitoring the degree of change in engine speed. By shorting out each spark plug, weak cylinders can be identified by comparing the absence of the cylinder with the absence of other cylinders, since a weak cylinder will not affect the engine speed as significantly as a properly firing cylinder. If booster leads as illustrated in FIG. 8 are installed on the engine, shorting the spark plug can be accomplished quite easily since the receptacle 50 is open for electrical contact to short out the spark plug.
It is apparent to one skilled in the art that the invention could also be used to diagnose most other ignition problems such as point dwell, coil power, high resistance connections, leaky wires or distributor carbon tracking.
It will be obvious to those skilled in the art that various modifications and changes can be made to the device without departing from the spirit and scope of this invention. Accordingly, all such modifications and changes as fall within the scope of the appended claims are intended to be part of this invention.
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|U.S. Classification||324/379, 73/114.62, 324/399, 324/392|
|Sep 13, 1996||FPAY||Fee payment|
Year of fee payment: 4
|Nov 13, 1996||AS||Assignment|
Owner name: MARKETING DIRECT LTD., CANADA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HANNAH, KENNETH H.;REEL/FRAME:008222/0244
Effective date: 19961008
|Oct 10, 2000||REMI||Maintenance fee reminder mailed|
|Mar 15, 2001||FPAY||Fee payment|
Year of fee payment: 8
|Mar 15, 2001||SULP||Surcharge for late payment|
Year of fee payment: 7
|Sep 15, 2004||FPAY||Fee payment|
Year of fee payment: 12


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