This Inner Loop Header: Depth=1\n\ts_clause 0x3\n\tscratch_store_b8 v0, v1, off\n\tscratch_store_b8 v0, v1, off offset:1\n\tscratch_store_b8 v0, v1, off offset:2\n\tscratch_store_b8 v0, v1, off offset:3\n\tv_add_nc_u32_e32 v0, 4, v0\n\ts_add_u32 s0, s0, 4\n\ts_addc_u32 s1, s1, 0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_cmp_lg_u64 s[0:1], 0\n\ts_cbranch_scc1 .LBB8_1\n; %bb.2:\n\tv_dual_mov_b32 v0, 4 :: v_dual_mov_b32 v1, 0xff\n\ts_movk_i32 s0, 0xfd50\n\ts_mov_b32 s1, -1\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_nc_u32_e32 v0, 0x558, v0\n.LBB8_3: ; =>This Inner Loop Header: Depth=1\n\ts_clause 0x3\n\tscratch_store_b8 v0, v1, off\n\tscratch_store_b8 v0, v1, off offset:1\n\tscratch_store_b8 v0, v1, off offset:2\n\tscratch_store_b8 v0, v1, off offset:3\n\tv_add_nc_u32_e32 v0, 4, v0\n\ts_add_u32 s0, s0, 4\n\ts_addc_u32 s1, s1, 0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_cmp_lg_u64 s[0:1], 0\n\ts_cbranch_scc1 .LBB8_3\n; %bb.4:\n\tv_dual_mov_b32 v0, 4 :: v_dual_mov_b32 v1, 0xab\n\tv_mov_b32_e32 v2, 0xaa\n\ts_mov_b32 s0, 0\n\ts_clause 0x1\n\tscratch_store_b32 off, v1, off offset:2052\n\tscratch_store_b32 off, v2, off offset:1368\n\tv_add_nc_u32_e32 v42, 0x808, v0\n.LBB8_5: ; =>This Inner Loop Header: Depth=1\n\tscratch_load_b32 v0, off, off offset:2740\n\tv_mov_b32_e32 v1, s0\n\ts_add_i32 s0, s0, 1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_cmpk_lg_i32 s0, 0xaa\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v0, v0, 2, v42\n\tscratch_store_b32 v0, v1, off\n\tscratch_load_b32 v0, off, off offset:2740\n\ts_waitcnt vmcnt(0)\n\tv_add_nc_u32_e32 v0, 1, v0\n\tscratch_store_b32 off, v0, off offset:2740\n\ts_cbranch_scc1 .LBB8_5\n; %bb.6:\n\tscratch_load_b32 v0, off, off offset:2752\n\ts_load_b64 s[2:3], s[22:23], 0x58\n\tv_mbcnt_lo_u32_b32 v23, -1, 0\n\ts_mov_b32 s0, exec_lo\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u32_e32 0, v0\n\ts_xor_b32 s16, exec_lo, s0\n\ts_cbranch_execz .LBB8_596\n; %bb.7:\n\tv_mov_b32_e32 v4, v23\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v4\n\tv_cmp_eq_u32_e64 s0, s0, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_13\n; %bb.8:\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s4, exec_lo\n\ts_waitcnt lgkmcnt(0)\n\tglobal_load_b64 v[8:9], v0, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[2:3] offset:40\n\tglobal_load_b64 v[5:6], v0, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v2, v2, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v3, v1, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v3, v2\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, v5, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo\n\tglobal_load_b64 v[6:7], v[1:2], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[6:7], v[8:9]\n\ts_cbranch_execz .LBB8_12\n; %bb.9:\n\ts_mov_b32 s5, 0\n\t.p2align\t6\n.LBB8_10: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[2:3] offset:40\n\tglobal_load_b64 v[10:11], v0, s[2:3]\n\tv_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v7, v2, v9\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]\n\tv_mov_b32_e32 v1, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]\n\tv_mov_b32_e32 v6, v2\n\tglobal_load_b64 v[6:7], v[5:6], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]\n\ts_or_b32 s5, vcc_lo, s5\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s5\n\ts_cbranch_execnz .LBB8_10\n; %bb.11:\n\ts_or_b32 exec_lo, exec_lo, s5\n.LBB8_12:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s4\n.LBB8_13:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v5, 0\n\tv_readfirstlane_b32 s4, v6\n\tv_readfirstlane_b32 s5, v7\n\ts_mov_b32 s8, exec_lo\n\ts_waitcnt lgkmcnt(0)\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v5, s[2:3] offset:40\n\tglobal_load_b128 v[0:3], v5, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s6, v8\n\tv_readfirstlane_b32 s7, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[6:7], s[4:5], s[6:7]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_15\n; %bb.14:\n\tv_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0\n\ts_mul_i32 s8, s7, 24\n\ts_mul_hi_u32 s9, s6, 24\n\tv_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1\n\ts_add_i32 s9, s9, s8\n\ts_mul_i32 s8, s6, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v10, vcc_lo, v0, s8\n\tv_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo\n\tglobal_store_b128 v[10:11], v[6:9], off offset:8\n.LBB8_15:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[8:9], s[6:7], 12\n\tv_lshlrev_b64 v[4:5], 6, v[4:5]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v2, vcc_lo, v2, s8\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo\n\tv_mov_b32_e32 v3, 0\n\ts_mov_b32 s8, 0\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_add_co_u32 v6, vcc_lo, v2, v4\n\tv_mov_b32_e32 v2, 33\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v4, v3\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8\n\tv_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10\n\tv_mov_b32_e32 v11, s11\n\ts_clause 0x3\n\tglobal_store_b128 v[6:7], v[2:5], off\n\tglobal_store_b128 v[6:7], v[8:11], off offset:16\n\tglobal_store_b128 v[6:7], v[8:11], off offset:32\n\tglobal_store_b128 v[6:7], v[8:11], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_23\n; %bb.16:\n\tv_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4\n\tv_mov_b32_e32 v12, s5\n\ts_clause 0x1\n\tglobal_load_b64 v[13:14], v10, s[2:3] offset:32 glc\n\tglobal_load_b64 v[2:3], v10, s[2:3] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s8, v2\n\tv_readfirstlane_b32 s9, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[8:9], s[8:9], s[4:5]\n\ts_mul_i32 s9, s9, 24\n\ts_mul_hi_u32 s10, s8, 24\n\ts_mul_i32 s8, s8, 24\n\ts_add_i32 s10, s10, s9\n\tv_add_co_u32 v8, vcc_lo, v0, s8\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo\n\ts_mov_b32 s8, exec_lo\n\tglobal_store_b64 v[8:9], v[13:14], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[13:14]\n\ts_cbranch_execz .LBB8_19\n; %bb.17:\n\ts_mov_b32 s9, 0\n.LBB8_18: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5\n\ts_sleep 1\n\tglobal_store_b64 v[8:9], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s9, vcc_lo, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s9\n\ts_cbranch_execnz .LBB8_18\n.LBB8_19:\n\ts_or_b32 exec_lo, exec_lo, s8\n\tv_mov_b32_e32 v2, 0\n\ts_mov_b32 s9, exec_lo\n\ts_mov_b32 s8, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s9, 0\n\tglobal_load_b64 v[2:3], v2, s[2:3] offset:16\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_21\n; %bb.20:\n\ts_bcnt1_i32_b32 s9, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_21:\n\ts_or_b32 exec_lo, exec_lo, s8\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_23\n; %bb.22:\n\tglobal_load_b32 v2, v[2:3], off offset:24\n\tv_mov_b32_e32 v3, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s8, v2\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_and_b32 m0, s8, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_23:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s7, 24\n\ts_mul_hi_u32 s7, s6, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s7, s7, s1\n\ts_mul_i32 s1, s6, 24\n\tv_add_co_u32 v0, vcc_lo, v0, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_27\n\t.p2align\t6\n.LBB8_24: ; in Loop: Header=BB8_27 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_26\n; %bb.25: ; in Loop: Header=BB8_27 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_27\n\ts_branch .LBB8_29\n\t.p2align\t6\n.LBB8_26:\n\ts_branch .LBB8_29\n.LBB8_27: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_24\n; %bb.28: ; in Loop: Header=BB8_27 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_24\n.LBB8_29:\n\tglobal_load_b64 v[20:21], v[6:7], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_33\n; %bb.30:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[2:3] offset:40\n\tglobal_load_b64 v[7:8], v6, s[2:3] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s4\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_33\n; %bb.31:\n\ts_mov_b32 s0, 0\n.LBB8_32: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_32\n.LBB8_33:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_getpc_b64 s[4:5]\n\ts_add_u32 s4, s4, .str.1@rel32@lo+4\n\ts_addc_u32 s5, s5, .str.1@rel32@hi+12\n\ts_mov_b32 s0, -1\n\ts_cmp_lg_u64 s[4:5], 0\n\ts_cbranch_scc0 .LBB8_112\n; %bb.34:\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v1, v21 :: v_dual_and_b32 v0, -3, v20\n\tv_mov_b32_e32 v25, 0\n\ts_mov_b64 s[6:7], 31\n\ts_branch .LBB8_36\n.LBB8_35: ; in Loop: Header=BB8_36 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_sub_u32 s6, s6, s8\n\ts_subb_u32 s7, s7, s9\n\ts_add_u32 s4, s4, s8\n\ts_addc_u32 s5, s5, s9\n\ts_cmp_lg_u64 s[6:7], 0\n\ts_cbranch_scc0 .LBB8_111\n.LBB8_36: ; =>This Loop Header: Depth=1\n ; Child Loop BB8_39 Depth 2\n ; Child Loop BB8_46 Depth 2\n ; Child Loop BB8_53 Depth 2\n ; Child Loop BB8_60 Depth 2\n ; Child Loop BB8_67 Depth 2\n ; Child Loop BB8_74 Depth 2\n ; Child Loop BB8_81 Depth 2\n ; Child Loop BB8_88 Depth 2\n ; Child Loop BB8_96 Depth 2\n ; Child Loop BB8_105 Depth 2\n ; Child Loop BB8_110 Depth 2\n\tv_cmp_lt_u64_e64 s0, s[6:7], 56\n ; implicit-def: $sgpr15\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b32 s0, s0, exec_lo\n\ts_cselect_b32 s8, s6, 56\n\ts_cselect_b32 s9, s7, 0\n\ts_cmp_gt_u32 s8, 7\n\ts_mov_b32 s0, -1\n\ts_cbranch_scc1 .LBB8_41\n; %bb.37: ; in Loop: Header=BB8_36 Depth=1\n\tv_mov_b32_e32 v2, 0\n\tv_mov_b32_e32 v3, 0\n\ts_cmp_eq_u32 s8, 0\n\ts_cbranch_scc1 .LBB8_40\n; %bb.38: ; in Loop: Header=BB8_36 Depth=1\n\ts_lshl_b64 s[0:1], s[8:9], 3\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], s[4:5]\n.LBB8_39: ; Parent Loop BB8_36 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v4, v25, s[12:13]\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[4:5], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_add_u32 s12, s12, 1\n\ts_addc_u32 s13, s13, 0\n\ts_cmp_lg_u32 s0, s10\n\tv_or_b32_e32 v2, v4, v2\n\tv_or_b32_e32 v3, v5, v3\n\ts_cbranch_scc1 .LBB8_39\n.LBB8_40: ; in Loop: Header=BB8_36 Depth=1\n\ts_mov_b32 s0, 0\n\ts_mov_b32 s15, 0\n.LBB8_41: ; in Loop: Header=BB8_36 Depth=1\n\ts_and_not1_b32 vcc_lo, exec_lo, s0\n\ts_mov_b64 s[0:1], s[4:5]\n\ts_cbranch_vccnz .LBB8_43\n; %bb.42: ; in Loop: Header=BB8_36 Depth=1\n\tglobal_load_b64 v[2:3], v25, s[4:5]\n\ts_add_i32 s15, s8, -8\n\ts_add_u32 s0, s4, 8\n\ts_addc_u32 s1, s5, 0\n.LBB8_43: ; in Loop: Header=BB8_36 Depth=1\n\ts_cmp_gt_u32 s15, 7\n\ts_cbranch_scc1 .LBB8_48\n; %bb.44: ; in Loop: Header=BB8_36 Depth=1\n\tv_mov_b32_e32 v4, 0\n\tv_mov_b32_e32 v5, 0\n\ts_cmp_eq_u32 s15, 0\n\ts_cbranch_scc1 .LBB8_47\n; %bb.45: ; in Loop: Header=BB8_36 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_46: ; Parent Loop BB8_36 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s18, s0, s12\n\ts_addc_u32 s19, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v6, v25, s[18:19]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[6:7], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s15, s12\n\tv_or_b32_e32 v4, v6, v4\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v5, v7, v5\n\ts_cbranch_scc1 .LBB8_46\n.LBB8_47: ; in Loop: Header=BB8_36 Depth=1\n\ts_mov_b32 s14, 0\n\ts_cbranch_execz .LBB8_49\n\ts_branch .LBB8_50\n.LBB8_48: ; in Loop: Header=BB8_36 Depth=1\n ; implicit-def: $vgpr4_vgpr5\n ; implicit-def: $sgpr14\n.LBB8_49: ; in Loop: Header=BB8_36 Depth=1\n\tglobal_load_b64 v[4:5], v25, s[0:1]\n\ts_add_i32 s14, s15, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_50: ; in Loop: Header=BB8_36 Depth=1\n\ts_cmp_gt_u32 s14, 7\n\ts_cbranch_scc1 .LBB8_55\n; %bb.51: ; in Loop: Header=BB8_36 Depth=1\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\ts_cmp_eq_u32 s14, 0\n\ts_cbranch_scc1 .LBB8_54\n; %bb.52: ; in Loop: Header=BB8_36 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_53: ; Parent Loop BB8_36 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s18, s0, s12\n\ts_addc_u32 s19, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v8, v25, s[18:19]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v8\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[8:9], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s14, s12\n\tv_or_b32_e32 v6, v8, v6\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v7, v9, v7\n\ts_cbranch_scc1 .LBB8_53\n.LBB8_54: ; in Loop: Header=BB8_36 Depth=1\n\ts_mov_b32 s15, 0\n\ts_cbranch_execz .LBB8_56\n\ts_branch .LBB8_57\n.LBB8_55: ; in Loop: Header=BB8_36 Depth=1\n ; implicit-def: $sgpr15\n.LBB8_56: ; in Loop: Header=BB8_36 Depth=1\n\tglobal_load_b64 v[6:7], v25, s[0:1]\n\ts_add_i32 s15, s14, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_57: ; in Loop: Header=BB8_36 Depth=1\n\ts_cmp_gt_u32 s15, 7\n\ts_cbranch_scc1 .LBB8_62\n; %bb.58: ; in Loop: Header=BB8_36 Depth=1\n\tv_mov_b32_e32 v8, 0\n\tv_mov_b32_e32 v9, 0\n\ts_cmp_eq_u32 s15, 0\n\ts_cbranch_scc1 .LBB8_61\n; %bb.59: ; in Loop: Header=BB8_36 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_60: ; Parent Loop BB8_36 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s18, s0, s12\n\ts_addc_u32 s19, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v10, v25, s[18:19]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v10\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[10:11], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s15, s12\n\tv_or_b32_e32 v8, v10, v8\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v9, v11, v9\n\ts_cbranch_scc1 .LBB8_60\n.LBB8_61: ; in Loop: Header=BB8_36 Depth=1\n\ts_mov_b32 s14, 0\n\ts_cbranch_execz .LBB8_63\n\ts_branch .LBB8_64\n.LBB8_62: ; in Loop: Header=BB8_36 Depth=1\n ; implicit-def: $vgpr8_vgpr9\n ; implicit-def: $sgpr14\n.LBB8_63: ; in Loop: Header=BB8_36 Depth=1\n\tglobal_load_b64 v[8:9], v25, s[0:1]\n\ts_add_i32 s14, s15, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_64: ; in Loop: Header=BB8_36 Depth=1\n\ts_cmp_gt_u32 s14, 7\n\ts_cbranch_scc1 .LBB8_69\n; %bb.65: ; in Loop: Header=BB8_36 Depth=1\n\tv_mov_b32_e32 v10, 0\n\tv_mov_b32_e32 v11, 0\n\ts_cmp_eq_u32 s14, 0\n\ts_cbranch_scc1 .LBB8_68\n; %bb.66: ; in Loop: Header=BB8_36 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_67: ; Parent Loop BB8_36 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s18, s0, s12\n\ts_addc_u32 s19, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v12, v25, s[18:19]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v12\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[12:13], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s14, s12\n\tv_or_b32_e32 v10, v12, v10\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v11, v13, v11\n\ts_cbranch_scc1 .LBB8_67\n.LBB8_68: ; in Loop: Header=BB8_36 Depth=1\n\ts_mov_b32 s15, 0\n\ts_cbranch_execz .LBB8_70\n\ts_branch .LBB8_71\n.LBB8_69: ; in Loop: Header=BB8_36 Depth=1\n ; implicit-def: $sgpr15\n.LBB8_70: ; in Loop: Header=BB8_36 Depth=1\n\tglobal_load_b64 v[10:11], v25, s[0:1]\n\ts_add_i32 s15, s14, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_71: ; in Loop: Header=BB8_36 Depth=1\n\ts_cmp_gt_u32 s15, 7\n\ts_cbranch_scc1 .LBB8_76\n; %bb.72: ; in Loop: Header=BB8_36 Depth=1\n\tv_mov_b32_e32 v12, 0\n\tv_mov_b32_e32 v13, 0\n\ts_cmp_eq_u32 s15, 0\n\ts_cbranch_scc1 .LBB8_75\n; %bb.73: ; in Loop: Header=BB8_36 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_74: ; Parent Loop BB8_36 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s18, s0, s12\n\ts_addc_u32 s19, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v14, v25, s[18:19]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v14\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[14:15], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s15, s12\n\tv_or_b32_e32 v12, v14, v12\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v13, v15, v13\n\ts_cbranch_scc1 .LBB8_74\n.LBB8_75: ; in Loop: Header=BB8_36 Depth=1\n\ts_mov_b32 s14, 0\n\ts_cbranch_execz .LBB8_77\n\ts_branch .LBB8_78\n.LBB8_76: ; in Loop: Header=BB8_36 Depth=1\n ; implicit-def: $vgpr12_vgpr13\n ; implicit-def: $sgpr14\n.LBB8_77: ; in Loop: Header=BB8_36 Depth=1\n\tglobal_load_b64 v[12:13], v25, s[0:1]\n\ts_add_i32 s14, s15, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_78: ; in Loop: Header=BB8_36 Depth=1\n\ts_cmp_gt_u32 s14, 7\n\ts_cbranch_scc1 .LBB8_83\n; %bb.79: ; in Loop: Header=BB8_36 Depth=1\n\tv_mov_b32_e32 v14, 0\n\tv_mov_b32_e32 v15, 0\n\ts_cmp_eq_u32 s14, 0\n\ts_cbranch_scc1 .LBB8_82\n; %bb.80: ; in Loop: Header=BB8_36 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], s[0:1]\n.LBB8_81: ; Parent Loop BB8_36 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v16, v25, s[12:13]\n\ts_add_i32 s14, s14, -1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v16\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[16:17], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_add_u32 s12, s12, 1\n\ts_addc_u32 s13, s13, 0\n\ts_cmp_lg_u32 s14, 0\n\tv_or_b32_e32 v14, v16, v14\n\tv_or_b32_e32 v15, v17, v15\n\ts_cbranch_scc1 .LBB8_81\n.LBB8_82: ; in Loop: Header=BB8_36 Depth=1\n\ts_cbranch_execz .LBB8_84\n\ts_branch .LBB8_85\n.LBB8_83: ; in Loop: Header=BB8_36 Depth=1\n.LBB8_84: ; in Loop: Header=BB8_36 Depth=1\n\tglobal_load_b64 v[14:15], v25, s[0:1]\n.LBB8_85: ; in Loop: Header=BB8_36 Depth=1\n\tv_mov_b32_e32 v24, v23\n\tv_mov_b32_e32 v26, 0\n\tv_mov_b32_e32 v27, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v24\n\tv_cmp_eq_u32_e64 s0, s0, v24\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_91\n; %bb.86: ; in Loop: Header=BB8_36 Depth=1\n\tglobal_load_b64 v[18:19], v25, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[16:17], v25, s[2:3] offset:40\n\tglobal_load_b64 v[26:27], v25, s[2:3]\n\ts_mov_b32 s10, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v17, v17, v19\n\tv_and_b32_e32 v16, v16, v18\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v17, v17, 24\n\tv_mul_hi_u32 v22, v16, 24\n\tv_mul_lo_u32 v16, v16, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v17, v22, v17\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v16, vcc_lo, v26, v16\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo\n\tglobal_load_b64 v[16:17], v[16:17], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[26:27], v[18:19]\n\ts_cbranch_execz .LBB8_90\n; %bb.87: ; in Loop: Header=BB8_36 Depth=1\n\ts_mov_b32 s11, 0\n\t.p2align\t6\n.LBB8_88: ; Parent Loop BB8_36 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[16:17], v25, s[2:3] offset:40\n\tglobal_load_b64 v[28:29], v25, s[2:3]\n\tv_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v16, v16, v18\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19\n\tv_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]\n\tglobal_load_b64 v[16:17], v[26:27], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]\n\ts_or_b32 s11, vcc_lo, s11\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s11\n\ts_cbranch_execnz .LBB8_88\n; %bb.89: ; in Loop: Header=BB8_36 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s11\n.LBB8_90: ; in Loop: Header=BB8_36 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s10\n.LBB8_91: ; in Loop: Header=BB8_36 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_clause 0x1\n\tglobal_load_b64 v[28:29], v25, s[2:3] offset:40\n\tglobal_load_b128 v[16:19], v25, s[2:3]\n\tv_readfirstlane_b32 s10, v26\n\tv_readfirstlane_b32 s11, v27\n\ts_mov_b32 s14, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s12, v28\n\tv_readfirstlane_b32 s13, v29\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[12:13], s[10:11], s[12:13]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_93\n; %bb.92: ; in Loop: Header=BB8_36 Depth=1\n\tv_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0\n\ts_mul_i32 s14, s13, 24\n\ts_mul_hi_u32 s15, s12, 24\n\tv_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1\n\ts_add_i32 s15, s15, s14\n\ts_mul_i32 s14, s12, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v30, vcc_lo, v16, s14\n\tv_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo\n\tglobal_store_b128 v[30:31], v[26:29], off offset:8\n.LBB8_93: ; in Loop: Header=BB8_36 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_cmp_gt_u64_e64 vcc_lo, s[6:7], 56\n\tv_or_b32_e32 v22, 2, v0\n\ts_lshl_b64 s[14:15], s[12:13], 12\n\tv_lshlrev_b64 v[26:27], 6, v[24:25]\n\ts_lshl_b32 s1, s8, 2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_i32 s1, s1, 28\n\tv_cndmask_b32_e32 v0, v22, v0, vcc_lo\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v18, vcc_lo, v18, s14\n\tv_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo\n\ts_and_b32 s1, s1, 0x1e0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v18, vcc_lo, v18, v26\n\tv_and_or_b32 v0, v0, 0xffffff1f, s1\n\tv_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo\n\ts_clause 0x3\n\tglobal_store_b128 v[18:19], v[0:3], off\n\tglobal_store_b128 v[18:19], v[4:7], off offset:16\n\tglobal_store_b128 v[18:19], v[8:11], off offset:32\n\tglobal_store_b128 v[18:19], v[12:15], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_101\n; %bb.94: ; in Loop: Header=BB8_36 Depth=1\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v25, s[2:3] offset:32 glc\n\tglobal_load_b64 v[0:1], v25, s[2:3] offset:40\n\tv_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s14, v0\n\tv_readfirstlane_b32 s15, v1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[14:15], s[14:15], s[10:11]\n\ts_mul_i32 s15, s15, 24\n\ts_mul_hi_u32 s17, s14, 24\n\ts_mul_i32 s14, s14, 24\n\ts_add_i32 s17, s17, s15\n\tv_add_co_u32 v4, vcc_lo, v16, s14\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s17, v17, vcc_lo\n\ts_mov_b32 s14, exec_lo\n\tglobal_store_b64 v[4:5], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[2:3], v[8:9]\n\ts_cbranch_execz .LBB8_97\n; %bb.95: ; in Loop: Header=BB8_36 Depth=1\n\ts_mov_b32 s15, 0\n.LBB8_96: ; Parent Loop BB8_36 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]\n\tv_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0\n\ts_or_b32 s15, vcc_lo, s15\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s15\n\ts_cbranch_execnz .LBB8_96\n.LBB8_97: ; in Loop: Header=BB8_36 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s14\n\tglobal_load_b64 v[0:1], v25, s[2:3] offset:16\n\ts_mov_b32 s15, exec_lo\n\ts_mov_b32 s14, exec_lo\n\tv_mbcnt_lo_u32_b32 v2, s15, 0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_eq_u32_e32 0, v2\n\ts_cbranch_execz .LBB8_99\n; %bb.98: ; in Loop: Header=BB8_36 Depth=1\n\ts_bcnt1_i32_b32 s15, s15\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off offset:8\n.LBB8_99: ; in Loop: Header=BB8_36 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s14\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\ts_cbranch_vccnz .LBB8_101\n; %bb.100: ; in Loop: Header=BB8_36 Depth=1\n\tglobal_load_b32 v24, v[0:1], off offset:24\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s14, v24\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[2:3], v[24:25], off\n\ts_and_b32 m0, s14, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_101: ; in Loop: Header=BB8_36 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s13, 24\n\ts_mul_hi_u32 s13, s12, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s13, s13, s1\n\ts_mul_i32 s1, s12, 24\n\tv_add_co_u32 v0, vcc_lo, v16, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_105\n\t.p2align\t6\n.LBB8_102: ; in Loop: Header=BB8_105 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_104\n; %bb.103: ; in Loop: Header=BB8_105 Depth=2\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_105\n\ts_branch .LBB8_107\n\t.p2align\t6\n.LBB8_104: ; in Loop: Header=BB8_36 Depth=1\n\ts_branch .LBB8_107\n.LBB8_105: ; Parent Loop BB8_36 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_102\n; %bb.106: ; in Loop: Header=BB8_105 Depth=2\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_102\n.LBB8_107: ; in Loop: Header=BB8_36 Depth=1\n\tglobal_load_b64 v[0:1], v[18:19], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_35\n; %bb.108: ; in Loop: Header=BB8_36 Depth=1\n\ts_clause 0x2\n\tglobal_load_b64 v[4:5], v25, s[2:3] offset:40\n\tglobal_load_b64 v[8:9], v25, s[2:3] offset:24 glc\n\tglobal_load_b64 v[6:7], v25, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v10, vcc_lo, v4, 1\n\tv_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, v10, s10\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\tv_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10\n\tv_and_b32_e32 v5, v3, v5\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v4, v2, v4\n\tv_mul_hi_u32 v10, v4, 24\n\tv_mul_lo_u32 v4, v4, 24\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_add_co_u32 v6, vcc_lo, v6, v4\n\tv_mov_b32_e32 v4, v8\n\tv_mul_lo_u32 v5, v5, 24\n\tv_add_nc_u32_e32 v5, v10, v5\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v5, v9\n\tglobal_store_b64 v[6:7], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_35\n; %bb.109: ; in Loop: Header=BB8_36 Depth=1\n\ts_mov_b32 s0, 0\n.LBB8_110: ; Parent Loop BB8_36 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]\n\tv_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_110\n\ts_branch .LBB8_35\n.LBB8_111:\n\ts_mov_b32 s0, 0\n.LBB8_112:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_b32 vcc_lo, exec_lo, s0\n\ts_cbranch_vccz .LBB8_140\n; %bb.113:\n\tv_mov_b32_e32 v4, v23\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v4\n\tv_cmp_eq_u32_e64 s0, s0, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_119\n; %bb.114:\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s4, exec_lo\n\tglobal_load_b64 v[8:9], v0, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[2:3] offset:40\n\tglobal_load_b64 v[5:6], v0, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v2, v2, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v3, v1, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v3, v2\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, v5, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo\n\tglobal_load_b64 v[6:7], v[1:2], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[6:7], v[8:9]\n\ts_cbranch_execz .LBB8_118\n; %bb.115:\n\ts_mov_b32 s5, 0\n\t.p2align\t6\n.LBB8_116: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[2:3] offset:40\n\tglobal_load_b64 v[10:11], v0, s[2:3]\n\tv_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v7, v2, v9\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]\n\tv_mov_b32_e32 v1, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]\n\tv_mov_b32_e32 v6, v2\n\tglobal_load_b64 v[6:7], v[5:6], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]\n\ts_or_b32 s5, vcc_lo, s5\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s5\n\ts_cbranch_execnz .LBB8_116\n; %bb.117:\n\ts_or_b32 exec_lo, exec_lo, s5\n.LBB8_118:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s4\n.LBB8_119:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v5, 0\n\tv_readfirstlane_b32 s4, v6\n\tv_readfirstlane_b32 s5, v7\n\ts_mov_b32 s8, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v5, s[2:3] offset:40\n\tglobal_load_b128 v[0:3], v5, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s6, v8\n\tv_readfirstlane_b32 s7, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[6:7], s[4:5], s[6:7]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_121\n; %bb.120:\n\tv_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0\n\ts_mul_i32 s8, s7, 24\n\ts_mul_hi_u32 s9, s6, 24\n\tv_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1\n\ts_add_i32 s9, s9, s8\n\ts_mul_i32 s8, s6, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v10, vcc_lo, v0, s8\n\tv_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo\n\tglobal_store_b128 v[10:11], v[6:9], off offset:8\n.LBB8_121:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[8:9], s[6:7], 12\n\tv_and_or_b32 v20, v20, 0xffffff1d, 34\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v7, vcc_lo, v2, s8\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s9, v3, vcc_lo\n\tv_lshlrev_b64 v[2:3], 6, v[4:5]\n\ts_mov_b32 s8, 0\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_add_co_u32 v8, vcc_lo, v7, v2\n\tv_mov_b32_e32 v6, 0\n\tv_add_co_ci_u32_e32 v9, vcc_lo, v9, v3, vcc_lo\n\tv_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11\n\tv_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10\n\ts_delay_alu instid0(VALU_DEP_4)\n\tv_mov_b32_e32 v7, v6\n\ts_clause 0x4\n\tglobal_store_b64 v[8:9], v[20:21], off\n\tglobal_store_b128 v[8:9], v[2:5], off offset:8\n\tglobal_store_b128 v[8:9], v[2:5], off offset:24\n\tglobal_store_b128 v[8:9], v[2:5], off offset:40\n\tglobal_store_b64 v[8:9], v[6:7], off offset:56\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_129\n; %bb.122:\n\tv_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4\n\tv_mov_b32_e32 v10, s5\n\ts_clause 0x1\n\tglobal_load_b64 v[11:12], v8, s[2:3] offset:32 glc\n\tglobal_load_b64 v[2:3], v8, s[2:3] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s8, v2\n\tv_readfirstlane_b32 s9, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[8:9], s[8:9], s[4:5]\n\ts_mul_i32 s9, s9, 24\n\ts_mul_hi_u32 s10, s8, 24\n\ts_mul_i32 s8, s8, 24\n\ts_add_i32 s10, s10, s9\n\tv_add_co_u32 v6, vcc_lo, v0, s8\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo\n\ts_mov_b32 s8, exec_lo\n\tglobal_store_b64 v[6:7], v[11:12], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[11:12]\n\ts_cbranch_execz .LBB8_125\n; %bb.123:\n\ts_mov_b32 s9, 0\n.LBB8_124: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s9, vcc_lo, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s9\n\ts_cbranch_execnz .LBB8_124\n.LBB8_125:\n\ts_or_b32 exec_lo, exec_lo, s8\n\tv_mov_b32_e32 v2, 0\n\ts_mov_b32 s9, exec_lo\n\ts_mov_b32 s8, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s9, 0\n\tglobal_load_b64 v[2:3], v2, s[2:3] offset:16\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_127\n; %bb.126:\n\ts_bcnt1_i32_b32 s9, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_127:\n\ts_or_b32 exec_lo, exec_lo, s8\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_129\n; %bb.128:\n\tglobal_load_b32 v2, v[2:3], off offset:24\n\tv_mov_b32_e32 v3, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s8, v2\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_and_b32 m0, s8, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_129:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s7, 24\n\ts_mul_hi_u32 s7, s6, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s7, s7, s1\n\ts_mul_i32 s1, s6, 24\n\tv_add_co_u32 v0, vcc_lo, v0, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_133\n\t.p2align\t6\n.LBB8_130: ; in Loop: Header=BB8_133 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_132\n; %bb.131: ; in Loop: Header=BB8_133 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_133\n\ts_branch .LBB8_135\n\t.p2align\t6\n.LBB8_132:\n\ts_branch .LBB8_135\n.LBB8_133: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_130\n; %bb.134: ; in Loop: Header=BB8_133 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_130\n.LBB8_135:\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_139\n; %bb.136:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[2:3] offset:40\n\tglobal_load_b64 v[7:8], v6, s[2:3] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s4\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_139\n; %bb.137:\n\ts_mov_b32 s0, 0\n.LBB8_138: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_138\n.LBB8_139:\n\ts_or_b32 exec_lo, exec_lo, s1\n.LBB8_140:\n\tscratch_load_b32 v2, off, off offset:2752\n\ts_waitcnt vmcnt(1)\n\tv_dual_mov_b32 v0, v23 :: v_dual_mov_b32 v7, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_readfirstlane_b32 s0, v0\n\tv_mov_b32_e32 v8, 0\n\tv_cmp_eq_u32_e64 s0, s0, v0\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_146\n; %bb.141:\n\tv_mov_b32_e32 v1, 0\n\ts_mov_b32 s4, exec_lo\n\tglobal_load_b64 v[5:6], v1, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[3:4], v1, s[2:3] offset:40\n\tglobal_load_b64 v[7:8], v1, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v4, v4, v6\n\tv_and_b32_e32 v3, v3, v5\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v4, v4, 24\n\tv_mul_hi_u32 v9, v3, 24\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v4, v9, v4\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v3, vcc_lo, v7, v3\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo\n\tglobal_load_b64 v[3:4], v[3:4], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[7:8], v1, v[3:6], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[7:8], v[5:6]\n\ts_cbranch_execz .LBB8_145\n; %bb.142:\n\ts_mov_b32 s5, 0\n\t.p2align\t6\n.LBB8_143: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[3:4], v1, s[2:3] offset:40\n\tglobal_load_b64 v[9:10], v1, s[2:3]\n\tv_dual_mov_b32 v5, v7 :: v_dual_mov_b32 v6, v8\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v3, v3, v5\n\tv_and_b32_e32 v4, v4, v6\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[7:8], null, v3, 24, v[9:10]\n\tv_mov_b32_e32 v3, v8\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_mad_u64_u32 v[8:9], null, v4, 24, v[3:4]\n\tglobal_load_b64 v[3:4], v[7:8], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[7:8], v1, v[3:6], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[5:6]\n\ts_or_b32 s5, vcc_lo, s5\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s5\n\ts_cbranch_execnz .LBB8_143\n; %bb.144:\n\ts_or_b32 exec_lo, exec_lo, s5\n.LBB8_145:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s4\n.LBB8_146:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v1, 0\n\tv_readfirstlane_b32 s4, v7\n\tv_readfirstlane_b32 s5, v8\n\ts_mov_b32 s8, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[9:10], v1, s[2:3] offset:40\n\tglobal_load_b128 v[3:6], v1, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s6, v9\n\tv_readfirstlane_b32 s7, v10\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[6:7], s[4:5], s[6:7]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_148\n; %bb.147:\n\tv_dual_mov_b32 v7, s8 :: v_dual_mov_b32 v8, 0\n\ts_mul_i32 s8, s7, 24\n\ts_mul_hi_u32 s9, s6, 24\n\tv_dual_mov_b32 v9, 2 :: v_dual_mov_b32 v10, 1\n\ts_add_i32 s9, s9, s8\n\ts_mul_i32 s8, s6, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v11, vcc_lo, v3, s8\n\tv_add_co_ci_u32_e32 v12, vcc_lo, s9, v4, vcc_lo\n\tglobal_store_b128 v[11:12], v[7:10], off offset:8\n.LBB8_148:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[8:9], s[6:7], 12\n\tv_lshlrev_b64 v[0:1], 6, v[0:1]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v5, vcc_lo, v5, s8\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s9, v6, vcc_lo\n\tv_mov_b32_e32 v6, 0\n\ts_mov_b32 s8, 0\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_add_co_u32 v0, vcc_lo, v5, v0\n\tv_mov_b32_e32 v5, 33\n\ts_mov_b32 s11, s8\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\tv_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo\n\tv_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v12, s11\n\tv_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v11, s10\n\tv_dual_mov_b32 v10, s9 :: v_dual_mov_b32 v9, s8\n\ts_clause 0x3\n\tglobal_store_b128 v[0:1], v[5:8], off\n\tglobal_store_b128 v[0:1], v[9:12], off offset:16\n\tglobal_store_b128 v[0:1], v[9:12], off offset:32\n\tglobal_store_b128 v[0:1], v[9:12], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_156\n; %bb.149:\n\tv_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, s4\n\tv_mov_b32_e32 v13, s5\n\ts_clause 0x1\n\tglobal_load_b64 v[14:15], v11, s[2:3] offset:32 glc\n\tglobal_load_b64 v[5:6], v11, s[2:3] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s8, v5\n\tv_readfirstlane_b32 s9, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[8:9], s[8:9], s[4:5]\n\ts_mul_i32 s9, s9, 24\n\ts_mul_hi_u32 s10, s8, 24\n\ts_mul_i32 s8, s8, 24\n\ts_add_i32 s10, s10, s9\n\tv_add_co_u32 v9, vcc_lo, v3, s8\n\tv_add_co_ci_u32_e32 v10, vcc_lo, s10, v4, vcc_lo\n\ts_mov_b32 s8, exec_lo\n\tglobal_store_b64 v[9:10], v[14:15], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v11, v[12:15], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[7:8], v[14:15]\n\ts_cbranch_execz .LBB8_152\n; %bb.150:\n\ts_mov_b32 s9, 0\n.LBB8_151: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v5, s4 :: v_dual_mov_b32 v6, s5\n\ts_sleep 1\n\tglobal_store_b64 v[9:10], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[5:6], v11, v[5:8], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[5:6], v[7:8]\n\tv_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5\n\ts_or_b32 s9, vcc_lo, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s9\n\ts_cbranch_execnz .LBB8_151\n.LBB8_152:\n\ts_or_b32 exec_lo, exec_lo, s8\n\tv_mov_b32_e32 v5, 0\n\ts_mov_b32 s9, exec_lo\n\ts_mov_b32 s8, exec_lo\n\tv_mbcnt_lo_u32_b32 v7, s9, 0\n\tglobal_load_b64 v[5:6], v5, s[2:3] offset:16\n\tv_cmpx_eq_u32_e32 0, v7\n\ts_cbranch_execz .LBB8_154\n; %bb.153:\n\ts_bcnt1_i32_b32 s9, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v7, s9\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[5:6], v[7:8], off offset:8\n.LBB8_154:\n\ts_or_b32 exec_lo, exec_lo, s8\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[7:8], v[5:6], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]\n\ts_cbranch_vccnz .LBB8_156\n; %bb.155:\n\tglobal_load_b32 v5, v[5:6], off offset:24\n\tv_mov_b32_e32 v6, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s8, v5\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[7:8], v[5:6], off\n\ts_and_b32 m0, s8, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_156:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s7, 24\n\ts_mul_hi_u32 s7, s6, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s7, s7, s1\n\ts_mul_i32 s1, s6, 24\n\tv_add_co_u32 v3, vcc_lo, v3, s1\n\tv_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v3, vcc_lo, v3, 20\n\tv_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo\n\ts_branch .LBB8_160\n\t.p2align\t6\n.LBB8_157: ; in Loop: Header=BB8_160 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v5\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_159\n; %bb.158: ; in Loop: Header=BB8_160 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_160\n\ts_branch .LBB8_162\n\t.p2align\t6\n.LBB8_159:\n\ts_branch .LBB8_162\n.LBB8_160: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v5, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_157\n; %bb.161: ; in Loop: Header=BB8_160 Depth=1\n\tglobal_load_b32 v5, v[3:4], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v5, 1, v5\n\ts_branch .LBB8_157\n.LBB8_162:\n\tglobal_load_b64 v[24:25], v[0:1], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_166\n; %bb.163:\n\tv_mov_b32_e32 v7, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[0:1], v7, s[2:3] offset:40\n\tglobal_load_b64 v[8:9], v7, s[2:3] offset:24 glc\n\tglobal_load_b64 v[5:6], v7, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v10, vcc_lo, v0, 1\n\tv_add_co_ci_u32_e32 v11, vcc_lo, 0, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v3, vcc_lo, v10, s4\n\tv_add_co_ci_u32_e32 v4, vcc_lo, s5, v11, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]\n\tv_dual_cndmask_b32 v4, v4, v11 :: v_dual_cndmask_b32 v3, v3, v10\n\tv_and_b32_e32 v1, v4, v1\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v0, v3, v0\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v10, v0, 24\n\tv_mul_lo_u32 v0, v0, 24\n\tv_add_nc_u32_e32 v1, v10, v1\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v0, vcc_lo, v5, v0\n\tv_mov_b32_e32 v5, v8\n\tv_add_co_ci_u32_e32 v1, vcc_lo, v6, v1, vcc_lo\n\tv_mov_b32_e32 v6, v9\n\tglobal_store_b64 v[0:1], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[5:6], v7, v[3:6], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[5:6], v[8:9]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_166\n; %bb.164:\n\ts_mov_b32 s0, 0\n.LBB8_165: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[0:1], v[5:6], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[8:9], v7, v[3:6], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[8:9], v[5:6]\n\tv_dual_mov_b32 v5, v8 :: v_dual_mov_b32 v6, v9\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_165\n.LBB8_166:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_getpc_b64 s[4:5]\n\ts_add_u32 s4, s4, .str.2@rel32@lo+4\n\ts_addc_u32 s5, s5, .str.2@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_cmp_lg_u64 s[4:5], 0\n\ts_cbranch_scc0 .LBB8_244\n; %bb.167:\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v27, 0 :: v_dual_and_b32 v26, 2, v24\n\tv_and_b32_e32 v0, -3, v24\n\ts_mov_b64 s[6:7], 17\n\tv_mov_b32_e32 v1, v25\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_dual_mov_b32 v29, v27 :: v_dual_mov_b32 v28, v26\n\ts_branch .LBB8_169\n.LBB8_168: ; in Loop: Header=BB8_169 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_sub_u32 s6, s6, s8\n\ts_subb_u32 s7, s7, s9\n\ts_add_u32 s4, s4, s8\n\ts_addc_u32 s5, s5, s9\n\ts_cmp_lg_u64 s[6:7], 0\n\ts_cbranch_scc0 .LBB8_245\n.LBB8_169: ; =>This Loop Header: Depth=1\n ; Child Loop BB8_172 Depth 2\n ; Child Loop BB8_179 Depth 2\n ; Child Loop BB8_186 Depth 2\n ; Child Loop BB8_193 Depth 2\n ; Child Loop BB8_200 Depth 2\n ; Child Loop BB8_207 Depth 2\n ; Child Loop BB8_214 Depth 2\n ; Child Loop BB8_221 Depth 2\n ; Child Loop BB8_229 Depth 2\n ; Child Loop BB8_238 Depth 2\n ; Child Loop BB8_243 Depth 2\n\tv_cmp_lt_u64_e64 s0, s[6:7], 56\n ; implicit-def: $vgpr5_vgpr6\n ; implicit-def: $sgpr15\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b32 s0, s0, exec_lo\n\ts_cselect_b32 s8, s6, 56\n\ts_cselect_b32 s9, s7, 0\n\ts_cmp_gt_u32 s8, 7\n\ts_mov_b32 s0, -1\n\ts_cbranch_scc1 .LBB8_174\n; %bb.170: ; in Loop: Header=BB8_169 Depth=1\n\tv_mov_b32_e32 v5, 0\n\tv_mov_b32_e32 v6, 0\n\ts_cmp_eq_u32 s8, 0\n\ts_cbranch_scc1 .LBB8_173\n; %bb.171: ; in Loop: Header=BB8_169 Depth=1\n\ts_lshl_b64 s[0:1], s[8:9], 3\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], s[4:5]\n.LBB8_172: ; Parent Loop BB8_169 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v3, v27, s[12:13]\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v26, 0xffff, v3\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[3:4], s10, v[26:27]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_add_u32 s12, s12, 1\n\ts_addc_u32 s13, s13, 0\n\ts_cmp_lg_u32 s0, s10\n\tv_or_b32_e32 v5, v3, v5\n\tv_or_b32_e32 v6, v4, v6\n\ts_cbranch_scc1 .LBB8_172\n.LBB8_173: ; in Loop: Header=BB8_169 Depth=1\n\ts_mov_b32 s0, 0\n\ts_mov_b32 s15, 0\n.LBB8_174: ; in Loop: Header=BB8_169 Depth=1\n\ts_and_not1_b32 vcc_lo, exec_lo, s0\n\ts_mov_b64 s[0:1], s[4:5]\n\ts_cbranch_vccnz .LBB8_176\n; %bb.175: ; in Loop: Header=BB8_169 Depth=1\n\tglobal_load_b64 v[5:6], v27, s[4:5]\n\ts_add_i32 s15, s8, -8\n\ts_add_u32 s0, s4, 8\n\ts_addc_u32 s1, s5, 0\n.LBB8_176: ; in Loop: Header=BB8_169 Depth=1\n\ts_cmp_gt_u32 s15, 7\n\ts_cbranch_scc1 .LBB8_181\n; %bb.177: ; in Loop: Header=BB8_169 Depth=1\n\tv_mov_b32_e32 v7, 0\n\tv_mov_b32_e32 v8, 0\n\ts_cmp_eq_u32 s15, 0\n\ts_cbranch_scc1 .LBB8_180\n; %bb.178: ; in Loop: Header=BB8_169 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_179: ; Parent Loop BB8_169 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s18, s0, s12\n\ts_addc_u32 s19, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v3, v27, s[18:19]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v26, 0xffff, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[3:4], s10, v[26:27]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s15, s12\n\tv_or_b32_e32 v7, v3, v7\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v8, v4, v8\n\ts_cbranch_scc1 .LBB8_179\n.LBB8_180: ; in Loop: Header=BB8_169 Depth=1\n\ts_mov_b32 s14, 0\n\ts_cbranch_execz .LBB8_182\n\ts_branch .LBB8_183\n.LBB8_181: ; in Loop: Header=BB8_169 Depth=1\n ; implicit-def: $vgpr7_vgpr8\n ; implicit-def: $sgpr14\n.LBB8_182: ; in Loop: Header=BB8_169 Depth=1\n\tglobal_load_b64 v[7:8], v27, s[0:1]\n\ts_add_i32 s14, s15, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_183: ; in Loop: Header=BB8_169 Depth=1\n\ts_cmp_gt_u32 s14, 7\n\ts_cbranch_scc1 .LBB8_188\n; %bb.184: ; in Loop: Header=BB8_169 Depth=1\n\tv_mov_b32_e32 v9, 0\n\tv_mov_b32_e32 v10, 0\n\ts_cmp_eq_u32 s14, 0\n\ts_cbranch_scc1 .LBB8_187\n; %bb.185: ; in Loop: Header=BB8_169 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_186: ; Parent Loop BB8_169 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s18, s0, s12\n\ts_addc_u32 s19, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v3, v27, s[18:19]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v26, 0xffff, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[3:4], s10, v[26:27]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s14, s12\n\tv_or_b32_e32 v9, v3, v9\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v10, v4, v10\n\ts_cbranch_scc1 .LBB8_186\n.LBB8_187: ; in Loop: Header=BB8_169 Depth=1\n\ts_mov_b32 s15, 0\n\ts_cbranch_execz .LBB8_189\n\ts_branch .LBB8_190\n.LBB8_188: ; in Loop: Header=BB8_169 Depth=1\n ; implicit-def: $sgpr15\n.LBB8_189: ; in Loop: Header=BB8_169 Depth=1\n\tglobal_load_b64 v[9:10], v27, s[0:1]\n\ts_add_i32 s15, s14, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_190: ; in Loop: Header=BB8_169 Depth=1\n\ts_cmp_gt_u32 s15, 7\n\ts_cbranch_scc1 .LBB8_195\n; %bb.191: ; in Loop: Header=BB8_169 Depth=1\n\tv_mov_b32_e32 v11, 0\n\tv_mov_b32_e32 v12, 0\n\ts_cmp_eq_u32 s15, 0\n\ts_cbranch_scc1 .LBB8_194\n; %bb.192: ; in Loop: Header=BB8_169 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_193: ; Parent Loop BB8_169 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s18, s0, s12\n\ts_addc_u32 s19, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v3, v27, s[18:19]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v26, 0xffff, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[3:4], s10, v[26:27]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s15, s12\n\tv_or_b32_e32 v11, v3, v11\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v12, v4, v12\n\ts_cbranch_scc1 .LBB8_193\n.LBB8_194: ; in Loop: Header=BB8_169 Depth=1\n\ts_mov_b32 s14, 0\n\ts_cbranch_execz .LBB8_196\n\ts_branch .LBB8_197\n.LBB8_195: ; in Loop: Header=BB8_169 Depth=1\n ; implicit-def: $vgpr11_vgpr12\n ; implicit-def: $sgpr14\n.LBB8_196: ; in Loop: Header=BB8_169 Depth=1\n\tglobal_load_b64 v[11:12], v27, s[0:1]\n\ts_add_i32 s14, s15, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_197: ; in Loop: Header=BB8_169 Depth=1\n\ts_cmp_gt_u32 s14, 7\n\ts_cbranch_scc1 .LBB8_202\n; %bb.198: ; in Loop: Header=BB8_169 Depth=1\n\tv_mov_b32_e32 v13, 0\n\tv_mov_b32_e32 v14, 0\n\ts_cmp_eq_u32 s14, 0\n\ts_cbranch_scc1 .LBB8_201\n; %bb.199: ; in Loop: Header=BB8_169 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_200: ; Parent Loop BB8_169 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s18, s0, s12\n\ts_addc_u32 s19, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v3, v27, s[18:19]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v26, 0xffff, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[3:4], s10, v[26:27]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s14, s12\n\tv_or_b32_e32 v13, v3, v13\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v14, v4, v14\n\ts_cbranch_scc1 .LBB8_200\n.LBB8_201: ; in Loop: Header=BB8_169 Depth=1\n\ts_mov_b32 s15, 0\n\ts_cbranch_execz .LBB8_203\n\ts_branch .LBB8_204\n.LBB8_202: ; in Loop: Header=BB8_169 Depth=1\n ; implicit-def: $sgpr15\n.LBB8_203: ; in Loop: Header=BB8_169 Depth=1\n\tglobal_load_b64 v[13:14], v27, s[0:1]\n\ts_add_i32 s15, s14, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_204: ; in Loop: Header=BB8_169 Depth=1\n\ts_cmp_gt_u32 s15, 7\n\ts_cbranch_scc1 .LBB8_209\n; %bb.205: ; in Loop: Header=BB8_169 Depth=1\n\tv_mov_b32_e32 v15, 0\n\tv_mov_b32_e32 v16, 0\n\ts_cmp_eq_u32 s15, 0\n\ts_cbranch_scc1 .LBB8_208\n; %bb.206: ; in Loop: Header=BB8_169 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_207: ; Parent Loop BB8_169 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s18, s0, s12\n\ts_addc_u32 s19, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v3, v27, s[18:19]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v26, 0xffff, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[3:4], s10, v[26:27]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s15, s12\n\tv_or_b32_e32 v15, v3, v15\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v16, v4, v16\n\ts_cbranch_scc1 .LBB8_207\n.LBB8_208: ; in Loop: Header=BB8_169 Depth=1\n\ts_mov_b32 s14, 0\n\ts_cbranch_execz .LBB8_210\n\ts_branch .LBB8_211\n.LBB8_209: ; in Loop: Header=BB8_169 Depth=1\n ; implicit-def: $vgpr15_vgpr16\n ; implicit-def: $sgpr14\n.LBB8_210: ; in Loop: Header=BB8_169 Depth=1\n\tglobal_load_b64 v[15:16], v27, s[0:1]\n\ts_add_i32 s14, s15, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_211: ; in Loop: Header=BB8_169 Depth=1\n\ts_cmp_gt_u32 s14, 7\n\ts_cbranch_scc1 .LBB8_216\n; %bb.212: ; in Loop: Header=BB8_169 Depth=1\n\tv_mov_b32_e32 v17, 0\n\tv_mov_b32_e32 v18, 0\n\ts_cmp_eq_u32 s14, 0\n\ts_cbranch_scc1 .LBB8_215\n; %bb.213: ; in Loop: Header=BB8_169 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], s[0:1]\n.LBB8_214: ; Parent Loop BB8_169 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v3, v27, s[12:13]\n\ts_add_i32 s14, s14, -1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v26, 0xffff, v3\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[3:4], s10, v[26:27]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_add_u32 s12, s12, 1\n\ts_addc_u32 s13, s13, 0\n\ts_cmp_lg_u32 s14, 0\n\tv_or_b32_e32 v17, v3, v17\n\tv_or_b32_e32 v18, v4, v18\n\ts_cbranch_scc1 .LBB8_214\n.LBB8_215: ; in Loop: Header=BB8_169 Depth=1\n\ts_cbranch_execz .LBB8_217\n\ts_branch .LBB8_218\n.LBB8_216: ; in Loop: Header=BB8_169 Depth=1\n.LBB8_217: ; in Loop: Header=BB8_169 Depth=1\n\tglobal_load_b64 v[17:18], v27, s[0:1]\n.LBB8_218: ; in Loop: Header=BB8_169 Depth=1\n\tv_dual_mov_b32 v26, v23 :: v_dual_mov_b32 v3, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_readfirstlane_b32 s0, v26\n\tv_mov_b32_e32 v4, 0\n\tv_cmp_eq_u32_e64 s0, s0, v26\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_224\n; %bb.219: ; in Loop: Header=BB8_169 Depth=1\n\tglobal_load_b64 v[21:22], v27, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[3:4], v27, s[2:3] offset:40\n\tglobal_load_b64 v[19:20], v27, s[2:3]\n\ts_mov_b32 s10, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v4, v4, v22\n\tv_and_b32_e32 v3, v3, v21\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v4, v4, 24\n\tv_mul_hi_u32 v30, v3, 24\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v4, v30, v4\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v3, vcc_lo, v19, v3\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v4, vcc_lo, v20, v4, vcc_lo\n\tglobal_load_b64 v[19:20], v[3:4], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[3:4], v27, v[19:22], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[3:4], v[21:22]\n\ts_cbranch_execz .LBB8_223\n; %bb.220: ; in Loop: Header=BB8_169 Depth=1\n\ts_mov_b32 s11, 0\n\t.p2align\t6\n.LBB8_221: ; Parent Loop BB8_169 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[19:20], v27, s[2:3] offset:40\n\tglobal_load_b64 v[30:31], v27, s[2:3]\n\tv_dual_mov_b32 v22, v4 :: v_dual_mov_b32 v21, v3\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v19, v19, v21\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[3:4], null, v19, 24, v[30:31]\n\tv_and_b32_e32 v30, v20, v22\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[19:20], null, v30, 24, v[4:5]\n\tv_mov_b32_e32 v4, v19\n\tglobal_load_b64 v[19:20], v[3:4], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[3:4], v27, v[19:22], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[3:4], v[21:22]\n\ts_or_b32 s11, vcc_lo, s11\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s11\n\ts_cbranch_execnz .LBB8_221\n; %bb.222: ; in Loop: Header=BB8_169 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s11\n.LBB8_223: ; in Loop: Header=BB8_169 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s10\n.LBB8_224: ; in Loop: Header=BB8_169 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_clause 0x1\n\tglobal_load_b64 v[30:31], v27, s[2:3] offset:40\n\tglobal_load_b128 v[19:22], v27, s[2:3]\n\tv_readfirstlane_b32 s10, v3\n\tv_readfirstlane_b32 s11, v4\n\ts_mov_b32 s14, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s12, v30\n\tv_readfirstlane_b32 s13, v31\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[12:13], s[10:11], s[12:13]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_226\n; %bb.225: ; in Loop: Header=BB8_169 Depth=1\n\tv_dual_mov_b32 v30, s14 :: v_dual_mov_b32 v31, 0\n\ts_mul_i32 s14, s13, 24\n\ts_mul_hi_u32 s15, s12, 24\n\tv_dual_mov_b32 v32, 2 :: v_dual_mov_b32 v33, 1\n\ts_add_i32 s15, s15, s14\n\ts_mul_i32 s14, s12, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v3, vcc_lo, v19, s14\n\tv_add_co_ci_u32_e32 v4, vcc_lo, s15, v20, vcc_lo\n\tglobal_store_b128 v[3:4], v[30:33], off offset:8\n.LBB8_226: ; in Loop: Header=BB8_169 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_cmp_gt_u64_e64 vcc_lo, s[6:7], 56\n\tv_or_b32_e32 v3, v1, v29\n\tv_or_b32_e32 v30, v0, v28\n\ts_lshl_b64 s[14:15], s[12:13], 12\n\ts_lshl_b32 s1, s8, 2\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\ts_add_i32 s1, s1, 28\n\tv_dual_cndmask_b32 v4, v3, v1 :: v_dual_cndmask_b32 v3, v30, v0\n\tv_lshlrev_b64 v[0:1], 6, v[26:27]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v21, vcc_lo, v21, s14\n\tv_add_co_ci_u32_e32 v22, vcc_lo, s15, v22, vcc_lo\n\ts_and_b32 s1, s1, 0x1e0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v0, vcc_lo, v21, v0\n\tv_and_or_b32 v3, v3, 0xffffff1f, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, v22, v1, vcc_lo\n\ts_clause 0x3\n\tglobal_store_b128 v[0:1], v[3:6], off\n\tglobal_store_b128 v[0:1], v[7:10], off offset:16\n\tglobal_store_b128 v[0:1], v[11:14], off offset:32\n\tglobal_store_b128 v[0:1], v[15:18], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_234\n; %bb.227: ; in Loop: Header=BB8_169 Depth=1\n\ts_clause 0x1\n\tglobal_load_b64 v[11:12], v27, s[2:3] offset:32 glc\n\tglobal_load_b64 v[3:4], v27, s[2:3] offset:40\n\tv_dual_mov_b32 v9, s10 :: v_dual_mov_b32 v10, s11\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s14, v3\n\tv_readfirstlane_b32 s15, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[14:15], s[14:15], s[10:11]\n\ts_mul_i32 s15, s15, 24\n\ts_mul_hi_u32 s17, s14, 24\n\ts_mul_i32 s14, s14, 24\n\ts_add_i32 s17, s17, s15\n\tv_add_co_u32 v7, vcc_lo, v19, s14\n\tv_add_co_ci_u32_e32 v8, vcc_lo, s17, v20, vcc_lo\n\ts_mov_b32 s14, exec_lo\n\tglobal_store_b64 v[7:8], v[11:12], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[5:6], v27, v[9:12], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[5:6], v[11:12]\n\ts_cbranch_execz .LBB8_230\n; %bb.228: ; in Loop: Header=BB8_169 Depth=1\n\ts_mov_b32 s15, 0\n.LBB8_229: ; Parent Loop BB8_169 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_dual_mov_b32 v3, s10 :: v_dual_mov_b32 v4, s11\n\ts_sleep 1\n\tglobal_store_b64 v[7:8], v[5:6], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[3:4], v27, v[3:6], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]\n\tv_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3\n\ts_or_b32 s15, vcc_lo, s15\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s15\n\ts_cbranch_execnz .LBB8_229\n.LBB8_230: ; in Loop: Header=BB8_169 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s14\n\tglobal_load_b64 v[3:4], v27, s[2:3] offset:16\n\ts_mov_b32 s15, exec_lo\n\ts_mov_b32 s14, exec_lo\n\tv_mbcnt_lo_u32_b32 v5, s15, 0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_eq_u32_e32 0, v5\n\ts_cbranch_execz .LBB8_232\n; %bb.231: ; in Loop: Header=BB8_169 Depth=1\n\ts_bcnt1_i32_b32 s15, s15\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v5, s15\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[3:4], v[5:6], off offset:8\n.LBB8_232: ; in Loop: Header=BB8_169 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s14\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[5:6], v[3:4], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]\n\ts_cbranch_vccnz .LBB8_234\n; %bb.233: ; in Loop: Header=BB8_169 Depth=1\n\tglobal_load_b32 v26, v[3:4], off offset:24\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s14, v26\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[5:6], v[26:27], off\n\ts_and_b32 m0, s14, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_234: ; in Loop: Header=BB8_169 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s13, 24\n\ts_mul_hi_u32 s13, s12, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s13, s13, s1\n\ts_mul_i32 s1, s12, 24\n\tv_add_co_u32 v3, vcc_lo, v19, s1\n\tv_add_co_ci_u32_e32 v4, vcc_lo, s13, v20, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v3, vcc_lo, v3, 20\n\tv_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo\n\ts_branch .LBB8_238\n\t.p2align\t6\n.LBB8_235: ; in Loop: Header=BB8_238 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v5\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_237\n; %bb.236: ; in Loop: Header=BB8_238 Depth=2\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_238\n\ts_branch .LBB8_240\n\t.p2align\t6\n.LBB8_237: ; in Loop: Header=BB8_169 Depth=1\n\ts_branch .LBB8_240\n.LBB8_238: ; Parent Loop BB8_169 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_mov_b32_e32 v5, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_235\n; %bb.239: ; in Loop: Header=BB8_238 Depth=2\n\tglobal_load_b32 v5, v[3:4], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v5, 1, v5\n\ts_branch .LBB8_235\n.LBB8_240: ; in Loop: Header=BB8_169 Depth=1\n\tglobal_load_b64 v[0:1], v[0:1], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_168\n; %bb.241: ; in Loop: Header=BB8_169 Depth=1\n\ts_clause 0x2\n\tglobal_load_b64 v[5:6], v27, s[2:3] offset:40\n\tglobal_load_b64 v[9:10], v27, s[2:3] offset:24 glc\n\tglobal_load_b64 v[7:8], v27, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v11, vcc_lo, v5, 1\n\tv_add_co_ci_u32_e32 v12, vcc_lo, 0, v6, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v3, vcc_lo, v11, s10\n\tv_add_co_ci_u32_e32 v4, vcc_lo, s11, v12, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]\n\tv_dual_cndmask_b32 v4, v4, v12 :: v_dual_cndmask_b32 v3, v3, v11\n\tv_and_b32_e32 v6, v4, v6\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v5, v3, v5\n\tv_mul_hi_u32 v11, v5, 24\n\tv_mul_lo_u32 v5, v5, 24\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_add_co_u32 v7, vcc_lo, v7, v5\n\tv_mov_b32_e32 v5, v9\n\tv_mul_lo_u32 v6, v6, 24\n\tv_add_nc_u32_e32 v6, v11, v6\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_co_ci_u32_e32 v8, vcc_lo, v8, v6, vcc_lo\n\tv_mov_b32_e32 v6, v10\n\tglobal_store_b64 v[7:8], v[9:10], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[5:6], v27, v[3:6], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[5:6], v[9:10]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_168\n; %bb.242: ; in Loop: Header=BB8_169 Depth=1\n\ts_mov_b32 s0, 0\n.LBB8_243: ; Parent Loop BB8_169 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\tglobal_store_b64 v[7:8], v[5:6], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[9:10], v27, v[3:6], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[9:10], v[5:6]\n\tv_dual_mov_b32 v5, v9 :: v_dual_mov_b32 v6, v10\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_243\n\ts_branch .LBB8_168\n.LBB8_244:\n\ts_cbranch_execnz .LBB8_246\n\ts_branch .LBB8_273\n.LBB8_245:\n\ts_branch .LBB8_273\n.LBB8_246:\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v0, v23 :: v_dual_mov_b32 v7, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_readfirstlane_b32 s0, v0\n\tv_mov_b32_e32 v8, 0\n\tv_cmp_eq_u32_e64 s0, s0, v0\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_252\n; %bb.247:\n\tv_mov_b32_e32 v1, 0\n\ts_mov_b32 s4, exec_lo\n\tglobal_load_b64 v[5:6], v1, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[3:4], v1, s[2:3] offset:40\n\tglobal_load_b64 v[7:8], v1, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v4, v4, v6\n\tv_and_b32_e32 v3, v3, v5\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v4, v4, 24\n\tv_mul_hi_u32 v9, v3, 24\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v4, v9, v4\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v3, vcc_lo, v7, v3\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo\n\tglobal_load_b64 v[3:4], v[3:4], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[7:8], v1, v[3:6], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[7:8], v[5:6]\n\ts_cbranch_execz .LBB8_251\n; %bb.248:\n\ts_mov_b32 s5, 0\n\t.p2align\t6\n.LBB8_249: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[3:4], v1, s[2:3] offset:40\n\tglobal_load_b64 v[9:10], v1, s[2:3]\n\tv_dual_mov_b32 v5, v7 :: v_dual_mov_b32 v6, v8\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v3, v3, v5\n\tv_and_b32_e32 v4, v4, v6\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[7:8], null, v3, 24, v[9:10]\n\tv_mov_b32_e32 v3, v8\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_mad_u64_u32 v[8:9], null, v4, 24, v[3:4]\n\tglobal_load_b64 v[3:4], v[7:8], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[7:8], v1, v[3:6], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[5:6]\n\ts_or_b32 s5, vcc_lo, s5\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s5\n\ts_cbranch_execnz .LBB8_249\n; %bb.250:\n\ts_or_b32 exec_lo, exec_lo, s5\n.LBB8_251:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s4\n.LBB8_252:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v1, 0\n\tv_readfirstlane_b32 s4, v7\n\tv_readfirstlane_b32 s5, v8\n\ts_mov_b32 s8, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[9:10], v1, s[2:3] offset:40\n\tglobal_load_b128 v[3:6], v1, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s6, v9\n\tv_readfirstlane_b32 s7, v10\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[6:7], s[4:5], s[6:7]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_254\n; %bb.253:\n\tv_dual_mov_b32 v7, s8 :: v_dual_mov_b32 v8, 0\n\ts_mul_i32 s8, s7, 24\n\ts_mul_hi_u32 s9, s6, 24\n\tv_dual_mov_b32 v9, 2 :: v_dual_mov_b32 v10, 1\n\ts_add_i32 s9, s9, s8\n\ts_mul_i32 s8, s6, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v11, vcc_lo, v3, s8\n\tv_add_co_ci_u32_e32 v12, vcc_lo, s9, v4, vcc_lo\n\tglobal_store_b128 v[11:12], v[7:10], off offset:8\n.LBB8_254:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[8:9], s[6:7], 12\n\tv_lshlrev_b64 v[0:1], 6, v[0:1]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v5, vcc_lo, v5, s8\n\tv_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo\n\ts_mov_b32 s8, 0\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v5, v0\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_mov_b32_e32 v9, 0\n\tv_and_or_b32 v24, v24, 0xffffff1f, 32\n\tv_add_co_ci_u32_e32 v1, vcc_lo, v6, v1, vcc_lo\n\tv_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v8, s11\n\tv_dual_mov_b32 v6, s9 :: v_dual_mov_b32 v7, s10\n\tv_mov_b32_e32 v10, v9\n\ts_clause 0x4\n\tglobal_store_b64 v[0:1], v[24:25], off\n\tglobal_store_b128 v[0:1], v[5:8], off offset:8\n\tglobal_store_b128 v[0:1], v[5:8], off offset:24\n\tglobal_store_b128 v[0:1], v[5:8], off offset:40\n\tglobal_store_b64 v[0:1], v[9:10], off offset:56\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_262\n; %bb.255:\n\tv_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, s4\n\tv_mov_b32_e32 v13, s5\n\ts_clause 0x1\n\tglobal_load_b64 v[14:15], v11, s[2:3] offset:32 glc\n\tglobal_load_b64 v[5:6], v11, s[2:3] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s8, v5\n\tv_readfirstlane_b32 s9, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[8:9], s[8:9], s[4:5]\n\ts_mul_i32 s9, s9, 24\n\ts_mul_hi_u32 s10, s8, 24\n\ts_mul_i32 s8, s8, 24\n\ts_add_i32 s10, s10, s9\n\tv_add_co_u32 v9, vcc_lo, v3, s8\n\tv_add_co_ci_u32_e32 v10, vcc_lo, s10, v4, vcc_lo\n\ts_mov_b32 s8, exec_lo\n\tglobal_store_b64 v[9:10], v[14:15], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v11, v[12:15], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[7:8], v[14:15]\n\ts_cbranch_execz .LBB8_258\n; %bb.256:\n\ts_mov_b32 s9, 0\n.LBB8_257: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v5, s4 :: v_dual_mov_b32 v6, s5\n\ts_sleep 1\n\tglobal_store_b64 v[9:10], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[5:6], v11, v[5:8], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[5:6], v[7:8]\n\tv_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5\n\ts_or_b32 s9, vcc_lo, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s9\n\ts_cbranch_execnz .LBB8_257\n.LBB8_258:\n\ts_or_b32 exec_lo, exec_lo, s8\n\tv_mov_b32_e32 v5, 0\n\ts_mov_b32 s9, exec_lo\n\ts_mov_b32 s8, exec_lo\n\tv_mbcnt_lo_u32_b32 v7, s9, 0\n\tglobal_load_b64 v[5:6], v5, s[2:3] offset:16\n\tv_cmpx_eq_u32_e32 0, v7\n\ts_cbranch_execz .LBB8_260\n; %bb.259:\n\ts_bcnt1_i32_b32 s9, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v7, s9\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[5:6], v[7:8], off offset:8\n.LBB8_260:\n\ts_or_b32 exec_lo, exec_lo, s8\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[7:8], v[5:6], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]\n\ts_cbranch_vccnz .LBB8_262\n; %bb.261:\n\tglobal_load_b32 v5, v[5:6], off offset:24\n\tv_mov_b32_e32 v6, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s8, v5\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[7:8], v[5:6], off\n\ts_and_b32 m0, s8, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_262:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s7, 24\n\ts_mul_hi_u32 s7, s6, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s7, s7, s1\n\ts_mul_i32 s1, s6, 24\n\tv_add_co_u32 v3, vcc_lo, v3, s1\n\tv_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v3, vcc_lo, v3, 20\n\tv_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo\n\ts_branch .LBB8_266\n\t.p2align\t6\n.LBB8_263: ; in Loop: Header=BB8_266 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v5\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_265\n; %bb.264: ; in Loop: Header=BB8_266 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_266\n\ts_branch .LBB8_268\n\t.p2align\t6\n.LBB8_265:\n\ts_branch .LBB8_268\n.LBB8_266: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v5, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_263\n; %bb.267: ; in Loop: Header=BB8_266 Depth=1\n\tglobal_load_b32 v5, v[3:4], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v5, 1, v5\n\ts_branch .LBB8_263\n.LBB8_268:\n\tglobal_load_b64 v[0:1], v[0:1], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_272\n; %bb.269:\n\tv_mov_b32_e32 v9, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[5:6], v9, s[2:3] offset:40\n\tglobal_load_b64 v[10:11], v9, s[2:3] offset:24 glc\n\tglobal_load_b64 v[7:8], v9, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v12, vcc_lo, v5, 1\n\tv_add_co_ci_u32_e32 v13, vcc_lo, 0, v6, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v3, vcc_lo, v12, s4\n\tv_add_co_ci_u32_e32 v4, vcc_lo, s5, v13, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]\n\tv_dual_cndmask_b32 v4, v4, v13 :: v_dual_cndmask_b32 v3, v3, v12\n\tv_and_b32_e32 v6, v4, v6\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v5, v3, v5\n\tv_mul_lo_u32 v6, v6, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v12, v5, 24\n\tv_mul_lo_u32 v5, v5, 24\n\tv_add_nc_u32_e32 v6, v12, v6\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v7, vcc_lo, v7, v5\n\tv_mov_b32_e32 v5, v10\n\tv_add_co_ci_u32_e32 v8, vcc_lo, v8, v6, vcc_lo\n\tv_mov_b32_e32 v6, v11\n\tglobal_store_b64 v[7:8], v[10:11], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[5:6], v9, v[3:6], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[5:6], v[10:11]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_272\n; %bb.270:\n\ts_mov_b32 s0, 0\n.LBB8_271: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[7:8], v[5:6], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[10:11], v9, v[3:6], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[10:11], v[5:6]\n\tv_dual_mov_b32 v5, v10 :: v_dual_mov_b32 v6, v11\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_271\n.LBB8_272:\n\ts_or_b32 exec_lo, exec_lo, s1\n.LBB8_273:\n\tv_dual_mov_b32 v8, v23 :: v_dual_mov_b32 v9, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_readfirstlane_b32 s0, v8\n\tv_mov_b32_e32 v10, 0\n\tv_cmp_eq_u32_e64 s0, s0, v8\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_279\n; %bb.274:\n\tv_mov_b32_e32 v3, 0\n\ts_mov_b32 s4, exec_lo\n\tglobal_load_b64 v[6:7], v3, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[4:5], v3, s[2:3] offset:40\n\tglobal_load_b64 v[9:10], v3, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v4, v4, v6\n\tv_and_b32_e32 v5, v5, v7\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v11, v4, 24\n\tv_mul_lo_u32 v5, v5, 24\n\tv_mul_lo_u32 v4, v4, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v5, v11, v5\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v4, vcc_lo, v9, v4\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v10, v5, vcc_lo\n\tglobal_load_b64 v[4:5], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[9:10], v3, v[4:7], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[9:10], v[6:7]\n\ts_cbranch_execz .LBB8_278\n; %bb.275:\n\ts_mov_b32 s5, 0\n\t.p2align\t6\n.LBB8_276: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[4:5], v3, s[2:3] offset:40\n\tglobal_load_b64 v[11:12], v3, s[2:3]\n\tv_dual_mov_b32 v6, v9 :: v_dual_mov_b32 v7, v10\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v4, v4, v6\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[9:10], null, v4, 24, v[11:12]\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_dual_mov_b32 v4, v10 :: v_dual_and_b32 v5, v5, v7\n\tv_mad_u64_u32 v[10:11], null, v5, 24, v[4:5]\n\tglobal_load_b64 v[4:5], v[9:10], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[9:10], v3, v[4:7], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[9:10], v[6:7]\n\ts_or_b32 s5, vcc_lo, s5\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s5\n\ts_cbranch_execnz .LBB8_276\n; %bb.277:\n\ts_or_b32 exec_lo, exec_lo, s5\n.LBB8_278:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s4\n.LBB8_279:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v3, 0\n\tv_readfirstlane_b32 s4, v9\n\tv_readfirstlane_b32 s5, v10\n\ts_mov_b32 s8, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[11:12], v3, s[2:3] offset:40\n\tglobal_load_b128 v[4:7], v3, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s6, v11\n\tv_readfirstlane_b32 s7, v12\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[6:7], s[4:5], s[6:7]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_281\n; %bb.280:\n\tv_dual_mov_b32 v9, s8 :: v_dual_mov_b32 v10, 0\n\ts_mul_i32 s8, s7, 24\n\ts_mul_hi_u32 s9, s6, 24\n\tv_dual_mov_b32 v11, 2 :: v_dual_mov_b32 v12, 1\n\ts_add_i32 s9, s9, s8\n\ts_mul_i32 s8, s6, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v13, vcc_lo, v4, s8\n\tv_add_co_ci_u32_e32 v14, vcc_lo, s9, v5, vcc_lo\n\tglobal_store_b128 v[13:14], v[9:12], off offset:8\n.LBB8_281:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[10:11], s[6:7], 12\n\ts_mov_b32 s8, 0\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v6, vcc_lo, v6, s10\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_mov_b32_e32 v3, 0\n\tv_and_or_b32 v0, v0, 0xffffff1d, 34\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mov_b32_e32 v9, v3\n\tv_lshlrev_b64 v[8:9], 6, v[8:9]\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v10, vcc_lo, v6, v8\n\tv_add_co_ci_u32_e32 v11, vcc_lo, v7, v9, vcc_lo\n\tv_mov_b32_e32 v6, s8\n\tv_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v7, s9\n\tv_mov_b32_e32 v9, s11\n\ts_clause 0x3\n\tglobal_store_b128 v[10:11], v[0:3], off\n\tglobal_store_b128 v[10:11], v[6:9], off offset:16\n\tglobal_store_b128 v[10:11], v[6:9], off offset:32\n\tglobal_store_b128 v[10:11], v[6:9], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_289\n; %bb.282:\n\tv_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4\n\tv_mov_b32_e32 v10, s5\n\ts_clause 0x1\n\tglobal_load_b64 v[11:12], v8, s[2:3] offset:32 glc\n\tglobal_load_b64 v[0:1], v8, s[2:3] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s8, v0\n\tv_readfirstlane_b32 s9, v1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[8:9], s[8:9], s[4:5]\n\ts_mul_i32 s9, s9, 24\n\ts_mul_hi_u32 s10, s8, 24\n\ts_mul_i32 s8, s8, 24\n\ts_add_i32 s10, s10, s9\n\tv_add_co_u32 v6, vcc_lo, v4, s8\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s10, v5, vcc_lo\n\ts_mov_b32 s8, exec_lo\n\tglobal_store_b64 v[6:7], v[11:12], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[2:3], v[11:12]\n\ts_cbranch_execz .LBB8_285\n; %bb.283:\n\ts_mov_b32 s9, 0\n.LBB8_284: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]\n\tv_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0\n\ts_or_b32 s9, vcc_lo, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s9\n\ts_cbranch_execnz .LBB8_284\n.LBB8_285:\n\ts_or_b32 exec_lo, exec_lo, s8\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s9, exec_lo\n\ts_mov_b32 s8, exec_lo\n\tv_mbcnt_lo_u32_b32 v2, s9, 0\n\tglobal_load_b64 v[0:1], v0, s[2:3] offset:16\n\tv_cmpx_eq_u32_e32 0, v2\n\ts_cbranch_execz .LBB8_287\n; %bb.286:\n\ts_bcnt1_i32_b32 s9, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s9\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off offset:8\n.LBB8_287:\n\ts_or_b32 exec_lo, exec_lo, s8\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\ts_cbranch_vccnz .LBB8_289\n; %bb.288:\n\tglobal_load_b32 v0, v[0:1], off offset:24\n\tv_mov_b32_e32 v1, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s8, v0\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[2:3], v[0:1], off\n\ts_and_b32 m0, s8, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_289:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s7, 24\n\ts_mul_hi_u32 s7, s6, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s7, s7, s1\n\ts_mul_i32 s1, s6, 24\n\tv_add_co_u32 v0, vcc_lo, v4, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s7, v5, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_293\n\t.p2align\t6\n.LBB8_290: ; in Loop: Header=BB8_293 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_292\n; %bb.291: ; in Loop: Header=BB8_293 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_293\n\ts_branch .LBB8_295\n\t.p2align\t6\n.LBB8_292:\n\ts_branch .LBB8_295\n.LBB8_293: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_290\n; %bb.294: ; in Loop: Header=BB8_293 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_290\n.LBB8_295:\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_299\n; %bb.296:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[2:3] offset:40\n\tglobal_load_b64 v[7:8], v6, s[2:3] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s4\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_299\n; %bb.297:\n\ts_mov_b32 s0, 0\n.LBB8_298: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_298\n.LBB8_299:\n\ts_or_b32 exec_lo, exec_lo, s1\n\tscratch_load_b32 v0, off, off offset:2744\n\tv_mov_b32_e32 v22, 4\n\ts_mov_b32 s17, exec_lo\n\ts_waitcnt vmcnt(0)\n\tv_lshlrev_b32_e32 v0, 2, v0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add3_u32 v0, v22, v0, 0x558\n\tscratch_load_b32 v32, v0, off\n\tscratch_load_b32 v0, off, off offset:2748\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u32_e64 v32, v0\n\ts_cbranch_execz .LBB8_462\n; %bb.300:\n\tv_dual_mov_b32 v25, 0 :: v_dual_mov_b32 v0, 33\n\tv_mov_b32_e32 v1, 0\n\ts_mov_b32 s4, 0\n\ts_mov_b32 s18, 0\n\ts_branch .LBB8_302\n.LBB8_301: ; in Loop: Header=BB8_302 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_lshlrev_b32_e32 v2, 2, v32\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add3_u32 v2, v22, v2, 0x558\n\tscratch_load_b32 v32, v2, off\n\tscratch_load_b32 v2, off, off offset:2748\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e32 vcc_lo, v32, v2\n\ts_or_b32 s18, vcc_lo, s18\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s18\n\ts_cbranch_execz .LBB8_462\n.LBB8_302: ; =>This Loop Header: Depth=1\n ; Child Loop BB8_305 Depth 2\n ; Child Loop BB8_313 Depth 2\n ; Child Loop BB8_322 Depth 2\n ; Child Loop BB8_327 Depth 2\n ; Child Loop BB8_412 Depth 2\n ; Child Loop BB8_420 Depth 2\n ; Child Loop BB8_429 Depth 2\n ; Child Loop BB8_434 Depth 2\n ; Child Loop BB8_331 Depth 2\n ; Child Loop BB8_334 Depth 3\n ; Child Loop BB8_342 Depth 3\n ; Child Loop BB8_349 Depth 3\n ; Child Loop BB8_356 Depth 3\n ; Child Loop BB8_363 Depth 3\n ; Child Loop BB8_370 Depth 3\n ; Child Loop BB8_377 Depth 3\n ; Child Loop BB8_384 Depth 3\n ; Child Loop BB8_392 Depth 3\n ; Child Loop BB8_401 Depth 3\n ; Child Loop BB8_406 Depth 3\n ; Child Loop BB8_439 Depth 2\n ; Child Loop BB8_447 Depth 2\n ; Child Loop BB8_456 Depth 2\n ; Child Loop BB8_461 Depth 2\n\tv_lshl_add_u32 v2, v32, 2, 4\n\tv_mov_b32_e32 v24, v23\n\tscratch_load_b32 v33, v2, off\n\tv_mov_b32_e32 v2, 0\n\tv_mov_b32_e32 v3, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\tv_readfirstlane_b32 s0, v24\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u32_e64 s0, s0, v24\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_308\n; %bb.303: ; in Loop: Header=BB8_302 Depth=1\n\tglobal_load_b64 v[4:5], v25, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[2:3], v25, s[2:3] offset:40\n\tglobal_load_b64 v[6:7], v25, s[2:3]\n\ts_mov_b32 s5, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v3, v3, v5\n\tv_and_b32_e32 v2, v2, v4\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v3, v3, 24\n\tv_mul_hi_u32 v8, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v3, v8, v3\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v2, vcc_lo, v6, v2\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo\n\tglobal_load_b64 v[2:3], v[2:3], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[2:3], v25, v[2:5], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[2:3], v[4:5]\n\ts_cbranch_execz .LBB8_307\n; %bb.304: ; in Loop: Header=BB8_302 Depth=1\n\ts_mov_b32 s6, 0\n\t.p2align\t6\n.LBB8_305: ; Parent Loop BB8_302 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[6:7], v25, s[2:3] offset:40\n\tglobal_load_b64 v[8:9], v25, s[2:3]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v6, v6, v4\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[2:3], null, v6, 24, v[8:9]\n\tv_and_b32_e32 v8, v7, v5\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[6:7], null, v8, 24, v[3:4]\n\tv_mov_b32_e32 v3, v6\n\tglobal_load_b64 v[2:3], v[2:3], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[2:3], v25, v[2:5], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\ts_or_b32 s6, vcc_lo, s6\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s6\n\ts_cbranch_execnz .LBB8_305\n; %bb.306: ; in Loop: Header=BB8_302 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s6\n.LBB8_307: ; in Loop: Header=BB8_302 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s5\n.LBB8_308: ; in Loop: Header=BB8_302 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v25, s[2:3] offset:40\n\tglobal_load_b128 v[4:7], v25, s[2:3]\n\tv_readfirstlane_b32 s8, v2\n\tv_readfirstlane_b32 s9, v3\n\ts_mov_b32 s5, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s6, v8\n\tv_readfirstlane_b32 s7, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[10:11], s[8:9], s[6:7]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_310\n; %bb.309: ; in Loop: Header=BB8_302 Depth=1\n\tv_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v9, 0\n\ts_mul_i32 s5, s11, 24\n\ts_mul_hi_u32 s6, s10, 24\n\tv_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1\n\ts_add_i32 s6, s6, s5\n\ts_mul_i32 s5, s10, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v2, vcc_lo, v4, s5\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s6, v5, vcc_lo\n\tglobal_store_b128 v[2:3], v[8:11], off offset:8\n.LBB8_310: ; in Loop: Header=BB8_302 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[6:7], s[10:11], 12\n\tv_lshlrev_b64 v[2:3], 6, v[24:25]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v6, vcc_lo, v6, s6\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo\n\ts_mov_b32 s7, s4\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_u32 v10, vcc_lo, v6, v2\n\ts_mov_b32 s5, s4\n\ts_mov_b32 s6, s4\n\tv_add_co_ci_u32_e32 v11, vcc_lo, v7, v3, vcc_lo\n\tv_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v9, s7\n\tv_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v8, s6\n\tv_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4\n\ts_clause 0x3\n\tglobal_store_b128 v[10:11], v[0:3], off\n\tglobal_store_b128 v[10:11], v[6:9], off offset:16\n\tglobal_store_b128 v[10:11], v[6:9], off offset:32\n\tglobal_store_b128 v[10:11], v[6:9], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_318\n; %bb.311: ; in Loop: Header=BB8_302 Depth=1\n\ts_clause 0x1\n\tglobal_load_b64 v[14:15], v25, s[2:3] offset:32 glc\n\tglobal_load_b64 v[2:3], v25, s[2:3] offset:40\n\tv_dual_mov_b32 v12, s8 :: v_dual_mov_b32 v13, s9\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\tv_readfirstlane_b32 s7, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[6:7], s[6:7], s[8:9]\n\ts_mul_i32 s5, s7, 24\n\ts_mul_hi_u32 s7, s6, 24\n\ts_mul_i32 s6, s6, 24\n\ts_add_i32 s7, s7, s5\n\tv_add_co_u32 v2, vcc_lo, v4, s6\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo\n\ts_mov_b32 s5, exec_lo\n\tglobal_store_b64 v[2:3], v[14:15], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[8:9], v25, v[12:15], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[8:9], v[14:15]\n\ts_cbranch_execz .LBB8_314\n; %bb.312: ; in Loop: Header=BB8_302 Depth=1\n\ts_mov_b32 s6, 0\n.LBB8_313: ; Parent Loop BB8_302 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9\n\ts_sleep 1\n\tglobal_store_b64 v[2:3], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[6:7], v25, v[6:9], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]\n\tv_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6\n\ts_or_b32 s6, vcc_lo, s6\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s6\n\ts_cbranch_execnz .LBB8_313\n.LBB8_314: ; in Loop: Header=BB8_302 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s5\n\tglobal_load_b64 v[2:3], v25, s[2:3] offset:16\n\ts_mov_b32 s6, exec_lo\n\ts_mov_b32 s5, exec_lo\n\tv_mbcnt_lo_u32_b32 v6, s6, 0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_eq_u32_e32 0, v6\n\ts_cbranch_execz .LBB8_316\n; %bb.315: ; in Loop: Header=BB8_302 Depth=1\n\ts_bcnt1_i32_b32 s6, s6\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v6, s6\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[6:7], off offset:8\n.LBB8_316: ; in Loop: Header=BB8_302 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[6:7], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]\n\ts_cbranch_vccnz .LBB8_318\n; %bb.317: ; in Loop: Header=BB8_302 Depth=1\n\tglobal_load_b32 v24, v[2:3], off offset:24\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s5, v24\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[6:7], v[24:25], off\n\ts_and_b32 m0, s5, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_318: ; in Loop: Header=BB8_302 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s11, 24\n\ts_mul_hi_u32 s5, s10, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s5, s5, s1\n\ts_mul_i32 s1, s10, 24\n\tv_add_co_u32 v2, vcc_lo, v4, s1\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, v2, 20\n\tv_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo\n\ts_branch .LBB8_322\n\t.p2align\t6\n.LBB8_319: ; in Loop: Header=BB8_322 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v4\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_321\n; %bb.320: ; in Loop: Header=BB8_322 Depth=2\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_322\n\ts_branch .LBB8_324\n\t.p2align\t6\n.LBB8_321: ; in Loop: Header=BB8_302 Depth=1\n\ts_branch .LBB8_324\n.LBB8_322: ; Parent Loop BB8_302 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_mov_b32_e32 v4, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_319\n; %bb.323: ; in Loop: Header=BB8_322 Depth=2\n\tglobal_load_b32 v4, v[2:3], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v4, 1, v4\n\ts_branch .LBB8_319\n.LBB8_324: ; in Loop: Header=BB8_302 Depth=1\n\tglobal_load_b64 v[26:27], v[10:11], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_328\n; %bb.325: ; in Loop: Header=BB8_302 Depth=1\n\ts_clause 0x2\n\tglobal_load_b64 v[4:5], v25, s[2:3] offset:40\n\tglobal_load_b64 v[8:9], v25, s[2:3] offset:24 glc\n\tglobal_load_b64 v[6:7], v25, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v10, vcc_lo, v4, 1\n\tv_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, v10, s8\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s9, v11, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\tv_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10\n\tv_and_b32_e32 v5, v3, v5\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v4, v2, v4\n\tv_mul_hi_u32 v10, v4, 24\n\tv_mul_lo_u32 v4, v4, 24\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_add_co_u32 v6, vcc_lo, v6, v4\n\tv_mov_b32_e32 v4, v8\n\tv_mul_lo_u32 v5, v5, 24\n\tv_add_nc_u32_e32 v5, v10, v5\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v5, v9\n\tglobal_store_b64 v[6:7], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_328\n; %bb.326: ; in Loop: Header=BB8_302 Depth=1\n\ts_mov_b32 s0, 0\n.LBB8_327: ; Parent Loop BB8_302 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]\n\tv_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_327\n.LBB8_328: ; in Loop: Header=BB8_302 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_getpc_b64 s[6:7]\n\ts_add_u32 s6, s6, .str.3@rel32@lo+4\n\ts_addc_u32 s7, s7, .str.3@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_cmp_lg_u64 s[6:7], 0\n\ts_cbranch_scc0 .LBB8_407\n; %bb.329: ; in Loop: Header=BB8_302 Depth=1\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v3, v27 :: v_dual_and_b32 v24, 2, v26\n\tv_dual_mov_b32 v29, v25 :: v_dual_and_b32 v2, -3, v26\n\ts_mov_b64 s[8:9], 6\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_mov_b32_e32 v28, v24\n\ts_branch .LBB8_331\n.LBB8_330: ; in Loop: Header=BB8_331 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_sub_u32 s8, s8, s10\n\ts_subb_u32 s9, s9, s11\n\ts_add_u32 s6, s6, s10\n\ts_addc_u32 s7, s7, s11\n\ts_cmp_lg_u64 s[8:9], 0\n\ts_cbranch_scc0 .LBB8_408\n.LBB8_331: ; Parent Loop BB8_302 Depth=1\n ; => This Loop Header: Depth=2\n ; Child Loop BB8_334 Depth 3\n ; Child Loop BB8_342 Depth 3\n ; Child Loop BB8_349 Depth 3\n ; Child Loop BB8_356 Depth 3\n ; Child Loop BB8_363 Depth 3\n ; Child Loop BB8_370 Depth 3\n ; Child Loop BB8_377 Depth 3\n ; Child Loop BB8_384 Depth 3\n ; Child Loop BB8_392 Depth 3\n ; Child Loop BB8_401 Depth 3\n ; Child Loop BB8_406 Depth 3\n\tv_cmp_lt_u64_e64 s0, s[8:9], 56\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b32 s0, s0, exec_lo\n\ts_cselect_b32 s10, s8, 56\n\ts_cselect_b32 s11, s9, 0\n\ts_cmp_gt_u32 s10, 7\n\ts_cbranch_scc1 .LBB8_336\n; %bb.332: ; in Loop: Header=BB8_331 Depth=2\n\tv_mov_b32_e32 v4, 0\n\tv_mov_b32_e32 v5, 0\n\ts_cmp_eq_u32 s10, 0\n\ts_cbranch_scc1 .LBB8_335\n; %bb.333: ; in Loop: Header=BB8_331 Depth=2\n\ts_lshl_b64 s[0:1], s[10:11], 3\n\ts_mov_b64 s[12:13], 0\n\ts_mov_b64 s[14:15], s[6:7]\n.LBB8_334: ; Parent Loop BB8_302 Depth=1\n ; Parent Loop BB8_331 Depth=2\n ; => This Inner Loop Header: Depth=3\n\tglobal_load_u8 v6, v25, s[14:15]\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v6\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[6:7], s12, v[24:25]\n\ts_add_u32 s12, s12, 8\n\ts_addc_u32 s13, s13, 0\n\ts_add_u32 s14, s14, 1\n\ts_addc_u32 s15, s15, 0\n\ts_cmp_lg_u32 s0, s12\n\tv_or_b32_e32 v4, v6, v4\n\tv_or_b32_e32 v5, v7, v5\n\ts_cbranch_scc1 .LBB8_334\n.LBB8_335: ; in Loop: Header=BB8_331 Depth=2\n\ts_mov_b32 s0, 0\n\ts_mov_b32 s5, 0\n\ts_branch .LBB8_337\n.LBB8_336: ; in Loop: Header=BB8_331 Depth=2\n\ts_mov_b32 s0, -1\n ; implicit-def: $vgpr4_vgpr5\n ; implicit-def: $sgpr5\n.LBB8_337: ; in Loop: Header=BB8_331 Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 vcc_lo, exec_lo, s0\n\ts_mov_b64 s[0:1], s[6:7]\n\ts_cbranch_vccnz .LBB8_339\n; %bb.338: ; in Loop: Header=BB8_331 Depth=2\n\tglobal_load_b64 v[4:5], v25, s[6:7]\n\ts_add_i32 s5, s10, -8\n\ts_add_u32 s0, s6, 8\n\ts_addc_u32 s1, s7, 0\n.LBB8_339: ; in Loop: Header=BB8_331 Depth=2\n\ts_cmp_gt_u32 s5, 7\n\ts_cbranch_scc1 .LBB8_344\n; %bb.340: ; in Loop: Header=BB8_331 Depth=2\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\ts_cmp_eq_u32 s5, 0\n\ts_cbranch_scc1 .LBB8_343\n; %bb.341: ; in Loop: Header=BB8_331 Depth=2\n\ts_mov_b64 s[12:13], 0\n\ts_mov_b64 s[14:15], 0\n.LBB8_342: ; Parent Loop BB8_302 Depth=1\n ; Parent Loop BB8_331 Depth=2\n ; => This Inner Loop Header: Depth=3\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s20, s0, s14\n\ts_addc_u32 s21, s1, s15\n\ts_add_u32 s14, s14, 1\n\tglobal_load_u8 v8, v25, s[20:21]\n\ts_addc_u32 s15, s15, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v8\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[8:9], s12, v[24:25]\n\ts_add_u32 s12, s12, 8\n\ts_addc_u32 s13, s13, 0\n\ts_cmp_lg_u32 s5, s14\n\tv_or_b32_e32 v6, v8, v6\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v7, v9, v7\n\ts_cbranch_scc1 .LBB8_342\n.LBB8_343: ; in Loop: Header=BB8_331 Depth=2\n\ts_mov_b32 s19, 0\n\ts_cbranch_execz .LBB8_345\n\ts_branch .LBB8_346\n.LBB8_344: ; in Loop: Header=BB8_331 Depth=2\n ; implicit-def: $vgpr6_vgpr7\n ; implicit-def: $sgpr19\n.LBB8_345: ; in Loop: Header=BB8_331 Depth=2\n\tglobal_load_b64 v[6:7], v25, s[0:1]\n\ts_add_i32 s19, s5, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_346: ; in Loop: Header=BB8_331 Depth=2\n\ts_cmp_gt_u32 s19, 7\n\ts_cbranch_scc1 .LBB8_351\n; %bb.347: ; in Loop: Header=BB8_331 Depth=2\n\tv_mov_b32_e32 v8, 0\n\tv_mov_b32_e32 v9, 0\n\ts_cmp_eq_u32 s19, 0\n\ts_cbranch_scc1 .LBB8_350\n; %bb.348: ; in Loop: Header=BB8_331 Depth=2\n\ts_mov_b64 s[12:13], 0\n\ts_mov_b64 s[14:15], 0\n.LBB8_349: ; Parent Loop BB8_302 Depth=1\n ; Parent Loop BB8_331 Depth=2\n ; => This Inner Loop Header: Depth=3\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s20, s0, s14\n\ts_addc_u32 s21, s1, s15\n\ts_add_u32 s14, s14, 1\n\tglobal_load_u8 v10, v25, s[20:21]\n\ts_addc_u32 s15, s15, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v10\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[10:11], s12, v[24:25]\n\ts_add_u32 s12, s12, 8\n\ts_addc_u32 s13, s13, 0\n\ts_cmp_lg_u32 s19, s14\n\tv_or_b32_e32 v8, v10, v8\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v9, v11, v9\n\ts_cbranch_scc1 .LBB8_349\n.LBB8_350: ; in Loop: Header=BB8_331 Depth=2\n\ts_mov_b32 s5, 0\n\ts_cbranch_execz .LBB8_352\n\ts_branch .LBB8_353\n.LBB8_351: ; in Loop: Header=BB8_331 Depth=2\n ; implicit-def: $sgpr5\n.LBB8_352: ; in Loop: Header=BB8_331 Depth=2\n\tglobal_load_b64 v[8:9], v25, s[0:1]\n\ts_add_i32 s5, s19, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_353: ; in Loop: Header=BB8_331 Depth=2\n\ts_cmp_gt_u32 s5, 7\n\ts_cbranch_scc1 .LBB8_358\n; %bb.354: ; in Loop: Header=BB8_331 Depth=2\n\tv_mov_b32_e32 v10, 0\n\tv_mov_b32_e32 v11, 0\n\ts_cmp_eq_u32 s5, 0\n\ts_cbranch_scc1 .LBB8_357\n; %bb.355: ; in Loop: Header=BB8_331 Depth=2\n\ts_mov_b64 s[12:13], 0\n\ts_mov_b64 s[14:15], 0\n.LBB8_356: ; Parent Loop BB8_302 Depth=1\n ; Parent Loop BB8_331 Depth=2\n ; => This Inner Loop Header: Depth=3\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s20, s0, s14\n\ts_addc_u32 s21, s1, s15\n\ts_add_u32 s14, s14, 1\n\tglobal_load_u8 v12, v25, s[20:21]\n\ts_addc_u32 s15, s15, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v12\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[12:13], s12, v[24:25]\n\ts_add_u32 s12, s12, 8\n\ts_addc_u32 s13, s13, 0\n\ts_cmp_lg_u32 s5, s14\n\tv_or_b32_e32 v10, v12, v10\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v11, v13, v11\n\ts_cbranch_scc1 .LBB8_356\n.LBB8_357: ; in Loop: Header=BB8_331 Depth=2\n\ts_mov_b32 s19, 0\n\ts_cbranch_execz .LBB8_359\n\ts_branch .LBB8_360\n.LBB8_358: ; in Loop: Header=BB8_331 Depth=2\n ; implicit-def: $vgpr10_vgpr11\n ; implicit-def: $sgpr19\n.LBB8_359: ; in Loop: Header=BB8_331 Depth=2\n\tglobal_load_b64 v[10:11], v25, s[0:1]\n\ts_add_i32 s19, s5, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_360: ; in Loop: Header=BB8_331 Depth=2\n\ts_cmp_gt_u32 s19, 7\n\ts_cbranch_scc1 .LBB8_365\n; %bb.361: ; in Loop: Header=BB8_331 Depth=2\n\tv_mov_b32_e32 v12, 0\n\tv_mov_b32_e32 v13, 0\n\ts_cmp_eq_u32 s19, 0\n\ts_cbranch_scc1 .LBB8_364\n; %bb.362: ; in Loop: Header=BB8_331 Depth=2\n\ts_mov_b64 s[12:13], 0\n\ts_mov_b64 s[14:15], 0\n.LBB8_363: ; Parent Loop BB8_302 Depth=1\n ; Parent Loop BB8_331 Depth=2\n ; => This Inner Loop Header: Depth=3\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s20, s0, s14\n\ts_addc_u32 s21, s1, s15\n\ts_add_u32 s14, s14, 1\n\tglobal_load_u8 v14, v25, s[20:21]\n\ts_addc_u32 s15, s15, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v14\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[14:15], s12, v[24:25]\n\ts_add_u32 s12, s12, 8\n\ts_addc_u32 s13, s13, 0\n\ts_cmp_lg_u32 s19, s14\n\tv_or_b32_e32 v12, v14, v12\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v13, v15, v13\n\ts_cbranch_scc1 .LBB8_363\n.LBB8_364: ; in Loop: Header=BB8_331 Depth=2\n\ts_mov_b32 s5, 0\n\ts_cbranch_execz .LBB8_366\n\ts_branch .LBB8_367\n.LBB8_365: ; in Loop: Header=BB8_331 Depth=2\n ; implicit-def: $sgpr5\n.LBB8_366: ; in Loop: Header=BB8_331 Depth=2\n\tglobal_load_b64 v[12:13], v25, s[0:1]\n\ts_add_i32 s5, s19, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_367: ; in Loop: Header=BB8_331 Depth=2\n\ts_cmp_gt_u32 s5, 7\n\ts_cbranch_scc1 .LBB8_372\n; %bb.368: ; in Loop: Header=BB8_331 Depth=2\n\tv_mov_b32_e32 v14, 0\n\tv_mov_b32_e32 v15, 0\n\ts_cmp_eq_u32 s5, 0\n\ts_cbranch_scc1 .LBB8_371\n; %bb.369: ; in Loop: Header=BB8_331 Depth=2\n\ts_mov_b64 s[12:13], 0\n\ts_mov_b64 s[14:15], 0\n.LBB8_370: ; Parent Loop BB8_302 Depth=1\n ; Parent Loop BB8_331 Depth=2\n ; => This Inner Loop Header: Depth=3\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s20, s0, s14\n\ts_addc_u32 s21, s1, s15\n\ts_add_u32 s14, s14, 1\n\tglobal_load_u8 v16, v25, s[20:21]\n\ts_addc_u32 s15, s15, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v16\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[16:17], s12, v[24:25]\n\ts_add_u32 s12, s12, 8\n\ts_addc_u32 s13, s13, 0\n\ts_cmp_lg_u32 s5, s14\n\tv_or_b32_e32 v14, v16, v14\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v15, v17, v15\n\ts_cbranch_scc1 .LBB8_370\n.LBB8_371: ; in Loop: Header=BB8_331 Depth=2\n\ts_mov_b32 s19, 0\n\ts_cbranch_execz .LBB8_373\n\ts_branch .LBB8_374\n.LBB8_372: ; in Loop: Header=BB8_331 Depth=2\n ; implicit-def: $vgpr14_vgpr15\n ; implicit-def: $sgpr19\n.LBB8_373: ; in Loop: Header=BB8_331 Depth=2\n\tglobal_load_b64 v[14:15], v25, s[0:1]\n\ts_add_i32 s19, s5, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_374: ; in Loop: Header=BB8_331 Depth=2\n\ts_cmp_gt_u32 s19, 7\n\ts_cbranch_scc1 .LBB8_379\n; %bb.375: ; in Loop: Header=BB8_331 Depth=2\n\tv_mov_b32_e32 v16, 0\n\tv_mov_b32_e32 v17, 0\n\ts_cmp_eq_u32 s19, 0\n\ts_cbranch_scc1 .LBB8_378\n; %bb.376: ; in Loop: Header=BB8_331 Depth=2\n\ts_mov_b64 s[12:13], 0\n\ts_mov_b64 s[14:15], s[0:1]\n.LBB8_377: ; Parent Loop BB8_302 Depth=1\n ; Parent Loop BB8_331 Depth=2\n ; => This Inner Loop Header: Depth=3\n\tglobal_load_u8 v18, v25, s[14:15]\n\ts_add_i32 s19, s19, -1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v18\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[18:19], s12, v[24:25]\n\ts_add_u32 s12, s12, 8\n\ts_addc_u32 s13, s13, 0\n\ts_add_u32 s14, s14, 1\n\ts_addc_u32 s15, s15, 0\n\ts_cmp_lg_u32 s19, 0\n\tv_or_b32_e32 v16, v18, v16\n\tv_or_b32_e32 v17, v19, v17\n\ts_cbranch_scc1 .LBB8_377\n.LBB8_378: ; in Loop: Header=BB8_331 Depth=2\n\ts_mov_b32 s5, 0\n\ts_cbranch_execz .LBB8_380\n\ts_branch .LBB8_381\n.LBB8_379: ; in Loop: Header=BB8_331 Depth=2\n\ts_mov_b32 s5, -1\n.LBB8_380: ; in Loop: Header=BB8_331 Depth=2\n\tglobal_load_b64 v[16:17], v25, s[0:1]\n.LBB8_381: ; in Loop: Header=BB8_331 Depth=2\n\tv_mov_b32_e32 v24, v23\n\tv_mov_b32_e32 v30, 0\n\tv_mov_b32_e32 v31, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v24\n\tv_cmp_eq_u32_e64 s0, s0, v24\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_387\n; %bb.382: ; in Loop: Header=BB8_331 Depth=2\n\tglobal_load_b64 v[20:21], v25, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[18:19], v25, s[2:3] offset:40\n\tglobal_load_b64 v[30:31], v25, s[2:3]\n\ts_mov_b32 s5, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v19, v19, v21\n\tv_and_b32_e32 v18, v18, v20\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v19, v19, 24\n\tv_mul_hi_u32 v34, v18, 24\n\tv_mul_lo_u32 v18, v18, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v19, v34, v19\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v18, vcc_lo, v30, v18\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v19, vcc_lo, v31, v19, vcc_lo\n\tglobal_load_b64 v[18:19], v[18:19], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[30:31], v25, v[18:21], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[30:31], v[20:21]\n\ts_cbranch_execz .LBB8_386\n; %bb.383: ; in Loop: Header=BB8_331 Depth=2\n\ts_mov_b32 s12, 0\n\t.p2align\t6\n.LBB8_384: ; Parent Loop BB8_302 Depth=1\n ; Parent Loop BB8_331 Depth=2\n ; => This Inner Loop Header: Depth=3\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[18:19], v25, s[2:3] offset:40\n\tglobal_load_b64 v[34:35], v25, s[2:3]\n\tv_dual_mov_b32 v20, v30 :: v_dual_mov_b32 v21, v31\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v18, v18, v20\n\tv_and_b32_e32 v19, v19, v21\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[30:31], null, v18, 24, v[34:35]\n\tv_mov_b32_e32 v18, v31\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[34:35], null, v19, 24, v[18:19]\n\tv_mov_b32_e32 v31, v34\n\tglobal_load_b64 v[18:19], v[30:31], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[30:31], v25, v[18:21], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[30:31], v[20:21]\n\ts_or_b32 s12, vcc_lo, s12\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s12\n\ts_cbranch_execnz .LBB8_384\n; %bb.385: ; in Loop: Header=BB8_331 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s12\n.LBB8_386: ; in Loop: Header=BB8_331 Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s5\n.LBB8_387: ; in Loop: Header=BB8_331 Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_clause 0x1\n\tglobal_load_b64 v[34:35], v25, s[2:3] offset:40\n\tglobal_load_b128 v[18:21], v25, s[2:3]\n\tv_readfirstlane_b32 s12, v30\n\tv_readfirstlane_b32 s13, v31\n\ts_mov_b32 s5, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s14, v34\n\tv_readfirstlane_b32 s15, v35\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[14:15], s[12:13], s[14:15]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_389\n; %bb.388: ; in Loop: Header=BB8_331 Depth=2\n\tv_dual_mov_b32 v34, s5 :: v_dual_mov_b32 v35, 0\n\ts_mul_i32 s5, s15, 24\n\ts_mul_hi_u32 s19, s14, 24\n\tv_dual_mov_b32 v36, 2 :: v_dual_mov_b32 v37, 1\n\ts_add_i32 s19, s19, s5\n\ts_mul_i32 s5, s14, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v30, vcc_lo, v18, s5\n\tv_add_co_ci_u32_e32 v31, vcc_lo, s19, v19, vcc_lo\n\tglobal_store_b128 v[30:31], v[34:37], off offset:8\n.LBB8_389: ; in Loop: Header=BB8_331 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_cmp_gt_u64_e64 vcc_lo, s[8:9], 56\n\tv_or_b32_e32 v30, v3, v29\n\tv_or_b32_e32 v31, v2, v28\n\ts_lshl_b64 s[20:21], s[14:15], 12\n\ts_lshl_b32 s1, s10, 2\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\ts_add_i32 s1, s1, 28\n\tv_dual_cndmask_b32 v3, v30, v3 :: v_dual_cndmask_b32 v2, v31, v2\n\tv_lshlrev_b64 v[30:31], 6, v[24:25]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v20, vcc_lo, v20, s20\n\tv_add_co_ci_u32_e32 v21, vcc_lo, s21, v21, vcc_lo\n\ts_and_b32 s1, s1, 0x1e0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v20, vcc_lo, v20, v30\n\tv_and_or_b32 v2, v2, 0xffffff1f, s1\n\tv_add_co_ci_u32_e32 v21, vcc_lo, v21, v31, vcc_lo\n\ts_clause 0x3\n\tglobal_store_b128 v[20:21], v[2:5], off\n\tglobal_store_b128 v[20:21], v[6:9], off offset:16\n\tglobal_store_b128 v[20:21], v[10:13], off offset:32\n\tglobal_store_b128 v[20:21], v[14:17], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_397\n; %bb.390: ; in Loop: Header=BB8_331 Depth=2\n\ts_clause 0x1\n\tglobal_load_b64 v[10:11], v25, s[2:3] offset:32 glc\n\tglobal_load_b64 v[2:3], v25, s[2:3] offset:40\n\tv_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s20, v2\n\tv_readfirstlane_b32 s21, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[20:21], s[20:21], s[12:13]\n\ts_mul_i32 s5, s21, 24\n\ts_mul_hi_u32 s19, s20, 24\n\ts_mul_i32 s20, s20, 24\n\ts_add_i32 s19, s19, s5\n\tv_add_co_u32 v6, vcc_lo, v18, s20\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s19, v19, vcc_lo\n\ts_mov_b32 s5, exec_lo\n\tglobal_store_b64 v[6:7], v[10:11], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v25, v[8:11], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[10:11]\n\ts_cbranch_execz .LBB8_393\n; %bb.391: ; in Loop: Header=BB8_331 Depth=2\n\ts_mov_b32 s19, 0\n.LBB8_392: ; Parent Loop BB8_302 Depth=1\n ; Parent Loop BB8_331 Depth=2\n ; => This Inner Loop Header: Depth=3\n\tv_dual_mov_b32 v2, s12 :: v_dual_mov_b32 v3, s13\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v25, v[2:5], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s19, vcc_lo, s19\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s19\n\ts_cbranch_execnz .LBB8_392\n.LBB8_393: ; in Loop: Header=BB8_331 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s5\n\tglobal_load_b64 v[2:3], v25, s[2:3] offset:16\n\ts_mov_b32 s19, exec_lo\n\ts_mov_b32 s5, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s19, 0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_395\n; %bb.394: ; in Loop: Header=BB8_331 Depth=2\n\ts_bcnt1_i32_b32 s19, s19\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s19\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_395: ; in Loop: Header=BB8_331 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_397\n; %bb.396: ; in Loop: Header=BB8_331 Depth=2\n\tglobal_load_b32 v24, v[2:3], off offset:24\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s5, v24\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[24:25], off\n\ts_and_b32 m0, s5, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_397: ; in Loop: Header=BB8_331 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s15, 24\n\ts_mul_hi_u32 s5, s14, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s5, s5, s1\n\ts_mul_i32 s1, s14, 24\n\tv_add_co_u32 v2, vcc_lo, v18, s1\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s5, v19, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, v2, 20\n\tv_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo\n\ts_branch .LBB8_401\n\t.p2align\t6\n.LBB8_398: ; in Loop: Header=BB8_401 Depth=3\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v4\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_400\n; %bb.399: ; in Loop: Header=BB8_401 Depth=3\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_401\n\ts_branch .LBB8_403\n\t.p2align\t6\n.LBB8_400: ; in Loop: Header=BB8_331 Depth=2\n\ts_branch .LBB8_403\n.LBB8_401: ; Parent Loop BB8_302 Depth=1\n ; Parent Loop BB8_331 Depth=2\n ; => This Inner Loop Header: Depth=3\n\tv_mov_b32_e32 v4, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_398\n; %bb.402: ; in Loop: Header=BB8_401 Depth=3\n\tglobal_load_b32 v4, v[2:3], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v4, 1, v4\n\ts_branch .LBB8_398\n.LBB8_403: ; in Loop: Header=BB8_331 Depth=2\n\tglobal_load_b64 v[2:3], v[20:21], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_330\n; %bb.404: ; in Loop: Header=BB8_331 Depth=2\n\ts_clause 0x2\n\tglobal_load_b64 v[6:7], v25, s[2:3] offset:40\n\tglobal_load_b64 v[10:11], v25, s[2:3] offset:24 glc\n\tglobal_load_b64 v[8:9], v25, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v12, vcc_lo, v6, 1\n\tv_add_co_ci_u32_e32 v13, vcc_lo, 0, v7, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v4, vcc_lo, v12, s12\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s13, v13, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\tv_dual_cndmask_b32 v5, v5, v13 :: v_dual_cndmask_b32 v4, v4, v12\n\tv_and_b32_e32 v7, v5, v7\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v6, v4, v6\n\tv_mul_hi_u32 v12, v6, 24\n\tv_mul_lo_u32 v6, v6, 24\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_add_co_u32 v8, vcc_lo, v8, v6\n\tv_mov_b32_e32 v6, v10\n\tv_mul_lo_u32 v7, v7, 24\n\tv_add_nc_u32_e32 v7, v12, v7\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_co_ci_u32_e32 v9, vcc_lo, v9, v7, vcc_lo\n\tv_mov_b32_e32 v7, v11\n\tglobal_store_b64 v[8:9], v[10:11], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[6:7], v25, v[4:7], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[6:7], v[10:11]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_330\n; %bb.405: ; in Loop: Header=BB8_331 Depth=2\n\ts_mov_b32 s0, 0\n.LBB8_406: ; Parent Loop BB8_302 Depth=1\n ; Parent Loop BB8_331 Depth=2\n ; => This Inner Loop Header: Depth=3\n\ts_sleep 1\n\tglobal_store_b64 v[8:9], v[6:7], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[10:11], v25, v[4:7], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[10:11], v[6:7]\n\tv_dual_mov_b32 v6, v10 :: v_dual_mov_b32 v7, v11\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_406\n\ts_branch .LBB8_330\n.LBB8_407: ; in Loop: Header=BB8_302 Depth=1\n ; implicit-def: $vgpr2_vgpr3\n\ts_cbranch_execnz .LBB8_409\n\ts_branch .LBB8_436\n.LBB8_408: ; in Loop: Header=BB8_302 Depth=1\n\ts_branch .LBB8_436\n.LBB8_409: ; in Loop: Header=BB8_302 Depth=1\n\tv_mov_b32_e32 v24, v23\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v24\n\tv_cmp_eq_u32_e64 s0, s0, v24\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_415\n; %bb.410: ; in Loop: Header=BB8_302 Depth=1\n\tglobal_load_b64 v[4:5], v25, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[2:3], v25, s[2:3] offset:40\n\tglobal_load_b64 v[6:7], v25, s[2:3]\n\ts_mov_b32 s5, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v3, v3, v5\n\tv_and_b32_e32 v2, v2, v4\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v3, v3, 24\n\tv_mul_hi_u32 v8, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v3, v8, v3\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v2, vcc_lo, v6, v2\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo\n\tglobal_load_b64 v[2:3], v[2:3], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v25, v[2:5], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[6:7], v[4:5]\n\ts_cbranch_execz .LBB8_414\n; %bb.411: ; in Loop: Header=BB8_302 Depth=1\n\ts_mov_b32 s6, 0\n\t.p2align\t6\n.LBB8_412: ; Parent Loop BB8_302 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[2:3], v25, s[2:3] offset:40\n\tglobal_load_b64 v[8:9], v25, s[2:3]\n\tv_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v2, v4\n\tv_and_b32_e32 v3, v3, v5\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[6:7], null, v2, 24, v[8:9]\n\tv_mov_b32_e32 v2, v7\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_mad_u64_u32 v[7:8], null, v3, 24, v[2:3]\n\tglobal_load_b64 v[2:3], v[6:7], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v25, v[2:5], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[6:7], v[4:5]\n\ts_or_b32 s6, vcc_lo, s6\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s6\n\ts_cbranch_execnz .LBB8_412\n; %bb.413: ; in Loop: Header=BB8_302 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s6\n.LBB8_414: ; in Loop: Header=BB8_302 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s5\n.LBB8_415: ; in Loop: Header=BB8_302 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v25, s[2:3] offset:40\n\tglobal_load_b128 v[2:5], v25, s[2:3]\n\tv_readfirstlane_b32 s8, v6\n\tv_readfirstlane_b32 s9, v7\n\ts_mov_b32 s5, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s6, v8\n\tv_readfirstlane_b32 s7, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[10:11], s[8:9], s[6:7]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_417\n; %bb.416: ; in Loop: Header=BB8_302 Depth=1\n\tv_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v7, 0\n\ts_mul_i32 s5, s11, 24\n\ts_mul_hi_u32 s6, s10, 24\n\tv_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1\n\ts_add_i32 s6, s6, s5\n\ts_mul_i32 s5, s10, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v10, vcc_lo, v2, s5\n\tv_add_co_ci_u32_e32 v11, vcc_lo, s6, v3, vcc_lo\n\tglobal_store_b128 v[10:11], v[6:9], off offset:8\n.LBB8_417: ; in Loop: Header=BB8_302 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[6:7], s[10:11], 12\n\ts_mov_b32 s5, s4\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v6, vcc_lo, v4, s6\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo\n\tv_lshlrev_b64 v[4:5], 6, v[24:25]\n\ts_mov_b32 s6, s4\n\ts_mov_b32 s7, s4\n\tv_mov_b32_e32 v10, 0\n\tv_and_or_b32 v26, v26, 0xffffff1f, 32\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_add_co_u32 v8, vcc_lo, v6, v4\n\tv_add_co_ci_u32_e32 v9, vcc_lo, v7, v5, vcc_lo\n\tv_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7\n\tv_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v6, s6\n\tv_mov_b32_e32 v11, v10\n\ts_clause 0x4\n\tglobal_store_b64 v[8:9], v[26:27], off\n\tglobal_store_b128 v[8:9], v[4:7], off offset:8\n\tglobal_store_b128 v[8:9], v[4:7], off offset:24\n\tglobal_store_b128 v[8:9], v[4:7], off offset:40\n\tglobal_store_b64 v[8:9], v[10:11], off offset:56\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_425\n; %bb.418: ; in Loop: Header=BB8_302 Depth=1\n\ts_clause 0x1\n\tglobal_load_b64 v[14:15], v25, s[2:3] offset:32 glc\n\tglobal_load_b64 v[4:5], v25, s[2:3] offset:40\n\tv_dual_mov_b32 v12, s8 :: v_dual_mov_b32 v13, s9\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v4\n\tv_readfirstlane_b32 s7, v5\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[6:7], s[6:7], s[8:9]\n\ts_mul_i32 s5, s7, 24\n\ts_mul_hi_u32 s7, s6, 24\n\ts_mul_i32 s6, s6, 24\n\ts_add_i32 s7, s7, s5\n\tv_add_co_u32 v10, vcc_lo, v2, s6\n\tv_add_co_ci_u32_e32 v11, vcc_lo, s7, v3, vcc_lo\n\ts_mov_b32 s5, exec_lo\n\tglobal_store_b64 v[10:11], v[14:15], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[6:7], v25, v[12:15], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[6:7], v[14:15]\n\ts_cbranch_execz .LBB8_421\n; %bb.419: ; in Loop: Header=BB8_302 Depth=1\n\ts_mov_b32 s6, 0\n.LBB8_420: ; Parent Loop BB8_302 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9\n\ts_sleep 1\n\tglobal_store_b64 v[10:11], v[6:7], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v25, v[4:7], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]\n\tv_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4\n\ts_or_b32 s6, vcc_lo, s6\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s6\n\ts_cbranch_execnz .LBB8_420\n.LBB8_421: ; in Loop: Header=BB8_302 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s5\n\tglobal_load_b64 v[4:5], v25, s[2:3] offset:16\n\ts_mov_b32 s6, exec_lo\n\ts_mov_b32 s5, exec_lo\n\tv_mbcnt_lo_u32_b32 v6, s6, 0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_eq_u32_e32 0, v6\n\ts_cbranch_execz .LBB8_423\n; %bb.422: ; in Loop: Header=BB8_302 Depth=1\n\ts_bcnt1_i32_b32 s6, s6\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v6, s6\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[4:5], v[6:7], off offset:8\n.LBB8_423: ; in Loop: Header=BB8_302 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[6:7], v[4:5], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]\n\ts_cbranch_vccnz .LBB8_425\n; %bb.424: ; in Loop: Header=BB8_302 Depth=1\n\tglobal_load_b32 v24, v[4:5], off offset:24\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s5, v24\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[6:7], v[24:25], off\n\ts_and_b32 m0, s5, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_425: ; in Loop: Header=BB8_302 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s11, 24\n\ts_mul_hi_u32 s5, s10, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s5, s5, s1\n\ts_mul_i32 s1, s10, 24\n\tv_add_co_u32 v2, vcc_lo, v2, s1\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, v2, 20\n\tv_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo\n\ts_branch .LBB8_429\n\t.p2align\t6\n.LBB8_426: ; in Loop: Header=BB8_429 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v4\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_428\n; %bb.427: ; in Loop: Header=BB8_429 Depth=2\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_429\n\ts_branch .LBB8_431\n\t.p2align\t6\n.LBB8_428: ; in Loop: Header=BB8_302 Depth=1\n\ts_branch .LBB8_431\n.LBB8_429: ; Parent Loop BB8_302 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_mov_b32_e32 v4, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_426\n; %bb.430: ; in Loop: Header=BB8_429 Depth=2\n\tglobal_load_b32 v4, v[2:3], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v4, 1, v4\n\ts_branch .LBB8_426\n.LBB8_431: ; in Loop: Header=BB8_302 Depth=1\n\tglobal_load_b64 v[2:3], v[8:9], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_435\n; %bb.432: ; in Loop: Header=BB8_302 Depth=1\n\ts_clause 0x2\n\tglobal_load_b64 v[6:7], v25, s[2:3] offset:40\n\tglobal_load_b64 v[10:11], v25, s[2:3] offset:24 glc\n\tglobal_load_b64 v[8:9], v25, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v12, vcc_lo, v6, 1\n\tv_add_co_ci_u32_e32 v13, vcc_lo, 0, v7, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v4, vcc_lo, v12, s8\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s9, v13, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\tv_dual_cndmask_b32 v5, v5, v13 :: v_dual_cndmask_b32 v4, v4, v12\n\tv_and_b32_e32 v7, v5, v7\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v6, v4, v6\n\tv_mul_hi_u32 v12, v6, 24\n\tv_mul_lo_u32 v6, v6, 24\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_add_co_u32 v8, vcc_lo, v8, v6\n\tv_mov_b32_e32 v6, v10\n\tv_mul_lo_u32 v7, v7, 24\n\tv_add_nc_u32_e32 v7, v12, v7\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_co_ci_u32_e32 v9, vcc_lo, v9, v7, vcc_lo\n\tv_mov_b32_e32 v7, v11\n\tglobal_store_b64 v[8:9], v[10:11], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[6:7], v25, v[4:7], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[6:7], v[10:11]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_435\n; %bb.433: ; in Loop: Header=BB8_302 Depth=1\n\ts_mov_b32 s0, 0\n.LBB8_434: ; Parent Loop BB8_302 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\tglobal_store_b64 v[8:9], v[6:7], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[10:11], v25, v[4:7], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[10:11], v[6:7]\n\tv_dual_mov_b32 v6, v10 :: v_dual_mov_b32 v7, v11\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_434\n.LBB8_435: ; in Loop: Header=BB8_302 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n.LBB8_436: ; in Loop: Header=BB8_302 Depth=1\n\tv_mov_b32_e32 v24, v23\n\tv_mov_b32_e32 v4, 0\n\tv_mov_b32_e32 v5, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v24\n\tv_cmp_eq_u32_e64 s0, s0, v24\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_442\n; %bb.437: ; in Loop: Header=BB8_302 Depth=1\n\tglobal_load_b64 v[6:7], v25, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[4:5], v25, s[2:3] offset:40\n\tglobal_load_b64 v[8:9], v25, s[2:3]\n\ts_mov_b32 s5, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v5, v5, v7\n\tv_and_b32_e32 v4, v4, v6\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v5, v5, 24\n\tv_mul_hi_u32 v10, v4, 24\n\tv_mul_lo_u32 v4, v4, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v5, v10, v5\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v4, vcc_lo, v8, v4\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo\n\tglobal_load_b64 v[4:5], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[4:5], v25, v[4:7], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[4:5], v[6:7]\n\ts_cbranch_execz .LBB8_441\n; %bb.438: ; in Loop: Header=BB8_302 Depth=1\n\ts_mov_b32 s6, 0\n\t.p2align\t6\n.LBB8_439: ; Parent Loop BB8_302 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v25, s[2:3] offset:40\n\tglobal_load_b64 v[10:11], v25, s[2:3]\n\tv_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v8, v8, v6\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[4:5], null, v8, 24, v[10:11]\n\tv_and_b32_e32 v10, v9, v7\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[8:9], null, v10, 24, v[5:6]\n\tv_mov_b32_e32 v5, v8\n\tglobal_load_b64 v[4:5], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[4:5], v25, v[4:7], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]\n\ts_or_b32 s6, vcc_lo, s6\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s6\n\ts_cbranch_execnz .LBB8_439\n; %bb.440: ; in Loop: Header=BB8_302 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s6\n.LBB8_441: ; in Loop: Header=BB8_302 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s5\n.LBB8_442: ; in Loop: Header=BB8_302 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_clause 0x1\n\tglobal_load_b64 v[10:11], v25, s[2:3] offset:40\n\tglobal_load_b128 v[6:9], v25, s[2:3]\n\tv_readfirstlane_b32 s8, v4\n\tv_readfirstlane_b32 s9, v5\n\ts_mov_b32 s5, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s6, v10\n\tv_readfirstlane_b32 s7, v11\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[10:11], s[8:9], s[6:7]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_444\n; %bb.443: ; in Loop: Header=BB8_302 Depth=1\n\tv_dual_mov_b32 v10, s5 :: v_dual_mov_b32 v11, 0\n\ts_mul_i32 s5, s11, 24\n\ts_mul_hi_u32 s6, s10, 24\n\tv_dual_mov_b32 v12, 2 :: v_dual_mov_b32 v13, 1\n\ts_add_i32 s6, s6, s5\n\ts_mul_i32 s5, s10, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v4, vcc_lo, v6, s5\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s6, v7, vcc_lo\n\tglobal_store_b128 v[4:5], v[10:13], off offset:8\n.LBB8_444: ; in Loop: Header=BB8_302 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_cvt_f64_f32_e32 v[4:5], v33\n\ts_lshl_b64 s[12:13], s[10:11], 12\n\tv_lshlrev_b64 v[10:11], 6, v[24:25]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v8, vcc_lo, v8, s12\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s13, v9, vcc_lo\n\ts_mov_b32 s7, s4\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_u32 v12, vcc_lo, v8, v10\n\ts_mov_b32 s5, s4\n\ts_mov_b32 s6, s4\n\tv_and_or_b32 v2, v2, 0xffffff1d, 34\n\tv_add_co_ci_u32_e32 v13, vcc_lo, v9, v11, vcc_lo\n\tv_dual_mov_b32 v11, s7 :: v_dual_mov_b32 v10, s6\n\tv_dual_mov_b32 v9, s5 :: v_dual_mov_b32 v8, s4\n\ts_clause 0x3\n\tglobal_store_b128 v[12:13], v[2:5], off\n\tglobal_store_b128 v[12:13], v[8:11], off offset:16\n\tglobal_store_b128 v[12:13], v[8:11], off offset:32\n\tglobal_store_b128 v[12:13], v[8:11], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_452\n; %bb.445: ; in Loop: Header=BB8_302 Depth=1\n\ts_clause 0x1\n\tglobal_load_b64 v[12:13], v25, s[2:3] offset:32 glc\n\tglobal_load_b64 v[2:3], v25, s[2:3] offset:40\n\tv_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\tv_readfirstlane_b32 s7, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[6:7], s[6:7], s[8:9]\n\ts_mul_i32 s5, s7, 24\n\ts_mul_hi_u32 s7, s6, 24\n\ts_mul_i32 s6, s6, 24\n\ts_add_i32 s7, s7, s5\n\tv_add_co_u32 v8, vcc_lo, v6, s6\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s7, v7, vcc_lo\n\ts_mov_b32 s5, exec_lo\n\tglobal_store_b64 v[8:9], v[12:13], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v25, v[10:13], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[12:13]\n\ts_cbranch_execz .LBB8_448\n; %bb.446: ; in Loop: Header=BB8_302 Depth=1\n\ts_mov_b32 s6, 0\n.LBB8_447: ; Parent Loop BB8_302 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9\n\ts_sleep 1\n\tglobal_store_b64 v[8:9], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v25, v[2:5], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s6, vcc_lo, s6\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s6\n\ts_cbranch_execnz .LBB8_447\n.LBB8_448: ; in Loop: Header=BB8_302 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s5\n\tglobal_load_b64 v[2:3], v25, s[2:3] offset:16\n\ts_mov_b32 s6, exec_lo\n\ts_mov_b32 s5, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s6, 0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_450\n; %bb.449: ; in Loop: Header=BB8_302 Depth=1\n\ts_bcnt1_i32_b32 s6, s6\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s6\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_450: ; in Loop: Header=BB8_302 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_452\n; %bb.451: ; in Loop: Header=BB8_302 Depth=1\n\tglobal_load_b32 v24, v[2:3], off offset:24\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s5, v24\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[24:25], off\n\ts_and_b32 m0, s5, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_452: ; in Loop: Header=BB8_302 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s11, 24\n\ts_mul_hi_u32 s5, s10, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s5, s5, s1\n\ts_mul_i32 s1, s10, 24\n\tv_add_co_u32 v2, vcc_lo, v6, s1\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s5, v7, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, v2, 20\n\tv_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo\n\ts_branch .LBB8_456\n\t.p2align\t6\n.LBB8_453: ; in Loop: Header=BB8_456 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v4\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_455\n; %bb.454: ; in Loop: Header=BB8_456 Depth=2\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_456\n\ts_branch .LBB8_458\n\t.p2align\t6\n.LBB8_455: ; in Loop: Header=BB8_302 Depth=1\n\ts_branch .LBB8_458\n.LBB8_456: ; Parent Loop BB8_302 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_mov_b32_e32 v4, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_453\n; %bb.457: ; in Loop: Header=BB8_456 Depth=2\n\tglobal_load_b32 v4, v[2:3], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v4, 1, v4\n\ts_branch .LBB8_453\n.LBB8_458: ; in Loop: Header=BB8_302 Depth=1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_301\n; %bb.459: ; in Loop: Header=BB8_302 Depth=1\n\ts_clause 0x2\n\tglobal_load_b64 v[4:5], v25, s[2:3] offset:40\n\tglobal_load_b64 v[8:9], v25, s[2:3] offset:24 glc\n\tglobal_load_b64 v[6:7], v25, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v10, vcc_lo, v4, 1\n\tv_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, v10, s8\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s9, v11, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\tv_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10\n\tv_and_b32_e32 v5, v3, v5\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v4, v2, v4\n\tv_mul_hi_u32 v10, v4, 24\n\tv_mul_lo_u32 v4, v4, 24\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_add_co_u32 v6, vcc_lo, v6, v4\n\tv_mov_b32_e32 v4, v8\n\tv_mul_lo_u32 v5, v5, 24\n\tv_add_nc_u32_e32 v5, v10, v5\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v5, v9\n\tglobal_store_b64 v[6:7], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_301\n; %bb.460: ; in Loop: Header=BB8_302 Depth=1\n\ts_mov_b32 s0, 0\n.LBB8_461: ; Parent Loop BB8_302 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]\n\tv_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_461\n\ts_branch .LBB8_301\n.LBB8_462:\n\ts_or_b32 exec_lo, exec_lo, s17\n; %bb.463:\n\tv_mov_b32_e32 v4, v23\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v4\n\tv_cmp_eq_u32_e64 s0, s0, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_469\n; %bb.464:\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s4, exec_lo\n\tglobal_load_b64 v[8:9], v0, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[2:3] offset:40\n\tglobal_load_b64 v[5:6], v0, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v2, v2, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v3, v1, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v3, v2\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, v5, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo\n\tglobal_load_b64 v[6:7], v[1:2], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[6:7], v[8:9]\n\ts_cbranch_execz .LBB8_468\n; %bb.465:\n\ts_mov_b32 s5, 0\n\t.p2align\t6\n.LBB8_466: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[2:3] offset:40\n\tglobal_load_b64 v[10:11], v0, s[2:3]\n\tv_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v7, v2, v9\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]\n\tv_mov_b32_e32 v1, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]\n\tv_mov_b32_e32 v6, v2\n\tglobal_load_b64 v[6:7], v[5:6], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]\n\ts_or_b32 s5, vcc_lo, s5\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s5\n\ts_cbranch_execnz .LBB8_466\n; %bb.467:\n\ts_or_b32 exec_lo, exec_lo, s5\n.LBB8_468:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s4\n.LBB8_469:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v5, 0\n\tv_readfirstlane_b32 s4, v6\n\tv_readfirstlane_b32 s5, v7\n\ts_mov_b32 s8, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v5, s[2:3] offset:40\n\tglobal_load_b128 v[0:3], v5, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s6, v8\n\tv_readfirstlane_b32 s7, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[6:7], s[4:5], s[6:7]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_471\n; %bb.470:\n\tv_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0\n\ts_mul_i32 s8, s7, 24\n\ts_mul_hi_u32 s9, s6, 24\n\tv_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1\n\ts_add_i32 s9, s9, s8\n\ts_mul_i32 s8, s6, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v10, vcc_lo, v0, s8\n\tv_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo\n\tglobal_store_b128 v[10:11], v[6:9], off offset:8\n.LBB8_471:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[8:9], s[6:7], 12\n\tv_lshlrev_b64 v[4:5], 6, v[4:5]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v2, vcc_lo, v2, s8\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo\n\tv_mov_b32_e32 v3, 0\n\ts_mov_b32 s8, 0\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_add_co_u32 v6, vcc_lo, v2, v4\n\tv_mov_b32_e32 v2, 33\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v4, v3\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8\n\tv_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10\n\tv_mov_b32_e32 v11, s11\n\ts_clause 0x3\n\tglobal_store_b128 v[6:7], v[2:5], off\n\tglobal_store_b128 v[6:7], v[8:11], off offset:16\n\tglobal_store_b128 v[6:7], v[8:11], off offset:32\n\tglobal_store_b128 v[6:7], v[8:11], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_479\n; %bb.472:\n\tv_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4\n\tv_mov_b32_e32 v12, s5\n\ts_clause 0x1\n\tglobal_load_b64 v[13:14], v10, s[2:3] offset:32 glc\n\tglobal_load_b64 v[2:3], v10, s[2:3] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s8, v2\n\tv_readfirstlane_b32 s9, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[8:9], s[8:9], s[4:5]\n\ts_mul_i32 s9, s9, 24\n\ts_mul_hi_u32 s10, s8, 24\n\ts_mul_i32 s8, s8, 24\n\ts_add_i32 s10, s10, s9\n\tv_add_co_u32 v8, vcc_lo, v0, s8\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo\n\ts_mov_b32 s8, exec_lo\n\tglobal_store_b64 v[8:9], v[13:14], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[13:14]\n\ts_cbranch_execz .LBB8_475\n; %bb.473:\n\ts_mov_b32 s9, 0\n.LBB8_474: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5\n\ts_sleep 1\n\tglobal_store_b64 v[8:9], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s9, vcc_lo, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s9\n\ts_cbranch_execnz .LBB8_474\n.LBB8_475:\n\ts_or_b32 exec_lo, exec_lo, s8\n\tv_mov_b32_e32 v2, 0\n\ts_mov_b32 s9, exec_lo\n\ts_mov_b32 s8, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s9, 0\n\tglobal_load_b64 v[2:3], v2, s[2:3] offset:16\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_477\n; %bb.476:\n\ts_bcnt1_i32_b32 s9, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_477:\n\ts_or_b32 exec_lo, exec_lo, s8\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_479\n; %bb.478:\n\tglobal_load_b32 v2, v[2:3], off offset:24\n\tv_mov_b32_e32 v3, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s8, v2\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_and_b32 m0, s8, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_479:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s7, 24\n\ts_mul_hi_u32 s7, s6, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s7, s7, s1\n\ts_mul_i32 s1, s6, 24\n\tv_add_co_u32 v0, vcc_lo, v0, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_483\n\t.p2align\t6\n.LBB8_480: ; in Loop: Header=BB8_483 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_482\n; %bb.481: ; in Loop: Header=BB8_483 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_483\n\ts_branch .LBB8_485\n\t.p2align\t6\n.LBB8_482:\n\ts_branch .LBB8_485\n.LBB8_483: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_480\n; %bb.484: ; in Loop: Header=BB8_483 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_480\n.LBB8_485:\n\tglobal_load_b64 v[20:21], v[6:7], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_489\n; %bb.486:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[2:3] offset:40\n\tglobal_load_b64 v[7:8], v6, s[2:3] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s4\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_489\n; %bb.487:\n\ts_mov_b32 s0, 0\n.LBB8_488: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_488\n.LBB8_489:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_getpc_b64 s[4:5]\n\ts_add_u32 s4, s4, .str.4@rel32@lo+4\n\ts_addc_u32 s5, s5, .str.4@rel32@hi+12\n\ts_mov_b32 s0, -1\n\ts_cmp_lg_u64 s[4:5], 0\n\ts_cbranch_scc0 .LBB8_568\n; %bb.490:\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v1, v21 :: v_dual_and_b32 v0, -3, v20\n\tv_mov_b32_e32 v25, 0\n\ts_mov_b64 s[6:7], 3\n\ts_branch .LBB8_492\n.LBB8_491: ; in Loop: Header=BB8_492 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_sub_u32 s6, s6, s8\n\ts_subb_u32 s7, s7, s9\n\ts_add_u32 s4, s4, s8\n\ts_addc_u32 s5, s5, s9\n\ts_cmp_eq_u64 s[6:7], 0\n\ts_cbranch_scc1 .LBB8_567\n.LBB8_492: ; =>This Loop Header: Depth=1\n ; Child Loop BB8_495 Depth 2\n ; Child Loop BB8_502 Depth 2\n ; Child Loop BB8_509 Depth 2\n ; Child Loop BB8_516 Depth 2\n ; Child Loop BB8_523 Depth 2\n ; Child Loop BB8_530 Depth 2\n ; Child Loop BB8_537 Depth 2\n ; Child Loop BB8_544 Depth 2\n ; Child Loop BB8_552 Depth 2\n ; Child Loop BB8_561 Depth 2\n ; Child Loop BB8_566 Depth 2\n\tv_cmp_lt_u64_e64 s0, s[6:7], 56\n ; implicit-def: $sgpr15\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b32 s0, s0, exec_lo\n\ts_cselect_b32 s8, s6, 56\n\ts_cselect_b32 s9, s7, 0\n\ts_cmp_gt_u32 s8, 7\n\ts_mov_b32 s0, -1\n\ts_cbranch_scc1 .LBB8_497\n; %bb.493: ; in Loop: Header=BB8_492 Depth=1\n\tv_mov_b32_e32 v2, 0\n\tv_mov_b32_e32 v3, 0\n\ts_cmp_eq_u32 s8, 0\n\ts_cbranch_scc1 .LBB8_496\n; %bb.494: ; in Loop: Header=BB8_492 Depth=1\n\ts_lshl_b64 s[0:1], s[8:9], 3\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], s[4:5]\n.LBB8_495: ; Parent Loop BB8_492 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v4, v25, s[12:13]\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[4:5], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_add_u32 s12, s12, 1\n\ts_addc_u32 s13, s13, 0\n\ts_cmp_lg_u32 s0, s10\n\tv_or_b32_e32 v2, v4, v2\n\tv_or_b32_e32 v3, v5, v3\n\ts_cbranch_scc1 .LBB8_495\n.LBB8_496: ; in Loop: Header=BB8_492 Depth=1\n\ts_mov_b32 s0, 0\n\ts_mov_b32 s15, 0\n.LBB8_497: ; in Loop: Header=BB8_492 Depth=1\n\ts_and_not1_b32 vcc_lo, exec_lo, s0\n\ts_mov_b64 s[0:1], s[4:5]\n\ts_cbranch_vccnz .LBB8_499\n; %bb.498: ; in Loop: Header=BB8_492 Depth=1\n\tglobal_load_b64 v[2:3], v25, s[4:5]\n\ts_add_i32 s15, s8, -8\n\ts_add_u32 s0, s4, 8\n\ts_addc_u32 s1, s5, 0\n.LBB8_499: ; in Loop: Header=BB8_492 Depth=1\n\ts_cmp_gt_u32 s15, 7\n\ts_cbranch_scc1 .LBB8_504\n; %bb.500: ; in Loop: Header=BB8_492 Depth=1\n\tv_mov_b32_e32 v4, 0\n\tv_mov_b32_e32 v5, 0\n\ts_cmp_eq_u32 s15, 0\n\ts_cbranch_scc1 .LBB8_503\n; %bb.501: ; in Loop: Header=BB8_492 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_502: ; Parent Loop BB8_492 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s18, s0, s12\n\ts_addc_u32 s19, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v6, v25, s[18:19]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[6:7], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s15, s12\n\tv_or_b32_e32 v4, v6, v4\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v5, v7, v5\n\ts_cbranch_scc1 .LBB8_502\n.LBB8_503: ; in Loop: Header=BB8_492 Depth=1\n\ts_mov_b32 s14, 0\n\ts_cbranch_execz .LBB8_505\n\ts_branch .LBB8_506\n.LBB8_504: ; in Loop: Header=BB8_492 Depth=1\n ; implicit-def: $vgpr4_vgpr5\n ; implicit-def: $sgpr14\n.LBB8_505: ; in Loop: Header=BB8_492 Depth=1\n\tglobal_load_b64 v[4:5], v25, s[0:1]\n\ts_add_i32 s14, s15, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_506: ; in Loop: Header=BB8_492 Depth=1\n\ts_cmp_gt_u32 s14, 7\n\ts_cbranch_scc1 .LBB8_511\n; %bb.507: ; in Loop: Header=BB8_492 Depth=1\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\ts_cmp_eq_u32 s14, 0\n\ts_cbranch_scc1 .LBB8_510\n; %bb.508: ; in Loop: Header=BB8_492 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_509: ; Parent Loop BB8_492 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s18, s0, s12\n\ts_addc_u32 s19, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v8, v25, s[18:19]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v8\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[8:9], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s14, s12\n\tv_or_b32_e32 v6, v8, v6\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v7, v9, v7\n\ts_cbranch_scc1 .LBB8_509\n.LBB8_510: ; in Loop: Header=BB8_492 Depth=1\n\ts_mov_b32 s15, 0\n\ts_cbranch_execz .LBB8_512\n\ts_branch .LBB8_513\n.LBB8_511: ; in Loop: Header=BB8_492 Depth=1\n ; implicit-def: $sgpr15\n.LBB8_512: ; in Loop: Header=BB8_492 Depth=1\n\tglobal_load_b64 v[6:7], v25, s[0:1]\n\ts_add_i32 s15, s14, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_513: ; in Loop: Header=BB8_492 Depth=1\n\ts_cmp_gt_u32 s15, 7\n\ts_cbranch_scc1 .LBB8_518\n; %bb.514: ; in Loop: Header=BB8_492 Depth=1\n\tv_mov_b32_e32 v8, 0\n\tv_mov_b32_e32 v9, 0\n\ts_cmp_eq_u32 s15, 0\n\ts_cbranch_scc1 .LBB8_517\n; %bb.515: ; in Loop: Header=BB8_492 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_516: ; Parent Loop BB8_492 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s18, s0, s12\n\ts_addc_u32 s19, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v10, v25, s[18:19]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v10\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[10:11], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s15, s12\n\tv_or_b32_e32 v8, v10, v8\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v9, v11, v9\n\ts_cbranch_scc1 .LBB8_516\n.LBB8_517: ; in Loop: Header=BB8_492 Depth=1\n\ts_mov_b32 s14, 0\n\ts_cbranch_execz .LBB8_519\n\ts_branch .LBB8_520\n.LBB8_518: ; in Loop: Header=BB8_492 Depth=1\n ; implicit-def: $vgpr8_vgpr9\n ; implicit-def: $sgpr14\n.LBB8_519: ; in Loop: Header=BB8_492 Depth=1\n\tglobal_load_b64 v[8:9], v25, s[0:1]\n\ts_add_i32 s14, s15, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_520: ; in Loop: Header=BB8_492 Depth=1\n\ts_cmp_gt_u32 s14, 7\n\ts_cbranch_scc1 .LBB8_525\n; %bb.521: ; in Loop: Header=BB8_492 Depth=1\n\tv_mov_b32_e32 v10, 0\n\tv_mov_b32_e32 v11, 0\n\ts_cmp_eq_u32 s14, 0\n\ts_cbranch_scc1 .LBB8_524\n; %bb.522: ; in Loop: Header=BB8_492 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_523: ; Parent Loop BB8_492 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s18, s0, s12\n\ts_addc_u32 s19, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v12, v25, s[18:19]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v12\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[12:13], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s14, s12\n\tv_or_b32_e32 v10, v12, v10\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v11, v13, v11\n\ts_cbranch_scc1 .LBB8_523\n.LBB8_524: ; in Loop: Header=BB8_492 Depth=1\n\ts_mov_b32 s15, 0\n\ts_cbranch_execz .LBB8_526\n\ts_branch .LBB8_527\n.LBB8_525: ; in Loop: Header=BB8_492 Depth=1\n ; implicit-def: $sgpr15\n.LBB8_526: ; in Loop: Header=BB8_492 Depth=1\n\tglobal_load_b64 v[10:11], v25, s[0:1]\n\ts_add_i32 s15, s14, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_527: ; in Loop: Header=BB8_492 Depth=1\n\ts_cmp_gt_u32 s15, 7\n\ts_cbranch_scc1 .LBB8_532\n; %bb.528: ; in Loop: Header=BB8_492 Depth=1\n\tv_mov_b32_e32 v12, 0\n\tv_mov_b32_e32 v13, 0\n\ts_cmp_eq_u32 s15, 0\n\ts_cbranch_scc1 .LBB8_531\n; %bb.529: ; in Loop: Header=BB8_492 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_530: ; Parent Loop BB8_492 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s18, s0, s12\n\ts_addc_u32 s19, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v14, v25, s[18:19]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v14\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[14:15], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s15, s12\n\tv_or_b32_e32 v12, v14, v12\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v13, v15, v13\n\ts_cbranch_scc1 .LBB8_530\n.LBB8_531: ; in Loop: Header=BB8_492 Depth=1\n\ts_mov_b32 s14, 0\n\ts_cbranch_execz .LBB8_533\n\ts_branch .LBB8_534\n.LBB8_532: ; in Loop: Header=BB8_492 Depth=1\n ; implicit-def: $vgpr12_vgpr13\n ; implicit-def: $sgpr14\n.LBB8_533: ; in Loop: Header=BB8_492 Depth=1\n\tglobal_load_b64 v[12:13], v25, s[0:1]\n\ts_add_i32 s14, s15, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_534: ; in Loop: Header=BB8_492 Depth=1\n\ts_cmp_gt_u32 s14, 7\n\ts_cbranch_scc1 .LBB8_539\n; %bb.535: ; in Loop: Header=BB8_492 Depth=1\n\tv_mov_b32_e32 v14, 0\n\tv_mov_b32_e32 v15, 0\n\ts_cmp_eq_u32 s14, 0\n\ts_cbranch_scc1 .LBB8_538\n; %bb.536: ; in Loop: Header=BB8_492 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], s[0:1]\n.LBB8_537: ; Parent Loop BB8_492 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v16, v25, s[12:13]\n\ts_add_i32 s14, s14, -1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v16\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[16:17], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_add_u32 s12, s12, 1\n\ts_addc_u32 s13, s13, 0\n\ts_cmp_lg_u32 s14, 0\n\tv_or_b32_e32 v14, v16, v14\n\tv_or_b32_e32 v15, v17, v15\n\ts_cbranch_scc1 .LBB8_537\n.LBB8_538: ; in Loop: Header=BB8_492 Depth=1\n\ts_cbranch_execz .LBB8_540\n\ts_branch .LBB8_541\n.LBB8_539: ; in Loop: Header=BB8_492 Depth=1\n.LBB8_540: ; in Loop: Header=BB8_492 Depth=1\n\tglobal_load_b64 v[14:15], v25, s[0:1]\n.LBB8_541: ; in Loop: Header=BB8_492 Depth=1\n\tv_mov_b32_e32 v24, v23\n\tv_mov_b32_e32 v26, 0\n\tv_mov_b32_e32 v27, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v24\n\tv_cmp_eq_u32_e64 s0, s0, v24\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_547\n; %bb.542: ; in Loop: Header=BB8_492 Depth=1\n\tglobal_load_b64 v[18:19], v25, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[16:17], v25, s[2:3] offset:40\n\tglobal_load_b64 v[26:27], v25, s[2:3]\n\ts_mov_b32 s10, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v17, v17, v19\n\tv_and_b32_e32 v16, v16, v18\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v17, v17, 24\n\tv_mul_hi_u32 v22, v16, 24\n\tv_mul_lo_u32 v16, v16, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v17, v22, v17\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v16, vcc_lo, v26, v16\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo\n\tglobal_load_b64 v[16:17], v[16:17], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[26:27], v[18:19]\n\ts_cbranch_execz .LBB8_546\n; %bb.543: ; in Loop: Header=BB8_492 Depth=1\n\ts_mov_b32 s11, 0\n\t.p2align\t6\n.LBB8_544: ; Parent Loop BB8_492 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[16:17], v25, s[2:3] offset:40\n\tglobal_load_b64 v[28:29], v25, s[2:3]\n\tv_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v16, v16, v18\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19\n\tv_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]\n\tglobal_load_b64 v[16:17], v[26:27], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]\n\ts_or_b32 s11, vcc_lo, s11\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s11\n\ts_cbranch_execnz .LBB8_544\n; %bb.545: ; in Loop: Header=BB8_492 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s11\n.LBB8_546: ; in Loop: Header=BB8_492 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s10\n.LBB8_547: ; in Loop: Header=BB8_492 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_clause 0x1\n\tglobal_load_b64 v[28:29], v25, s[2:3] offset:40\n\tglobal_load_b128 v[16:19], v25, s[2:3]\n\tv_readfirstlane_b32 s10, v26\n\tv_readfirstlane_b32 s11, v27\n\ts_mov_b32 s14, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s12, v28\n\tv_readfirstlane_b32 s13, v29\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[12:13], s[10:11], s[12:13]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_549\n; %bb.548: ; in Loop: Header=BB8_492 Depth=1\n\tv_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0\n\ts_mul_i32 s14, s13, 24\n\ts_mul_hi_u32 s15, s12, 24\n\tv_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1\n\ts_add_i32 s15, s15, s14\n\ts_mul_i32 s14, s12, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v30, vcc_lo, v16, s14\n\tv_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo\n\tglobal_store_b128 v[30:31], v[26:29], off offset:8\n.LBB8_549: ; in Loop: Header=BB8_492 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_cmp_gt_u64_e64 vcc_lo, s[6:7], 56\n\tv_or_b32_e32 v22, 2, v0\n\ts_lshl_b64 s[14:15], s[12:13], 12\n\tv_lshlrev_b64 v[26:27], 6, v[24:25]\n\ts_lshl_b32 s1, s8, 2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_i32 s1, s1, 28\n\tv_cndmask_b32_e32 v0, v22, v0, vcc_lo\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v18, vcc_lo, v18, s14\n\tv_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo\n\ts_and_b32 s1, s1, 0x1e0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v18, vcc_lo, v18, v26\n\tv_and_or_b32 v0, v0, 0xffffff1f, s1\n\tv_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo\n\ts_clause 0x3\n\tglobal_store_b128 v[18:19], v[0:3], off\n\tglobal_store_b128 v[18:19], v[4:7], off offset:16\n\tglobal_store_b128 v[18:19], v[8:11], off offset:32\n\tglobal_store_b128 v[18:19], v[12:15], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_557\n; %bb.550: ; in Loop: Header=BB8_492 Depth=1\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v25, s[2:3] offset:32 glc\n\tglobal_load_b64 v[0:1], v25, s[2:3] offset:40\n\tv_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s14, v0\n\tv_readfirstlane_b32 s15, v1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[14:15], s[14:15], s[10:11]\n\ts_mul_i32 s15, s15, 24\n\ts_mul_hi_u32 s17, s14, 24\n\ts_mul_i32 s14, s14, 24\n\ts_add_i32 s17, s17, s15\n\tv_add_co_u32 v4, vcc_lo, v16, s14\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s17, v17, vcc_lo\n\ts_mov_b32 s14, exec_lo\n\tglobal_store_b64 v[4:5], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[2:3], v[8:9]\n\ts_cbranch_execz .LBB8_553\n; %bb.551: ; in Loop: Header=BB8_492 Depth=1\n\ts_mov_b32 s15, 0\n.LBB8_552: ; Parent Loop BB8_492 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]\n\tv_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0\n\ts_or_b32 s15, vcc_lo, s15\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s15\n\ts_cbranch_execnz .LBB8_552\n.LBB8_553: ; in Loop: Header=BB8_492 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s14\n\tglobal_load_b64 v[0:1], v25, s[2:3] offset:16\n\ts_mov_b32 s15, exec_lo\n\ts_mov_b32 s14, exec_lo\n\tv_mbcnt_lo_u32_b32 v2, s15, 0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_eq_u32_e32 0, v2\n\ts_cbranch_execz .LBB8_555\n; %bb.554: ; in Loop: Header=BB8_492 Depth=1\n\ts_bcnt1_i32_b32 s15, s15\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off offset:8\n.LBB8_555: ; in Loop: Header=BB8_492 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s14\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\ts_cbranch_vccnz .LBB8_557\n; %bb.556: ; in Loop: Header=BB8_492 Depth=1\n\tglobal_load_b32 v24, v[0:1], off offset:24\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s14, v24\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[2:3], v[24:25], off\n\ts_and_b32 m0, s14, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_557: ; in Loop: Header=BB8_492 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s13, 24\n\ts_mul_hi_u32 s13, s12, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s13, s13, s1\n\ts_mul_i32 s1, s12, 24\n\tv_add_co_u32 v0, vcc_lo, v16, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_561\n\t.p2align\t6\n.LBB8_558: ; in Loop: Header=BB8_561 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_560\n; %bb.559: ; in Loop: Header=BB8_561 Depth=2\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_561\n\ts_branch .LBB8_563\n\t.p2align\t6\n.LBB8_560: ; in Loop: Header=BB8_492 Depth=1\n\ts_branch .LBB8_563\n.LBB8_561: ; Parent Loop BB8_492 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_558\n; %bb.562: ; in Loop: Header=BB8_561 Depth=2\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_558\n.LBB8_563: ; in Loop: Header=BB8_492 Depth=1\n\tglobal_load_b64 v[0:1], v[18:19], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_491\n; %bb.564: ; in Loop: Header=BB8_492 Depth=1\n\ts_clause 0x2\n\tglobal_load_b64 v[4:5], v25, s[2:3] offset:40\n\tglobal_load_b64 v[8:9], v25, s[2:3] offset:24 glc\n\tglobal_load_b64 v[6:7], v25, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v10, vcc_lo, v4, 1\n\tv_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, v10, s10\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\tv_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10\n\tv_and_b32_e32 v5, v3, v5\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v4, v2, v4\n\tv_mul_hi_u32 v10, v4, 24\n\tv_mul_lo_u32 v4, v4, 24\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_add_co_u32 v6, vcc_lo, v6, v4\n\tv_mov_b32_e32 v4, v8\n\tv_mul_lo_u32 v5, v5, 24\n\tv_add_nc_u32_e32 v5, v10, v5\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v5, v9\n\tglobal_store_b64 v[6:7], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_491\n; %bb.565: ; in Loop: Header=BB8_492 Depth=1\n\ts_mov_b32 s0, 0\n.LBB8_566: ; Parent Loop BB8_492 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]\n\tv_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_566\n\ts_branch .LBB8_491\n.LBB8_567:\n\ts_mov_b32 s0, 0\n.LBB8_568:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_b32 vcc_lo, exec_lo, s0\n\ts_cbranch_vccz .LBB8_596\n; %bb.569:\n\t;;#ASMSTART\n\t;;#ASMEND\n\tv_readfirstlane_b32 s0, v23\n\tv_mov_b32_e32 v4, 0\n\tv_mov_b32_e32 v5, 0\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u32_e64 s0, s0, v23\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_575\n; %bb.570:\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s4, exec_lo\n\tglobal_load_b64 v[6:7], v0, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[2:3] offset:40\n\tglobal_load_b64 v[3:4], v0, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v6\n\tv_and_b32_e32 v2, v2, v7\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v5, v1, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v5, v2\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, v3, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo\n\tglobal_load_b64 v[4:5], v[1:2], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[4:5], v[6:7]\n\ts_cbranch_execz .LBB8_574\n; %bb.571:\n\ts_mov_b32 s5, 0\n\t.p2align\t6\n.LBB8_572: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[2:3] offset:40\n\tglobal_load_b64 v[8:9], v0, s[2:3]\n\tv_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v1, v1, v6\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7\n\tv_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]\n\tglobal_load_b64 v[4:5], v[3:4], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]\n\ts_or_b32 s5, vcc_lo, s5\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s5\n\ts_cbranch_execnz .LBB8_572\n; %bb.573:\n\ts_or_b32 exec_lo, exec_lo, s5\n.LBB8_574:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s4\n.LBB8_575:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v24, 0\n\tv_readfirstlane_b32 s4, v4\n\tv_readfirstlane_b32 s5, v5\n\ts_mov_b32 s8, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[6:7], v24, s[2:3] offset:40\n\tglobal_load_b128 v[0:3], v24, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s6, v6\n\tv_readfirstlane_b32 s7, v7\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[6:7], s[4:5], s[6:7]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_577\n; %bb.576:\n\tv_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0\n\ts_mul_i32 s8, s7, 24\n\ts_mul_hi_u32 s9, s6, 24\n\tv_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1\n\ts_add_i32 s9, s9, s8\n\ts_mul_i32 s8, s6, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v8, vcc_lo, v0, s8\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo\n\tglobal_store_b128 v[8:9], v[4:7], off offset:8\n.LBB8_577:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[8:9], s[6:7], 12\n\tv_and_or_b32 v20, v20, 0xffffff1d, 34\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v4, vcc_lo, v2, s8\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo\n\tv_lshlrev_b64 v[2:3], 6, v[23:24]\n\ts_mov_b32 s8, 0\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_add_co_u32 v8, vcc_lo, v4, v2\n\tv_mov_b32_e32 v6, 0\n\tv_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo\n\tv_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11\n\tv_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10\n\ts_delay_alu instid0(VALU_DEP_4)\n\tv_mov_b32_e32 v7, v6\n\ts_clause 0x4\n\tglobal_store_b64 v[8:9], v[20:21], off\n\tglobal_store_b128 v[8:9], v[2:5], off offset:8\n\tglobal_store_b128 v[8:9], v[2:5], off offset:24\n\tglobal_store_b128 v[8:9], v[2:5], off offset:40\n\tglobal_store_b64 v[8:9], v[6:7], off offset:56\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_585\n; %bb.578:\n\tv_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4\n\tv_mov_b32_e32 v10, s5\n\ts_clause 0x1\n\tglobal_load_b64 v[11:12], v8, s[2:3] offset:32 glc\n\tglobal_load_b64 v[2:3], v8, s[2:3] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s8, v2\n\tv_readfirstlane_b32 s9, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[8:9], s[8:9], s[4:5]\n\ts_mul_i32 s9, s9, 24\n\ts_mul_hi_u32 s10, s8, 24\n\ts_mul_i32 s8, s8, 24\n\ts_add_i32 s10, s10, s9\n\tv_add_co_u32 v6, vcc_lo, v0, s8\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo\n\ts_mov_b32 s8, exec_lo\n\tglobal_store_b64 v[6:7], v[11:12], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[11:12]\n\ts_cbranch_execz .LBB8_581\n; %bb.579:\n\ts_mov_b32 s9, 0\n.LBB8_580: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s9, vcc_lo, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s9\n\ts_cbranch_execnz .LBB8_580\n.LBB8_581:\n\ts_or_b32 exec_lo, exec_lo, s8\n\tv_mov_b32_e32 v2, 0\n\ts_mov_b32 s9, exec_lo\n\ts_mov_b32 s8, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s9, 0\n\tglobal_load_b64 v[2:3], v2, s[2:3] offset:16\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_583\n; %bb.582:\n\ts_bcnt1_i32_b32 s9, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_583:\n\ts_or_b32 exec_lo, exec_lo, s8\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_585\n; %bb.584:\n\tglobal_load_b32 v2, v[2:3], off offset:24\n\tv_mov_b32_e32 v3, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s8, v2\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_and_b32 m0, s8, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_585:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s7, 24\n\ts_mul_hi_u32 s7, s6, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s7, s7, s1\n\ts_mul_i32 s1, s6, 24\n\tv_add_co_u32 v0, vcc_lo, v0, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_589\n\t.p2align\t6\n.LBB8_586: ; in Loop: Header=BB8_589 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_588\n; %bb.587: ; in Loop: Header=BB8_589 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_589\n\ts_branch .LBB8_591\n\t.p2align\t6\n.LBB8_588:\n\ts_branch .LBB8_591\n.LBB8_589: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_586\n; %bb.590: ; in Loop: Header=BB8_589 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_586\n.LBB8_591:\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_595\n; %bb.592:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[2:3] offset:40\n\tglobal_load_b64 v[7:8], v6, s[2:3] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s4\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_595\n; %bb.593:\n\ts_mov_b32 s0, 0\n.LBB8_594: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_594\n.LBB8_595:\n\ts_or_b32 exec_lo, exec_lo, s1\n ; implicit-def: $vgpr23\n.LBB8_596:\n\ts_and_not1_saveexec_b32 s14, s16\n\ts_cbranch_execz .LBB8_730\n; %bb.597:\n\tv_mov_b32_e32 v4, v23\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v4\n\tv_cmp_eq_u32_e64 s0, s0, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_603\n; %bb.598:\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s4, exec_lo\n\ts_waitcnt lgkmcnt(0)\n\tglobal_load_b64 v[8:9], v0, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[2:3] offset:40\n\tglobal_load_b64 v[5:6], v0, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v2, v2, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v3, v1, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v3, v2\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, v5, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo\n\tglobal_load_b64 v[6:7], v[1:2], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[6:7], v[8:9]\n\ts_cbranch_execz .LBB8_602\n; %bb.599:\n\ts_mov_b32 s5, 0\n\t.p2align\t6\n.LBB8_600: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[2:3] offset:40\n\tglobal_load_b64 v[10:11], v0, s[2:3]\n\tv_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v7, v2, v9\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]\n\tv_mov_b32_e32 v1, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]\n\tv_mov_b32_e32 v6, v2\n\tglobal_load_b64 v[6:7], v[5:6], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]\n\ts_or_b32 s5, vcc_lo, s5\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s5\n\ts_cbranch_execnz .LBB8_600\n; %bb.601:\n\ts_or_b32 exec_lo, exec_lo, s5\n.LBB8_602:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s4\n.LBB8_603:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v5, 0\n\tv_readfirstlane_b32 s4, v6\n\tv_readfirstlane_b32 s5, v7\n\ts_mov_b32 s8, exec_lo\n\ts_waitcnt lgkmcnt(0)\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v5, s[2:3] offset:40\n\tglobal_load_b128 v[0:3], v5, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s6, v8\n\tv_readfirstlane_b32 s7, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[6:7], s[4:5], s[6:7]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_605\n; %bb.604:\n\tv_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0\n\ts_mul_i32 s8, s7, 24\n\ts_mul_hi_u32 s9, s6, 24\n\tv_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1\n\ts_add_i32 s9, s9, s8\n\ts_mul_i32 s8, s6, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v10, vcc_lo, v0, s8\n\tv_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo\n\tglobal_store_b128 v[10:11], v[6:9], off offset:8\n.LBB8_605:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[8:9], s[6:7], 12\n\tv_lshlrev_b64 v[4:5], 6, v[4:5]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v2, vcc_lo, v2, s8\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo\n\tv_mov_b32_e32 v3, 0\n\ts_mov_b32 s8, 0\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_add_co_u32 v6, vcc_lo, v2, v4\n\tv_mov_b32_e32 v2, 33\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v4, v3\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8\n\tv_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10\n\tv_mov_b32_e32 v11, s11\n\ts_clause 0x3\n\tglobal_store_b128 v[6:7], v[2:5], off\n\tglobal_store_b128 v[6:7], v[8:11], off offset:16\n\tglobal_store_b128 v[6:7], v[8:11], off offset:32\n\tglobal_store_b128 v[6:7], v[8:11], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_613\n; %bb.606:\n\tv_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4\n\tv_mov_b32_e32 v12, s5\n\ts_clause 0x1\n\tglobal_load_b64 v[13:14], v10, s[2:3] offset:32 glc\n\tglobal_load_b64 v[2:3], v10, s[2:3] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s8, v2\n\tv_readfirstlane_b32 s9, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[8:9], s[8:9], s[4:5]\n\ts_mul_i32 s9, s9, 24\n\ts_mul_hi_u32 s10, s8, 24\n\ts_mul_i32 s8, s8, 24\n\ts_add_i32 s10, s10, s9\n\tv_add_co_u32 v8, vcc_lo, v0, s8\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo\n\ts_mov_b32 s8, exec_lo\n\tglobal_store_b64 v[8:9], v[13:14], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[13:14]\n\ts_cbranch_execz .LBB8_609\n; %bb.607:\n\ts_mov_b32 s9, 0\n.LBB8_608: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5\n\ts_sleep 1\n\tglobal_store_b64 v[8:9], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s9, vcc_lo, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s9\n\ts_cbranch_execnz .LBB8_608\n.LBB8_609:\n\ts_or_b32 exec_lo, exec_lo, s8\n\tv_mov_b32_e32 v2, 0\n\ts_mov_b32 s9, exec_lo\n\ts_mov_b32 s8, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s9, 0\n\tglobal_load_b64 v[2:3], v2, s[2:3] offset:16\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_611\n; %bb.610:\n\ts_bcnt1_i32_b32 s9, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_611:\n\ts_or_b32 exec_lo, exec_lo, s8\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_613\n; %bb.612:\n\tglobal_load_b32 v2, v[2:3], off offset:24\n\tv_mov_b32_e32 v3, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s8, v2\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_and_b32 m0, s8, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_613:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s7, 24\n\ts_mul_hi_u32 s7, s6, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s7, s7, s1\n\ts_mul_i32 s1, s6, 24\n\tv_add_co_u32 v0, vcc_lo, v0, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_617\n\t.p2align\t6\n.LBB8_614: ; in Loop: Header=BB8_617 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_616\n; %bb.615: ; in Loop: Header=BB8_617 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_617\n\ts_branch .LBB8_619\n\t.p2align\t6\n.LBB8_616:\n\ts_branch .LBB8_619\n.LBB8_617: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_614\n; %bb.618: ; in Loop: Header=BB8_617 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_614\n.LBB8_619:\n\tglobal_load_b64 v[20:21], v[6:7], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_623\n; %bb.620:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[2:3] offset:40\n\tglobal_load_b64 v[7:8], v6, s[2:3] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s4\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_623\n; %bb.621:\n\ts_mov_b32 s0, 0\n.LBB8_622: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_622\n.LBB8_623:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_getpc_b64 s[4:5]\n\ts_add_u32 s4, s4, .str@rel32@lo+4\n\ts_addc_u32 s5, s5, .str@rel32@hi+12\n\ts_mov_b32 s0, -1\n\ts_cmp_lg_u64 s[4:5], 0\n\ts_cbranch_scc0 .LBB8_702\n; %bb.624:\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v1, v21 :: v_dual_and_b32 v0, -3, v20\n\tv_mov_b32_e32 v25, 0\n\ts_mov_b64 s[6:7], 26\n\ts_branch .LBB8_626\n.LBB8_625: ; in Loop: Header=BB8_626 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_sub_u32 s6, s6, s8\n\ts_subb_u32 s7, s7, s9\n\ts_add_u32 s4, s4, s8\n\ts_addc_u32 s5, s5, s9\n\ts_cmp_eq_u64 s[6:7], 0\n\ts_cbranch_scc1 .LBB8_701\n.LBB8_626: ; =>This Loop Header: Depth=1\n ; Child Loop BB8_629 Depth 2\n ; Child Loop BB8_636 Depth 2\n ; Child Loop BB8_643 Depth 2\n ; Child Loop BB8_650 Depth 2\n ; Child Loop BB8_657 Depth 2\n ; Child Loop BB8_664 Depth 2\n ; Child Loop BB8_671 Depth 2\n ; Child Loop BB8_678 Depth 2\n ; Child Loop BB8_686 Depth 2\n ; Child Loop BB8_695 Depth 2\n ; Child Loop BB8_700 Depth 2\n\tv_cmp_lt_u64_e64 s0, s[6:7], 56\n ; implicit-def: $sgpr16\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b32 s0, s0, exec_lo\n\ts_cselect_b32 s8, s6, 56\n\ts_cselect_b32 s9, s7, 0\n\ts_cmp_gt_u32 s8, 7\n\ts_mov_b32 s0, -1\n\ts_cbranch_scc1 .LBB8_631\n; %bb.627: ; in Loop: Header=BB8_626 Depth=1\n\tv_mov_b32_e32 v2, 0\n\tv_mov_b32_e32 v3, 0\n\ts_cmp_eq_u32 s8, 0\n\ts_cbranch_scc1 .LBB8_630\n; %bb.628: ; in Loop: Header=BB8_626 Depth=1\n\ts_lshl_b64 s[0:1], s[8:9], 3\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], s[4:5]\n.LBB8_629: ; Parent Loop BB8_626 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v4, v25, s[12:13]\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[4:5], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_add_u32 s12, s12, 1\n\ts_addc_u32 s13, s13, 0\n\ts_cmp_lg_u32 s0, s10\n\tv_or_b32_e32 v2, v4, v2\n\tv_or_b32_e32 v3, v5, v3\n\ts_cbranch_scc1 .LBB8_629\n.LBB8_630: ; in Loop: Header=BB8_626 Depth=1\n\ts_mov_b32 s0, 0\n\ts_mov_b32 s16, 0\n.LBB8_631: ; in Loop: Header=BB8_626 Depth=1\n\ts_and_not1_b32 vcc_lo, exec_lo, s0\n\ts_mov_b64 s[0:1], s[4:5]\n\ts_cbranch_vccnz .LBB8_633\n; %bb.632: ; in Loop: Header=BB8_626 Depth=1\n\tglobal_load_b64 v[2:3], v25, s[4:5]\n\ts_add_i32 s16, s8, -8\n\ts_add_u32 s0, s4, 8\n\ts_addc_u32 s1, s5, 0\n.LBB8_633: ; in Loop: Header=BB8_626 Depth=1\n\ts_cmp_gt_u32 s16, 7\n\ts_cbranch_scc1 .LBB8_638\n; %bb.634: ; in Loop: Header=BB8_626 Depth=1\n\tv_mov_b32_e32 v4, 0\n\tv_mov_b32_e32 v5, 0\n\ts_cmp_eq_u32 s16, 0\n\ts_cbranch_scc1 .LBB8_637\n; %bb.635: ; in Loop: Header=BB8_626 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_636: ; Parent Loop BB8_626 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s18, s0, s12\n\ts_addc_u32 s19, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v6, v25, s[18:19]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[6:7], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s16, s12\n\tv_or_b32_e32 v4, v6, v4\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v5, v7, v5\n\ts_cbranch_scc1 .LBB8_636\n.LBB8_637: ; in Loop: Header=BB8_626 Depth=1\n\ts_mov_b32 s15, 0\n\ts_cbranch_execz .LBB8_639\n\ts_branch .LBB8_640\n.LBB8_638: ; in Loop: Header=BB8_626 Depth=1\n ; implicit-def: $vgpr4_vgpr5\n ; implicit-def: $sgpr15\n.LBB8_639: ; in Loop: Header=BB8_626 Depth=1\n\tglobal_load_b64 v[4:5], v25, s[0:1]\n\ts_add_i32 s15, s16, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_640: ; in Loop: Header=BB8_626 Depth=1\n\ts_cmp_gt_u32 s15, 7\n\ts_cbranch_scc1 .LBB8_645\n; %bb.641: ; in Loop: Header=BB8_626 Depth=1\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\ts_cmp_eq_u32 s15, 0\n\ts_cbranch_scc1 .LBB8_644\n; %bb.642: ; in Loop: Header=BB8_626 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_643: ; Parent Loop BB8_626 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s16, s0, s12\n\ts_addc_u32 s17, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v8, v25, s[16:17]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v8\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[8:9], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s15, s12\n\tv_or_b32_e32 v6, v8, v6\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v7, v9, v7\n\ts_cbranch_scc1 .LBB8_643\n.LBB8_644: ; in Loop: Header=BB8_626 Depth=1\n\ts_mov_b32 s16, 0\n\ts_cbranch_execz .LBB8_646\n\ts_branch .LBB8_647\n.LBB8_645: ; in Loop: Header=BB8_626 Depth=1\n ; implicit-def: $sgpr16\n.LBB8_646: ; in Loop: Header=BB8_626 Depth=1\n\tglobal_load_b64 v[6:7], v25, s[0:1]\n\ts_add_i32 s16, s15, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_647: ; in Loop: Header=BB8_626 Depth=1\n\ts_cmp_gt_u32 s16, 7\n\ts_cbranch_scc1 .LBB8_652\n; %bb.648: ; in Loop: Header=BB8_626 Depth=1\n\tv_mov_b32_e32 v8, 0\n\tv_mov_b32_e32 v9, 0\n\ts_cmp_eq_u32 s16, 0\n\ts_cbranch_scc1 .LBB8_651\n; %bb.649: ; in Loop: Header=BB8_626 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_650: ; Parent Loop BB8_626 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s18, s0, s12\n\ts_addc_u32 s19, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v10, v25, s[18:19]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v10\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[10:11], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s16, s12\n\tv_or_b32_e32 v8, v10, v8\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v9, v11, v9\n\ts_cbranch_scc1 .LBB8_650\n.LBB8_651: ; in Loop: Header=BB8_626 Depth=1\n\ts_mov_b32 s15, 0\n\ts_cbranch_execz .LBB8_653\n\ts_branch .LBB8_654\n.LBB8_652: ; in Loop: Header=BB8_626 Depth=1\n ; implicit-def: $vgpr8_vgpr9\n ; implicit-def: $sgpr15\n.LBB8_653: ; in Loop: Header=BB8_626 Depth=1\n\tglobal_load_b64 v[8:9], v25, s[0:1]\n\ts_add_i32 s15, s16, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_654: ; in Loop: Header=BB8_626 Depth=1\n\ts_cmp_gt_u32 s15, 7\n\ts_cbranch_scc1 .LBB8_659\n; %bb.655: ; in Loop: Header=BB8_626 Depth=1\n\tv_mov_b32_e32 v10, 0\n\tv_mov_b32_e32 v11, 0\n\ts_cmp_eq_u32 s15, 0\n\ts_cbranch_scc1 .LBB8_658\n; %bb.656: ; in Loop: Header=BB8_626 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_657: ; Parent Loop BB8_626 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s16, s0, s12\n\ts_addc_u32 s17, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v12, v25, s[16:17]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v12\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[12:13], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s15, s12\n\tv_or_b32_e32 v10, v12, v10\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v11, v13, v11\n\ts_cbranch_scc1 .LBB8_657\n.LBB8_658: ; in Loop: Header=BB8_626 Depth=1\n\ts_mov_b32 s16, 0\n\ts_cbranch_execz .LBB8_660\n\ts_branch .LBB8_661\n.LBB8_659: ; in Loop: Header=BB8_626 Depth=1\n ; implicit-def: $sgpr16\n.LBB8_660: ; in Loop: Header=BB8_626 Depth=1\n\tglobal_load_b64 v[10:11], v25, s[0:1]\n\ts_add_i32 s16, s15, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_661: ; in Loop: Header=BB8_626 Depth=1\n\ts_cmp_gt_u32 s16, 7\n\ts_cbranch_scc1 .LBB8_666\n; %bb.662: ; in Loop: Header=BB8_626 Depth=1\n\tv_mov_b32_e32 v12, 0\n\tv_mov_b32_e32 v13, 0\n\ts_cmp_eq_u32 s16, 0\n\ts_cbranch_scc1 .LBB8_665\n; %bb.663: ; in Loop: Header=BB8_626 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB8_664: ; Parent Loop BB8_626 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s18, s0, s12\n\ts_addc_u32 s19, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v14, v25, s[18:19]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v14\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[14:15], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s16, s12\n\tv_or_b32_e32 v12, v14, v12\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v13, v15, v13\n\ts_cbranch_scc1 .LBB8_664\n.LBB8_665: ; in Loop: Header=BB8_626 Depth=1\n\ts_mov_b32 s15, 0\n\ts_cbranch_execz .LBB8_667\n\ts_branch .LBB8_668\n.LBB8_666: ; in Loop: Header=BB8_626 Depth=1\n ; implicit-def: $vgpr12_vgpr13\n ; implicit-def: $sgpr15\n.LBB8_667: ; in Loop: Header=BB8_626 Depth=1\n\tglobal_load_b64 v[12:13], v25, s[0:1]\n\ts_add_i32 s15, s16, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_668: ; in Loop: Header=BB8_626 Depth=1\n\ts_cmp_gt_u32 s15, 7\n\ts_cbranch_scc1 .LBB8_673\n; %bb.669: ; in Loop: Header=BB8_626 Depth=1\n\tv_mov_b32_e32 v14, 0\n\tv_mov_b32_e32 v15, 0\n\ts_cmp_eq_u32 s15, 0\n\ts_cbranch_scc1 .LBB8_672\n; %bb.670: ; in Loop: Header=BB8_626 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], s[0:1]\n.LBB8_671: ; Parent Loop BB8_626 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v16, v25, s[12:13]\n\ts_add_i32 s15, s15, -1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v24, 0xffff, v16\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[16:17], s10, v[24:25]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_add_u32 s12, s12, 1\n\ts_addc_u32 s13, s13, 0\n\ts_cmp_lg_u32 s15, 0\n\tv_or_b32_e32 v14, v16, v14\n\tv_or_b32_e32 v15, v17, v15\n\ts_cbranch_scc1 .LBB8_671\n.LBB8_672: ; in Loop: Header=BB8_626 Depth=1\n\ts_cbranch_execz .LBB8_674\n\ts_branch .LBB8_675\n.LBB8_673: ; in Loop: Header=BB8_626 Depth=1\n.LBB8_674: ; in Loop: Header=BB8_626 Depth=1\n\tglobal_load_b64 v[14:15], v25, s[0:1]\n.LBB8_675: ; in Loop: Header=BB8_626 Depth=1\n\tv_mov_b32_e32 v24, v23\n\tv_mov_b32_e32 v26, 0\n\tv_mov_b32_e32 v27, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v24\n\tv_cmp_eq_u32_e64 s0, s0, v24\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_681\n; %bb.676: ; in Loop: Header=BB8_626 Depth=1\n\tglobal_load_b64 v[18:19], v25, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[16:17], v25, s[2:3] offset:40\n\tglobal_load_b64 v[26:27], v25, s[2:3]\n\ts_mov_b32 s10, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v17, v17, v19\n\tv_and_b32_e32 v16, v16, v18\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v17, v17, 24\n\tv_mul_hi_u32 v22, v16, 24\n\tv_mul_lo_u32 v16, v16, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v17, v22, v17\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v16, vcc_lo, v26, v16\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo\n\tglobal_load_b64 v[16:17], v[16:17], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[26:27], v[18:19]\n\ts_cbranch_execz .LBB8_680\n; %bb.677: ; in Loop: Header=BB8_626 Depth=1\n\ts_mov_b32 s11, 0\n\t.p2align\t6\n.LBB8_678: ; Parent Loop BB8_626 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[16:17], v25, s[2:3] offset:40\n\tglobal_load_b64 v[28:29], v25, s[2:3]\n\tv_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v16, v16, v18\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19\n\tv_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]\n\tglobal_load_b64 v[16:17], v[26:27], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]\n\ts_or_b32 s11, vcc_lo, s11\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s11\n\ts_cbranch_execnz .LBB8_678\n; %bb.679: ; in Loop: Header=BB8_626 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s11\n.LBB8_680: ; in Loop: Header=BB8_626 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s10\n.LBB8_681: ; in Loop: Header=BB8_626 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_clause 0x1\n\tglobal_load_b64 v[28:29], v25, s[2:3] offset:40\n\tglobal_load_b128 v[16:19], v25, s[2:3]\n\tv_readfirstlane_b32 s10, v26\n\tv_readfirstlane_b32 s11, v27\n\ts_mov_b32 s15, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s12, v28\n\tv_readfirstlane_b32 s13, v29\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[12:13], s[10:11], s[12:13]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_683\n; %bb.682: ; in Loop: Header=BB8_626 Depth=1\n\tv_dual_mov_b32 v26, s15 :: v_dual_mov_b32 v27, 0\n\ts_mul_i32 s15, s13, 24\n\ts_mul_hi_u32 s16, s12, 24\n\tv_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1\n\ts_add_i32 s16, s16, s15\n\ts_mul_i32 s15, s12, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v30, vcc_lo, v16, s15\n\tv_add_co_ci_u32_e32 v31, vcc_lo, s16, v17, vcc_lo\n\tglobal_store_b128 v[30:31], v[26:29], off offset:8\n.LBB8_683: ; in Loop: Header=BB8_626 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_cmp_gt_u64_e64 vcc_lo, s[6:7], 56\n\tv_or_b32_e32 v22, 2, v0\n\ts_lshl_b64 s[16:17], s[12:13], 12\n\tv_lshlrev_b64 v[26:27], 6, v[24:25]\n\ts_lshl_b32 s1, s8, 2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_i32 s1, s1, 28\n\tv_cndmask_b32_e32 v0, v22, v0, vcc_lo\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v18, vcc_lo, v18, s16\n\tv_add_co_ci_u32_e32 v19, vcc_lo, s17, v19, vcc_lo\n\ts_and_b32 s1, s1, 0x1e0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v18, vcc_lo, v18, v26\n\tv_and_or_b32 v0, v0, 0xffffff1f, s1\n\tv_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo\n\ts_clause 0x3\n\tglobal_store_b128 v[18:19], v[0:3], off\n\tglobal_store_b128 v[18:19], v[4:7], off offset:16\n\tglobal_store_b128 v[18:19], v[8:11], off offset:32\n\tglobal_store_b128 v[18:19], v[12:15], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_691\n; %bb.684: ; in Loop: Header=BB8_626 Depth=1\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v25, s[2:3] offset:32 glc\n\tglobal_load_b64 v[0:1], v25, s[2:3] offset:40\n\tv_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s16, v0\n\tv_readfirstlane_b32 s17, v1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[16:17], s[16:17], s[10:11]\n\ts_mul_i32 s15, s17, 24\n\ts_mul_hi_u32 s17, s16, 24\n\ts_mul_i32 s16, s16, 24\n\ts_add_i32 s17, s17, s15\n\tv_add_co_u32 v4, vcc_lo, v16, s16\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s17, v17, vcc_lo\n\ts_mov_b32 s15, exec_lo\n\tglobal_store_b64 v[4:5], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[2:3], v[8:9]\n\ts_cbranch_execz .LBB8_687\n; %bb.685: ; in Loop: Header=BB8_626 Depth=1\n\ts_mov_b32 s16, 0\n.LBB8_686: ; Parent Loop BB8_626 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]\n\tv_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0\n\ts_or_b32 s16, vcc_lo, s16\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s16\n\ts_cbranch_execnz .LBB8_686\n.LBB8_687: ; in Loop: Header=BB8_626 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s15\n\tglobal_load_b64 v[0:1], v25, s[2:3] offset:16\n\ts_mov_b32 s16, exec_lo\n\ts_mov_b32 s15, exec_lo\n\tv_mbcnt_lo_u32_b32 v2, s16, 0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_eq_u32_e32 0, v2\n\ts_cbranch_execz .LBB8_689\n; %bb.688: ; in Loop: Header=BB8_626 Depth=1\n\ts_bcnt1_i32_b32 s16, s16\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s16\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off offset:8\n.LBB8_689: ; in Loop: Header=BB8_626 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s15\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\ts_cbranch_vccnz .LBB8_691\n; %bb.690: ; in Loop: Header=BB8_626 Depth=1\n\tglobal_load_b32 v24, v[0:1], off offset:24\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s15, v24\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[2:3], v[24:25], off\n\ts_and_b32 m0, s15, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_691: ; in Loop: Header=BB8_626 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s13, 24\n\ts_mul_hi_u32 s13, s12, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s13, s13, s1\n\ts_mul_i32 s1, s12, 24\n\tv_add_co_u32 v0, vcc_lo, v16, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_695\n\t.p2align\t6\n.LBB8_692: ; in Loop: Header=BB8_695 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_694\n; %bb.693: ; in Loop: Header=BB8_695 Depth=2\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_695\n\ts_branch .LBB8_697\n\t.p2align\t6\n.LBB8_694: ; in Loop: Header=BB8_626 Depth=1\n\ts_branch .LBB8_697\n.LBB8_695: ; Parent Loop BB8_626 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_692\n; %bb.696: ; in Loop: Header=BB8_695 Depth=2\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_692\n.LBB8_697: ; in Loop: Header=BB8_626 Depth=1\n\tglobal_load_b64 v[0:1], v[18:19], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_625\n; %bb.698: ; in Loop: Header=BB8_626 Depth=1\n\ts_clause 0x2\n\tglobal_load_b64 v[4:5], v25, s[2:3] offset:40\n\tglobal_load_b64 v[8:9], v25, s[2:3] offset:24 glc\n\tglobal_load_b64 v[6:7], v25, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v10, vcc_lo, v4, 1\n\tv_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, v10, s10\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\tv_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10\n\tv_and_b32_e32 v5, v3, v5\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v4, v2, v4\n\tv_mul_hi_u32 v10, v4, 24\n\tv_mul_lo_u32 v4, v4, 24\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_add_co_u32 v6, vcc_lo, v6, v4\n\tv_mov_b32_e32 v4, v8\n\tv_mul_lo_u32 v5, v5, 24\n\tv_add_nc_u32_e32 v5, v10, v5\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v5, v9\n\tglobal_store_b64 v[6:7], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_625\n; %bb.699: ; in Loop: Header=BB8_626 Depth=1\n\ts_mov_b32 s0, 0\n.LBB8_700: ; Parent Loop BB8_626 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]\n\tv_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_700\n\ts_branch .LBB8_625\n.LBB8_701:\n\ts_mov_b32 s0, 0\n.LBB8_702:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_b32 vcc_lo, exec_lo, s0\n\ts_cbranch_vccz .LBB8_730\n; %bb.703:\n\t;;#ASMSTART\n\t;;#ASMEND\n\tv_readfirstlane_b32 s0, v23\n\tv_mov_b32_e32 v4, 0\n\tv_mov_b32_e32 v5, 0\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u32_e64 s0, s0, v23\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_709\n; %bb.704:\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s4, exec_lo\n\tglobal_load_b64 v[6:7], v0, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[2:3] offset:40\n\tglobal_load_b64 v[3:4], v0, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v6\n\tv_and_b32_e32 v2, v2, v7\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v5, v1, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v5, v2\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, v3, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo\n\tglobal_load_b64 v[4:5], v[1:2], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[4:5], v[6:7]\n\ts_cbranch_execz .LBB8_708\n; %bb.705:\n\ts_mov_b32 s5, 0\n\t.p2align\t6\n.LBB8_706: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[2:3] offset:40\n\tglobal_load_b64 v[8:9], v0, s[2:3]\n\tv_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v1, v1, v6\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7\n\tv_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]\n\tglobal_load_b64 v[4:5], v[3:4], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]\n\ts_or_b32 s5, vcc_lo, s5\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s5\n\ts_cbranch_execnz .LBB8_706\n; %bb.707:\n\ts_or_b32 exec_lo, exec_lo, s5\n.LBB8_708:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s4\n.LBB8_709:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v24, 0\n\tv_readfirstlane_b32 s4, v4\n\tv_readfirstlane_b32 s5, v5\n\ts_mov_b32 s8, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[6:7], v24, s[2:3] offset:40\n\tglobal_load_b128 v[0:3], v24, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s6, v6\n\tv_readfirstlane_b32 s7, v7\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[6:7], s[4:5], s[6:7]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_711\n; %bb.710:\n\tv_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0\n\ts_mul_i32 s8, s7, 24\n\ts_mul_hi_u32 s9, s6, 24\n\tv_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1\n\ts_add_i32 s9, s9, s8\n\ts_mul_i32 s8, s6, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v8, vcc_lo, v0, s8\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo\n\tglobal_store_b128 v[8:9], v[4:7], off offset:8\n.LBB8_711:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[8:9], s[6:7], 12\n\tv_and_or_b32 v20, v20, 0xffffff1d, 34\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v4, vcc_lo, v2, s8\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo\n\tv_lshlrev_b64 v[2:3], 6, v[23:24]\n\ts_mov_b32 s8, 0\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_add_co_u32 v8, vcc_lo, v4, v2\n\tv_mov_b32_e32 v6, 0\n\tv_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo\n\tv_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11\n\tv_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10\n\ts_delay_alu instid0(VALU_DEP_4)\n\tv_mov_b32_e32 v7, v6\n\ts_clause 0x4\n\tglobal_store_b64 v[8:9], v[20:21], off\n\tglobal_store_b128 v[8:9], v[2:5], off offset:8\n\tglobal_store_b128 v[8:9], v[2:5], off offset:24\n\tglobal_store_b128 v[8:9], v[2:5], off offset:40\n\tglobal_store_b64 v[8:9], v[6:7], off offset:56\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_719\n; %bb.712:\n\tv_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4\n\tv_mov_b32_e32 v10, s5\n\ts_clause 0x1\n\tglobal_load_b64 v[11:12], v8, s[2:3] offset:32 glc\n\tglobal_load_b64 v[2:3], v8, s[2:3] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s8, v2\n\tv_readfirstlane_b32 s9, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[8:9], s[8:9], s[4:5]\n\ts_mul_i32 s9, s9, 24\n\ts_mul_hi_u32 s10, s8, 24\n\ts_mul_i32 s8, s8, 24\n\ts_add_i32 s10, s10, s9\n\tv_add_co_u32 v6, vcc_lo, v0, s8\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo\n\ts_mov_b32 s8, exec_lo\n\tglobal_store_b64 v[6:7], v[11:12], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[11:12]\n\ts_cbranch_execz .LBB8_715\n; %bb.713:\n\ts_mov_b32 s9, 0\n.LBB8_714: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s9, vcc_lo, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s9\n\ts_cbranch_execnz .LBB8_714\n.LBB8_715:\n\ts_or_b32 exec_lo, exec_lo, s8\n\tv_mov_b32_e32 v2, 0\n\ts_mov_b32 s9, exec_lo\n\ts_mov_b32 s8, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s9, 0\n\tglobal_load_b64 v[2:3], v2, s[2:3] offset:16\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_717\n; %bb.716:\n\ts_bcnt1_i32_b32 s9, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_717:\n\ts_or_b32 exec_lo, exec_lo, s8\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_719\n; %bb.718:\n\tglobal_load_b32 v2, v[2:3], off offset:24\n\tv_mov_b32_e32 v3, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s8, v2\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_and_b32 m0, s8, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_719:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s7, 24\n\ts_mul_hi_u32 s7, s6, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s7, s7, s1\n\ts_mul_i32 s1, s6, 24\n\tv_add_co_u32 v0, vcc_lo, v0, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_723\n\t.p2align\t6\n.LBB8_720: ; in Loop: Header=BB8_723 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_722\n; %bb.721: ; in Loop: Header=BB8_723 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_723\n\ts_branch .LBB8_725\n\t.p2align\t6\n.LBB8_722:\n\ts_branch .LBB8_725\n.LBB8_723: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_720\n; %bb.724: ; in Loop: Header=BB8_723 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_720\n.LBB8_725:\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_729\n; %bb.726:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[2:3] offset:40\n\tglobal_load_b64 v[7:8], v6, s[2:3] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s4\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_729\n; %bb.727:\n\ts_mov_b32 s0, 0\n.LBB8_728: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_728\n.LBB8_729:\n\ts_or_b32 exec_lo, exec_lo, s1\n.LBB8_730:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s14\n\tv_mov_b32_e32 v2, 4\n\ts_movk_i32 s0, 0x558\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, 0\n\tv_mov_b32_e32 v1, 0\n\tv_add_nc_u32_e64 v3, s0, 4\n\tv_add_nc_u32_e32 v2, 0x2a8, v2\n\ts_waitcnt lgkmcnt(0)\n\ts_mov_b32 s2, 5\n\ts_mov_b32 s1, 0x3ffb3333\n\ts_mov_b32 s0, 0x33333333\n.LBB8_731: ; =>This Inner Loop Header: Depth=1\n\ts_clause 0x1\n\tscratch_load_b32 v4, off, off offset:2740\n\tscratch_load_b32 v5, off, off offset:2748\n\ts_add_i32 s2, s2, -1\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\ts_cmp_eq_u32 s2, 0\n\ts_waitcnt vmcnt(1)\n\tv_add_nc_u32_e32 v6, -1, v4\n\tv_lshl_add_u32 v4, v6, 2, v42\n\tscratch_load_b32 v7, v4, off\n\ts_waitcnt vmcnt(1)\n\tv_lshl_add_u32 v4, v5, 2, v2\n\tscratch_load_b32 v8, v4, off\n\tv_mul_f64 v[4:5], v[0:1], s[0:1]\n\tv_add_f64 v[0:1], v[0:1], 1.0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_cvt_f32_f64_e32 v4, v[4:5]\n\ts_waitcnt vmcnt(1)\n\tv_lshlrev_b32_e32 v5, 2, v7\n\tv_add_nc_u32_e32 v9, 4, v5\n\tv_add_nc_u32_e32 v10, v2, v5\n\tv_add_nc_u32_e32 v5, v3, v5\n\tscratch_store_b32 off, v6, off offset:2740\n\tscratch_store_b32 v9, v4, off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 v10, v8, off\n\tscratch_load_b32 v4, off, off offset:2748\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 v5, v4, off\n\tscratch_load_b32 v4, off, off offset:2748\n\tv_lshl_add_u32 v5, v8, 2, v3\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v4, v4, 2, v2\n\ts_clause 0x1\n\tscratch_store_b32 v4, v7, off\n\tscratch_store_b32 v5, v7, off\n\tscratch_load_b32 v4, off, off offset:2752\n\ts_waitcnt vmcnt(0)\n\tv_add_nc_u32_e32 v4, 1, v4\n\tscratch_store_b32 off, v4, off offset:2752\n\ts_cbranch_scc0 .LBB8_731\n; %bb.732:\n\ts_load_b64 s[26:27], s[22:23], 0x58\n\tv_mbcnt_lo_u32_b32 v41, -1, 0\n\tv_mov_b32_e32 v6, 0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v41\n\t;;#ASMSTART\n\t;;#ASMEND\n\tv_readfirstlane_b32 s0, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u32_e64 s0, s0, v4\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_738\n; %bb.733:\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s2, exec_lo\n\ts_waitcnt lgkmcnt(0)\n\tglobal_load_b64 v[8:9], v0, s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[5:6], v0, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v2, v2, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v3, v1, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v3, v2\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, v5, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo\n\tglobal_load_b64 v[6:7], v[1:2], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[6:7], v[8:9]\n\ts_cbranch_execz .LBB8_737\n; %bb.734:\n\ts_mov_b32 s3, 0\n\t.p2align\t6\n.LBB8_735: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[10:11], v0, s[26:27]\n\tv_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v7, v2, v9\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]\n\tv_mov_b32_e32 v1, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]\n\tv_mov_b32_e32 v6, v2\n\tglobal_load_b64 v[6:7], v[5:6], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]\n\ts_or_b32 s3, vcc_lo, s3\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s3\n\ts_cbranch_execnz .LBB8_735\n; %bb.736:\n\ts_or_b32 exec_lo, exec_lo, s3\n.LBB8_737:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s2\n.LBB8_738:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v5, 0\n\tv_readfirstlane_b32 s2, v6\n\tv_readfirstlane_b32 s3, v7\n\ts_mov_b32 s6, exec_lo\n\ts_waitcnt lgkmcnt(0)\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v5, s[26:27] offset:40\n\tglobal_load_b128 v[0:3], v5, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s4, v8\n\tv_readfirstlane_b32 s5, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[4:5], s[2:3], s[4:5]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_740\n; %bb.739:\n\tv_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, 0\n\ts_mul_i32 s6, s5, 24\n\ts_mul_hi_u32 s7, s4, 24\n\tv_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1\n\ts_add_i32 s7, s7, s6\n\ts_mul_i32 s6, s4, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v10, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo\n\tglobal_store_b128 v[10:11], v[6:9], off offset:8\n.LBB8_740:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[6:7], s[4:5], 12\n\tv_lshlrev_b64 v[4:5], 6, v[4:5]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v2, vcc_lo, v2, s6\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo\n\tv_mov_b32_e32 v3, 0\n\ts_mov_b32 s8, 0\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_add_co_u32 v6, vcc_lo, v2, v4\n\tv_mov_b32_e32 v2, 33\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v4, v3\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8\n\tv_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10\n\tv_mov_b32_e32 v11, s11\n\ts_clause 0x3\n\tglobal_store_b128 v[6:7], v[2:5], off\n\tglobal_store_b128 v[6:7], v[8:11], off offset:16\n\tglobal_store_b128 v[6:7], v[8:11], off offset:32\n\tglobal_store_b128 v[6:7], v[8:11], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_748\n; %bb.741:\n\tv_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s2\n\tv_mov_b32_e32 v12, s3\n\ts_clause 0x1\n\tglobal_load_b64 v[13:14], v10, s[26:27] offset:32 glc\n\tglobal_load_b64 v[2:3], v10, s[26:27] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\tv_readfirstlane_b32 s7, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[6:7], s[6:7], s[2:3]\n\ts_mul_i32 s7, s7, 24\n\ts_mul_hi_u32 s8, s6, 24\n\ts_mul_i32 s6, s6, 24\n\ts_add_i32 s8, s8, s7\n\tv_add_co_u32 v8, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s8, v1, vcc_lo\n\ts_mov_b32 s6, exec_lo\n\tglobal_store_b64 v[8:9], v[13:14], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[13:14]\n\ts_cbranch_execz .LBB8_744\n; %bb.742:\n\ts_mov_b32 s7, 0\n.LBB8_743: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3\n\ts_sleep 1\n\tglobal_store_b64 v[8:9], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s7, vcc_lo, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s7\n\ts_cbranch_execnz .LBB8_743\n.LBB8_744:\n\ts_or_b32 exec_lo, exec_lo, s6\n\tv_mov_b32_e32 v2, 0\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 s6, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s7, 0\n\tglobal_load_b64 v[2:3], v2, s[26:27] offset:16\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_746\n; %bb.745:\n\ts_bcnt1_i32_b32 s7, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s7\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_746:\n\ts_or_b32 exec_lo, exec_lo, s6\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_748\n; %bb.747:\n\tglobal_load_b32 v2, v[2:3], off offset:24\n\tv_mov_b32_e32 v3, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_and_b32 m0, s6, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_748:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s5, 24\n\ts_mul_hi_u32 s5, s4, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s5, s5, s1\n\ts_mul_i32 s1, s4, 24\n\tv_add_co_u32 v0, vcc_lo, v0, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_752\n\t.p2align\t6\n.LBB8_749: ; in Loop: Header=BB8_752 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_751\n; %bb.750: ; in Loop: Header=BB8_752 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_752\n\ts_branch .LBB8_754\n\t.p2align\t6\n.LBB8_751:\n\ts_branch .LBB8_754\n.LBB8_752: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_749\n; %bb.753: ; in Loop: Header=BB8_752 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_749\n.LBB8_754:\n\tglobal_load_b64 v[20:21], v[6:7], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_758\n; %bb.755:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[26:27] offset:40\n\tglobal_load_b64 v[7:8], v6, s[26:27] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[26:27]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s2\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_758\n; %bb.756:\n\ts_mov_b32 s0, 0\n.LBB8_757: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_757\n.LBB8_758:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_getpc_b64 s[2:3]\n\ts_add_u32 s2, s2, .str.5@rel32@lo+4\n\ts_addc_u32 s3, s3, .str.5@rel32@hi+12\n\ts_mov_b32 s0, -1\n\ts_cmp_lg_u64 s[2:3], 0\n\ts_cbranch_scc0 .LBB8_837\n; %bb.759:\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v1, v21 :: v_dual_and_b32 v0, -3, v20\n\tv_mov_b32_e32 v23, 0\n\ts_mov_b64 s[4:5], 44\n\ts_branch .LBB8_761\n.LBB8_760: ; in Loop: Header=BB8_761 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_sub_u32 s4, s4, s6\n\ts_subb_u32 s5, s5, s7\n\ts_add_u32 s2, s2, s6\n\ts_addc_u32 s3, s3, s7\n\ts_cmp_lg_u64 s[4:5], 0\n\ts_cbranch_scc0 .LBB8_836\n.LBB8_761: ; =>This Loop Header: Depth=1\n ; Child Loop BB8_764 Depth 2\n ; Child Loop BB8_771 Depth 2\n ; Child Loop BB8_778 Depth 2\n ; Child Loop BB8_785 Depth 2\n ; Child Loop BB8_792 Depth 2\n ; Child Loop BB8_799 Depth 2\n ; Child Loop BB8_806 Depth 2\n ; Child Loop BB8_813 Depth 2\n ; Child Loop BB8_821 Depth 2\n ; Child Loop BB8_830 Depth 2\n ; Child Loop BB8_835 Depth 2\n\tv_cmp_lt_u64_e64 s0, s[4:5], 56\n ; implicit-def: $sgpr13\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b32 s0, s0, exec_lo\n\ts_cselect_b32 s6, s4, 56\n\ts_cselect_b32 s7, s5, 0\n\ts_cmp_gt_u32 s6, 7\n\ts_mov_b32 s0, -1\n\ts_cbranch_scc1 .LBB8_766\n; %bb.762: ; in Loop: Header=BB8_761 Depth=1\n\tv_mov_b32_e32 v2, 0\n\tv_mov_b32_e32 v3, 0\n\ts_cmp_eq_u32 s6, 0\n\ts_cbranch_scc1 .LBB8_765\n; %bb.763: ; in Loop: Header=BB8_761 Depth=1\n\ts_lshl_b64 s[0:1], s[6:7], 3\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], s[2:3]\n.LBB8_764: ; Parent Loop BB8_761 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v4, v23, s[10:11]\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[4:5], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_add_u32 s10, s10, 1\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s0, s8\n\tv_or_b32_e32 v2, v4, v2\n\tv_or_b32_e32 v3, v5, v3\n\ts_cbranch_scc1 .LBB8_764\n.LBB8_765: ; in Loop: Header=BB8_761 Depth=1\n\ts_mov_b32 s0, 0\n\ts_mov_b32 s13, 0\n.LBB8_766: ; in Loop: Header=BB8_761 Depth=1\n\ts_and_not1_b32 vcc_lo, exec_lo, s0\n\ts_mov_b64 s[0:1], s[2:3]\n\ts_cbranch_vccnz .LBB8_768\n; %bb.767: ; in Loop: Header=BB8_761 Depth=1\n\tglobal_load_b64 v[2:3], v23, s[2:3]\n\ts_add_i32 s13, s6, -8\n\ts_add_u32 s0, s2, 8\n\ts_addc_u32 s1, s3, 0\n.LBB8_768: ; in Loop: Header=BB8_761 Depth=1\n\ts_cmp_gt_u32 s13, 7\n\ts_cbranch_scc1 .LBB8_773\n; %bb.769: ; in Loop: Header=BB8_761 Depth=1\n\tv_mov_b32_e32 v4, 0\n\tv_mov_b32_e32 v5, 0\n\ts_cmp_eq_u32 s13, 0\n\ts_cbranch_scc1 .LBB8_772\n; %bb.770: ; in Loop: Header=BB8_761 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_771: ; Parent Loop BB8_761 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v6, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[6:7], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s13, s10\n\tv_or_b32_e32 v4, v6, v4\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v5, v7, v5\n\ts_cbranch_scc1 .LBB8_771\n.LBB8_772: ; in Loop: Header=BB8_761 Depth=1\n\ts_mov_b32 s12, 0\n\ts_cbranch_execz .LBB8_774\n\ts_branch .LBB8_775\n.LBB8_773: ; in Loop: Header=BB8_761 Depth=1\n ; implicit-def: $vgpr4_vgpr5\n ; implicit-def: $sgpr12\n.LBB8_774: ; in Loop: Header=BB8_761 Depth=1\n\tglobal_load_b64 v[4:5], v23, s[0:1]\n\ts_add_i32 s12, s13, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_775: ; in Loop: Header=BB8_761 Depth=1\n\ts_cmp_gt_u32 s12, 7\n\ts_cbranch_scc1 .LBB8_780\n; %bb.776: ; in Loop: Header=BB8_761 Depth=1\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\ts_cmp_eq_u32 s12, 0\n\ts_cbranch_scc1 .LBB8_779\n; %bb.777: ; in Loop: Header=BB8_761 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_778: ; Parent Loop BB8_761 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v8, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v8\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[8:9], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s12, s10\n\tv_or_b32_e32 v6, v8, v6\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v7, v9, v7\n\ts_cbranch_scc1 .LBB8_778\n.LBB8_779: ; in Loop: Header=BB8_761 Depth=1\n\ts_mov_b32 s13, 0\n\ts_cbranch_execz .LBB8_781\n\ts_branch .LBB8_782\n.LBB8_780: ; in Loop: Header=BB8_761 Depth=1\n ; implicit-def: $sgpr13\n.LBB8_781: ; in Loop: Header=BB8_761 Depth=1\n\tglobal_load_b64 v[6:7], v23, s[0:1]\n\ts_add_i32 s13, s12, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_782: ; in Loop: Header=BB8_761 Depth=1\n\ts_cmp_gt_u32 s13, 7\n\ts_cbranch_scc1 .LBB8_787\n; %bb.783: ; in Loop: Header=BB8_761 Depth=1\n\tv_mov_b32_e32 v8, 0\n\tv_mov_b32_e32 v9, 0\n\ts_cmp_eq_u32 s13, 0\n\ts_cbranch_scc1 .LBB8_786\n; %bb.784: ; in Loop: Header=BB8_761 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_785: ; Parent Loop BB8_761 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v10, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v10\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[10:11], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s13, s10\n\tv_or_b32_e32 v8, v10, v8\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v9, v11, v9\n\ts_cbranch_scc1 .LBB8_785\n.LBB8_786: ; in Loop: Header=BB8_761 Depth=1\n\ts_mov_b32 s12, 0\n\ts_cbranch_execz .LBB8_788\n\ts_branch .LBB8_789\n.LBB8_787: ; in Loop: Header=BB8_761 Depth=1\n ; implicit-def: $vgpr8_vgpr9\n ; implicit-def: $sgpr12\n.LBB8_788: ; in Loop: Header=BB8_761 Depth=1\n\tglobal_load_b64 v[8:9], v23, s[0:1]\n\ts_add_i32 s12, s13, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_789: ; in Loop: Header=BB8_761 Depth=1\n\ts_cmp_gt_u32 s12, 7\n\ts_cbranch_scc1 .LBB8_794\n; %bb.790: ; in Loop: Header=BB8_761 Depth=1\n\tv_mov_b32_e32 v10, 0\n\tv_mov_b32_e32 v11, 0\n\ts_cmp_eq_u32 s12, 0\n\ts_cbranch_scc1 .LBB8_793\n; %bb.791: ; in Loop: Header=BB8_761 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_792: ; Parent Loop BB8_761 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v12, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v12\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[12:13], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s12, s10\n\tv_or_b32_e32 v10, v12, v10\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v11, v13, v11\n\ts_cbranch_scc1 .LBB8_792\n.LBB8_793: ; in Loop: Header=BB8_761 Depth=1\n\ts_mov_b32 s13, 0\n\ts_cbranch_execz .LBB8_795\n\ts_branch .LBB8_796\n.LBB8_794: ; in Loop: Header=BB8_761 Depth=1\n ; implicit-def: $sgpr13\n.LBB8_795: ; in Loop: Header=BB8_761 Depth=1\n\tglobal_load_b64 v[10:11], v23, s[0:1]\n\ts_add_i32 s13, s12, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_796: ; in Loop: Header=BB8_761 Depth=1\n\ts_cmp_gt_u32 s13, 7\n\ts_cbranch_scc1 .LBB8_801\n; %bb.797: ; in Loop: Header=BB8_761 Depth=1\n\tv_mov_b32_e32 v12, 0\n\tv_mov_b32_e32 v13, 0\n\ts_cmp_eq_u32 s13, 0\n\ts_cbranch_scc1 .LBB8_800\n; %bb.798: ; in Loop: Header=BB8_761 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_799: ; Parent Loop BB8_761 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v14, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v14\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[14:15], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s13, s10\n\tv_or_b32_e32 v12, v14, v12\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v13, v15, v13\n\ts_cbranch_scc1 .LBB8_799\n.LBB8_800: ; in Loop: Header=BB8_761 Depth=1\n\ts_mov_b32 s12, 0\n\ts_cbranch_execz .LBB8_802\n\ts_branch .LBB8_803\n.LBB8_801: ; in Loop: Header=BB8_761 Depth=1\n ; implicit-def: $vgpr12_vgpr13\n ; implicit-def: $sgpr12\n.LBB8_802: ; in Loop: Header=BB8_761 Depth=1\n\tglobal_load_b64 v[12:13], v23, s[0:1]\n\ts_add_i32 s12, s13, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_803: ; in Loop: Header=BB8_761 Depth=1\n\ts_cmp_gt_u32 s12, 7\n\ts_cbranch_scc1 .LBB8_808\n; %bb.804: ; in Loop: Header=BB8_761 Depth=1\n\tv_mov_b32_e32 v14, 0\n\tv_mov_b32_e32 v15, 0\n\ts_cmp_eq_u32 s12, 0\n\ts_cbranch_scc1 .LBB8_807\n; %bb.805: ; in Loop: Header=BB8_761 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], s[0:1]\n.LBB8_806: ; Parent Loop BB8_761 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v16, v23, s[10:11]\n\ts_add_i32 s12, s12, -1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v16\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[16:17], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_add_u32 s10, s10, 1\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s12, 0\n\tv_or_b32_e32 v14, v16, v14\n\tv_or_b32_e32 v15, v17, v15\n\ts_cbranch_scc1 .LBB8_806\n.LBB8_807: ; in Loop: Header=BB8_761 Depth=1\n\ts_cbranch_execz .LBB8_809\n\ts_branch .LBB8_810\n.LBB8_808: ; in Loop: Header=BB8_761 Depth=1\n.LBB8_809: ; in Loop: Header=BB8_761 Depth=1\n\tglobal_load_b64 v[14:15], v23, s[0:1]\n.LBB8_810: ; in Loop: Header=BB8_761 Depth=1\n\tv_mov_b32_e32 v22, v41\n\tv_mov_b32_e32 v24, 0\n\tv_mov_b32_e32 v25, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v22\n\tv_cmp_eq_u32_e64 s0, s0, v22\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_816\n; %bb.811: ; in Loop: Header=BB8_761 Depth=1\n\tglobal_load_b64 v[18:19], v23, s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[16:17], v23, s[26:27] offset:40\n\tglobal_load_b64 v[24:25], v23, s[26:27]\n\ts_mov_b32 s8, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v17, v17, v19\n\tv_and_b32_e32 v16, v16, v18\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v17, v17, 24\n\tv_mul_hi_u32 v26, v16, 24\n\tv_mul_lo_u32 v16, v16, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v17, v26, v17\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v16, vcc_lo, v24, v16\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v17, vcc_lo, v25, v17, vcc_lo\n\tglobal_load_b64 v[16:17], v[16:17], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[24:25], v23, v[16:19], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[24:25], v[18:19]\n\ts_cbranch_execz .LBB8_815\n; %bb.812: ; in Loop: Header=BB8_761 Depth=1\n\ts_mov_b32 s9, 0\n\t.p2align\t6\n.LBB8_813: ; Parent Loop BB8_761 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[16:17], v23, s[26:27] offset:40\n\tglobal_load_b64 v[26:27], v23, s[26:27]\n\tv_dual_mov_b32 v18, v24 :: v_dual_mov_b32 v19, v25\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v16, v16, v18\n\tv_and_b32_e32 v17, v17, v19\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[24:25], null, v16, 24, v[26:27]\n\tv_mov_b32_e32 v16, v25\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_mad_u64_u32 v[25:26], null, v17, 24, v[16:17]\n\tglobal_load_b64 v[16:17], v[24:25], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[24:25], v23, v[16:19], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[24:25], v[18:19]\n\ts_or_b32 s9, vcc_lo, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s9\n\ts_cbranch_execnz .LBB8_813\n; %bb.814: ; in Loop: Header=BB8_761 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s9\n.LBB8_815: ; in Loop: Header=BB8_761 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s8\n.LBB8_816: ; in Loop: Header=BB8_761 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_clause 0x1\n\tglobal_load_b64 v[26:27], v23, s[26:27] offset:40\n\tglobal_load_b128 v[16:19], v23, s[26:27]\n\tv_readfirstlane_b32 s8, v24\n\tv_readfirstlane_b32 s9, v25\n\ts_mov_b32 s12, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s10, v26\n\tv_readfirstlane_b32 s11, v27\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[10:11], s[8:9], s[10:11]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_818\n; %bb.817: ; in Loop: Header=BB8_761 Depth=1\n\tv_dual_mov_b32 v24, s12 :: v_dual_mov_b32 v25, 0\n\ts_mul_i32 s12, s11, 24\n\ts_mul_hi_u32 s13, s10, 24\n\tv_dual_mov_b32 v26, 2 :: v_dual_mov_b32 v27, 1\n\ts_add_i32 s13, s13, s12\n\ts_mul_i32 s12, s10, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v28, vcc_lo, v16, s12\n\tv_add_co_ci_u32_e32 v29, vcc_lo, s13, v17, vcc_lo\n\tglobal_store_b128 v[28:29], v[24:27], off offset:8\n.LBB8_818: ; in Loop: Header=BB8_761 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_cmp_gt_u64_e64 vcc_lo, s[4:5], 56\n\tv_or_b32_e32 v24, 2, v0\n\ts_lshl_b64 s[12:13], s[10:11], 12\n\ts_lshl_b32 s1, s6, 2\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\ts_add_i32 s1, s1, 28\n\tv_cndmask_b32_e32 v0, v24, v0, vcc_lo\n\tv_lshlrev_b64 v[24:25], 6, v[22:23]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v18, vcc_lo, v18, s12\n\tv_add_co_ci_u32_e32 v19, vcc_lo, s13, v19, vcc_lo\n\ts_and_b32 s1, s1, 0x1e0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v18, vcc_lo, v18, v24\n\tv_and_or_b32 v0, v0, 0xffffff1f, s1\n\tv_add_co_ci_u32_e32 v19, vcc_lo, v19, v25, vcc_lo\n\ts_clause 0x3\n\tglobal_store_b128 v[18:19], v[0:3], off\n\tglobal_store_b128 v[18:19], v[4:7], off offset:16\n\tglobal_store_b128 v[18:19], v[8:11], off offset:32\n\tglobal_store_b128 v[18:19], v[12:15], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_826\n; %bb.819: ; in Loop: Header=BB8_761 Depth=1\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v23, s[26:27] offset:32 glc\n\tglobal_load_b64 v[0:1], v23, s[26:27] offset:40\n\tv_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s12, v0\n\tv_readfirstlane_b32 s13, v1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[12:13], s[12:13], s[8:9]\n\ts_mul_i32 s13, s13, 24\n\ts_mul_hi_u32 s14, s12, 24\n\ts_mul_i32 s12, s12, 24\n\ts_add_i32 s14, s14, s13\n\tv_add_co_u32 v4, vcc_lo, v16, s12\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s14, v17, vcc_lo\n\ts_mov_b32 s12, exec_lo\n\tglobal_store_b64 v[4:5], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v23, v[6:9], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[2:3], v[8:9]\n\ts_cbranch_execz .LBB8_822\n; %bb.820: ; in Loop: Header=BB8_761 Depth=1\n\ts_mov_b32 s13, 0\n.LBB8_821: ; Parent Loop BB8_761 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v23, v[0:3], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]\n\tv_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0\n\ts_or_b32 s13, vcc_lo, s13\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s13\n\ts_cbranch_execnz .LBB8_821\n.LBB8_822: ; in Loop: Header=BB8_761 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s12\n\tglobal_load_b64 v[0:1], v23, s[26:27] offset:16\n\ts_mov_b32 s13, exec_lo\n\ts_mov_b32 s12, exec_lo\n\tv_mbcnt_lo_u32_b32 v2, s13, 0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_eq_u32_e32 0, v2\n\ts_cbranch_execz .LBB8_824\n; %bb.823: ; in Loop: Header=BB8_761 Depth=1\n\ts_bcnt1_i32_b32 s13, s13\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s13\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off offset:8\n.LBB8_824: ; in Loop: Header=BB8_761 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s12\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\ts_cbranch_vccnz .LBB8_826\n; %bb.825: ; in Loop: Header=BB8_761 Depth=1\n\tglobal_load_b32 v22, v[0:1], off offset:24\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s12, v22\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[2:3], v[22:23], off\n\ts_and_b32 m0, s12, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_826: ; in Loop: Header=BB8_761 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s11, 24\n\ts_mul_hi_u32 s11, s10, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s11, s11, s1\n\ts_mul_i32 s1, s10, 24\n\tv_add_co_u32 v0, vcc_lo, v16, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s11, v17, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_830\n\t.p2align\t6\n.LBB8_827: ; in Loop: Header=BB8_830 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_829\n; %bb.828: ; in Loop: Header=BB8_830 Depth=2\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_830\n\ts_branch .LBB8_832\n\t.p2align\t6\n.LBB8_829: ; in Loop: Header=BB8_761 Depth=1\n\ts_branch .LBB8_832\n.LBB8_830: ; Parent Loop BB8_761 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_827\n; %bb.831: ; in Loop: Header=BB8_830 Depth=2\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_827\n.LBB8_832: ; in Loop: Header=BB8_761 Depth=1\n\tglobal_load_b64 v[0:1], v[18:19], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_760\n; %bb.833: ; in Loop: Header=BB8_761 Depth=1\n\ts_clause 0x2\n\tglobal_load_b64 v[4:5], v23, s[26:27] offset:40\n\tglobal_load_b64 v[8:9], v23, s[26:27] offset:24 glc\n\tglobal_load_b64 v[6:7], v23, s[26:27]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v10, vcc_lo, v4, 1\n\tv_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, v10, s8\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s9, v11, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\tv_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10\n\tv_and_b32_e32 v5, v3, v5\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v4, v2, v4\n\tv_mul_hi_u32 v10, v4, 24\n\tv_mul_lo_u32 v4, v4, 24\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_add_co_u32 v6, vcc_lo, v6, v4\n\tv_mov_b32_e32 v4, v8\n\tv_mul_lo_u32 v5, v5, 24\n\tv_add_nc_u32_e32 v5, v10, v5\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v5, v9\n\tglobal_store_b64 v[6:7], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v23, v[2:5], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_760\n; %bb.834: ; in Loop: Header=BB8_761 Depth=1\n\ts_mov_b32 s0, 0\n.LBB8_835: ; Parent Loop BB8_761 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[8:9], v23, v[2:5], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]\n\tv_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_835\n\ts_branch .LBB8_760\n.LBB8_836:\n\ts_mov_b32 s0, 0\n.LBB8_837:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_b32 vcc_lo, exec_lo, s0\n\ts_cbranch_vccz .LBB8_865\n; %bb.838:\n\tv_mov_b32_e32 v4, v41\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v4\n\tv_cmp_eq_u32_e64 s0, s0, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_844\n; %bb.839:\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s2, exec_lo\n\tglobal_load_b64 v[8:9], v0, s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[5:6], v0, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v2, v2, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v3, v1, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v3, v2\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, v5, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo\n\tglobal_load_b64 v[6:7], v[1:2], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[6:7], v[8:9]\n\ts_cbranch_execz .LBB8_843\n; %bb.840:\n\ts_mov_b32 s3, 0\n\t.p2align\t6\n.LBB8_841: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[10:11], v0, s[26:27]\n\tv_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v7, v2, v9\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]\n\tv_mov_b32_e32 v1, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]\n\tv_mov_b32_e32 v6, v2\n\tglobal_load_b64 v[6:7], v[5:6], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]\n\ts_or_b32 s3, vcc_lo, s3\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s3\n\ts_cbranch_execnz .LBB8_841\n; %bb.842:\n\ts_or_b32 exec_lo, exec_lo, s3\n.LBB8_843:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s2\n.LBB8_844:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v5, 0\n\tv_readfirstlane_b32 s2, v6\n\tv_readfirstlane_b32 s3, v7\n\ts_mov_b32 s6, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v5, s[26:27] offset:40\n\tglobal_load_b128 v[0:3], v5, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s4, v8\n\tv_readfirstlane_b32 s5, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[4:5], s[2:3], s[4:5]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_846\n; %bb.845:\n\tv_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, 0\n\ts_mul_i32 s6, s5, 24\n\ts_mul_hi_u32 s7, s4, 24\n\tv_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1\n\ts_add_i32 s7, s7, s6\n\ts_mul_i32 s6, s4, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v10, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo\n\tglobal_store_b128 v[10:11], v[6:9], off offset:8\n.LBB8_846:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[6:7], s[4:5], 12\n\ts_mov_b32 s8, 0\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v7, vcc_lo, v2, s6\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo\n\tv_lshlrev_b64 v[2:3], 6, v[4:5]\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_mov_b32_e32 v6, 0\n\tv_and_or_b32 v20, v20, 0xffffff1d, 34\n\tv_add_co_u32 v8, vcc_lo, v7, v2\n\tv_add_co_ci_u32_e32 v9, vcc_lo, v9, v3, vcc_lo\n\tv_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11\n\tv_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10\n\tv_mov_b32_e32 v7, v6\n\ts_clause 0x4\n\tglobal_store_b64 v[8:9], v[20:21], off\n\tglobal_store_b128 v[8:9], v[2:5], off offset:8\n\tglobal_store_b128 v[8:9], v[2:5], off offset:24\n\tglobal_store_b128 v[8:9], v[2:5], off offset:40\n\tglobal_store_b64 v[8:9], v[6:7], off offset:56\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_854\n; %bb.847:\n\tv_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s2\n\tv_mov_b32_e32 v10, s3\n\ts_clause 0x1\n\tglobal_load_b64 v[11:12], v8, s[26:27] offset:32 glc\n\tglobal_load_b64 v[2:3], v8, s[26:27] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\tv_readfirstlane_b32 s7, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[6:7], s[6:7], s[2:3]\n\ts_mul_i32 s7, s7, 24\n\ts_mul_hi_u32 s8, s6, 24\n\ts_mul_i32 s6, s6, 24\n\ts_add_i32 s8, s8, s7\n\tv_add_co_u32 v6, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s8, v1, vcc_lo\n\ts_mov_b32 s6, exec_lo\n\tglobal_store_b64 v[6:7], v[11:12], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[11:12]\n\ts_cbranch_execz .LBB8_850\n; %bb.848:\n\ts_mov_b32 s7, 0\n.LBB8_849: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s7, vcc_lo, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s7\n\ts_cbranch_execnz .LBB8_849\n.LBB8_850:\n\ts_or_b32 exec_lo, exec_lo, s6\n\tv_mov_b32_e32 v2, 0\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 s6, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s7, 0\n\tglobal_load_b64 v[2:3], v2, s[26:27] offset:16\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_852\n; %bb.851:\n\ts_bcnt1_i32_b32 s7, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s7\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_852:\n\ts_or_b32 exec_lo, exec_lo, s6\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_854\n; %bb.853:\n\tglobal_load_b32 v2, v[2:3], off offset:24\n\tv_mov_b32_e32 v3, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_and_b32 m0, s6, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_854:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s5, 24\n\ts_mul_hi_u32 s5, s4, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s5, s5, s1\n\ts_mul_i32 s1, s4, 24\n\tv_add_co_u32 v0, vcc_lo, v0, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_858\n\t.p2align\t6\n.LBB8_855: ; in Loop: Header=BB8_858 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_857\n; %bb.856: ; in Loop: Header=BB8_858 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_858\n\ts_branch .LBB8_860\n\t.p2align\t6\n.LBB8_857:\n\ts_branch .LBB8_860\n.LBB8_858: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_855\n; %bb.859: ; in Loop: Header=BB8_858 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_855\n.LBB8_860:\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_864\n; %bb.861:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[26:27] offset:40\n\tglobal_load_b64 v[7:8], v6, s[26:27] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[26:27]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s2\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_864\n; %bb.862:\n\ts_mov_b32 s0, 0\n.LBB8_863: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_863\n.LBB8_864:\n\ts_or_b32 exec_lo, exec_lo, s1\n.LBB8_865:\n\ts_mov_b64 s[28:29], src_private_base\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v0, 4 :: v_dual_mov_b32 v1, s29\n\ts_add_u32 s8, s22, 8\n\ts_addc_u32 s9, s23, 0\n\ts_mov_b32 s28, 4\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, _Z9printListRN18gpu_linearized_stl4listIfLi170EEE@rel32@lo+4\n\ts_addc_u32 s1, s1, _Z9printListRN18gpu_linearized_stl4listIfLi170EEE@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_swappc_b64 s[30:31], s[0:1]\n\ts_movk_i32 s0, 0x558\n\ts_movk_i32 s1, 0x2a8\n\tv_mov_b32_e32 v0, 0\n\tv_mov_b32_e32 v1, 0x40180000\n\tv_add_nc_u32_e64 v2, s0, 4\n\tv_add_nc_u32_e64 v3, s1, 4\n\ts_mov_b32 s0, 4\n.LBB8_866: ; =>This Inner Loop Header: Depth=1\n\ts_clause 0x1\n\tscratch_load_b32 v4, off, off offset:2740\n\tscratch_load_b32 v6, off, off offset:2744\n\ts_add_i32 s0, s0, -1\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)\n\ts_cmp_eq_u32 s0, 0\n\ts_waitcnt vmcnt(1)\n\tv_add_nc_u32_e32 v7, -1, v4\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v5, v6, 2, v2\n\tv_lshl_add_u32 v4, v7, 2, v42\n\ts_clause 0x1\n\tscratch_load_b32 v8, v4, off\n\tscratch_load_b32 v9, v5, off\n\tv_mul_f64 v[4:5], v[0:1], 0x40040000\n\tv_add_f64 v[0:1], v[0:1], 1.0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)\n\tv_cvt_f32_f64_e32 v4, v[4:5]\n\ts_waitcnt vmcnt(1)\n\tv_lshlrev_b32_e32 v5, 2, v8\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v10, v9, 2, v3\n\tv_add_nc_u32_e32 v11, 4, v5\n\tv_add_nc_u32_e32 v12, v3, v5\n\tv_add_nc_u32_e32 v5, v2, v5\n\tscratch_store_b32 off, v7, off offset:2740\n\ts_clause 0x3\n\tscratch_store_b32 v11, v4, off\n\tscratch_store_b32 v12, v6, off\n\tscratch_store_b32 v5, v9, off\n\tscratch_store_b32 v10, v8, off\n\tscratch_load_b32 v4, off, off offset:2744\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v4, v4, 2, v2\n\tscratch_store_b32 v4, v8, off\n\tscratch_load_b32 v4, off, off offset:2752\n\ts_waitcnt vmcnt(0)\n\tv_add_nc_u32_e32 v4, 1, v4\n\tscratch_store_b32 off, v4, off offset:2752\n\ts_cbranch_scc0 .LBB8_866\n; %bb.867:\n\tv_mov_b32_e32 v4, v41\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v4\n\tv_cmp_eq_u32_e64 s0, s0, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_873\n; %bb.868:\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s2, exec_lo\n\tglobal_load_b64 v[8:9], v0, s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[5:6], v0, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v2, v2, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v3, v1, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v3, v2\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, v5, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo\n\tglobal_load_b64 v[6:7], v[1:2], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[6:7], v[8:9]\n\ts_cbranch_execz .LBB8_872\n; %bb.869:\n\ts_mov_b32 s3, 0\n\t.p2align\t6\n.LBB8_870: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[10:11], v0, s[26:27]\n\tv_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v7, v2, v9\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]\n\tv_mov_b32_e32 v1, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]\n\tv_mov_b32_e32 v6, v2\n\tglobal_load_b64 v[6:7], v[5:6], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]\n\ts_or_b32 s3, vcc_lo, s3\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s3\n\ts_cbranch_execnz .LBB8_870\n; %bb.871:\n\ts_or_b32 exec_lo, exec_lo, s3\n.LBB8_872:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s2\n.LBB8_873:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v5, 0\n\tv_readfirstlane_b32 s2, v6\n\tv_readfirstlane_b32 s3, v7\n\ts_mov_b32 s6, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v5, s[26:27] offset:40\n\tglobal_load_b128 v[0:3], v5, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s4, v8\n\tv_readfirstlane_b32 s5, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[4:5], s[2:3], s[4:5]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_875\n; %bb.874:\n\tv_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, 0\n\ts_mul_i32 s6, s5, 24\n\ts_mul_hi_u32 s7, s4, 24\n\tv_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1\n\ts_add_i32 s7, s7, s6\n\ts_mul_i32 s6, s4, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v10, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo\n\tglobal_store_b128 v[10:11], v[6:9], off offset:8\n.LBB8_875:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[6:7], s[4:5], 12\n\tv_lshlrev_b64 v[4:5], 6, v[4:5]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v2, vcc_lo, v2, s6\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo\n\tv_mov_b32_e32 v3, 0\n\ts_mov_b32 s8, 0\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_add_co_u32 v6, vcc_lo, v2, v4\n\tv_mov_b32_e32 v2, 33\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v4, v3\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8\n\tv_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10\n\tv_mov_b32_e32 v11, s11\n\ts_clause 0x3\n\tglobal_store_b128 v[6:7], v[2:5], off\n\tglobal_store_b128 v[6:7], v[8:11], off offset:16\n\tglobal_store_b128 v[6:7], v[8:11], off offset:32\n\tglobal_store_b128 v[6:7], v[8:11], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_883\n; %bb.876:\n\tv_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s2\n\tv_mov_b32_e32 v12, s3\n\ts_clause 0x1\n\tglobal_load_b64 v[13:14], v10, s[26:27] offset:32 glc\n\tglobal_load_b64 v[2:3], v10, s[26:27] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\tv_readfirstlane_b32 s7, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[6:7], s[6:7], s[2:3]\n\ts_mul_i32 s7, s7, 24\n\ts_mul_hi_u32 s8, s6, 24\n\ts_mul_i32 s6, s6, 24\n\ts_add_i32 s8, s8, s7\n\tv_add_co_u32 v8, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s8, v1, vcc_lo\n\ts_mov_b32 s6, exec_lo\n\tglobal_store_b64 v[8:9], v[13:14], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[13:14]\n\ts_cbranch_execz .LBB8_879\n; %bb.877:\n\ts_mov_b32 s7, 0\n.LBB8_878: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3\n\ts_sleep 1\n\tglobal_store_b64 v[8:9], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s7, vcc_lo, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s7\n\ts_cbranch_execnz .LBB8_878\n.LBB8_879:\n\ts_or_b32 exec_lo, exec_lo, s6\n\tv_mov_b32_e32 v2, 0\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 s6, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s7, 0\n\tglobal_load_b64 v[2:3], v2, s[26:27] offset:16\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_881\n; %bb.880:\n\ts_bcnt1_i32_b32 s7, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s7\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_881:\n\ts_or_b32 exec_lo, exec_lo, s6\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_883\n; %bb.882:\n\tglobal_load_b32 v2, v[2:3], off offset:24\n\tv_mov_b32_e32 v3, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_and_b32 m0, s6, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_883:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s5, 24\n\ts_mul_hi_u32 s5, s4, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s5, s5, s1\n\ts_mul_i32 s1, s4, 24\n\tv_add_co_u32 v0, vcc_lo, v0, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_887\n\t.p2align\t6\n.LBB8_884: ; in Loop: Header=BB8_887 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_886\n; %bb.885: ; in Loop: Header=BB8_887 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_887\n\ts_branch .LBB8_889\n\t.p2align\t6\n.LBB8_886:\n\ts_branch .LBB8_889\n.LBB8_887: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_884\n; %bb.888: ; in Loop: Header=BB8_887 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_884\n.LBB8_889:\n\tglobal_load_b64 v[20:21], v[6:7], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_893\n; %bb.890:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[26:27] offset:40\n\tglobal_load_b64 v[7:8], v6, s[26:27] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[26:27]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s2\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_893\n; %bb.891:\n\ts_mov_b32 s0, 0\n.LBB8_892: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_892\n.LBB8_893:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_getpc_b64 s[2:3]\n\ts_add_u32 s2, s2, .str.6@rel32@lo+4\n\ts_addc_u32 s3, s3, .str.6@rel32@hi+12\n\ts_mov_b32 s0, -1\n\ts_cmp_lg_u64 s[2:3], 0\n\ts_cbranch_scc0 .LBB8_972\n; %bb.894:\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v1, v21 :: v_dual_and_b32 v0, -3, v20\n\tv_mov_b32_e32 v23, 0\n\ts_mov_b64 s[4:5], 46\n\ts_branch .LBB8_896\n.LBB8_895: ; in Loop: Header=BB8_896 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_sub_u32 s4, s4, s6\n\ts_subb_u32 s5, s5, s7\n\ts_add_u32 s2, s2, s6\n\ts_addc_u32 s3, s3, s7\n\ts_cmp_lg_u64 s[4:5], 0\n\ts_cbranch_scc0 .LBB8_971\n.LBB8_896: ; =>This Loop Header: Depth=1\n ; Child Loop BB8_899 Depth 2\n ; Child Loop BB8_906 Depth 2\n ; Child Loop BB8_913 Depth 2\n ; Child Loop BB8_920 Depth 2\n ; Child Loop BB8_927 Depth 2\n ; Child Loop BB8_934 Depth 2\n ; Child Loop BB8_941 Depth 2\n ; Child Loop BB8_948 Depth 2\n ; Child Loop BB8_956 Depth 2\n ; Child Loop BB8_965 Depth 2\n ; Child Loop BB8_970 Depth 2\n\tv_cmp_lt_u64_e64 s0, s[4:5], 56\n ; implicit-def: $sgpr13\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b32 s0, s0, exec_lo\n\ts_cselect_b32 s6, s4, 56\n\ts_cselect_b32 s7, s5, 0\n\ts_cmp_gt_u32 s6, 7\n\ts_mov_b32 s0, -1\n\ts_cbranch_scc1 .LBB8_901\n; %bb.897: ; in Loop: Header=BB8_896 Depth=1\n\tv_mov_b32_e32 v2, 0\n\tv_mov_b32_e32 v3, 0\n\ts_cmp_eq_u32 s6, 0\n\ts_cbranch_scc1 .LBB8_900\n; %bb.898: ; in Loop: Header=BB8_896 Depth=1\n\ts_lshl_b64 s[0:1], s[6:7], 3\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], s[2:3]\n.LBB8_899: ; Parent Loop BB8_896 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v4, v23, s[10:11]\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[4:5], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_add_u32 s10, s10, 1\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s0, s8\n\tv_or_b32_e32 v2, v4, v2\n\tv_or_b32_e32 v3, v5, v3\n\ts_cbranch_scc1 .LBB8_899\n.LBB8_900: ; in Loop: Header=BB8_896 Depth=1\n\ts_mov_b32 s0, 0\n\ts_mov_b32 s13, 0\n.LBB8_901: ; in Loop: Header=BB8_896 Depth=1\n\ts_and_not1_b32 vcc_lo, exec_lo, s0\n\ts_mov_b64 s[0:1], s[2:3]\n\ts_cbranch_vccnz .LBB8_903\n; %bb.902: ; in Loop: Header=BB8_896 Depth=1\n\tglobal_load_b64 v[2:3], v23, s[2:3]\n\ts_add_i32 s13, s6, -8\n\ts_add_u32 s0, s2, 8\n\ts_addc_u32 s1, s3, 0\n.LBB8_903: ; in Loop: Header=BB8_896 Depth=1\n\ts_cmp_gt_u32 s13, 7\n\ts_cbranch_scc1 .LBB8_908\n; %bb.904: ; in Loop: Header=BB8_896 Depth=1\n\tv_mov_b32_e32 v4, 0\n\tv_mov_b32_e32 v5, 0\n\ts_cmp_eq_u32 s13, 0\n\ts_cbranch_scc1 .LBB8_907\n; %bb.905: ; in Loop: Header=BB8_896 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_906: ; Parent Loop BB8_896 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v6, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[6:7], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s13, s10\n\tv_or_b32_e32 v4, v6, v4\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v5, v7, v5\n\ts_cbranch_scc1 .LBB8_906\n.LBB8_907: ; in Loop: Header=BB8_896 Depth=1\n\ts_mov_b32 s12, 0\n\ts_cbranch_execz .LBB8_909\n\ts_branch .LBB8_910\n.LBB8_908: ; in Loop: Header=BB8_896 Depth=1\n ; implicit-def: $vgpr4_vgpr5\n ; implicit-def: $sgpr12\n.LBB8_909: ; in Loop: Header=BB8_896 Depth=1\n\tglobal_load_b64 v[4:5], v23, s[0:1]\n\ts_add_i32 s12, s13, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_910: ; in Loop: Header=BB8_896 Depth=1\n\ts_cmp_gt_u32 s12, 7\n\ts_cbranch_scc1 .LBB8_915\n; %bb.911: ; in Loop: Header=BB8_896 Depth=1\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\ts_cmp_eq_u32 s12, 0\n\ts_cbranch_scc1 .LBB8_914\n; %bb.912: ; in Loop: Header=BB8_896 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_913: ; Parent Loop BB8_896 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v8, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v8\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[8:9], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s12, s10\n\tv_or_b32_e32 v6, v8, v6\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v7, v9, v7\n\ts_cbranch_scc1 .LBB8_913\n.LBB8_914: ; in Loop: Header=BB8_896 Depth=1\n\ts_mov_b32 s13, 0\n\ts_cbranch_execz .LBB8_916\n\ts_branch .LBB8_917\n.LBB8_915: ; in Loop: Header=BB8_896 Depth=1\n ; implicit-def: $sgpr13\n.LBB8_916: ; in Loop: Header=BB8_896 Depth=1\n\tglobal_load_b64 v[6:7], v23, s[0:1]\n\ts_add_i32 s13, s12, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_917: ; in Loop: Header=BB8_896 Depth=1\n\ts_cmp_gt_u32 s13, 7\n\ts_cbranch_scc1 .LBB8_922\n; %bb.918: ; in Loop: Header=BB8_896 Depth=1\n\tv_mov_b32_e32 v8, 0\n\tv_mov_b32_e32 v9, 0\n\ts_cmp_eq_u32 s13, 0\n\ts_cbranch_scc1 .LBB8_921\n; %bb.919: ; in Loop: Header=BB8_896 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_920: ; Parent Loop BB8_896 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v10, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v10\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[10:11], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s13, s10\n\tv_or_b32_e32 v8, v10, v8\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v9, v11, v9\n\ts_cbranch_scc1 .LBB8_920\n.LBB8_921: ; in Loop: Header=BB8_896 Depth=1\n\ts_mov_b32 s12, 0\n\ts_cbranch_execz .LBB8_923\n\ts_branch .LBB8_924\n.LBB8_922: ; in Loop: Header=BB8_896 Depth=1\n ; implicit-def: $vgpr8_vgpr9\n ; implicit-def: $sgpr12\n.LBB8_923: ; in Loop: Header=BB8_896 Depth=1\n\tglobal_load_b64 v[8:9], v23, s[0:1]\n\ts_add_i32 s12, s13, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_924: ; in Loop: Header=BB8_896 Depth=1\n\ts_cmp_gt_u32 s12, 7\n\ts_cbranch_scc1 .LBB8_929\n; %bb.925: ; in Loop: Header=BB8_896 Depth=1\n\tv_mov_b32_e32 v10, 0\n\tv_mov_b32_e32 v11, 0\n\ts_cmp_eq_u32 s12, 0\n\ts_cbranch_scc1 .LBB8_928\n; %bb.926: ; in Loop: Header=BB8_896 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_927: ; Parent Loop BB8_896 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v12, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v12\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[12:13], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s12, s10\n\tv_or_b32_e32 v10, v12, v10\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v11, v13, v11\n\ts_cbranch_scc1 .LBB8_927\n.LBB8_928: ; in Loop: Header=BB8_896 Depth=1\n\ts_mov_b32 s13, 0\n\ts_cbranch_execz .LBB8_930\n\ts_branch .LBB8_931\n.LBB8_929: ; in Loop: Header=BB8_896 Depth=1\n ; implicit-def: $sgpr13\n.LBB8_930: ; in Loop: Header=BB8_896 Depth=1\n\tglobal_load_b64 v[10:11], v23, s[0:1]\n\ts_add_i32 s13, s12, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_931: ; in Loop: Header=BB8_896 Depth=1\n\ts_cmp_gt_u32 s13, 7\n\ts_cbranch_scc1 .LBB8_936\n; %bb.932: ; in Loop: Header=BB8_896 Depth=1\n\tv_mov_b32_e32 v12, 0\n\tv_mov_b32_e32 v13, 0\n\ts_cmp_eq_u32 s13, 0\n\ts_cbranch_scc1 .LBB8_935\n; %bb.933: ; in Loop: Header=BB8_896 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_934: ; Parent Loop BB8_896 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v14, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v14\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[14:15], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s13, s10\n\tv_or_b32_e32 v12, v14, v12\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v13, v15, v13\n\ts_cbranch_scc1 .LBB8_934\n.LBB8_935: ; in Loop: Header=BB8_896 Depth=1\n\ts_mov_b32 s12, 0\n\ts_cbranch_execz .LBB8_937\n\ts_branch .LBB8_938\n.LBB8_936: ; in Loop: Header=BB8_896 Depth=1\n ; implicit-def: $vgpr12_vgpr13\n ; implicit-def: $sgpr12\n.LBB8_937: ; in Loop: Header=BB8_896 Depth=1\n\tglobal_load_b64 v[12:13], v23, s[0:1]\n\ts_add_i32 s12, s13, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_938: ; in Loop: Header=BB8_896 Depth=1\n\ts_cmp_gt_u32 s12, 7\n\ts_cbranch_scc1 .LBB8_943\n; %bb.939: ; in Loop: Header=BB8_896 Depth=1\n\tv_mov_b32_e32 v14, 0\n\tv_mov_b32_e32 v15, 0\n\ts_cmp_eq_u32 s12, 0\n\ts_cbranch_scc1 .LBB8_942\n; %bb.940: ; in Loop: Header=BB8_896 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], s[0:1]\n.LBB8_941: ; Parent Loop BB8_896 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v16, v23, s[10:11]\n\ts_add_i32 s12, s12, -1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v16\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[16:17], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_add_u32 s10, s10, 1\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s12, 0\n\tv_or_b32_e32 v14, v16, v14\n\tv_or_b32_e32 v15, v17, v15\n\ts_cbranch_scc1 .LBB8_941\n.LBB8_942: ; in Loop: Header=BB8_896 Depth=1\n\ts_cbranch_execz .LBB8_944\n\ts_branch .LBB8_945\n.LBB8_943: ; in Loop: Header=BB8_896 Depth=1\n.LBB8_944: ; in Loop: Header=BB8_896 Depth=1\n\tglobal_load_b64 v[14:15], v23, s[0:1]\n.LBB8_945: ; in Loop: Header=BB8_896 Depth=1\n\tv_mov_b32_e32 v22, v41\n\tv_mov_b32_e32 v24, 0\n\tv_mov_b32_e32 v25, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v22\n\tv_cmp_eq_u32_e64 s0, s0, v22\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_951\n; %bb.946: ; in Loop: Header=BB8_896 Depth=1\n\tglobal_load_b64 v[18:19], v23, s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[16:17], v23, s[26:27] offset:40\n\tglobal_load_b64 v[24:25], v23, s[26:27]\n\ts_mov_b32 s8, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v17, v17, v19\n\tv_and_b32_e32 v16, v16, v18\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v17, v17, 24\n\tv_mul_hi_u32 v26, v16, 24\n\tv_mul_lo_u32 v16, v16, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v17, v26, v17\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v16, vcc_lo, v24, v16\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v17, vcc_lo, v25, v17, vcc_lo\n\tglobal_load_b64 v[16:17], v[16:17], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[24:25], v23, v[16:19], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[24:25], v[18:19]\n\ts_cbranch_execz .LBB8_950\n; %bb.947: ; in Loop: Header=BB8_896 Depth=1\n\ts_mov_b32 s9, 0\n\t.p2align\t6\n.LBB8_948: ; Parent Loop BB8_896 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[16:17], v23, s[26:27] offset:40\n\tglobal_load_b64 v[26:27], v23, s[26:27]\n\tv_dual_mov_b32 v18, v24 :: v_dual_mov_b32 v19, v25\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v16, v16, v18\n\tv_and_b32_e32 v17, v17, v19\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[24:25], null, v16, 24, v[26:27]\n\tv_mov_b32_e32 v16, v25\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_mad_u64_u32 v[25:26], null, v17, 24, v[16:17]\n\tglobal_load_b64 v[16:17], v[24:25], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[24:25], v23, v[16:19], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[24:25], v[18:19]\n\ts_or_b32 s9, vcc_lo, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s9\n\ts_cbranch_execnz .LBB8_948\n; %bb.949: ; in Loop: Header=BB8_896 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s9\n.LBB8_950: ; in Loop: Header=BB8_896 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s8\n.LBB8_951: ; in Loop: Header=BB8_896 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_clause 0x1\n\tglobal_load_b64 v[26:27], v23, s[26:27] offset:40\n\tglobal_load_b128 v[16:19], v23, s[26:27]\n\tv_readfirstlane_b32 s8, v24\n\tv_readfirstlane_b32 s9, v25\n\ts_mov_b32 s12, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s10, v26\n\tv_readfirstlane_b32 s11, v27\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[10:11], s[8:9], s[10:11]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_953\n; %bb.952: ; in Loop: Header=BB8_896 Depth=1\n\tv_dual_mov_b32 v24, s12 :: v_dual_mov_b32 v25, 0\n\ts_mul_i32 s12, s11, 24\n\ts_mul_hi_u32 s13, s10, 24\n\tv_dual_mov_b32 v26, 2 :: v_dual_mov_b32 v27, 1\n\ts_add_i32 s13, s13, s12\n\ts_mul_i32 s12, s10, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v28, vcc_lo, v16, s12\n\tv_add_co_ci_u32_e32 v29, vcc_lo, s13, v17, vcc_lo\n\tglobal_store_b128 v[28:29], v[24:27], off offset:8\n.LBB8_953: ; in Loop: Header=BB8_896 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_cmp_gt_u64_e64 vcc_lo, s[4:5], 56\n\tv_or_b32_e32 v24, 2, v0\n\ts_lshl_b64 s[12:13], s[10:11], 12\n\ts_lshl_b32 s1, s6, 2\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\ts_add_i32 s1, s1, 28\n\tv_cndmask_b32_e32 v0, v24, v0, vcc_lo\n\tv_lshlrev_b64 v[24:25], 6, v[22:23]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v18, vcc_lo, v18, s12\n\tv_add_co_ci_u32_e32 v19, vcc_lo, s13, v19, vcc_lo\n\ts_and_b32 s1, s1, 0x1e0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v18, vcc_lo, v18, v24\n\tv_and_or_b32 v0, v0, 0xffffff1f, s1\n\tv_add_co_ci_u32_e32 v19, vcc_lo, v19, v25, vcc_lo\n\ts_clause 0x3\n\tglobal_store_b128 v[18:19], v[0:3], off\n\tglobal_store_b128 v[18:19], v[4:7], off offset:16\n\tglobal_store_b128 v[18:19], v[8:11], off offset:32\n\tglobal_store_b128 v[18:19], v[12:15], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_961\n; %bb.954: ; in Loop: Header=BB8_896 Depth=1\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v23, s[26:27] offset:32 glc\n\tglobal_load_b64 v[0:1], v23, s[26:27] offset:40\n\tv_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s12, v0\n\tv_readfirstlane_b32 s13, v1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[12:13], s[12:13], s[8:9]\n\ts_mul_i32 s13, s13, 24\n\ts_mul_hi_u32 s14, s12, 24\n\ts_mul_i32 s12, s12, 24\n\ts_add_i32 s14, s14, s13\n\tv_add_co_u32 v4, vcc_lo, v16, s12\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s14, v17, vcc_lo\n\ts_mov_b32 s12, exec_lo\n\tglobal_store_b64 v[4:5], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v23, v[6:9], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[2:3], v[8:9]\n\ts_cbranch_execz .LBB8_957\n; %bb.955: ; in Loop: Header=BB8_896 Depth=1\n\ts_mov_b32 s13, 0\n.LBB8_956: ; Parent Loop BB8_896 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v23, v[0:3], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]\n\tv_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0\n\ts_or_b32 s13, vcc_lo, s13\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s13\n\ts_cbranch_execnz .LBB8_956\n.LBB8_957: ; in Loop: Header=BB8_896 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s12\n\tglobal_load_b64 v[0:1], v23, s[26:27] offset:16\n\ts_mov_b32 s13, exec_lo\n\ts_mov_b32 s12, exec_lo\n\tv_mbcnt_lo_u32_b32 v2, s13, 0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_eq_u32_e32 0, v2\n\ts_cbranch_execz .LBB8_959\n; %bb.958: ; in Loop: Header=BB8_896 Depth=1\n\ts_bcnt1_i32_b32 s13, s13\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s13\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off offset:8\n.LBB8_959: ; in Loop: Header=BB8_896 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s12\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\ts_cbranch_vccnz .LBB8_961\n; %bb.960: ; in Loop: Header=BB8_896 Depth=1\n\tglobal_load_b32 v22, v[0:1], off offset:24\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s12, v22\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[2:3], v[22:23], off\n\ts_and_b32 m0, s12, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_961: ; in Loop: Header=BB8_896 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s11, 24\n\ts_mul_hi_u32 s11, s10, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s11, s11, s1\n\ts_mul_i32 s1, s10, 24\n\tv_add_co_u32 v0, vcc_lo, v16, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s11, v17, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_965\n\t.p2align\t6\n.LBB8_962: ; in Loop: Header=BB8_965 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_964\n; %bb.963: ; in Loop: Header=BB8_965 Depth=2\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_965\n\ts_branch .LBB8_967\n\t.p2align\t6\n.LBB8_964: ; in Loop: Header=BB8_896 Depth=1\n\ts_branch .LBB8_967\n.LBB8_965: ; Parent Loop BB8_896 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_962\n; %bb.966: ; in Loop: Header=BB8_965 Depth=2\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_962\n.LBB8_967: ; in Loop: Header=BB8_896 Depth=1\n\tglobal_load_b64 v[0:1], v[18:19], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_895\n; %bb.968: ; in Loop: Header=BB8_896 Depth=1\n\ts_clause 0x2\n\tglobal_load_b64 v[4:5], v23, s[26:27] offset:40\n\tglobal_load_b64 v[8:9], v23, s[26:27] offset:24 glc\n\tglobal_load_b64 v[6:7], v23, s[26:27]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v10, vcc_lo, v4, 1\n\tv_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, v10, s8\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s9, v11, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\tv_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10\n\tv_and_b32_e32 v5, v3, v5\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v4, v2, v4\n\tv_mul_hi_u32 v10, v4, 24\n\tv_mul_lo_u32 v4, v4, 24\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_add_co_u32 v6, vcc_lo, v6, v4\n\tv_mov_b32_e32 v4, v8\n\tv_mul_lo_u32 v5, v5, 24\n\tv_add_nc_u32_e32 v5, v10, v5\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v5, v9\n\tglobal_store_b64 v[6:7], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v23, v[2:5], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_895\n; %bb.969: ; in Loop: Header=BB8_896 Depth=1\n\ts_mov_b32 s0, 0\n.LBB8_970: ; Parent Loop BB8_896 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[8:9], v23, v[2:5], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]\n\tv_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_970\n\ts_branch .LBB8_895\n.LBB8_971:\n\ts_mov_b32 s0, 0\n.LBB8_972:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_b32 vcc_lo, exec_lo, s0\n\ts_cbranch_vccz .LBB8_1000\n; %bb.973:\n\tv_mov_b32_e32 v4, v41\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v4\n\tv_cmp_eq_u32_e64 s0, s0, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_979\n; %bb.974:\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s2, exec_lo\n\tglobal_load_b64 v[8:9], v0, s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[5:6], v0, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v2, v2, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v3, v1, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v3, v2\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, v5, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo\n\tglobal_load_b64 v[6:7], v[1:2], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[6:7], v[8:9]\n\ts_cbranch_execz .LBB8_978\n; %bb.975:\n\ts_mov_b32 s3, 0\n\t.p2align\t6\n.LBB8_976: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[10:11], v0, s[26:27]\n\tv_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v7, v2, v9\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]\n\tv_mov_b32_e32 v1, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]\n\tv_mov_b32_e32 v6, v2\n\tglobal_load_b64 v[6:7], v[5:6], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]\n\ts_or_b32 s3, vcc_lo, s3\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s3\n\ts_cbranch_execnz .LBB8_976\n; %bb.977:\n\ts_or_b32 exec_lo, exec_lo, s3\n.LBB8_978:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s2\n.LBB8_979:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v5, 0\n\tv_readfirstlane_b32 s2, v6\n\tv_readfirstlane_b32 s3, v7\n\ts_mov_b32 s6, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v5, s[26:27] offset:40\n\tglobal_load_b128 v[0:3], v5, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s4, v8\n\tv_readfirstlane_b32 s5, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[4:5], s[2:3], s[4:5]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_981\n; %bb.980:\n\tv_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, 0\n\ts_mul_i32 s6, s5, 24\n\ts_mul_hi_u32 s7, s4, 24\n\tv_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1\n\ts_add_i32 s7, s7, s6\n\ts_mul_i32 s6, s4, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v10, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo\n\tglobal_store_b128 v[10:11], v[6:9], off offset:8\n.LBB8_981:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[6:7], s[4:5], 12\n\ts_mov_b32 s8, 0\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v7, vcc_lo, v2, s6\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo\n\tv_lshlrev_b64 v[2:3], 6, v[4:5]\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_mov_b32_e32 v6, 0\n\tv_and_or_b32 v20, v20, 0xffffff1d, 34\n\tv_add_co_u32 v8, vcc_lo, v7, v2\n\tv_add_co_ci_u32_e32 v9, vcc_lo, v9, v3, vcc_lo\n\tv_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11\n\tv_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10\n\tv_mov_b32_e32 v7, v6\n\ts_clause 0x4\n\tglobal_store_b64 v[8:9], v[20:21], off\n\tglobal_store_b128 v[8:9], v[2:5], off offset:8\n\tglobal_store_b128 v[8:9], v[2:5], off offset:24\n\tglobal_store_b128 v[8:9], v[2:5], off offset:40\n\tglobal_store_b64 v[8:9], v[6:7], off offset:56\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_989\n; %bb.982:\n\tv_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s2\n\tv_mov_b32_e32 v10, s3\n\ts_clause 0x1\n\tglobal_load_b64 v[11:12], v8, s[26:27] offset:32 glc\n\tglobal_load_b64 v[2:3], v8, s[26:27] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\tv_readfirstlane_b32 s7, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[6:7], s[6:7], s[2:3]\n\ts_mul_i32 s7, s7, 24\n\ts_mul_hi_u32 s8, s6, 24\n\ts_mul_i32 s6, s6, 24\n\ts_add_i32 s8, s8, s7\n\tv_add_co_u32 v6, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s8, v1, vcc_lo\n\ts_mov_b32 s6, exec_lo\n\tglobal_store_b64 v[6:7], v[11:12], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[11:12]\n\ts_cbranch_execz .LBB8_985\n; %bb.983:\n\ts_mov_b32 s7, 0\n.LBB8_984: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s7, vcc_lo, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s7\n\ts_cbranch_execnz .LBB8_984\n.LBB8_985:\n\ts_or_b32 exec_lo, exec_lo, s6\n\tv_mov_b32_e32 v2, 0\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 s6, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s7, 0\n\tglobal_load_b64 v[2:3], v2, s[26:27] offset:16\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_987\n; %bb.986:\n\ts_bcnt1_i32_b32 s7, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s7\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_987:\n\ts_or_b32 exec_lo, exec_lo, s6\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_989\n; %bb.988:\n\tglobal_load_b32 v2, v[2:3], off offset:24\n\tv_mov_b32_e32 v3, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_and_b32 m0, s6, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_989:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s5, 24\n\ts_mul_hi_u32 s5, s4, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s5, s5, s1\n\ts_mul_i32 s1, s4, 24\n\tv_add_co_u32 v0, vcc_lo, v0, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_993\n\t.p2align\t6\n.LBB8_990: ; in Loop: Header=BB8_993 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_992\n; %bb.991: ; in Loop: Header=BB8_993 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_993\n\ts_branch .LBB8_995\n\t.p2align\t6\n.LBB8_992:\n\ts_branch .LBB8_995\n.LBB8_993: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_990\n; %bb.994: ; in Loop: Header=BB8_993 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_990\n.LBB8_995:\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_999\n; %bb.996:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[26:27] offset:40\n\tglobal_load_b64 v[7:8], v6, s[26:27] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[26:27]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s2\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_999\n; %bb.997:\n\ts_mov_b32 s0, 0\n.LBB8_998: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_998\n.LBB8_999:\n\ts_or_b32 exec_lo, exec_lo, s1\n.LBB8_1000:\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29\n\ts_add_u32 s8, s22, 8\n\ts_addc_u32 s9, s23, 0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, _Z9printListRN18gpu_linearized_stl4listIfLi170EEE@rel32@lo+4\n\ts_addc_u32 s1, s1, _Z9printListRN18gpu_linearized_stl4listIfLi170EEE@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_dual_mov_b32 v1, 4 :: v_dual_mov_b32 v2, -1\n\ts_movk_i32 s0, 0x558\n\tv_add_nc_u32_e64 v0, s0, 4\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_nc_u32_e32 v1, 0x2a8, v1\n\ts_mov_b32 s0, 1\n\ts_set_inst_prefetch_distance 0x1\n\t.p2align\t6\n.LBB8_1001: ; =>This Inner Loop Header: Depth=1\n\tscratch_load_b32 v3, off, off offset:2748\n\ts_add_i32 s0, s0, -1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_cmp_lg_u32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v3, v3, 2, v1\n\tscratch_load_b32 v4, v3, off\n\ts_waitcnt vmcnt(0)\n\tv_lshlrev_b32_e32 v5, 2, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_nc_u32_e32 v6, v1, v5\n\tv_add_nc_u32_e32 v5, v0, v5\n\tscratch_load_b32 v7, v6, off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 v3, v7, off\n\tscratch_load_b32 v3, v6, off\n\tscratch_load_b32 v7, off, off offset:2748\n\ts_waitcnt vmcnt(1)\n\tv_lshl_add_u32 v3, v3, 2, v0\n\ts_waitcnt vmcnt(0)\n\ts_clause 0x2\n\tscratch_store_b32 v3, v7, off\n\tscratch_store_b32 v5, v2, off\n\tscratch_store_b32 v6, v2, off\n\ts_clause 0x1\n\tscratch_load_b32 v3, off, off offset:2752\n\tscratch_load_b32 v5, off, off offset:2740\n\ts_waitcnt vmcnt(1)\n\tv_add_nc_u32_e32 v3, -1, v3\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v5, v5, 2, v42\n\tscratch_store_b32 off, v3, off offset:2752\n\tscratch_store_b32 v5, v4, off\n\tscratch_load_b32 v3, off, off offset:2740\n\ts_waitcnt vmcnt(0)\n\tv_add_nc_u32_e32 v3, 1, v3\n\tscratch_store_b32 off, v3, off offset:2740\n\ts_cbranch_scc0 .LBB8_1001\n; %bb.1002:\n\ts_set_inst_prefetch_distance 0x2\n\tv_mov_b32_e32 v4, v41\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v4\n\tv_cmp_eq_u32_e64 s0, s0, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1008\n; %bb.1003:\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s2, exec_lo\n\tglobal_load_b64 v[8:9], v0, s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[5:6], v0, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v2, v2, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v3, v1, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v3, v2\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, v5, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo\n\tglobal_load_b64 v[6:7], v[1:2], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[6:7], v[8:9]\n\ts_cbranch_execz .LBB8_1007\n; %bb.1004:\n\ts_mov_b32 s3, 0\n\t.p2align\t6\n.LBB8_1005: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[10:11], v0, s[26:27]\n\tv_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v7, v2, v9\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]\n\tv_mov_b32_e32 v1, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]\n\tv_mov_b32_e32 v6, v2\n\tglobal_load_b64 v[6:7], v[5:6], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]\n\ts_or_b32 s3, vcc_lo, s3\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s3\n\ts_cbranch_execnz .LBB8_1005\n; %bb.1006:\n\ts_or_b32 exec_lo, exec_lo, s3\n.LBB8_1007:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s2\n.LBB8_1008:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v5, 0\n\tv_readfirstlane_b32 s2, v6\n\tv_readfirstlane_b32 s3, v7\n\ts_mov_b32 s6, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v5, s[26:27] offset:40\n\tglobal_load_b128 v[0:3], v5, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s4, v8\n\tv_readfirstlane_b32 s5, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[4:5], s[2:3], s[4:5]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1010\n; %bb.1009:\n\tv_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, 0\n\ts_mul_i32 s6, s5, 24\n\ts_mul_hi_u32 s7, s4, 24\n\tv_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1\n\ts_add_i32 s7, s7, s6\n\ts_mul_i32 s6, s4, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v10, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo\n\tglobal_store_b128 v[10:11], v[6:9], off offset:8\n.LBB8_1010:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[6:7], s[4:5], 12\n\tv_lshlrev_b64 v[4:5], 6, v[4:5]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v2, vcc_lo, v2, s6\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo\n\tv_mov_b32_e32 v3, 0\n\ts_mov_b32 s8, 0\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_add_co_u32 v6, vcc_lo, v2, v4\n\tv_mov_b32_e32 v2, 33\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v4, v3\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8\n\tv_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10\n\tv_mov_b32_e32 v11, s11\n\ts_clause 0x3\n\tglobal_store_b128 v[6:7], v[2:5], off\n\tglobal_store_b128 v[6:7], v[8:11], off offset:16\n\tglobal_store_b128 v[6:7], v[8:11], off offset:32\n\tglobal_store_b128 v[6:7], v[8:11], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1018\n; %bb.1011:\n\tv_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s2\n\tv_mov_b32_e32 v12, s3\n\ts_clause 0x1\n\tglobal_load_b64 v[13:14], v10, s[26:27] offset:32 glc\n\tglobal_load_b64 v[2:3], v10, s[26:27] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\tv_readfirstlane_b32 s7, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[6:7], s[6:7], s[2:3]\n\ts_mul_i32 s7, s7, 24\n\ts_mul_hi_u32 s8, s6, 24\n\ts_mul_i32 s6, s6, 24\n\ts_add_i32 s8, s8, s7\n\tv_add_co_u32 v8, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s8, v1, vcc_lo\n\ts_mov_b32 s6, exec_lo\n\tglobal_store_b64 v[8:9], v[13:14], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[13:14]\n\ts_cbranch_execz .LBB8_1014\n; %bb.1012:\n\ts_mov_b32 s7, 0\n.LBB8_1013: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3\n\ts_sleep 1\n\tglobal_store_b64 v[8:9], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s7, vcc_lo, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s7\n\ts_cbranch_execnz .LBB8_1013\n.LBB8_1014:\n\ts_or_b32 exec_lo, exec_lo, s6\n\tv_mov_b32_e32 v2, 0\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 s6, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s7, 0\n\tglobal_load_b64 v[2:3], v2, s[26:27] offset:16\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_1016\n; %bb.1015:\n\ts_bcnt1_i32_b32 s7, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s7\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_1016:\n\ts_or_b32 exec_lo, exec_lo, s6\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_1018\n; %bb.1017:\n\tglobal_load_b32 v2, v[2:3], off offset:24\n\tv_mov_b32_e32 v3, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_and_b32 m0, s6, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_1018:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s5, 24\n\ts_mul_hi_u32 s5, s4, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s5, s5, s1\n\ts_mul_i32 s1, s4, 24\n\tv_add_co_u32 v0, vcc_lo, v0, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_1022\n\t.p2align\t6\n.LBB8_1019: ; in Loop: Header=BB8_1022 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_1021\n; %bb.1020: ; in Loop: Header=BB8_1022 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_1022\n\ts_branch .LBB8_1024\n\t.p2align\t6\n.LBB8_1021:\n\ts_branch .LBB8_1024\n.LBB8_1022: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1019\n; %bb.1023: ; in Loop: Header=BB8_1022 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_1019\n.LBB8_1024:\n\tglobal_load_b64 v[20:21], v[6:7], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1028\n; %bb.1025:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[26:27] offset:40\n\tglobal_load_b64 v[7:8], v6, s[26:27] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[26:27]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s2\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_1028\n; %bb.1026:\n\ts_mov_b32 s0, 0\n.LBB8_1027: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_1027\n.LBB8_1028:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_getpc_b64 s[2:3]\n\ts_add_u32 s2, s2, .str.7@rel32@lo+4\n\ts_addc_u32 s3, s3, .str.7@rel32@hi+12\n\ts_mov_b32 s0, -1\n\ts_cmp_lg_u64 s[2:3], 0\n\ts_cbranch_scc0 .LBB8_1107\n; %bb.1029:\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v1, v21 :: v_dual_and_b32 v0, -3, v20\n\tv_mov_b32_e32 v23, 0\n\ts_mov_b64 s[4:5], 38\n\ts_branch .LBB8_1031\n.LBB8_1030: ; in Loop: Header=BB8_1031 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_sub_u32 s4, s4, s6\n\ts_subb_u32 s5, s5, s7\n\ts_add_u32 s2, s2, s6\n\ts_addc_u32 s3, s3, s7\n\ts_cmp_lg_u64 s[4:5], 0\n\ts_cbranch_scc0 .LBB8_1106\n.LBB8_1031: ; =>This Loop Header: Depth=1\n ; Child Loop BB8_1034 Depth 2\n ; Child Loop BB8_1041 Depth 2\n ; Child Loop BB8_1048 Depth 2\n ; Child Loop BB8_1055 Depth 2\n ; Child Loop BB8_1062 Depth 2\n ; Child Loop BB8_1069 Depth 2\n ; Child Loop BB8_1076 Depth 2\n ; Child Loop BB8_1083 Depth 2\n ; Child Loop BB8_1091 Depth 2\n ; Child Loop BB8_1100 Depth 2\n ; Child Loop BB8_1105 Depth 2\n\tv_cmp_lt_u64_e64 s0, s[4:5], 56\n ; implicit-def: $sgpr13\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b32 s0, s0, exec_lo\n\ts_cselect_b32 s6, s4, 56\n\ts_cselect_b32 s7, s5, 0\n\ts_cmp_gt_u32 s6, 7\n\ts_mov_b32 s0, -1\n\ts_cbranch_scc1 .LBB8_1036\n; %bb.1032: ; in Loop: Header=BB8_1031 Depth=1\n\tv_mov_b32_e32 v2, 0\n\tv_mov_b32_e32 v3, 0\n\ts_cmp_eq_u32 s6, 0\n\ts_cbranch_scc1 .LBB8_1035\n; %bb.1033: ; in Loop: Header=BB8_1031 Depth=1\n\ts_lshl_b64 s[0:1], s[6:7], 3\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], s[2:3]\n.LBB8_1034: ; Parent Loop BB8_1031 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v4, v23, s[10:11]\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[4:5], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_add_u32 s10, s10, 1\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s0, s8\n\tv_or_b32_e32 v2, v4, v2\n\tv_or_b32_e32 v3, v5, v3\n\ts_cbranch_scc1 .LBB8_1034\n.LBB8_1035: ; in Loop: Header=BB8_1031 Depth=1\n\ts_mov_b32 s0, 0\n\ts_mov_b32 s13, 0\n.LBB8_1036: ; in Loop: Header=BB8_1031 Depth=1\n\ts_and_not1_b32 vcc_lo, exec_lo, s0\n\ts_mov_b64 s[0:1], s[2:3]\n\ts_cbranch_vccnz .LBB8_1038\n; %bb.1037: ; in Loop: Header=BB8_1031 Depth=1\n\tglobal_load_b64 v[2:3], v23, s[2:3]\n\ts_add_i32 s13, s6, -8\n\ts_add_u32 s0, s2, 8\n\ts_addc_u32 s1, s3, 0\n.LBB8_1038: ; in Loop: Header=BB8_1031 Depth=1\n\ts_cmp_gt_u32 s13, 7\n\ts_cbranch_scc1 .LBB8_1043\n; %bb.1039: ; in Loop: Header=BB8_1031 Depth=1\n\tv_mov_b32_e32 v4, 0\n\tv_mov_b32_e32 v5, 0\n\ts_cmp_eq_u32 s13, 0\n\ts_cbranch_scc1 .LBB8_1042\n; %bb.1040: ; in Loop: Header=BB8_1031 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1041: ; Parent Loop BB8_1031 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v6, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[6:7], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s13, s10\n\tv_or_b32_e32 v4, v6, v4\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v5, v7, v5\n\ts_cbranch_scc1 .LBB8_1041\n.LBB8_1042: ; in Loop: Header=BB8_1031 Depth=1\n\ts_mov_b32 s12, 0\n\ts_cbranch_execz .LBB8_1044\n\ts_branch .LBB8_1045\n.LBB8_1043: ; in Loop: Header=BB8_1031 Depth=1\n ; implicit-def: $vgpr4_vgpr5\n ; implicit-def: $sgpr12\n.LBB8_1044: ; in Loop: Header=BB8_1031 Depth=1\n\tglobal_load_b64 v[4:5], v23, s[0:1]\n\ts_add_i32 s12, s13, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1045: ; in Loop: Header=BB8_1031 Depth=1\n\ts_cmp_gt_u32 s12, 7\n\ts_cbranch_scc1 .LBB8_1050\n; %bb.1046: ; in Loop: Header=BB8_1031 Depth=1\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\ts_cmp_eq_u32 s12, 0\n\ts_cbranch_scc1 .LBB8_1049\n; %bb.1047: ; in Loop: Header=BB8_1031 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1048: ; Parent Loop BB8_1031 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v8, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v8\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[8:9], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s12, s10\n\tv_or_b32_e32 v6, v8, v6\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v7, v9, v7\n\ts_cbranch_scc1 .LBB8_1048\n.LBB8_1049: ; in Loop: Header=BB8_1031 Depth=1\n\ts_mov_b32 s13, 0\n\ts_cbranch_execz .LBB8_1051\n\ts_branch .LBB8_1052\n.LBB8_1050: ; in Loop: Header=BB8_1031 Depth=1\n ; implicit-def: $sgpr13\n.LBB8_1051: ; in Loop: Header=BB8_1031 Depth=1\n\tglobal_load_b64 v[6:7], v23, s[0:1]\n\ts_add_i32 s13, s12, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1052: ; in Loop: Header=BB8_1031 Depth=1\n\ts_cmp_gt_u32 s13, 7\n\ts_cbranch_scc1 .LBB8_1057\n; %bb.1053: ; in Loop: Header=BB8_1031 Depth=1\n\tv_mov_b32_e32 v8, 0\n\tv_mov_b32_e32 v9, 0\n\ts_cmp_eq_u32 s13, 0\n\ts_cbranch_scc1 .LBB8_1056\n; %bb.1054: ; in Loop: Header=BB8_1031 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1055: ; Parent Loop BB8_1031 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v10, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v10\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[10:11], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s13, s10\n\tv_or_b32_e32 v8, v10, v8\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v9, v11, v9\n\ts_cbranch_scc1 .LBB8_1055\n.LBB8_1056: ; in Loop: Header=BB8_1031 Depth=1\n\ts_mov_b32 s12, 0\n\ts_cbranch_execz .LBB8_1058\n\ts_branch .LBB8_1059\n.LBB8_1057: ; in Loop: Header=BB8_1031 Depth=1\n ; implicit-def: $vgpr8_vgpr9\n ; implicit-def: $sgpr12\n.LBB8_1058: ; in Loop: Header=BB8_1031 Depth=1\n\tglobal_load_b64 v[8:9], v23, s[0:1]\n\ts_add_i32 s12, s13, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1059: ; in Loop: Header=BB8_1031 Depth=1\n\ts_cmp_gt_u32 s12, 7\n\ts_cbranch_scc1 .LBB8_1064\n; %bb.1060: ; in Loop: Header=BB8_1031 Depth=1\n\tv_mov_b32_e32 v10, 0\n\tv_mov_b32_e32 v11, 0\n\ts_cmp_eq_u32 s12, 0\n\ts_cbranch_scc1 .LBB8_1063\n; %bb.1061: ; in Loop: Header=BB8_1031 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1062: ; Parent Loop BB8_1031 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v12, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v12\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[12:13], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s12, s10\n\tv_or_b32_e32 v10, v12, v10\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v11, v13, v11\n\ts_cbranch_scc1 .LBB8_1062\n.LBB8_1063: ; in Loop: Header=BB8_1031 Depth=1\n\ts_mov_b32 s13, 0\n\ts_cbranch_execz .LBB8_1065\n\ts_branch .LBB8_1066\n.LBB8_1064: ; in Loop: Header=BB8_1031 Depth=1\n ; implicit-def: $sgpr13\n.LBB8_1065: ; in Loop: Header=BB8_1031 Depth=1\n\tglobal_load_b64 v[10:11], v23, s[0:1]\n\ts_add_i32 s13, s12, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1066: ; in Loop: Header=BB8_1031 Depth=1\n\ts_cmp_gt_u32 s13, 7\n\ts_cbranch_scc1 .LBB8_1071\n; %bb.1067: ; in Loop: Header=BB8_1031 Depth=1\n\tv_mov_b32_e32 v12, 0\n\tv_mov_b32_e32 v13, 0\n\ts_cmp_eq_u32 s13, 0\n\ts_cbranch_scc1 .LBB8_1070\n; %bb.1068: ; in Loop: Header=BB8_1031 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1069: ; Parent Loop BB8_1031 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v14, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v14\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[14:15], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s13, s10\n\tv_or_b32_e32 v12, v14, v12\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v13, v15, v13\n\ts_cbranch_scc1 .LBB8_1069\n.LBB8_1070: ; in Loop: Header=BB8_1031 Depth=1\n\ts_mov_b32 s12, 0\n\ts_cbranch_execz .LBB8_1072\n\ts_branch .LBB8_1073\n.LBB8_1071: ; in Loop: Header=BB8_1031 Depth=1\n ; implicit-def: $vgpr12_vgpr13\n ; implicit-def: $sgpr12\n.LBB8_1072: ; in Loop: Header=BB8_1031 Depth=1\n\tglobal_load_b64 v[12:13], v23, s[0:1]\n\ts_add_i32 s12, s13, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1073: ; in Loop: Header=BB8_1031 Depth=1\n\ts_cmp_gt_u32 s12, 7\n\ts_cbranch_scc1 .LBB8_1078\n; %bb.1074: ; in Loop: Header=BB8_1031 Depth=1\n\tv_mov_b32_e32 v14, 0\n\tv_mov_b32_e32 v15, 0\n\ts_cmp_eq_u32 s12, 0\n\ts_cbranch_scc1 .LBB8_1077\n; %bb.1075: ; in Loop: Header=BB8_1031 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], s[0:1]\n.LBB8_1076: ; Parent Loop BB8_1031 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v16, v23, s[10:11]\n\ts_add_i32 s12, s12, -1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v16\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[16:17], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_add_u32 s10, s10, 1\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s12, 0\n\tv_or_b32_e32 v14, v16, v14\n\tv_or_b32_e32 v15, v17, v15\n\ts_cbranch_scc1 .LBB8_1076\n.LBB8_1077: ; in Loop: Header=BB8_1031 Depth=1\n\ts_cbranch_execz .LBB8_1079\n\ts_branch .LBB8_1080\n.LBB8_1078: ; in Loop: Header=BB8_1031 Depth=1\n.LBB8_1079: ; in Loop: Header=BB8_1031 Depth=1\n\tglobal_load_b64 v[14:15], v23, s[0:1]\n.LBB8_1080: ; in Loop: Header=BB8_1031 Depth=1\n\tv_mov_b32_e32 v22, v41\n\tv_mov_b32_e32 v24, 0\n\tv_mov_b32_e32 v25, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v22\n\tv_cmp_eq_u32_e64 s0, s0, v22\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1086\n; %bb.1081: ; in Loop: Header=BB8_1031 Depth=1\n\tglobal_load_b64 v[18:19], v23, s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[16:17], v23, s[26:27] offset:40\n\tglobal_load_b64 v[24:25], v23, s[26:27]\n\ts_mov_b32 s8, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v17, v17, v19\n\tv_and_b32_e32 v16, v16, v18\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v17, v17, 24\n\tv_mul_hi_u32 v26, v16, 24\n\tv_mul_lo_u32 v16, v16, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v17, v26, v17\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v16, vcc_lo, v24, v16\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v17, vcc_lo, v25, v17, vcc_lo\n\tglobal_load_b64 v[16:17], v[16:17], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[24:25], v23, v[16:19], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[24:25], v[18:19]\n\ts_cbranch_execz .LBB8_1085\n; %bb.1082: ; in Loop: Header=BB8_1031 Depth=1\n\ts_mov_b32 s9, 0\n\t.p2align\t6\n.LBB8_1083: ; Parent Loop BB8_1031 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[16:17], v23, s[26:27] offset:40\n\tglobal_load_b64 v[26:27], v23, s[26:27]\n\tv_dual_mov_b32 v18, v24 :: v_dual_mov_b32 v19, v25\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v16, v16, v18\n\tv_and_b32_e32 v17, v17, v19\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[24:25], null, v16, 24, v[26:27]\n\tv_mov_b32_e32 v16, v25\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_mad_u64_u32 v[25:26], null, v17, 24, v[16:17]\n\tglobal_load_b64 v[16:17], v[24:25], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[24:25], v23, v[16:19], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[24:25], v[18:19]\n\ts_or_b32 s9, vcc_lo, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s9\n\ts_cbranch_execnz .LBB8_1083\n; %bb.1084: ; in Loop: Header=BB8_1031 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s9\n.LBB8_1085: ; in Loop: Header=BB8_1031 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s8\n.LBB8_1086: ; in Loop: Header=BB8_1031 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_clause 0x1\n\tglobal_load_b64 v[26:27], v23, s[26:27] offset:40\n\tglobal_load_b128 v[16:19], v23, s[26:27]\n\tv_readfirstlane_b32 s8, v24\n\tv_readfirstlane_b32 s9, v25\n\ts_mov_b32 s12, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s10, v26\n\tv_readfirstlane_b32 s11, v27\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[10:11], s[8:9], s[10:11]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1088\n; %bb.1087: ; in Loop: Header=BB8_1031 Depth=1\n\tv_dual_mov_b32 v24, s12 :: v_dual_mov_b32 v25, 0\n\ts_mul_i32 s12, s11, 24\n\ts_mul_hi_u32 s13, s10, 24\n\tv_dual_mov_b32 v26, 2 :: v_dual_mov_b32 v27, 1\n\ts_add_i32 s13, s13, s12\n\ts_mul_i32 s12, s10, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v28, vcc_lo, v16, s12\n\tv_add_co_ci_u32_e32 v29, vcc_lo, s13, v17, vcc_lo\n\tglobal_store_b128 v[28:29], v[24:27], off offset:8\n.LBB8_1088: ; in Loop: Header=BB8_1031 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_cmp_gt_u64_e64 vcc_lo, s[4:5], 56\n\tv_or_b32_e32 v24, 2, v0\n\ts_lshl_b64 s[12:13], s[10:11], 12\n\ts_lshl_b32 s1, s6, 2\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\ts_add_i32 s1, s1, 28\n\tv_cndmask_b32_e32 v0, v24, v0, vcc_lo\n\tv_lshlrev_b64 v[24:25], 6, v[22:23]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v18, vcc_lo, v18, s12\n\tv_add_co_ci_u32_e32 v19, vcc_lo, s13, v19, vcc_lo\n\ts_and_b32 s1, s1, 0x1e0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v18, vcc_lo, v18, v24\n\tv_and_or_b32 v0, v0, 0xffffff1f, s1\n\tv_add_co_ci_u32_e32 v19, vcc_lo, v19, v25, vcc_lo\n\ts_clause 0x3\n\tglobal_store_b128 v[18:19], v[0:3], off\n\tglobal_store_b128 v[18:19], v[4:7], off offset:16\n\tglobal_store_b128 v[18:19], v[8:11], off offset:32\n\tglobal_store_b128 v[18:19], v[12:15], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1096\n; %bb.1089: ; in Loop: Header=BB8_1031 Depth=1\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v23, s[26:27] offset:32 glc\n\tglobal_load_b64 v[0:1], v23, s[26:27] offset:40\n\tv_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s12, v0\n\tv_readfirstlane_b32 s13, v1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[12:13], s[12:13], s[8:9]\n\ts_mul_i32 s13, s13, 24\n\ts_mul_hi_u32 s14, s12, 24\n\ts_mul_i32 s12, s12, 24\n\ts_add_i32 s14, s14, s13\n\tv_add_co_u32 v4, vcc_lo, v16, s12\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s14, v17, vcc_lo\n\ts_mov_b32 s12, exec_lo\n\tglobal_store_b64 v[4:5], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v23, v[6:9], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[2:3], v[8:9]\n\ts_cbranch_execz .LBB8_1092\n; %bb.1090: ; in Loop: Header=BB8_1031 Depth=1\n\ts_mov_b32 s13, 0\n.LBB8_1091: ; Parent Loop BB8_1031 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v23, v[0:3], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]\n\tv_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0\n\ts_or_b32 s13, vcc_lo, s13\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s13\n\ts_cbranch_execnz .LBB8_1091\n.LBB8_1092: ; in Loop: Header=BB8_1031 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s12\n\tglobal_load_b64 v[0:1], v23, s[26:27] offset:16\n\ts_mov_b32 s13, exec_lo\n\ts_mov_b32 s12, exec_lo\n\tv_mbcnt_lo_u32_b32 v2, s13, 0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_eq_u32_e32 0, v2\n\ts_cbranch_execz .LBB8_1094\n; %bb.1093: ; in Loop: Header=BB8_1031 Depth=1\n\ts_bcnt1_i32_b32 s13, s13\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s13\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off offset:8\n.LBB8_1094: ; in Loop: Header=BB8_1031 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s12\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\ts_cbranch_vccnz .LBB8_1096\n; %bb.1095: ; in Loop: Header=BB8_1031 Depth=1\n\tglobal_load_b32 v22, v[0:1], off offset:24\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s12, v22\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[2:3], v[22:23], off\n\ts_and_b32 m0, s12, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_1096: ; in Loop: Header=BB8_1031 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s11, 24\n\ts_mul_hi_u32 s11, s10, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s11, s11, s1\n\ts_mul_i32 s1, s10, 24\n\tv_add_co_u32 v0, vcc_lo, v16, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s11, v17, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_1100\n\t.p2align\t6\n.LBB8_1097: ; in Loop: Header=BB8_1100 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_1099\n; %bb.1098: ; in Loop: Header=BB8_1100 Depth=2\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_1100\n\ts_branch .LBB8_1102\n\t.p2align\t6\n.LBB8_1099: ; in Loop: Header=BB8_1031 Depth=1\n\ts_branch .LBB8_1102\n.LBB8_1100: ; Parent Loop BB8_1031 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1097\n; %bb.1101: ; in Loop: Header=BB8_1100 Depth=2\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_1097\n.LBB8_1102: ; in Loop: Header=BB8_1031 Depth=1\n\tglobal_load_b64 v[0:1], v[18:19], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1030\n; %bb.1103: ; in Loop: Header=BB8_1031 Depth=1\n\ts_clause 0x2\n\tglobal_load_b64 v[4:5], v23, s[26:27] offset:40\n\tglobal_load_b64 v[8:9], v23, s[26:27] offset:24 glc\n\tglobal_load_b64 v[6:7], v23, s[26:27]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v10, vcc_lo, v4, 1\n\tv_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, v10, s8\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s9, v11, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\tv_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10\n\tv_and_b32_e32 v5, v3, v5\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v4, v2, v4\n\tv_mul_hi_u32 v10, v4, 24\n\tv_mul_lo_u32 v4, v4, 24\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_add_co_u32 v6, vcc_lo, v6, v4\n\tv_mov_b32_e32 v4, v8\n\tv_mul_lo_u32 v5, v5, 24\n\tv_add_nc_u32_e32 v5, v10, v5\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v5, v9\n\tglobal_store_b64 v[6:7], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v23, v[2:5], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_1030\n; %bb.1104: ; in Loop: Header=BB8_1031 Depth=1\n\ts_mov_b32 s0, 0\n.LBB8_1105: ; Parent Loop BB8_1031 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[8:9], v23, v[2:5], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]\n\tv_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_1105\n\ts_branch .LBB8_1030\n.LBB8_1106:\n\ts_mov_b32 s0, 0\n.LBB8_1107:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_b32 vcc_lo, exec_lo, s0\n\ts_cbranch_vccz .LBB8_1135\n; %bb.1108:\n\tv_mov_b32_e32 v4, v41\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v4\n\tv_cmp_eq_u32_e64 s0, s0, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1114\n; %bb.1109:\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s2, exec_lo\n\tglobal_load_b64 v[8:9], v0, s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[5:6], v0, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v2, v2, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v3, v1, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v3, v2\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, v5, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo\n\tglobal_load_b64 v[6:7], v[1:2], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[6:7], v[8:9]\n\ts_cbranch_execz .LBB8_1113\n; %bb.1110:\n\ts_mov_b32 s3, 0\n\t.p2align\t6\n.LBB8_1111: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[10:11], v0, s[26:27]\n\tv_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v7, v2, v9\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]\n\tv_mov_b32_e32 v1, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]\n\tv_mov_b32_e32 v6, v2\n\tglobal_load_b64 v[6:7], v[5:6], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]\n\ts_or_b32 s3, vcc_lo, s3\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s3\n\ts_cbranch_execnz .LBB8_1111\n; %bb.1112:\n\ts_or_b32 exec_lo, exec_lo, s3\n.LBB8_1113:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s2\n.LBB8_1114:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v5, 0\n\tv_readfirstlane_b32 s2, v6\n\tv_readfirstlane_b32 s3, v7\n\ts_mov_b32 s6, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v5, s[26:27] offset:40\n\tglobal_load_b128 v[0:3], v5, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s4, v8\n\tv_readfirstlane_b32 s5, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[4:5], s[2:3], s[4:5]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1116\n; %bb.1115:\n\tv_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, 0\n\ts_mul_i32 s6, s5, 24\n\ts_mul_hi_u32 s7, s4, 24\n\tv_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1\n\ts_add_i32 s7, s7, s6\n\ts_mul_i32 s6, s4, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v10, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo\n\tglobal_store_b128 v[10:11], v[6:9], off offset:8\n.LBB8_1116:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[6:7], s[4:5], 12\n\ts_mov_b32 s8, 0\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v7, vcc_lo, v2, s6\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo\n\tv_lshlrev_b64 v[2:3], 6, v[4:5]\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_mov_b32_e32 v6, 0\n\tv_and_or_b32 v20, v20, 0xffffff1d, 34\n\tv_add_co_u32 v8, vcc_lo, v7, v2\n\tv_add_co_ci_u32_e32 v9, vcc_lo, v9, v3, vcc_lo\n\tv_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11\n\tv_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10\n\tv_mov_b32_e32 v7, v6\n\ts_clause 0x4\n\tglobal_store_b64 v[8:9], v[20:21], off\n\tglobal_store_b128 v[8:9], v[2:5], off offset:8\n\tglobal_store_b128 v[8:9], v[2:5], off offset:24\n\tglobal_store_b128 v[8:9], v[2:5], off offset:40\n\tglobal_store_b64 v[8:9], v[6:7], off offset:56\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1124\n; %bb.1117:\n\tv_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s2\n\tv_mov_b32_e32 v10, s3\n\ts_clause 0x1\n\tglobal_load_b64 v[11:12], v8, s[26:27] offset:32 glc\n\tglobal_load_b64 v[2:3], v8, s[26:27] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\tv_readfirstlane_b32 s7, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[6:7], s[6:7], s[2:3]\n\ts_mul_i32 s7, s7, 24\n\ts_mul_hi_u32 s8, s6, 24\n\ts_mul_i32 s6, s6, 24\n\ts_add_i32 s8, s8, s7\n\tv_add_co_u32 v6, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s8, v1, vcc_lo\n\ts_mov_b32 s6, exec_lo\n\tglobal_store_b64 v[6:7], v[11:12], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[11:12]\n\ts_cbranch_execz .LBB8_1120\n; %bb.1118:\n\ts_mov_b32 s7, 0\n.LBB8_1119: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s7, vcc_lo, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s7\n\ts_cbranch_execnz .LBB8_1119\n.LBB8_1120:\n\ts_or_b32 exec_lo, exec_lo, s6\n\tv_mov_b32_e32 v2, 0\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 s6, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s7, 0\n\tglobal_load_b64 v[2:3], v2, s[26:27] offset:16\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_1122\n; %bb.1121:\n\ts_bcnt1_i32_b32 s7, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s7\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_1122:\n\ts_or_b32 exec_lo, exec_lo, s6\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_1124\n; %bb.1123:\n\tglobal_load_b32 v2, v[2:3], off offset:24\n\tv_mov_b32_e32 v3, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_and_b32 m0, s6, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_1124:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s5, 24\n\ts_mul_hi_u32 s5, s4, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s5, s5, s1\n\ts_mul_i32 s1, s4, 24\n\tv_add_co_u32 v0, vcc_lo, v0, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_1128\n\t.p2align\t6\n.LBB8_1125: ; in Loop: Header=BB8_1128 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_1127\n; %bb.1126: ; in Loop: Header=BB8_1128 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_1128\n\ts_branch .LBB8_1130\n\t.p2align\t6\n.LBB8_1127:\n\ts_branch .LBB8_1130\n.LBB8_1128: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1125\n; %bb.1129: ; in Loop: Header=BB8_1128 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_1125\n.LBB8_1130:\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1134\n; %bb.1131:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[26:27] offset:40\n\tglobal_load_b64 v[7:8], v6, s[26:27] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[26:27]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s2\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_1134\n; %bb.1132:\n\ts_mov_b32 s0, 0\n.LBB8_1133: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_1133\n.LBB8_1134:\n\ts_or_b32 exec_lo, exec_lo, s1\n.LBB8_1135:\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29\n\ts_add_u32 s8, s22, 8\n\ts_addc_u32 s9, s23, 0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, _Z9printListRN18gpu_linearized_stl4listIfLi170EEE@rel32@lo+4\n\ts_addc_u32 s1, s1, _Z9printListRN18gpu_linearized_stl4listIfLi170EEE@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_dual_mov_b32 v1, 4 :: v_dual_mov_b32 v2, -1\n\ts_movk_i32 s0, 0x2a8\n\tv_add_nc_u32_e64 v0, s0, 4\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_nc_u32_e32 v1, 0x558, v1\n\ts_mov_b32 s0, 1\n\ts_set_inst_prefetch_distance 0x1\n\t.p2align\t6\n.LBB8_1136: ; =>This Inner Loop Header: Depth=1\n\tscratch_load_b32 v3, off, off offset:2744\n\ts_add_i32 s0, s0, -1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_cmp_lg_u32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v3, v3, 2, v1\n\tscratch_load_b32 v4, v3, off\n\ts_waitcnt vmcnt(0)\n\tv_lshlrev_b32_e32 v5, 2, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_nc_u32_e32 v6, v1, v5\n\tv_add_nc_u32_e32 v5, v0, v5\n\tscratch_load_b32 v7, v6, off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 v3, v7, off\n\tscratch_load_b32 v3, v6, off\n\tscratch_load_b32 v7, off, off offset:2744\n\ts_waitcnt vmcnt(1)\n\tv_lshl_add_u32 v3, v3, 2, v0\n\ts_waitcnt vmcnt(0)\n\ts_clause 0x2\n\tscratch_store_b32 v3, v7, off\n\tscratch_store_b32 v6, v2, off\n\tscratch_store_b32 v5, v2, off\n\ts_clause 0x1\n\tscratch_load_b32 v3, off, off offset:2752\n\tscratch_load_b32 v5, off, off offset:2740\n\ts_waitcnt vmcnt(1)\n\tv_add_nc_u32_e32 v3, -1, v3\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v5, v5, 2, v42\n\tscratch_store_b32 off, v3, off offset:2752\n\tscratch_store_b32 v5, v4, off\n\tscratch_load_b32 v3, off, off offset:2740\n\ts_waitcnt vmcnt(0)\n\tv_add_nc_u32_e32 v3, 1, v3\n\tscratch_store_b32 off, v3, off offset:2740\n\ts_cbranch_scc0 .LBB8_1136\n; %bb.1137:\n\ts_set_inst_prefetch_distance 0x2\n\tv_mov_b32_e32 v4, v41\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v4\n\tv_cmp_eq_u32_e64 s0, s0, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1143\n; %bb.1138:\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s2, exec_lo\n\tglobal_load_b64 v[8:9], v0, s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[5:6], v0, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v2, v2, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v3, v1, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v3, v2\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, v5, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo\n\tglobal_load_b64 v[6:7], v[1:2], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[6:7], v[8:9]\n\ts_cbranch_execz .LBB8_1142\n; %bb.1139:\n\ts_mov_b32 s3, 0\n\t.p2align\t6\n.LBB8_1140: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[10:11], v0, s[26:27]\n\tv_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v7, v2, v9\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]\n\tv_mov_b32_e32 v1, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]\n\tv_mov_b32_e32 v6, v2\n\tglobal_load_b64 v[6:7], v[5:6], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]\n\ts_or_b32 s3, vcc_lo, s3\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s3\n\ts_cbranch_execnz .LBB8_1140\n; %bb.1141:\n\ts_or_b32 exec_lo, exec_lo, s3\n.LBB8_1142:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s2\n.LBB8_1143:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v5, 0\n\tv_readfirstlane_b32 s2, v6\n\tv_readfirstlane_b32 s3, v7\n\ts_mov_b32 s6, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v5, s[26:27] offset:40\n\tglobal_load_b128 v[0:3], v5, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s4, v8\n\tv_readfirstlane_b32 s5, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[4:5], s[2:3], s[4:5]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1145\n; %bb.1144:\n\tv_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, 0\n\ts_mul_i32 s6, s5, 24\n\ts_mul_hi_u32 s7, s4, 24\n\tv_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1\n\ts_add_i32 s7, s7, s6\n\ts_mul_i32 s6, s4, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v10, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo\n\tglobal_store_b128 v[10:11], v[6:9], off offset:8\n.LBB8_1145:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[6:7], s[4:5], 12\n\tv_lshlrev_b64 v[4:5], 6, v[4:5]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v2, vcc_lo, v2, s6\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo\n\tv_mov_b32_e32 v3, 0\n\ts_mov_b32 s8, 0\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_add_co_u32 v6, vcc_lo, v2, v4\n\tv_mov_b32_e32 v2, 33\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v4, v3\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8\n\tv_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10\n\tv_mov_b32_e32 v11, s11\n\ts_clause 0x3\n\tglobal_store_b128 v[6:7], v[2:5], off\n\tglobal_store_b128 v[6:7], v[8:11], off offset:16\n\tglobal_store_b128 v[6:7], v[8:11], off offset:32\n\tglobal_store_b128 v[6:7], v[8:11], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1153\n; %bb.1146:\n\tv_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s2\n\tv_mov_b32_e32 v12, s3\n\ts_clause 0x1\n\tglobal_load_b64 v[13:14], v10, s[26:27] offset:32 glc\n\tglobal_load_b64 v[2:3], v10, s[26:27] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\tv_readfirstlane_b32 s7, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[6:7], s[6:7], s[2:3]\n\ts_mul_i32 s7, s7, 24\n\ts_mul_hi_u32 s8, s6, 24\n\ts_mul_i32 s6, s6, 24\n\ts_add_i32 s8, s8, s7\n\tv_add_co_u32 v8, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s8, v1, vcc_lo\n\ts_mov_b32 s6, exec_lo\n\tglobal_store_b64 v[8:9], v[13:14], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[13:14]\n\ts_cbranch_execz .LBB8_1149\n; %bb.1147:\n\ts_mov_b32 s7, 0\n.LBB8_1148: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3\n\ts_sleep 1\n\tglobal_store_b64 v[8:9], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s7, vcc_lo, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s7\n\ts_cbranch_execnz .LBB8_1148\n.LBB8_1149:\n\ts_or_b32 exec_lo, exec_lo, s6\n\tv_mov_b32_e32 v2, 0\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 s6, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s7, 0\n\tglobal_load_b64 v[2:3], v2, s[26:27] offset:16\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_1151\n; %bb.1150:\n\ts_bcnt1_i32_b32 s7, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s7\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_1151:\n\ts_or_b32 exec_lo, exec_lo, s6\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_1153\n; %bb.1152:\n\tglobal_load_b32 v2, v[2:3], off offset:24\n\tv_mov_b32_e32 v3, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_and_b32 m0, s6, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_1153:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s5, 24\n\ts_mul_hi_u32 s5, s4, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s5, s5, s1\n\ts_mul_i32 s1, s4, 24\n\tv_add_co_u32 v0, vcc_lo, v0, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_1157\n\t.p2align\t6\n.LBB8_1154: ; in Loop: Header=BB8_1157 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_1156\n; %bb.1155: ; in Loop: Header=BB8_1157 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_1157\n\ts_branch .LBB8_1159\n\t.p2align\t6\n.LBB8_1156:\n\ts_branch .LBB8_1159\n.LBB8_1157: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1154\n; %bb.1158: ; in Loop: Header=BB8_1157 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_1154\n.LBB8_1159:\n\tglobal_load_b64 v[20:21], v[6:7], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1163\n; %bb.1160:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[26:27] offset:40\n\tglobal_load_b64 v[7:8], v6, s[26:27] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[26:27]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s2\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_1163\n; %bb.1161:\n\ts_mov_b32 s0, 0\n.LBB8_1162: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_1162\n.LBB8_1163:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_getpc_b64 s[2:3]\n\ts_add_u32 s2, s2, .str.8@rel32@lo+4\n\ts_addc_u32 s3, s3, .str.8@rel32@hi+12\n\ts_mov_b32 s0, -1\n\ts_cmp_lg_u64 s[2:3], 0\n\ts_cbranch_scc0 .LBB8_1242\n; %bb.1164:\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v1, v21 :: v_dual_and_b32 v0, -3, v20\n\tv_mov_b32_e32 v23, 0\n\ts_mov_b64 s[4:5], 39\n\ts_branch .LBB8_1166\n.LBB8_1165: ; in Loop: Header=BB8_1166 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_sub_u32 s4, s4, s6\n\ts_subb_u32 s5, s5, s7\n\ts_add_u32 s2, s2, s6\n\ts_addc_u32 s3, s3, s7\n\ts_cmp_lg_u64 s[4:5], 0\n\ts_cbranch_scc0 .LBB8_1241\n.LBB8_1166: ; =>This Loop Header: Depth=1\n ; Child Loop BB8_1169 Depth 2\n ; Child Loop BB8_1176 Depth 2\n ; Child Loop BB8_1183 Depth 2\n ; Child Loop BB8_1190 Depth 2\n ; Child Loop BB8_1197 Depth 2\n ; Child Loop BB8_1204 Depth 2\n ; Child Loop BB8_1211 Depth 2\n ; Child Loop BB8_1218 Depth 2\n ; Child Loop BB8_1226 Depth 2\n ; Child Loop BB8_1235 Depth 2\n ; Child Loop BB8_1240 Depth 2\n\tv_cmp_lt_u64_e64 s0, s[4:5], 56\n ; implicit-def: $sgpr13\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b32 s0, s0, exec_lo\n\ts_cselect_b32 s6, s4, 56\n\ts_cselect_b32 s7, s5, 0\n\ts_cmp_gt_u32 s6, 7\n\ts_mov_b32 s0, -1\n\ts_cbranch_scc1 .LBB8_1171\n; %bb.1167: ; in Loop: Header=BB8_1166 Depth=1\n\tv_mov_b32_e32 v2, 0\n\tv_mov_b32_e32 v3, 0\n\ts_cmp_eq_u32 s6, 0\n\ts_cbranch_scc1 .LBB8_1170\n; %bb.1168: ; in Loop: Header=BB8_1166 Depth=1\n\ts_lshl_b64 s[0:1], s[6:7], 3\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], s[2:3]\n.LBB8_1169: ; Parent Loop BB8_1166 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v4, v23, s[10:11]\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[4:5], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_add_u32 s10, s10, 1\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s0, s8\n\tv_or_b32_e32 v2, v4, v2\n\tv_or_b32_e32 v3, v5, v3\n\ts_cbranch_scc1 .LBB8_1169\n.LBB8_1170: ; in Loop: Header=BB8_1166 Depth=1\n\ts_mov_b32 s0, 0\n\ts_mov_b32 s13, 0\n.LBB8_1171: ; in Loop: Header=BB8_1166 Depth=1\n\ts_and_not1_b32 vcc_lo, exec_lo, s0\n\ts_mov_b64 s[0:1], s[2:3]\n\ts_cbranch_vccnz .LBB8_1173\n; %bb.1172: ; in Loop: Header=BB8_1166 Depth=1\n\tglobal_load_b64 v[2:3], v23, s[2:3]\n\ts_add_i32 s13, s6, -8\n\ts_add_u32 s0, s2, 8\n\ts_addc_u32 s1, s3, 0\n.LBB8_1173: ; in Loop: Header=BB8_1166 Depth=1\n\ts_cmp_gt_u32 s13, 7\n\ts_cbranch_scc1 .LBB8_1178\n; %bb.1174: ; in Loop: Header=BB8_1166 Depth=1\n\tv_mov_b32_e32 v4, 0\n\tv_mov_b32_e32 v5, 0\n\ts_cmp_eq_u32 s13, 0\n\ts_cbranch_scc1 .LBB8_1177\n; %bb.1175: ; in Loop: Header=BB8_1166 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1176: ; Parent Loop BB8_1166 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v6, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[6:7], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s13, s10\n\tv_or_b32_e32 v4, v6, v4\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v5, v7, v5\n\ts_cbranch_scc1 .LBB8_1176\n.LBB8_1177: ; in Loop: Header=BB8_1166 Depth=1\n\ts_mov_b32 s12, 0\n\ts_cbranch_execz .LBB8_1179\n\ts_branch .LBB8_1180\n.LBB8_1178: ; in Loop: Header=BB8_1166 Depth=1\n ; implicit-def: $vgpr4_vgpr5\n ; implicit-def: $sgpr12\n.LBB8_1179: ; in Loop: Header=BB8_1166 Depth=1\n\tglobal_load_b64 v[4:5], v23, s[0:1]\n\ts_add_i32 s12, s13, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1180: ; in Loop: Header=BB8_1166 Depth=1\n\ts_cmp_gt_u32 s12, 7\n\ts_cbranch_scc1 .LBB8_1185\n; %bb.1181: ; in Loop: Header=BB8_1166 Depth=1\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\ts_cmp_eq_u32 s12, 0\n\ts_cbranch_scc1 .LBB8_1184\n; %bb.1182: ; in Loop: Header=BB8_1166 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1183: ; Parent Loop BB8_1166 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v8, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v8\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[8:9], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s12, s10\n\tv_or_b32_e32 v6, v8, v6\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v7, v9, v7\n\ts_cbranch_scc1 .LBB8_1183\n.LBB8_1184: ; in Loop: Header=BB8_1166 Depth=1\n\ts_mov_b32 s13, 0\n\ts_cbranch_execz .LBB8_1186\n\ts_branch .LBB8_1187\n.LBB8_1185: ; in Loop: Header=BB8_1166 Depth=1\n ; implicit-def: $sgpr13\n.LBB8_1186: ; in Loop: Header=BB8_1166 Depth=1\n\tglobal_load_b64 v[6:7], v23, s[0:1]\n\ts_add_i32 s13, s12, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1187: ; in Loop: Header=BB8_1166 Depth=1\n\ts_cmp_gt_u32 s13, 7\n\ts_cbranch_scc1 .LBB8_1192\n; %bb.1188: ; in Loop: Header=BB8_1166 Depth=1\n\tv_mov_b32_e32 v8, 0\n\tv_mov_b32_e32 v9, 0\n\ts_cmp_eq_u32 s13, 0\n\ts_cbranch_scc1 .LBB8_1191\n; %bb.1189: ; in Loop: Header=BB8_1166 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1190: ; Parent Loop BB8_1166 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v10, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v10\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[10:11], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s13, s10\n\tv_or_b32_e32 v8, v10, v8\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v9, v11, v9\n\ts_cbranch_scc1 .LBB8_1190\n.LBB8_1191: ; in Loop: Header=BB8_1166 Depth=1\n\ts_mov_b32 s12, 0\n\ts_cbranch_execz .LBB8_1193\n\ts_branch .LBB8_1194\n.LBB8_1192: ; in Loop: Header=BB8_1166 Depth=1\n ; implicit-def: $vgpr8_vgpr9\n ; implicit-def: $sgpr12\n.LBB8_1193: ; in Loop: Header=BB8_1166 Depth=1\n\tglobal_load_b64 v[8:9], v23, s[0:1]\n\ts_add_i32 s12, s13, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1194: ; in Loop: Header=BB8_1166 Depth=1\n\ts_cmp_gt_u32 s12, 7\n\ts_cbranch_scc1 .LBB8_1199\n; %bb.1195: ; in Loop: Header=BB8_1166 Depth=1\n\tv_mov_b32_e32 v10, 0\n\tv_mov_b32_e32 v11, 0\n\ts_cmp_eq_u32 s12, 0\n\ts_cbranch_scc1 .LBB8_1198\n; %bb.1196: ; in Loop: Header=BB8_1166 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1197: ; Parent Loop BB8_1166 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v12, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v12\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[12:13], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s12, s10\n\tv_or_b32_e32 v10, v12, v10\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v11, v13, v11\n\ts_cbranch_scc1 .LBB8_1197\n.LBB8_1198: ; in Loop: Header=BB8_1166 Depth=1\n\ts_mov_b32 s13, 0\n\ts_cbranch_execz .LBB8_1200\n\ts_branch .LBB8_1201\n.LBB8_1199: ; in Loop: Header=BB8_1166 Depth=1\n ; implicit-def: $sgpr13\n.LBB8_1200: ; in Loop: Header=BB8_1166 Depth=1\n\tglobal_load_b64 v[10:11], v23, s[0:1]\n\ts_add_i32 s13, s12, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1201: ; in Loop: Header=BB8_1166 Depth=1\n\ts_cmp_gt_u32 s13, 7\n\ts_cbranch_scc1 .LBB8_1206\n; %bb.1202: ; in Loop: Header=BB8_1166 Depth=1\n\tv_mov_b32_e32 v12, 0\n\tv_mov_b32_e32 v13, 0\n\ts_cmp_eq_u32 s13, 0\n\ts_cbranch_scc1 .LBB8_1205\n; %bb.1203: ; in Loop: Header=BB8_1166 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1204: ; Parent Loop BB8_1166 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v14, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v14\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[14:15], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s13, s10\n\tv_or_b32_e32 v12, v14, v12\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v13, v15, v13\n\ts_cbranch_scc1 .LBB8_1204\n.LBB8_1205: ; in Loop: Header=BB8_1166 Depth=1\n\ts_mov_b32 s12, 0\n\ts_cbranch_execz .LBB8_1207\n\ts_branch .LBB8_1208\n.LBB8_1206: ; in Loop: Header=BB8_1166 Depth=1\n ; implicit-def: $vgpr12_vgpr13\n ; implicit-def: $sgpr12\n.LBB8_1207: ; in Loop: Header=BB8_1166 Depth=1\n\tglobal_load_b64 v[12:13], v23, s[0:1]\n\ts_add_i32 s12, s13, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1208: ; in Loop: Header=BB8_1166 Depth=1\n\ts_cmp_gt_u32 s12, 7\n\ts_cbranch_scc1 .LBB8_1213\n; %bb.1209: ; in Loop: Header=BB8_1166 Depth=1\n\tv_mov_b32_e32 v14, 0\n\tv_mov_b32_e32 v15, 0\n\ts_cmp_eq_u32 s12, 0\n\ts_cbranch_scc1 .LBB8_1212\n; %bb.1210: ; in Loop: Header=BB8_1166 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], s[0:1]\n.LBB8_1211: ; Parent Loop BB8_1166 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v16, v23, s[10:11]\n\ts_add_i32 s12, s12, -1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v16\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[16:17], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_add_u32 s10, s10, 1\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s12, 0\n\tv_or_b32_e32 v14, v16, v14\n\tv_or_b32_e32 v15, v17, v15\n\ts_cbranch_scc1 .LBB8_1211\n.LBB8_1212: ; in Loop: Header=BB8_1166 Depth=1\n\ts_cbranch_execz .LBB8_1214\n\ts_branch .LBB8_1215\n.LBB8_1213: ; in Loop: Header=BB8_1166 Depth=1\n.LBB8_1214: ; in Loop: Header=BB8_1166 Depth=1\n\tglobal_load_b64 v[14:15], v23, s[0:1]\n.LBB8_1215: ; in Loop: Header=BB8_1166 Depth=1\n\tv_mov_b32_e32 v22, v41\n\tv_mov_b32_e32 v24, 0\n\tv_mov_b32_e32 v25, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v22\n\tv_cmp_eq_u32_e64 s0, s0, v22\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1221\n; %bb.1216: ; in Loop: Header=BB8_1166 Depth=1\n\tglobal_load_b64 v[18:19], v23, s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[16:17], v23, s[26:27] offset:40\n\tglobal_load_b64 v[24:25], v23, s[26:27]\n\ts_mov_b32 s8, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v17, v17, v19\n\tv_and_b32_e32 v16, v16, v18\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v17, v17, 24\n\tv_mul_hi_u32 v26, v16, 24\n\tv_mul_lo_u32 v16, v16, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v17, v26, v17\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v16, vcc_lo, v24, v16\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v17, vcc_lo, v25, v17, vcc_lo\n\tglobal_load_b64 v[16:17], v[16:17], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[24:25], v23, v[16:19], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[24:25], v[18:19]\n\ts_cbranch_execz .LBB8_1220\n; %bb.1217: ; in Loop: Header=BB8_1166 Depth=1\n\ts_mov_b32 s9, 0\n\t.p2align\t6\n.LBB8_1218: ; Parent Loop BB8_1166 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[16:17], v23, s[26:27] offset:40\n\tglobal_load_b64 v[26:27], v23, s[26:27]\n\tv_dual_mov_b32 v18, v24 :: v_dual_mov_b32 v19, v25\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v16, v16, v18\n\tv_and_b32_e32 v17, v17, v19\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[24:25], null, v16, 24, v[26:27]\n\tv_mov_b32_e32 v16, v25\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_mad_u64_u32 v[25:26], null, v17, 24, v[16:17]\n\tglobal_load_b64 v[16:17], v[24:25], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[24:25], v23, v[16:19], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[24:25], v[18:19]\n\ts_or_b32 s9, vcc_lo, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s9\n\ts_cbranch_execnz .LBB8_1218\n; %bb.1219: ; in Loop: Header=BB8_1166 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s9\n.LBB8_1220: ; in Loop: Header=BB8_1166 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s8\n.LBB8_1221: ; in Loop: Header=BB8_1166 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_clause 0x1\n\tglobal_load_b64 v[26:27], v23, s[26:27] offset:40\n\tglobal_load_b128 v[16:19], v23, s[26:27]\n\tv_readfirstlane_b32 s8, v24\n\tv_readfirstlane_b32 s9, v25\n\ts_mov_b32 s12, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s10, v26\n\tv_readfirstlane_b32 s11, v27\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[10:11], s[8:9], s[10:11]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1223\n; %bb.1222: ; in Loop: Header=BB8_1166 Depth=1\n\tv_dual_mov_b32 v24, s12 :: v_dual_mov_b32 v25, 0\n\ts_mul_i32 s12, s11, 24\n\ts_mul_hi_u32 s13, s10, 24\n\tv_dual_mov_b32 v26, 2 :: v_dual_mov_b32 v27, 1\n\ts_add_i32 s13, s13, s12\n\ts_mul_i32 s12, s10, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v28, vcc_lo, v16, s12\n\tv_add_co_ci_u32_e32 v29, vcc_lo, s13, v17, vcc_lo\n\tglobal_store_b128 v[28:29], v[24:27], off offset:8\n.LBB8_1223: ; in Loop: Header=BB8_1166 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_cmp_gt_u64_e64 vcc_lo, s[4:5], 56\n\tv_or_b32_e32 v24, 2, v0\n\ts_lshl_b64 s[12:13], s[10:11], 12\n\ts_lshl_b32 s1, s6, 2\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\ts_add_i32 s1, s1, 28\n\tv_cndmask_b32_e32 v0, v24, v0, vcc_lo\n\tv_lshlrev_b64 v[24:25], 6, v[22:23]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v18, vcc_lo, v18, s12\n\tv_add_co_ci_u32_e32 v19, vcc_lo, s13, v19, vcc_lo\n\ts_and_b32 s1, s1, 0x1e0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v18, vcc_lo, v18, v24\n\tv_and_or_b32 v0, v0, 0xffffff1f, s1\n\tv_add_co_ci_u32_e32 v19, vcc_lo, v19, v25, vcc_lo\n\ts_clause 0x3\n\tglobal_store_b128 v[18:19], v[0:3], off\n\tglobal_store_b128 v[18:19], v[4:7], off offset:16\n\tglobal_store_b128 v[18:19], v[8:11], off offset:32\n\tglobal_store_b128 v[18:19], v[12:15], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1231\n; %bb.1224: ; in Loop: Header=BB8_1166 Depth=1\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v23, s[26:27] offset:32 glc\n\tglobal_load_b64 v[0:1], v23, s[26:27] offset:40\n\tv_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s12, v0\n\tv_readfirstlane_b32 s13, v1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[12:13], s[12:13], s[8:9]\n\ts_mul_i32 s13, s13, 24\n\ts_mul_hi_u32 s14, s12, 24\n\ts_mul_i32 s12, s12, 24\n\ts_add_i32 s14, s14, s13\n\tv_add_co_u32 v4, vcc_lo, v16, s12\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s14, v17, vcc_lo\n\ts_mov_b32 s12, exec_lo\n\tglobal_store_b64 v[4:5], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v23, v[6:9], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[2:3], v[8:9]\n\ts_cbranch_execz .LBB8_1227\n; %bb.1225: ; in Loop: Header=BB8_1166 Depth=1\n\ts_mov_b32 s13, 0\n.LBB8_1226: ; Parent Loop BB8_1166 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v23, v[0:3], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]\n\tv_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0\n\ts_or_b32 s13, vcc_lo, s13\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s13\n\ts_cbranch_execnz .LBB8_1226\n.LBB8_1227: ; in Loop: Header=BB8_1166 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s12\n\tglobal_load_b64 v[0:1], v23, s[26:27] offset:16\n\ts_mov_b32 s13, exec_lo\n\ts_mov_b32 s12, exec_lo\n\tv_mbcnt_lo_u32_b32 v2, s13, 0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_eq_u32_e32 0, v2\n\ts_cbranch_execz .LBB8_1229\n; %bb.1228: ; in Loop: Header=BB8_1166 Depth=1\n\ts_bcnt1_i32_b32 s13, s13\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s13\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off offset:8\n.LBB8_1229: ; in Loop: Header=BB8_1166 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s12\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\ts_cbranch_vccnz .LBB8_1231\n; %bb.1230: ; in Loop: Header=BB8_1166 Depth=1\n\tglobal_load_b32 v22, v[0:1], off offset:24\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s12, v22\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[2:3], v[22:23], off\n\ts_and_b32 m0, s12, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_1231: ; in Loop: Header=BB8_1166 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s11, 24\n\ts_mul_hi_u32 s11, s10, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s11, s11, s1\n\ts_mul_i32 s1, s10, 24\n\tv_add_co_u32 v0, vcc_lo, v16, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s11, v17, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_1235\n\t.p2align\t6\n.LBB8_1232: ; in Loop: Header=BB8_1235 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_1234\n; %bb.1233: ; in Loop: Header=BB8_1235 Depth=2\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_1235\n\ts_branch .LBB8_1237\n\t.p2align\t6\n.LBB8_1234: ; in Loop: Header=BB8_1166 Depth=1\n\ts_branch .LBB8_1237\n.LBB8_1235: ; Parent Loop BB8_1166 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1232\n; %bb.1236: ; in Loop: Header=BB8_1235 Depth=2\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_1232\n.LBB8_1237: ; in Loop: Header=BB8_1166 Depth=1\n\tglobal_load_b64 v[0:1], v[18:19], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1165\n; %bb.1238: ; in Loop: Header=BB8_1166 Depth=1\n\ts_clause 0x2\n\tglobal_load_b64 v[4:5], v23, s[26:27] offset:40\n\tglobal_load_b64 v[8:9], v23, s[26:27] offset:24 glc\n\tglobal_load_b64 v[6:7], v23, s[26:27]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v10, vcc_lo, v4, 1\n\tv_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, v10, s8\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s9, v11, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\tv_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10\n\tv_and_b32_e32 v5, v3, v5\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v4, v2, v4\n\tv_mul_hi_u32 v10, v4, 24\n\tv_mul_lo_u32 v4, v4, 24\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_add_co_u32 v6, vcc_lo, v6, v4\n\tv_mov_b32_e32 v4, v8\n\tv_mul_lo_u32 v5, v5, 24\n\tv_add_nc_u32_e32 v5, v10, v5\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v5, v9\n\tglobal_store_b64 v[6:7], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v23, v[2:5], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_1165\n; %bb.1239: ; in Loop: Header=BB8_1166 Depth=1\n\ts_mov_b32 s0, 0\n.LBB8_1240: ; Parent Loop BB8_1166 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[8:9], v23, v[2:5], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]\n\tv_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_1240\n\ts_branch .LBB8_1165\n.LBB8_1241:\n\ts_mov_b32 s0, 0\n.LBB8_1242:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_b32 vcc_lo, exec_lo, s0\n\ts_cbranch_vccz .LBB8_1270\n; %bb.1243:\n\tv_mov_b32_e32 v4, v41\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v4\n\tv_cmp_eq_u32_e64 s0, s0, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1249\n; %bb.1244:\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s2, exec_lo\n\tglobal_load_b64 v[8:9], v0, s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[5:6], v0, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v2, v2, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v3, v1, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v3, v2\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, v5, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo\n\tglobal_load_b64 v[6:7], v[1:2], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[6:7], v[8:9]\n\ts_cbranch_execz .LBB8_1248\n; %bb.1245:\n\ts_mov_b32 s3, 0\n\t.p2align\t6\n.LBB8_1246: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[10:11], v0, s[26:27]\n\tv_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v7, v2, v9\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]\n\tv_mov_b32_e32 v1, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]\n\tv_mov_b32_e32 v6, v2\n\tglobal_load_b64 v[6:7], v[5:6], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]\n\ts_or_b32 s3, vcc_lo, s3\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s3\n\ts_cbranch_execnz .LBB8_1246\n; %bb.1247:\n\ts_or_b32 exec_lo, exec_lo, s3\n.LBB8_1248:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s2\n.LBB8_1249:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v5, 0\n\tv_readfirstlane_b32 s2, v6\n\tv_readfirstlane_b32 s3, v7\n\ts_mov_b32 s6, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v5, s[26:27] offset:40\n\tglobal_load_b128 v[0:3], v5, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s4, v8\n\tv_readfirstlane_b32 s5, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[4:5], s[2:3], s[4:5]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1251\n; %bb.1250:\n\tv_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, 0\n\ts_mul_i32 s6, s5, 24\n\ts_mul_hi_u32 s7, s4, 24\n\tv_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1\n\ts_add_i32 s7, s7, s6\n\ts_mul_i32 s6, s4, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v10, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo\n\tglobal_store_b128 v[10:11], v[6:9], off offset:8\n.LBB8_1251:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[6:7], s[4:5], 12\n\ts_mov_b32 s8, 0\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v7, vcc_lo, v2, s6\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo\n\tv_lshlrev_b64 v[2:3], 6, v[4:5]\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_mov_b32_e32 v6, 0\n\tv_and_or_b32 v20, v20, 0xffffff1d, 34\n\tv_add_co_u32 v8, vcc_lo, v7, v2\n\tv_add_co_ci_u32_e32 v9, vcc_lo, v9, v3, vcc_lo\n\tv_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11\n\tv_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10\n\tv_mov_b32_e32 v7, v6\n\ts_clause 0x4\n\tglobal_store_b64 v[8:9], v[20:21], off\n\tglobal_store_b128 v[8:9], v[2:5], off offset:8\n\tglobal_store_b128 v[8:9], v[2:5], off offset:24\n\tglobal_store_b128 v[8:9], v[2:5], off offset:40\n\tglobal_store_b64 v[8:9], v[6:7], off offset:56\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1259\n; %bb.1252:\n\tv_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s2\n\tv_mov_b32_e32 v10, s3\n\ts_clause 0x1\n\tglobal_load_b64 v[11:12], v8, s[26:27] offset:32 glc\n\tglobal_load_b64 v[2:3], v8, s[26:27] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\tv_readfirstlane_b32 s7, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[6:7], s[6:7], s[2:3]\n\ts_mul_i32 s7, s7, 24\n\ts_mul_hi_u32 s8, s6, 24\n\ts_mul_i32 s6, s6, 24\n\ts_add_i32 s8, s8, s7\n\tv_add_co_u32 v6, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s8, v1, vcc_lo\n\ts_mov_b32 s6, exec_lo\n\tglobal_store_b64 v[6:7], v[11:12], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[11:12]\n\ts_cbranch_execz .LBB8_1255\n; %bb.1253:\n\ts_mov_b32 s7, 0\n.LBB8_1254: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s7, vcc_lo, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s7\n\ts_cbranch_execnz .LBB8_1254\n.LBB8_1255:\n\ts_or_b32 exec_lo, exec_lo, s6\n\tv_mov_b32_e32 v2, 0\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 s6, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s7, 0\n\tglobal_load_b64 v[2:3], v2, s[26:27] offset:16\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_1257\n; %bb.1256:\n\ts_bcnt1_i32_b32 s7, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s7\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_1257:\n\ts_or_b32 exec_lo, exec_lo, s6\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_1259\n; %bb.1258:\n\tglobal_load_b32 v2, v[2:3], off offset:24\n\tv_mov_b32_e32 v3, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_and_b32 m0, s6, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_1259:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s5, 24\n\ts_mul_hi_u32 s5, s4, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s5, s5, s1\n\ts_mul_i32 s1, s4, 24\n\tv_add_co_u32 v0, vcc_lo, v0, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_1263\n\t.p2align\t6\n.LBB8_1260: ; in Loop: Header=BB8_1263 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_1262\n; %bb.1261: ; in Loop: Header=BB8_1263 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_1263\n\ts_branch .LBB8_1265\n\t.p2align\t6\n.LBB8_1262:\n\ts_branch .LBB8_1265\n.LBB8_1263: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1260\n; %bb.1264: ; in Loop: Header=BB8_1263 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_1260\n.LBB8_1265:\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1269\n; %bb.1266:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[26:27] offset:40\n\tglobal_load_b64 v[7:8], v6, s[26:27] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[26:27]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s2\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_1269\n; %bb.1267:\n\ts_mov_b32 s0, 0\n.LBB8_1268: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_1268\n.LBB8_1269:\n\ts_or_b32 exec_lo, exec_lo, s1\n.LBB8_1270:\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29\n\ts_add_u32 s8, s22, 8\n\ts_addc_u32 s9, s23, 0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, _Z9printListRN18gpu_linearized_stl4listIfLi170EEE@rel32@lo+4\n\ts_addc_u32 s1, s1, _Z9printListRN18gpu_linearized_stl4listIfLi170EEE@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_mov_b32_e32 v4, v41\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\tv_readfirstlane_b32 s0, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u32_e64 s0, s0, v4\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1276\n; %bb.1271:\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s2, exec_lo\n\tglobal_load_b64 v[8:9], v0, s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[5:6], v0, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v2, v2, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v3, v1, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v3, v2\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, v5, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo\n\tglobal_load_b64 v[6:7], v[1:2], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[6:7], v[8:9]\n\ts_cbranch_execz .LBB8_1275\n; %bb.1272:\n\ts_mov_b32 s3, 0\n\t.p2align\t6\n.LBB8_1273: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[10:11], v0, s[26:27]\n\tv_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v7, v2, v9\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]\n\tv_mov_b32_e32 v1, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]\n\tv_mov_b32_e32 v6, v2\n\tglobal_load_b64 v[6:7], v[5:6], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]\n\ts_or_b32 s3, vcc_lo, s3\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s3\n\ts_cbranch_execnz .LBB8_1273\n; %bb.1274:\n\ts_or_b32 exec_lo, exec_lo, s3\n.LBB8_1275:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s2\n.LBB8_1276:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v5, 0\n\tv_readfirstlane_b32 s2, v6\n\tv_readfirstlane_b32 s3, v7\n\ts_mov_b32 s6, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v5, s[26:27] offset:40\n\tglobal_load_b128 v[0:3], v5, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s4, v8\n\tv_readfirstlane_b32 s5, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[4:5], s[2:3], s[4:5]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1278\n; %bb.1277:\n\tv_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, 0\n\ts_mul_i32 s6, s5, 24\n\ts_mul_hi_u32 s7, s4, 24\n\tv_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1\n\ts_add_i32 s7, s7, s6\n\ts_mul_i32 s6, s4, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v10, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo\n\tglobal_store_b128 v[10:11], v[6:9], off offset:8\n.LBB8_1278:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[6:7], s[4:5], 12\n\tv_lshlrev_b64 v[4:5], 6, v[4:5]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v2, vcc_lo, v2, s6\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo\n\tv_mov_b32_e32 v3, 0\n\ts_mov_b32 s8, 0\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_add_co_u32 v6, vcc_lo, v2, v4\n\tv_mov_b32_e32 v2, 33\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v4, v3\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8\n\tv_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10\n\tv_mov_b32_e32 v11, s11\n\ts_clause 0x3\n\tglobal_store_b128 v[6:7], v[2:5], off\n\tglobal_store_b128 v[6:7], v[8:11], off offset:16\n\tglobal_store_b128 v[6:7], v[8:11], off offset:32\n\tglobal_store_b128 v[6:7], v[8:11], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1286\n; %bb.1279:\n\tv_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s2\n\tv_mov_b32_e32 v12, s3\n\ts_clause 0x1\n\tglobal_load_b64 v[13:14], v10, s[26:27] offset:32 glc\n\tglobal_load_b64 v[2:3], v10, s[26:27] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\tv_readfirstlane_b32 s7, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[6:7], s[6:7], s[2:3]\n\ts_mul_i32 s7, s7, 24\n\ts_mul_hi_u32 s8, s6, 24\n\ts_mul_i32 s6, s6, 24\n\ts_add_i32 s8, s8, s7\n\tv_add_co_u32 v8, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s8, v1, vcc_lo\n\ts_mov_b32 s6, exec_lo\n\tglobal_store_b64 v[8:9], v[13:14], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[13:14]\n\ts_cbranch_execz .LBB8_1282\n; %bb.1280:\n\ts_mov_b32 s7, 0\n.LBB8_1281: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3\n\ts_sleep 1\n\tglobal_store_b64 v[8:9], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s7, vcc_lo, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s7\n\ts_cbranch_execnz .LBB8_1281\n.LBB8_1282:\n\ts_or_b32 exec_lo, exec_lo, s6\n\tv_mov_b32_e32 v2, 0\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 s6, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s7, 0\n\tglobal_load_b64 v[2:3], v2, s[26:27] offset:16\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_1284\n; %bb.1283:\n\ts_bcnt1_i32_b32 s7, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s7\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_1284:\n\ts_or_b32 exec_lo, exec_lo, s6\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_1286\n; %bb.1285:\n\tglobal_load_b32 v2, v[2:3], off offset:24\n\tv_mov_b32_e32 v3, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_and_b32 m0, s6, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_1286:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s5, 24\n\ts_mul_hi_u32 s5, s4, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s5, s5, s1\n\ts_mul_i32 s1, s4, 24\n\tv_add_co_u32 v0, vcc_lo, v0, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_1290\n\t.p2align\t6\n.LBB8_1287: ; in Loop: Header=BB8_1290 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_1289\n; %bb.1288: ; in Loop: Header=BB8_1290 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_1290\n\ts_branch .LBB8_1292\n\t.p2align\t6\n.LBB8_1289:\n\ts_branch .LBB8_1292\n.LBB8_1290: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1287\n; %bb.1291: ; in Loop: Header=BB8_1290 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_1287\n.LBB8_1292:\n\tglobal_load_b64 v[20:21], v[6:7], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1296\n; %bb.1293:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[26:27] offset:40\n\tglobal_load_b64 v[7:8], v6, s[26:27] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[26:27]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s2\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_1296\n; %bb.1294:\n\ts_mov_b32 s0, 0\n.LBB8_1295: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_1295\n.LBB8_1296:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_getpc_b64 s[2:3]\n\ts_add_u32 s2, s2, .str.9@rel32@lo+4\n\ts_addc_u32 s3, s3, .str.9@rel32@hi+12\n\ts_mov_b32 s0, -1\n\ts_cmp_lg_u64 s[2:3], 0\n\ts_cbranch_scc0 .LBB8_1375\n; %bb.1297:\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v1, v21 :: v_dual_and_b32 v0, -3, v20\n\tv_mov_b32_e32 v23, 0\n\ts_mov_b64 s[4:5], 23\n\ts_branch .LBB8_1299\n.LBB8_1298: ; in Loop: Header=BB8_1299 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_sub_u32 s4, s4, s6\n\ts_subb_u32 s5, s5, s7\n\ts_add_u32 s2, s2, s6\n\ts_addc_u32 s3, s3, s7\n\ts_cmp_lg_u64 s[4:5], 0\n\ts_cbranch_scc0 .LBB8_1374\n.LBB8_1299: ; =>This Loop Header: Depth=1\n ; Child Loop BB8_1302 Depth 2\n ; Child Loop BB8_1309 Depth 2\n ; Child Loop BB8_1316 Depth 2\n ; Child Loop BB8_1323 Depth 2\n ; Child Loop BB8_1330 Depth 2\n ; Child Loop BB8_1337 Depth 2\n ; Child Loop BB8_1344 Depth 2\n ; Child Loop BB8_1351 Depth 2\n ; Child Loop BB8_1359 Depth 2\n ; Child Loop BB8_1368 Depth 2\n ; Child Loop BB8_1373 Depth 2\n\tv_cmp_lt_u64_e64 s0, s[4:5], 56\n ; implicit-def: $sgpr13\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b32 s0, s0, exec_lo\n\ts_cselect_b32 s6, s4, 56\n\ts_cselect_b32 s7, s5, 0\n\ts_cmp_gt_u32 s6, 7\n\ts_mov_b32 s0, -1\n\ts_cbranch_scc1 .LBB8_1304\n; %bb.1300: ; in Loop: Header=BB8_1299 Depth=1\n\tv_mov_b32_e32 v2, 0\n\tv_mov_b32_e32 v3, 0\n\ts_cmp_eq_u32 s6, 0\n\ts_cbranch_scc1 .LBB8_1303\n; %bb.1301: ; in Loop: Header=BB8_1299 Depth=1\n\ts_lshl_b64 s[0:1], s[6:7], 3\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], s[2:3]\n.LBB8_1302: ; Parent Loop BB8_1299 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v4, v23, s[10:11]\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[4:5], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_add_u32 s10, s10, 1\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s0, s8\n\tv_or_b32_e32 v2, v4, v2\n\tv_or_b32_e32 v3, v5, v3\n\ts_cbranch_scc1 .LBB8_1302\n.LBB8_1303: ; in Loop: Header=BB8_1299 Depth=1\n\ts_mov_b32 s0, 0\n\ts_mov_b32 s13, 0\n.LBB8_1304: ; in Loop: Header=BB8_1299 Depth=1\n\ts_and_not1_b32 vcc_lo, exec_lo, s0\n\ts_mov_b64 s[0:1], s[2:3]\n\ts_cbranch_vccnz .LBB8_1306\n; %bb.1305: ; in Loop: Header=BB8_1299 Depth=1\n\tglobal_load_b64 v[2:3], v23, s[2:3]\n\ts_add_i32 s13, s6, -8\n\ts_add_u32 s0, s2, 8\n\ts_addc_u32 s1, s3, 0\n.LBB8_1306: ; in Loop: Header=BB8_1299 Depth=1\n\ts_cmp_gt_u32 s13, 7\n\ts_cbranch_scc1 .LBB8_1311\n; %bb.1307: ; in Loop: Header=BB8_1299 Depth=1\n\tv_mov_b32_e32 v4, 0\n\tv_mov_b32_e32 v5, 0\n\ts_cmp_eq_u32 s13, 0\n\ts_cbranch_scc1 .LBB8_1310\n; %bb.1308: ; in Loop: Header=BB8_1299 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1309: ; Parent Loop BB8_1299 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v6, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[6:7], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s13, s10\n\tv_or_b32_e32 v4, v6, v4\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v5, v7, v5\n\ts_cbranch_scc1 .LBB8_1309\n.LBB8_1310: ; in Loop: Header=BB8_1299 Depth=1\n\ts_mov_b32 s12, 0\n\ts_cbranch_execz .LBB8_1312\n\ts_branch .LBB8_1313\n.LBB8_1311: ; in Loop: Header=BB8_1299 Depth=1\n ; implicit-def: $vgpr4_vgpr5\n ; implicit-def: $sgpr12\n.LBB8_1312: ; in Loop: Header=BB8_1299 Depth=1\n\tglobal_load_b64 v[4:5], v23, s[0:1]\n\ts_add_i32 s12, s13, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1313: ; in Loop: Header=BB8_1299 Depth=1\n\ts_cmp_gt_u32 s12, 7\n\ts_cbranch_scc1 .LBB8_1318\n; %bb.1314: ; in Loop: Header=BB8_1299 Depth=1\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\ts_cmp_eq_u32 s12, 0\n\ts_cbranch_scc1 .LBB8_1317\n; %bb.1315: ; in Loop: Header=BB8_1299 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1316: ; Parent Loop BB8_1299 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v8, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v8\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[8:9], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s12, s10\n\tv_or_b32_e32 v6, v8, v6\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v7, v9, v7\n\ts_cbranch_scc1 .LBB8_1316\n.LBB8_1317: ; in Loop: Header=BB8_1299 Depth=1\n\ts_mov_b32 s13, 0\n\ts_cbranch_execz .LBB8_1319\n\ts_branch .LBB8_1320\n.LBB8_1318: ; in Loop: Header=BB8_1299 Depth=1\n ; implicit-def: $sgpr13\n.LBB8_1319: ; in Loop: Header=BB8_1299 Depth=1\n\tglobal_load_b64 v[6:7], v23, s[0:1]\n\ts_add_i32 s13, s12, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1320: ; in Loop: Header=BB8_1299 Depth=1\n\ts_cmp_gt_u32 s13, 7\n\ts_cbranch_scc1 .LBB8_1325\n; %bb.1321: ; in Loop: Header=BB8_1299 Depth=1\n\tv_mov_b32_e32 v8, 0\n\tv_mov_b32_e32 v9, 0\n\ts_cmp_eq_u32 s13, 0\n\ts_cbranch_scc1 .LBB8_1324\n; %bb.1322: ; in Loop: Header=BB8_1299 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1323: ; Parent Loop BB8_1299 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v10, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v10\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[10:11], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s13, s10\n\tv_or_b32_e32 v8, v10, v8\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v9, v11, v9\n\ts_cbranch_scc1 .LBB8_1323\n.LBB8_1324: ; in Loop: Header=BB8_1299 Depth=1\n\ts_mov_b32 s12, 0\n\ts_cbranch_execz .LBB8_1326\n\ts_branch .LBB8_1327\n.LBB8_1325: ; in Loop: Header=BB8_1299 Depth=1\n ; implicit-def: $vgpr8_vgpr9\n ; implicit-def: $sgpr12\n.LBB8_1326: ; in Loop: Header=BB8_1299 Depth=1\n\tglobal_load_b64 v[8:9], v23, s[0:1]\n\ts_add_i32 s12, s13, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1327: ; in Loop: Header=BB8_1299 Depth=1\n\ts_cmp_gt_u32 s12, 7\n\ts_cbranch_scc1 .LBB8_1332\n; %bb.1328: ; in Loop: Header=BB8_1299 Depth=1\n\tv_mov_b32_e32 v10, 0\n\tv_mov_b32_e32 v11, 0\n\ts_cmp_eq_u32 s12, 0\n\ts_cbranch_scc1 .LBB8_1331\n; %bb.1329: ; in Loop: Header=BB8_1299 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1330: ; Parent Loop BB8_1299 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v12, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v12\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[12:13], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s12, s10\n\tv_or_b32_e32 v10, v12, v10\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v11, v13, v11\n\ts_cbranch_scc1 .LBB8_1330\n.LBB8_1331: ; in Loop: Header=BB8_1299 Depth=1\n\ts_mov_b32 s13, 0\n\ts_cbranch_execz .LBB8_1333\n\ts_branch .LBB8_1334\n.LBB8_1332: ; in Loop: Header=BB8_1299 Depth=1\n ; implicit-def: $sgpr13\n.LBB8_1333: ; in Loop: Header=BB8_1299 Depth=1\n\tglobal_load_b64 v[10:11], v23, s[0:1]\n\ts_add_i32 s13, s12, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1334: ; in Loop: Header=BB8_1299 Depth=1\n\ts_cmp_gt_u32 s13, 7\n\ts_cbranch_scc1 .LBB8_1339\n; %bb.1335: ; in Loop: Header=BB8_1299 Depth=1\n\tv_mov_b32_e32 v12, 0\n\tv_mov_b32_e32 v13, 0\n\ts_cmp_eq_u32 s13, 0\n\ts_cbranch_scc1 .LBB8_1338\n; %bb.1336: ; in Loop: Header=BB8_1299 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1337: ; Parent Loop BB8_1299 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v14, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v14\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[14:15], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s13, s10\n\tv_or_b32_e32 v12, v14, v12\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v13, v15, v13\n\ts_cbranch_scc1 .LBB8_1337\n.LBB8_1338: ; in Loop: Header=BB8_1299 Depth=1\n\ts_mov_b32 s12, 0\n\ts_cbranch_execz .LBB8_1340\n\ts_branch .LBB8_1341\n.LBB8_1339: ; in Loop: Header=BB8_1299 Depth=1\n ; implicit-def: $vgpr12_vgpr13\n ; implicit-def: $sgpr12\n.LBB8_1340: ; in Loop: Header=BB8_1299 Depth=1\n\tglobal_load_b64 v[12:13], v23, s[0:1]\n\ts_add_i32 s12, s13, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1341: ; in Loop: Header=BB8_1299 Depth=1\n\ts_cmp_gt_u32 s12, 7\n\ts_cbranch_scc1 .LBB8_1346\n; %bb.1342: ; in Loop: Header=BB8_1299 Depth=1\n\tv_mov_b32_e32 v14, 0\n\tv_mov_b32_e32 v15, 0\n\ts_cmp_eq_u32 s12, 0\n\ts_cbranch_scc1 .LBB8_1345\n; %bb.1343: ; in Loop: Header=BB8_1299 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], s[0:1]\n.LBB8_1344: ; Parent Loop BB8_1299 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v16, v23, s[10:11]\n\ts_add_i32 s12, s12, -1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v16\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[16:17], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_add_u32 s10, s10, 1\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s12, 0\n\tv_or_b32_e32 v14, v16, v14\n\tv_or_b32_e32 v15, v17, v15\n\ts_cbranch_scc1 .LBB8_1344\n.LBB8_1345: ; in Loop: Header=BB8_1299 Depth=1\n\ts_cbranch_execz .LBB8_1347\n\ts_branch .LBB8_1348\n.LBB8_1346: ; in Loop: Header=BB8_1299 Depth=1\n.LBB8_1347: ; in Loop: Header=BB8_1299 Depth=1\n\tglobal_load_b64 v[14:15], v23, s[0:1]\n.LBB8_1348: ; in Loop: Header=BB8_1299 Depth=1\n\tv_mov_b32_e32 v22, v41\n\tv_mov_b32_e32 v24, 0\n\tv_mov_b32_e32 v25, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v22\n\tv_cmp_eq_u32_e64 s0, s0, v22\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1354\n; %bb.1349: ; in Loop: Header=BB8_1299 Depth=1\n\tglobal_load_b64 v[18:19], v23, s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[16:17], v23, s[26:27] offset:40\n\tglobal_load_b64 v[24:25], v23, s[26:27]\n\ts_mov_b32 s8, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v17, v17, v19\n\tv_and_b32_e32 v16, v16, v18\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v17, v17, 24\n\tv_mul_hi_u32 v26, v16, 24\n\tv_mul_lo_u32 v16, v16, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v17, v26, v17\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v16, vcc_lo, v24, v16\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v17, vcc_lo, v25, v17, vcc_lo\n\tglobal_load_b64 v[16:17], v[16:17], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[24:25], v23, v[16:19], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[24:25], v[18:19]\n\ts_cbranch_execz .LBB8_1353\n; %bb.1350: ; in Loop: Header=BB8_1299 Depth=1\n\ts_mov_b32 s9, 0\n\t.p2align\t6\n.LBB8_1351: ; Parent Loop BB8_1299 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[16:17], v23, s[26:27] offset:40\n\tglobal_load_b64 v[26:27], v23, s[26:27]\n\tv_dual_mov_b32 v18, v24 :: v_dual_mov_b32 v19, v25\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v16, v16, v18\n\tv_and_b32_e32 v17, v17, v19\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[24:25], null, v16, 24, v[26:27]\n\tv_mov_b32_e32 v16, v25\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_mad_u64_u32 v[25:26], null, v17, 24, v[16:17]\n\tglobal_load_b64 v[16:17], v[24:25], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[24:25], v23, v[16:19], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[24:25], v[18:19]\n\ts_or_b32 s9, vcc_lo, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s9\n\ts_cbranch_execnz .LBB8_1351\n; %bb.1352: ; in Loop: Header=BB8_1299 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s9\n.LBB8_1353: ; in Loop: Header=BB8_1299 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s8\n.LBB8_1354: ; in Loop: Header=BB8_1299 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_clause 0x1\n\tglobal_load_b64 v[26:27], v23, s[26:27] offset:40\n\tglobal_load_b128 v[16:19], v23, s[26:27]\n\tv_readfirstlane_b32 s8, v24\n\tv_readfirstlane_b32 s9, v25\n\ts_mov_b32 s12, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s10, v26\n\tv_readfirstlane_b32 s11, v27\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[10:11], s[8:9], s[10:11]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1356\n; %bb.1355: ; in Loop: Header=BB8_1299 Depth=1\n\tv_dual_mov_b32 v24, s12 :: v_dual_mov_b32 v25, 0\n\ts_mul_i32 s12, s11, 24\n\ts_mul_hi_u32 s13, s10, 24\n\tv_dual_mov_b32 v26, 2 :: v_dual_mov_b32 v27, 1\n\ts_add_i32 s13, s13, s12\n\ts_mul_i32 s12, s10, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v28, vcc_lo, v16, s12\n\tv_add_co_ci_u32_e32 v29, vcc_lo, s13, v17, vcc_lo\n\tglobal_store_b128 v[28:29], v[24:27], off offset:8\n.LBB8_1356: ; in Loop: Header=BB8_1299 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_cmp_gt_u64_e64 vcc_lo, s[4:5], 56\n\tv_or_b32_e32 v24, 2, v0\n\ts_lshl_b64 s[12:13], s[10:11], 12\n\ts_lshl_b32 s1, s6, 2\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\ts_add_i32 s1, s1, 28\n\tv_cndmask_b32_e32 v0, v24, v0, vcc_lo\n\tv_lshlrev_b64 v[24:25], 6, v[22:23]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v18, vcc_lo, v18, s12\n\tv_add_co_ci_u32_e32 v19, vcc_lo, s13, v19, vcc_lo\n\ts_and_b32 s1, s1, 0x1e0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v18, vcc_lo, v18, v24\n\tv_and_or_b32 v0, v0, 0xffffff1f, s1\n\tv_add_co_ci_u32_e32 v19, vcc_lo, v19, v25, vcc_lo\n\ts_clause 0x3\n\tglobal_store_b128 v[18:19], v[0:3], off\n\tglobal_store_b128 v[18:19], v[4:7], off offset:16\n\tglobal_store_b128 v[18:19], v[8:11], off offset:32\n\tglobal_store_b128 v[18:19], v[12:15], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1364\n; %bb.1357: ; in Loop: Header=BB8_1299 Depth=1\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v23, s[26:27] offset:32 glc\n\tglobal_load_b64 v[0:1], v23, s[26:27] offset:40\n\tv_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s12, v0\n\tv_readfirstlane_b32 s13, v1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[12:13], s[12:13], s[8:9]\n\ts_mul_i32 s13, s13, 24\n\ts_mul_hi_u32 s14, s12, 24\n\ts_mul_i32 s12, s12, 24\n\ts_add_i32 s14, s14, s13\n\tv_add_co_u32 v4, vcc_lo, v16, s12\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s14, v17, vcc_lo\n\ts_mov_b32 s12, exec_lo\n\tglobal_store_b64 v[4:5], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v23, v[6:9], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[2:3], v[8:9]\n\ts_cbranch_execz .LBB8_1360\n; %bb.1358: ; in Loop: Header=BB8_1299 Depth=1\n\ts_mov_b32 s13, 0\n.LBB8_1359: ; Parent Loop BB8_1299 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v23, v[0:3], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]\n\tv_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0\n\ts_or_b32 s13, vcc_lo, s13\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s13\n\ts_cbranch_execnz .LBB8_1359\n.LBB8_1360: ; in Loop: Header=BB8_1299 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s12\n\tglobal_load_b64 v[0:1], v23, s[26:27] offset:16\n\ts_mov_b32 s13, exec_lo\n\ts_mov_b32 s12, exec_lo\n\tv_mbcnt_lo_u32_b32 v2, s13, 0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_eq_u32_e32 0, v2\n\ts_cbranch_execz .LBB8_1362\n; %bb.1361: ; in Loop: Header=BB8_1299 Depth=1\n\ts_bcnt1_i32_b32 s13, s13\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s13\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off offset:8\n.LBB8_1362: ; in Loop: Header=BB8_1299 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s12\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\ts_cbranch_vccnz .LBB8_1364\n; %bb.1363: ; in Loop: Header=BB8_1299 Depth=1\n\tglobal_load_b32 v22, v[0:1], off offset:24\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s12, v22\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[2:3], v[22:23], off\n\ts_and_b32 m0, s12, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_1364: ; in Loop: Header=BB8_1299 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s11, 24\n\ts_mul_hi_u32 s11, s10, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s11, s11, s1\n\ts_mul_i32 s1, s10, 24\n\tv_add_co_u32 v0, vcc_lo, v16, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s11, v17, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_1368\n\t.p2align\t6\n.LBB8_1365: ; in Loop: Header=BB8_1368 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_1367\n; %bb.1366: ; in Loop: Header=BB8_1368 Depth=2\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_1368\n\ts_branch .LBB8_1370\n\t.p2align\t6\n.LBB8_1367: ; in Loop: Header=BB8_1299 Depth=1\n\ts_branch .LBB8_1370\n.LBB8_1368: ; Parent Loop BB8_1299 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1365\n; %bb.1369: ; in Loop: Header=BB8_1368 Depth=2\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_1365\n.LBB8_1370: ; in Loop: Header=BB8_1299 Depth=1\n\tglobal_load_b64 v[0:1], v[18:19], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1298\n; %bb.1371: ; in Loop: Header=BB8_1299 Depth=1\n\ts_clause 0x2\n\tglobal_load_b64 v[4:5], v23, s[26:27] offset:40\n\tglobal_load_b64 v[8:9], v23, s[26:27] offset:24 glc\n\tglobal_load_b64 v[6:7], v23, s[26:27]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v10, vcc_lo, v4, 1\n\tv_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, v10, s8\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s9, v11, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\tv_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10\n\tv_and_b32_e32 v5, v3, v5\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v4, v2, v4\n\tv_mul_hi_u32 v10, v4, 24\n\tv_mul_lo_u32 v4, v4, 24\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_add_co_u32 v6, vcc_lo, v6, v4\n\tv_mov_b32_e32 v4, v8\n\tv_mul_lo_u32 v5, v5, 24\n\tv_add_nc_u32_e32 v5, v10, v5\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v5, v9\n\tglobal_store_b64 v[6:7], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v23, v[2:5], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_1298\n; %bb.1372: ; in Loop: Header=BB8_1299 Depth=1\n\ts_mov_b32 s0, 0\n.LBB8_1373: ; Parent Loop BB8_1299 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[8:9], v23, v[2:5], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]\n\tv_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_1373\n\ts_branch .LBB8_1298\n.LBB8_1374:\n\ts_mov_b32 s0, 0\n.LBB8_1375:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_b32 vcc_lo, exec_lo, s0\n\ts_cbranch_vccz .LBB8_1403\n; %bb.1376:\n\tv_mov_b32_e32 v4, v41\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v4\n\tv_cmp_eq_u32_e64 s0, s0, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1382\n; %bb.1377:\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s2, exec_lo\n\tglobal_load_b64 v[8:9], v0, s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[5:6], v0, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v2, v2, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v3, v1, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v3, v2\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, v5, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo\n\tglobal_load_b64 v[6:7], v[1:2], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[6:7], v[8:9]\n\ts_cbranch_execz .LBB8_1381\n; %bb.1378:\n\ts_mov_b32 s3, 0\n\t.p2align\t6\n.LBB8_1379: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[10:11], v0, s[26:27]\n\tv_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v7, v2, v9\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]\n\tv_mov_b32_e32 v1, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]\n\tv_mov_b32_e32 v6, v2\n\tglobal_load_b64 v[6:7], v[5:6], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]\n\ts_or_b32 s3, vcc_lo, s3\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s3\n\ts_cbranch_execnz .LBB8_1379\n; %bb.1380:\n\ts_or_b32 exec_lo, exec_lo, s3\n.LBB8_1381:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s2\n.LBB8_1382:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v5, 0\n\tv_readfirstlane_b32 s2, v6\n\tv_readfirstlane_b32 s3, v7\n\ts_mov_b32 s6, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v5, s[26:27] offset:40\n\tglobal_load_b128 v[0:3], v5, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s4, v8\n\tv_readfirstlane_b32 s5, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[4:5], s[2:3], s[4:5]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1384\n; %bb.1383:\n\tv_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, 0\n\ts_mul_i32 s6, s5, 24\n\ts_mul_hi_u32 s7, s4, 24\n\tv_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1\n\ts_add_i32 s7, s7, s6\n\ts_mul_i32 s6, s4, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v10, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo\n\tglobal_store_b128 v[10:11], v[6:9], off offset:8\n.LBB8_1384:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[6:7], s[4:5], 12\n\ts_mov_b32 s8, 0\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v7, vcc_lo, v2, s6\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo\n\tv_lshlrev_b64 v[2:3], 6, v[4:5]\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_mov_b32_e32 v6, 0\n\tv_and_or_b32 v20, v20, 0xffffff1d, 34\n\tv_add_co_u32 v8, vcc_lo, v7, v2\n\tv_add_co_ci_u32_e32 v9, vcc_lo, v9, v3, vcc_lo\n\tv_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11\n\tv_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10\n\tv_mov_b32_e32 v7, v6\n\ts_clause 0x4\n\tglobal_store_b64 v[8:9], v[20:21], off\n\tglobal_store_b128 v[8:9], v[2:5], off offset:8\n\tglobal_store_b128 v[8:9], v[2:5], off offset:24\n\tglobal_store_b128 v[8:9], v[2:5], off offset:40\n\tglobal_store_b64 v[8:9], v[6:7], off offset:56\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1392\n; %bb.1385:\n\tv_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s2\n\tv_mov_b32_e32 v10, s3\n\ts_clause 0x1\n\tglobal_load_b64 v[11:12], v8, s[26:27] offset:32 glc\n\tglobal_load_b64 v[2:3], v8, s[26:27] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\tv_readfirstlane_b32 s7, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[6:7], s[6:7], s[2:3]\n\ts_mul_i32 s7, s7, 24\n\ts_mul_hi_u32 s8, s6, 24\n\ts_mul_i32 s6, s6, 24\n\ts_add_i32 s8, s8, s7\n\tv_add_co_u32 v6, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s8, v1, vcc_lo\n\ts_mov_b32 s6, exec_lo\n\tglobal_store_b64 v[6:7], v[11:12], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[11:12]\n\ts_cbranch_execz .LBB8_1388\n; %bb.1386:\n\ts_mov_b32 s7, 0\n.LBB8_1387: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s7, vcc_lo, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s7\n\ts_cbranch_execnz .LBB8_1387\n.LBB8_1388:\n\ts_or_b32 exec_lo, exec_lo, s6\n\tv_mov_b32_e32 v2, 0\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 s6, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s7, 0\n\tglobal_load_b64 v[2:3], v2, s[26:27] offset:16\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_1390\n; %bb.1389:\n\ts_bcnt1_i32_b32 s7, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s7\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_1390:\n\ts_or_b32 exec_lo, exec_lo, s6\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_1392\n; %bb.1391:\n\tglobal_load_b32 v2, v[2:3], off offset:24\n\tv_mov_b32_e32 v3, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_and_b32 m0, s6, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_1392:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s5, 24\n\ts_mul_hi_u32 s5, s4, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s5, s5, s1\n\ts_mul_i32 s1, s4, 24\n\tv_add_co_u32 v0, vcc_lo, v0, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_1396\n\t.p2align\t6\n.LBB8_1393: ; in Loop: Header=BB8_1396 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_1395\n; %bb.1394: ; in Loop: Header=BB8_1396 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_1396\n\ts_branch .LBB8_1398\n\t.p2align\t6\n.LBB8_1395:\n\ts_branch .LBB8_1398\n.LBB8_1396: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1393\n; %bb.1397: ; in Loop: Header=BB8_1396 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_1393\n.LBB8_1398:\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1402\n; %bb.1399:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[26:27] offset:40\n\tglobal_load_b64 v[7:8], v6, s[26:27] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[26:27]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s2\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_1402\n; %bb.1400:\n\ts_mov_b32 s0, 0\n.LBB8_1401: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_1401\n.LBB8_1402:\n\ts_or_b32 exec_lo, exec_lo, s1\n.LBB8_1403:\n\tscratch_load_b32 v0, off, off offset:2744\n\tv_mov_b32_e32 v4, v41\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v1, 4 :: v_dual_lshlrev_b32 v0, 2, v0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add3_u32 v0, v1, v0, 0x558\n\tscratch_load_b32 v0, v0, off\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v0, v0, 2, 4\n\tscratch_load_b32 v28, v0, off\n\t;;#ASMSTART\n\t;;#ASMEND\n\tv_readfirstlane_b32 s0, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u32_e64 s0, s0, v4\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1409\n; %bb.1404:\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s2, exec_lo\n\tglobal_load_b64 v[8:9], v0, s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[5:6], v0, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v2, v2, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v3, v1, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v3, v2\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, v5, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo\n\tglobal_load_b64 v[6:7], v[1:2], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[6:7], v[8:9]\n\ts_cbranch_execz .LBB8_1408\n; %bb.1405:\n\ts_mov_b32 s3, 0\n\t.p2align\t6\n.LBB8_1406: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[10:11], v0, s[26:27]\n\tv_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v7, v2, v9\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]\n\tv_mov_b32_e32 v1, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]\n\tv_mov_b32_e32 v6, v2\n\tglobal_load_b64 v[6:7], v[5:6], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]\n\ts_or_b32 s3, vcc_lo, s3\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s3\n\ts_cbranch_execnz .LBB8_1406\n; %bb.1407:\n\ts_or_b32 exec_lo, exec_lo, s3\n.LBB8_1408:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s2\n.LBB8_1409:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v5, 0\n\tv_readfirstlane_b32 s2, v6\n\tv_readfirstlane_b32 s3, v7\n\ts_mov_b32 s6, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v5, s[26:27] offset:40\n\tglobal_load_b128 v[0:3], v5, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s4, v8\n\tv_readfirstlane_b32 s5, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[4:5], s[2:3], s[4:5]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1411\n; %bb.1410:\n\tv_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, 0\n\ts_mul_i32 s6, s5, 24\n\ts_mul_hi_u32 s7, s4, 24\n\tv_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1\n\ts_add_i32 s7, s7, s6\n\ts_mul_i32 s6, s4, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v10, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo\n\tglobal_store_b128 v[10:11], v[6:9], off offset:8\n.LBB8_1411:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[6:7], s[4:5], 12\n\tv_lshlrev_b64 v[4:5], 6, v[4:5]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v2, vcc_lo, v2, s6\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo\n\tv_mov_b32_e32 v3, 0\n\ts_mov_b32 s8, 0\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_add_co_u32 v6, vcc_lo, v2, v4\n\tv_mov_b32_e32 v2, 33\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v4, v3\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8\n\tv_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10\n\tv_mov_b32_e32 v11, s11\n\ts_clause 0x3\n\tglobal_store_b128 v[6:7], v[2:5], off\n\tglobal_store_b128 v[6:7], v[8:11], off offset:16\n\tglobal_store_b128 v[6:7], v[8:11], off offset:32\n\tglobal_store_b128 v[6:7], v[8:11], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1419\n; %bb.1412:\n\tv_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s2\n\tv_mov_b32_e32 v12, s3\n\ts_clause 0x1\n\tglobal_load_b64 v[13:14], v10, s[26:27] offset:32 glc\n\tglobal_load_b64 v[2:3], v10, s[26:27] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\tv_readfirstlane_b32 s7, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[6:7], s[6:7], s[2:3]\n\ts_mul_i32 s7, s7, 24\n\ts_mul_hi_u32 s8, s6, 24\n\ts_mul_i32 s6, s6, 24\n\ts_add_i32 s8, s8, s7\n\tv_add_co_u32 v8, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s8, v1, vcc_lo\n\ts_mov_b32 s6, exec_lo\n\tglobal_store_b64 v[8:9], v[13:14], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[13:14]\n\ts_cbranch_execz .LBB8_1415\n; %bb.1413:\n\ts_mov_b32 s7, 0\n.LBB8_1414: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3\n\ts_sleep 1\n\tglobal_store_b64 v[8:9], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s7, vcc_lo, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s7\n\ts_cbranch_execnz .LBB8_1414\n.LBB8_1415:\n\ts_or_b32 exec_lo, exec_lo, s6\n\tv_mov_b32_e32 v2, 0\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 s6, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s7, 0\n\tglobal_load_b64 v[2:3], v2, s[26:27] offset:16\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_1417\n; %bb.1416:\n\ts_bcnt1_i32_b32 s7, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s7\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_1417:\n\ts_or_b32 exec_lo, exec_lo, s6\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_1419\n; %bb.1418:\n\tglobal_load_b32 v2, v[2:3], off offset:24\n\tv_mov_b32_e32 v3, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_and_b32 m0, s6, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_1419:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s5, 24\n\ts_mul_hi_u32 s5, s4, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s5, s5, s1\n\ts_mul_i32 s1, s4, 24\n\tv_add_co_u32 v0, vcc_lo, v0, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_1423\n\t.p2align\t6\n.LBB8_1420: ; in Loop: Header=BB8_1423 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_1422\n; %bb.1421: ; in Loop: Header=BB8_1423 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_1423\n\ts_branch .LBB8_1425\n\t.p2align\t6\n.LBB8_1422:\n\ts_branch .LBB8_1425\n.LBB8_1423: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1420\n; %bb.1424: ; in Loop: Header=BB8_1423 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_1420\n.LBB8_1425:\n\tglobal_load_b64 v[20:21], v[6:7], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1429\n; %bb.1426:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[26:27] offset:40\n\tglobal_load_b64 v[7:8], v6, s[26:27] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[26:27]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s2\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_1429\n; %bb.1427:\n\ts_mov_b32 s0, 0\n.LBB8_1428: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_1428\n.LBB8_1429:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_getpc_b64 s[2:3]\n\ts_add_u32 s2, s2, .str.10@rel32@lo+4\n\ts_addc_u32 s3, s3, .str.10@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_cmp_lg_u64 s[2:3], 0\n\ts_cbranch_scc0 .LBB8_1507\n; %bb.1430:\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v23, 0 :: v_dual_and_b32 v22, 2, v20\n\tv_and_b32_e32 v0, -3, v20\n\ts_mov_b64 s[4:5], 7\n\tv_mov_b32_e32 v1, v21\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_dual_mov_b32 v25, v23 :: v_dual_mov_b32 v24, v22\n\ts_branch .LBB8_1432\n.LBB8_1431: ; in Loop: Header=BB8_1432 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_sub_u32 s4, s4, s6\n\ts_subb_u32 s5, s5, s7\n\ts_add_u32 s2, s2, s6\n\ts_addc_u32 s3, s3, s7\n\ts_cmp_lg_u64 s[4:5], 0\n\ts_cbranch_scc0 .LBB8_1508\n.LBB8_1432: ; =>This Loop Header: Depth=1\n ; Child Loop BB8_1435 Depth 2\n ; Child Loop BB8_1442 Depth 2\n ; Child Loop BB8_1449 Depth 2\n ; Child Loop BB8_1456 Depth 2\n ; Child Loop BB8_1463 Depth 2\n ; Child Loop BB8_1470 Depth 2\n ; Child Loop BB8_1477 Depth 2\n ; Child Loop BB8_1484 Depth 2\n ; Child Loop BB8_1492 Depth 2\n ; Child Loop BB8_1501 Depth 2\n ; Child Loop BB8_1506 Depth 2\n\tv_cmp_lt_u64_e64 s0, s[4:5], 56\n ; implicit-def: $vgpr2_vgpr3\n ; implicit-def: $sgpr13\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b32 s0, s0, exec_lo\n\ts_cselect_b32 s6, s4, 56\n\ts_cselect_b32 s7, s5, 0\n\ts_cmp_gt_u32 s6, 7\n\ts_mov_b32 s0, -1\n\ts_cbranch_scc1 .LBB8_1437\n; %bb.1433: ; in Loop: Header=BB8_1432 Depth=1\n\tv_mov_b32_e32 v2, 0\n\tv_mov_b32_e32 v3, 0\n\ts_cmp_eq_u32 s6, 0\n\ts_cbranch_scc1 .LBB8_1436\n; %bb.1434: ; in Loop: Header=BB8_1432 Depth=1\n\ts_lshl_b64 s[0:1], s[6:7], 3\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], s[2:3]\n.LBB8_1435: ; Parent Loop BB8_1432 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v4, v23, s[10:11]\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[4:5], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_add_u32 s10, s10, 1\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s0, s8\n\tv_or_b32_e32 v2, v4, v2\n\tv_or_b32_e32 v3, v5, v3\n\ts_cbranch_scc1 .LBB8_1435\n.LBB8_1436: ; in Loop: Header=BB8_1432 Depth=1\n\ts_mov_b32 s0, 0\n\ts_mov_b32 s13, 0\n.LBB8_1437: ; in Loop: Header=BB8_1432 Depth=1\n\ts_and_not1_b32 vcc_lo, exec_lo, s0\n\ts_mov_b64 s[0:1], s[2:3]\n\ts_cbranch_vccnz .LBB8_1439\n; %bb.1438: ; in Loop: Header=BB8_1432 Depth=1\n\tglobal_load_b64 v[2:3], v23, s[2:3]\n\ts_add_i32 s13, s6, -8\n\ts_add_u32 s0, s2, 8\n\ts_addc_u32 s1, s3, 0\n.LBB8_1439: ; in Loop: Header=BB8_1432 Depth=1\n\ts_cmp_gt_u32 s13, 7\n\ts_cbranch_scc1 .LBB8_1444\n; %bb.1440: ; in Loop: Header=BB8_1432 Depth=1\n\tv_mov_b32_e32 v4, 0\n\tv_mov_b32_e32 v5, 0\n\ts_cmp_eq_u32 s13, 0\n\ts_cbranch_scc1 .LBB8_1443\n; %bb.1441: ; in Loop: Header=BB8_1432 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1442: ; Parent Loop BB8_1432 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v6, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[6:7], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s13, s10\n\tv_or_b32_e32 v4, v6, v4\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v5, v7, v5\n\ts_cbranch_scc1 .LBB8_1442\n.LBB8_1443: ; in Loop: Header=BB8_1432 Depth=1\n\ts_mov_b32 s12, 0\n\ts_cbranch_execz .LBB8_1445\n\ts_branch .LBB8_1446\n.LBB8_1444: ; in Loop: Header=BB8_1432 Depth=1\n ; implicit-def: $vgpr4_vgpr5\n ; implicit-def: $sgpr12\n.LBB8_1445: ; in Loop: Header=BB8_1432 Depth=1\n\tglobal_load_b64 v[4:5], v23, s[0:1]\n\ts_add_i32 s12, s13, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1446: ; in Loop: Header=BB8_1432 Depth=1\n\ts_cmp_gt_u32 s12, 7\n\ts_cbranch_scc1 .LBB8_1451\n; %bb.1447: ; in Loop: Header=BB8_1432 Depth=1\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\ts_cmp_eq_u32 s12, 0\n\ts_cbranch_scc1 .LBB8_1450\n; %bb.1448: ; in Loop: Header=BB8_1432 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1449: ; Parent Loop BB8_1432 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v8, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v8\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[8:9], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s12, s10\n\tv_or_b32_e32 v6, v8, v6\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v7, v9, v7\n\ts_cbranch_scc1 .LBB8_1449\n.LBB8_1450: ; in Loop: Header=BB8_1432 Depth=1\n\ts_mov_b32 s13, 0\n\ts_cbranch_execz .LBB8_1452\n\ts_branch .LBB8_1453\n.LBB8_1451: ; in Loop: Header=BB8_1432 Depth=1\n ; implicit-def: $sgpr13\n.LBB8_1452: ; in Loop: Header=BB8_1432 Depth=1\n\tglobal_load_b64 v[6:7], v23, s[0:1]\n\ts_add_i32 s13, s12, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1453: ; in Loop: Header=BB8_1432 Depth=1\n\ts_cmp_gt_u32 s13, 7\n\ts_cbranch_scc1 .LBB8_1458\n; %bb.1454: ; in Loop: Header=BB8_1432 Depth=1\n\tv_mov_b32_e32 v8, 0\n\tv_mov_b32_e32 v9, 0\n\ts_cmp_eq_u32 s13, 0\n\ts_cbranch_scc1 .LBB8_1457\n; %bb.1455: ; in Loop: Header=BB8_1432 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1456: ; Parent Loop BB8_1432 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v10, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v10\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[10:11], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s13, s10\n\tv_or_b32_e32 v8, v10, v8\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v9, v11, v9\n\ts_cbranch_scc1 .LBB8_1456\n.LBB8_1457: ; in Loop: Header=BB8_1432 Depth=1\n\ts_mov_b32 s12, 0\n\ts_cbranch_execz .LBB8_1459\n\ts_branch .LBB8_1460\n.LBB8_1458: ; in Loop: Header=BB8_1432 Depth=1\n ; implicit-def: $vgpr8_vgpr9\n ; implicit-def: $sgpr12\n.LBB8_1459: ; in Loop: Header=BB8_1432 Depth=1\n\tglobal_load_b64 v[8:9], v23, s[0:1]\n\ts_add_i32 s12, s13, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1460: ; in Loop: Header=BB8_1432 Depth=1\n\ts_cmp_gt_u32 s12, 7\n\ts_cbranch_scc1 .LBB8_1465\n; %bb.1461: ; in Loop: Header=BB8_1432 Depth=1\n\tv_mov_b32_e32 v10, 0\n\tv_mov_b32_e32 v11, 0\n\ts_cmp_eq_u32 s12, 0\n\ts_cbranch_scc1 .LBB8_1464\n; %bb.1462: ; in Loop: Header=BB8_1432 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1463: ; Parent Loop BB8_1432 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v12, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v12\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[12:13], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s12, s10\n\tv_or_b32_e32 v10, v12, v10\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v11, v13, v11\n\ts_cbranch_scc1 .LBB8_1463\n.LBB8_1464: ; in Loop: Header=BB8_1432 Depth=1\n\ts_mov_b32 s13, 0\n\ts_cbranch_execz .LBB8_1466\n\ts_branch .LBB8_1467\n.LBB8_1465: ; in Loop: Header=BB8_1432 Depth=1\n ; implicit-def: $sgpr13\n.LBB8_1466: ; in Loop: Header=BB8_1432 Depth=1\n\tglobal_load_b64 v[10:11], v23, s[0:1]\n\ts_add_i32 s13, s12, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1467: ; in Loop: Header=BB8_1432 Depth=1\n\ts_cmp_gt_u32 s13, 7\n\ts_cbranch_scc1 .LBB8_1472\n; %bb.1468: ; in Loop: Header=BB8_1432 Depth=1\n\tv_mov_b32_e32 v12, 0\n\tv_mov_b32_e32 v13, 0\n\ts_cmp_eq_u32 s13, 0\n\ts_cbranch_scc1 .LBB8_1471\n; %bb.1469: ; in Loop: Header=BB8_1432 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], 0\n.LBB8_1470: ; Parent Loop BB8_1432 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s14, s0, s10\n\ts_addc_u32 s15, s1, s11\n\ts_add_u32 s10, s10, 1\n\tglobal_load_u8 v14, v23, s[14:15]\n\ts_addc_u32 s11, s11, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v14\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[14:15], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_cmp_lg_u32 s13, s10\n\tv_or_b32_e32 v12, v14, v12\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v13, v15, v13\n\ts_cbranch_scc1 .LBB8_1470\n.LBB8_1471: ; in Loop: Header=BB8_1432 Depth=1\n\ts_mov_b32 s12, 0\n\ts_cbranch_execz .LBB8_1473\n\ts_branch .LBB8_1474\n.LBB8_1472: ; in Loop: Header=BB8_1432 Depth=1\n ; implicit-def: $vgpr12_vgpr13\n ; implicit-def: $sgpr12\n.LBB8_1473: ; in Loop: Header=BB8_1432 Depth=1\n\tglobal_load_b64 v[12:13], v23, s[0:1]\n\ts_add_i32 s12, s13, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB8_1474: ; in Loop: Header=BB8_1432 Depth=1\n\ts_cmp_gt_u32 s12, 7\n\ts_cbranch_scc1 .LBB8_1479\n; %bb.1475: ; in Loop: Header=BB8_1432 Depth=1\n\tv_mov_b32_e32 v14, 0\n\tv_mov_b32_e32 v15, 0\n\ts_cmp_eq_u32 s12, 0\n\ts_cbranch_scc1 .LBB8_1478\n; %bb.1476: ; in Loop: Header=BB8_1432 Depth=1\n\ts_mov_b64 s[8:9], 0\n\ts_mov_b64 s[10:11], s[0:1]\n.LBB8_1477: ; Parent Loop BB8_1432 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v16, v23, s[10:11]\n\ts_add_i32 s12, s12, -1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v22, 0xffff, v16\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[16:17], s8, v[22:23]\n\ts_add_u32 s8, s8, 8\n\ts_addc_u32 s9, s9, 0\n\ts_add_u32 s10, s10, 1\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s12, 0\n\tv_or_b32_e32 v14, v16, v14\n\tv_or_b32_e32 v15, v17, v15\n\ts_cbranch_scc1 .LBB8_1477\n.LBB8_1478: ; in Loop: Header=BB8_1432 Depth=1\n\ts_cbranch_execz .LBB8_1480\n\ts_branch .LBB8_1481\n.LBB8_1479: ; in Loop: Header=BB8_1432 Depth=1\n.LBB8_1480: ; in Loop: Header=BB8_1432 Depth=1\n\tglobal_load_b64 v[14:15], v23, s[0:1]\n.LBB8_1481: ; in Loop: Header=BB8_1432 Depth=1\n\tv_mov_b32_e32 v22, v41\n\tv_mov_b32_e32 v26, 0\n\tv_mov_b32_e32 v27, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v22\n\tv_cmp_eq_u32_e64 s0, s0, v22\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1487\n; %bb.1482: ; in Loop: Header=BB8_1432 Depth=1\n\tglobal_load_b64 v[18:19], v23, s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[16:17], v23, s[26:27] offset:40\n\tglobal_load_b64 v[26:27], v23, s[26:27]\n\ts_mov_b32 s8, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v17, v17, v19\n\tv_and_b32_e32 v16, v16, v18\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v17, v17, 24\n\tv_mul_hi_u32 v29, v16, 24\n\tv_mul_lo_u32 v16, v16, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v17, v29, v17\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v16, vcc_lo, v26, v16\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo\n\tglobal_load_b64 v[16:17], v[16:17], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[26:27], v23, v[16:19], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[26:27], v[18:19]\n\ts_cbranch_execz .LBB8_1486\n; %bb.1483: ; in Loop: Header=BB8_1432 Depth=1\n\ts_mov_b32 s9, 0\n\t.p2align\t6\n.LBB8_1484: ; Parent Loop BB8_1432 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[16:17], v23, s[26:27] offset:40\n\tglobal_load_b64 v[29:30], v23, s[26:27]\n\tv_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v16, v16, v18\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[26:27], null, v16, 24, v[29:30]\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19\n\tv_mad_u64_u32 v[29:30], null, v17, 24, v[16:17]\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_mov_b32_e32 v27, v29\n\tglobal_load_b64 v[16:17], v[26:27], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[26:27], v23, v[16:19], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]\n\ts_or_b32 s9, vcc_lo, s9\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s9\n\ts_cbranch_execnz .LBB8_1484\n; %bb.1485: ; in Loop: Header=BB8_1432 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s9\n.LBB8_1486: ; in Loop: Header=BB8_1432 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s8\n.LBB8_1487: ; in Loop: Header=BB8_1432 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_clause 0x1\n\tglobal_load_b64 v[29:30], v23, s[26:27] offset:40\n\tglobal_load_b128 v[16:19], v23, s[26:27]\n\tv_readfirstlane_b32 s8, v26\n\tv_readfirstlane_b32 s9, v27\n\ts_mov_b32 s12, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s10, v29\n\tv_readfirstlane_b32 s11, v30\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[10:11], s[8:9], s[10:11]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1489\n; %bb.1488: ; in Loop: Header=BB8_1432 Depth=1\n\tv_dual_mov_b32 v29, s12 :: v_dual_mov_b32 v30, 0\n\ts_mul_i32 s12, s11, 24\n\ts_mul_hi_u32 s13, s10, 24\n\tv_dual_mov_b32 v31, 2 :: v_dual_mov_b32 v32, 1\n\ts_add_i32 s13, s13, s12\n\ts_mul_i32 s12, s10, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v26, vcc_lo, v16, s12\n\tv_add_co_ci_u32_e32 v27, vcc_lo, s13, v17, vcc_lo\n\tglobal_store_b128 v[26:27], v[29:32], off offset:8\n.LBB8_1489: ; in Loop: Header=BB8_1432 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_cmp_gt_u64_e64 vcc_lo, s[4:5], 56\n\tv_or_b32_e32 v26, v1, v25\n\tv_or_b32_e32 v27, v0, v24\n\ts_lshl_b64 s[12:13], s[10:11], 12\n\ts_lshl_b32 s1, s6, 2\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\ts_add_i32 s1, s1, 28\n\tv_dual_cndmask_b32 v1, v26, v1 :: v_dual_cndmask_b32 v0, v27, v0\n\tv_lshlrev_b64 v[26:27], 6, v[22:23]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v18, vcc_lo, v18, s12\n\tv_add_co_ci_u32_e32 v19, vcc_lo, s13, v19, vcc_lo\n\ts_and_b32 s1, s1, 0x1e0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v18, vcc_lo, v18, v26\n\tv_and_or_b32 v0, v0, 0xffffff1f, s1\n\tv_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo\n\ts_clause 0x3\n\tglobal_store_b128 v[18:19], v[0:3], off\n\tglobal_store_b128 v[18:19], v[4:7], off offset:16\n\tglobal_store_b128 v[18:19], v[8:11], off offset:32\n\tglobal_store_b128 v[18:19], v[12:15], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1497\n; %bb.1490: ; in Loop: Header=BB8_1432 Depth=1\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v23, s[26:27] offset:32 glc\n\tglobal_load_b64 v[0:1], v23, s[26:27] offset:40\n\tv_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s12, v0\n\tv_readfirstlane_b32 s13, v1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[12:13], s[12:13], s[8:9]\n\ts_mul_i32 s13, s13, 24\n\ts_mul_hi_u32 s14, s12, 24\n\ts_mul_i32 s12, s12, 24\n\ts_add_i32 s14, s14, s13\n\tv_add_co_u32 v4, vcc_lo, v16, s12\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s14, v17, vcc_lo\n\ts_mov_b32 s12, exec_lo\n\tglobal_store_b64 v[4:5], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v23, v[6:9], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[2:3], v[8:9]\n\ts_cbranch_execz .LBB8_1493\n; %bb.1491: ; in Loop: Header=BB8_1432 Depth=1\n\ts_mov_b32 s13, 0\n.LBB8_1492: ; Parent Loop BB8_1432 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v23, v[0:3], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]\n\tv_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0\n\ts_or_b32 s13, vcc_lo, s13\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s13\n\ts_cbranch_execnz .LBB8_1492\n.LBB8_1493: ; in Loop: Header=BB8_1432 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s12\n\tglobal_load_b64 v[0:1], v23, s[26:27] offset:16\n\ts_mov_b32 s13, exec_lo\n\ts_mov_b32 s12, exec_lo\n\tv_mbcnt_lo_u32_b32 v2, s13, 0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_eq_u32_e32 0, v2\n\ts_cbranch_execz .LBB8_1495\n; %bb.1494: ; in Loop: Header=BB8_1432 Depth=1\n\ts_bcnt1_i32_b32 s13, s13\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s13\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off offset:8\n.LBB8_1495: ; in Loop: Header=BB8_1432 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s12\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\ts_cbranch_vccnz .LBB8_1497\n; %bb.1496: ; in Loop: Header=BB8_1432 Depth=1\n\tglobal_load_b32 v22, v[0:1], off offset:24\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s12, v22\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[2:3], v[22:23], off\n\ts_and_b32 m0, s12, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_1497: ; in Loop: Header=BB8_1432 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s11, 24\n\ts_mul_hi_u32 s11, s10, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s11, s11, s1\n\ts_mul_i32 s1, s10, 24\n\tv_add_co_u32 v0, vcc_lo, v16, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s11, v17, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_1501\n\t.p2align\t6\n.LBB8_1498: ; in Loop: Header=BB8_1501 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_1500\n; %bb.1499: ; in Loop: Header=BB8_1501 Depth=2\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_1501\n\ts_branch .LBB8_1503\n\t.p2align\t6\n.LBB8_1500: ; in Loop: Header=BB8_1432 Depth=1\n\ts_branch .LBB8_1503\n.LBB8_1501: ; Parent Loop BB8_1432 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1498\n; %bb.1502: ; in Loop: Header=BB8_1501 Depth=2\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_1498\n.LBB8_1503: ; in Loop: Header=BB8_1432 Depth=1\n\tglobal_load_b64 v[0:1], v[18:19], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1431\n; %bb.1504: ; in Loop: Header=BB8_1432 Depth=1\n\ts_clause 0x2\n\tglobal_load_b64 v[4:5], v23, s[26:27] offset:40\n\tglobal_load_b64 v[8:9], v23, s[26:27] offset:24 glc\n\tglobal_load_b64 v[6:7], v23, s[26:27]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v10, vcc_lo, v4, 1\n\tv_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, v10, s8\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s9, v11, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\tv_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10\n\tv_and_b32_e32 v5, v3, v5\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v4, v2, v4\n\tv_mul_hi_u32 v10, v4, 24\n\tv_mul_lo_u32 v4, v4, 24\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_add_co_u32 v6, vcc_lo, v6, v4\n\tv_mov_b32_e32 v4, v8\n\tv_mul_lo_u32 v5, v5, 24\n\tv_add_nc_u32_e32 v5, v10, v5\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v5, v9\n\tglobal_store_b64 v[6:7], v[8:9], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v23, v[2:5], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_1431\n; %bb.1505: ; in Loop: Header=BB8_1432 Depth=1\n\ts_mov_b32 s0, 0\n.LBB8_1506: ; Parent Loop BB8_1432 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[8:9], v23, v[2:5], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]\n\tv_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_1506\n\ts_branch .LBB8_1431\n.LBB8_1507:\n ; implicit-def: $vgpr0_vgpr1\n\ts_cbranch_execnz .LBB8_1509\n\ts_branch .LBB8_1536\n.LBB8_1508:\n\ts_branch .LBB8_1536\n.LBB8_1509:\n\tv_mov_b32_e32 v4, v41\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v7, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v4\n\tv_cmp_eq_u32_e64 s0, s0, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1515\n; %bb.1510:\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s2, exec_lo\n\tglobal_load_b64 v[8:9], v0, s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[5:6], v0, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v2, v2, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v3, v1, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v3, v2\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, v5, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo\n\tglobal_load_b64 v[6:7], v[1:2], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[6:7], v[8:9]\n\ts_cbranch_execz .LBB8_1514\n; %bb.1511:\n\ts_mov_b32 s3, 0\n\t.p2align\t6\n.LBB8_1512: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[26:27] offset:40\n\tglobal_load_b64 v[10:11], v0, s[26:27]\n\tv_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v7, v2, v9\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]\n\tv_mov_b32_e32 v1, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]\n\tv_mov_b32_e32 v6, v2\n\tglobal_load_b64 v[6:7], v[5:6], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]\n\ts_or_b32 s3, vcc_lo, s3\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s3\n\ts_cbranch_execnz .LBB8_1512\n; %bb.1513:\n\ts_or_b32 exec_lo, exec_lo, s3\n.LBB8_1514:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s2\n.LBB8_1515:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v5, 0\n\tv_readfirstlane_b32 s2, v6\n\tv_readfirstlane_b32 s3, v7\n\ts_mov_b32 s6, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v5, s[26:27] offset:40\n\tglobal_load_b128 v[0:3], v5, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s4, v8\n\tv_readfirstlane_b32 s5, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[4:5], s[2:3], s[4:5]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1517\n; %bb.1516:\n\tv_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, 0\n\ts_mul_i32 s6, s5, 24\n\ts_mul_hi_u32 s7, s4, 24\n\tv_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1\n\ts_add_i32 s7, s7, s6\n\ts_mul_i32 s6, s4, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v10, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo\n\tglobal_store_b128 v[10:11], v[6:9], off offset:8\n.LBB8_1517:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_lshl_b64 s[6:7], s[4:5], 12\n\ts_mov_b32 s8, 0\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v6, vcc_lo, v2, s6\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo\n\tv_lshlrev_b64 v[2:3], 6, v[4:5]\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_mov_b32_e32 v8, 0\n\tv_and_or_b32 v20, v20, 0xffffff1f, 32\n\tv_add_co_u32 v6, vcc_lo, v6, v2\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v3, vcc_lo\n\tv_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11\n\tv_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10\n\tv_mov_b32_e32 v9, v8\n\ts_clause 0x4\n\tglobal_store_b64 v[6:7], v[20:21], off\n\tglobal_store_b128 v[6:7], v[2:5], off offset:8\n\tglobal_store_b128 v[6:7], v[2:5], off offset:24\n\tglobal_store_b128 v[6:7], v[2:5], off offset:40\n\tglobal_store_b64 v[6:7], v[8:9], off offset:56\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1525\n; %bb.1518:\n\tv_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s2\n\tv_mov_b32_e32 v12, s3\n\ts_clause 0x1\n\tglobal_load_b64 v[13:14], v10, s[26:27] offset:32 glc\n\tglobal_load_b64 v[2:3], v10, s[26:27] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\tv_readfirstlane_b32 s7, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[6:7], s[6:7], s[2:3]\n\ts_mul_i32 s7, s7, 24\n\ts_mul_hi_u32 s8, s6, 24\n\ts_mul_i32 s6, s6, 24\n\ts_add_i32 s8, s8, s7\n\tv_add_co_u32 v8, vcc_lo, v0, s6\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s8, v1, vcc_lo\n\ts_mov_b32 s6, exec_lo\n\tglobal_store_b64 v[8:9], v[13:14], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[13:14]\n\ts_cbranch_execz .LBB8_1521\n; %bb.1519:\n\ts_mov_b32 s7, 0\n.LBB8_1520: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3\n\ts_sleep 1\n\tglobal_store_b64 v[8:9], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s7, vcc_lo, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s7\n\ts_cbranch_execnz .LBB8_1520\n.LBB8_1521:\n\ts_or_b32 exec_lo, exec_lo, s6\n\tv_mov_b32_e32 v2, 0\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 s6, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s7, 0\n\tglobal_load_b64 v[2:3], v2, s[26:27] offset:16\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB8_1523\n; %bb.1522:\n\ts_bcnt1_i32_b32 s7, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s7\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB8_1523:\n\ts_or_b32 exec_lo, exec_lo, s6\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB8_1525\n; %bb.1524:\n\tglobal_load_b32 v2, v[2:3], off offset:24\n\tv_mov_b32_e32 v3, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v2\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_and_b32 m0, s6, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_1525:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s5, 24\n\ts_mul_hi_u32 s5, s4, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s5, s5, s1\n\ts_mul_i32 s1, s4, 24\n\tv_add_co_u32 v0, vcc_lo, v0, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_1529\n\t.p2align\t6\n.LBB8_1526: ; in Loop: Header=BB8_1529 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_1528\n; %bb.1527: ; in Loop: Header=BB8_1529 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_1529\n\ts_branch .LBB8_1531\n\t.p2align\t6\n.LBB8_1528:\n\ts_branch .LBB8_1531\n.LBB8_1529: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1526\n; %bb.1530: ; in Loop: Header=BB8_1529 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_1526\n.LBB8_1531:\n\tglobal_load_b64 v[0:1], v[6:7], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1535\n; %bb.1532:\n\tv_mov_b32_e32 v8, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[4:5], v8, s[26:27] offset:40\n\tglobal_load_b64 v[9:10], v8, s[26:27] offset:24 glc\n\tglobal_load_b64 v[6:7], v8, s[26:27]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v11, vcc_lo, v4, 1\n\tv_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, v11, s2\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s3, v12, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\tv_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11\n\tv_and_b32_e32 v5, v3, v5\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v4, v2, v4\n\tv_mul_lo_u32 v5, v5, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v11, v4, 24\n\tv_mul_lo_u32 v4, v4, 24\n\tv_add_nc_u32_e32 v5, v11, v5\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v6, vcc_lo, v6, v4\n\tv_mov_b32_e32 v4, v9\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v5, v10\n\tglobal_store_b64 v[6:7], v[9:10], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_1535\n; %bb.1533:\n\ts_mov_b32 s0, 0\n.LBB8_1534: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]\n\tv_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_1534\n.LBB8_1535:\n\ts_or_b32 exec_lo, exec_lo, s1\n.LBB8_1536:\n\t;;#ASMSTART\n\t;;#ASMEND\n\tv_readfirstlane_b32 s0, v41\n\tv_mov_b32_e32 v2, 0\n\tv_mov_b32_e32 v3, 0\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u32_e64 s0, s0, v41\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1542\n; %bb.1537:\n\tv_mov_b32_e32 v4, 0\n\ts_mov_b32 s2, exec_lo\n\tglobal_load_b64 v[7:8], v4, s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[2:3], v4, s[26:27] offset:40\n\tglobal_load_b64 v[5:6], v4, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v3, v3, v8\n\tv_and_b32_e32 v2, v2, v7\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v3, v3, 24\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v2, vcc_lo, v5, v2\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v3, vcc_lo, v6, v3, vcc_lo\n\tglobal_load_b64 v[5:6], v[2:3], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[2:3], v4, v[5:8], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[2:3], v[7:8]\n\ts_cbranch_execz .LBB8_1541\n; %bb.1538:\n\ts_mov_b32 s3, 0\n\t.p2align\t6\n.LBB8_1539: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[5:6], v4, s[26:27] offset:40\n\tglobal_load_b64 v[9:10], v4, s[26:27]\n\tv_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v5, v5, v7\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[2:3], null, v5, 24, v[9:10]\n\tv_and_b32_e32 v9, v6, v8\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[5:6], null, v9, 24, v[3:4]\n\tv_mov_b32_e32 v3, v5\n\tglobal_load_b64 v[5:6], v[2:3], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[2:3], v4, v[5:8], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_or_b32 s3, vcc_lo, s3\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s3\n\ts_cbranch_execnz .LBB8_1539\n; %bb.1540:\n\ts_or_b32 exec_lo, exec_lo, s3\n.LBB8_1541:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s2\n.LBB8_1542:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v42, 0\n\tv_readfirstlane_b32 s2, v2\n\tv_readfirstlane_b32 s3, v3\n\ts_mov_b32 s6, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v42, s[26:27] offset:40\n\tglobal_load_b128 v[4:7], v42, s[26:27]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s4, v8\n\tv_readfirstlane_b32 s5, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b64 s[4:5], s[2:3], s[4:5]\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1544\n; %bb.1543:\n\tv_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, 0\n\ts_mul_i32 s6, s5, 24\n\ts_mul_hi_u32 s7, s4, 24\n\tv_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1\n\ts_add_i32 s7, s7, s6\n\ts_mul_i32 s6, s4, 24\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v2, vcc_lo, v4, s6\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo\n\tglobal_store_b128 v[2:3], v[8:11], off offset:8\n.LBB8_1544:\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_cvt_f64_f32_e32 v[2:3], v28\n\ts_lshl_b64 s[6:7], s[4:5], 12\n\tv_lshlrev_b64 v[8:9], 6, v[41:42]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v6, vcc_lo, v6, s6\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo\n\ts_mov_b32 s8, 0\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_u32 v10, vcc_lo, v6, v8\n\ts_mov_b32 s9, s8\n\ts_mov_b32 s10, s8\n\ts_mov_b32 s11, s8\n\tv_and_or_b32 v0, v0, 0xffffff1d, 34\n\tv_add_co_ci_u32_e32 v11, vcc_lo, v7, v9, vcc_lo\n\tv_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9\n\tv_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, s11\n\ts_clause 0x3\n\tglobal_store_b128 v[10:11], v[0:3], off\n\tglobal_store_b128 v[10:11], v[6:9], off offset:16\n\tglobal_store_b128 v[10:11], v[6:9], off offset:32\n\tglobal_store_b128 v[10:11], v[6:9], off offset:48\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1552\n; %bb.1545:\n\tv_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s2\n\tv_mov_b32_e32 v10, s3\n\ts_clause 0x1\n\tglobal_load_b64 v[11:12], v8, s[26:27] offset:32 glc\n\tglobal_load_b64 v[0:1], v8, s[26:27] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v0\n\tv_readfirstlane_b32 s7, v1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[6:7], s[6:7], s[2:3]\n\ts_mul_i32 s7, s7, 24\n\ts_mul_hi_u32 s8, s6, 24\n\ts_mul_i32 s6, s6, 24\n\ts_add_i32 s8, s8, s7\n\tv_add_co_u32 v6, vcc_lo, v4, s6\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s8, v5, vcc_lo\n\ts_mov_b32 s6, exec_lo\n\tglobal_store_b64 v[6:7], v[11:12], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[2:3], v[11:12]\n\ts_cbranch_execz .LBB8_1548\n; %bb.1546:\n\ts_mov_b32 s7, 0\n.LBB8_1547: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[26:27] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]\n\tv_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0\n\ts_or_b32 s7, vcc_lo, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s7\n\ts_cbranch_execnz .LBB8_1547\n.LBB8_1548:\n\ts_or_b32 exec_lo, exec_lo, s6\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 s6, exec_lo\n\tv_mbcnt_lo_u32_b32 v2, s7, 0\n\tglobal_load_b64 v[0:1], v0, s[26:27] offset:16\n\tv_cmpx_eq_u32_e32 0, v2\n\ts_cbranch_execz .LBB8_1550\n; %bb.1549:\n\ts_bcnt1_i32_b32 s7, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s7\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off offset:8\n.LBB8_1550:\n\ts_or_b32 exec_lo, exec_lo, s6\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\ts_cbranch_vccnz .LBB8_1552\n; %bb.1551:\n\tglobal_load_b32 v0, v[0:1], off offset:24\n\tv_mov_b32_e32 v1, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s6, v0\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[2:3], v[0:1], off\n\ts_and_b32 m0, s6, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB8_1552:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_mul_i32 s1, s5, 24\n\ts_mul_hi_u32 s5, s4, 24\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_add_i32 s5, s5, s1\n\ts_mul_i32 s1, s4, 24\n\tv_add_co_u32 v0, vcc_lo, v4, s1\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB8_1556\n\t.p2align\t6\n.LBB8_1553: ; in Loop: Header=BB8_1556 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB8_1555\n; %bb.1554: ; in Loop: Header=BB8_1556 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB8_1556\n\ts_branch .LBB8_1558\n\t.p2align\t6\n.LBB8_1555:\n\ts_branch .LBB8_1558\n.LBB8_1556: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1553\n; %bb.1557: ; in Loop: Header=BB8_1556 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB8_1553\n.LBB8_1558:\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB8_1562\n; %bb.1559:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[26:27] offset:40\n\tglobal_load_b64 v[7:8], v6, s[26:27] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[26:27]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s2\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB8_1562\n; %bb.1560:\n\ts_mov_b32 s0, 0\n.LBB8_1561: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[26:27] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_1561\n.LBB8_1562:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_add_u32 s16, s22, 8\n\ts_addc_u32 s17, s23, 0\n\ts_getpc_b64 s[18:19]\n\ts_add_u32 s18, s18, __ockl_printf_begin@rel32@lo+4\n\ts_addc_u32 s19, s19, __ockl_printf_begin@rel32@hi+12\n\ts_mov_b64 s[8:9], s[16:17]\n\ts_swappc_b64 s[30:31], s[18:19]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, .str.11@rel32@lo+4\n\ts_addc_u32 s1, s1, .str.11@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)\n\tv_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1\n\ts_cmp_lg_u64 s[0:1], 0\n\tv_mov_b32_e32 v6, 1\n\ts_cselect_b32 s2, 14, 0\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s2\n\ts_mov_b64 s[8:9], s[16:17]\n\ts_mov_b32 s36, 0\n\ts_getpc_b64 s[20:21]\n\ts_add_u32 s20, s20, __ockl_printf_append_string_n@rel32@lo+4\n\ts_addc_u32 s21, s21, __ockl_printf_append_string_n@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)\n\ts_swappc_b64 s[30:31], s[20:21]\n\tscratch_load_b32 v0, off, off offset:2744\n\ts_mov_b64 s[8:9], s[16:17]\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v1, 4 :: v_dual_lshlrev_b32 v0, 2, v0\n\tv_add3_u32 v0, v1, v0, 0x558\n\tscratch_load_b32 v0, v0, off\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v0, v0, 2, 4\n\tscratch_load_b32 v0, v0, off\n\ts_waitcnt vmcnt(0)\n\tv_cvt_f64_f32_e32 v[37:38], v0\n\ts_swappc_b64 s[30:31], s[18:19]\n\ts_getpc_b64 s[26:27]\n\ts_add_u32 s26, s26, .str.10@rel32@lo+4\n\ts_addc_u32 s27, s27, .str.10@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)\n\tv_dual_mov_b32 v2, s26 :: v_dual_mov_b32 v3, s27\n\ts_cmp_lg_u64 s[26:27], 0\n\tv_mov_b32_e32 v6, 0\n\ts_cselect_b32 s37, 7, 0\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s37\n\ts_mov_b64 s[8:9], s[16:17]\n\ts_swappc_b64 s[30:31], s[20:21]\n\ts_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)\n\tv_dual_mov_b32 v2, v37 :: v_dual_mov_b32 v3, v38\n\ts_mov_b64 s[8:9], s[16:17]\n\ts_getpc_b64 s[34:35]\n\ts_add_u32 s34, s34, __ockl_printf_append_args@rel32@lo+4\n\ts_addc_u32 s35, s35, __ockl_printf_append_args@rel32@hi+12\n\ts_swappc_b64 s[30:31], s[34:35]\n\tscratch_load_b32 v37, off, off offset:2748\n\ts_mov_b64 s[8:9], s[16:17]\n\ts_swappc_b64 s[30:31], s[18:19]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, .str.12@rel32@lo+4\n\ts_addc_u32 s1, s1, .str.12@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)\n\tv_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1\n\ts_cmp_lg_u64 s[0:1], 0\n\tv_mov_b32_e32 v6, 1\n\ts_cselect_b32 s2, 53, 0\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s2\n\ts_mov_b64 s[8:9], s[16:17]\n\ts_swappc_b64 s[30:31], s[20:21]\n\ts_movk_i32 s0, 0x2a8\n\ts_mov_b64 s[8:9], s[16:17]\n\tv_add_nc_u32_e64 v39, s0, 4\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshl_add_u32 v0, v37, 2, v39\n\tscratch_load_b32 v0, v0, off\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v0, v0, 2, 4\n\tscratch_load_b32 v0, v0, off\n\ts_waitcnt vmcnt(0)\n\tv_cvt_f64_f32_e32 v[37:38], v0\n\ts_swappc_b64 s[30:31], s[18:19]\n\tv_dual_mov_b32 v2, s26 :: v_dual_mov_b32 v3, s27\n\tv_dual_mov_b32 v4, s37 :: v_dual_mov_b32 v5, 0\n\tv_mov_b32_e32 v6, 0\n\ts_mov_b64 s[8:9], s[16:17]\n\ts_swappc_b64 s[30:31], s[20:21]\n\ts_delay_alu instid0(VALU_DEP_4)\n\tv_dual_mov_b32 v2, v37 :: v_dual_mov_b32 v3, v38\n\ts_mov_b64 s[8:9], s[16:17]\n\ts_swappc_b64 s[30:31], s[34:35]\n\ts_mov_b64 s[8:9], s[16:17]\n\ts_swappc_b64 s[30:31], s[18:19]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, .str.13@rel32@lo+4\n\ts_addc_u32 s1, s1, .str.13@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)\n\tv_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1\n\ts_cmp_lg_u64 s[0:1], 0\n\tv_mov_b32_e32 v6, 1\n\ts_cselect_b32 s2, 13, 0\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s2\n\ts_mov_b64 s[8:9], s[16:17]\n\ts_swappc_b64 s[30:31], s[20:21]\n\tscratch_load_b32 v0, off, off offset:2748\n\ts_mov_b64 s[8:9], s[16:17]\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v0, v0, 2, v39\n\tscratch_load_b32 v0, v0, off\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v0, v0, 2, 4\n\tscratch_load_b32 v0, v0, off\n\ts_waitcnt vmcnt(0)\n\tv_cvt_f64_f32_e32 v[37:38], v0\n\ts_swappc_b64 s[30:31], s[18:19]\n\tv_dual_mov_b32 v2, s26 :: v_dual_mov_b32 v3, s27\n\tv_dual_mov_b32 v4, s37 :: v_dual_mov_b32 v5, 0\n\tv_mov_b32_e32 v6, 0\n\ts_mov_b64 s[8:9], s[16:17]\n\ts_swappc_b64 s[30:31], s[20:21]\n\ts_delay_alu instid0(VALU_DEP_4)\n\tv_dual_mov_b32 v2, v37 :: v_dual_mov_b32 v3, v38\n\ts_mov_b64 s[8:9], s[16:17]\n\ts_swappc_b64 s[30:31], s[34:35]\n\tscratch_load_b32 v0, off, off offset:2744\n\ts_mov_b32 s0, exec_lo\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u32_e32 -1, v0\n\ts_cbranch_execz .LBB8_1564\n\t.p2align\t6\n.LBB8_1563: ; =>This Inner Loop Header: Depth=1\n\tv_lshl_add_u32 v1, v0, 2, 4\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_nc_u32_e32 v2, 0x558, v1\n\tv_add_nc_u32_e32 v1, 0x2a8, v1\n\ts_clause 0x1\n\tscratch_load_b32 v0, v2, off\n\tscratch_load_b32 v3, v1, off\n\ts_waitcnt vmcnt(0)\n\ts_clause 0x1\n\tscratch_store_b32 v2, v3, off\n\tscratch_store_b32 v1, v0, off\n\tv_cmp_eq_u32_e32 vcc_lo, -1, v0\n\ts_or_b32 s36, vcc_lo, s36\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s36\n\ts_cbranch_execnz .LBB8_1563\n.LBB8_1564:\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_clause 0x1\n\tscratch_load_b32 v0, off, off offset:2748\n\tscratch_load_b32 v1, off, off offset:2744\n\ts_load_b64 s[26:27], s[24:25], 0x4\n\tv_and_b32_e32 v2, 0x3ff, v40\n\tv_bfe_u32 v45, v40, 10, 10\n\tv_bfe_u32 v46, v40, 20, 10\n\ts_mov_b32 s46, 0\n\ts_waitcnt vmcnt(1)\n\tscratch_store_b32 off, v0, off offset:2744\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v1, off offset:2748\n\ts_waitcnt lgkmcnt(0)\n\ts_lshr_b32 s0, s26, 16\n\ts_add_u32 s24, s22, 8\n\ts_mul_i32 s0, s0, s27\n\ts_addc_u32 s25, s23, 0\n\tv_mul_lo_u32 v47, s0, v2\n\ts_mov_b64 s[0:1], src_shared_base\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_getpc_b64 s[34:35]\n\ts_add_u32 s34, s34, __ockl_printf_begin@rel32@lo+4\n\ts_addc_u32 s35, s35, __ockl_printf_begin@rel32@hi+12\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u32_u24 v2, v45, s27, v47\n\tv_add_lshl_u32 v49, v2, v46, 2\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, 0x1000, v49\n\tv_cmp_ne_u32_e32 vcc_lo, -1, v49\n\tv_cmp_ne_u32_e64 s0, -1, v2\n\tv_cndmask_b32_e32 v41, 0, v49, vcc_lo\n\tv_cndmask_b32_e64 v43, 0, s1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_cndmask_b32_e64 v42, 0, v2, s0\n\tv_cndmask_b32_e64 v44, 0, s1, s0\n\ts_swappc_b64 s[30:31], s[34:35]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, .str.14@rel32@lo+4\n\ts_addc_u32 s1, s1, .str.14@rel32@hi+12\n\tv_mov_b32_e32 v6, 1\n\ts_cmp_lg_u64 s[0:1], 0\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_cselect_b32 s2, -1, 0\n\ts_getpc_b64 s[36:37]\n\ts_add_u32 s36, s36, __ockl_printf_append_string_n@rel32@lo+4\n\ts_addc_u32 s37, s37, __ockl_printf_append_string_n@rel32@hi+12\n\tv_cndmask_b32_e64 v2, 0, 1, s2\n\tv_mov_b32_e32 v5, 0\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_dual_mov_b32 v3, s1 :: v_dual_lshlrev_b32 v4, 4, v2\n\tv_mov_b32_e32 v2, s0\n\ts_swappc_b64 s[30:31], s[36:37]\n\tv_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_getpc_b64 s[38:39]\n\ts_add_u32 s38, s38, _Z9printListRN18gpu_linearized_stl4listIfLi170EEE@rel32@lo+4\n\ts_addc_u32 s39, s39, _Z9printListRN18gpu_linearized_stl4listIfLi170EEE@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_swappc_b64 s[30:31], s[38:39]\n\tscratch_load_b32 v0, off, off offset:2744\n\tv_dual_mov_b32 v48, 4 :: v_dual_mov_b32 v51, 0x4048f5c3\n\tv_mov_b32_e32 v4, v44\n\ts_getpc_b64 s[40:41]\n\ts_add_u32 s40, s40, _ZN18gpu_linearized_stl4listIfLi170EE6insertEiRKf@rel32@lo+4\n\ts_addc_u32 s41, s41, _ZN18gpu_linearized_stl4listIfLi170EE6insertEiRKf@rel32@hi+12\n\tv_dual_mov_b32 v1, s29 :: v_dual_add_nc_u32 v50, 0x558, v48\n\tds_store_b32 v49, v51 offset:4096\n\tv_mov_b32_e32 v3, v42\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v0, v0, 2, v50\n\tscratch_load_b32 v2, v0, off\n\tv_mov_b32_e32 v0, s28\n\ts_swappc_b64 s[30:31], s[40:41]\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_swappc_b64 s[30:31], s[34:35]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, .str.15@rel32@lo+4\n\ts_addc_u32 s1, s1, .str.15@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)\n\tv_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1\n\ts_cmp_lg_u64 s[0:1], 0\n\tv_mov_b32_e32 v6, 1\n\ts_cselect_b32 s2, 33, 0\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s2\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_swappc_b64 s[30:31], s[36:37]\n\tv_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_swappc_b64 s[30:31], s[38:39]\n\tscratch_load_b32 v2, off, off offset:2748\n\tv_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29\n\tv_dual_mov_b32 v3, v41 :: v_dual_mov_b32 v4, v43\n\tds_store_b32 v49, v51\n\ts_swappc_b64 s[30:31], s[40:41]\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_swappc_b64 s[30:31], s[34:35]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, .str.16@rel32@lo+4\n\ts_addc_u32 s1, s1, .str.16@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)\n\tv_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1\n\ts_cmp_lg_u64 s[0:1], 0\n\tv_mov_b32_e32 v6, 1\n\ts_cselect_b32 s2, 31, 0\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s2\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_swappc_b64 s[30:31], s[36:37]\n\tv_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_swappc_b64 s[30:31], s[38:39]\n\tscratch_load_b32 v0, off, off offset:2744\n\ts_getpc_b64 s[42:43]\n\ts_add_u32 s42, s42, _ZN18gpu_linearized_stl4listIfLi170EE5eraseEi@rel32@lo+4\n\ts_addc_u32 s43, s43, _ZN18gpu_linearized_stl4listIfLi170EE5eraseEi@rel32@hi+12\n\tv_mov_b32_e32 v1, s29\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v0, v0, 2, v50\n\tscratch_load_b32 v2, v0, off\n\tv_mov_b32_e32 v0, s28\n\ts_swappc_b64 s[30:31], s[42:43]\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_swappc_b64 s[30:31], s[34:35]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, .str.17@rel32@lo+4\n\ts_addc_u32 s1, s1, .str.17@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)\n\tv_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1\n\ts_cmp_lg_u64 s[0:1], 0\n\tv_mov_b32_e32 v6, 1\n\ts_cselect_b32 s2, 26, 0\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s2\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_swappc_b64 s[30:31], s[36:37]\n\tv_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_swappc_b64 s[30:31], s[38:39]\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_swappc_b64 s[30:31], s[34:35]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, .str.9@rel32@lo+4\n\ts_addc_u32 s1, s1, .str.9@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)\n\tv_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1\n\ts_cmp_lg_u64 s[0:1], 0\n\tv_mov_b32_e32 v6, 1\n\ts_cselect_b32 s2, 23, 0\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s2\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_swappc_b64 s[30:31], s[36:37]\n\tscratch_load_b32 v0, off, off offset:2744\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v0, v0, 2, v50\n\tscratch_load_b32 v0, v0, off\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v0, v0, 2, 4\n\tscratch_load_b32 v0, v0, off\n\ts_waitcnt vmcnt(0)\n\tv_cvt_f64_f32_e32 v[37:38], v0\n\ts_swappc_b64 s[30:31], s[34:35]\n\ts_getpc_b64 s[40:41]\n\ts_add_u32 s40, s40, .str.10@rel32@lo+4\n\ts_addc_u32 s41, s41, .str.10@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)\n\tv_dual_mov_b32 v2, s40 :: v_dual_mov_b32 v3, s41\n\ts_cmp_lg_u64 s[40:41], 0\n\tv_mov_b32_e32 v6, 0\n\ts_cselect_b32 s47, 7, 0\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s47\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_swappc_b64 s[30:31], s[36:37]\n\ts_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)\n\tv_dual_mov_b32 v2, v37 :: v_dual_mov_b32 v3, v38\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_getpc_b64 s[44:45]\n\ts_add_u32 s44, s44, __ockl_printf_append_args@rel32@lo+4\n\ts_addc_u32 s45, s45, __ockl_printf_append_args@rel32@hi+12\n\ts_swappc_b64 s[30:31], s[44:45]\n\tscratch_load_b32 v2, off, off offset:2748\n\tv_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29\n\ts_swappc_b64 s[30:31], s[42:43]\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_swappc_b64 s[30:31], s[34:35]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, .str.18@rel32@lo+4\n\ts_addc_u32 s1, s1, .str.18@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)\n\tv_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1\n\ts_cmp_lg_u64 s[0:1], 0\n\tv_mov_b32_e32 v6, 1\n\ts_cselect_b32 s2, 24, 0\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s2\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_swappc_b64 s[30:31], s[36:37]\n\tv_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_swappc_b64 s[30:31], s[38:39]\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_swappc_b64 s[30:31], s[34:35]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, .str.13@rel32@lo+4\n\ts_addc_u32 s1, s1, .str.13@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)\n\tv_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1\n\ts_cmp_lg_u64 s[0:1], 0\n\tv_mov_b32_e32 v6, 1\n\ts_cselect_b32 s2, 13, 0\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s2\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_swappc_b64 s[30:31], s[36:37]\n\tscratch_load_b32 v0, off, off offset:2748\n\ts_movk_i32 s0, 0x2a8\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_waitcnt vmcnt(0)\n\tv_lshlrev_b32_e32 v0, 2, v0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add3_u32 v0, 4, v0, s0\n\tscratch_load_b32 v0, v0, off\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v0, v0, 2, 4\n\tscratch_load_b32 v0, v0, off\n\ts_waitcnt vmcnt(0)\n\tv_cvt_f64_f32_e32 v[37:38], v0\n\ts_swappc_b64 s[30:31], s[34:35]\n\tv_dual_mov_b32 v2, s40 :: v_dual_mov_b32 v3, s41\n\tv_dual_mov_b32 v4, s47 :: v_dual_mov_b32 v5, 0\n\tv_mov_b32_e32 v6, 0\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_swappc_b64 s[30:31], s[36:37]\n\ts_delay_alu instid0(VALU_DEP_4)\n\tv_dual_mov_b32 v2, v37 :: v_dual_mov_b32 v3, v38\n\ts_mov_b64 s[8:9], s[24:25]\n\ts_swappc_b64 s[30:31], s[44:45]\n\tscratch_load_b32 v0, off, off offset:2744\n\ts_mov_b32 s4, exec_lo\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v0, v0, 2, v50\n\tscratch_load_b32 v14, v0, off\n\tscratch_load_b32 v0, off, off offset:2748\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u32_e64 v14, v0\n\ts_cbranch_execz .LBB8_1567\n; %bb.1565:\n\tv_mul_u32_u24_e32 v0, s27, v45\n\ts_mov_b64 s[0:1], src_shared_base\n\tv_mov_b32_e32 v18, 0x41b1c28f\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_add3_u32 v0, v47, v0, v46\n\tv_lshl_add_u32 v17, v0, 2, 0x2000\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmp_ne_u32_e32 vcc_lo, -1, v17\n\tv_cndmask_b32_e32 v15, 0, v17, vcc_lo\n\tv_cndmask_b32_e64 v16, 0, s1, vcc_lo\n\t.p2align\t6\n.LBB8_1566: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)\n\tv_dual_mov_b32 v2, v14 :: v_dual_mov_b32 v3, v15\n\tv_mov_b32_e32 v4, v16\n\tds_store_b32 v17, v18\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, _ZN18gpu_linearized_stl4listIfLi170EE6insertEiRKf@rel32@lo+4\n\ts_addc_u32 s1, s1, _ZN18gpu_linearized_stl4listIfLi170EE6insertEiRKf@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_lshlrev_b32_e32 v0, 2, v14\n\tv_add3_u32 v0, v48, v0, 0x558\n\tscratch_load_b32 v14, v0, off\n\tscratch_load_b32 v0, off, off offset:2748\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e32 vcc_lo, v14, v0\n\ts_or_b32 s46, vcc_lo, s46\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s46\n\ts_cbranch_execnz .LBB8_1566\n.LBB8_1567:\n\ts_or_b32 exec_lo, exec_lo, s4\n\tv_and_b32_e32 v0, 0x3ff, v40\n\ts_lshr_b32 s0, s26, 16\n\ts_add_u32 s16, s22, 8\n\ts_mul_i32 s0, s0, s27\n\ts_addc_u32 s17, s23, 0\n\tv_mul_lo_u32 v0, s0, v0\n\ts_mov_b64 s[0:1], src_shared_base\n\ts_mov_b64 s[8:9], s[16:17]\n\ts_mov_b32 s24, 0\n\ts_getpc_b64 s[2:3]\n\ts_add_u32 s2, s2, __ockl_printf_begin@rel32@lo+4\n\ts_addc_u32 s3, s3, __ockl_printf_begin@rel32@hi+12\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u32_u24 v0, v45, s27, v0\n\tv_add_lshl_u32 v43, v0, v46, 2\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_add_nc_u32_e32 v42, 0x3000, v43\n\tv_cmp_ne_u32_e32 vcc_lo, -1, v42\n\tv_cndmask_b32_e32 v40, 0, v42, vcc_lo\n\tv_cndmask_b32_e64 v41, 0, s1, vcc_lo\n\ts_swappc_b64 s[30:31], s[2:3]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, .str.19@rel32@lo+4\n\ts_addc_u32 s1, s1, .str.19@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)\n\tv_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1\n\ts_cmp_lg_u64 s[0:1], 0\n\tv_mov_b32_e32 v6, 1\n\ts_cselect_b32 s4, 0x52, 0\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s4\n\ts_mov_b64 s[8:9], s[16:17]\n\ts_getpc_b64 s[2:3]\n\ts_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4\n\ts_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_swappc_b64 s[30:31], s[2:3]\n\tv_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29\n\ts_mov_b64 s[8:9], s[16:17]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, _Z9printListRN18gpu_linearized_stl4listIfLi170EEE@rel32@lo+4\n\ts_addc_u32 s1, s1, _Z9printListRN18gpu_linearized_stl4listIfLi170EEE@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_dual_mov_b32 v15, 0x41b1c28f :: v_dual_mov_b32 v0, s28\n\tv_dual_mov_b32 v1, s29 :: v_dual_mov_b32 v2, v40\n\tv_mov_b32_e32 v3, v41\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, _ZN18gpu_linearized_stl4listIfLi170EE4findERKf@rel32@lo+4\n\ts_addc_u32 s1, s1, _ZN18gpu_linearized_stl4listIfLi170EE4findERKf@rel32@hi+12\n\tds_store_b32 v43, v15 offset:12288\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:2748\n\ts_mov_b32 s4, exec_lo\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u32_e64 v2, v0\n\ts_cbranch_execz .LBB8_1569\n\t.p2align\t6\n.LBB8_1568: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, _ZN18gpu_linearized_stl4listIfLi170EE5eraseEi@rel32@lo+4\n\ts_addc_u32 s1, s1, _ZN18gpu_linearized_stl4listIfLi170EE5eraseEi@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_dual_mov_b32 v2, v40 :: v_dual_mov_b32 v3, v41\n\tds_store_b32 v42, v15\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, _ZN18gpu_linearized_stl4listIfLi170EE4findERKf@rel32@lo+4\n\ts_addc_u32 s1, s1, _ZN18gpu_linearized_stl4listIfLi170EE4findERKf@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:2748\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e32 vcc_lo, v2, v0\n\ts_or_b32 s24, vcc_lo, s24\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s24\n\ts_cbranch_execnz .LBB8_1568\n.LBB8_1569:\n\ts_or_b32 exec_lo, exec_lo, s4\n\ts_add_u32 s22, s22, 8\n\ts_addc_u32 s23, s23, 0\n\ts_getpc_b64 s[36:37]\n\ts_add_u32 s36, s36, __ockl_printf_begin@rel32@lo+4\n\ts_addc_u32 s37, s37, __ockl_printf_begin@rel32@hi+12\n\ts_mov_b64 s[8:9], s[22:23]\n\ts_mov_b64 s[24:25], src_private_base\n\ts_swappc_b64 s[30:31], s[36:37]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, .str.20@rel32@lo+4\n\ts_addc_u32 s1, s1, .str.20@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)\n\tv_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1\n\ts_cmp_lg_u64 s[0:1], 0\n\tv_mov_b32_e32 v6, 1\n\ts_cselect_b32 s2, 60, 0\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s2\n\ts_mov_b64 s[8:9], s[22:23]\n\ts_getpc_b64 s[26:27]\n\ts_add_u32 s26, s26, __ockl_printf_append_string_n@rel32@lo+4\n\ts_addc_u32 s27, s27, __ockl_printf_append_string_n@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_swappc_b64 s[30:31], s[26:27]\n\tv_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29\n\ts_mov_b64 s[8:9], s[22:23]\n\ts_getpc_b64 s[34:35]\n\ts_add_u32 s34, s34, _Z9printListRN18gpu_linearized_stl4listIfLi170EEE@rel32@lo+4\n\ts_addc_u32 s35, s35, _Z9printListRN18gpu_linearized_stl4listIfLi170EEE@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)\n\ts_swappc_b64 s[30:31], s[34:35]\n\tv_dual_mov_b32 v0, 0xac4 :: v_dual_mov_b32 v1, s25\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, _ZN18gpu_linearized_stl4listIfLi170EEC2Ev@rel32@lo+4\n\ts_addc_u32 s1, s1, _ZN18gpu_linearized_stl4listIfLi170EEC2Ev@rel32@hi+12\n\ts_swappc_b64 s[30:31], s[0:1]\n\ts_clause 0x1\n\tscratch_load_b32 v0, off, s33\n\tscratch_load_b32 v1, off, s33 offset:8\n\ts_movk_i32 s0, 0x808\n\tscratch_load_b32 v5, off, off offset:2744\n\ts_mov_b64 s[8:9], s[22:23]\n\ts_waitcnt vmcnt(2)\n\tv_dual_mov_b32 v7, 4 :: v_dual_add_nc_u32 v0, -1, v0\n\ts_waitcnt vmcnt(0)\n\tv_lshlrev_b32_e32 v5, 2, v5\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_lshlrev_b32_e32 v2, 2, v0\n\tv_add3_u32 v5, v7, v5, 0x558\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\tv_add3_u32 v2, 0xac4, v2, s0\n\ts_movk_i32 s0, 0x2a8\n\tv_add_nc_u32_e64 v3, 0xac4, s0\n\ts_movk_i32 s0, 0x558\n\tscratch_load_b32 v2, v2, off\n\tv_lshl_add_u32 v1, v1, 2, v3\n\tscratch_load_b32 v1, v1, off\n\ts_waitcnt vmcnt(1)\n\tv_lshlrev_b32_e32 v4, 2, v2\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_nc_u32_e32 v6, v3, v4\n\tscratch_store_b32 off, v0, s33\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 v6, v1, off\n\tscratch_load_b32 v0, off, s33 offset:8\n\tv_add_nc_u32_e64 v6, 0xac4, s0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_nc_u32_e32 v8, v6, v4\n\tv_lshl_add_u32 v1, v1, 2, v6\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 v8, v0, off\n\tscratch_load_b32 v0, off, s33 offset:8\n\tscratch_load_b32 v5, v5, off\n\ts_waitcnt vmcnt(1)\n\tv_lshl_add_u32 v0, v0, 2, v3\n\ts_waitcnt vmcnt(0)\n\tv_lshl_add_u32 v3, v5, 2, 4\n\ts_clause 0x1\n\tscratch_store_b32 v0, v2, off\n\tscratch_store_b32 v1, v2, off\n\tscratch_load_b32 v0, off, s33 offset:12\n\tscratch_load_b32 v1, v3, off\n\tv_add_nc_u32_e32 v2, 0xac4, v4\n\tv_mov_b32_e32 v4, 0x461d9800\n\ts_waitcnt vmcnt(1)\n\tv_add_nc_u32_e32 v0, 1, v0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 v2, v1, off\n\tscratch_store_b32 v3, v4, off\n\tscratch_store_b32 off, v0, s33 offset:12\n\ts_swappc_b64 s[30:31], s[36:37]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, .str.21@rel32@lo+4\n\ts_addc_u32 s1, s1, .str.21@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)\n\tv_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1\n\ts_cmp_lg_u64 s[0:1], 0\n\tv_mov_b32_e32 v6, 1\n\ts_cselect_b32 s2, 19, 0\n\tv_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s2\n\ts_mov_b64 s[8:9], s[22:23]\n\ts_swappc_b64 s[30:31], s[26:27]\n\tv_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29\n\ts_mov_b64 s[8:9], s[22:23]\n\ts_swappc_b64 s[30:31], s[34:35]\n\tv_dual_mov_b32 v0, 0xac4 :: v_dual_mov_b32 v1, s25\n\ts_mov_b64 s[8:9], s[22:23]\n\ts_swappc_b64 s[30:31], s[34:35]\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z4testPf\n\t\t.amdhsa_group_segment_fixed_size 16384\n\t\t.amdhsa_private_segment_fixed_size 5520\n\t\t.amdhsa_kernarg_size 264\n\t\t.amdhsa_user_sgpr_count 15\n\t\t.amdhsa_user_sgpr_dispatch_ptr 1\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 1\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 0\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 2\n\t\t.amdhsa_next_free_vgpr 52\n\t\t.amdhsa_next_free_sgpr 48\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end8:\n\t.size\t_Z4testPf, .Lfunc_end8-_Z4testPf\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 67024\n; NumSgprs: 50\n; NumVgprs: 52\n; ScratchSize: 5520\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 16384 bytes/workgroup (compile time only)\n; SGPRBlocks: 6\n; VGPRBlocks: 6\n; NumSGPRsForWavesPerEU: 50\n; NumVGPRsForWavesPerEU: 52\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1\n; COMPUTE_PGM_RSRC2:USER_SGPR: 15\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2\n\t.section\t.text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,\"axG\",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat\n\t.protected\t_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ ; -- Begin function _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_\n\t.globl\t_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_\n\t.p2align\t8\n\t.type\t_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,@function\n_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_: ; @_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_\n; %bb.0:\n\ts_load_b128 s[4:7], s[0:1], 0x10\n\ts_lshl_b32 s2, s15, 8\n\ts_waitcnt lgkmcnt(0)\n\ts_add_u32 s2, s2, s6\n\ts_addc_u32 s3, 0, s7\n\ts_sub_u32 s4, s4, s2\n\ts_subb_u32 s5, s5, s3\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cmp_gt_u64_e64 s5, 0x100, s[4:5]\n\ts_and_b32 s5, s5, exec_lo\n\ts_cselect_b32 s4, s4, 0x100\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)\n\tv_cmp_gt_u32_e32 vcc_lo, s4, v0\n\ts_cmpk_eq_i32 s4, 0x100\n\ts_cselect_b32 s4, -1, 0\n\ts_or_b32 s4, s4, vcc_lo\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_saveexec_b32 s5, s4\n\ts_cbranch_execz .LBB9_2\n; %bb.1:\n\ts_clause 0x1\n\ts_load_b64 s[4:5], s[0:1], 0x0\n\ts_load_b32 s6, s[0:1], 0x8\n\tv_lshlrev_b32_e32 v0, 2, v0\n\ts_lshl_b64 s[0:1], s[2:3], 2\n\ts_waitcnt lgkmcnt(0)\n\ts_add_u32 s0, s4, s0\n\ts_addc_u32 s1, s5, s1\n\tv_add_co_u32 v0, s0, s0, v0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_co_ci_u32_e64 v1, null, s1, 0, s0\n\tv_mov_b32_e32 v2, s6\n\tflat_store_b32 v[0:1], v2\n.LBB9_2:\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 32\n\t\t.amdhsa_user_sgpr_count 15\n\t\t.amdhsa_user_sgpr_dispatch_ptr 0\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 0\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 0\n\t\t.amdhsa_next_free_vgpr 3\n\t\t.amdhsa_next_free_sgpr 16\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.section\t.text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,\"axG\",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat\n.Lfunc_end9:\n\t.size\t_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, .Lfunc_end9-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 168\n; NumSgprs: 18\n; NumVgprs: 3\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 2\n; VGPRBlocks: 0\n; NumSGPRsForWavesPerEU: 18\n; NumVGPRsForWavesPerEU: 3\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 15\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t.str,@object ; @.str\n\t.section\t.rodata.str1.1,\"aMS\",@progbits,1\n.str:\n\t.asciz\t\"\\n===== Empty list =====\\n\\n\"\n\t.size\t.str, 26\n\n\t.type\t.str.1,@object ; @.str.1\n.str.1:\n\t.asciz\t\"\\n===== Showing the list =====\\n\"\n\t.size\t.str.1, 31\n\n\t.type\t.str.2,@object ; @.str.2\n.str.2:\n\t.asciz\t\"list size = %d \\n\"\n\t.size\t.str.2, 17\n\n\t.type\t.str.3,@object ; @.str.3\n.str.3:\n\t.asciz\t\"%.2f \"\n\t.size\t.str.3, 6\n\n\t.type\t.str.4,@object ; @.str.4\n.str.4:\n\t.asciz\t\"\\n\\n\"\n\t.size\t.str.4, 3\n\n\t.type\t.str.5,@object ; @.str.5\n.str.5:\n\t.asciz\t\"for(int i=0;i<5;++i) list.push_back(i*1.7);\"\n\t.size\t.str.5, 44\n\n\t.type\t.str.6,@object ; @.str.6\n.str.6:\n\t.asciz\t\"for(int i=6;i<11;++i) list.push_front(i*2.5);\"\n\t.size\t.str.6, 46\n\n\t.type\t.str.7,@object ; @.str.7\n.str.7:\n\t.asciz\t\"for(int i=0;i<2;++i) list.pop_back();\"\n\t.size\t.str.7, 38\n\n\t.type\t.str.8,@object ; @.str.8\n.str.8:\n\t.asciz\t\"for(int i=0;i<2;++i) list.pop_front();\"\n\t.size\t.str.8, 39\n\n\t.type\t.str.9,@object ; @.str.9\n.str.9:\n\t.asciz\t\"list.at(list.begin())\\n\"\n\t.size\t.str.9, 23\n\n\t.type\t.str.10,@object ; @.str.10\n.str.10:\n\t.asciz\t\"%.2f\\n\\n\"\n\t.size\t.str.10, 7\n\n\t.type\t.str.11,@object ; @.str.11\n.str.11:\n\t.asciz\t\"list.front()\\n\"\n\t.size\t.str.11, 14\n\n\t.type\t.str.12,@object ; @.str.12\n.str.12:\n\t.asciz\t\"auto idx = list.end(); list.at(list.decrement(idx))\\n\"\n\t.size\t.str.12, 53\n\n\t.type\t.str.13,@object ; @.str.13\n.str.13:\n\t.asciz\t\"list.back()\\n\"\n\t.size\t.str.13, 13\n\n\t.type\t.str.14,@object ; @.str.14\n.str.14:\n\t.asciz\t\"list.reverse();\"\n\t.size\t.str.14, 16\n\n\t.type\t.str.15,@object ; @.str.15\n.str.15:\n\t.asciz\t\"list.insert(list.begin(), 3.14);\"\n\t.size\t.str.15, 33\n\n\t.type\t.str.16,@object ; @.str.16\n.str.16:\n\t.asciz\t\"list.insert(list.end(), 3.14);\"\n\t.size\t.str.16, 31\n\n\t.type\t.str.17,@object ; @.str.17\n.str.17:\n\t.asciz\t\"list.erase(list.begin());\"\n\t.size\t.str.17, 26\n\n\t.type\t.str.18,@object ; @.str.18\n.str.18:\n\t.asciz\t\"list.erase(list.end());\"\n\t.size\t.str.18, 24\n\n\t.type\t.str.19,@object ; @.str.19\n.str.19:\n\t.asciz\t\"for(auto p=list.begin(); p!=list.end(); list.increment(p)) list.insert(p, 22.22);\"\n\t.size\t.str.19, 82\n\n\t.type\t.str.20,@object ; @.str.20\n.str.20:\n\t.asciz\t\"while((auto p=list.find(22.22))!=list.end()) list.erase(p);\"\n\t.size\t.str.20, 60\n\n\t.type\t.str.21,@object ; @.str.21\n.str.21:\n\t.asciz\t\"Reference checking\"\n\t.size\t.str.21, 19\n\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .offset: 8\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 12\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 16\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 20\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 22\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 24\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 26\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 28\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 30\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 48\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 56\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 64\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 72\n .size: 2\n .value_kind: hidden_grid_dims\n - .offset: 88\n .size: 8\n .value_kind: hidden_hostcall_buffer\n .group_segment_fixed_size: 16384\n .kernarg_segment_align: 8\n .kernarg_segment_size: 264\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z4testPf\n .private_segment_fixed_size: 5520\n .sgpr_count: 50\n .sgpr_spill_count: 0\n .symbol: _Z4testPf.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 52\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\n - .args:\n - .offset: 0\n .size: 16\n .value_kind: by_value\n - .offset: 16\n .size: 8\n .value_kind: by_value\n - .offset: 24\n .size: 8\n .value_kind: by_value\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 32\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 256\n .name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_\n .private_segment_fixed_size: 0\n .sgpr_count: 18\n .sgpr_spill_count: 0\n .symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 3\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162570,"cells":{"id":{"kind":"string","value":"07db6120ec3250010d986d7202c0f5adf1cdc470_O0"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z9dctKernelPfS_ --------------------------\n .section .text._Z9dctKernelPfS_,\"ax\",@progbits\n .sectionflags @\"SHF_BARRIERS=1\"\n .sectioninfo @\"SHI_REGISTERS=31\"\n .align 128\n\n\n\n\n .global _Z9dctKernelPfS_\n .type _Z9dctKernelPfS_,@function\n .size _Z9dctKernelPfS_,(.L_x_15 - _Z9dctKernelPfS_)\n .other _Z9dctKernelPfS_,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z9dctKernelPfS_:\n.text._Z9dctKernelPfS_:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ IADD3 R1, R1, -0x20, RZ ;\n /*0020*/ S2R R0, SR_LMEMHIOFF ;\n /*0030*/ ISETP.GE.U32.AND P0, PT, R1, R0, PT ;\n /*0040*/ @P0 BRA `(.L_x_0) ;\n /*0050*/ BPT.TRAP 0x1 ;\n.L_x_0:\n /*0060*/ MOV R18, c[0x0][0x118] ;\n /*0070*/ MOV R19, c[0x0][0x11c] ;\n /*0080*/ IADD3 R0, R1, RZ, RZ ;\n /*0090*/ MOV R0, R0 ;\n /*00a0*/ MOV R2, R0 ;\n /*00b0*/ MOV R3, RZ ;\n /*00c0*/ MOV R12, R2 ;\n /*00d0*/ MOV R11, R3 ;\n /*00e0*/ MOV R12, R12 ;\n /*00f0*/ MOV R11, R11 ;\n /*0100*/ MOV R2, RZ ;\n /*0110*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0120*/ MOV R7, R2 ;\n /*0130*/ MOV R8, R3 ;\n /*0140*/ MOV R7, R7 ;\n /*0150*/ MOV R8, R8 ;\n /*0160*/ MOV R2, 0x8 ;\n /*0170*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0180*/ MOV R4, R2 ;\n /*0190*/ MOV R5, R3 ;\n /*01a0*/ MOV R4, R4 ;\n /*01b0*/ MOV R5, R5 ;\n /*01c0*/ IADD3 R12, P0, R12, RZ, RZ ;\n /*01d0*/ IADD3.X R11, R11, RZ, RZ, P0, !PT ;\n /*01e0*/ MOV R0, c[0x0][0x0] ;\n /*01f0*/ S2R R2, SR_CTAID.X ;\n /*0200*/ MOV R2, R2 ;\n /*0210*/ S2R R3, SR_TID.X ;\n /*0220*/ MOV R3, R3 ;\n /*0230*/ IMAD R10, R2, R0, R3 ;\n /*0240*/ ISETP.GT.AND P0, PT, R10, 0x1fff, PT ;\n /*0250*/ MOV R7, R7 ;\n /*0260*/ MOV R8, R8 ;\n /*0270*/ MOV R2, R4 ;\n /*0280*/ MOV R0, R5 ;\n /*0290*/ MOV R12, R12 ;\n /*02a0*/ MOV R11, R11 ;\n /*02b0*/ MOV R3, R3 ;\n /*02c0*/ MOV R10, R10 ;\n /*02d0*/ @P0 BRA `(.L_x_1) ;\n /*02e0*/ MOV R7, R7 ;\n /*02f0*/ MOV R8, R8 ;\n /*0300*/ IMAD.WIDE R4, R10, 0x4, RZ ;\n /*0310*/ MOV R6, R4 ;\n /*0320*/ MOV R5, R5 ;\n /*0330*/ IADD3 R4, P0, R7, R6, RZ ;\n /*0340*/ IADD3.X R5, R8, R5, RZ, P0, !PT ;\n /*0350*/ MOV R4, R4 ;\n /*0360*/ MOV R5, R5 ;\n /*0370*/ MOV R4, R4 ;\n /*0380*/ MOV R5, R5 ;\n /*0390*/ R2UR UR4, R18 ;\n /*03a0*/ R2UR UR5, R19 ;\n /*03b0*/ LDG.E R4, [R4.64] ;\n /*03c0*/ SHF.L.U32 R3, R3, 0x2, RZ ;\n /*03d0*/ MOV R5, RZ ;\n /*03e0*/ IADD3 R3, R5, R3, RZ ;\n /*03f0*/ MOV R3, R3 ;\n /*0400*/ STS [R3], R4 ;\n.L_x_1:\n /*0410*/ WARPSYNC 0xffffffff ;\n /*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ;\n /*0430*/ ISETP.EQ.AND P0, PT, R10, RZ, PT ;\n /*0440*/ MOV R9, RZ ;\n /*0450*/ MOV R8, 0x3c3504f3 ;\n /*0460*/ FSEL R8, R8, 0.015625, P0 ;\n /*0470*/ I2F.F64 R4, R10 ;\n /*0480*/ DMUL R4, R4, c[0x2][0x0] ;\n /*0490*/ MOV R7, R2 ;\n /*04a0*/ MOV R6, R0 ;\n /*04b0*/ MOV R0, RZ ;\n /*04c0*/ MOV R13, c[0x4][0x0] ;\n /*04d0*/ MOV R14, c[0x4][0x4] ;\n /*04e0*/ MOV R9, R9 ;\n /*04f0*/ MOV R8, R8 ;\n /*0500*/ MOV R2, R4 ;\n /*0510*/ MOV R3, R5 ;\n /*0520*/ MOV R7, R7 ;\n /*0530*/ MOV R6, R6 ;\n /*0540*/ MOV R5, R0 ;\n /*0550*/ MOV R4, R13 ;\n /*0560*/ MOV R0, R14 ;\n.L_x_13:\n /*0570*/ SHF.L.U32 R13, R9, 0x1, RZ ;\n /*0580*/ LOP3.LUT R13, R13, 0x1, RZ, 0xfc, !PT ;\n /*0590*/ I2F.F64 R14, R13 ;\n /*05a0*/ DMUL R14, R2, R14 ;\n /*05b0*/ DMUL R14, R14, 6.103515625e-05 ;\n /*05c0*/ F2F.F32.F64 R14, R14 ;\n /*05d0*/ FMUL R13, R14, 0.63661974668502807617 ;\n /*05e0*/ F2I.NTZ R13, R13 ;\n /*05f0*/ I2FP.F32.S32 R15, R13 ;\n /*0600*/ MOV R16, 0xbfc90fda ;\n /*0610*/ FFMA R16, R15, R16, R14 ;\n /*0620*/ MOV R17, 0xb3a22168 ;\n /*0630*/ FFMA R16, R15, R17, R16 ;\n /*0640*/ MOV R17, 0xa7c234c5 ;\n /*0650*/ FFMA R16, R15, R17, R16 ;\n /*0660*/ FADD R15, -RZ, |R14| ;\n /*0670*/ MOV R15, R15 ;\n /*0680*/ FSETP.LTU.AND P0, PT, R15, 105615, PT ;\n /*0690*/ MOV R14, R14 ;\n /*06a0*/ MOV R13, R13 ;\n /*06b0*/ MOV R16, R16 ;\n /*06c0*/ MOV R15, R15 ;\n /*06d0*/ BSSY B0, `(.L_x_2) ;\n /*06e0*/ @P0 BRA `(.L_x_3) ;\n /*06f0*/ FSETP.EQ.AND P0, PT, R15, +INF , PT ;\n /*0700*/ @P0 BRA `(.L_x_4) ;\n /*0710*/ BRA `(.L_x_5) ;\n.L_x_4:\n /*0720*/ MOV R13, RZ ;\n /*0730*/ FMUL R13, R14, R13 ;\n /*0740*/ MOV R14, RZ ;\n /*0750*/ MOV R16, R13 ;\n /*0760*/ MOV R13, R14 ;\n /*0770*/ BRA `(.L_x_3) ;\n.L_x_5:\n /*0780*/ MOV R13, R14 ;\n /*0790*/ SHF.R.U32.HI R14, RZ, 0x17, R13 ;\n /*07a0*/ LOP3.LUT R14, R14, 0xff, RZ, 0xc0, !PT ;\n /*07b0*/ IADD3 R14, R14, -0x80, RZ ;\n /*07c0*/ SHF.L.U32 R15, R13, 0x8, RZ ;\n /*07d0*/ LOP3.LUT R15, R15, 0x80000000, RZ, 0xfc, !PT ;\n /*07e0*/ SHF.R.U32.HI R17, RZ, 0x5, R14 ;\n /*07f0*/ MOV R20, RZ ;\n /*0800*/ MOV R22, RZ ;\n /*0810*/ MOV R25, RZ ;\n /*0820*/ MOV R26, R12 ;\n /*0830*/ MOV R24, R11 ;\n /*0840*/ MOV R27, R4 ;\n /*0850*/ MOV R23, R0 ;\n /*0860*/ MOV R13, R13 ;\n /*0870*/ MOV R16, R14 ;\n /*0880*/ MOV R21, R15 ;\n /*0890*/ MOV R17, R17 ;\n /*08a0*/ MOV R20, R20 ;\n /*08b0*/ MOV R22, R22 ;\n /*08c0*/ MOV R25, R25 ;\n /*08d0*/ MOV R26, R26 ;\n /*08e0*/ MOV R24, R24 ;\n /*08f0*/ MOV R27, R27 ;\n /*0900*/ MOV R23, R23 ;\n.L_x_6:\n /*0910*/ MOV R14, R27 ;\n /*0920*/ MOV R15, R23 ;\n /*0930*/ MOV R14, R14 ;\n /*0940*/ MOV R15, R15 ;\n /*0950*/ R2UR UR4, R18 ;\n /*0960*/ R2UR UR5, R19 ;\n /*0970*/ LDG.E.CONSTANT R14, [R14.64] ;\n /*0980*/ IMAD.U32 R15, R14, R21, RZ ;\n /*0990*/ IMAD.HI.U32 R14, R14, R21, RZ ;\n /*09a0*/ MOV R15, R15 ;\n /*09b0*/ MOV R28, R14 ;\n /*09c0*/ IADD3 R14, P0, R15, R20, RZ ;\n /*09d0*/ IADD3.X R22, R28, R22, RZ, P0, !PT ;\n /*09e0*/ SHF.R.U64 R20, R14, 0x20, R22 ;\n /*09f0*/ SHF.R.U32.HI R22, RZ, 0x20, R22 ;\n /*0a00*/ MOV R15, R26 ;\n /*0a10*/ MOV R24, R24 ;\n /*0a20*/ MOV R14, R14 ;\n /*0a30*/ STL [R15], R14 ;\n /*0a40*/ IADD3 R27, P0, R27, 0x4, RZ ;\n /*0a50*/ IADD3.X R23, R23, RZ, RZ, P0, !PT ;\n /*0a60*/ IADD3 R26, P0, R26, 0x4, RZ ;\n /*0a70*/ IADD3.X R24, R24, RZ, RZ, P0, !PT ;\n /*0a80*/ IADD3 R25, R25, 0x1, RZ ;\n /*0a90*/ ISETP.NE.AND P0, PT, R25, 0x6, PT ;\n /*0aa0*/ MOV R20, R20 ;\n /*0ab0*/ MOV R22, R22 ;\n /*0ac0*/ MOV R27, R27 ;\n /*0ad0*/ MOV R23, R23 ;\n /*0ae0*/ MOV R26, R26 ;\n /*0af0*/ MOV R24, R24 ;\n /*0b00*/ MOV R25, R25 ;\n /*0b10*/ @P0 BRA `(.L_x_6) ;\n /*0b20*/ IADD3 R14, P0, R12, 0x18, RZ ;\n /*0b30*/ IADD3.X R15, R11, RZ, RZ, P0, !PT ;\n /*0b40*/ MOV R14, R14 ;\n /*0b50*/ MOV R15, R15 ;\n /*0b60*/ MOV R20, R20 ;\n /*0b70*/ STL [R14], R20 ;\n /*0b80*/ MOV R14, 0x4 ;\n /*0b90*/ IADD3 R20, R14, -R17, RZ ;\n /*0ba0*/ MOV R14, 0x6 ;\n /*0bb0*/ IADD3 R14, R14, -R17, RZ ;\n /*0bc0*/ IMAD.WIDE R14, R14, 0x4, RZ ;\n /*0bd0*/ MOV R17, R14 ;\n /*0be0*/ MOV R14, R15 ;\n /*0bf0*/ IADD3 R15, P0, R12, R17, RZ ;\n /*0c00*/ IADD3.X R17, R11, R14, RZ, P0, !PT ;\n /*0c10*/ MOV R14, R15 ;\n /*0c20*/ MOV R17, R17 ;\n /*0c30*/ LDL R14, [R14] ;\n /*0c40*/ IADD3 R15, P0, R15, -0x4, RZ ;\n /*0c50*/ IADD3.X R17, R17, -0x1, RZ, P0, !PT ;\n /*0c60*/ MOV R15, R15 ;\n /*0c70*/ MOV R17, R17 ;\n /*0c80*/ LDL R15, [R15] ;\n /*0c90*/ LOP3.LUT R16, R16, 0x1f, RZ, 0xc0, !PT ;\n /*0ca0*/ ISETP.EQ.AND P0, PT, R16, RZ, PT ;\n /*0cb0*/ MOV R17, R20 ;\n /*0cc0*/ MOV R20, R14 ;\n /*0cd0*/ MOV R14, R15 ;\n /*0ce0*/ MOV R15, R16 ;\n /*0cf0*/ BSSY B1, `(.L_x_7) ;\n /*0d00*/ @P0 BRA `(.L_x_8) ;\n /*0d10*/ MOV R16, 0x20 ;\n /*0d20*/ IADD3 R21, R16, -R15, RZ ;\n /*0d30*/ SHF.R.U32.HI R16, RZ, R21, R14 ;\n /*0d40*/ SHF.L.U32 R20, R20, R15, RZ ;\n /*0d50*/ IADD3 R20, R16, R20, RZ ;\n /*0d60*/ IMAD.WIDE R16, R17, 0x4, RZ ;\n /*0d70*/ MOV R22, R16 ;\n /*0d80*/ MOV R17, R17 ;\n /*0d90*/ IADD3 R16, P0, R12, R22, RZ ;\n /*0da0*/ IADD3.X R17, R11, R17, RZ, P0, !PT ;\n /*0db0*/ MOV R16, R16 ;\n /*0dc0*/ MOV R17, R17 ;\n /*0dd0*/ LDL R16, [R16] ;\n /*0de0*/ SHF.R.U32.HI R16, RZ, R21, R16 ;\n /*0df0*/ SHF.L.U32 R14, R14, R15, RZ ;\n /*0e00*/ IADD3 R14, R16, R14, RZ ;\n /*0e10*/ MOV R20, R20 ;\n /*0e20*/ MOV R14, R14 ;\n.L_x_8:\n /*0e30*/ BSYNC B1 ;\n.L_x_7:\n /*0e40*/ LOP3.LUT R13, R13, 0x80000000, RZ, 0xc0, !PT ;\n /*0e50*/ SHF.R.U32.HI R15, RZ, 0x1e, R14 ;\n /*0e60*/ SHF.L.U32 R16, R20, 0x2, RZ ;\n /*0e70*/ LOP3.LUT R15, R15, R16, RZ, 0xfc, !PT ;\n /*0e80*/ SHF.R.U32.HI R17, RZ, 0x1f, R15 ;\n /*0e90*/ SHF.R.U32.HI R20, RZ, 0x1e, R20 ;\n /*0ea0*/ IADD3 R20, R17, R20, RZ ;\n /*0eb0*/ IADD3 R16, RZ, -R20, RZ ;\n /*0ec0*/ MOV R16, R16 ;\n /*0ed0*/ MOV R16, R16 ;\n /*0ee0*/ ISETP.EQ.AND P0, PT, R13, RZ, PT ;\n /*0ef0*/ SEL R20, R20, R16, P0 ;\n /*0f00*/ ISETP.NE.AND P0, PT, R17, RZ, PT ;\n /*0f10*/ LOP3.LUT R16, R13, 0x80000000, RZ, 0x3c, !PT ;\n /*0f20*/ SEL R21, R16, R13, P0 ;\n /*0f30*/ SEL R13, RZ, 0xffffffff, !P0 ;\n /*0f40*/ LOP3.LUT R15, R15, R13, RZ, 0x3c, !PT ;\n /*0f50*/ SHF.L.U32 R14, R14, 0x2, RZ ;\n /*0f60*/ LOP3.LUT R13, R14, R13, RZ, 0x3c, !PT ;\n /*0f70*/ MOV R15, R15 ;\n /*0f80*/ MOV R14, R15 ;\n /*0f90*/ MOV R15, RZ ;\n /*0fa0*/ MOV R13, R13 ;\n /*0fb0*/ MOV R16, R13 ;\n /*0fc0*/ MOV R17, RZ ;\n /*0fd0*/ MOV R14, R14 ;\n /*0fe0*/ MOV R15, R15 ;\n /*0ff0*/ MOV R16, R16 ;\n /*1000*/ MOV R17, R17 ;\n /*1010*/ MOV R22, 0x20 ;\n /*1020*/ MOV R23, 0x20 ;\n /*1030*/ MOV R13, R20 ;\n /*1040*/ MOV R20, R21 ;\n /*1050*/ MOV R14, R14 ;\n /*1060*/ MOV R15, R15 ;\n /*1070*/ MOV R16, R16 ;\n /*1080*/ MOV R17, R17 ;\n /*1090*/ MOV R24, R22 ;\n /*10a0*/ MOV R23, R23 ;\n /*10b0*/ MOV R21, R14 ;\n /*10c0*/ MOV R22, R15 ;\n /*10d0*/ MOV R21, R21 ;\n /*10e0*/ MOV R22, R22 ;\n /*10f0*/ MOV R15, R16 ;\n /*1100*/ MOV R14, R17 ;\n /*1110*/ MOV R15, R15 ;\n /*1120*/ MOV R14, R14 ;\n /*1130*/ MOV R16, R24 ;\n /*1140*/ MOV R23, R23 ;\n /*1150*/ MOV R23, R23 ;\n /*1160*/ SHF.R.S32.HI R17, RZ, 0x1f, R23 ;\n /*1170*/ MOV R23, R23 ;\n /*1180*/ MOV R17, R17 ;\n /*1190*/ MOV R25, 0x1 ;\n /*11a0*/ SHF.L.U64.HI R25, R25, R23, RZ ;\n /*11b0*/ MOV R24, 0x1 ;\n /*11c0*/ SHF.L.U32 R24, R24, R23, RZ ;\n /*11d0*/ IADD3 R24, P0, R24, -0x1, RZ ;\n /*11e0*/ IADD3.X R25, R25, -0x1, RZ, P0, !PT ;\n /*11f0*/ LOP3.LUT R23, R24, R21, RZ, 0xc0, !PT ;\n /*1200*/ LOP3.LUT R22, R25, R22, RZ, 0xc0, !PT ;\n /*1210*/ MOV R16, R16 ;\n /*1220*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ;\n /*1230*/ MOV R21, R16 ;\n /*1240*/ MOV R17, R17 ;\n /*1250*/ SHF.L.U64.HI R22, R23, R21, R22 ;\n /*1260*/ SHF.L.U32 R21, R23, R21, RZ ;\n /*1270*/ MOV R16, R16 ;\n /*1280*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ;\n /*1290*/ MOV R16, R16 ;\n /*12a0*/ MOV R17, R17 ;\n /*12b0*/ SHF.L.U64.HI R17, R24, R16, R25 ;\n /*12c0*/ SHF.L.U32 R16, R24, R16, RZ ;\n /*12d0*/ LOP3.LUT R16, RZ, R16, RZ, 0x33, !PT ;\n /*12e0*/ LOP3.LUT R17, RZ, R17, RZ, 0x33, !PT ;\n /*12f0*/ LOP3.LUT R15, R15, R16, RZ, 0xc0, !PT ;\n /*1300*/ LOP3.LUT R16, R14, R17, RZ, 0xc0, !PT ;\n /*1310*/ LOP3.LUT R14, R21, R15, RZ, 0xfc, !PT ;\n /*1320*/ LOP3.LUT R15, R22, R16, RZ, 0xfc, !PT ;\n /*1330*/ MOV R14, R14 ;\n /*1340*/ MOV R15, R15 ;\n /*1350*/ MOV R14, R14 ;\n /*1360*/ MOV R15, R15 ;\n /*1370*/ MOV R14, R14 ;\n /*1380*/ MOV R15, R15 ;\n /*1390*/ I2F.F64.S64 R14, R14 ;\n /*13a0*/ DMUL R14, R14, c[0x2][0x8] ;\n /*13b0*/ F2F.F32.F64 R14, R14 ;\n /*13c0*/ ISETP.EQ.AND P0, PT, R20, RZ, PT ;\n /*13d0*/ FADD R15, -RZ, -R14 ;\n /*13e0*/ MOV R15, R15 ;\n /*13f0*/ FSEL R15, R14, R15, P0 ;\n /*1400*/ MOV R16, R15 ;\n /*1410*/ BRA `(.L_x_3) ;\n.L_x_3:\n /*1420*/ BSYNC B0 ;\n.L_x_2:\n /*1430*/ IADD3 R13, R13, 0x1, RZ ;\n /*1440*/ LOP3.LUT R14, R13, 0x1, RZ, 0xc0, !PT ;\n /*1450*/ ISETP.EQ.AND P0, PT, R14, RZ, PT ;\n /*1460*/ FSEL R14, R16, 1, P0 ;\n /*1470*/ FMUL R16, R16, R16 ;\n /*1480*/ MOV R15, 0xb94d4153 ;\n /*1490*/ MOV R13, R13 ;\n /*14a0*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x80, 0x0 ;\n /*14b0*/ MOV R14, R14 ;\n /*14c0*/ MOV R16, R16 ;\n /*14d0*/ MOV R15, R15 ;\n /*14e0*/ BSSY B0, `(.L_x_9) ;\n /*14f0*/ @P0 BRA `(.L_x_10) ;\n /*1500*/ MOV R15, 0xbab607ed ;\n /*1510*/ MOV R17, 0x37cbac00 ;\n /*1520*/ FFMA R15, R17, R16, R15 ;\n /*1530*/ MOV R15, R15 ;\n.L_x_10:\n /*1540*/ BSYNC B0 ;\n.L_x_9:\n /*1550*/ MOV R17, 0x3c0885e4 ;\n /*1560*/ FSEL R17, R17, 0.041666727513074874878, P0 ;\n /*1570*/ FFMA R15, R15, R16, R17 ;\n /*1580*/ MOV R17, 0x3e2aaaa8 ;\n /*1590*/ FSEL R17, -R17, -0.4999999701976776123, P0 ;\n /*15a0*/ FFMA R15, R15, R16, R17 ;\n /*15b0*/ MOV R17, RZ ;\n /*15c0*/ FFMA R16, R16, R14, R17 ;\n /*15d0*/ FFMA R15, R15, R16, R14 ;\n /*15e0*/ LOP3.LUT R13, R13, 0x2, RZ, 0xc0, !PT ;\n /*15f0*/ ISETP.EQ.AND P0, PT, R13, RZ, PT ;\n /*1600*/ MOV R17, R17 ;\n /*1610*/ MOV R15, R15 ;\n /*1620*/ BSSY B0, `(.L_x_11) ;\n /*1630*/ @P0 BRA `(.L_x_12) ;\n /*1640*/ MOV R13, 0xbf800000 ;\n /*1650*/ FFMA R13, R15, R13, R17 ;\n /*1660*/ MOV R15, R13 ;\n.L_x_12:\n /*1670*/ BSYNC B0 ;\n.L_x_11:\n /*1680*/ SHF.L.U32 R13, R9, 0x2, RZ ;\n /*1690*/ MOV R14, RZ ;\n /*16a0*/ IADD3 R13, R14, R13, RZ ;\n /*16b0*/ MOV R13, R13 ;\n /*16c0*/ LDS R13, [R13] ;\n /*16d0*/ FFMA R5, R15, R13, R5 ;\n /*16e0*/ IADD3 R9, R9, 0x1, RZ ;\n /*16f0*/ ISETP.LT.U32.AND P0, PT, R9, 0x2000, PT ;\n /*1700*/ MOV R5, R5 ;\n /*1710*/ MOV R9, R9 ;\n /*1720*/ @P0 BRA `(.L_x_13) ;\n /*1730*/ FMUL R8, R8, R5 ;\n /*1740*/ IMAD.WIDE R10, R10, 0x4, RZ ;\n /*1750*/ MOV R2, R10 ;\n /*1760*/ MOV R3, R11 ;\n /*1770*/ IADD3 R2, P0, R7, R2, RZ ;\n /*1780*/ IADD3.X R3, R6, R3, RZ, P0, !PT ;\n /*1790*/ MOV R2, R2 ;\n /*17a0*/ MOV R3, R3 ;\n /*17b0*/ MOV R2, R2 ;\n /*17c0*/ MOV R3, R3 ;\n /*17d0*/ R2UR UR4, R18 ;\n /*17e0*/ R2UR UR5, R19 ;\n /*17f0*/ STG.E [R2.64], R8 ;\n /*1800*/ EXIT ;\n.L_x_14:\n /*1810*/ BRA `(.L_x_14);\n /*1820*/ NOP;\n /*1830*/ NOP;\n /*1840*/ NOP;\n /*1850*/ NOP;\n /*1860*/ NOP;\n /*1870*/ NOP;\n /*1880*/ NOP;\n /*1890*/ NOP;\n /*18a0*/ NOP;\n /*18b0*/ NOP;\n /*18c0*/ NOP;\n /*18d0*/ NOP;\n /*18e0*/ NOP;\n /*18f0*/ NOP;\n.L_x_15:\n"},"hip":{"kind":"string","value":"\t.text\n\t.file\t\"cuda_code_028189.hip\"\n\t.globl\t_Z24__device_stub__dctKernelPfS_ # -- Begin function _Z24__device_stub__dctKernelPfS_\n\t.p2align\t4, 0x90\n\t.type\t_Z24__device_stub__dctKernelPfS_,@function\n_Z24__device_stub__dctKernelPfS_: # @_Z24__device_stub__dctKernelPfS_\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$88, %rsp\n\t.cfi_def_cfa_offset 96\n\tmovq\t%rdi, 56(%rsp)\n\tmovq\t%rsi, 48(%rsp)\n\tleaq\t56(%rsp), %rax\n\tmovq\t%rax, 64(%rsp)\n\tleaq\t48(%rsp), %rax\n\tmovq\t%rax, 72(%rsp)\n\tleaq\t32(%rsp), %rdi\n\tleaq\t16(%rsp), %rsi\n\tleaq\t8(%rsp), %rdx\n\tmovq\t%rsp, %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t32(%rsp), %rsi\n\tmovl\t40(%rsp), %edx\n\tmovq\t16(%rsp), %rcx\n\tmovl\t24(%rsp), %r8d\n\tleaq\t64(%rsp), %r9\n\tmovl\t$_Z9dctKernelPfS_, %edi\n\tpushq\t(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t16(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$104, %rsp\n\t.cfi_adjust_cfa_offset -104\n\tretq\n.Lfunc_end0:\n\t.size\t_Z24__device_stub__dctKernelPfS_, .Lfunc_end0-_Z24__device_stub__dctKernelPfS_\n\t.cfi_endproc\n # -- End function\n\t.globl\t_Z15initializeInputPfi # -- Begin function _Z15initializeInputPfi\n\t.p2align\t4, 0x90\n\t.type\t_Z15initializeInputPfi,@function\n_Z15initializeInputPfi: # @_Z15initializeInputPfi\n\t.cfi_startproc\n# %bb.0:\n\ttestl\t%esi, %esi\n\tjle\t.LBB1_5\n# %bb.1:\n\tmovl\t%esi, %edx\n\tmovl\t%edx, %eax\n\tandl\t$3, %eax\n\tcmpl\t$4, %esi\n\tjae\t.LBB1_6\n# %bb.2:\n\txorl\t%ecx, %ecx\n\tjmp\t.LBB1_3\n.LBB1_6:\n\tandl\t$2147483644, %edx # imm = 0x7FFFFFFC\n\txorl\t%ecx, %ecx\n\t.p2align\t4, 0x90\n.LBB1_7: # =>This Inner Loop Header: Depth=1\n\txorps\t%xmm0, %xmm0\n\tcvtsi2ss\t%ecx, %xmm0\n\tmovss\t%xmm0, (%rdi,%rcx,4)\n\tleal\t1(%rcx), %esi\n\txorps\t%xmm0, %xmm0\n\tcvtsi2ss\t%esi, %xmm0\n\tmovss\t%xmm0, 4(%rdi,%rcx,4)\n\tleal\t2(%rcx), %esi\n\txorps\t%xmm0, %xmm0\n\tcvtsi2ss\t%esi, %xmm0\n\tleal\t3(%rcx), %esi\n\txorps\t%xmm1, %xmm1\n\tcvtsi2ss\t%esi, %xmm1\n\tmovss\t%xmm0, 8(%rdi,%rcx,4)\n\tmovss\t%xmm1, 12(%rdi,%rcx,4)\n\taddq\t$4, %rcx\n\tcmpq\t%rdx, %rcx\n\tjne\t.LBB1_7\n.LBB1_3:\n\ttestq\t%rax, %rax\n\tje\t.LBB1_5\n\t.p2align\t4, 0x90\n.LBB1_4: # =>This Inner Loop Header: Depth=1\n\txorps\t%xmm0, %xmm0\n\tcvtsi2ss\t%ecx, %xmm0\n\tmovss\t%xmm0, (%rdi,%rcx,4)\n\tincq\t%rcx\n\tdecq\t%rax\n\tjne\t.LBB1_4\n.LBB1_5:\n\tretq\n.Lfunc_end1:\n\t.size\t_Z15initializeInputPfi, .Lfunc_end1-_Z15initializeInputPfi\n\t.cfi_endproc\n # -- End function\n\t.globl\tmain # -- Begin function main\n\t.p2align\t4, 0x90\n\t.type\tmain,@function\nmain: # @main\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rbp\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 32\n\tsubq\t$16, %rsp\n\t.cfi_def_cfa_offset 48\n\t.cfi_offset %rbx, -32\n\t.cfi_offset %r14, -24\n\t.cfi_offset %rbp, -16\n\tmovl\t$32768, %edi # imm = 0x8000\n\tcallq\t_Znam\n\tmovq\t%rax, %rbx\n\tmovl\t$32768, %edi # imm = 0x8000\n\tcallq\t_Znam\n\tmovq\t%rax, %r14\n\txorl\t%eax, %eax\n\t.p2align\t4, 0x90\n.LBB2_1: # =>This Inner Loop Header: Depth=1\n\txorps\t%xmm0, %xmm0\n\tcvtsi2ss\t%eax, %xmm0\n\tmovss\t%xmm0, (%rbx,%rax,4)\n\tleal\t1(%rax), %ecx\n\txorps\t%xmm0, %xmm0\n\tcvtsi2ss\t%ecx, %xmm0\n\tmovss\t%xmm0, 4(%rbx,%rax,4)\n\tleal\t2(%rax), %ecx\n\txorps\t%xmm0, %xmm0\n\tcvtsi2ss\t%ecx, %xmm0\n\tleal\t3(%rax), %ecx\n\txorps\t%xmm1, %xmm1\n\tcvtsi2ss\t%ecx, %xmm1\n\tmovss\t%xmm0, 8(%rbx,%rax,4)\n\tmovss\t%xmm1, 12(%rbx,%rax,4)\n\taddq\t$4, %rax\n\tcmpq\t$8192, %rax # imm = 0x2000\n\tjne\t.LBB2_1\n# %bb.2:\n\tmovq\t%rsp, %rdi\n\tmovl\t$32768, %esi # imm = 0x8000\n\tcallq\thipMalloc\n\ttestl\t%eax, %eax\n\tje\t.LBB2_5\n# %bb.3:\n\tmovl\t%eax, %ebp\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$42, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n\tmovl\t%ebp, %edi\n\tcallq\thipGetErrorString\n\ttestq\t%rax, %rax\n\tje\t.LBB2_8\n# %bb.4:\n\tmovq\t%rax, %rdi\n\tmovq\t%rax, %rbx\n\tcallq\tstrlen\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rbx, %rsi\n\tmovq\t%rax, %rdx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n\tjmp\t.LBB2_9\n.LBB2_5:\n\tleaq\t8(%rsp), %rdi\n\tmovl\t$32768, %esi # imm = 0x8000\n\tcallq\thipMalloc\n\ttestl\t%eax, %eax\n\tje\t.LBB2_14\n# %bb.6:\n\tmovl\t%eax, %ebp\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$43, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n\tmovl\t%ebp, %edi\n\tcallq\thipGetErrorString\n\ttestq\t%rax, %rax\n\tje\t.LBB2_17\n# %bb.7:\n\tmovq\t%rax, %rdi\n\tmovq\t%rax, %rbx\n\tcallq\tstrlen\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rbx, %rsi\n\tmovq\t%rax, %rdx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n\tjmp\t.LBB2_18\n.LBB2_8:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tleaq\t_ZSt4cerr(%rax), %rdi\n\tmovl\t_ZSt4cerr+32(%rax), %esi\n\torl\t$1, %esi\n\tcallq\t_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate\n.LBB2_9:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tmovq\t_ZSt4cerr+240(%rax), %rbx\n\ttestq\t%rbx, %rbx\n\tje\t.LBB2_45\n# %bb.10:\n\tcmpb\t$0, 56(%rbx)\n\tje\t.LBB2_12\n# %bb.11:\n\tmovzbl\t67(%rbx), %eax\n\tjmp\t.LBB2_13\n.LBB2_12:\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZNKSt5ctypeIcE13_M_widen_initEv\n\tmovq\t(%rbx), %rax\n\tmovq\t%rbx, %rdi\n\tmovl\t$10, %esi\n\tcallq\t*48(%rax)\n.LBB2_13:\n\tmovsbl\t%al, %esi\n\tmovl\t$_ZSt4cerr, %edi\n\tcallq\t_ZNSo3putEc\n\tmovq\t%rax, %rdi\n\tcallq\t_ZNSo5flushEv\n\tjmp\t.LBB2_42\n.LBB2_14:\n\tmovq\t(%rsp), %rdi\n\tmovl\t$32768, %edx # imm = 0x8000\n\tmovq\t%rbx, %rsi\n\tmovl\t$1, %ecx\n\tcallq\thipMemcpy\n\ttestl\t%eax, %eax\n\tje\t.LBB2_23\n# %bb.15:\n\tmovl\t%eax, %ebp\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$36, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n\tmovl\t%ebp, %edi\n\tcallq\thipGetErrorString\n\ttestq\t%rax, %rax\n\tje\t.LBB2_28\n# %bb.16:\n\tmovq\t%rax, %rdi\n\tmovq\t%rax, %rbx\n\tcallq\tstrlen\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rbx, %rsi\n\tmovq\t%rax, %rdx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n\tjmp\t.LBB2_29\n.LBB2_17:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tleaq\t_ZSt4cerr(%rax), %rdi\n\tmovl\t_ZSt4cerr+32(%rax), %esi\n\torl\t$1, %esi\n\tcallq\t_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate\n.LBB2_18:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tmovq\t_ZSt4cerr+240(%rax), %rbx\n\ttestq\t%rbx, %rbx\n\tje\t.LBB2_45\n# %bb.19:\n\tcmpb\t$0, 56(%rbx)\n\tje\t.LBB2_21\n# %bb.20:\n\tmovzbl\t67(%rbx), %eax\n\tjmp\t.LBB2_22\n.LBB2_21:\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZNKSt5ctypeIcE13_M_widen_initEv\n\tmovq\t(%rbx), %rax\n\tmovq\t%rbx, %rdi\n\tmovl\t$10, %esi\n\tcallq\t*48(%rax)\n.LBB2_22:\n\tmovsbl\t%al, %esi\n\tmovl\t$_ZSt4cerr, %edi\n\tcallq\t_ZNSo3putEc\n\tmovq\t%rax, %rdi\n\tcallq\t_ZNSo5flushEv\n\tmovq\t(%rsp), %rdi\n\tjmp\t.LBB2_41\n.LBB2_23:\n\tmovabsq\t$4294967328, %rdi # imm = 0x100000020\n\tleaq\t224(%rdi), %rdx\n\tmovl\t$1024, %r8d # imm = 0x400\n\tmovl\t$1, %esi\n\tmovl\t$1, %ecx\n\txorl\t%r9d, %r9d\n\tcallq\t__hipPushCallConfiguration\n\ttestl\t%eax, %eax\n\tjne\t.LBB2_25\n# %bb.24:\n\tmovq\t(%rsp), %rdi\n\tmovq\t8(%rsp), %rsi\n\tcallq\t_Z24__device_stub__dctKernelPfS_\n.LBB2_25:\n\tcallq\thipGetLastError\n\ttestl\t%eax, %eax\n\tje\t.LBB2_32\n# %bb.26:\n\tmovl\t%eax, %ebp\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str.3, %esi\n\tmovl\t$24, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n\tmovl\t%ebp, %edi\n\tcallq\thipGetErrorString\n\ttestq\t%rax, %rax\n\tje\t.LBB2_34\n# %bb.27:\n\tmovq\t%rax, %rdi\n\tmovq\t%rax, %rbx\n\tcallq\tstrlen\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rbx, %rsi\n\tmovq\t%rax, %rdx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n\tjmp\t.LBB2_35\n.LBB2_28:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tleaq\t_ZSt4cerr(%rax), %rdi\n\tmovl\t_ZSt4cerr+32(%rax), %esi\n\torl\t$1, %esi\n\tcallq\t_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate\n.LBB2_29:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tmovq\t_ZSt4cerr+240(%rax), %rbx\n\ttestq\t%rbx, %rbx\n\tje\t.LBB2_45\n# %bb.30:\n\tcmpb\t$0, 56(%rbx)\n\tje\t.LBB2_38\n.LBB2_31:\n\tmovzbl\t67(%rbx), %eax\n\tjmp\t.LBB2_39\n.LBB2_32:\n\tmovq\t8(%rsp), %rsi\n\tmovl\t$32768, %edx # imm = 0x8000\n\tmovq\t%r14, %rdi\n\tmovl\t$2, %ecx\n\tcallq\thipMemcpy\n\ttestl\t%eax, %eax\n\tje\t.LBB2_44\n# %bb.33:\n\tmovl\t%eax, %ebp\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str.4, %esi\n\tmovl\t$35, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n\tmovl\t%ebp, %edi\n\tcallq\thipGetErrorString\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rax, %rsi\n\tcallq\t_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_\n\tjmp\t.LBB2_40\n.LBB2_34:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tleaq\t_ZSt4cerr(%rax), %rdi\n\tmovl\t_ZSt4cerr+32(%rax), %esi\n\torl\t$1, %esi\n\tcallq\t_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate\n.LBB2_35:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tmovq\t_ZSt4cerr+240(%rax), %rbx\n\ttestq\t%rbx, %rbx\n\tje\t.LBB2_45\n# %bb.36:\n\tcmpb\t$0, 56(%rbx)\n\tjne\t.LBB2_31\n.LBB2_38:\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZNKSt5ctypeIcE13_M_widen_initEv\n\tmovq\t(%rbx), %rax\n\tmovq\t%rbx, %rdi\n\tmovl\t$10, %esi\n\tcallq\t*48(%rax)\n.LBB2_39:\n\tmovsbl\t%al, %esi\n\tmovl\t$_ZSt4cerr, %edi\n\tcallq\t_ZNSo3putEc\n\tmovq\t%rax, %rdi\n\tcallq\t_ZNSo5flushEv\n.LBB2_40:\n\tmovq\t(%rsp), %rdi\n\tcallq\thipFree\n\tmovq\t8(%rsp), %rdi\n.LBB2_41:\n\tcallq\thipFree\n.LBB2_42:\n\tmovl\t$-1, %eax\n.LBB2_43:\n\taddq\t$16, %rsp\n\t.cfi_def_cfa_offset 32\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 16\n\tpopq\t%rbp\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB2_44:\n\t.cfi_def_cfa_offset 48\n\tmovq\t(%rsp), %rdi\n\tcallq\thipFree\n\tmovq\t8(%rsp), %rdi\n\tcallq\thipFree\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZdaPv\n\tmovq\t%r14, %rdi\n\tcallq\t_ZdaPv\n\tmovl\t$_ZSt4cout, %edi\n\tmovl\t$.L.str.5, %esi\n\tmovl\t$39, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n\tmovl\t$_ZSt4cout, %edi\n\tcallq\t_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_\n\txorl\t%eax, %eax\n\tjmp\t.LBB2_43\n.LBB2_45:\n\tcallq\t_ZSt16__throw_bad_castv\n.Lfunc_end2:\n\t.size\tmain, .Lfunc_end2-main\n\t.cfi_endproc\n # -- End function\n\t.section\t.text.startup,\"ax\",@progbits\n\t.p2align\t4, 0x90 # -- Begin function _GLOBAL__sub_I_cuda_code_028189.hip\n\t.type\t_GLOBAL__sub_I_cuda_code_028189.hip,@function\n_GLOBAL__sub_I_cuda_code_028189.hip: # @_GLOBAL__sub_I_cuda_code_028189.hip\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 16\n\tmovl\t$_ZStL8__ioinit, %edi\n\tcallq\t_ZNSt8ios_base4InitC1Ev\n\tmovl\t$_ZNSt8ios_base4InitD1Ev, %edi\n\tmovl\t$_ZStL8__ioinit, %esi\n\tmovl\t$__dso_handle, %edx\n\tpopq\t%rax\n\t.cfi_def_cfa_offset 8\n\tjmp\t__cxa_atexit # TAILCALL\n.Lfunc_end3:\n\t.size\t_GLOBAL__sub_I_cuda_code_028189.hip, .Lfunc_end3-_GLOBAL__sub_I_cuda_code_028189.hip\n\t.cfi_endproc\n # -- End function\n\t.text\n\t.p2align\t4, 0x90 # -- Begin function __hip_module_ctor\n\t.type\t__hip_module_ctor,@function\n__hip_module_ctor: # @__hip_module_ctor\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$40, %rsp\n\t.cfi_def_cfa_offset 48\n\tmovq\t__hip_gpubin_handle(%rip), %rdi\n\ttestq\t%rdi, %rdi\n\tjne\t.LBB4_2\n# %bb.1:\n\tmovl\t$__hip_fatbin_wrapper, %edi\n\tcallq\t__hipRegisterFatBinary\n\tmovq\t%rax, %rdi\n\tmovq\t%rax, __hip_gpubin_handle(%rip)\n.LBB4_2:\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, 16(%rsp)\n\tmovups\t%xmm0, (%rsp)\n\tmovl\t$_Z9dctKernelPfS_, %esi\n\tmovl\t$.L__unnamed_1, %edx\n\tmovl\t$.L__unnamed_1, %ecx\n\tmovl\t$-1, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipRegisterFunction\n\tmovl\t$__hip_module_dtor, %edi\n\taddq\t$40, %rsp\n\t.cfi_def_cfa_offset 8\n\tjmp\tatexit # TAILCALL\n.Lfunc_end4:\n\t.size\t__hip_module_ctor, .Lfunc_end4-__hip_module_ctor\n\t.cfi_endproc\n # -- End function\n\t.p2align\t4, 0x90 # -- Begin function __hip_module_dtor\n\t.type\t__hip_module_dtor,@function\n__hip_module_dtor: # @__hip_module_dtor\n\t.cfi_startproc\n# %bb.0:\n\tmovq\t__hip_gpubin_handle(%rip), %rdi\n\ttestq\t%rdi, %rdi\n\tje\t.LBB5_2\n# %bb.1:\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 16\n\tcallq\t__hipUnregisterFatBinary\n\tmovq\t$0, __hip_gpubin_handle(%rip)\n\taddq\t$8, %rsp\n\t.cfi_def_cfa_offset 8\n.LBB5_2:\n\tretq\n.Lfunc_end5:\n\t.size\t__hip_module_dtor, .Lfunc_end5-__hip_module_dtor\n\t.cfi_endproc\n # -- End function\n\t.type\t_ZStL8__ioinit,@object # @_ZStL8__ioinit\n\t.local\t_ZStL8__ioinit\n\t.comm\t_ZStL8__ioinit,1,1\n\t.hidden\t__dso_handle\n\t.type\t_Z9dctKernelPfS_,@object # @_Z9dctKernelPfS_\n\t.section\t.rodata,\"a\",@progbits\n\t.globl\t_Z9dctKernelPfS_\n\t.p2align\t3, 0x0\n_Z9dctKernelPfS_:\n\t.quad\t_Z24__device_stub__dctKernelPfS_\n\t.size\t_Z9dctKernelPfS_, 8\n\n\t.type\t.L.str,@object # @.str\n\t.section\t.rodata.str1.1,\"aMS\",@progbits,1\n.L.str:\n\t.asciz\t\"Error allocating device memory for input: \"\n\t.size\t.L.str, 43\n\n\t.type\t.L.str.1,@object # @.str.1\n.L.str.1:\n\t.asciz\t\"Error allocating device memory for output: \"\n\t.size\t.L.str.1, 44\n\n\t.type\t.L.str.2,@object # @.str.2\n.L.str.2:\n\t.asciz\t\"Error copying input data to device: \"\n\t.size\t.L.str.2, 37\n\n\t.type\t.L.str.3,@object # @.str.3\n.L.str.3:\n\t.asciz\t\"Error launching kernel: \"\n\t.size\t.L.str.3, 25\n\n\t.type\t.L.str.4,@object # @.str.4\n.L.str.4:\n\t.asciz\t\"Error copying output data to host: \"\n\t.size\t.L.str.4, 36\n\n\t.type\t.L.str.5,@object # @.str.5\n.L.str.5:\n\t.asciz\t\"DCT computation completed successfully.\"\n\t.size\t.L.str.5, 40\n\n\t.type\t.L__unnamed_1,@object # @0\n.L__unnamed_1:\n\t.asciz\t\"_Z9dctKernelPfS_\"\n\t.size\t.L__unnamed_1, 17\n\n\t.type\t__hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper\n\t.section\t.hipFatBinSegment,\"a\",@progbits\n\t.p2align\t3, 0x0\n__hip_fatbin_wrapper:\n\t.long\t1212764230 # 0x48495046\n\t.long\t1 # 0x1\n\t.quad\t__hip_fatbin\n\t.quad\t0\n\t.size\t__hip_fatbin_wrapper, 24\n\n\t.type\t__hip_gpubin_handle,@object # @__hip_gpubin_handle\n\t.local\t__hip_gpubin_handle\n\t.comm\t__hip_gpubin_handle,8,8\n\t.section\t.init_array,\"aw\",@init_array\n\t.p2align\t3, 0x0\n\t.quad\t_GLOBAL__sub_I_cuda_code_028189.hip\n\t.quad\t__hip_module_ctor\n\t.type\t__hip_cuid_,@object # @__hip_cuid_\n\t.bss\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 # 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n"}}},{"rowIdx":162571,"cells":{"id":{"kind":"string","value":"fd9b245afe7de6d03f859452bb8c93d4bf35a1f2_O1"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z13sigmoidKernelIdEvPT_S1_i --------------------------\n .section .text._Z13sigmoidKernelIdEvPT_S1_i,\"ax\",@progbits\n .sectionflags @\"SHF_BARRIERS=1\"\n .sectioninfo @\"SHI_REGISTERS=16\"\n .align 128\n\n\n\n\n .global _Z13sigmoidKernelIdEvPT_S1_i\n .type _Z13sigmoidKernelIdEvPT_S1_i,@function\n .size _Z13sigmoidKernelIdEvPT_S1_i,(.L_x_21 - _Z13sigmoidKernelIdEvPT_S1_i)\n .other _Z13sigmoidKernelIdEvPT_S1_i,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z13sigmoidKernelIdEvPT_S1_i:\n.text._Z13sigmoidKernelIdEvPT_S1_i:\n /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;\n /*0010*/ S2R R0, SR_TID.X ;\n /*0020*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*0030*/ BSSY B0, `(.L_x_0) ;\n /*0040*/ S2R R3, SR_CTAID.X ;\n /*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ;\n /*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ;\n /*0070*/ @P0 BRA `(.L_x_1) ;\n /*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ;\n /*0090*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ;\n /*00a0*/ LDG.E.64 R4, [R4.64] ;\n /*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x652b82fe ;\n /*00c0*/ BSSY B1, `(.L_x_2) ;\n /*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3ff71547 ;\n /*00e0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x69ce2bdf ;\n /*00f0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3e5ade15 ;\n /*0100*/ DFMA R2, -R4, R2, 6.75539944105574400000e+15 ;\n /*0110*/ DADD R6, R2, -6.75539944105574400000e+15 ;\n /*0120*/ DFMA R8, R6, c[0x2][0x0], -R4 ;\n /*0130*/ DFMA R8, R6, c[0x2][0x8], R8 ;\n /*0140*/ DFMA R6, R8, R10, c[0x2][0x10] ;\n /*0150*/ DFMA R6, R8, R6, c[0x2][0x18] ;\n /*0160*/ DFMA R6, R8, R6, c[0x2][0x20] ;\n /*0170*/ DFMA R6, R8, R6, c[0x2][0x28] ;\n /*0180*/ DFMA R6, R8, R6, c[0x2][0x30] ;\n /*0190*/ DFMA R6, R8, R6, c[0x2][0x38] ;\n /*01a0*/ DFMA R6, R8, R6, c[0x2][0x40] ;\n /*01b0*/ DFMA R6, R8, R6, c[0x2][0x48] ;\n /*01c0*/ DFMA R6, R8, R6, c[0x2][0x50] ;\n /*01d0*/ DFMA R6, R8, R6, 1 ;\n /*01e0*/ DFMA R8, R8, R6, 1 ;\n /*01f0*/ DADD R6, -RZ, -R4 ;\n /*0200*/ IMAD R11, R2, 0x100000, R9 ;\n /*0210*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ;\n /*0220*/ IMAD.MOV.U32 R12, RZ, RZ, R7 ;\n /*0230*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ;\n /*0240*/ FSETP.GEU.AND P0, PT, |R12|, 4.1917929649353027344, PT ;\n /*0250*/ @!P0 BRA `(.L_x_3) ;\n /*0260*/ DSETP.GT.AND P0, PT, R4, RZ, PT ;\n /*0270*/ DADD R4, -R4, +INF ;\n /*0280*/ FSEL R10, R4, RZ, !P0 ;\n /*0290*/ FSEL R11, R5, RZ, !P0 ;\n /*02a0*/ FSETP.GEU.AND P0, PT, |R12|, 4.2275390625, PT ;\n /*02b0*/ @!P0 LEA.HI R3, R2, R2, RZ, 0x1 ;\n /*02c0*/ @!P0 SHF.R.S32.HI R3, RZ, 0x1, R3 ;\n /*02d0*/ @!P0 IMAD R9, R3, 0x100000, R9 ;\n /*02e0*/ @!P0 IMAD.IADD R3, R2, 0x1, -R3 ;\n /*02f0*/ @!P0 MOV R2, RZ ;\n /*0300*/ @!P0 LEA R3, R3, 0x3ff00000, 0x14 ;\n /*0310*/ @!P0 DMUL R10, R8, R2 ;\n.L_x_3:\n /*0320*/ BSYNC B1 ;\n.L_x_2:\n /*0330*/ DADD R10, R10, 1 ;\n /*0340*/ BSSY B1, `(.L_x_4) ;\n /*0350*/ MUFU.RCP64H R3, R11 ;\n /*0360*/ IADD3 R2, R11, 0x300402, RZ ;\n /*0370*/ FSETP.GEU.AND P0, PT, |R2|, 5.8789094863358348022e-39, PT ;\n /*0380*/ DFMA R4, -R10, R2, 1 ;\n /*0390*/ DFMA R4, R4, R4, R4 ;\n /*03a0*/ DFMA R4, R2, R4, R2 ;\n /*03b0*/ DFMA R2, -R10, R4, 1 ;\n /*03c0*/ DFMA R2, R4, R2, R4 ;\n /*03d0*/ @P0 BRA `(.L_x_5) ;\n /*03e0*/ LOP3.LUT R2, R11, 0x7fffffff, RZ, 0xc0, !PT ;\n /*03f0*/ IADD3 R3, R2, -0x100000, RZ ;\n /*0400*/ MOV R2, 0x420 ;\n /*0410*/ CALL.REL.NOINC `($__internal_0_$__cuda_sm20_dblrcp_rn_slowpath_v3) ;\n /*0420*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ;\n /*0430*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ;\n.L_x_5:\n /*0440*/ BSYNC B1 ;\n.L_x_4:\n /*0450*/ LEA R4, P0, R0, c[0x0][0x168], 0x3 ;\n /*0460*/ LEA.HI.X R5, R0, c[0x0][0x16c], R7, 0x3, P0 ;\n /*0470*/ STG.E.64 [R4.64], R2 ;\n.L_x_1:\n /*0480*/ BSYNC B0 ;\n.L_x_0:\n /*0490*/ BAR.SYNC.DEFER_BLOCKING 0x0 ;\n /*04a0*/ EXIT ;\n\n\n\n\n .weak $__internal_0_$__cuda_sm20_dblrcp_rn_slowpath_v3\n .type $__internal_0_$__cuda_sm20_dblrcp_rn_slowpath_v3,@function\n .size $__internal_0_$__cuda_sm20_dblrcp_rn_slowpath_v3,(.L_x_21 - $__internal_0_$__cuda_sm20_dblrcp_rn_slowpath_v3)\n$__internal_0_$__cuda_sm20_dblrcp_rn_slowpath_v3:\n /*04b0*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ;\n /*04c0*/ BSSY B2, `(.L_x_6) ;\n /*04d0*/ IMAD.MOV.U32 R13, RZ, RZ, R11 ;\n /*04e0*/ LOP3.LUT R6, R11, 0x7fffffff, RZ, 0xc0, !PT ;\n /*04f0*/ DSETP.GTU.AND P0, PT, |R12|, +INF , PT ;\n /*0500*/ @P0 BRA `(.L_x_7) ;\n /*0510*/ IADD3 R4, R6, -0x1, RZ ;\n /*0520*/ ISETP.GE.U32.AND P0, PT, R4, 0x7fefffff, PT ;\n /*0530*/ @P0 LOP3.LUT R5, R13, 0x7ff00000, RZ, 0x3c, !PT ;\n /*0540*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ;\n /*0550*/ @P0 BRA `(.L_x_8) ;\n /*0560*/ ISETP.GE.U32.AND P0, PT, R6, 0x1000001, PT ;\n /*0570*/ @!P0 BRA `(.L_x_9) ;\n /*0580*/ IADD3 R5, R13, -0x3fe00000, RZ ;\n /*0590*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ;\n /*05a0*/ MOV R4, R12 ;\n /*05b0*/ MUFU.RCP64H R9, R5 ;\n /*05c0*/ DFMA R10, -R4, R8, 1 ;\n /*05d0*/ DFMA R10, R10, R10, R10 ;\n /*05e0*/ DFMA R10, R8, R10, R8 ;\n /*05f0*/ DFMA R8, -R4, R10, 1 ;\n /*0600*/ DFMA R8, R10, R8, R10 ;\n /*0610*/ DMUL R8, R8, 2.2250738585072013831e-308 ;\n /*0620*/ DFMA R10, -R12, R8, 1 ;\n /*0630*/ DFMA R10, R10, R10, R10 ;\n /*0640*/ DFMA R4, R8, R10, R8 ;\n /*0650*/ BRA `(.L_x_8) ;\n.L_x_9:\n /*0660*/ DMUL R8, R12, 8.11296384146066816958e+31 ;\n /*0670*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ;\n /*0680*/ MUFU.RCP64H R5, R9 ;\n /*0690*/ DFMA R10, -R8, R4, 1 ;\n /*06a0*/ DFMA R10, R10, R10, R10 ;\n /*06b0*/ DFMA R10, R4, R10, R4 ;\n /*06c0*/ DFMA R4, -R8, R10, 1 ;\n /*06d0*/ DFMA R4, R10, R4, R10 ;\n /*06e0*/ DMUL R4, R4, 8.11296384146066816958e+31 ;\n /*06f0*/ BRA `(.L_x_8) ;\n.L_x_7:\n /*0700*/ LOP3.LUT R5, R13, 0x80000, RZ, 0xfc, !PT ;\n /*0710*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ;\n.L_x_8:\n /*0720*/ BSYNC B2 ;\n.L_x_6:\n /*0730*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ;\n /*0740*/ RET.REL.NODEC R2 `(_Z13sigmoidKernelIdEvPT_S1_i) ;\n.L_x_10:\n /*0750*/ BRA `(.L_x_10);\n /*0760*/ NOP;\n /*0770*/ NOP;\n /*0780*/ NOP;\n /*0790*/ NOP;\n /*07a0*/ NOP;\n /*07b0*/ NOP;\n /*07c0*/ NOP;\n /*07d0*/ NOP;\n /*07e0*/ NOP;\n /*07f0*/ NOP;\n.L_x_21:\n\n\n//--------------------- .text._Z13sigmoidKernelIfEvPT_S1_i --------------------------\n .section .text._Z13sigmoidKernelIfEvPT_S1_i,\"ax\",@progbits\n .sectionflags @\"SHF_BARRIERS=1\"\n .sectioninfo @\"SHI_REGISTERS=14\"\n .align 128\n\n\n\n\n .global _Z13sigmoidKernelIfEvPT_S1_i\n .type _Z13sigmoidKernelIfEvPT_S1_i,@function\n .size _Z13sigmoidKernelIfEvPT_S1_i,(.L_x_22 - _Z13sigmoidKernelIfEvPT_S1_i)\n .other _Z13sigmoidKernelIfEvPT_S1_i,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z13sigmoidKernelIfEvPT_S1_i:\n.text._Z13sigmoidKernelIfEvPT_S1_i:\n /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;\n /*0010*/ S2R R3, SR_TID.X ;\n /*0020*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*0030*/ BSSY B0, `(.L_x_11) ;\n /*0040*/ S2R R0, SR_CTAID.X ;\n /*0050*/ IMAD R3, R0, c[0x0][0x0], R3 ;\n /*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ;\n /*0070*/ @P0 BRA `(.L_x_12) ;\n /*0080*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ;\n /*0090*/ IMAD.WIDE R4, R3, R4, c[0x0][0x160] ;\n /*00a0*/ LDG.E R4, [R4.64] ;\n /*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3bbb989d ;\n /*00c0*/ MOV R9, 0x437c0000 ;\n /*00d0*/ BSSY B1, `(.L_x_13) ;\n /*00e0*/ FFMA.SAT R0, -R4, R7, 0.5 ;\n /*00f0*/ FFMA.RM R0, R0, R9, 12582913 ;\n /*0100*/ FADD R7, R0.reuse, -12583039 ;\n /*0110*/ IMAD.SHL.U32 R0, R0, 0x800000, RZ ;\n /*0120*/ FFMA R7, -R4, 1.4426950216293334961, -R7 ;\n /*0130*/ FFMA R7, -R4, 1.925963033500011079e-08, R7 ;\n /*0140*/ MUFU.EX2 R7, R7 ;\n /*0150*/ FFMA R0, R0, R7, 1 ;\n /*0160*/ IADD3 R2, R0, 0x1800000, RZ ;\n /*0170*/ LOP3.LUT R2, R2, 0x7f800000, RZ, 0xc0, !PT ;\n /*0180*/ ISETP.GT.U32.AND P0, PT, R2, 0x1ffffff, PT ;\n /*0190*/ @P0 BRA `(.L_x_14) ;\n /*01a0*/ MOV R11, 0x1c0 ;\n /*01b0*/ CALL.REL.NOINC `($__internal_1_$__cuda_sm20_rcp_rn_f32_slowpath) ;\n /*01c0*/ IMAD.MOV.U32 R5, RZ, RZ, R0 ;\n /*01d0*/ BRA `(.L_x_15) ;\n.L_x_14:\n /*01e0*/ MUFU.RCP R5, R0 ;\n /*01f0*/ FFMA R2, R0, R5, -1 ;\n /*0200*/ FADD.FTZ R2, -R2, -RZ ;\n /*0210*/ FFMA R5, R5, R2, R5 ;\n.L_x_15:\n /*0220*/ BSYNC B1 ;\n.L_x_13:\n /*0230*/ MOV R2, 0x4 ;\n /*0240*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ;\n /*0250*/ STG.E [R2.64], R5 ;\n.L_x_12:\n /*0260*/ BSYNC B0 ;\n.L_x_11:\n /*0270*/ BAR.SYNC.DEFER_BLOCKING 0x0 ;\n /*0280*/ EXIT ;\n\n\n\n\n .weak $__internal_1_$__cuda_sm20_rcp_rn_f32_slowpath\n .type $__internal_1_$__cuda_sm20_rcp_rn_f32_slowpath,@function\n .size $__internal_1_$__cuda_sm20_rcp_rn_f32_slowpath,(.L_x_22 - $__internal_1_$__cuda_sm20_rcp_rn_f32_slowpath)\n$__internal_1_$__cuda_sm20_rcp_rn_f32_slowpath:\n /*0290*/ IMAD.SHL.U32 R2, R0, 0x2, RZ ;\n /*02a0*/ BSSY B2, `(.L_x_16) ;\n /*02b0*/ SHF.R.U32.HI R2, RZ, 0x18, R2 ;\n /*02c0*/ ISETP.NE.U32.AND P0, PT, R2, RZ, PT ;\n /*02d0*/ @P0 BRA `(.L_x_17) ;\n /*02e0*/ IMAD.SHL.U32 R2, R0, 0x2, RZ ;\n /*02f0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ;\n /*0300*/ @P0 FFMA R5, R0, 1.84467440737095516160e+19, RZ ;\n /*0310*/ @P0 MUFU.RCP R2, R5 ;\n /*0320*/ @P0 FFMA R4, R5, R2, -1 ;\n /*0330*/ @P0 FADD.FTZ R7, -R4, -RZ ;\n /*0340*/ @!P0 MUFU.RCP R4, R0 ;\n /*0350*/ @P0 FFMA R2, R2, R7, R2 ;\n /*0360*/ @P0 FFMA R4, R2, 1.84467440737095516160e+19, RZ ;\n /*0370*/ BRA `(.L_x_18) ;\n.L_x_17:\n /*0380*/ IADD3 R4, R2, -0xfd, RZ ;\n /*0390*/ ISETP.GT.U32.AND P0, PT, R4, 0x1, PT ;\n /*03a0*/ @P0 BRA `(.L_x_19) ;\n /*03b0*/ LOP3.LUT R5, R0, 0x7fffff, RZ, 0xc0, !PT ;\n /*03c0*/ IADD3 R2, R2, -0xfc, RZ ;\n /*03d0*/ LOP3.LUT R5, R5, 0x3f800000, RZ, 0xfc, !PT ;\n /*03e0*/ MUFU.RCP R6, R5 ;\n /*03f0*/ FFMA R7, R5, R6, -1 ;\n /*0400*/ FADD.FTZ R7, -R7, -RZ ;\n /*0410*/ FFMA.RM R8, R6.reuse, R7.reuse, R6.reuse ;\n /*0420*/ FFMA.RP R7, R6, R7, R6 ;\n /*0430*/ FSETP.NEU.FTZ.AND P0, PT, R8.reuse, R7, PT ;\n /*0440*/ MOV R7, 0x3 ;\n /*0450*/ LOP3.LUT R8, R8, 0x7fffff, RZ, 0xc0, !PT ;\n /*0460*/ SHF.L.U32 R10, R7, R4, RZ ;\n /*0470*/ LOP3.LUT R7, R8, 0x800000, RZ, 0xfc, !PT ;\n /*0480*/ SEL R6, RZ, 0xffffffff, !P0 ;\n /*0490*/ LOP3.LUT R5, R10, R7, RZ, 0xc0, !PT ;\n /*04a0*/ SHF.R.U32.HI R9, RZ, R2, R7 ;\n /*04b0*/ IMAD.MOV R6, RZ, RZ, -R6 ;\n /*04c0*/ SHF.R.U32.HI R5, RZ, R4, R5 ;\n /*04d0*/ LOP3.LUT P1, RZ, R6, R4, R7, 0xf8, !PT ;\n /*04e0*/ LOP3.LUT P0, RZ, R5.reuse, 0x1, RZ, 0xc0, !PT ;\n /*04f0*/ LOP3.LUT P2, RZ, R5, 0x2, RZ, 0xc0, !PT ;\n /*0500*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ;\n /*0510*/ LOP3.LUT P1, RZ, R0, 0x7fffff, RZ, 0xc0, !PT ;\n /*0520*/ SEL R2, RZ, 0x1, !P0 ;\n /*0530*/ IMAD.MOV R2, RZ, RZ, -R2 ;\n /*0540*/ ISETP.GE.AND P0, PT, R2, RZ, PT ;\n /*0550*/ @!P0 IADD3 R9, R9, 0x1, RZ ;\n /*0560*/ @!P1 SHF.L.U32 R9, R9, 0x1, RZ ;\n /*0570*/ LOP3.LUT R4, R9, 0x80000000, R0, 0xf8, !PT ;\n /*0580*/ BRA `(.L_x_18) ;\n.L_x_19:\n /*0590*/ MUFU.RCP R4, R0 ;\n.L_x_18:\n /*05a0*/ BSYNC B2 ;\n.L_x_16:\n /*05b0*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ;\n /*05c0*/ MOV R5, 0x0 ;\n /*05d0*/ IMAD.MOV.U32 R4, RZ, RZ, R11 ;\n /*05e0*/ RET.REL.NODEC R4 `(_Z13sigmoidKernelIfEvPT_S1_i) ;\n.L_x_20:\n /*05f0*/ BRA `(.L_x_20);\n /*0600*/ NOP;\n /*0610*/ NOP;\n /*0620*/ NOP;\n /*0630*/ NOP;\n /*0640*/ NOP;\n /*0650*/ NOP;\n /*0660*/ NOP;\n /*0670*/ NOP;\n.L_x_22:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.weak\t__cxa_pure_virtual ; -- Begin function __cxa_pure_virtual\n\t.p2align\t2\n\t.type\t__cxa_pure_virtual,@function\n__cxa_pure_virtual: ; @__cxa_pure_virtual\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB0_1: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB0_1\n.Lfunc_end0:\n\t.size\t__cxa_pure_virtual, .Lfunc_end0-__cxa_pure_virtual\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 56\n; NumSgprs: 1\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.weak\t__cxa_deleted_virtual ; -- Begin function __cxa_deleted_virtual\n\t.p2align\t2\n\t.type\t__cxa_deleted_virtual,@function\n__cxa_deleted_virtual: ; @__cxa_deleted_virtual\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB1_1: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB1_1\n.Lfunc_end1:\n\t.size\t__cxa_deleted_virtual, .Lfunc_end1-__cxa_deleted_virtual\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 56\n; NumSgprs: 1\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hsa_signal_add\n\t.type\t__ockl_hsa_signal_add,@function\n__ockl_hsa_signal_add: ; @__ockl_hsa_signal_add\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v6, s32 offset:48 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v4, s32 offset:36 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v3, s32 offset:32 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v2\n\tscratch_load_b32 v2, off, s32 offset:32 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v1, s32 offset:28 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v1, v0\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[3:4], s32 offset:20 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v3, v1\n\tscratch_store_b64 off, v[3:4], s32 offset:12 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v0, v1\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v1, v2\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v0, s1, v0, s1\n\tv_add_co_ci_u32_e64 v2, s0, v1, s0, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s32 offset:4 ; 8-byte Folded Spill\n; %bb.1:\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 3\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, 0\n ; implicit-def: $vgpr6 : SGPR spill to VGPR lane\n\tv_writelane_b32 v6, s1, 0\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 1\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_3\n; %bb.2:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 4\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s1, 2\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 3\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_17\n\ts_branch .LBB2_4\n.LBB2_3:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 1\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s2, v6, 0\n\tv_writelane_b32 v6, s2, 4\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s2, 5\n\tv_writelane_b32 v6, s1, 6\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 7\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_13\n\ts_branch .LBB2_6\n.LBB2_4:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 5\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, -1\n\tv_writelane_b32 v6, s0, 8\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 9\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_15\n\ts_branch .LBB2_18\n.LBB2_5:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 10\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_readlane_b32 s0, v6, 11\n\ts_and_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 0\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_3\n.LBB2_6:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 12\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_7\n\ts_branch .LBB2_14\n.LBB2_7:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 12\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s2, v6, 4\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s2, 13\n\tv_writelane_b32 v6, s1, 14\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 15\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_9\n; %bb.8:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 4\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_lt_i32_e64 s2, v0, s0\n\ts_mov_b32 s0, -1\n\ts_mov_b32 s0, exec_lo\n\ts_and_not1_b32 s1, s1, exec_lo\n\ts_and_b32 s2, s2, exec_lo\n\ts_or_b32 s1, s1, s2\n\tv_writelane_b32 v6, s1, 13\n\tv_writelane_b32 v6, s0, 14\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n.LBB2_9:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s3, v6, 15\n\ts_or_b32 exec_lo, exec_lo, s3\n\tv_readlane_b32 s1, v6, 4\n\tv_readlane_b32 s2, v6, 13\n\tv_readlane_b32 s0, v6, 14\n\ts_and_b32 s0, s0, exec_lo\n\ts_and_not1_b32 s1, s1, exec_lo\n\ts_and_b32 s2, s2, exec_lo\n\ts_or_b32 s1, s1, s2\n\tv_writelane_b32 v6, s1, 5\n\tv_writelane_b32 v6, s0, 6\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_13\n.LBB2_10:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 16\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 17\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n.LBB2_11:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 18\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v6, 17\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 19\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_19\n; %bb.12:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_branch .LBB2_19\n.LBB2_13:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v6, 7\n\ts_or_b32 exec_lo, exec_lo, s2\n\tv_readlane_b32 s0, v6, 5\n\tv_readlane_b32 s1, v6, 6\n\tv_writelane_b32 v6, s1, 16\n\tv_writelane_b32 v6, s1, 17\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 18\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_11\n\ts_branch .LBB2_10\n.LBB2_14:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_branch .LBB2_7\n.LBB2_15:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 9\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_readlane_b32 s0, v6, 8\n\ts_and_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 2\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_17\n.LBB2_16:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_branch .LBB2_5\n.LBB2_17:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 3\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v6, 2\n\tv_writelane_b32 v6, s1, 11\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 10\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_5\n\ts_branch .LBB2_16\n.LBB2_18:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b32 s0, 0\n\ts_xor_b32 s0, exec_lo, -1\n\tv_writelane_b32 v6, s0, 8\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_15\n.LBB2_19:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 19\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:12 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[0:1], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:40 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_ne_u64_e64 s1, v[0:1], s[0:1]\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 20\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_21\n; %bb.20:\n\tscratch_load_b64 v[1:2], off, s32 offset:40 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s32 offset:12 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b32 v0, v[3:4], off offset:24\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v5, 0\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\tv_mov_b32_e32 v4, v5\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[1:2], v[3:4], off\n\tv_readfirstlane_b32 s0, v0\n\ts_mov_b32 s1, 0xff\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB2_21:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 20\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v6, off, s32 offset:48 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end2:\n\t.size\t__ockl_hsa_signal_add, .Lfunc_end2-__ockl_hsa_signal_add\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 1952\n; NumSgprs: 33\n; NumVgprs: 7\n; ScratchSize: 56\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hostcall_internal\n\t.type\t__ockl_hostcall_internal,@function\n__ockl_hostcall_internal: ; @__ockl_hostcall_internal\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s18, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v24, s33 offset:308 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v25, s33 offset:312 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v26, s33 offset:316 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0x150\n\tv_writelane_b32 v24, s30, 0\n\tv_writelane_b32 v24, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:132 ; 4-byte Folded Spill\n ; implicit-def: $vgpr26 : SGPR spill to VGPR lane\n\tv_writelane_b32 v26, s6, 0\n\tv_writelane_b32 v26, s7, 1\n\tscratch_store_b32 off, v18, s33 offset:128 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v16\n\tscratch_load_b32 v16, off, s33 offset:128 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:124 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v14\n\tscratch_load_b32 v14, off, s33 offset:124 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:120 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v12\n\tscratch_load_b32 v12, off, s33 offset:120 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:116 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v10\n\tscratch_load_b32 v10, off, s33 offset:116 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:112 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v8\n\tscratch_load_b32 v8, off, s33 offset:112 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:108 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v6\n\tscratch_load_b32 v6, off, s33 offset:108 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:104 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v4\n\tscratch_load_b32 v4, off, s33 offset:104 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:100 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v2\n\tscratch_load_b32 v2, off, s33 offset:100 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:96 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v1, s33 offset:92 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v1, v0\n\tscratch_load_b32 v0, off, s33 offset:92 ; 4-byte Folded Reload\n\tv_writelane_b32 v26, s15, 2\n\tv_writelane_b32 v26, s14, 3\n\tv_writelane_b32 v26, s13, 4\n\tv_writelane_b32 v26, s12, 5\n\tv_writelane_b32 v26, s10, 6\n\tv_writelane_b32 v26, s11, 7\n\tv_writelane_b32 v26, s8, 8\n\tv_writelane_b32 v26, s9, 9\n\tv_writelane_b32 v26, s4, 10\n\tv_writelane_b32 v26, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\ts_waitcnt vmcnt(8)\n\tv_mov_b32_e32 v18, v16\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr15 killed $vgpr15 def $vgpr15_vgpr16 killed $exec\n\ts_waitcnt vmcnt(7)\n\tv_mov_b32_e32 v16, v14\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec\n\ts_waitcnt vmcnt(6)\n\tv_mov_b32_e32 v14, v12\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\ts_waitcnt vmcnt(5)\n\tv_mov_b32_e32 v12, v10\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\ts_waitcnt vmcnt(4)\n\tv_mov_b32_e32 v10, v8\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\ts_waitcnt vmcnt(3)\n\tv_mov_b32_e32 v8, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v6, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[17:18], s33 offset:84 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[15:16], s33 offset:76 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[13:14], s33 offset:68 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[11:12], s33 offset:60 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[9:10], s33 offset:52 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[7:8], s33 offset:44 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[5:6], s33 offset:36 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[3:4], s33 offset:28 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s0, -1\n\tv_mbcnt_lo_u32_b32 v0, s0, s1\n\tv_mbcnt_hi_u32_b32 v0, s0, v0\n\t;;#ASMSTART\n\t;;#ASMEND\n\tv_mov_b32_e32 v3, v0\n\tscratch_store_b32 off, v3, s33 offset:24 ; 4-byte Folded Spill\n\tv_readfirstlane_b32 s0, v0\n\tscratch_store_b64 off, v[1:2], s33 offset:16 ; 8-byte Folded Spill\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, s1\n\tv_writelane_b32 v26, s0, 12\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v0, 0\n\tv_mov_b32_e32 v1, 0\n\tscratch_store_b64 off, v[0:1], s33 offset:8 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 13\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_6\n; %bb.1:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_mov_b64 s[2:3], 24\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:160 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b64 s[2:3], 40\n\tv_mov_b32_e32 v4, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v5, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v4, s1, v4, s1\n\tv_add_co_ci_u32_e64 v6, s0, v5, s0, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tscratch_store_b64 off, v[4:5], s33 offset:152 ; 8-byte Folded Spill\n\tglobal_load_b64 v[5:6], v[0:1], off\n\tglobal_load_b64 v[10:11], v[0:1], off offset:40\n\tv_mov_b32_e32 v8, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v11\n\tv_and_b32_e64 v4, v4, v8\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v7, v10\n\tv_and_b32_e64 v12, v7, v9\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_mov_b32_e32 v4, v12\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[10:11], s0, v4, s1, 0\n\tv_mov_b32_e32 v14, v11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec\n\tv_mov_b32_e32 v15, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[12:13], s0, v[12:13]\n\tv_mov_b32_e32 v4, v12\n\tv_mad_u64_u32 v[12:13], s1, v4, s1, v[14:15]\n ; kill: def $vgpr12 killed $vgpr12 killed $vgpr12_vgpr13 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s1\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_lshlrev_b64 v[13:14], s0, v[12:13]\n\tv_mov_b32_e32 v7, v14\n\tv_mov_b32_e32 v11, v10\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\tv_mov_b32_e32 v4, v12\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v10, v13\n\tv_mov_b32_e32 v7, v11\n\tv_or_b32_e64 v10, v7, v10\n ; kill: def $vgpr10 killed $vgpr10 def $vgpr10_vgpr11 killed $exec\n\tv_mov_b32_e32 v11, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v11\n\tv_add_co_u32 v4, s0, v4, v7\n\tv_add_co_ci_u32_e64 v6, s0, v5, v6, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tglobal_load_b64 v[4:5], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v10, v5\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s0, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:144 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:136 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 15\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_5\n.LBB3_2: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 14\n\tscratch_load_b64 v[2:3], off, s33 offset:144 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:160 ; 8-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:152 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[5:6], v[4:5], off\n\tglobal_load_b64 v[10:11], v[7:8], off\n\tv_mov_b32_e32 v8, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v11\n\tv_and_b32_e64 v4, v4, v8\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v7, v10\n\tv_and_b32_e64 v12, v7, v9\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_mov_b32_e32 v4, v12\n\ts_mov_b32 s2, 24\n\tv_mad_u64_u32 v[10:11], s0, v4, s2, 0\n\tv_mov_b32_e32 v14, v11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec\n\tv_mov_b32_e32 v15, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[12:13], s0, v[12:13]\n\tv_mov_b32_e32 v4, v12\n\tv_mad_u64_u32 v[12:13], s2, v4, s2, v[14:15]\n ; kill: def $vgpr12 killed $vgpr12 killed $vgpr12_vgpr13 killed $exec\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s2\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_lshlrev_b64 v[13:14], s0, v[12:13]\n\tv_mov_b32_e32 v7, v14\n\tv_mov_b32_e32 v11, v10\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\tv_mov_b32_e32 v4, v12\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v10, v13\n\tv_mov_b32_e32 v7, v11\n\tv_or_b32_e64 v10, v7, v10\n ; kill: def $vgpr10 killed $vgpr10 def $vgpr10_vgpr11 killed $exec\n\tv_mov_b32_e32 v11, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v11\n\tv_add_co_u32 v4, s0, v4, v7\n\tv_add_co_ci_u32_e64 v6, s0, v5, v6, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tglobal_load_b64 v[4:5], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v10, v5\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e64 s0, v[0:1], v[2:3]\n\ts_or_b32 s0, s0, s1\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:144 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:168 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 16\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_2\n; %bb.3:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 16\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.4:\n\tscratch_load_b64 v[0:1], off, s33 offset:168 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:136 ; 8-byte Folded Spill\n.LBB3_5:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:136 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:8 ; 8-byte Folded Spill\n.LBB3_6:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 13\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:8 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[4:5], s0, v[4:5]\n\tv_mov_b32_e32 v2, v4\n\tv_readfirstlane_b32 s4, v3\n\tv_readfirstlane_b32 s2, v2\n ; implicit-def: $sgpr5\n ; implicit-def: $sgpr3\n ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3\n\ts_mov_b32 s3, s5\n\ts_lshl_b64 s[2:3], s[2:3], s0\n\ts_mov_b32 s0, 0\n ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5\n\ts_mov_b32 s5, s0\n\ts_or_b64 s[2:3], s[2:3], s[4:5]\n\tv_writelane_b32 v26, s2, 17\n\tv_writelane_b32 v26, s3, 18\n\tglobal_load_b64 v[2:3], v[0:1], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:200 ; 8-byte Folded Spill\n\ts_mov_b64 s[6:7], 40\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s7\n\tv_add_co_u32 v2, s4, v2, s4\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s4\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tglobal_load_b64 v[3:4], v[0:1], off offset:40\n\ts_mov_b32 s0, s3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v4\n\tv_and_b32_e64 v2, s0, v2\n\ts_mov_b32 s0, s2\n ; kill: def $vgpr3 killed $vgpr3 killed $vgpr3_vgpr4 killed $exec\n\tv_and_b32_e64 v3, s0, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v5, v3\n\tscratch_store_b64 off, v[5:6], s33 offset:184 ; 8-byte Folded Spill\n\tglobal_load_b64 v[1:2], v[0:1], off offset:8\n\ts_mov_b32 s0, 12\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s0, v0, v3\n\tv_add_co_ci_u32_e64 v2, s0, v1, v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:176 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], exec\n\tv_writelane_b32 v26, s2, 19\n\tv_writelane_b32 v26, s3, 20\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 21\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_8\n; %bb.7:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 19\n\tv_readlane_b32 s1, v26, 20\n\tscratch_load_b32 v2, off, s33 offset:96 ; 4-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v5, v0\n\ts_mov_b32 s3, 24\n\tv_mad_u64_u32 v[3:4], s2, v5, s3, 0\n\tv_mov_b32_e32 v9, v4\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v5, s2\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v5\n\ts_mov_b32 s2, 32\n\tv_lshrrev_b64 v[0:1], s2, v[0:1]\n\tv_mov_b32_e32 v5, v0\n\tv_mad_u64_u32 v[0:1], s3, v5, s3, v[9:10]\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v5, s3\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v5\n\tv_lshlrev_b64 v[9:10], s2, v[0:1]\n\tv_mov_b32_e32 v1, v10\n\tv_mov_b32_e32 v4, v3\n\ts_mov_b32 s2, 0\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v0, v5\n\tv_or_b32_e64 v0, v0, v1\n\tv_mov_b32_e32 v3, v9\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v5, v1, v3\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v0\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v3, v6\n\tv_add_co_u32 v0, s2, v0, v4\n\tv_add_co_ci_u32_e64 v3, s2, v1, v3, s2\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tglobal_store_b32 v[0:1], v2, off offset:16\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tglobal_store_b64 v[0:1], v[2:3], off offset:8\n\tv_mov_b32_e32 v2, 1\n\tglobal_store_b32 v[0:1], v2, off offset:20\n.LBB3_8:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[2:3], off, s33 offset:84 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:76 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:68 ; 8-byte Folded Reload\n\tscratch_load_b64 v[8:9], off, s33 offset:60 ; 8-byte Folded Reload\n\tscratch_load_b64 v[10:11], off, s33 offset:52 ; 8-byte Folded Reload\n\tscratch_load_b64 v[12:13], off, s33 offset:44 ; 8-byte Folded Reload\n\tscratch_load_b64 v[14:15], off, s33 offset:36 ; 8-byte Folded Reload\n\tscratch_load_b64 v[16:17], off, s33 offset:28 ; 8-byte Folded Reload\n\tscratch_load_b64 v[22:23], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:24 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v18, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v18\n\ts_mov_b32 s0, 6\n\ts_waitcnt vmcnt(0)\n\tv_lshlrev_b64 v[20:21], s0, v[0:1]\n\tv_mov_b32_e32 v0, v22\n\tv_mov_b32_e32 v19, v20\n\tv_mov_b32_e32 v1, v23\n\tv_mov_b32_e32 v18, v21\n\tv_add_co_u32 v0, s0, v0, v19\n\tv_add_co_ci_u32_e64 v18, s0, v1, v18, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v18\n\tscratch_store_b64 off, v[0:1], s33 offset:216 ; 8-byte Folded Spill\n\tglobal_store_b64 v[0:1], v[16:17], off\n\ts_mov_b64 s[4:5], 8\n\tv_mov_b32_e32 v16, v0\n\ts_mov_b32 s2, s4\n\tv_mov_b32_e32 v17, v1\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v16, s2, v16, s2\n\tv_add_co_ci_u32_e64 v18, s0, v17, s0, s2\n ; kill: def $vgpr16 killed $vgpr16 def $vgpr16_vgpr17 killed $exec\n\tv_mov_b32_e32 v17, v18\n\tscratch_store_b64 off, v[16:17], s33 offset:208 ; 8-byte Folded Spill\n\tglobal_store_b64 v[0:1], v[14:15], off offset:8\n\tglobal_store_b64 v[0:1], v[12:13], off offset:16\n\tglobal_store_b64 v[0:1], v[10:11], off offset:24\n\tglobal_store_b64 v[0:1], v[8:9], off offset:32\n\tglobal_store_b64 v[0:1], v[6:7], off offset:40\n\tglobal_store_b64 v[0:1], v[4:5], off offset:48\n\tglobal_store_b64 v[0:1], v[2:3], off offset:56\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 22\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_13\n; %bb.9:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[5:6], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:192 ; 8-byte Folded Reload\n\ts_mov_b64 s[4:5], 32\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s4\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:240 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:32 glc\n\ts_waitcnt vmcnt(1)\n\tglobal_load_b64 v[7:8], v[7:8], off\n\ts_mov_b32 s0, s3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v8\n\tv_and_b32_e64 v4, v4, s0\n\ts_mov_b32 s1, s2\n ; kill: def $vgpr7 killed $vgpr7 killed $vgpr7_vgpr8 killed $exec\n\tv_and_b32_e64 v7, v7, s1\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v4\n\tv_mov_b32_e32 v4, v7\n\ts_mov_b32 s3, 24\n\tv_mad_u64_u32 v[9:10], s2, v4, s3, 0\n\tv_mov_b32_e32 v11, v10\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v4, s2\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\ts_mov_b32 s2, 32\n\tv_lshrrev_b64 v[7:8], s2, v[7:8]\n\tv_mov_b32_e32 v4, v7\n\tv_mad_u64_u32 v[7:8], s3, v4, s3, v[11:12]\n ; kill: def $vgpr7 killed $vgpr7 killed $vgpr7_vgpr8 killed $exec\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v4, s3\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v4\n\tv_lshlrev_b64 v[7:8], s2, v[7:8]\n\tv_mov_b32_e32 v11, v8\n ; kill: def $vgpr9 killed $vgpr9 killed $vgpr9_vgpr10 killed $exec\n\ts_mov_b32 s2, 0\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v4, v10\n\tv_or_b32_e64 v4, v4, v11\n\tv_mov_b32_e32 v8, v7\n\tv_mov_b32_e32 v7, v9\n\tv_or_b32_e64 v8, v7, v8\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v8\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v9\n\tv_add_co_u32 v4, s2, v4, v7\n\tv_add_co_ci_u32_e64 v6, s2, v5, v6, s2\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tscratch_store_b64 off, v[4:5], s33 offset:232 ; 8-byte Folded Spill\n\tglobal_store_b64 v[4:5], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s1\n\tv_mov_b32_e32 v10, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s2, v[0:1], v[2:3]\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s2, 23\n\tv_writelane_b32 v26, s0, 24\n\tscratch_store_b64 off, v[0:1], s33 offset:224 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 25\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_14\n.LBB3_10: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 24\n\tv_readlane_b32 s1, v26, 23\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[2:3], off, s33 offset:224 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:240 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:232 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_store_b64 v[4:5], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n\ts_mov_b32 s1, s3\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v10, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s1, v[0:1], v[2:3]\n\ts_or_b32 s0, s1, s0\n\tv_writelane_b32 v26, s1, 23\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 24\n\tscratch_store_b64 off, v[0:1], s33 offset:224 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 26\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_10\n; %bb.11:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 26\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.12:\n\ts_branch .LBB3_14\n.LBB3_13:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_branch .LBB3_15\n.LBB3_14:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 25\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s15, v26, 2\n\tv_readlane_b32 s14, v26, 3\n\tv_readlane_b32 s13, v26, 4\n\tv_readlane_b32 s12, v26, 5\n\tv_readlane_b32 s10, v26, 6\n\tv_readlane_b32 s11, v26, 7\n\tv_readlane_b32 s8, v26, 8\n\tv_readlane_b32 s9, v26, 9\n\tv_readlane_b32 s6, v26, 0\n\tv_readlane_b32 s7, v26, 1\n\tv_readlane_b32 s4, v26, 10\n\tv_readlane_b32 s5, v26, 11\n\tscratch_load_b32 v31, off, s33 offset:132 ; 4-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_mov_b32 s0, 32\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[0:1], s0, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v2\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hsa_signal_add@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hsa_signal_add@rel32@hi+12\n\tv_mov_b32_e32 v2, 1\n\tv_mov_b32_e32 v3, 0\n\tv_mov_b32_e32 v4, 3\n\ts_swappc_b64 s[30:31], s[0:1]\n\ts_branch .LBB3_13\n.LBB3_15:\n\tscratch_load_b64 v[6:7], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[3:4], s0, v2, s1, 0\n\tv_mov_b32_e32 v8, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v2\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[0:1]\n\tv_mov_b32_e32 v2, v0\n\tv_mad_u64_u32 v[0:1], s1, v2, s1, v[8:9]\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_lshlrev_b64 v[1:2], s0, v[0:1]\n\tv_mov_b32_e32 v5, v2\n ; kill: def $vgpr3 killed $vgpr3 killed $vgpr3_vgpr4 killed $exec\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_mov_b32_e32 v0, v4\n\tv_or_b32_e64 v0, v0, v5\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v1, v3\n\tv_or_b32_e64 v4, v1, v2\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v1, v6\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v1, s0, v1, v3\n\tv_add_co_ci_u32_e64 v0, s0, v0, v2, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b64 s[2:3], 20\n\tv_mov_b32_e32 v0, v1\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v1, v2\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v0, s1, v0, s1\n\tv_add_co_ci_u32_e64 v2, s0, v1, s0, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:248 ; 8-byte Folded Spill\n.LBB3_16: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 12\n\ts_mov_b32 s0, 1\n\tv_mov_b32_e32 v0, 1\n\tscratch_store_b32 off, v0, s33 offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 27\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_18\n; %bb.17: ; in Loop: Header=BB3_16 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:248 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b32 v0, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b32 s0, 1\n\tv_and_b32_e64 v0, v0, s0\n\tscratch_store_b32 off, v0, s33 offset:256 ; 4-byte Folded Spill\n.LBB3_18: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 27\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s33 offset:256 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s1, v0\n\ts_mov_b32 s0, -1\n\ts_mov_b32 s2, 0\n\ts_cmp_eq_u32 s1, s2\n\tv_writelane_b32 v26, s0, 28\n\ts_mov_b32 s17, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_cbranch_scc1 .LBB3_20\n; %bb.19: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_sleep 1\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v26, s0, 28\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n.LBB3_20: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 28\n\tv_cndmask_b32_e64 v0, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v0, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n\ts_cbranch_vccnz .LBB3_16\n; %bb.21:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[0:1], off, s33 offset:208 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:216 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[2:3], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:268 ; 8-byte Folded Spill\n\tglobal_load_b64 v[0:1], v[0:1], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:260 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 29\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_27\n; %bb.22:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:192 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[11:12], v[2:3], off\n\ts_mov_b64 s[4:5], 1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v11\n\ts_mov_b32 s1, s4\n\tv_mov_b32_e32 v3, v12\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v4, v2\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v5, v3\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v4, s1, v4, s1\n\tv_add_co_ci_u32_e64 v6, s0, v5, s0, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_eq_u64_e64 s0, v[4:5], s[0:1]\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v6, v5\n\tv_cndmask_b32_e64 v10, v6, v7, s0\n\tv_mov_b32_e32 v3, v2\n\tv_mov_b32_e32 v2, v4\n\tv_cndmask_b32_e64 v4, v2, v3, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v8, v4\n\tv_mov_b32_e32 v9, v10\n\tv_mov_b32_e32 v2, v8\n\tv_mov_b32_e32 v3, v9\n\tscratch_store_b64 off, v[2:3], s33 offset:300 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], 24\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v5, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v5\n\tscratch_store_b64 off, v[2:3], s33 offset:292 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:24 glc\n\tglobal_load_b64 v[6:7], v[0:1], off\n\tv_mov_b32_e32 v5, v9\n\tv_mov_b32_e32 v13, v12\n\tv_and_b32_e64 v5, v5, v13\n ; kill: def $vgpr8 killed $vgpr8 killed $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v11\n\tv_and_b32_e64 v8, v8, v9\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v5\n\tv_mov_b32_e32 v5, v8\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[11:12], s0, v5, s1, 0\n\tv_mov_b32_e32 v13, v12\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v5, s0\n ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec\n\tv_mov_b32_e32 v14, v5\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[8:9], s0, v[8:9]\n\tv_mov_b32_e32 v5, v8\n\tv_mad_u64_u32 v[8:9], s1, v5, s1, v[13:14]\n ; kill: def $vgpr8 killed $vgpr8 killed $vgpr8_vgpr9 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v5, s1\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v5\n\tv_lshlrev_b64 v[8:9], s0, v[8:9]\n\tv_mov_b32_e32 v13, v9\n ; kill: def $vgpr11 killed $vgpr11 killed $vgpr11_vgpr12 killed $exec\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v5, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v5\n\tv_mov_b32_e32 v5, v12\n\tv_or_b32_e64 v5, v5, v13\n\tv_mov_b32_e32 v9, v8\n\tv_mov_b32_e32 v8, v11\n\tv_or_b32_e64 v11, v8, v9\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v5\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v8, v11\n\tv_mov_b32_e32 v6, v7\n\tv_mov_b32_e32 v7, v12\n\tv_add_co_u32 v5, s0, v5, v8\n\tv_add_co_ci_u32_e64 v7, s0, v6, v7, s0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v7\n\tscratch_store_b64 off, v[5:6], s33 offset:284 ; 8-byte Folded Spill\n\tglobal_store_b64 v[5:6], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s2, v[0:1], v[2:3]\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s2, 30\n\tv_writelane_b32 v26, s0, 31\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\tscratch_store_b64 off, v[0:1], s33 offset:276 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n ; implicit-def: $vgpr26 : SGPR spill to VGPR lane\n\tv_writelane_b32 v26, s0, 0\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_26\n.LBB3_23: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v25, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v25, 31\n\tv_readlane_b32 s1, v25, 30\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\tscratch_load_b64 v[2:3], off, s33 offset:276 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:292 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:300 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:284 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_store_b64 v[6:7], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v10, v5\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s1, v[0:1], v[2:3]\n\ts_or_b32 s0, s1, s0\n\tv_writelane_b32 v25, s1, 30\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v25, s1, 31\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v25, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\tscratch_store_b64 off, v[0:1], s33 offset:276 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_23\n; %bb.24:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.25:\n.LBB3_26:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 0\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB3_27:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[3:4], off, s33 offset:260 ; 8-byte Folded Reload\n\tscratch_load_b64 v[1:2], off, s33 offset:268 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v3\n\tv_mov_b32_e32 v3, v4\n\tv_readlane_b32 s30, v24, 0\n\tv_readlane_b32 s31, v24, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v24, off, s33 offset:308 ; 4-byte Folded Reload\n\tscratch_load_b32 v25, off, s33 offset:312 ; 4-byte Folded Reload\n\tscratch_load_b32 v26, off, s33 offset:316 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xfffffeb0\n\ts_mov_b32 s33, s18\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end3:\n\t.size\t__ockl_hostcall_internal, .Lfunc_end3-__ockl_hostcall_internal\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 5344\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 392\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hostcall_preview\n\t.type\t__ockl_hostcall_preview,@function\n__ockl_hostcall_preview: ; @__ockl_hostcall_preview\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v27, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tv_writelane_b32 v27, s33, 0\n\tv_writelane_b32 v27, s30, 1\n\tv_writelane_b32 v27, s31, 2\n\tv_mov_b32_e32 v18, v16\n\tv_mov_b32_e32 v17, v15\n\tv_mov_b32_e32 v16, v14\n\tv_mov_b32_e32 v15, v13\n\tv_mov_b32_e32 v14, v12\n\tv_mov_b32_e32 v13, v11\n\tv_mov_b32_e32 v12, v10\n\tv_mov_b32_e32 v11, v9\n\tv_mov_b32_e32 v10, v8\n\tv_mov_b32_e32 v9, v7\n\tv_mov_b32_e32 v8, v6\n\tv_mov_b32_e32 v7, v5\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v5, v3\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s0, s[0:1], 0x0\n\ts_mov_b32 s1, 0x1f4\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_i32 s0, s1\n\ts_mov_b32 s1, 0x50\n\ts_mov_b32 s0, 24\n\ts_cselect_b32 s0, s0, s1\n\ts_load_b64 s[0:1], s[8:9], s0 offset:0x0\n\ts_waitcnt lgkmcnt(0)\n\ts_mov_b32 s3, s0\n\ts_mov_b32 s2, 32\n\ts_lshr_b64 s[0:1], s[0:1], s2\n\ts_mov_b32 s2, s0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_internal@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_internal@rel32@hi+12\n\tv_mov_b32_e32 v0, s3\n\tv_mov_b32_e32 v1, s2\n\tv_readlane_b32 s30, v27, 1\n\tv_readlane_b32 s31, v27, 2\n\tv_readlane_b32 s33, v27, 0\n\ts_xor_saveexec_b32 s2, -1\n\tscratch_load_b32 v27, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s2\n\ts_setpc_b64 s[0:1]\n.Lfunc_end4:\n\t.size\t__ockl_hostcall_preview, .Lfunc_end4-__ockl_hostcall_preview\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 272\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 400\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_stderr_begin\n\t.type\t__ockl_fprintf_stderr_begin,@function\n__ockl_fprintf_stderr_begin: ; @__ockl_fprintf_stderr_begin\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s16, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v28, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 16\n\tv_writelane_b32 v28, s30, 0\n\tv_writelane_b32 v28, s31, 1\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\tv_mov_b32_e32 v1, 33\n\tv_mov_b32_e32 v3, 1\n\tv_mov_b32_e32 v16, 0\n\tv_mov_b32_e32 v2, v16\n\tv_mov_b32_e32 v4, v16\n\tv_mov_b32_e32 v5, v16\n\tv_mov_b32_e32 v6, v16\n\tv_mov_b32_e32 v7, v16\n\tv_mov_b32_e32 v8, v16\n\tv_mov_b32_e32 v9, v16\n\tv_mov_b32_e32 v10, v16\n\tv_mov_b32_e32 v11, v16\n\tv_mov_b32_e32 v12, v16\n\tv_mov_b32_e32 v13, v16\n\tv_mov_b32_e32 v14, v16\n\tv_mov_b32_e32 v15, v16\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_store_b32 off, v1, s33 ; 4-byte Folded Spill\n ; kill: def $vgpr1 killed $vgpr3 killed $exec\n\tscratch_load_b32 v3, off, s33 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v3\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v28, 0\n\tv_readlane_b32 s31, v28, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v28, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, -16\n\ts_mov_b32 s33, s16\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end5:\n\t.size\t__ockl_fprintf_stderr_begin, .Lfunc_end5-__ockl_fprintf_stderr_begin\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 228\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 416\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_append_string_n\n\t.type\t__ockl_fprintf_append_string_n,@function\n__ockl_fprintf_append_string_n: ; @__ockl_fprintf_append_string_n\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s20, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v32, s33 offset:704 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v33, s33 offset:708 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v34, s33 offset:712 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0x2d0\n\tv_writelane_b32 v32, s30, 0\n\tv_writelane_b32 v32, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:68 ; 4-byte Folded Spill\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\tv_writelane_b32 v34, s6, 0\n\tv_writelane_b32 v34, s7, 1\n\tscratch_store_b32 off, v6, s33 offset:60 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v5, s33 offset:56 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v4, s33 offset:64 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v6, v3\n\tscratch_load_b32 v3, off, s33 offset:64 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v4, v2\n\tscratch_load_b32 v2, off, s33 offset:60 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v4, s33 offset:52 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v7, v1\n\tscratch_load_b32 v1, off, s33 offset:56 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v5, v0\n\tscratch_load_b32 v0, off, s33 offset:52 ; 4-byte Folded Reload\n\tv_writelane_b32 v34, s15, 2\n\tv_writelane_b32 v34, s14, 3\n\tv_writelane_b32 v34, s13, 4\n\tv_writelane_b32 v34, s12, 5\n\tv_writelane_b32 v34, s10, 6\n\tv_writelane_b32 v34, s11, 7\n\tv_writelane_b32 v34, s8, 8\n\tv_writelane_b32 v34, s9, 9\n\tv_writelane_b32 v34, s4, 10\n\tv_writelane_b32 v34, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v1\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v7\n\tscratch_store_b64 off, v[3:4], s33 offset:44 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v3, v0\n\tscratch_store_b64 off, v[3:4], s33 offset:36 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s0, 0\n\tv_cmp_eq_u32_e64 s0, v2, s0\n\tv_mov_b32_e32 v4, v6\n\ts_mov_b64 s[2:3], 2\n\ts_mov_b32 s1, s3\n\tv_or_b32_e64 v2, v4, s1\n\tv_mov_b32_e32 v3, v5\n\ts_mov_b32 s1, s2\n\tv_or_b32_e64 v5, v3, s1\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v2\n\tv_mov_b32_e32 v2, v6\n\tv_cndmask_b32_e64 v4, v2, v4, s0\n\tv_mov_b32_e32 v2, v5\n\tv_cndmask_b32_e64 v2, v2, v3, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:28 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_ne_u64_e64 s0, v[0:1], s[0:1]\n ; implicit-def: $sgpr4_sgpr5_sgpr6_sgpr7\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tv_mov_b32_e32 v2, s6\n\tv_mov_b32_e32 v3, s7\n\tscratch_store_b128 off, v[0:3], s33 offset:12 ; 16-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 12\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_3\n\ts_branch .LBB6_2\n.LBB6_1:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v34, 2\n\tv_readlane_b32 s14, v34, 3\n\tv_readlane_b32 s13, v34, 4\n\tv_readlane_b32 s12, v34, 5\n\tv_readlane_b32 s10, v34, 6\n\tv_readlane_b32 s11, v34, 7\n\tv_readlane_b32 s8, v34, 8\n\tv_readlane_b32 s9, v34, 9\n\tv_readlane_b32 s6, v34, 0\n\tv_readlane_b32 s7, v34, 1\n\tv_readlane_b32 s4, v34, 10\n\tv_readlane_b32 s5, v34, 11\n\tscratch_load_b32 v31, off, s33 offset:68 ; 4-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:28 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v3\n\tv_and_b32_e64 v4, v0, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v0, v2\n\tv_and_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_mov_b32_e32 v4, v1\n\ts_mov_b64 s[0:1], 32\n\ts_mov_b32 s2, s1\n\tv_or_b32_e64 v4, v4, s2\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_or_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_mov_b32_e32 v1, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[2:3], s0, v[2:3]\n ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\tv_mov_b32_e32 v16, 0\n\tscratch_store_b32 off, v16, s33 offset:88 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v16\n\tv_mov_b32_e32 v4, v16\n\tv_mov_b32_e32 v5, v16\n\tv_mov_b32_e32 v6, v16\n\tv_mov_b32_e32 v7, v16\n\tv_mov_b32_e32 v8, v16\n\tv_mov_b32_e32 v9, v16\n\tv_mov_b32_e32 v10, v16\n\tv_mov_b32_e32 v11, v16\n\tv_mov_b32_e32 v12, v16\n\tv_mov_b32_e32 v13, v16\n\tv_mov_b32_e32 v14, v16\n\tv_mov_b32_e32 v15, v16\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_mov_b32_e32 v6, v1\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v4, v3\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v6\n\tv_mov_b32_e32 v2, v5\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b128 off, v[0:3], s33 offset:72 ; 16-byte Folded Spill\n\ts_branch .LBB6_63\n.LBB6_2:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b64 v[4:5], off, s33 offset:36 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:44 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:28 ; 8-byte Folded Reload\n\ts_mov_b64 s[0:1], 2\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v1, v3\n\tv_and_b32_e64 v8, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v0, v2\n\tv_and_b32_e64 v2, v0, s0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v8\n\tscratch_store_b64 off, v[2:3], s33 offset:124 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], -3\n\ts_mov_b32 s2, s1\n\tv_and_b32_e64 v2, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_and_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v10, v1\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\ts_mov_b64 s[2:3], 0\n\ts_mov_b32 s0, s3\n\ts_mov_b32 s1, s2\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v9, s1\n\tv_mov_b32_e32 v8, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v10\n\tv_mov_b32_e32 v2, v9\n\tv_mov_b32_e32 v3, v8\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v34, s0, 13\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[6:7], s33 offset:116 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[4:5], s33 offset:108 ; 8-byte Folded Spill\n\tscratch_store_b128 off, v[0:3], s33 offset:92 ; 16-byte Folded Spill\n\ts_branch .LBB6_4\n.LBB6_3:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 12\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b128 v[0:3], off, s33 offset:12 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:72 ; 16-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 14\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_63\n\ts_branch .LBB6_1\n.LBB6_4: ; =>This Loop Header: Depth=1\n ; Child Loop BB6_8 Depth 2\n ; Child Loop BB6_16 Depth 2\n ; Child Loop BB6_24 Depth 2\n ; Child Loop BB6_32 Depth 2\n ; Child Loop BB6_40 Depth 2\n ; Child Loop BB6_48 Depth 2\n ; Child Loop BB6_56 Depth 2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 13\n\tscratch_load_b64 v[6:7], off, s33 offset:124 ; 8-byte Folded Reload\n\tscratch_load_b128 v[8:11], off, s33 offset:92 ; 16-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:116 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:108 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:176 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[3:4], s33 offset:168 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 15\n\ts_mov_b64 s[2:3], 56\n\tv_cmp_gt_u64_e64 s0, v[3:4], s[2:3]\n\tv_mov_b32_e32 v1, v9\n\tv_mov_b32_e32 v2, v8\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v8, v2\n\tv_mov_b32_e32 v9, v1\n\tv_mov_b32_e32 v0, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or_b32_e64 v0, v0, v5\n\tv_mov_b32_e32 v5, v8\n\tv_or_b32_e64 v5, v5, v6\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v0\n\tv_mov_b32_e32 v0, v6\n\tv_cndmask_b32_e64 v0, v0, v1, s0\n\tv_mov_b32_e32 v1, v5\n\tv_cndmask_b32_e64 v1, v1, v2, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_cmp_lt_u64_e64 s1, v[3:4], s[2:3]\n\tv_mov_b32_e32 v0, v4\n\ts_mov_b32 s0, s3\n\tv_cndmask_b32_e64 v5, s0, v0, s1\n\tv_mov_b32_e32 v0, v3\n\ts_mov_b32 s0, s2\n\tv_cndmask_b32_e64 v0, s0, v0, s1\n\tscratch_store_b32 off, v0, s33 offset:164 ; 4-byte Folded Spill\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v3, v0\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:156 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:148 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:140 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:132 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 16\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_6\n; %bb.5: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:164 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 17\n\tv_writelane_b32 v34, s0, 18\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:184 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_11\n\ts_branch .LBB6_8\n.LBB6_6: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 16\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 20\n\tscratch_load_b64 v[0:1], off, s33 offset:140 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:132 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:212 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:208 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:200 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 21\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_12\n; %bb.7: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:212 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:208 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:200 ; 8-byte Folded Spill\n\ts_branch .LBB6_12\n.LBB6_8: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 18\n\tv_readlane_b32 s2, v34, 17\n\tscratch_load_b64 v[4:5], off, s33 offset:192 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:176 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 17\n\tv_writelane_b32 v34, s1, 18\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:220 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 22\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_8\n; %bb.9: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.10: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:220 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:184 ; 8-byte Folded Spill\n.LBB6_11: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 19\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:140 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 20\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:132 ; 8-byte Folded Spill\n\ts_branch .LBB6_6\n.LBB6_12: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:212 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:208 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:200 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:256 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:252 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:244 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:236 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:228 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 23\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_14\n; %bb.13: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:252 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 24\n\tv_writelane_b32 v34, s0, 25\n\tscratch_store_b64 off, v[2:3], s33 offset:272 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:264 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 26\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_19\n\ts_branch .LBB6_16\n.LBB6_14: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 23\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 27\n\tscratch_load_b64 v[0:1], off, s33 offset:236 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:228 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:292 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:288 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:280 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 28\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_20\n; %bb.15: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:244 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:252 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:292 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:288 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:280 ; 8-byte Folded Spill\n\ts_branch .LBB6_20\n.LBB6_16: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 25\n\tv_readlane_b32 s2, v34, 24\n\tscratch_load_b64 v[4:5], off, s33 offset:272 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:252 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:244 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 24\n\tv_writelane_b32 v34, s1, 25\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:272 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:300 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 29\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_16\n; %bb.17: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.18: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:300 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:264 ; 8-byte Folded Spill\n.LBB6_19: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 26\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:244 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:264 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:236 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 27\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:228 ; 8-byte Folded Spill\n\ts_branch .LBB6_14\n.LBB6_20: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 28\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:292 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:288 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:280 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:336 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:332 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:324 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:316 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:308 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 30\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_22\n; %bb.21: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:332 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v33, s2, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tv_writelane_b32 v34, s0, 0\n\tscratch_store_b64 off, v[2:3], s33 offset:352 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:344 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_27\n\ts_branch .LBB6_24\n.LBB6_22: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v33, 30\n\ts_or_saveexec_b32 s0, s0\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v34, 2\n\tscratch_load_b64 v[0:1], off, s33 offset:316 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:308 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:372 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:368 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:360 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 3\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_28\n; %bb.23: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:324 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:332 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:372 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:368 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:360 ; 8-byte Folded Spill\n\ts_branch .LBB6_28\n.LBB6_24: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 0\n\tv_readlane_b32 s2, v33, 31\n\tscratch_load_b64 v[4:5], off, s33 offset:352 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:332 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:324 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v33, s2, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tv_writelane_b32 v34, s1, 0\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:352 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:380 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 4\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_24\n; %bb.25: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.26: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:380 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:344 ; 8-byte Folded Spill\n.LBB6_27: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:324 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:344 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:316 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:308 ; 8-byte Folded Spill\n\ts_branch .LBB6_22\n.LBB6_28: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 3\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:372 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:368 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:360 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:416 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:412 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:404 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:396 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:388 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 5\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_30\n; %bb.29: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:412 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 6\n\tv_writelane_b32 v34, s0, 7\n\tscratch_store_b64 off, v[2:3], s33 offset:432 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:424 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 8\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_35\n\ts_branch .LBB6_32\n.LBB6_30: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 5\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 9\n\tscratch_load_b64 v[0:1], off, s33 offset:396 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:388 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:452 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:448 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:440 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 10\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_36\n; %bb.31: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:404 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:412 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:452 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:448 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:440 ; 8-byte Folded Spill\n\ts_branch .LBB6_36\n.LBB6_32: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 7\n\tv_readlane_b32 s2, v34, 6\n\tscratch_load_b64 v[4:5], off, s33 offset:432 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:412 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:404 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 6\n\tv_writelane_b32 v34, s1, 7\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:432 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:460 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 11\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_32\n; %bb.33: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 11\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.34: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:460 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:424 ; 8-byte Folded Spill\n.LBB6_35: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 8\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:404 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:424 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:396 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 9\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:388 ; 8-byte Folded Spill\n\ts_branch .LBB6_30\n.LBB6_36: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 10\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:452 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:448 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:440 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:496 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:492 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:484 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:476 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:468 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 12\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_38\n; %bb.37: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:492 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 13\n\tv_writelane_b32 v34, s0, 14\n\tscratch_store_b64 off, v[2:3], s33 offset:512 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:504 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 15\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_43\n\ts_branch .LBB6_40\n.LBB6_38: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 12\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 16\n\tscratch_load_b64 v[0:1], off, s33 offset:476 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:468 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:532 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:528 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:520 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 17\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_44\n; %bb.39: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:484 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:492 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:532 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:528 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:520 ; 8-byte Folded Spill\n\ts_branch .LBB6_44\n.LBB6_40: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 14\n\tv_readlane_b32 s2, v34, 13\n\tscratch_load_b64 v[4:5], off, s33 offset:512 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:492 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:484 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 13\n\tv_writelane_b32 v34, s1, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:512 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:540 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 18\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_40\n; %bb.41: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 18\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.42: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:540 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:504 ; 8-byte Folded Spill\n.LBB6_43: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:484 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:504 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:476 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 16\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:468 ; 8-byte Folded Spill\n\ts_branch .LBB6_38\n.LBB6_44: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 17\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:532 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:528 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:520 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:576 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:572 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:564 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:556 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:548 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_46\n; %bb.45: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:572 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 20\n\tv_writelane_b32 v34, s0, 21\n\tscratch_store_b64 off, v[2:3], s33 offset:592 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:584 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 22\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_51\n\ts_branch .LBB6_48\n.LBB6_46: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 19\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 23\n\tscratch_load_b64 v[0:1], off, s33 offset:556 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:548 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:612 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:608 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:600 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 24\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_52\n; %bb.47: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:564 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:572 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:612 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:608 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:600 ; 8-byte Folded Spill\n\ts_branch .LBB6_52\n.LBB6_48: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 21\n\tv_readlane_b32 s2, v34, 20\n\tscratch_load_b64 v[4:5], off, s33 offset:592 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:572 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:564 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 20\n\tv_writelane_b32 v34, s1, 21\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:592 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:620 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 25\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_48\n; %bb.49: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 25\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.50: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:620 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:584 ; 8-byte Folded Spill\n.LBB6_51: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:564 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:584 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:556 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 23\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:548 ; 8-byte Folded Spill\n\ts_branch .LBB6_46\n.LBB6_52: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 24\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:612 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:608 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:600 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:648 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:644 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:636 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s33 offset:628 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 26\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_54\n; %bb.53: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:644 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 27\n\tv_writelane_b32 v34, s0, 28\n\tscratch_store_b64 off, v[2:3], s33 offset:664 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:656 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 29\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_59\n\ts_branch .LBB6_56\n.LBB6_54: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 26\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:628 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:672 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 30\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_60\n; %bb.55: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[2:3], off, s33 offset:636 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tflat_load_u8 v0, v[2:3]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v4, v[2:3] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v5, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v7, v1\n\tv_mov_b32_e32 v4, v6\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v5\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v4\n\tflat_load_u8 v4, v[2:3] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v8, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v4\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v10, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or3_b32 v4, v4, v5, v10\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v5, v8\n\tv_mov_b32_e32 v1, v6\n\tv_or3_b32 v0, v0, v1, v5\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v4, s1, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[6:7], s2, v[4:5]\n\tflat_load_u8 v4, v[2:3] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v4, s1, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[8:9], s0, v[4:5]\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v10, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or3_b32 v4, v4, v5, v10\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v5, v8\n\tv_mov_b32_e32 v1, v6\n\tv_or3_b32 v0, v0, v1, v5\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:6\n\tv_mov_b32_e32 v6, 0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[4:5], s0, v[4:5]\n\tflat_load_u8 v2, v[2:3] offset:7\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v6\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[6:7], s0, v[2:3]\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v8, v7\n\tv_mov_b32_e32 v3, v5\n\tv_or3_b32 v2, v2, v3, v8\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v3, v6\n\tv_mov_b32_e32 v1, v4\n\tv_or3_b32 v0, v0, v1, v3\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:672 ; 8-byte Folded Spill\n\ts_branch .LBB6_60\n.LBB6_56: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 28\n\tv_readlane_b32 s2, v34, 27\n\tscratch_load_b64 v[4:5], off, s33 offset:664 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:644 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:636 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 27\n\tv_writelane_b32 v34, s1, 28\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:664 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:680 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_56\n; %bb.57: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 31\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.58: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:680 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:656 ; 8-byte Folded Spill\n.LBB6_59: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:656 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:628 ; 8-byte Folded Spill\n\ts_branch .LBB6_54\n.LBB6_60: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v34, 30\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v33, 2\n\tv_readlane_b32 s14, v33, 3\n\tv_readlane_b32 s13, v33, 4\n\tv_readlane_b32 s12, v33, 5\n\tv_readlane_b32 s10, v33, 6\n\tv_readlane_b32 s11, v33, 7\n\tv_readlane_b32 s8, v33, 8\n\tv_readlane_b32 s9, v33, 9\n\tv_readlane_b32 s6, v33, 0\n\tv_readlane_b32 s7, v33, 1\n\tv_readlane_b32 s4, v33, 10\n\tv_readlane_b32 s5, v33, 11\n\tscratch_load_b64 v[0:1], off, s33 offset:156 ; 8-byte Folded Reload\n\tscratch_load_b32 v31, off, s33 offset:68 ; 4-byte Folded Reload\n\tscratch_load_b64 v[19:20], off, s33 offset:648 ; 8-byte Folded Reload\n\tscratch_load_b64 v[21:22], off, s33 offset:576 ; 8-byte Folded Reload\n\tscratch_load_b64 v[23:24], off, s33 offset:496 ; 8-byte Folded Reload\n\tscratch_load_b64 v[25:26], off, s33 offset:416 ; 8-byte Folded Reload\n\tscratch_load_b64 v[27:28], off, s33 offset:336 ; 8-byte Folded Reload\n\tscratch_load_b64 v[29:30], off, s33 offset:256 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:148 ; 8-byte Folded Reload\n\tscratch_load_b64 v[17:18], off, s33 offset:672 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(9)\n\tv_mov_b32_e32 v1, v0\n\ts_mov_b32 s0, 28\n\tv_mov_b32_e32 v0, 2\n\tv_lshl_add_u32 v1, v1, v0, s0\n\ts_mov_b32 s0, 0x1e0\n\tv_and_b32_e64 v5, v1, s0\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v1, 0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v1\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v1, v3\n\tv_and_b32_e64 v1, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v4, v2\n\tv_and_b32_e64 v7, v4, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v4, v6\n\tv_or_b32_e64 v1, v1, v4\n\tv_mov_b32_e32 v4, v7\n ; kill: def $vgpr5 killed $vgpr5 killed $vgpr5_vgpr6 killed $exec\n\tv_or_b32_e64 v4, v4, v5\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v1\n\tv_mov_b32_e32 v1, v4\n\ts_mov_b32 s0, 32\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\tv_writelane_b32 v34, s0, 0\n\tv_lshrrev_b64 v[2:3], s0, v[2:3]\n ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec\n\tv_lshrrev_b64 v[3:4], s0, v[29:30]\n\tv_mov_b32_e32 v4, v3\n\tv_lshrrev_b64 v[5:6], s0, v[27:28]\n\tv_mov_b32_e32 v6, v5\n\tv_lshrrev_b64 v[7:8], s0, v[25:26]\n\tv_mov_b32_e32 v8, v7\n\tv_lshrrev_b64 v[9:10], s0, v[23:24]\n\tv_mov_b32_e32 v10, v9\n\tv_lshrrev_b64 v[11:12], s0, v[21:22]\n\tv_mov_b32_e32 v12, v11\n\tv_lshrrev_b64 v[13:14], s0, v[19:20]\n\tv_mov_b32_e32 v14, v13\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[15:16], s0, v[17:18]\n\tv_mov_b32_e32 v16, v15\n\tv_mov_b32_e32 v3, v29\n\tv_mov_b32_e32 v5, v27\n\tv_mov_b32_e32 v7, v25\n\tv_mov_b32_e32 v9, v23\n\tv_mov_b32_e32 v11, v21\n\tv_mov_b32_e32 v13, v19\n\tv_mov_b32_e32 v15, v17\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b64 v[4:5], off, s33 offset:168 ; 8-byte Folded Reload\n\tscratch_load_b64 v[12:13], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b64 v[10:11], off, s33 offset:156 ; 8-byte Folded Reload\n\tv_readlane_b32 s1, v33, 15\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v7, v2\n\tv_mov_b32_e32 v6, v3\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v2, v7\n\tv_mov_b32_e32 v3, v6\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v6, v4\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v5, v11\n\tv_sub_co_u32 v6, s0, v6, v7\n\tv_sub_co_ci_u32_e64 v4, s0, v4, v5, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v4\n\tv_mov_b32_e32 v4, v12\n\tv_mov_b32_e32 v9, v10\n\tv_mov_b32_e32 v5, v13\n\tv_mov_b32_e32 v8, v11\n\tv_add_co_u32 v4, s0, v4, v9\n\tv_add_co_ci_u32_e64 v8, s0, v5, v8, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v8\n\ts_mov_b64 s[2:3], 0\n\tv_cmp_eq_u64_e64 s0, v[6:7], s[2:3]\n\ts_or_b32 s0, s0, s1\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v33, s1, 13\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[6:7], s33 offset:116 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[4:5], s33 offset:108 ; 8-byte Folded Spill\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v6, v2\n\tv_mov_b32_e32 v5, v1\n\tv_mov_b32_e32 v4, v0\n\tscratch_store_b128 off, v[4:7], s33 offset:92 ; 16-byte Folded Spill\n\tscratch_store_b128 off, v[0:3], s33 offset:688 ; 16-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:8 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_4\n; %bb.61:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:8 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.62:\n\tscratch_load_b128 v[0:3], off, s33 offset:688 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:12 ; 16-byte Folded Spill\n\ts_branch .LBB6_3\n.LBB6_63:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 14\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b128 v[3:6], off, s33 offset:72 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v0, v3\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v32, 0\n\tv_readlane_b32 s31, v32, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v32, off, s33 offset:704 ; 4-byte Folded Reload\n\tscratch_load_b32 v33, off, s33 offset:708 ; 4-byte Folded Reload\n\tscratch_load_b32 v34, off, s33 offset:712 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xfffffd30\n\ts_mov_b32 s33, s20\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end6:\n\t.size\t__ockl_fprintf_append_string_n, .Lfunc_end6-__ockl_fprintf_append_string_n\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 11984\n; NumSgprs: 36\n; NumVgprs: 35\n; ScratchSize: 1120\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_append_args\n\t.type\t__ockl_fprintf_append_args,@function\n__ockl_fprintf_append_args: ; @__ockl_fprintf_append_args\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s19, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v28, s33 offset:8 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v29, s33 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 32\n\tv_writelane_b32 v28, s30, 0\n\tv_writelane_b32 v28, s31, 1\n\tscratch_store_b32 off, v17, s33 offset:4 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v17, v2\n\tv_mov_b32_e32 v18, v0\n\tscratch_load_b32 v0, off, s33 offset:4 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v15\n ; kill: def $vgpr20 killed $vgpr16 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v13\n ; kill: def $vgpr20 killed $vgpr14 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v11\n ; kill: def $vgpr20 killed $vgpr12 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v9\n ; kill: def $vgpr20 killed $vgpr10 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v7\n ; kill: def $vgpr20 killed $vgpr8 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v5\n ; kill: def $vgpr20 killed $vgpr6 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v3\n ; kill: def $vgpr20 killed $vgpr4 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr18 killed $vgpr18 def $vgpr18_vgpr19 killed $exec\n\tv_mov_b32_e32 v19, v1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s0, v0, s0\n\tv_mov_b32_e32 v1, v19\n\ts_mov_b64 s[2:3], 2\n\ts_mov_b32 s1, s3\n\tv_or_b32_e64 v0, v1, s1\n\tv_mov_b32_e32 v2, v18\n\ts_mov_b32 s1, s2\n\tv_or_b32_e64 v18, v2, s1\n ; kill: def $vgpr18 killed $vgpr18 def $vgpr18_vgpr19 killed $exec\n\tv_mov_b32_e32 v19, v0\n\tv_mov_b32_e32 v0, v19\n\tv_cndmask_b32_e64 v0, v0, v1, s0\n\tv_mov_b32_e32 v1, v18\n\tv_cndmask_b32_e64 v1, v1, v2, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v0, v2\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\tv_and_b32_e64 v0, v0, s2\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_and_b32_e64 v1, v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\tv_mov_b32_e32 v18, v0\n\ts_mov_b32 s0, 5\n\tv_lshlrev_b64 v[17:18], s0, v[17:18]\n\tv_mov_b32_e32 v0, v2\n\tv_mov_b32_e32 v19, v18\n\tv_or_b32_e64 v0, v0, v19\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v17\n\tv_or_b32_e64 v17, v1, v2\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\tv_mov_b32_e32 v18, v0\n\tv_mov_b32_e32 v1, v17\n\ts_mov_b32 s0, 32\n ; implicit-def: $vgpr29 : SGPR spill to VGPR lane\n\tv_writelane_b32 v29, s0, 0\n\tv_lshrrev_b64 v[17:18], s0, v[17:18]\n\tv_mov_b32_e32 v2, v17\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v29, 0\n\tscratch_store_b32 off, v1, s33 ; 4-byte Folded Spill\n ; kill: def $vgpr1 killed $vgpr3 killed $exec\n\tscratch_load_b32 v3, off, s33 ; 4-byte Folded Reload\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v1, s1\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v3\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v28, 0\n\tv_readlane_b32 s31, v28, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v28, off, s33 offset:8 ; 4-byte Folded Reload\n\tscratch_load_b32 v29, off, s33 offset:12 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xffffffe0\n\ts_mov_b32 s33, s19\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end7:\n\t.size\t__ockl_fprintf_append_args, .Lfunc_end7-__ockl_fprintf_append_args\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 452\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 432\n; MemoryBound: 0\n\t.text\n\t.hidden\t__assert_fail ; -- Begin function __assert_fail\n\t.weak\t__assert_fail\n\t.p2align\t2\n\t.type\t__assert_fail,@function\n__assert_fail: ; @__assert_fail\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s27, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v35, s33 offset:176 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v36, s33 offset:180 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v37, s33 offset:184 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xc0\n\tv_writelane_b32 v35, s30, 0\n\tv_writelane_b32 v35, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:168 ; 4-byte Folded Spill\n ; implicit-def: $vgpr37 : SGPR spill to VGPR lane\n\tv_writelane_b32 v37, s6, 0\n\tv_writelane_b32 v37, s7, 1\n\tscratch_store_b32 off, v5, s33 offset:164 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v3, s33 offset:160 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v5, v2\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v7, v0\n\tscratch_load_b32 v0, off, s33 offset:160 ; 4-byte Folded Reload\n\tv_writelane_b32 v37, s15, 2\n\tv_writelane_b32 v37, s14, 3\n\tv_writelane_b32 v37, s13, 4\n\tv_writelane_b32 v37, s12, 5\n\tv_writelane_b32 v37, s10, 6\n\tv_writelane_b32 v37, s11, 7\n\tv_writelane_b32 v37, s8, 8\n\tv_writelane_b32 v37, s9, 9\n\tv_writelane_b32 v37, s4, 10\n\tv_writelane_b32 v37, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v6, v0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b64 s[0:1], src_private_base\n\ts_mov_b32 s2, 32\n\ts_lshr_b64 s[0:1], s[0:1], s2\n\ts_mov_b32 s24, s0\n\tv_writelane_b32 v37, s24, 12\n\ts_mov_b32 s20, s33\n ; kill: def $sgpr20 killed $sgpr20 def $sgpr20_sgpr21\n\ts_mov_b32 s21, s24\n\ts_mov_b64 s[0:1], s[20:21]\n\tv_writelane_b32 v37, s0, 13\n\tv_writelane_b32 v37, s1, 14\n\ts_add_i32 s0, s33, 8\n\ts_mov_b32 s18, s0\n ; kill: def $sgpr18 killed $sgpr18 def $sgpr18_sgpr19\n\ts_mov_b32 s19, s24\n\ts_mov_b64 s[0:1], s[18:19]\n\tv_writelane_b32 v37, s0, 15\n\tv_writelane_b32 v37, s1, 16\n\ts_add_i32 s0, s33, 16\n\ts_mov_b32 s2, s0\n ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3\n\ts_mov_b32 s3, s24\n\ts_mov_b64 s[0:1], s[2:3]\n\tv_writelane_b32 v37, s0, 17\n\tv_writelane_b32 v37, s1, 18\n\ts_add_i32 s1, s33, 24\n\ts_mov_b32 s0, s1\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s24\n\ts_mov_b64 s[16:17], s[0:1]\n\tv_writelane_b32 v37, s16, 19\n\tv_writelane_b32 v37, s17, 20\n\ts_add_i32 s17, s33, 32\n\ts_mov_b32 s16, s17\n ; kill: def $sgpr16 killed $sgpr16 def $sgpr16_sgpr17\n\ts_mov_b32 s17, s24\n\tv_writelane_b32 v37, s16, 21\n\tv_writelane_b32 v37, s17, 22\n\ts_mov_b64 s[22:23], s[16:17]\n\tv_writelane_b32 v37, s22, 23\n\tv_writelane_b32 v37, s23, 24\n\ts_add_i32 s23, s33, 0x50\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v37, s22, 25\n\tv_writelane_b32 v37, s23, 26\n\tv_writelane_b32 v37, s22, 27\n\tv_writelane_b32 v37, s23, 28\n\ts_add_i32 s23, s33, 0x58\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v37, s22, 29\n\tv_writelane_b32 v37, s23, 30\n ; implicit-def: $vgpr36 : SGPR spill to VGPR lane\n\tv_writelane_b32 v37, s22, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:148 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_writelane_b32 v36, s23, 0\n\ts_add_i32 s23, s33, 0x60\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 1\n\tv_writelane_b32 v36, s23, 2\n\ts_add_i32 s23, s33, 0x68\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 3\n\tv_writelane_b32 v36, s23, 4\n\ts_add_i32 s23, s33, 0x70\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 5\n\tv_writelane_b32 v36, s23, 6\n\ts_add_i32 s23, s33, 0x78\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 7\n\tv_writelane_b32 v36, s23, 8\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_mov_b32_e32 v0, s20\n\tv_mov_b32_e32 v1, s21\n\tflat_store_b64 v[0:1], v[7:8]\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tflat_store_b64 v[0:1], v[5:6]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b32 v[0:1], v4\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, s33 offset:156 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+35\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+43\n\tglobal_load_b128 v[0:3], v0, s[0:1]\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:128\n\tscratch_load_b64 v[0:1], off, s33 offset:136\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_d16_hi_b8 v[3:4], v2 offset:45\n\ts_mov_b32 s1, 24\n\tv_lshrrev_b32_e64 v5, s1, v2\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v5 offset:46\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v2 offset:43\n\ts_mov_b32 s0, 8\n\tv_lshrrev_b32_e64 v4, s0, v2\n\tv_mov_b32_e32 v2, s16\n\tv_mov_b32_e32 v3, s17\n\tflat_store_b8 v[2:3], v4 offset:44\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_d16_hi_b8 v[1:2], v0 offset:41\n\tv_lshrrev_b32_e64 v3, s1, v0\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v3 offset:42\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v0 offset:39\n\tv_lshrrev_b32_e64 v2, s0, v0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b8 v[0:1], v2 offset:40\n\tscratch_load_b64 v[0:1], off, s33 offset:128\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_d16_hi_b8 v[3:4], v2 offset:37\n\tv_lshrrev_b32_e64 v5, s1, v2\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v5 offset:38\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v2 offset:35\n\tv_lshrrev_b32_e64 v4, s0, v2\n\tv_mov_b32_e32 v2, s16\n\tv_mov_b32_e32 v3, s17\n\tflat_store_b8 v[2:3], v4 offset:36\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_d16_hi_b8 v[1:2], v0 offset:33\n\tv_lshrrev_b32_e64 v3, s1, v0\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v3 offset:34\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v0 offset:31\n\tv_lshrrev_b32_e64 v2, s0, v0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b8 v[0:1], v2 offset:32\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+20\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+28\n\ts_load_b128 s[0:3], s[0:1], 0x0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v5, s3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b128 v[0:1], v[2:5] offset:16\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+4\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+12\n\ts_load_b128 s[0:3], s[0:1], 0x0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v5, s3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b128 v[0:1], v[2:5]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_stderr_begin@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_stderr_begin@rel32@hi+12\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v2, off, s33 offset:156 ; 4-byte Folded Reload\n\tv_readlane_b32 s2, v37, 25\n\tv_readlane_b32 s3, v37, 26\n\tv_readlane_b32 s0, v37, 29\n\tv_readlane_b32 s1, v37, 30\n\tv_mov_b32_e32 v3, v0\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b64 v[0:1], v[3:4]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0)\n\tflat_store_b32 v[0:1], v2\n; %bb.1:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 23\n\tv_readlane_b32 s1, v36, 24\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s3, v37, 2\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 9\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_2: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s3, v37, 2\n\tv_readlane_b32 s0, v37, 10\n\tv_readlane_b32 s1, v37, 9\n\tv_writelane_b32 v37, s1, 11\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 12\n\tv_writelane_b32 v37, s0, 13\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 14\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_4\n; %bb.3: ; in Loop: Header=BB8_2 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 12\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 13\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_4: ; in Loop: Header=BB8_2 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 14\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 11\n\tv_readlane_b32 s1, v37, 13\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 10\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 9\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 15\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_2\n; %bb.5:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.6:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 23\n\tv_readlane_b32 s3, v36, 24\n\tv_readlane_b32 s4, v37, 1\n\tv_readlane_b32 s5, v37, 2\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, s2\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.7:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 23\n\tv_readlane_b32 s1, v37, 24\n\tv_readlane_b32 s2, v37, 31\n\tv_readlane_b32 s3, v36, 0\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v5, v4\n\tv_mov_b32_e32 v6, v0\n\ts_mov_b32 s3, 32\n\ts_lshr_b64 s[16:17], s[0:1], s3\n\ts_mov_b32 s2, s16\n\tv_lshrrev_b64 v[0:1], s3, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[5:6], s3, v[5:6]\n ; kill: def $vgpr5 killed $vgpr5 killed $vgpr5_vgpr6 killed $exec\n\ts_mov_b32 s3, s0\n\tv_mov_b32_e32 v0, v2\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v2, s3\n\tv_mov_b32_e32 v3, s2\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.8:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 3\n\tv_readlane_b32 s1, v37, 4\n\tv_readlane_b32 s2, v36, 15\n\tv_readlane_b32 s3, v36, 16\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 16\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_9: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 3\n\tv_readlane_b32 s3, v37, 4\n\tv_readlane_b32 s0, v37, 17\n\tv_readlane_b32 s1, v37, 16\n\tv_writelane_b32 v37, s1, 18\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 19\n\tv_writelane_b32 v37, s0, 20\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 21\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_11\n; %bb.10: ; in Loop: Header=BB8_9 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 19\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 20\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_11: ; in Loop: Header=BB8_9 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 18\n\tv_readlane_b32 s1, v37, 20\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 17\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 16\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 22\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_9\n; %bb.12:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.13:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 15\n\tv_readlane_b32 s3, v36, 16\n\tv_readlane_b32 s4, v37, 3\n\tv_readlane_b32 s5, v37, 4\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.14:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 15\n\tv_readlane_b32 s3, v37, 16\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_writelane_b32 v36, s0, 23\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\tscratch_store_b32 off, v6, s33 offset:172 ; 4-byte Folded Spill\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tscratch_load_b32 v17, off, s33 offset:172 ; 4-byte Folded Reload\n\tv_readlane_b32 s2, v37, 17\n\tv_readlane_b32 s3, v37, 18\n\tv_readlane_b32 s0, v36, 23\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v3, v[0:1]\n\ts_waitcnt vmcnt(1) lgkmcnt(1)\n\tv_lshrrev_b64 v[0:1], s0, v[4:5]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v4\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_args@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_args@rel32@hi+12\n\tv_mov_b32_e32 v2, 1\n\tv_mov_b32_e32 v4, v17\n\tv_mov_b32_e32 v5, v17\n\tv_mov_b32_e32 v6, v17\n\tv_mov_b32_e32 v7, v17\n\tv_mov_b32_e32 v8, v17\n\tv_mov_b32_e32 v9, v17\n\tv_mov_b32_e32 v10, v17\n\tv_mov_b32_e32 v11, v17\n\tv_mov_b32_e32 v12, v17\n\tv_mov_b32_e32 v13, v17\n\tv_mov_b32_e32 v14, v17\n\tv_mov_b32_e32 v15, v17\n\tv_mov_b32_e32 v16, v17\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.15:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 5\n\tv_readlane_b32 s1, v37, 6\n\tv_readlane_b32 s2, v36, 19\n\tv_readlane_b32 s3, v36, 20\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 24\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_16: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 5\n\tv_readlane_b32 s3, v37, 6\n\tv_readlane_b32 s0, v37, 25\n\tv_readlane_b32 s1, v37, 24\n\tv_writelane_b32 v37, s1, 26\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 27\n\tv_writelane_b32 v37, s0, 28\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 29\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_18\n; %bb.17: ; in Loop: Header=BB8_16 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 27\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 28\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_18: ; in Loop: Header=BB8_16 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 26\n\tv_readlane_b32 s1, v37, 28\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 25\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 24\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 30\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_16\n; %bb.19:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 30\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.20:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 19\n\tv_readlane_b32 s3, v36, 20\n\tv_readlane_b32 s4, v37, 5\n\tv_readlane_b32 s5, v37, 6\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.21:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 19\n\tv_readlane_b32 s3, v37, 20\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.22:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 7\n\tv_readlane_b32 s1, v37, 8\n\tv_readlane_b32 s2, v36, 13\n\tv_readlane_b32 s3, v36, 14\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_23: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v36, 7\n\tv_readlane_b32 s3, v36, 8\n ; implicit-def: $vgpr37 : SGPR spill to VGPR lane\n\tv_readlane_b32 s0, v37, 0\n\tv_readlane_b32 s1, v36, 31\n\tv_writelane_b32 v37, s1, 1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 2\n\tv_writelane_b32 v37, s0, 3\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 4\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_25\n; %bb.24: ; in Loop: Header=BB8_23 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 2\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 3\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_25: ; in Loop: Header=BB8_23 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s1, v37, 3\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 0\n\ts_mov_b32 s1, s0\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v36, s1, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 5\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_23\n; %bb.26:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 5\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.27:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 13\n\tv_readlane_b32 s3, v36, 14\n\tv_readlane_b32 s4, v37, 7\n\tv_readlane_b32 s5, v37, 8\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.28:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 13\n\tv_readlane_b32 s3, v37, 14\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 1\n\ts_swappc_b64 s[30:31], s[0:1]\n\ts_cbranch_execnz .LBB8_30\n; %bb.29:\n\tv_readlane_b32 s30, v35, 0\n\tv_readlane_b32 s31, v35, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v35, off, s33 offset:176 ; 4-byte Folded Reload\n\tscratch_load_b32 v36, off, s33 offset:180 ; 4-byte Folded Reload\n\tscratch_load_b32 v37, off, s33 offset:184 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xffffff40\n\ts_mov_b32 s33, s27\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.LBB8_30:\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB8_31: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB8_31\n.Lfunc_end8:\n\t.size\t__assert_fail, .Lfunc_end8-__assert_fail\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 6148\n; NumSgprs: 36\n; NumVgprs: 38\n; ScratchSize: 1312\n; MemoryBound: 0\n\t.text\n\t.hidden\t__assertfail ; -- Begin function __assertfail\n\t.weak\t__assertfail\n\t.p2align\t2\n\t.type\t__assertfail,@function\n__assertfail: ; @__assertfail\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_cbranch_execnz .LBB9_2\n; %bb.1:\n\ts_setpc_b64 s[30:31]\n.LBB9_2:\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB9_3: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB9_3\n.Lfunc_end9:\n\t.size\t__assertfail, .Lfunc_end9-__assertfail\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 64\n; NumSgprs: 32\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_get_local_id\n\t.type\t__ockl_get_local_id,@function\n__ockl_get_local_id: ; @__ockl_get_local_id\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v2, s32 offset:36 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v31, s32 offset:8 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill\n; %bb.1:\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n ; implicit-def: $vgpr2 : SGPR spill to VGPR lane\n\tv_writelane_b32 v2, s1, 0\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_4\n; %bb.2:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v2, s1, 1\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_7\n; %bb.3:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 2\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_10\n\ts_branch .LBB10_9\n.LBB10_4:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 0\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:12 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 3\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB10_13\n; %bb.5:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 4\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_12\n; %bb.6:\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0x3ff\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_branch .LBB10_12\n.LBB10_7:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 1\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:16 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:32 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 5\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB10_11\n; %bb.8:\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_bfe_u32 v0, v0, 10, 10\n\tscratch_store_b32 off, v0, s32 offset:32 ; 4-byte Folded Spill\n\ts_branch .LBB10_11\n.LBB10_9:\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_bfe_u32 v0, v0, 20, 10\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n.LBB10_10:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 2\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:20 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_branch .LBB10_7\n.LBB10_11:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 5\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:32 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_branch .LBB10_4\n.LBB10_12:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n.LBB10_13:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 3\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:24 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v1, 0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v2, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end10:\n\t.size\t__ockl_get_local_id, .Lfunc_end10-__ockl_get_local_id\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 912\n; NumSgprs: 33\n; NumVgprs: 32\n; ScratchSize: 44\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_get_group_id\n\t.type\t__ockl_get_group_id,@function\n__ockl_get_group_id: ; @__ockl_get_group_id\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v2, s32 offset:32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill\n ; implicit-def: $vgpr2 : SGPR spill to VGPR lane\n\tv_writelane_b32 v2, s14, 0\n\tv_writelane_b32 v2, s13, 1\n\tv_writelane_b32 v2, s12, 2\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n; %bb.1:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v2, s1, 3\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_4\n; %bb.2:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v2, s1, 4\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_7\n; %bb.3:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 5\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_10\n\ts_branch .LBB11_9\n.LBB11_4:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 3\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 6\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB11_13\n; %bb.5:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 7\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_12\n; %bb.6:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 2\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_branch .LBB11_12\n.LBB11_7:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 4\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:12 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 8\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB11_11\n; %bb.8:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 1\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_branch .LBB11_11\n.LBB11_9:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 0\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n.LBB11_10:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 5\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:16 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_branch .LBB11_7\n.LBB11_11:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 8\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill\n\ts_branch .LBB11_4\n.LBB11_12:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 7\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:24 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n.LBB11_13:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 6\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:20 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v1, 0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v2, off, s32 offset:32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end11:\n\t.size\t__ockl_get_group_id, .Lfunc_end11-__ockl_get_group_id\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 988\n; NumSgprs: 33\n; NumVgprs: 3\n; ScratchSize: 40\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_get_local_size\n\t.type\t__ockl_get_local_size,@function\n__ockl_get_local_size: ; @__ockl_get_local_size\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v4, s32 offset:104 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill\n ; implicit-def: $vgpr4 : SGPR spill to VGPR lane\n\tv_writelane_b32 v4, s14, 0\n\tv_writelane_b32 v4, s13, 1\n\tv_writelane_b32 v4, s12, 2\n\tv_writelane_b32 v4, s8, 3\n\tv_writelane_b32 v4, s9, 4\n\tv_writelane_b32 v4, s4, 5\n\tv_writelane_b32 v4, s5, 6\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n; %bb.1:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:8 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v4, s1, 7\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_4\n; %bb.2:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:16 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v4, s1, 8\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_10\n; %bb.3:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 1\n\tv_mov_b32_e32 v0, 1\n\tv_mov_b32_e32 v1, 0\n\tscratch_store_b64 off, v[0:1], s32 offset:24 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v4, s0, 9\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_20\n\ts_branch .LBB12_15\n.LBB12_4:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 7\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:8 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:32 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v4, s0, 10\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB12_25\n; %bb.5:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 1\n\tv_mov_b32_e32 v0, 1\n\tv_mov_b32_e32 v1, 0\n\tscratch_store_b64 off, v[0:1], s32 offset:40 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v4, s0, 11\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_24\n; %bb.6:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n ; implicit-def: $sgpr2_sgpr3\n\ts_mov_b32 s4, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s4\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:48 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v4, s0, 12\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB12_9\n.LBB12_7:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 12\n\tscratch_load_b64 v[0:1], off, s32 offset:48 ; 8-byte Folded Reload\n\tv_cndmask_b32_e64 v2, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v2, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n ; kill: def $vgpr0_vgpr1 killed $vgpr0_vgpr1 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:56 ; 8-byte Folded Spill\n\ts_cbranch_vccnz .LBB12_23\n; %bb.8:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v4, 2\n\tv_readlane_b32 s2, v4, 5\n\tv_readlane_b32 s3, v4, 6\n\tv_mov_b32_e32 v0, 0\n\tglobal_load_u16 v1, v0, s[2:3] offset:4\n\ts_load_b32 s0, s[2:3], 0xc\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v0, s1, v1\n\ts_waitcnt lgkmcnt(0)\n\tv_sub_nc_u32_e64 v0, s0, v0\n ; implicit-def: $sgpr0\n\tv_min_u32_e64 v0, v0, v1\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr0_sgpr1\n\tscratch_store_b64 off, v[0:1], s32 offset:56 ; 8-byte Folded Spill\n\ts_branch .LBB12_23\n.LBB12_9:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 3\n\tv_readlane_b32 s1, v4, 4\n\tv_readlane_b32 s2, v4, 2\n\ts_load_b32 s3, s[0:1], 0x0\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_u32 s2, s3\n\ts_mov_b32 s3, 18\n\ts_mov_b32 s2, 12\n\ts_cselect_b32 s2, s2, s3\n\tv_mov_b32_e32 v0, s2\n\tglobal_load_u16 v0, v0, s[0:1]\n\ts_mov_b32 s0, 0xffff\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n ; implicit-def: $sgpr0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr2_sgpr3\n\tscratch_store_b64 off, v[0:1], s32 offset:48 ; 8-byte Folded Spill\n\tv_writelane_b32 v4, s0, 12\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB12_7\n.LBB12_10:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 8\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:16 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:64 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v4, s0, 13\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB12_22\n; %bb.11:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n ; implicit-def: $sgpr2_sgpr3\n\ts_mov_b32 s4, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s4\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:72 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v4, s0, 14\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB12_14\n.LBB12_12:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 14\n\tscratch_load_b64 v[0:1], off, s32 offset:72 ; 8-byte Folded Reload\n\tv_cndmask_b32_e64 v2, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v2, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n ; kill: def $vgpr0_vgpr1 killed $vgpr0_vgpr1 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:80 ; 8-byte Folded Spill\n\ts_cbranch_vccnz .LBB12_21\n; %bb.13:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v4, 1\n\tv_readlane_b32 s2, v4, 5\n\tv_readlane_b32 s3, v4, 6\n\tv_mov_b32_e32 v0, 0\n\tglobal_load_u16 v1, v0, s[2:3] offset:6\n\ts_load_b32 s0, s[2:3], 0x10\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v0, s1, v1\n\ts_waitcnt lgkmcnt(0)\n\tv_sub_nc_u32_e64 v0, s0, v0\n ; implicit-def: $sgpr0\n\tv_min_u32_e64 v0, v0, v1\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr0_sgpr1\n\tscratch_store_b64 off, v[0:1], s32 offset:80 ; 8-byte Folded Spill\n\ts_branch .LBB12_21\n.LBB12_14:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 3\n\tv_readlane_b32 s1, v4, 4\n\tv_readlane_b32 s2, v4, 1\n\ts_load_b32 s3, s[0:1], 0x4\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_u32 s2, s3\n\ts_mov_b32 s3, 20\n\ts_mov_b32 s2, 14\n\ts_cselect_b32 s2, s2, s3\n\tv_mov_b32_e32 v0, s2\n\tglobal_load_u16 v0, v0, s[0:1]\n\ts_mov_b32 s0, 0xffff\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n ; implicit-def: $sgpr0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr2_sgpr3\n\tscratch_store_b64 off, v[0:1], s32 offset:72 ; 8-byte Folded Spill\n\tv_writelane_b32 v4, s0, 14\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB12_12\n.LBB12_15:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n ; implicit-def: $sgpr2_sgpr3\n\ts_mov_b32 s4, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s4\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:88 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v4, s0, 15\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB12_18\n.LBB12_16:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 15\n\tscratch_load_b64 v[0:1], off, s32 offset:88 ; 8-byte Folded Reload\n\tv_cndmask_b32_e64 v2, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v2, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n ; kill: def $vgpr0_vgpr1 killed $vgpr0_vgpr1 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:96 ; 8-byte Folded Spill\n\ts_cbranch_vccnz .LBB12_19\n; %bb.17:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v4, 0\n\tv_readlane_b32 s2, v4, 5\n\tv_readlane_b32 s3, v4, 6\n\tv_mov_b32_e32 v0, 0\n\tglobal_load_u16 v1, v0, s[2:3] offset:8\n\ts_load_b32 s0, s[2:3], 0x14\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v0, s1, v1\n\ts_waitcnt lgkmcnt(0)\n\tv_sub_nc_u32_e64 v0, s0, v0\n ; implicit-def: $sgpr0\n\tv_min_u32_e64 v0, v0, v1\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr0_sgpr1\n\tscratch_store_b64 off, v[0:1], s32 offset:96 ; 8-byte Folded Spill\n\ts_branch .LBB12_19\n.LBB12_18:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 3\n\tv_readlane_b32 s1, v4, 4\n\tv_readlane_b32 s2, v4, 0\n\ts_load_b32 s3, s[0:1], 0x8\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_u32 s2, s3\n\ts_mov_b32 s3, 22\n\ts_mov_b32 s2, 16\n\ts_cselect_b32 s2, s2, s3\n\tv_mov_b32_e32 v0, s2\n\tglobal_load_u16 v0, v0, s[0:1]\n\ts_mov_b32 s0, 0xffff\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n ; implicit-def: $sgpr0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr2_sgpr3\n\tscratch_store_b64 off, v[0:1], s32 offset:88 ; 8-byte Folded Spill\n\tv_writelane_b32 v4, s0, 15\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB12_16\n.LBB12_19:\n\tscratch_load_b64 v[0:1], off, s32 offset:96 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:24 ; 8-byte Folded Spill\n.LBB12_20:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 9\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:24 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:16 ; 8-byte Folded Spill\n\ts_branch .LBB12_10\n.LBB12_21:\n\tscratch_load_b64 v[0:1], off, s32 offset:80 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:64 ; 8-byte Folded Spill\n.LBB12_22:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 13\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:64 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:8 ; 8-byte Folded Spill\n\ts_branch .LBB12_4\n.LBB12_23:\n\tscratch_load_b64 v[0:1], off, s32 offset:56 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:40 ; 8-byte Folded Spill\n.LBB12_24:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 11\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:40 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:32 ; 8-byte Folded Spill\n.LBB12_25:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 10\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[2:3], off, s32 offset:32 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 32\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[0:1], s0, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v2\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v4, off, s32 offset:104 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end12:\n\t.size\t__ockl_get_local_size, .Lfunc_end12-__ockl_get_local_size\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 2384\n; NumSgprs: 35\n; NumVgprs: 5\n; ScratchSize: 112\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function _ZL20__work_group_barrierj\n\t.type\t_ZL20__work_group_barrierj,@function\n_ZL20__work_group_barrierj: ; @_ZL20__work_group_barrierj\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v3, s32 offset:8 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b64 s[0:1], src_private_base\n\ts_mov_b32 s2, 32\n\ts_lshr_b64 s[0:1], s[0:1], s2\n\ts_mov_b32 s2, s0\n\ts_mov_b32 s0, s32\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v0, v[0:1]\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_eq_u32_e64 s0, v0, s0\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n ; implicit-def: $vgpr3 : SGPR spill to VGPR lane\n\tv_writelane_b32 v3, s1, 0\n\ts_or_saveexec_b32 s4, -1\n\tscratch_store_b32 off, v3, s32 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s4\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB13_1\n\ts_branch .LBB13_3\n.LBB13_1:\n\ts_or_saveexec_b32 s4, -1\n\tscratch_load_b32 v3, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s4\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v3, 0\n\ts_or_saveexec_b32 s0, s0\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v3, s0, 1\n\ts_or_saveexec_b32 s4, -1\n\tscratch_store_b32 off, v3, s32 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s4\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB13_4\n; %bb.2:\n\ts_waitcnt_vscnt null, 0x0\n\ts_barrier\n\tbuffer_gl0_inv\n\ts_branch .LBB13_4\n.LBB13_3:\n\ts_waitcnt_vscnt null, 0x0\n\ts_barrier\n\ts_branch .LBB13_1\n.LBB13_4:\n\ts_or_saveexec_b32 s4, -1\n\tscratch_load_b32 v3, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s4\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v3, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v3, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end13:\n\t.size\t_ZL20__work_group_barrierj, .Lfunc_end13-_ZL20__work_group_barrierj\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 300\n; NumSgprs: 33\n; NumVgprs: 4\n; ScratchSize: 16\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function _ZL9__barrieri\n\t.type\t_ZL9__barrieri,@function\n_ZL9__barrieri: ; @_ZL9__barrieri\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s3, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v4, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 16\n\tv_writelane_b32 v4, s30, 0\n\tv_writelane_b32 v4, s31, 1\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b64 s[0:1], src_private_base\n\ts_mov_b32 s2, 32\n\ts_lshr_b64 s[0:1], s[0:1], s2\n\ts_mov_b32 s2, s0\n\ts_mov_b32 s0, s33\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v0, v[0:1]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, _ZL20__work_group_barrierj@rel32@lo+4\n\ts_addc_u32 s1, s1, _ZL20__work_group_barrierj@rel32@hi+12\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s30, v4, 0\n\tv_readlane_b32 s31, v4, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v4, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, -16\n\ts_mov_b32 s33, s3\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end14:\n\t.size\t_ZL9__barrieri, .Lfunc_end14-_ZL9__barrieri\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 180\n; NumSgprs: 34\n; NumVgprs: 32\n; ScratchSize: 32\n; MemoryBound: 0\n\t.section\t.text._Z13__syncthreadsv,\"axG\",@progbits,_Z13__syncthreadsv,comdat\n\t.hidden\t_Z13__syncthreadsv ; -- Begin function _Z13__syncthreadsv\n\t.weak\t_Z13__syncthreadsv\n\t.p2align\t2\n\t.type\t_Z13__syncthreadsv,@function\n_Z13__syncthreadsv: ; @_Z13__syncthreadsv\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s16, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v5, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 16\n\tv_writelane_b32 v5, s30, 0\n\tv_writelane_b32 v5, s31, 1\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, _ZL9__barrieri@rel32@lo+4\n\ts_addc_u32 s1, s1, _ZL9__barrieri@rel32@hi+12\n\tv_mov_b32_e32 v0, 1\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s30, v5, 0\n\tv_readlane_b32 s31, v5, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v5, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, -16\n\ts_mov_b32 s33, s16\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end15:\n\t.size\t_Z13__syncthreadsv, .Lfunc_end15-_Z13__syncthreadsv\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 124\n; NumSgprs: 34\n; NumVgprs: 32\n; ScratchSize: 48\n; MemoryBound: 0\n\t.section\t.text._Z13sigmoidKernelIfEvPT_S1_i,\"axG\",@progbits,_Z13sigmoidKernelIfEvPT_S1_i,comdat\n\t.protected\t_Z13sigmoidKernelIfEvPT_S1_i ; -- Begin function _Z13sigmoidKernelIfEvPT_S1_i\n\t.globl\t_Z13sigmoidKernelIfEvPT_S1_i\n\t.p2align\t8\n\t.type\t_Z13sigmoidKernelIfEvPT_S1_i,@function\n_Z13sigmoidKernelIfEvPT_S1_i: ; @_Z13sigmoidKernelIfEvPT_S1_i\n; %bb.0:\n\ts_mov_b32 s32, 0x80\n ; implicit-def: $vgpr40 : SGPR spill to VGPR lane\n\tv_writelane_b32 v40, s15, 0\n\ts_mov_b32 s6, s14\n\tv_readlane_b32 s14, v40, 0\n\tv_writelane_b32 v40, s6, 1\n\ts_mov_b32 s12, s13\n\tv_readlane_b32 s13, v40, 1\n\tv_writelane_b32 v40, s12, 2\n\ts_mov_b64 s[10:11], s[4:5]\n\tv_writelane_b32 v40, s10, 3\n\tv_writelane_b32 v40, s11, 4\n\tv_writelane_b32 v40, s2, 5\n\tv_writelane_b32 v40, s3, 6\n\ts_mov_b64 s[4:5], s[0:1]\n\tv_readlane_b32 s0, v40, 5\n\tv_readlane_b32 s1, v40, 6\n\tv_writelane_b32 v40, s4, 7\n\tv_writelane_b32 v40, s5, 8\n\tv_mov_b32_e32 v31, v0\n\tscratch_store_b32 off, v31, off offset:108 ; 4-byte Folded Spill\n\ts_load_b64 s[24:25], s[0:1], 0x0\n\ts_load_b64 s[20:21], s[0:1], 0x8\n\ts_load_b32 s2, s[0:1], 0x10\n\ts_mov_b64 s[6:7], src_private_base\n\ts_mov_b32 s3, 32\n\ts_lshr_b64 s[6:7], s[6:7], s3\n\ts_mov_b32 s3, s6\n\ts_mov_b32 s22, 48\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s3\n\ts_mov_b32 s18, 56\n ; kill: def $sgpr18 killed $sgpr18 def $sgpr18_sgpr19\n\ts_mov_b32 s19, s3\n\ts_mov_b32 s16, 64\n ; kill: def $sgpr16 killed $sgpr16 def $sgpr16_sgpr17\n\ts_mov_b32 s17, s3\n\ts_mov_b64 s[6:7], s[16:17]\n\tv_writelane_b32 v40, s6, 9\n\tv_writelane_b32 v40, s7, 10\n\ts_mov_b32 s8, 0x48\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s3\n\ts_mov_b64 s[6:7], s[8:9]\n\tv_writelane_b32 v40, s6, 11\n\tv_writelane_b32 v40, s7, 12\n\ts_mov_b32 s6, 0x50\n ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7\n\ts_mov_b32 s7, s3\n\tv_writelane_b32 v40, s6, 13\n\tv_writelane_b32 v40, s7, 14\n\ts_mov_b32 s26, 0x54\n ; kill: def $sgpr26 killed $sgpr26 def $sgpr26_sgpr27\n\ts_mov_b32 s27, s3\n\tv_writelane_b32 v40, s26, 15\n\tv_writelane_b32 v40, s27, 16\n\tv_writelane_b32 v40, s26, 17\n\tv_writelane_b32 v40, s27, 18\n\tv_mov_b32_e32 v0, s22\n\tv_mov_b32_e32 v1, s23\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v2, s24\n\tv_mov_b32_e32 v3, s25\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s22\n\tv_mov_b32_e32 v1, s23\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tv_mov_b32_e32 v2, s20\n\tv_mov_b32_e32 v3, s21\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\ts_waitcnt vmcnt(1) lgkmcnt(2)\n\tflat_store_b64 v[0:1], v[4:5]\n\tv_mov_b32_e32 v0, s8\n\tv_mov_b32_e32 v1, s9\n\ts_waitcnt vmcnt(0) lgkmcnt(1)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tv_mov_b32_e32 v2, s2\n\tflat_store_b32 v[0:1], v2\n\ts_mov_b64 s[6:7], 24\n\ts_mov_b32 s2, s0\n\ts_mov_b32 s0, s1\n\ts_mov_b32 s3, s6\n\ts_mov_b32 s1, s7\n\ts_add_u32 s8, s2, s3\n\ts_addc_u32 s0, s0, s1\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s0\n\tv_writelane_b32 v40, s8, 19\n\tv_writelane_b32 v40, s9, 20\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_id@rel32@hi+12\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, off offset:104 ; 4-byte Folded Spill\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:108 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v40, 0\n\tv_readlane_b32 s13, v40, 1\n\tv_readlane_b32 s12, v40, 2\n\tv_readlane_b32 s10, v40, 3\n\tv_readlane_b32 s11, v40, 4\n\tv_readlane_b32 s8, v40, 19\n\tv_readlane_b32 s9, v40, 20\n\tv_readlane_b32 s4, v40, 7\n\tv_readlane_b32 s5, v40, 8\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:104 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:112 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:112 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v1, off offset:96 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_group_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_group_id@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:108 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v40, 0\n\tv_readlane_b32 s13, v40, 1\n\tv_readlane_b32 s12, v40, 2\n\tv_readlane_b32 s10, v40, 3\n\tv_readlane_b32 s11, v40, 4\n\tv_readlane_b32 s8, v40, 19\n\tv_readlane_b32 s9, v40, 20\n\tv_readlane_b32 s4, v40, 7\n\tv_readlane_b32 s5, v40, 8\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:104 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:100 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:100 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v1, off offset:92 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_size@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_size@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v4, off, off offset:96 ; 4-byte Folded Reload\n\tscratch_load_b32 v2, off, off offset:92 ; 4-byte Folded Reload\n\tv_readlane_b32 s2, v40, 15\n\tv_readlane_b32 s3, v40, 16\n\tv_readlane_b32 s0, v40, 13\n\tv_readlane_b32 s1, v40, 14\n\tv_mov_b32_e32 v3, v1\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tv_mov_b32_e32 v3, v0\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr5\n ; implicit-def: $sgpr5\n\tv_mov_b32_e32 v0, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[0:1], s4, v2, v3, v[4:5]\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v2, s1\n\tv_mov_b32_e32 v1, s0\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_lt_i32_e64 s1, v0, v1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v40, s0, 21\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v40, off offset:88 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB16_2\n; %bb.1:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v40, off, off offset:88 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v40, 17\n\tv_readlane_b32 s3, v40, 18\n\tv_readlane_b32 s4, v40, 11\n\tv_readlane_b32 s5, v40, 12\n\tv_readlane_b32 s0, v40, 9\n\tv_readlane_b32 s1, v40, 10\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\ts_mov_b32 s0, 2\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b32 v0, v[0:1]\n\ts_mov_b32 s1, 0x80000000\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_xor_b32_e64 v2, s1, v0\n\ts_mov_b64 s[6:7], src_private_base\n\ts_mov_b32 s1, 32\n\ts_lshr_b64 s[6:7], s[6:7], s1\n\ts_mov_b32 s1, s6\n\ts_mov_b32 s6, 28\n ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7\n\ts_mov_b32 s7, s1\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tflat_load_b32 v2, v[0:1]\n\ts_mov_b32 s6, 8\n ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7\n\ts_mov_b32 s7, s1\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tflat_load_b32 v1, v[0:1]\n\ts_mov_b32 s1, 0x3fb8aa3b\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mul_f32_e64 v0, v1, s1\n\tv_fma_f32 v3, v1, s1, -v0\n\ts_mov_b32 s1, 0x32a5705f\n\tv_fmac_f32_e64 v3, v1, s1\n\tv_rndne_f32_e64 v2, v0\n\tv_sub_f32_e64 v0, v0, v2\n\tv_add_f32_e64 v0, v0, v3\n\tv_exp_f32_e64 v0, v0\n\tv_cvt_i32_f32_e64 v2, v2\n\ts_waitcnt_depctr 0xfff\n\tv_ldexp_f32 v0, v0, v2\n\ts_mov_b32 s1, 0xc2ce8ed0\n\tv_cmp_lt_f32_e64 s6, v1, s1\n\ts_mov_b32 s1, 0\n\tv_cndmask_b32_e64 v0, v0, s1, s6\n\ts_mov_b32 s1, 0x42b17218\n\tv_cmp_gt_f32_e64 s6, v1, s1\n\ts_mov_b32 s1, 0x7f800000\n\tv_cndmask_b32_e64 v0, v0, s1, s6\n\ts_mov_b32 s1, 1.0\n\tv_add_f32_e64 v1, v0, s1\n\tv_div_scale_f32 v0, s6, v1, v1, s1\n\tv_rcp_f32_e64 v2, v0\n\ts_waitcnt_depctr 0xfff\n\tv_fma_f32 v3, -v0, v2, s1\n\tv_fmac_f32_e64 v2, v3, v2\n\tv_div_scale_f32 v4, vcc_lo, s1, v1, s1\n\tv_mul_f32_e64 v3, v4, v2\n\tv_fma_f32 v5, -v0, v3, v4\n\tv_fmac_f32_e64 v3, v5, v2\n\tv_fma_f32 v0, -v0, v3, v4\n\tv_div_fmas_f32 v0, v0, v2, v3\n\tv_div_fixup_f32 v2, v0, v1, s1\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b64 v[7:8], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v3, 31, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tv_lshlrev_b64 v[5:6], s0, v[0:1]\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v3, v6\n\tv_add_co_u32 v0, s0, v0, v4\n\tv_add_co_ci_u32_e64 v3, s0, v1, v3, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_store_b32 v[0:1], v2\n.LBB16_2:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v40, off, off offset:88 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v40, 21\n\ts_or_b32 exec_lo, exec_lo, s2\n\tv_readlane_b32 s14, v40, 0\n\tv_readlane_b32 s13, v40, 1\n\tv_readlane_b32 s12, v40, 2\n\tv_readlane_b32 s10, v40, 3\n\tv_readlane_b32 s11, v40, 4\n\tv_readlane_b32 s4, v40, 7\n\tv_readlane_b32 s5, v40, 8\n\tv_readlane_b32 s0, v40, 5\n\tv_readlane_b32 s1, v40, 6\n\tscratch_load_b32 v31, off, off offset:108 ; 4-byte Folded Reload\n\ts_mov_b64 s[6:7], 24\n\ts_mov_b32 s2, s0\n\ts_mov_b32 s0, s1\n\ts_mov_b32 s3, s6\n\ts_mov_b32 s1, s7\n\ts_add_u32 s8, s2, s3\n\ts_addc_u32 s0, s0, s1\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, _Z13__syncthreadsv@rel32@lo+4\n\ts_addc_u32 s1, s1, _Z13__syncthreadsv@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z13sigmoidKernelIfEvPT_S1_i\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 240\n\t\t.amdhsa_kernarg_size 280\n\t\t.amdhsa_user_sgpr_count 13\n\t\t.amdhsa_user_sgpr_dispatch_ptr 1\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 1\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 1\n\t\t.amdhsa_enable_private_segment 1\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 1\n\t\t.amdhsa_system_sgpr_workgroup_id_z 1\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 2\n\t\t.amdhsa_next_free_vgpr 41\n\t\t.amdhsa_next_free_sgpr 34\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.section\t.text._Z13sigmoidKernelIfEvPT_S1_i,\"axG\",@progbits,_Z13sigmoidKernelIfEvPT_S1_i,comdat\n.Lfunc_end16:\n\t.size\t_Z13sigmoidKernelIfEvPT_S1_i, .Lfunc_end16-_Z13sigmoidKernelIfEvPT_S1_i\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 1868\n; NumSgprs: 36\n; NumVgprs: 41\n; ScratchSize: 240\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 4\n; VGPRBlocks: 5\n; NumSGPRsForWavesPerEU: 36\n; NumVGPRsForWavesPerEU: 41\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1\n; COMPUTE_PGM_RSRC2:USER_SGPR: 13\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2\n\t.text\n\t.p2align\t2 ; -- Begin function __ocml_exp_f64\n\t.type\t__ocml_exp_f64,@function\n__ocml_exp_f64: ; @__ocml_exp_f64\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s2, 0x3ff71547\n\ts_mov_b32 s0, 0x652b82fe\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s2\n\tv_mul_f64 v[0:1], v[2:3], s[0:1]\n\tv_rndne_f64_e64 v[4:5], v[0:1]\n\ts_mov_b32 s2, 0xbfe62e42\n\ts_mov_b32 s0, 0xfefa39ef\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s2\n\tv_fma_f64 v[0:1], v[4:5], s[0:1], v[2:3]\n\ts_mov_b32 s2, 0xbc7abc9e\n\ts_mov_b32 s0, 0x3b39803f\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s2\n\tv_fma_f64 v[0:1], v[4:5], s[0:1], v[0:1]\n\ts_mov_b32 s0, 0x3e928af3\n\ts_mov_b32 s2, 0xfca7ab0c\n ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3\n\ts_mov_b32 s3, s0\n\ts_mov_b32 s4, 0x3e5ade15\n\ts_mov_b32 s0, 0x6a5dcb37\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s4\n\tv_fma_f64 v[6:7], v[0:1], s[0:1], s[2:3]\n\ts_mov_b32 s2, 0x3ec71dee\n\ts_mov_b32 s0, 0x623fde64\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s2\n\tv_fma_f64 v[6:7], v[0:1], v[6:7], s[0:1]\n\ts_mov_b32 s2, 0x3efa0199\n\ts_mov_b32 s0, 0x7c89e6b0\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s2\n\tv_fma_f64 v[6:7], v[0:1], v[6:7], s[0:1]\n\ts_mov_b32 s2, 0x3f2a01a0\n\ts_mov_b32 s0, 0x14761f6e\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s2\n\tv_fma_f64 v[6:7], v[0:1], v[6:7], s[0:1]\n\ts_mov_b32 s2, 0x3f56c16c\n\ts_mov_b32 s0, 0x1852b7b0\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s2\n\tv_fma_f64 v[6:7], v[0:1], v[6:7], s[0:1]\n\ts_mov_b32 s2, 0x3f811111\n\ts_mov_b32 s0, 0x11122322\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s2\n\tv_fma_f64 v[6:7], v[0:1], v[6:7], s[0:1]\n\ts_mov_b32 s2, 0x3fa55555\n\ts_mov_b32 s0, 0x555502a1\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s2\n\tv_fma_f64 v[6:7], v[0:1], v[6:7], s[0:1]\n\ts_mov_b32 s2, 0x3fc55555\n\ts_mov_b32 s0, 0x55555511\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s2\n\tv_fma_f64 v[6:7], v[0:1], v[6:7], s[0:1]\n\ts_mov_b32 s2, 0x3fe00000\n\ts_mov_b32 s0, 11\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s2\n\tv_fma_f64 v[6:7], v[0:1], v[6:7], s[0:1]\n\ts_mov_b64 s[0:1], 1.0\n\tv_fma_f64 v[6:7], v[0:1], v[6:7], s[0:1]\n\tv_fma_f64 v[0:1], v[0:1], v[6:7], s[0:1]\n\tv_cvt_i32_f64_e64 v4, v[4:5]\n\tv_ldexp_f64 v[4:5], v[0:1], v4\n\tv_mov_b32_e32 v0, 0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_finite_only_opt@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_finite_only_opt@rel32@hi+12\n\tglobal_load_u8 v0, v0, s[0:1]\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u16_e64 s1, v0, s0\n\ts_mov_b32 s2, 0\n\ts_mov_b32 s3, 0x40900000\n\tv_cmp_gt_f64_e64 s0, v[2:3], s[2:3]\n\ts_and_b32 s1, s0, s1\n\tv_mov_b32_e32 v0, v5\n\ts_mov_b32 s0, 0x7ff00000\n\ts_mov_b32 s2, 0\n ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3\n\ts_mov_b32 s3, s0\n\ts_mov_b32 s0, s3\n\tv_cndmask_b32_e64 v1, v0, s0, s1\n\tv_mov_b32_e32 v0, v4\n\ts_mov_b32 s0, s2\n\tv_cndmask_b32_e64 v0, v0, s0, s1\n\ts_mov_b32 s0, 0\n\ts_mov_b32 s1, 0xc090cc00\n\tv_cmp_lt_f64_e64 s1, v[2:3], s[0:1]\n\ts_mov_b64 s[2:3], 0\n\ts_mov_b32 s0, s2\n\tv_cndmask_b32_e64 v0, v0, s0, s1\n\ts_mov_b32 s0, s3\n\tv_cndmask_b32_e64 v3, v1, s0, s1\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\ts_setpc_b64 s[30:31]\n.Lfunc_end17:\n\t.size\t__ocml_exp_f64, .Lfunc_end17-__ocml_exp_f64\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 600\n; NumSgprs: 32\n; NumVgprs: 8\n; ScratchSize: 0\n; MemoryBound: 0\n\t.section\t.text._Z13sigmoidKernelIdEvPT_S1_i,\"axG\",@progbits,_Z13sigmoidKernelIdEvPT_S1_i,comdat\n\t.protected\t_Z13sigmoidKernelIdEvPT_S1_i ; -- Begin function _Z13sigmoidKernelIdEvPT_S1_i\n\t.globl\t_Z13sigmoidKernelIdEvPT_S1_i\n\t.p2align\t8\n\t.type\t_Z13sigmoidKernelIdEvPT_S1_i,@function\n_Z13sigmoidKernelIdEvPT_S1_i: ; @_Z13sigmoidKernelIdEvPT_S1_i\n; %bb.0:\n\ts_mov_b32 s32, 0x80\n ; implicit-def: $vgpr40 : SGPR spill to VGPR lane\n\tv_writelane_b32 v40, s15, 0\n\ts_mov_b32 s6, s14\n\tv_readlane_b32 s14, v40, 0\n\tv_writelane_b32 v40, s6, 1\n\ts_mov_b32 s12, s13\n\tv_readlane_b32 s13, v40, 1\n\tv_writelane_b32 v40, s12, 2\n\ts_mov_b64 s[10:11], s[4:5]\n\tv_writelane_b32 v40, s10, 3\n\tv_writelane_b32 v40, s11, 4\n\tv_writelane_b32 v40, s2, 5\n\tv_writelane_b32 v40, s3, 6\n\ts_mov_b64 s[4:5], s[0:1]\n\tv_readlane_b32 s0, v40, 5\n\tv_readlane_b32 s1, v40, 6\n\tv_writelane_b32 v40, s4, 7\n\tv_writelane_b32 v40, s5, 8\n\tv_mov_b32_e32 v31, v0\n\tscratch_store_b32 off, v31, off offset:108 ; 4-byte Folded Spill\n\ts_load_b64 s[24:25], s[0:1], 0x0\n\ts_load_b64 s[20:21], s[0:1], 0x8\n\ts_load_b32 s2, s[0:1], 0x10\n\ts_mov_b64 s[6:7], src_private_base\n\ts_mov_b32 s3, 32\n\ts_lshr_b64 s[6:7], s[6:7], s3\n\ts_mov_b32 s3, s6\n\ts_mov_b32 s22, 48\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s3\n\ts_mov_b32 s18, 56\n ; kill: def $sgpr18 killed $sgpr18 def $sgpr18_sgpr19\n\ts_mov_b32 s19, s3\n\ts_mov_b32 s16, 64\n ; kill: def $sgpr16 killed $sgpr16 def $sgpr16_sgpr17\n\ts_mov_b32 s17, s3\n\ts_mov_b64 s[6:7], s[16:17]\n\tv_writelane_b32 v40, s6, 9\n\tv_writelane_b32 v40, s7, 10\n\ts_mov_b32 s8, 0x48\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s3\n\ts_mov_b64 s[6:7], s[8:9]\n\tv_writelane_b32 v40, s6, 11\n\tv_writelane_b32 v40, s7, 12\n\ts_mov_b32 s6, 0x50\n ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7\n\ts_mov_b32 s7, s3\n\tv_writelane_b32 v40, s6, 13\n\tv_writelane_b32 v40, s7, 14\n\ts_mov_b32 s26, 0x54\n ; kill: def $sgpr26 killed $sgpr26 def $sgpr26_sgpr27\n\ts_mov_b32 s27, s3\n\tv_writelane_b32 v40, s26, 15\n\tv_writelane_b32 v40, s27, 16\n\tv_writelane_b32 v40, s26, 17\n\tv_writelane_b32 v40, s27, 18\n\tv_mov_b32_e32 v0, s22\n\tv_mov_b32_e32 v1, s23\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v2, s24\n\tv_mov_b32_e32 v3, s25\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s22\n\tv_mov_b32_e32 v1, s23\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tv_mov_b32_e32 v2, s20\n\tv_mov_b32_e32 v3, s21\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\ts_waitcnt vmcnt(1) lgkmcnt(2)\n\tflat_store_b64 v[0:1], v[4:5]\n\tv_mov_b32_e32 v0, s8\n\tv_mov_b32_e32 v1, s9\n\ts_waitcnt vmcnt(0) lgkmcnt(1)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tv_mov_b32_e32 v2, s2\n\tflat_store_b32 v[0:1], v2\n\ts_mov_b64 s[6:7], 24\n\ts_mov_b32 s2, s0\n\ts_mov_b32 s0, s1\n\ts_mov_b32 s3, s6\n\ts_mov_b32 s1, s7\n\ts_add_u32 s8, s2, s3\n\ts_addc_u32 s0, s0, s1\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s0\n\tv_writelane_b32 v40, s8, 19\n\tv_writelane_b32 v40, s9, 20\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_id@rel32@hi+12\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, off offset:104 ; 4-byte Folded Spill\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:108 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v40, 0\n\tv_readlane_b32 s13, v40, 1\n\tv_readlane_b32 s12, v40, 2\n\tv_readlane_b32 s10, v40, 3\n\tv_readlane_b32 s11, v40, 4\n\tv_readlane_b32 s8, v40, 19\n\tv_readlane_b32 s9, v40, 20\n\tv_readlane_b32 s4, v40, 7\n\tv_readlane_b32 s5, v40, 8\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:104 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:112 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:112 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v1, off offset:96 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_group_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_group_id@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:108 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v40, 0\n\tv_readlane_b32 s13, v40, 1\n\tv_readlane_b32 s12, v40, 2\n\tv_readlane_b32 s10, v40, 3\n\tv_readlane_b32 s11, v40, 4\n\tv_readlane_b32 s8, v40, 19\n\tv_readlane_b32 s9, v40, 20\n\tv_readlane_b32 s4, v40, 7\n\tv_readlane_b32 s5, v40, 8\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:104 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:100 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:100 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v1, off offset:92 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_size@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_size@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v4, off, off offset:96 ; 4-byte Folded Reload\n\tscratch_load_b32 v2, off, off offset:92 ; 4-byte Folded Reload\n\tv_readlane_b32 s2, v40, 15\n\tv_readlane_b32 s3, v40, 16\n\tv_readlane_b32 s0, v40, 13\n\tv_readlane_b32 s1, v40, 14\n\tv_mov_b32_e32 v3, v1\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tv_mov_b32_e32 v3, v0\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr5\n ; implicit-def: $sgpr5\n\tv_mov_b32_e32 v0, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[0:1], s4, v2, v3, v[4:5]\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v2, s1\n\tv_mov_b32_e32 v1, s0\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_lt_i32_e64 s1, v0, v1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v40, s0, 21\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v40, off offset:88 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB18_2\n; %bb.1:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v40, off, off offset:88 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v40, 17\n\tv_readlane_b32 s1, v40, 18\n\tv_readlane_b32 s14, v40, 0\n\tv_readlane_b32 s13, v40, 1\n\tv_readlane_b32 s12, v40, 2\n\tv_readlane_b32 s10, v40, 3\n\tv_readlane_b32 s11, v40, 4\n\tv_readlane_b32 s4, v40, 7\n\tv_readlane_b32 s5, v40, 8\n\tv_readlane_b32 s8, v40, 5\n\tv_readlane_b32 s9, v40, 6\n\tv_readlane_b32 s2, v40, 9\n\tv_readlane_b32 s3, v40, 10\n\tscratch_load_b32 v31, off, off offset:108 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s1\n\tv_mov_b32_e32 v3, s0\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\ts_mov_b32 s0, 3\n\tv_writelane_b32 v40, s0, 22\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v40, off offset:88 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s0, v0, v3\n\tv_add_co_ci_u32_e64 v2, s0, v1, v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[1:2], v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v0, v2\n\ts_mov_b32 s0, 0x80000000\n\tv_xor_b32_e64 v0, s0, v0\n\tv_mov_b32_e32 v2, v1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b64 s[2:3], src_private_base\n\ts_mov_b32 s0, 32\n\ts_lshr_b64 s[2:3], s[2:3], s0\n\ts_mov_b32 s1, s2\n\ts_mov_b32 s2, 16\n ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3\n\ts_mov_b32 s3, s1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b64 s[16:17], 24\n\ts_mov_b32 s7, s8\n\ts_mov_b32 s1, s9\n\ts_mov_b32 s8, s16\n\ts_mov_b32 s6, s17\n\ts_add_u32 s8, s7, s8\n\ts_addc_u32 s1, s1, s6\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[1:2], v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v0, v1\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ocml_exp_f64@rel32@lo+4\n\ts_addc_u32 s1, s1, __ocml_exp_f64@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s4, v40, 11\n\tv_readlane_b32 s5, v40, 12\n\tv_readlane_b32 s2, v40, 17\n\tv_readlane_b32 s3, v40, 18\n\tv_readlane_b32 s0, v40, 22\n\tv_mov_b32_e32 v2, v1\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\ts_mov_b64 s[6:7], 1.0\n\tv_add_f64 v[2:3], v[0:1], s[6:7]\n\tv_div_scale_f64 v[0:1], s1, v[2:3], v[2:3], s[6:7]\n\tv_rcp_f64_e64 v[4:5], v[0:1]\n\ts_waitcnt_depctr 0xfff\n\tv_fma_f64 v[6:7], -v[0:1], v[4:5], s[6:7]\n\tv_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]\n\tv_fma_f64 v[6:7], -v[0:1], v[4:5], s[6:7]\n\tv_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]\n\tv_div_scale_f64 v[8:9], vcc_lo, s[6:7], v[2:3], s[6:7]\n\tv_mul_f64 v[6:7], v[8:9], v[4:5]\n\tv_fma_f64 v[0:1], -v[0:1], v[6:7], v[8:9]\n\tv_div_fmas_f64 v[0:1], v[0:1], v[4:5], v[6:7]\n\tv_div_fixup_f64 v[2:3], v[0:1], v[2:3], s[6:7]\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v4, 31, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_lshlrev_b64 v[6:7], s0, v[0:1]\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v1, v9\n\tv_mov_b32_e32 v4, v7\n\tv_add_co_u32 v0, s0, v0, v5\n\tv_add_co_ci_u32_e64 v4, s0, v1, v4, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_store_b64 v[0:1], v[2:3]\n.LBB18_2:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v40, off, off offset:88 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v40, 21\n\ts_or_b32 exec_lo, exec_lo, s2\n\tv_readlane_b32 s14, v40, 0\n\tv_readlane_b32 s13, v40, 1\n\tv_readlane_b32 s12, v40, 2\n\tv_readlane_b32 s10, v40, 3\n\tv_readlane_b32 s11, v40, 4\n\tv_readlane_b32 s4, v40, 7\n\tv_readlane_b32 s5, v40, 8\n\tv_readlane_b32 s0, v40, 5\n\tv_readlane_b32 s1, v40, 6\n\tscratch_load_b32 v31, off, off offset:108 ; 4-byte Folded Reload\n\ts_mov_b64 s[6:7], 24\n\ts_mov_b32 s2, s0\n\ts_mov_b32 s0, s1\n\ts_mov_b32 s3, s6\n\ts_mov_b32 s1, s7\n\ts_add_u32 s8, s2, s3\n\ts_addc_u32 s0, s0, s1\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, _Z13__syncthreadsv@rel32@lo+4\n\ts_addc_u32 s1, s1, _Z13__syncthreadsv@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z13sigmoidKernelIdEvPT_S1_i\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 240\n\t\t.amdhsa_kernarg_size 280\n\t\t.amdhsa_user_sgpr_count 13\n\t\t.amdhsa_user_sgpr_dispatch_ptr 1\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 1\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 1\n\t\t.amdhsa_enable_private_segment 1\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 1\n\t\t.amdhsa_system_sgpr_workgroup_id_z 1\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 2\n\t\t.amdhsa_next_free_vgpr 41\n\t\t.amdhsa_next_free_sgpr 34\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.section\t.text._Z13sigmoidKernelIdEvPT_S1_i,\"axG\",@progbits,_Z13sigmoidKernelIdEvPT_S1_i,comdat\n.Lfunc_end18:\n\t.size\t_Z13sigmoidKernelIdEvPT_S1_i, .Lfunc_end18-_Z13sigmoidKernelIdEvPT_S1_i\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 1888\n; NumSgprs: 36\n; NumVgprs: 41\n; ScratchSize: 240\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 4\n; VGPRBlocks: 5\n; NumSGPRsForWavesPerEU: 36\n; NumVGPRsForWavesPerEU: 41\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1\n; COMPUTE_PGM_RSRC2:USER_SGPR: 13\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__const.__assert_fail.fmt,@object ; @__const.__assert_fail.fmt\n\t.section\t.rodata.str1.16,\"aMS\",@progbits,1\n\t.p2align\t4, 0x0\n__const.__assert_fail.fmt:\n\t.asciz\t\"%s:%u: %s: Device-side assertion `%s' failed.\\n\"\n\t.size\t__const.__assert_fail.fmt, 47\n\n\t.protected\tthreadIdx\n\t.protected\tblockIdx\n\t.protected\tblockDim\n\t.type\t.str,@object ; @.str\n\t.section\t.rodata.str1.1,\"aMS\",@progbits,1\n.str:\n\t.asciz\t\"workgroup\"\n\t.size\t.str, 10\n\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.type\t__oclc_finite_only_opt,@object ; @__oclc_finite_only_opt\n\t.section\t.rodata,\"a\",@progbits\n__oclc_finite_only_opt:\n\t.byte\t0 ; 0x0\n\t.size\t__oclc_finite_only_opt, 1\n\n\t.hidden\t__oclc_ABI_version ; @__oclc_ABI_version\n\t.type\t__oclc_ABI_version,@object\n\t.weak\t__oclc_ABI_version\n\t.p2align\t2, 0x0\n__oclc_ABI_version:\n\t.long\t500 ; 0x1f4\n\t.size\t__oclc_ABI_version, 4\n\n\t.weak\tthreadIdx\n\t.weak\tblockIdx\n\t.weak\tblockDim\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .offset: 16\n .size: 4\n .value_kind: by_value\n - .offset: 24\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 28\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 32\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 36\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 38\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 40\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 42\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 44\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 46\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 64\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 72\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 80\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 88\n .size: 2\n .value_kind: hidden_grid_dims\n - .offset: 104\n .size: 8\n .value_kind: hidden_hostcall_buffer\n - .offset: 112\n .size: 8\n .value_kind: hidden_multigrid_sync_arg\n - .offset: 120\n .size: 8\n .value_kind: hidden_heap_v1\n - .offset: 128\n .size: 8\n .value_kind: hidden_default_queue\n - .offset: 224\n .size: 8\n .value_kind: hidden_queue_ptr\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 280\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z13sigmoidKernelIfEvPT_S1_i\n .private_segment_fixed_size: 240\n .sgpr_count: 36\n .sgpr_spill_count: 22\n .symbol: _Z13sigmoidKernelIfEvPT_S1_i.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: true\n .vgpr_count: 41\n .vgpr_spill_count: 7\n .wavefront_size: 32\n .workgroup_processor_mode: 1\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .offset: 16\n .size: 4\n .value_kind: by_value\n - .offset: 24\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 28\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 32\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 36\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 38\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 40\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 42\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 44\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 46\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 64\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 72\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 80\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 88\n .size: 2\n .value_kind: hidden_grid_dims\n - .offset: 104\n .size: 8\n .value_kind: hidden_hostcall_buffer\n - .offset: 112\n .size: 8\n .value_kind: hidden_multigrid_sync_arg\n - .offset: 120\n .size: 8\n .value_kind: hidden_heap_v1\n - .offset: 128\n .size: 8\n .value_kind: hidden_default_queue\n - .offset: 224\n .size: 8\n .value_kind: hidden_queue_ptr\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 280\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z13sigmoidKernelIdEvPT_S1_i\n .private_segment_fixed_size: 240\n .sgpr_count: 36\n .sgpr_spill_count: 23\n .symbol: _Z13sigmoidKernelIdEvPT_S1_i.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: true\n .vgpr_count: 41\n .vgpr_spill_count: 8\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162572,"cells":{"id":{"kind":"string","value":"b7dfd71e41a9af786312078168759f2258d87a2f_O1"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z22redBlackTreeOperationsP4Node --------------------------\n .section .text._Z22redBlackTreeOperationsP4Node,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=8\"\n .align 128\n\n\n\n\n .global _Z22redBlackTreeOperationsP4Node\n .type _Z22redBlackTreeOperationsP4Node,@function\n .size _Z22redBlackTreeOperationsP4Node,(.L_x_2 - _Z22redBlackTreeOperationsP4Node)\n .other _Z22redBlackTreeOperationsP4Node,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z22redBlackTreeOperationsP4Node:\n.text._Z22redBlackTreeOperationsP4Node:\n /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;\n /*0010*/ S2R R2, SR_CTAID.X ;\n /*0020*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*0030*/ S2R R3, SR_TID.X ;\n /*0040*/ IMAD R2, R2, c[0x0][0x0], R3 ;\n /*0050*/ LOP3.LUT R0, R2, 0x1, RZ, 0xc0, !PT ;\n /*0060*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ;\n /*0070*/ ISETP.GT.OR P0, PT, R2, 0x1f, !P0 ;\n /*0080*/ @P0 EXIT ;\n /*0090*/ IMAD.MOV.U32 R3, RZ, RZ, 0x14 ;\n /*00a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;\n /*00b0*/ LDG.E R0, [R2.64+0x4] ;\n /*00c0*/ IADD3 R5, -R0, 0x1, RZ ;\n /*00d0*/ STG.E [R2.64+0x4], R5 ;\n /*00e0*/ EXIT ;\n.L_x_0:\n /*00f0*/ BRA `(.L_x_0);\n /*0100*/ NOP;\n /*0110*/ NOP;\n /*0120*/ NOP;\n /*0130*/ NOP;\n /*0140*/ NOP;\n /*0150*/ NOP;\n /*0160*/ NOP;\n /*0170*/ NOP;\n.L_x_2:\n\n\n//--------------------- .text._Z15initializeNodesP4Node --------------------------\n .section .text._Z15initializeNodesP4Node,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=10\"\n .align 128\n\n\n\n\n .global _Z15initializeNodesP4Node\n .type _Z15initializeNodesP4Node,@function\n .size _Z15initializeNodesP4Node,(.L_x_3 - _Z15initializeNodesP4Node)\n .other _Z15initializeNodesP4Node,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z15initializeNodesP4Node:\n.text._Z15initializeNodesP4Node:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ S2R R5, SR_CTAID.X ;\n /*0020*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*0030*/ S2R R0, SR_TID.X ;\n /*0040*/ IMAD R5, R5, c[0x0][0x0], R0 ;\n /*0050*/ ISETP.GT.AND P0, PT, R5, 0x1f, PT ;\n /*0060*/ @P0 EXIT ;\n /*0070*/ MOV R2, 0x14 ;\n /*0080*/ MOV R7, 0xffffffff ;\n /*0090*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ;\n /*00a0*/ STG.E [R2.64], R5 ;\n /*00b0*/ STG.E [R2.64+0x4], RZ ;\n /*00c0*/ STG.E [R2.64+0x8], R7 ;\n /*00d0*/ STG.E [R2.64+0xc], R7 ;\n /*00e0*/ STG.E [R2.64+0x10], R7 ;\n /*00f0*/ EXIT ;\n.L_x_1:\n /*0100*/ BRA `(.L_x_1);\n /*0110*/ NOP;\n /*0120*/ NOP;\n /*0130*/ NOP;\n /*0140*/ NOP;\n /*0150*/ NOP;\n /*0160*/ NOP;\n /*0170*/ NOP;\n /*0180*/ NOP;\n /*0190*/ NOP;\n /*01a0*/ NOP;\n /*01b0*/ NOP;\n /*01c0*/ NOP;\n /*01d0*/ NOP;\n /*01e0*/ NOP;\n /*01f0*/ NOP;\n.L_x_3:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.protected\t_Z15initializeNodesP4Node ; -- Begin function _Z15initializeNodesP4Node\n\t.globl\t_Z15initializeNodesP4Node\n\t.p2align\t8\n\t.type\t_Z15initializeNodesP4Node,@function\n_Z15initializeNodesP4Node: ; @_Z15initializeNodesP4Node\n; %bb.0:\n\ts_load_b32 s2, s[0:1], 0x14\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s2, s2, 0xffff\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]\n\ts_mov_b32 s2, exec_lo\n\tv_cmpx_gt_i32_e32 32, v1\n\ts_cbranch_execz .LBB0_2\n; %bb.1:\n\ts_load_b64 s[0:1], s[0:1], 0x0\n\tv_dual_mov_b32 v3, -1 :: v_dual_mov_b32 v2, 0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_mov_b32_e32 v4, v3\n\tv_mov_b32_e32 v5, v3\n\ts_waitcnt lgkmcnt(0)\n\tv_mad_i64_i32 v[6:7], null, v1, 20, s[0:1]\n\ts_clause 0x1\n\tglobal_store_b32 v[6:7], v1, off\n\tglobal_store_b128 v[6:7], v[2:5], off offset:4\n.LBB0_2:\n\ts_nop 0\n\ts_sendmsg sendmsg(MSG_DEALLOC_VGPRS)\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z15initializeNodesP4Node\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 264\n\t\t.amdhsa_user_sgpr_count 15\n\t\t.amdhsa_user_sgpr_dispatch_ptr 0\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 0\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 0\n\t\t.amdhsa_next_free_vgpr 8\n\t\t.amdhsa_next_free_sgpr 16\n\t\t.amdhsa_reserve_vcc 0\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end0:\n\t.size\t_Z15initializeNodesP4Node, .Lfunc_end0-_Z15initializeNodesP4Node\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 116\n; NumSgprs: 16\n; NumVgprs: 8\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 1\n; VGPRBlocks: 0\n; NumSGPRsForWavesPerEU: 16\n; NumVGPRsForWavesPerEU: 8\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 15\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0\n\t.text\n\t.protected\t_Z22redBlackTreeOperationsP4Node ; -- Begin function _Z22redBlackTreeOperationsP4Node\n\t.globl\t_Z22redBlackTreeOperationsP4Node\n\t.p2align\t8\n\t.type\t_Z22redBlackTreeOperationsP4Node,@function\n_Z22redBlackTreeOperationsP4Node: ; @_Z22redBlackTreeOperationsP4Node\n; %bb.0:\n\ts_load_b32 s2, s[0:1], 0x14\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s2, s2, 0xffff\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]\n\tv_and_b32_e32 v0, 1, v1\n\tv_cmp_gt_i32_e32 vcc_lo, 32, v1\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u32_e64 s2, 0, v0\n\ts_and_b32 s2, vcc_lo, s2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_saveexec_b32 s3, s2\n\ts_cbranch_execz .LBB1_2\n; %bb.1:\n\ts_load_b64 s[0:1], s[0:1], 0x0\n\ts_waitcnt lgkmcnt(0)\n\tv_mad_i64_i32 v[2:3], null, v1, 20, s[0:1]\n\tglobal_load_b32 v0, v[2:3], off offset:4\n\ts_waitcnt vmcnt(0)\n\tv_sub_nc_u32_e32 v0, 1, v0\n\tglobal_store_b32 v[2:3], v0, off offset:4\n.LBB1_2:\n\ts_nop 0\n\ts_sendmsg sendmsg(MSG_DEALLOC_VGPRS)\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z22redBlackTreeOperationsP4Node\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 264\n\t\t.amdhsa_user_sgpr_count 15\n\t\t.amdhsa_user_sgpr_dispatch_ptr 0\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 0\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 0\n\t\t.amdhsa_next_free_vgpr 4\n\t\t.amdhsa_next_free_sgpr 16\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end1:\n\t.size\t_Z22redBlackTreeOperationsP4Node, .Lfunc_end1-_Z22redBlackTreeOperationsP4Node\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 124\n; NumSgprs: 18\n; NumVgprs: 4\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 2\n; VGPRBlocks: 0\n; NumSGPRsForWavesPerEU: 18\n; NumVGPRsForWavesPerEU: 4\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 15\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .offset: 8\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 12\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 16\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 20\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 22\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 24\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 26\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 28\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 30\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 48\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 56\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 64\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 72\n .size: 2\n .value_kind: hidden_grid_dims\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 264\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z15initializeNodesP4Node\n .private_segment_fixed_size: 0\n .sgpr_count: 16\n .sgpr_spill_count: 0\n .symbol: _Z15initializeNodesP4Node.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 8\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .offset: 8\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 12\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 16\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 20\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 22\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 24\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 26\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 28\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 30\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 48\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 56\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 64\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 72\n .size: 2\n .value_kind: hidden_grid_dims\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 264\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z22redBlackTreeOperationsP4Node\n .private_segment_fixed_size: 0\n .sgpr_count: 18\n .sgpr_spill_count: 0\n .symbol: _Z22redBlackTreeOperationsP4Node.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 4\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162573,"cells":{"id":{"kind":"string","value":"1837d1242fe55e3df3a94c35ece42e25d5a2400e_O1"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z3muliPfS_ --------------------------\n .section .text._Z3muliPfS_,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=22\"\n .align 128\n\n\n\n\n .global _Z3muliPfS_\n .type _Z3muliPfS_,@function\n .size _Z3muliPfS_,(.L_x_10 - _Z3muliPfS_)\n .other _Z3muliPfS_,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z3muliPfS_:\n.text._Z3muliPfS_:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ S2R R3, SR_CTAID.X ;\n /*0020*/ S2R R0, SR_TID.X ;\n /*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ;\n /*0040*/ MOV R0, c[0x0][0x0] ;\n /*0050*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ;\n /*0060*/ IMAD R0, R0, c[0x0][0xc], RZ ;\n /*0070*/ @P0 EXIT ;\n /*0080*/ I2F.U32.RP R6, R0 ;\n /*0090*/ IADD3 R7, RZ, -R0, RZ ;\n /*00a0*/ IMAD.IADD R2, R0.reuse, 0x1, R3 ;\n /*00b0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ;\n /*00c0*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*00d0*/ BSSY B0, `(.L_x_0) ;\n /*00e0*/ MUFU.RCP R6, R6 ;\n /*00f0*/ IADD3 R4, R6, 0xffffffe, RZ ;\n /*0100*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ;\n /*0110*/ MOV R4, RZ ;\n /*0120*/ IMAD R7, R7, R5, RZ ;\n /*0130*/ IMAD.HI.U32 R8, R5, R7, R4 ;\n /*0140*/ LOP3.LUT R5, RZ, R2, RZ, 0x33, !PT ;\n /*0150*/ IADD3 R5, R5, c[0x0][0x160], R0 ;\n /*0160*/ IMAD.HI.U32 R8, R8, R5, RZ ;\n /*0170*/ IADD3 R2, -R8, RZ, RZ ;\n /*0180*/ IMAD R5, R0, R2, R5 ;\n /*0190*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ;\n /*01a0*/ @P0 IADD3 R5, -R0, R5, RZ ;\n /*01b0*/ @P0 IADD3 R8, R8, 0x1, RZ ;\n /*01c0*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ;\n /*01d0*/ @P1 IADD3 R8, R8, 0x1, RZ ;\n /*01e0*/ @!P2 LOP3.LUT R8, RZ, R0, RZ, 0x33, !PT ;\n /*01f0*/ IADD3 R2, R8, 0x1, RZ ;\n /*0200*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ;\n /*0210*/ @!P0 BRA `(.L_x_1) ;\n /*0220*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ;\n /*0230*/ IMAD.WIDE R4, R3, R6, c[0x0][0x170] ;\n /*0240*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ;\n.L_x_2:\n /*0250*/ LDG.E R9, [R4.64] ;\n /*0260*/ LDG.E R10, [R6.64] ;\n /*0270*/ IADD3 R2, R2, -0x1, RZ ;\n /*0280*/ IADD3 R3, R0, R3, RZ ;\n /*0290*/ ISETP.NE.AND P0, PT, R2, RZ, PT ;\n /*02a0*/ IMAD.WIDE R6, R0, 0x4, R6 ;\n /*02b0*/ FMUL R9, R9, R10 ;\n /*02c0*/ STG.E [R4.64], R9 ;\n /*02d0*/ IMAD.WIDE R4, R0, 0x4, R4 ;\n /*02e0*/ @P0 BRA `(.L_x_2) ;\n.L_x_1:\n /*02f0*/ BSYNC B0 ;\n.L_x_0:\n /*0300*/ ISETP.GE.U32.AND P0, PT, R8, 0x3, PT ;\n /*0310*/ @!P0 EXIT ;\n.L_x_3:\n /*0320*/ MOV R4, 0x4 ;\n /*0330*/ IMAD.WIDE R6, R3, R4, c[0x0][0x170] ;\n /*0340*/ IMAD.WIDE R4, R3, R4, c[0x0][0x168] ;\n /*0350*/ LDG.E R2, [R6.64] ;\n /*0360*/ LDG.E R9, [R4.64] ;\n /*0370*/ IMAD.WIDE R10, R0, 0x4, R6 ;\n /*0380*/ FMUL R17, R2, R9 ;\n /*0390*/ IMAD.WIDE R8, R0.reuse, 0x4, R4 ;\n /*03a0*/ STG.E [R6.64], R17 ;\n /*03b0*/ LDG.E R2, [R10.64] ;\n /*03c0*/ LDG.E R13, [R8.64] ;\n /*03d0*/ IMAD.WIDE R14, R0, 0x4, R10 ;\n /*03e0*/ FMUL R19, R2, R13 ;\n /*03f0*/ IMAD.WIDE R12, R0.reuse, 0x4, R8 ;\n /*0400*/ STG.E [R10.64], R19 ;\n /*0410*/ LDG.E R2, [R14.64] ;\n /*0420*/ LDG.E R5, [R12.64] ;\n /*0430*/ IMAD.WIDE R6, R0, 0x4, R14 ;\n /*0440*/ FMUL R17, R2, R5 ;\n /*0450*/ IMAD.WIDE R4, R0.reuse, 0x4, R12 ;\n /*0460*/ STG.E [R14.64], R17 ;\n /*0470*/ LDG.E R5, [R4.64] ;\n /*0480*/ LDG.E R2, [R6.64] ;\n /*0490*/ IADD3 R3, R0, R3, R0 ;\n /*04a0*/ IADD3 R3, R0, R3, R0 ;\n /*04b0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ;\n /*04c0*/ FMUL R9, R2, R5 ;\n /*04d0*/ STG.E [R6.64], R9 ;\n /*04e0*/ @!P0 BRA `(.L_x_3) ;\n /*04f0*/ EXIT ;\n.L_x_4:\n /*0500*/ BRA `(.L_x_4);\n /*0510*/ NOP;\n /*0520*/ NOP;\n /*0530*/ NOP;\n /*0540*/ NOP;\n /*0550*/ NOP;\n /*0560*/ NOP;\n /*0570*/ NOP;\n /*0580*/ NOP;\n /*0590*/ NOP;\n /*05a0*/ NOP;\n /*05b0*/ NOP;\n /*05c0*/ NOP;\n /*05d0*/ NOP;\n /*05e0*/ NOP;\n /*05f0*/ NOP;\n.L_x_10:\n\n\n//--------------------- .text._Z3addiPfS_ --------------------------\n .section .text._Z3addiPfS_,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=22\"\n .align 128\n\n\n\n\n .global _Z3addiPfS_\n .type _Z3addiPfS_,@function\n .size _Z3addiPfS_,(.L_x_11 - _Z3addiPfS_)\n .other _Z3addiPfS_,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z3addiPfS_:\n.text._Z3addiPfS_:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ S2R R3, SR_CTAID.X ;\n /*0020*/ S2R R0, SR_TID.X ;\n /*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ;\n /*0040*/ MOV R0, c[0x0][0x0] ;\n /*0050*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ;\n /*0060*/ IMAD R0, R0, c[0x0][0xc], RZ ;\n /*0070*/ @P0 EXIT ;\n /*0080*/ I2F.U32.RP R6, R0 ;\n /*0090*/ IADD3 R7, RZ, -R0, RZ ;\n /*00a0*/ IMAD.IADD R2, R0.reuse, 0x1, R3 ;\n /*00b0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ;\n /*00c0*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*00d0*/ BSSY B0, `(.L_x_5) ;\n /*00e0*/ MUFU.RCP R6, R6 ;\n /*00f0*/ IADD3 R4, R6, 0xffffffe, RZ ;\n /*0100*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ;\n /*0110*/ MOV R4, RZ ;\n /*0120*/ IMAD R7, R7, R5, RZ ;\n /*0130*/ IMAD.HI.U32 R8, R5, R7, R4 ;\n /*0140*/ LOP3.LUT R5, RZ, R2, RZ, 0x33, !PT ;\n /*0150*/ IADD3 R5, R5, c[0x0][0x160], R0 ;\n /*0160*/ IMAD.HI.U32 R8, R8, R5, RZ ;\n /*0170*/ IADD3 R2, -R8, RZ, RZ ;\n /*0180*/ IMAD R5, R0, R2, R5 ;\n /*0190*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ;\n /*01a0*/ @P0 IADD3 R5, -R0, R5, RZ ;\n /*01b0*/ @P0 IADD3 R8, R8, 0x1, RZ ;\n /*01c0*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ;\n /*01d0*/ @P1 IADD3 R8, R8, 0x1, RZ ;\n /*01e0*/ @!P2 LOP3.LUT R8, RZ, R0, RZ, 0x33, !PT ;\n /*01f0*/ IADD3 R2, R8, 0x1, RZ ;\n /*0200*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ;\n /*0210*/ @!P0 BRA `(.L_x_6) ;\n /*0220*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ;\n /*0230*/ IMAD.WIDE R4, R3, R6, c[0x0][0x170] ;\n /*0240*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ;\n.L_x_7:\n /*0250*/ LDG.E R9, [R4.64] ;\n /*0260*/ LDG.E R10, [R6.64] ;\n /*0270*/ IADD3 R2, R2, -0x1, RZ ;\n /*0280*/ IADD3 R3, R0, R3, RZ ;\n /*0290*/ ISETP.NE.AND P0, PT, R2, RZ, PT ;\n /*02a0*/ IMAD.WIDE R6, R0, 0x4, R6 ;\n /*02b0*/ FADD R9, R9, R10 ;\n /*02c0*/ STG.E [R4.64], R9 ;\n /*02d0*/ IMAD.WIDE R4, R0, 0x4, R4 ;\n /*02e0*/ @P0 BRA `(.L_x_7) ;\n.L_x_6:\n /*02f0*/ BSYNC B0 ;\n.L_x_5:\n /*0300*/ ISETP.GE.U32.AND P0, PT, R8, 0x3, PT ;\n /*0310*/ @!P0 EXIT ;\n.L_x_8:\n /*0320*/ MOV R4, 0x4 ;\n /*0330*/ IMAD.WIDE R6, R3, R4, c[0x0][0x170] ;\n /*0340*/ IMAD.WIDE R4, R3, R4, c[0x0][0x168] ;\n /*0350*/ LDG.E R2, [R6.64] ;\n /*0360*/ LDG.E R9, [R4.64] ;\n /*0370*/ IMAD.WIDE R10, R0, 0x4, R6 ;\n /*0380*/ FADD R17, R2, R9 ;\n /*0390*/ IMAD.WIDE R8, R0.reuse, 0x4, R4 ;\n /*03a0*/ STG.E [R6.64], R17 ;\n /*03b0*/ LDG.E R2, [R10.64] ;\n /*03c0*/ LDG.E R13, [R8.64] ;\n /*03d0*/ IMAD.WIDE R14, R0, 0x4, R10 ;\n /*03e0*/ FADD R19, R2, R13 ;\n /*03f0*/ IMAD.WIDE R12, R0.reuse, 0x4, R8 ;\n /*0400*/ STG.E [R10.64], R19 ;\n /*0410*/ LDG.E R2, [R14.64] ;\n /*0420*/ LDG.E R5, [R12.64] ;\n /*0430*/ IMAD.WIDE R6, R0, 0x4, R14 ;\n /*0440*/ FADD R17, R2, R5 ;\n /*0450*/ IMAD.WIDE R4, R0.reuse, 0x4, R12 ;\n /*0460*/ STG.E [R14.64], R17 ;\n /*0470*/ LDG.E R5, [R4.64] ;\n /*0480*/ LDG.E R2, [R6.64] ;\n /*0490*/ IADD3 R3, R0, R3, R0 ;\n /*04a0*/ IADD3 R3, R0, R3, R0 ;\n /*04b0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ;\n /*04c0*/ FADD R9, R2, R5 ;\n /*04d0*/ STG.E [R6.64], R9 ;\n /*04e0*/ @!P0 BRA `(.L_x_8) ;\n /*04f0*/ EXIT ;\n.L_x_9:\n /*0500*/ BRA `(.L_x_9);\n /*0510*/ NOP;\n /*0520*/ NOP;\n /*0530*/ NOP;\n /*0540*/ NOP;\n /*0550*/ NOP;\n /*0560*/ NOP;\n /*0570*/ NOP;\n /*0580*/ NOP;\n /*0590*/ NOP;\n /*05a0*/ NOP;\n /*05b0*/ NOP;\n /*05c0*/ NOP;\n /*05d0*/ NOP;\n /*05e0*/ NOP;\n /*05f0*/ NOP;\n.L_x_11:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.protected\t_Z3addiPfS_ ; -- Begin function _Z3addiPfS_\n\t.globl\t_Z3addiPfS_\n\t.p2align\t8\n\t.type\t_Z3addiPfS_,@function\n_Z3addiPfS_: ; @_Z3addiPfS_\n; %bb.0:\n\ts_clause 0x1\n\ts_load_b32 s4, s[0:1], 0x24\n\ts_load_b32 s10, s[0:1], 0x0\n\ts_add_u32 s2, s0, 24\n\ts_addc_u32 s3, s1, 0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s8, s4, 0xffff\n\ts_mov_b32 s4, exec_lo\n\tv_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_gt_i32_e64 s10, v1\n\ts_cbranch_execz .LBB0_3\n; %bb.1:\n\ts_load_b32 s2, s[2:3], 0x0\n\ts_load_b128 s[4:7], s[0:1], 0x8\n\tv_ashrrev_i32_e32 v2, 31, v1\n\ts_mov_b32 s1, 0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)\n\tv_lshlrev_b64 v[2:3], 2, v[1:2]\n\ts_waitcnt lgkmcnt(0)\n\ts_mul_i32 s2, s2, s8\n\ts_ashr_i32 s3, s2, 31\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_lshl_b64 s[8:9], s[2:3], 2\n\t.p2align\t6\n.LBB0_2: ; =>This Inner Loop Header: Depth=1\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_co_u32 v4, vcc_lo, s4, v2\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo\n\tv_add_co_u32 v6, vcc_lo, s6, v2\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo\n\tv_add_co_u32 v2, vcc_lo, v2, s8\n\tglobal_load_b32 v0, v[4:5], off\n\tglobal_load_b32 v4, v[6:7], off\n\tv_add_nc_u32_e32 v1, s2, v1\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo\n\ts_waitcnt vmcnt(0)\n\tv_add_f32_e32 v0, v0, v4\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)\n\tv_cmp_le_i32_e64 s0, s10, v1\n\tglobal_store_b32 v[6:7], v0, off\n\ts_or_b32 s1, s0, s1\n\ts_and_not1_b32 exec_lo, exec_lo, s1\n\ts_cbranch_execnz .LBB0_2\n.LBB0_3:\n\ts_nop 0\n\ts_sendmsg sendmsg(MSG_DEALLOC_VGPRS)\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z3addiPfS_\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 280\n\t\t.amdhsa_user_sgpr_count 15\n\t\t.amdhsa_user_sgpr_dispatch_ptr 0\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 0\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 0\n\t\t.amdhsa_next_free_vgpr 8\n\t\t.amdhsa_next_free_sgpr 16\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end0:\n\t.size\t_Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 236\n; NumSgprs: 18\n; NumVgprs: 8\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 2\n; VGPRBlocks: 0\n; NumSGPRsForWavesPerEU: 18\n; NumVGPRsForWavesPerEU: 8\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 15\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0\n\t.text\n\t.protected\t_Z3muliPfS_ ; -- Begin function _Z3muliPfS_\n\t.globl\t_Z3muliPfS_\n\t.p2align\t8\n\t.type\t_Z3muliPfS_,@function\n_Z3muliPfS_: ; @_Z3muliPfS_\n; %bb.0:\n\ts_clause 0x1\n\ts_load_b32 s4, s[0:1], 0x24\n\ts_load_b32 s10, s[0:1], 0x0\n\ts_add_u32 s2, s0, 24\n\ts_addc_u32 s3, s1, 0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s8, s4, 0xffff\n\ts_mov_b32 s4, exec_lo\n\tv_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_gt_i32_e64 s10, v1\n\ts_cbranch_execz .LBB1_3\n; %bb.1:\n\ts_load_b32 s2, s[2:3], 0x0\n\ts_load_b128 s[4:7], s[0:1], 0x8\n\tv_ashrrev_i32_e32 v2, 31, v1\n\ts_mov_b32 s1, 0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)\n\tv_lshlrev_b64 v[2:3], 2, v[1:2]\n\ts_waitcnt lgkmcnt(0)\n\ts_mul_i32 s2, s2, s8\n\ts_ashr_i32 s3, s2, 31\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_lshl_b64 s[8:9], s[2:3], 2\n\t.p2align\t6\n.LBB1_2: ; =>This Inner Loop Header: Depth=1\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_co_u32 v4, vcc_lo, s4, v2\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo\n\tv_add_co_u32 v6, vcc_lo, s6, v2\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo\n\tv_add_co_u32 v2, vcc_lo, v2, s8\n\tglobal_load_b32 v0, v[4:5], off\n\tglobal_load_b32 v4, v[6:7], off\n\tv_add_nc_u32_e32 v1, s2, v1\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo\n\ts_waitcnt vmcnt(0)\n\tv_mul_f32_e32 v0, v0, v4\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)\n\tv_cmp_le_i32_e64 s0, s10, v1\n\tglobal_store_b32 v[6:7], v0, off\n\ts_or_b32 s1, s0, s1\n\ts_and_not1_b32 exec_lo, exec_lo, s1\n\ts_cbranch_execnz .LBB1_2\n.LBB1_3:\n\ts_nop 0\n\ts_sendmsg sendmsg(MSG_DEALLOC_VGPRS)\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z3muliPfS_\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 280\n\t\t.amdhsa_user_sgpr_count 15\n\t\t.amdhsa_user_sgpr_dispatch_ptr 0\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 0\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 0\n\t\t.amdhsa_next_free_vgpr 8\n\t\t.amdhsa_next_free_sgpr 16\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end1:\n\t.size\t_Z3muliPfS_, .Lfunc_end1-_Z3muliPfS_\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 236\n; NumSgprs: 18\n; NumVgprs: 8\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 2\n; VGPRBlocks: 0\n; NumSGPRsForWavesPerEU: 18\n; NumVGPRsForWavesPerEU: 8\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 15\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .offset: 0\n .size: 4\n .value_kind: by_value\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 16\n .size: 8\n .value_kind: global_buffer\n - .offset: 24\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 28\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 32\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 36\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 38\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 40\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 42\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 44\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 46\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 64\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 72\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 80\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 88\n .size: 2\n .value_kind: hidden_grid_dims\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 280\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z3addiPfS_\n .private_segment_fixed_size: 0\n .sgpr_count: 18\n .sgpr_spill_count: 0\n .symbol: _Z3addiPfS_.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 8\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\n - .args:\n - .offset: 0\n .size: 4\n .value_kind: by_value\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 16\n .size: 8\n .value_kind: global_buffer\n - .offset: 24\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 28\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 32\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 36\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 38\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 40\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 42\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 44\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 46\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 64\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 72\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 80\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 88\n .size: 2\n .value_kind: hidden_grid_dims\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 280\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z3muliPfS_\n .private_segment_fixed_size: 0\n .sgpr_count: 18\n .sgpr_spill_count: 0\n .symbol: _Z3muliPfS_.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 8\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162574,"cells":{"id":{"kind":"string","value":"4469afdad3ac6207bf347134ba64a496d6099f67_O0"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z7computefiffPfS_fffffffffffffffffff --------------------------\n .section .text._Z7computefiffPfS_fffffffffffffffffff,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=51\"\n .align 128\n\n\n\n\n .global _Z7computefiffPfS_fffffffffffffffffff\n .type _Z7computefiffPfS_fffffffffffffffffff,@function\n .size _Z7computefiffPfS_fffffffffffffffffff,(.L_x_103 - _Z7computefiffPfS_fffffffffffffffffff)\n .other _Z7computefiffPfS_fffffffffffffffffff,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z7computefiffPfS_fffffffffffffffffff:\n.text._Z7computefiffPfS_fffffffffffffffffff:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ IADD3 R1, R1, -0x28, RZ ;\n /*0020*/ S2R R0, SR_LMEMHIOFF ;\n /*0030*/ ISETP.GE.U32.AND P0, PT, R1, R0, PT ;\n /*0040*/ @P0 BRA `(.L_x_0) ;\n /*0050*/ BPT.TRAP 0x1 ;\n.L_x_0:\n /*0060*/ MOV R30, c[0x0][0x118] ;\n /*0070*/ MOV R31, c[0x0][0x11c] ;\n /*0080*/ IADD3 R0, R1, RZ, RZ ;\n /*0090*/ MOV R0, R0 ;\n /*00a0*/ MOV R2, R0 ;\n /*00b0*/ MOV R3, RZ ;\n /*00c0*/ MOV R0, R2 ;\n /*00d0*/ MOV R2, R3 ;\n /*00e0*/ MOV R0, R0 ;\n /*00f0*/ MOV R2, R2 ;\n /*0100*/ MOV R6, c[0x0][0x20] ;\n /*0110*/ MOV R7, c[0x0][0x24] ;\n /*0120*/ IADD3 R6, P0, R0, R6, RZ ;\n /*0130*/ IADD3.X R7, R2, R7, RZ, P0, !PT ;\n /*0140*/ MOV R3, 0x4 ;\n /*0150*/ LDC R3, c[0x0][R3+0x160] ;\n /*0160*/ MOV R32, R3 ;\n /*0170*/ MOV R3, 0x8 ;\n /*0180*/ LDC R3, c[0x0][R3+0x160] ;\n /*0190*/ MOV R29, R3 ;\n /*01a0*/ MOV R3, 0xc ;\n /*01b0*/ LDC R3, c[0x0][R3+0x160] ;\n /*01c0*/ MOV R25, R3 ;\n /*01d0*/ MOV R4, 0x10 ;\n /*01e0*/ LDC.64 R4, c[0x0][R4+0x160] ;\n /*01f0*/ MOV R20, R4 ;\n /*0200*/ MOV R21, R5 ;\n /*0210*/ MOV R20, R20 ;\n /*0220*/ MOV R21, R21 ;\n /*0230*/ MOV R4, 0x18 ;\n /*0240*/ LDC.64 R4, c[0x0][R4+0x160] ;\n /*0250*/ MOV R18, R4 ;\n /*0260*/ MOV R19, R5 ;\n /*0270*/ MOV R18, R18 ;\n /*0280*/ MOV R19, R19 ;\n /*0290*/ MOV R3, 0x20 ;\n /*02a0*/ LDC R3, c[0x0][R3+0x160] ;\n /*02b0*/ MOV R28, R3 ;\n /*02c0*/ MOV R3, 0x24 ;\n /*02d0*/ LDC R3, c[0x0][R3+0x160] ;\n /*02e0*/ MOV R35, R3 ;\n /*02f0*/ MOV R3, 0x28 ;\n /*0300*/ LDC R3, c[0x0][R3+0x160] ;\n /*0310*/ MOV R37, R3 ;\n /*0320*/ MOV R3, 0x2c ;\n /*0330*/ LDC R3, c[0x0][R3+0x160] ;\n /*0340*/ MOV R33, R3 ;\n /*0350*/ MOV R3, 0x30 ;\n /*0360*/ LDC R3, c[0x0][R3+0x160] ;\n /*0370*/ MOV R38, R3 ;\n /*0380*/ MOV R3, 0x34 ;\n /*0390*/ LDC R3, c[0x0][R3+0x160] ;\n /*03a0*/ MOV R36, R3 ;\n /*03b0*/ MOV R3, 0x38 ;\n /*03c0*/ LDC R3, c[0x0][R3+0x160] ;\n /*03d0*/ MOV R3, R3 ;\n /*03e0*/ MOV R4, 0x3c ;\n /*03f0*/ LDC R4, c[0x0][R4+0x160] ;\n /*0400*/ MOV R4, R4 ;\n /*0410*/ MOV R5, 0x40 ;\n /*0420*/ LDC R5, c[0x0][R5+0x160] ;\n /*0430*/ MOV R5, R5 ;\n /*0440*/ MOV R8, 0x44 ;\n /*0450*/ LDC R8, c[0x0][R8+0x160] ;\n /*0460*/ MOV R8, R8 ;\n /*0470*/ MOV R9, 0x48 ;\n /*0480*/ LDC R9, c[0x0][R9+0x160] ;\n /*0490*/ MOV R9, R9 ;\n /*04a0*/ MOV R10, 0x4c ;\n /*04b0*/ LDC R10, c[0x0][R10+0x160] ;\n /*04c0*/ MOV R10, R10 ;\n /*04d0*/ MOV R11, 0x50 ;\n /*04e0*/ LDC R11, c[0x0][R11+0x160] ;\n /*04f0*/ MOV R11, R11 ;\n /*0500*/ MOV R12, 0x54 ;\n /*0510*/ LDC R12, c[0x0][R12+0x160] ;\n /*0520*/ MOV R12, R12 ;\n /*0530*/ MOV R13, 0x58 ;\n /*0540*/ LDC R13, c[0x0][R13+0x160] ;\n /*0550*/ MOV R13, R13 ;\n /*0560*/ MOV R14, 0x5c ;\n /*0570*/ LDC R14, c[0x0][R14+0x160] ;\n /*0580*/ MOV R14, R14 ;\n /*0590*/ MOV R15, 0x60 ;\n /*05a0*/ LDC R15, c[0x0][R15+0x160] ;\n /*05b0*/ MOV R15, R15 ;\n /*05c0*/ MOV R16, 0x64 ;\n /*05d0*/ LDC R16, c[0x0][R16+0x160] ;\n /*05e0*/ MOV R16, R16 ;\n /*05f0*/ MOV R17, 0x68 ;\n /*0600*/ LDC R17, c[0x0][R17+0x160] ;\n /*0610*/ MOV R17, R17 ;\n /*0620*/ MOV R18, R18 ;\n /*0630*/ MOV R19, R19 ;\n /*0640*/ MOV R20, R20 ;\n /*0650*/ MOV R21, R21 ;\n /*0660*/ IADD3 R22, P0, R0, RZ, RZ ;\n /*0670*/ IADD3.X R23, R2, RZ, RZ, P0, !PT ;\n /*0680*/ MOV R24, RZ ;\n /*0690*/ MOV R24, R24 ;\n /*06a0*/ MOV R25, R25 ;\n /*06b0*/ MOV R39, R24 ;\n /*06c0*/ MOV R40, R25 ;\n /*06d0*/ MOV R25, R25 ;\n /*06e0*/ MUFU.RCP R26, R25 ;\n /*06f0*/ FADD R27, -RZ, -R25 ;\n /*0700*/ MOV R27, R27 ;\n /*0710*/ MOV R34, 0x3f800000 ;\n /*0720*/ FFMA R34, R27, R26, R34 ;\n /*0730*/ FCHK P0, R39, R40 ;\n /*0740*/ FFMA R34, R26, R34, R26 ;\n /*0750*/ MOV R26, RZ ;\n /*0760*/ MOV R39, R24 ;\n /*0770*/ FFMA R26, R39, R34, R26 ;\n /*0780*/ FFMA R27, R27, R26, R39 ;\n /*0790*/ FFMA R26, R27, R34, R26 ;\n /*07a0*/ MOV R26, R26 ;\n /*07b0*/ MOV R0, R0 ;\n /*07c0*/ MOV R2, R2 ;\n /*07d0*/ MOV R6, R6 ;\n /*07e0*/ MOV R7, R7 ;\n /*07f0*/ MOV R32, R32 ;\n /*0800*/ MOV R29, R29 ;\n /*0810*/ MOV R28, R28 ;\n /*0820*/ MOV R35, R35 ;\n /*0830*/ MOV R37, R37 ;\n /*0840*/ MOV R33, R33 ;\n /*0850*/ MOV R38, R38 ;\n /*0860*/ MOV R36, R36 ;\n /*0870*/ MOV R3, R3 ;\n /*0880*/ MOV R4, R4 ;\n /*0890*/ MOV R5, R5 ;\n /*08a0*/ MOV R8, R8 ;\n /*08b0*/ MOV R9, R9 ;\n /*08c0*/ MOV R10, R10 ;\n /*08d0*/ MOV R11, R11 ;\n /*08e0*/ MOV R12, R12 ;\n /*08f0*/ MOV R13, R13 ;\n /*0900*/ MOV R14, R14 ;\n /*0910*/ MOV R15, R15 ;\n /*0920*/ MOV R16, R16 ;\n /*0930*/ MOV R17, R17 ;\n /*0940*/ MOV R18, R18 ;\n /*0950*/ MOV R19, R19 ;\n /*0960*/ MOV R20, R20 ;\n /*0970*/ MOV R21, R21 ;\n /*0980*/ MOV R22, R22 ;\n /*0990*/ MOV R23, R23 ;\n /*09a0*/ MOV R34, R24 ;\n /*09b0*/ MOV R24, R24 ;\n /*09c0*/ MOV R25, R25 ;\n /*09d0*/ MOV R26, R26 ;\n /*09e0*/ @P0 BRA `(.L_x_1) ;\n /*09f0*/ BRA `(.L_x_2) ;\n.L_x_1:\n /*0a00*/ MOV R24, R24 ;\n /*0a10*/ MOV R25, R25 ;\n /*0a20*/ MOV R41, R24 ;\n /*0a30*/ MOV R27, R25 ;\n /*0a40*/ MOV R26, 0xa60 ;\n /*0a50*/ CALL.REL.NOINC `($__internal_2_$__cuda_sm3x_div_rn_noftz_f32_slowpath) ;\n /*0a60*/ MOV R24, R25 ;\n /*0a70*/ MOV R24, R24 ;\n /*0a80*/ MOV R26, R24 ;\n.L_x_2:\n /*0a90*/ MOV R26, R26 ;\n /*0aa0*/ FADD R29, R34, -R29 ;\n /*0ab0*/ FADD R26, R29, R26 ;\n /*0ac0*/ FADD R26, R26, 1.4012984643248170709e-44 ;\n /*0ad0*/ FMUL R26, R26, -1.7407000149285479626e-37 ;\n /*0ae0*/ ISETP.LT.AND P0, PT, R32, 0x1, PT ;\n /*0af0*/ MOV R34, R26 ;\n /*0b00*/ @P0 BRA `(.L_x_3) ;\n /*0b10*/ MOV R28, R28 ;\n /*0b20*/ MOV R35, R35 ;\n /*0b30*/ MOV R27, R28 ;\n /*0b40*/ MOV R29, R35 ;\n /*0b50*/ MOV R24, R35 ;\n /*0b60*/ MUFU.RCP R25, R24 ;\n /*0b70*/ FADD R24, -RZ, -R24 ;\n /*0b80*/ MOV R24, R24 ;\n /*0b90*/ MOV R26, 0x3f800000 ;\n /*0ba0*/ FFMA R26, R24, R25, R26 ;\n /*0bb0*/ FCHK P0, R27, R29 ;\n /*0bc0*/ FFMA R26, R25, R26, R25 ;\n /*0bd0*/ MOV R25, RZ ;\n /*0be0*/ MOV R27, R28 ;\n /*0bf0*/ FFMA R25, R27, R26, R25 ;\n /*0c00*/ FFMA R24, R24, R25, R27 ;\n /*0c10*/ FFMA R24, R24, R26, R25 ;\n /*0c20*/ MOV R24, R24 ;\n /*0c30*/ MOV R28, R28 ;\n /*0c40*/ MOV R35, R35 ;\n /*0c50*/ MOV R24, R24 ;\n /*0c60*/ @P0 BRA `(.L_x_4) ;\n /*0c70*/ BRA `(.L_x_5) ;\n.L_x_4:\n /*0c80*/ MOV R28, R28 ;\n /*0c90*/ MOV R35, R35 ;\n /*0ca0*/ MOV R41, R28 ;\n /*0cb0*/ MOV R27, R35 ;\n /*0cc0*/ MOV R26, 0xce0 ;\n /*0cd0*/ CALL.REL.NOINC `($__internal_2_$__cuda_sm3x_div_rn_noftz_f32_slowpath) ;\n /*0ce0*/ MOV R24, R25 ;\n /*0cf0*/ MOV R24, R24 ;\n /*0d00*/ MOV R24, R24 ;\n.L_x_5:\n /*0d10*/ MOV R24, R24 ;\n /*0d20*/ FADD R24, R24, -180.5099945068359375 ;\n /*0d30*/ FADD R37, R37, 1.24799997854467540836e+28 ;\n /*0d40*/ FSETP.LT.AND P0, PT, R37, 1.175494350822287508e-38, PT ;\n /*0d50*/ FMUL R28, R37, 8388608 ;\n /*0d60*/ FSEL R28, R28, R37, P0 ;\n /*0d70*/ FSEL R25, RZ, -23, !P0 ;\n /*0d80*/ MOV R28, R28 ;\n /*0d90*/ IADD3 R26, R28, -0x3f2aaaab, RZ ;\n /*0da0*/ LOP3.LUT R26, R26, 0xff800000, RZ, 0xc0, !PT ;\n /*0db0*/ IADD3 R27, R28, -R26, RZ ;\n /*0dc0*/ MOV R27, R27 ;\n /*0dd0*/ I2FP.F32.S32 R26, R26 ;\n /*0de0*/ MOV R29, 0x34000000 ;\n /*0df0*/ FFMA R25, R26, R29, R25 ;\n /*0e00*/ FADD R27, R27, -1 ;\n /*0e10*/ MOV R26, 0x3e1039f6 ;\n /*0e20*/ MOV R29, 0xbe055027 ;\n /*0e30*/ FFMA R26, R29, R27, R26 ;\n /*0e40*/ MOV R29, 0xbdf8cdcc ;\n /*0e50*/ FFMA R26, R26, R27, R29 ;\n /*0e60*/ MOV R29, 0x3e0f2955 ;\n /*0e70*/ FFMA R26, R26, R27, R29 ;\n /*0e80*/ MOV R29, 0xbe2ad8b9 ;\n /*0e90*/ FFMA R26, R26, R27, R29 ;\n /*0ea0*/ MOV R29, 0x3e4ced0b ;\n /*0eb0*/ FFMA R26, R26, R27, R29 ;\n /*0ec0*/ MOV R29, 0xbe7fff22 ;\n /*0ed0*/ FFMA R26, R26, R27, R29 ;\n /*0ee0*/ MOV R29, 0x3eaaaa78 ;\n /*0ef0*/ FFMA R26, R26, R27, R29 ;\n /*0f00*/ MOV R29, 0xbf000000 ;\n /*0f10*/ FFMA R26, R26, R27, R29 ;\n /*0f20*/ FMUL R26, R27, R26 ;\n /*0f30*/ FFMA R26, R26, R27, R27 ;\n /*0f40*/ MOV R27, 0x3f317218 ;\n /*0f50*/ FFMA R25, R25, R27, R26 ;\n /*0f60*/ ISETP.GT.U32.AND P1, PT, R28, 0x7f7fffff, PT ;\n /*0f70*/ MOV R38, R38 ;\n /*0f80*/ MOV R26, 0x82215231 ;\n /*0f90*/ MOV R37, R38 ;\n /*0fa0*/ MOV R39, R26 ;\n /*0fb0*/ MOV R26, R26 ;\n /*0fc0*/ MUFU.RCP R27, R26 ;\n /*0fd0*/ FADD R29, -RZ, -R26 ;\n /*0fe0*/ MOV R29, R29 ;\n /*0ff0*/ MOV R35, 0x3f800000 ;\n /*1000*/ FFMA R35, R29, R27, R35 ;\n /*1010*/ FCHK P0, R37, R39 ;\n /*1020*/ FFMA R35, R27, R35, R27 ;\n /*1030*/ MOV R27, RZ ;\n /*1040*/ MOV R37, R38 ;\n /*1050*/ FFMA R27, R37, R35, R27 ;\n /*1060*/ FFMA R29, R29, R27, R37 ;\n /*1070*/ FFMA R29, R29, R35, R27 ;\n /*1080*/ MOV R27, R29 ;\n /*1090*/ MOV R24, R24 ;\n /*10a0*/ MOV R28, R28 ;\n /*10b0*/ MOV R29, R25 ;\n /*10c0*/ PLOP3.LUT P1, PT, P1, PT, PT, 0x80, 0x0 ;\n /*10d0*/ MOV R38, R38 ;\n /*10e0*/ MOV R26, R26 ;\n /*10f0*/ MOV R27, R27 ;\n /*1100*/ @P0 BRA `(.L_x_6) ;\n /*1110*/ BRA `(.L_x_7) ;\n.L_x_6:\n /*1120*/ MOV R38, R38 ;\n /*1130*/ MOV R26, R26 ;\n /*1140*/ MOV R41, R38 ;\n /*1150*/ MOV R27, R26 ;\n /*1160*/ MOV R26, 0x1180 ;\n /*1170*/ CALL.REL.NOINC `($__internal_2_$__cuda_sm3x_div_rn_noftz_f32_slowpath) ;\n /*1180*/ MOV R25, R25 ;\n /*1190*/ MOV R25, R25 ;\n /*11a0*/ MOV R27, R25 ;\n.L_x_7:\n /*11b0*/ MOV R27, R27 ;\n /*11c0*/ FADD R27, R27, -1.03460000000000000000e+09 ;\n /*11d0*/ FMUL R36, R36, RZ ;\n /*11e0*/ FADD R27, R27, -R36 ;\n /*11f0*/ FADD R25, R33, -R27 ;\n /*1200*/ IADD3 R26, R32, -0x1, RZ ;\n /*1210*/ LOP3.LUT R27, R32, 0x3, RZ, 0xc0, !PT ;\n /*1220*/ MOV R25, R25 ;\n /*1230*/ MOV R33, R26 ;\n /*1240*/ MOV R26, R27 ;\n /*1250*/ @P1 BRA `(.L_x_8) ;\n /*1260*/ BRA `(.L_x_9) ;\n.L_x_8:\n /*1270*/ ISETP.LT.U32.AND P0, PT, R33, 0x3, PT ;\n /*1280*/ MOV R27, RZ ;\n /*1290*/ MOV R27, R27 ;\n /*12a0*/ @P0 BRA `(.L_x_10) ;\n /*12b0*/ FSETP.EQ.AND P0, PT, R28, RZ, PT ;\n /*12c0*/ IADD3 R29, R32, -R26, RZ ;\n /*12d0*/ MOV R27, 0x7f800000 ;\n /*12e0*/ FFMA R27, R28, R27, R27 ;\n /*12f0*/ FSEL R27, R27, -INF , !P0 ;\n /*1300*/ MOV R32, RZ ;\n /*1310*/ MOV R29, R29 ;\n /*1320*/ MOV R35, R27 ;\n /*1330*/ MOV R27, R32 ;\n.L_x_11:\n /*1340*/ IMAD.WIDE R32, R27, 0x4, RZ ;\n /*1350*/ MOV R38, R32 ;\n /*1360*/ MOV R39, R33 ;\n /*1370*/ IADD3 R37, P0, R20, R38, RZ ;\n /*1380*/ IADD3.X R36, R21, R39, RZ, P0, !PT ;\n /*1390*/ MOV R32, R37 ;\n /*13a0*/ MOV R33, R36 ;\n /*13b0*/ MOV R32, R32 ;\n /*13c0*/ MOV R33, R33 ;\n /*13d0*/ R2UR UR4, R30 ;\n /*13e0*/ R2UR UR5, R31 ;\n /*13f0*/ STG.E [R32.64], R24 ;\n /*1400*/ IADD3 R38, P0, R18, R38, RZ ;\n /*1410*/ IADD3.X R39, R19, R39, RZ, P0, !PT ;\n /*1420*/ MOV R40, 0x7b4476d0 ;\n /*1430*/ MOV R32, R38 ;\n /*1440*/ MOV R33, R39 ;\n /*1450*/ MOV R32, R32 ;\n /*1460*/ MOV R33, R33 ;\n /*1470*/ R2UR UR4, R30 ;\n /*1480*/ R2UR UR5, R31 ;\n /*1490*/ STG.E [R32.64], R40 ;\n /*14a0*/ MOV R32, R37 ;\n /*14b0*/ MOV R33, R36 ;\n /*14c0*/ MOV R32, R32 ;\n /*14d0*/ MOV R33, R33 ;\n /*14e0*/ R2UR UR4, R30 ;\n /*14f0*/ R2UR UR5, R31 ;\n /*1500*/ LDG.E R32, [R32.64] ;\n /*1510*/ FADD R32, R32, 1.02009998806386007928e+36 ;\n /*1520*/ FADD R32, R32, R35 ;\n /*1530*/ FADD R32, R34, R32 ;\n /*1540*/ FADD R34, R25, R32 ;\n /*1550*/ IADD3 R32, P0, R37, 0x4, RZ ;\n /*1560*/ IADD3.X R33, R36, RZ, RZ, P0, !PT ;\n /*1570*/ MOV R32, R32 ;\n /*1580*/ MOV R33, R33 ;\n /*1590*/ MOV R32, R32 ;\n /*15a0*/ MOV R33, R33 ;\n /*15b0*/ R2UR UR4, R30 ;\n /*15c0*/ R2UR UR5, R31 ;\n /*15d0*/ STG.E [R32.64], R24 ;\n /*15e0*/ IADD3 R32, P0, R38, 0x4, RZ ;\n /*15f0*/ IADD3.X R33, R39, RZ, RZ, P0, !PT ;\n /*1600*/ MOV R32, R32 ;\n /*1610*/ MOV R33, R33 ;\n /*1620*/ MOV R32, R32 ;\n /*1630*/ MOV R33, R33 ;\n /*1640*/ R2UR UR4, R30 ;\n /*1650*/ R2UR UR5, R31 ;\n /*1660*/ STG.E [R32.64], R40 ;\n /*1670*/ IADD3 R32, P0, R37, 0x4, RZ ;\n /*1680*/ IADD3.X R33, R36, RZ, RZ, P0, !PT ;\n /*1690*/ MOV R32, R32 ;\n /*16a0*/ MOV R33, R33 ;\n /*16b0*/ MOV R32, R32 ;\n /*16c0*/ MOV R33, R33 ;\n /*16d0*/ R2UR UR4, R30 ;\n /*16e0*/ R2UR UR5, R31 ;\n /*16f0*/ LDG.E R32, [R32.64] ;\n /*1700*/ FADD R32, R32, 1.02009998806386007928e+36 ;\n /*1710*/ FADD R32, R32, R35 ;\n /*1720*/ FADD R32, R34, R32 ;\n /*1730*/ FADD R34, R25, R32 ;\n /*1740*/ IADD3 R32, P0, R37, 0x8, RZ ;\n /*1750*/ IADD3.X R33, R36, RZ, RZ, P0, !PT ;\n /*1760*/ MOV R32, R32 ;\n /*1770*/ MOV R33, R33 ;\n /*1780*/ MOV R32, R32 ;\n /*1790*/ MOV R33, R33 ;\n /*17a0*/ R2UR UR4, R30 ;\n /*17b0*/ R2UR UR5, R31 ;\n /*17c0*/ STG.E [R32.64], R24 ;\n /*17d0*/ IADD3 R32, P0, R38, 0x8, RZ ;\n /*17e0*/ IADD3.X R33, R39, RZ, RZ, P0, !PT ;\n /*17f0*/ MOV R32, R32 ;\n /*1800*/ MOV R33, R33 ;\n /*1810*/ MOV R32, R32 ;\n /*1820*/ MOV R33, R33 ;\n /*1830*/ R2UR UR4, R30 ;\n /*1840*/ R2UR UR5, R31 ;\n /*1850*/ STG.E [R32.64], R40 ;\n /*1860*/ IADD3 R32, P0, R37, 0x8, RZ ;\n /*1870*/ IADD3.X R33, R36, RZ, RZ, P0, !PT ;\n /*1880*/ MOV R32, R32 ;\n /*1890*/ MOV R33, R33 ;\n /*18a0*/ MOV R32, R32 ;\n /*18b0*/ MOV R33, R33 ;\n /*18c0*/ R2UR UR4, R30 ;\n /*18d0*/ R2UR UR5, R31 ;\n /*18e0*/ LDG.E R32, [R32.64] ;\n /*18f0*/ FADD R32, R32, 1.02009998806386007928e+36 ;\n /*1900*/ FADD R32, R32, R35 ;\n /*1910*/ FADD R32, R34, R32 ;\n /*1920*/ FADD R34, R25, R32 ;\n /*1930*/ IADD3 R32, P0, R37, 0xc, RZ ;\n /*1940*/ IADD3.X R33, R36, RZ, RZ, P0, !PT ;\n /*1950*/ MOV R32, R32 ;\n /*1960*/ MOV R33, R33 ;\n /*1970*/ MOV R32, R32 ;\n /*1980*/ MOV R33, R33 ;\n /*1990*/ R2UR UR4, R30 ;\n /*19a0*/ R2UR UR5, R31 ;\n /*19b0*/ STG.E [R32.64], R24 ;\n /*19c0*/ IADD3 R32, P0, R38, 0xc, RZ ;\n /*19d0*/ IADD3.X R33, R39, RZ, RZ, P0, !PT ;\n /*19e0*/ MOV R32, R32 ;\n /*19f0*/ MOV R33, R33 ;\n /*1a00*/ MOV R32, R32 ;\n /*1a10*/ MOV R33, R33 ;\n /*1a20*/ R2UR UR4, R30 ;\n /*1a30*/ R2UR UR5, R31 ;\n /*1a40*/ STG.E [R32.64], R40 ;\n /*1a50*/ IADD3 R32, P0, R37, 0xc, RZ ;\n /*1a60*/ IADD3.X R33, R36, RZ, RZ, P0, !PT ;\n /*1a70*/ MOV R32, R32 ;\n /*1a80*/ MOV R33, R33 ;\n /*1a90*/ MOV R32, R32 ;\n /*1aa0*/ MOV R33, R33 ;\n /*1ab0*/ R2UR UR4, R30 ;\n /*1ac0*/ R2UR UR5, R31 ;\n /*1ad0*/ LDG.E R32, [R32.64] ;\n /*1ae0*/ FADD R32, R32, 1.02009998806386007928e+36 ;\n /*1af0*/ FADD R32, R32, R35 ;\n /*1b00*/ FADD R32, R34, R32 ;\n /*1b10*/ FADD R32, R25, R32 ;\n /*1b20*/ IADD3 R27, R27, 0x4, RZ ;\n /*1b30*/ IADD3 R29, R29, -0x4, RZ ;\n /*1b40*/ ISETP.NE.AND P0, PT, R29, RZ, PT ;\n /*1b50*/ MOV R34, R32 ;\n /*1b60*/ MOV R27, R27 ;\n /*1b70*/ MOV R29, R29 ;\n /*1b80*/ @P0 BRA `(.L_x_11) ;\n.L_x_10:\n /*1b90*/ ISETP.EQ.AND P0, PT, R26, RZ, PT ;\n /*1ba0*/ @P0 BRA `(.L_x_3) ;\n /*1bb0*/ FSETP.EQ.AND P0, PT, R28, RZ, PT ;\n /*1bc0*/ MOV R29, 0x7f800000 ;\n /*1bd0*/ FFMA R28, R28, R29, R29 ;\n /*1be0*/ FSEL R32, R28, -INF , !P0 ;\n /*1bf0*/ IMAD.WIDE R28, R27, 0x4, RZ ;\n /*1c00*/ MOV R33, R28 ;\n /*1c10*/ MOV R28, R29 ;\n /*1c20*/ IADD3 R27, P0, R18, R33, RZ ;\n /*1c30*/ IADD3.X R19, R19, R28, RZ, P0, !PT ;\n /*1c40*/ IADD3 R20, P0, R20, R33, RZ ;\n /*1c50*/ IADD3.X R18, R21, R28, RZ, P0, !PT ;\n /*1c60*/ MOV R32, R32 ;\n /*1c70*/ MOV R21, R27 ;\n /*1c80*/ MOV R27, R19 ;\n /*1c90*/ MOV R28, R20 ;\n /*1ca0*/ MOV R20, R18 ;\n.L_x_12:\n /*1cb0*/ MOV R18, R28 ;\n /*1cc0*/ MOV R19, R20 ;\n /*1cd0*/ MOV R18, R18 ;\n /*1ce0*/ MOV R19, R19 ;\n /*1cf0*/ R2UR UR4, R30 ;\n /*1d00*/ R2UR UR5, R31 ;\n /*1d10*/ STG.E [R18.64], R24 ;\n /*1d20*/ MOV R29, 0x7b4476d0 ;\n /*1d30*/ MOV R18, R21 ;\n /*1d40*/ MOV R19, R27 ;\n /*1d50*/ MOV R18, R18 ;\n /*1d60*/ MOV R19, R19 ;\n /*1d70*/ R2UR UR4, R30 ;\n /*1d80*/ R2UR UR5, R31 ;\n /*1d90*/ STG.E [R18.64], R29 ;\n /*1da0*/ MOV R18, R28 ;\n /*1db0*/ MOV R19, R20 ;\n /*1dc0*/ MOV R18, R18 ;\n /*1dd0*/ MOV R19, R19 ;\n /*1de0*/ R2UR UR4, R30 ;\n /*1df0*/ R2UR UR5, R31 ;\n /*1e00*/ LDG.E R18, [R18.64] ;\n /*1e10*/ FADD R18, R18, 1.02009998806386007928e+36 ;\n /*1e20*/ FADD R18, R18, R32 ;\n /*1e30*/ FADD R18, R34, R18 ;\n /*1e40*/ FADD R18, R25, R18 ;\n /*1e50*/ IADD3 R21, P0, R21, 0x4, RZ ;\n /*1e60*/ IADD3.X R27, R27, RZ, RZ, P0, !PT ;\n /*1e70*/ IADD3 R19, P0, R28, 0x4, RZ ;\n /*1e80*/ IADD3.X R20, R20, RZ, RZ, P0, !PT ;\n /*1e90*/ IADD3 R26, R26, -0x1, RZ ;\n /*1ea0*/ ISETP.NE.AND P0, PT, R26, RZ, PT ;\n /*1eb0*/ MOV R34, R18 ;\n /*1ec0*/ MOV R21, R21 ;\n /*1ed0*/ MOV R27, R27 ;\n /*1ee0*/ MOV R28, R19 ;\n /*1ef0*/ MOV R20, R20 ;\n /*1f00*/ MOV R26, R26 ;\n /*1f10*/ @P0 BRA `(.L_x_12) ;\n /*1f20*/ BRA `(.L_x_3) ;\n.L_x_9:\n /*1f30*/ FSETP.EQ.AND P0, PT, R28, RZ, PT ;\n /*1f40*/ @P0 BRA `(.L_x_13) ;\n /*1f50*/ BRA `(.L_x_14) ;\n.L_x_13:\n /*1f60*/ ISETP.LT.U32.AND P0, PT, R33, 0x3, PT ;\n /*1f70*/ MOV R27, RZ ;\n /*1f80*/ MOV R27, R27 ;\n /*1f90*/ @P0 BRA `(.L_x_15) ;\n /*1fa0*/ IADD3 R32, R32, -R26, RZ ;\n /*1fb0*/ MOV R27, RZ ;\n /*1fc0*/ MOV R32, R32 ;\n /*1fd0*/ MOV R27, R27 ;\n.L_x_16:\n /*1fe0*/ IMAD.WIDE R28, R27, 0x4, RZ ;\n /*1ff0*/ MOV R36, R28 ;\n /*2000*/ MOV R37, R29 ;\n /*2010*/ IADD3 R35, P0, R20, R36, RZ ;\n /*2020*/ IADD3.X R33, R21, R37, RZ, P0, !PT ;\n /*2030*/ MOV R28, R35 ;\n /*2040*/ MOV R29, R33 ;\n /*2050*/ MOV R28, R28 ;\n /*2060*/ MOV R29, R29 ;\n /*2070*/ R2UR UR4, R30 ;\n /*2080*/ R2UR UR5, R31 ;\n /*2090*/ STG.E [R28.64], R24 ;\n /*20a0*/ IADD3 R36, P0, R18, R36, RZ ;\n /*20b0*/ IADD3.X R37, R19, R37, RZ, P0, !PT ;\n /*20c0*/ MOV R38, 0x7b4476d0 ;\n /*20d0*/ MOV R28, R36 ;\n /*20e0*/ MOV R29, R37 ;\n /*20f0*/ MOV R28, R28 ;\n /*2100*/ MOV R29, R29 ;\n /*2110*/ R2UR UR4, R30 ;\n /*2120*/ R2UR UR5, R31 ;\n /*2130*/ STG.E [R28.64], R38 ;\n /*2140*/ MOV R28, R35 ;\n /*2150*/ MOV R29, R33 ;\n /*2160*/ MOV R28, R28 ;\n /*2170*/ MOV R29, R29 ;\n /*2180*/ R2UR UR4, R30 ;\n /*2190*/ R2UR UR5, R31 ;\n /*21a0*/ LDG.E R28, [R28.64] ;\n /*21b0*/ FADD R28, R28, 1.02009998806386007928e+36 ;\n /*21c0*/ FADD R28, R28, -INF ;\n /*21d0*/ FADD R28, R34, R28 ;\n /*21e0*/ FADD R34, R25, R28 ;\n /*21f0*/ IADD3 R28, P0, R35, 0x4, RZ ;\n /*2200*/ IADD3.X R29, R33, RZ, RZ, P0, !PT ;\n /*2210*/ MOV R28, R28 ;\n /*2220*/ MOV R29, R29 ;\n /*2230*/ MOV R28, R28 ;\n /*2240*/ MOV R29, R29 ;\n /*2250*/ R2UR UR4, R30 ;\n /*2260*/ R2UR UR5, R31 ;\n /*2270*/ STG.E [R28.64], R24 ;\n /*2280*/ IADD3 R28, P0, R36, 0x4, RZ ;\n /*2290*/ IADD3.X R29, R37, RZ, RZ, P0, !PT ;\n /*22a0*/ MOV R28, R28 ;\n /*22b0*/ MOV R29, R29 ;\n /*22c0*/ MOV R28, R28 ;\n /*22d0*/ MOV R29, R29 ;\n /*22e0*/ R2UR UR4, R30 ;\n /*22f0*/ R2UR UR5, R31 ;\n /*2300*/ STG.E [R28.64], R38 ;\n /*2310*/ IADD3 R28, P0, R35, 0x4, RZ ;\n /*2320*/ IADD3.X R29, R33, RZ, RZ, P0, !PT ;\n /*2330*/ MOV R28, R28 ;\n /*2340*/ MOV R29, R29 ;\n /*2350*/ MOV R28, R28 ;\n /*2360*/ MOV R29, R29 ;\n /*2370*/ R2UR UR4, R30 ;\n /*2380*/ R2UR UR5, R31 ;\n /*2390*/ LDG.E R28, [R28.64] ;\n /*23a0*/ FADD R28, R28, 1.02009998806386007928e+36 ;\n /*23b0*/ FADD R28, R28, -INF ;\n /*23c0*/ FADD R28, R34, R28 ;\n /*23d0*/ FADD R34, R25, R28 ;\n /*23e0*/ IADD3 R28, P0, R35, 0x8, RZ ;\n /*23f0*/ IADD3.X R29, R33, RZ, RZ, P0, !PT ;\n /*2400*/ MOV R28, R28 ;\n /*2410*/ MOV R29, R29 ;\n /*2420*/ MOV R28, R28 ;\n /*2430*/ MOV R29, R29 ;\n /*2440*/ R2UR UR4, R30 ;\n /*2450*/ R2UR UR5, R31 ;\n /*2460*/ STG.E [R28.64], R24 ;\n /*2470*/ IADD3 R28, P0, R36, 0x8, RZ ;\n /*2480*/ IADD3.X R29, R37, RZ, RZ, P0, !PT ;\n /*2490*/ MOV R28, R28 ;\n /*24a0*/ MOV R29, R29 ;\n /*24b0*/ MOV R28, R28 ;\n /*24c0*/ MOV R29, R29 ;\n /*24d0*/ R2UR UR4, R30 ;\n /*24e0*/ R2UR UR5, R31 ;\n /*24f0*/ STG.E [R28.64], R38 ;\n /*2500*/ IADD3 R28, P0, R35, 0x8, RZ ;\n /*2510*/ IADD3.X R29, R33, RZ, RZ, P0, !PT ;\n /*2520*/ MOV R28, R28 ;\n /*2530*/ MOV R29, R29 ;\n /*2540*/ MOV R28, R28 ;\n /*2550*/ MOV R29, R29 ;\n /*2560*/ R2UR UR4, R30 ;\n /*2570*/ R2UR UR5, R31 ;\n /*2580*/ LDG.E R28, [R28.64] ;\n /*2590*/ FADD R28, R28, 1.02009998806386007928e+36 ;\n /*25a0*/ FADD R28, R28, -INF ;\n /*25b0*/ FADD R28, R34, R28 ;\n /*25c0*/ FADD R34, R25, R28 ;\n /*25d0*/ IADD3 R28, P0, R35, 0xc, RZ ;\n /*25e0*/ IADD3.X R29, R33, RZ, RZ, P0, !PT ;\n /*25f0*/ MOV R28, R28 ;\n /*2600*/ MOV R29, R29 ;\n /*2610*/ MOV R28, R28 ;\n /*2620*/ MOV R29, R29 ;\n /*2630*/ R2UR UR4, R30 ;\n /*2640*/ R2UR UR5, R31 ;\n /*2650*/ STG.E [R28.64], R24 ;\n /*2660*/ IADD3 R28, P0, R36, 0xc, RZ ;\n /*2670*/ IADD3.X R29, R37, RZ, RZ, P0, !PT ;\n /*2680*/ MOV R28, R28 ;\n /*2690*/ MOV R29, R29 ;\n /*26a0*/ MOV R28, R28 ;\n /*26b0*/ MOV R29, R29 ;\n /*26c0*/ R2UR UR4, R30 ;\n /*26d0*/ R2UR UR5, R31 ;\n /*26e0*/ STG.E [R28.64], R38 ;\n /*26f0*/ IADD3 R28, P0, R35, 0xc, RZ ;\n /*2700*/ IADD3.X R29, R33, RZ, RZ, P0, !PT ;\n /*2710*/ MOV R28, R28 ;\n /*2720*/ MOV R29, R29 ;\n /*2730*/ MOV R28, R28 ;\n /*2740*/ MOV R29, R29 ;\n /*2750*/ R2UR UR4, R30 ;\n /*2760*/ R2UR UR5, R31 ;\n /*2770*/ LDG.E R28, [R28.64] ;\n /*2780*/ FADD R28, R28, 1.02009998806386007928e+36 ;\n /*2790*/ FADD R28, R28, -INF ;\n /*27a0*/ FADD R28, R34, R28 ;\n /*27b0*/ FADD R28, R25, R28 ;\n /*27c0*/ IADD3 R27, R27, 0x4, RZ ;\n /*27d0*/ IADD3 R32, R32, -0x4, RZ ;\n /*27e0*/ ISETP.NE.AND P0, PT, R32, RZ, PT ;\n /*27f0*/ MOV R34, R28 ;\n /*2800*/ MOV R27, R27 ;\n /*2810*/ MOV R32, R32 ;\n /*2820*/ @P0 BRA `(.L_x_16) ;\n.L_x_15:\n /*2830*/ ISETP.EQ.AND P0, PT, R26, RZ, PT ;\n /*2840*/ @P0 BRA `(.L_x_3) ;\n /*2850*/ IMAD.WIDE R28, R27, 0x4, RZ ;\n /*2860*/ MOV R32, R28 ;\n /*2870*/ MOV R28, R29 ;\n /*2880*/ IADD3 R27, P0, R18, R32, RZ ;\n /*2890*/ IADD3.X R19, R19, R28, RZ, P0, !PT ;\n /*28a0*/ IADD3 R20, P0, R20, R32, RZ ;\n /*28b0*/ IADD3.X R18, R21, R28, RZ, P0, !PT ;\n /*28c0*/ MOV R21, R27 ;\n /*28d0*/ MOV R27, R19 ;\n /*28e0*/ MOV R28, R20 ;\n /*28f0*/ MOV R20, R18 ;\n.L_x_17:\n /*2900*/ MOV R18, R28 ;\n /*2910*/ MOV R19, R20 ;\n /*2920*/ MOV R18, R18 ;\n /*2930*/ MOV R19, R19 ;\n /*2940*/ R2UR UR4, R30 ;\n /*2950*/ R2UR UR5, R31 ;\n /*2960*/ STG.E [R18.64], R24 ;\n /*2970*/ MOV R29, 0x7b4476d0 ;\n /*2980*/ MOV R18, R21 ;\n /*2990*/ MOV R19, R27 ;\n /*29a0*/ MOV R18, R18 ;\n /*29b0*/ MOV R19, R19 ;\n /*29c0*/ R2UR UR4, R30 ;\n /*29d0*/ R2UR UR5, R31 ;\n /*29e0*/ STG.E [R18.64], R29 ;\n /*29f0*/ MOV R18, R28 ;\n /*2a00*/ MOV R19, R20 ;\n /*2a10*/ MOV R18, R18 ;\n /*2a20*/ MOV R19, R19 ;\n /*2a30*/ R2UR UR4, R30 ;\n /*2a40*/ R2UR UR5, R31 ;\n /*2a50*/ LDG.E R18, [R18.64] ;\n /*2a60*/ FADD R18, R18, 1.02009998806386007928e+36 ;\n /*2a70*/ FADD R18, R18, -INF ;\n /*2a80*/ FADD R18, R34, R18 ;\n /*2a90*/ FADD R18, R25, R18 ;\n /*2aa0*/ IADD3 R21, P0, R21, 0x4, RZ ;\n /*2ab0*/ IADD3.X R27, R27, RZ, RZ, P0, !PT ;\n /*2ac0*/ IADD3 R19, P0, R28, 0x4, RZ ;\n /*2ad0*/ IADD3.X R20, R20, RZ, RZ, P0, !PT ;\n /*2ae0*/ IADD3 R26, R26, -0x1, RZ ;\n /*2af0*/ ISETP.EQ.AND P0, PT, R26, RZ, PT ;\n /*2b00*/ MOV R34, R18 ;\n /*2b10*/ MOV R21, R21 ;\n /*2b20*/ MOV R27, R27 ;\n /*2b30*/ MOV R28, R19 ;\n /*2b40*/ MOV R20, R20 ;\n /*2b50*/ MOV R26, R26 ;\n /*2b60*/ @P0 BRA `(.L_x_3) ;\n /*2b70*/ BRA `(.L_x_17) ;\n.L_x_14:\n /*2b80*/ ISETP.LT.U32.AND P0, PT, R33, 0x3, PT ;\n /*2b90*/ MOV R27, RZ ;\n /*2ba0*/ MOV R27, R27 ;\n /*2bb0*/ @P0 BRA `(.L_x_18) ;\n /*2bc0*/ IADD3 R28, R32, -R26, RZ ;\n /*2bd0*/ MOV R27, RZ ;\n /*2be0*/ MOV R28, R28 ;\n /*2bf0*/ MOV R27, R27 ;\n.L_x_19:\n /*2c00*/ IMAD.WIDE R32, R27, 0x4, RZ ;\n /*2c10*/ MOV R37, R32 ;\n /*2c20*/ MOV R38, R33 ;\n /*2c30*/ IADD3 R36, P0, R20, R37, RZ ;\n /*2c40*/ IADD3.X R35, R21, R38, RZ, P0, !PT ;\n /*2c50*/ MOV R32, R36 ;\n /*2c60*/ MOV R33, R35 ;\n /*2c70*/ MOV R32, R32 ;\n /*2c80*/ MOV R33, R33 ;\n /*2c90*/ R2UR UR4, R30 ;\n /*2ca0*/ R2UR UR5, R31 ;\n /*2cb0*/ STG.E [R32.64], R24 ;\n /*2cc0*/ IADD3 R37, P0, R18, R37, RZ ;\n /*2cd0*/ IADD3.X R38, R19, R38, RZ, P0, !PT ;\n /*2ce0*/ MOV R39, 0x7b4476d0 ;\n /*2cf0*/ MOV R32, R37 ;\n /*2d00*/ MOV R33, R38 ;\n /*2d10*/ MOV R32, R32 ;\n /*2d20*/ MOV R33, R33 ;\n /*2d30*/ R2UR UR4, R30 ;\n /*2d40*/ R2UR UR5, R31 ;\n /*2d50*/ STG.E [R32.64], R39 ;\n /*2d60*/ MOV R32, R36 ;\n /*2d70*/ MOV R33, R35 ;\n /*2d80*/ MOV R32, R32 ;\n /*2d90*/ MOV R33, R33 ;\n /*2da0*/ R2UR UR4, R30 ;\n /*2db0*/ R2UR UR5, R31 ;\n /*2dc0*/ LDG.E R32, [R32.64] ;\n /*2dd0*/ FADD R32, R32, 1.02009998806386007928e+36 ;\n /*2de0*/ FADD R32, R32, R29 ;\n /*2df0*/ FADD R32, R34, R32 ;\n /*2e00*/ FADD R34, R25, R32 ;\n /*2e10*/ IADD3 R32, P0, R36, 0x4, RZ ;\n /*2e20*/ IADD3.X R33, R35, RZ, RZ, P0, !PT ;\n /*2e30*/ MOV R32, R32 ;\n /*2e40*/ MOV R33, R33 ;\n /*2e50*/ MOV R32, R32 ;\n /*2e60*/ MOV R33, R33 ;\n /*2e70*/ R2UR UR4, R30 ;\n /*2e80*/ R2UR UR5, R31 ;\n /*2e90*/ STG.E [R32.64], R24 ;\n /*2ea0*/ IADD3 R32, P0, R37, 0x4, RZ ;\n /*2eb0*/ IADD3.X R33, R38, RZ, RZ, P0, !PT ;\n /*2ec0*/ MOV R32, R32 ;\n /*2ed0*/ MOV R33, R33 ;\n /*2ee0*/ MOV R32, R32 ;\n /*2ef0*/ MOV R33, R33 ;\n /*2f00*/ R2UR UR4, R30 ;\n /*2f10*/ R2UR UR5, R31 ;\n /*2f20*/ STG.E [R32.64], R39 ;\n /*2f30*/ IADD3 R32, P0, R36, 0x4, RZ ;\n /*2f40*/ IADD3.X R33, R35, RZ, RZ, P0, !PT ;\n /*2f50*/ MOV R32, R32 ;\n /*2f60*/ MOV R33, R33 ;\n /*2f70*/ MOV R32, R32 ;\n /*2f80*/ MOV R33, R33 ;\n /*2f90*/ R2UR UR4, R30 ;\n /*2fa0*/ R2UR UR5, R31 ;\n /*2fb0*/ LDG.E R32, [R32.64] ;\n /*2fc0*/ FADD R32, R32, 1.02009998806386007928e+36 ;\n /*2fd0*/ FADD R32, R32, R29 ;\n /*2fe0*/ FADD R32, R34, R32 ;\n /*2ff0*/ FADD R34, R25, R32 ;\n /*3000*/ IADD3 R32, P0, R36, 0x8, RZ ;\n /*3010*/ IADD3.X R33, R35, RZ, RZ, P0, !PT ;\n /*3020*/ MOV R32, R32 ;\n /*3030*/ MOV R33, R33 ;\n /*3040*/ MOV R32, R32 ;\n /*3050*/ MOV R33, R33 ;\n /*3060*/ R2UR UR4, R30 ;\n /*3070*/ R2UR UR5, R31 ;\n /*3080*/ STG.E [R32.64], R24 ;\n /*3090*/ IADD3 R32, P0, R37, 0x8, RZ ;\n /*30a0*/ IADD3.X R33, R38, RZ, RZ, P0, !PT ;\n /*30b0*/ MOV R32, R32 ;\n /*30c0*/ MOV R33, R33 ;\n /*30d0*/ MOV R32, R32 ;\n /*30e0*/ MOV R33, R33 ;\n /*30f0*/ R2UR UR4, R30 ;\n /*3100*/ R2UR UR5, R31 ;\n /*3110*/ STG.E [R32.64], R39 ;\n /*3120*/ IADD3 R32, P0, R36, 0x8, RZ ;\n /*3130*/ IADD3.X R33, R35, RZ, RZ, P0, !PT ;\n /*3140*/ MOV R32, R32 ;\n /*3150*/ MOV R33, R33 ;\n /*3160*/ MOV R32, R32 ;\n /*3170*/ MOV R33, R33 ;\n /*3180*/ R2UR UR4, R30 ;\n /*3190*/ R2UR UR5, R31 ;\n /*31a0*/ LDG.E R32, [R32.64] ;\n /*31b0*/ FADD R32, R32, 1.02009998806386007928e+36 ;\n /*31c0*/ FADD R32, R32, R29 ;\n /*31d0*/ FADD R32, R34, R32 ;\n /*31e0*/ FADD R34, R25, R32 ;\n /*31f0*/ IADD3 R32, P0, R36, 0xc, RZ ;\n /*3200*/ IADD3.X R33, R35, RZ, RZ, P0, !PT ;\n /*3210*/ MOV R32, R32 ;\n /*3220*/ MOV R33, R33 ;\n /*3230*/ MOV R32, R32 ;\n /*3240*/ MOV R33, R33 ;\n /*3250*/ R2UR UR4, R30 ;\n /*3260*/ R2UR UR5, R31 ;\n /*3270*/ STG.E [R32.64], R24 ;\n /*3280*/ IADD3 R32, P0, R37, 0xc, RZ ;\n /*3290*/ IADD3.X R33, R38, RZ, RZ, P0, !PT ;\n /*32a0*/ MOV R32, R32 ;\n /*32b0*/ MOV R33, R33 ;\n /*32c0*/ MOV R32, R32 ;\n /*32d0*/ MOV R33, R33 ;\n /*32e0*/ R2UR UR4, R30 ;\n /*32f0*/ R2UR UR5, R31 ;\n /*3300*/ STG.E [R32.64], R39 ;\n /*3310*/ IADD3 R32, P0, R36, 0xc, RZ ;\n /*3320*/ IADD3.X R33, R35, RZ, RZ, P0, !PT ;\n /*3330*/ MOV R32, R32 ;\n /*3340*/ MOV R33, R33 ;\n /*3350*/ MOV R32, R32 ;\n /*3360*/ MOV R33, R33 ;\n /*3370*/ R2UR UR4, R30 ;\n /*3380*/ R2UR UR5, R31 ;\n /*3390*/ LDG.E R32, [R32.64] ;\n /*33a0*/ FADD R32, R32, 1.02009998806386007928e+36 ;\n /*33b0*/ FADD R32, R32, R29 ;\n /*33c0*/ FADD R32, R34, R32 ;\n /*33d0*/ FADD R32, R25, R32 ;\n /*33e0*/ IADD3 R27, R27, 0x4, RZ ;\n /*33f0*/ IADD3 R28, R28, -0x4, RZ ;\n /*3400*/ ISETP.NE.AND P0, PT, R28, RZ, PT ;\n /*3410*/ MOV R34, R32 ;\n /*3420*/ MOV R27, R27 ;\n /*3430*/ MOV R28, R28 ;\n /*3440*/ @P0 BRA `(.L_x_19) ;\n.L_x_18:\n /*3450*/ ISETP.EQ.AND P0, PT, R26, RZ, PT ;\n /*3460*/ @P0 BRA `(.L_x_3) ;\n /*3470*/ IMAD.WIDE R32, R27, 0x4, RZ ;\n /*3480*/ MOV R28, R32 ;\n /*3490*/ MOV R32, R33 ;\n /*34a0*/ IADD3 R27, P0, R18, R28, RZ ;\n /*34b0*/ IADD3.X R19, R19, R32, RZ, P0, !PT ;\n /*34c0*/ IADD3 R20, P0, R20, R28, RZ ;\n /*34d0*/ IADD3.X R18, R21, R32, RZ, P0, !PT ;\n /*34e0*/ MOV R21, R27 ;\n /*34f0*/ MOV R27, R19 ;\n /*3500*/ MOV R28, R20 ;\n /*3510*/ MOV R20, R18 ;\n.L_x_20:\n /*3520*/ MOV R18, R28 ;\n /*3530*/ MOV R19, R20 ;\n /*3540*/ MOV R18, R18 ;\n /*3550*/ MOV R19, R19 ;\n /*3560*/ R2UR UR4, R30 ;\n /*3570*/ R2UR UR5, R31 ;\n /*3580*/ STG.E [R18.64], R24 ;\n /*3590*/ MOV R32, 0x7b4476d0 ;\n /*35a0*/ MOV R18, R21 ;\n /*35b0*/ MOV R19, R27 ;\n /*35c0*/ MOV R18, R18 ;\n /*35d0*/ MOV R19, R19 ;\n /*35e0*/ R2UR UR4, R30 ;\n /*35f0*/ R2UR UR5, R31 ;\n /*3600*/ STG.E [R18.64], R32 ;\n /*3610*/ MOV R18, R28 ;\n /*3620*/ MOV R19, R20 ;\n /*3630*/ MOV R18, R18 ;\n /*3640*/ MOV R19, R19 ;\n /*3650*/ R2UR UR4, R30 ;\n /*3660*/ R2UR UR5, R31 ;\n /*3670*/ LDG.E R18, [R18.64] ;\n /*3680*/ FADD R18, R18, 1.02009998806386007928e+36 ;\n /*3690*/ FADD R18, R18, R29 ;\n /*36a0*/ FADD R18, R34, R18 ;\n /*36b0*/ FADD R18, R25, R18 ;\n /*36c0*/ IADD3 R21, P0, R21, 0x4, RZ ;\n /*36d0*/ IADD3.X R27, R27, RZ, RZ, P0, !PT ;\n /*36e0*/ IADD3 R19, P0, R28, 0x4, RZ ;\n /*36f0*/ IADD3.X R20, R20, RZ, RZ, P0, !PT ;\n /*3700*/ IADD3 R26, R26, -0x1, RZ ;\n /*3710*/ ISETP.EQ.AND P0, PT, R26, RZ, PT ;\n /*3720*/ MOV R34, R18 ;\n /*3730*/ MOV R21, R21 ;\n /*3740*/ MOV R27, R27 ;\n /*3750*/ MOV R28, R19 ;\n /*3760*/ MOV R20, R20 ;\n /*3770*/ MOV R26, R26 ;\n /*3780*/ @P0 BRA `(.L_x_3) ;\n /*3790*/ BRA `(.L_x_20) ;\n.L_x_3:\n /*37a0*/ FMUL R3, R3, RZ ;\n /*37b0*/ FSETP.LEU.AND P0, PT, R34, R3, PT ;\n /*37c0*/ BSSY B0, `(.L_x_21) ;\n /*37d0*/ @P0 BRA `(.L_x_22) ;\n /*37e0*/ FADD R9, R9, RZ ;\n /*37f0*/ FMUL R9, R9, 19.933000564575195312 ;\n /*3800*/ MOV R8, R8 ;\n /*3810*/ MOV R9, R9 ;\n /*3820*/ MOV R8, R8 ;\n /*3830*/ MOV R9, R9 ;\n /*3840*/ MOV R3, R9 ;\n /*3850*/ MUFU.RCP R18, R3 ;\n /*3860*/ FADD R3, -RZ, -R3 ;\n /*3870*/ MOV R3, R3 ;\n /*3880*/ MOV R19, 0x3f800000 ;\n /*3890*/ FFMA R19, R3, R18, R19 ;\n /*38a0*/ FCHK P0, R8, R9 ;\n /*38b0*/ FFMA R19, R18, R19, R18 ;\n /*38c0*/ MOV R18, RZ ;\n /*38d0*/ MOV R8, R8 ;\n /*38e0*/ FFMA R18, R8, R19, R18 ;\n /*38f0*/ FFMA R3, R3, R18, R8 ;\n /*3900*/ FFMA R3, R3, R19, R18 ;\n /*3910*/ MOV R3, R3 ;\n /*3920*/ MOV R8, R8 ;\n /*3930*/ MOV R9, R9 ;\n /*3940*/ MOV R3, R3 ;\n /*3950*/ @P0 BRA `(.L_x_23) ;\n /*3960*/ BRA `(.L_x_24) ;\n.L_x_23:\n /*3970*/ MOV R8, R8 ;\n /*3980*/ MOV R9, R9 ;\n /*3990*/ MOV R41, R8 ;\n /*39a0*/ MOV R27, R9 ;\n /*39b0*/ MOV R26, 0x39d0 ;\n /*39c0*/ CALL.REL.NOINC `($__internal_2_$__cuda_sm3x_div_rn_noftz_f32_slowpath) ;\n /*39d0*/ MOV R3, R25 ;\n /*39e0*/ MOV R3, R3 ;\n /*39f0*/ MOV R3, R3 ;\n.L_x_24:\n /*3a00*/ MOV R3, R3 ;\n /*3a10*/ FADD R3, R3, 1.5774000234896991286e-36 ;\n /*3a20*/ MOV R3, R3 ;\n /*3a30*/ MOV R3, R3 ;\n /*3a40*/ MOV R3, R3 ;\n /*3a50*/ MOV R3, R3 ;\n /*3a60*/ MUFU.RSQ R8, R3 ;\n /*3a70*/ MOV R3, R3 ;\n /*3a80*/ IADD3 R9, R3, -0xd000000, RZ ;\n /*3a90*/ MOV R18, 0x727fffff ;\n /*3aa0*/ ISETP.LE.U32.AND P0, PT, R9, R18, PT ;\n /*3ab0*/ MOV R3, R3 ;\n /*3ac0*/ MOV R8, R8 ;\n /*3ad0*/ BSSY B1, `(.L_x_25) ;\n /*3ae0*/ @P0 BRA `(.L_x_26) ;\n /*3af0*/ MOV R3, R3 ;\n /*3b00*/ MOV R3, R3 ;\n /*3b10*/ MOV R20, 0x3b30 ;\n /*3b20*/ CALL.REL.NOINC `($__internal_1_$__cuda_sm20_sqrt_rn_f32_slowpath) ;\n /*3b30*/ MOV R3, R3 ;\n /*3b40*/ MOV R3, R3 ;\n /*3b50*/ MOV R3, R3 ;\n /*3b60*/ MOV R3, R3 ;\n /*3b70*/ BRA `(.L_x_27) ;\n.L_x_26:\n /*3b80*/ FMUL.FTZ R9, R8, R3 ;\n /*3b90*/ FADD R18, -RZ, -R9 ;\n /*3ba0*/ MOV R18, R18 ;\n /*3bb0*/ FFMA R18, R18, R9, R3 ;\n /*3bc0*/ MOV R3, 0x3f000000 ;\n /*3bd0*/ FMUL.FTZ R3, R8, R3 ;\n /*3be0*/ FFMA R3, R18, R3, R9 ;\n /*3bf0*/ MOV R3, R3 ;\n.L_x_27:\n /*3c00*/ BSYNC B1 ;\n.L_x_25:\n /*3c10*/ MOV R3, R3 ;\n /*3c20*/ MOV R3, R3 ;\n /*3c30*/ MOV R3, R3 ;\n /*3c40*/ MOV R3, R3 ;\n /*3c50*/ FADD R3, R3, R5 ;\n /*3c60*/ FMUL R5, R3, 0.63661974668502807617 ;\n /*3c70*/ F2I.NTZ R5, R5 ;\n /*3c80*/ I2FP.F32.S32 R8, R5 ;\n /*3c90*/ MOV R9, 0xbfc90fda ;\n /*3ca0*/ FFMA R9, R8, R9, R3 ;\n /*3cb0*/ MOV R18, 0xb3a22168 ;\n /*3cc0*/ FFMA R9, R8, R18, R9 ;\n /*3cd0*/ MOV R18, 0xa7c234c5 ;\n /*3ce0*/ FFMA R9, R8, R18, R9 ;\n /*3cf0*/ FADD R8, -RZ, |R3| ;\n /*3d00*/ MOV R8, R8 ;\n /*3d10*/ FSETP.LTU.AND P0, PT, R8, 105615, PT ;\n /*3d20*/ MOV R18, R3 ;\n /*3d30*/ MOV R3, R5 ;\n /*3d40*/ MOV R9, R9 ;\n /*3d50*/ MOV R8, R8 ;\n /*3d60*/ BSSY B1, `(.L_x_28) ;\n /*3d70*/ @P0 BRA `(.L_x_29) ;\n /*3d80*/ FSETP.EQ.AND P0, PT, R8, +INF , PT ;\n /*3d90*/ @P0 BRA `(.L_x_30) ;\n /*3da0*/ BRA `(.L_x_31) ;\n.L_x_30:\n /*3db0*/ MOV R3, RZ ;\n /*3dc0*/ FMUL R3, R18, R3 ;\n /*3dd0*/ MOV R5, RZ ;\n /*3de0*/ MOV R9, R3 ;\n /*3df0*/ MOV R3, R5 ;\n /*3e00*/ BRA `(.L_x_29) ;\n.L_x_31:\n /*3e10*/ MOV R3, R18 ;\n /*3e20*/ SHF.R.U32.HI R5, RZ, 0x17, R3 ;\n /*3e30*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ;\n /*3e40*/ IADD3 R5, R5, -0x80, RZ ;\n /*3e50*/ SHF.L.U32 R8, R3, 0x8, RZ ;\n /*3e60*/ LOP3.LUT R8, R8, 0x80000000, RZ, 0xfc, !PT ;\n /*3e70*/ SHF.R.U32.HI R9, RZ, 0x5, R5 ;\n /*3e80*/ MOV R25, RZ ;\n /*3e90*/ MOV R29, RZ ;\n /*3ea0*/ MOV R18, RZ ;\n /*3eb0*/ MOV R21, c[0x4][0x10] ;\n /*3ec0*/ MOV R24, c[0x4][0x14] ;\n /*3ed0*/ MOV R27, R22 ;\n /*3ee0*/ MOV R28, R23 ;\n /*3ef0*/ MOV R3, R3 ;\n /*3f00*/ MOV R5, R5 ;\n /*3f10*/ MOV R20, R8 ;\n /*3f20*/ MOV R8, R9 ;\n /*3f30*/ MOV R25, R25 ;\n /*3f40*/ MOV R29, R29 ;\n /*3f50*/ MOV R9, R18 ;\n /*3f60*/ MOV R21, R21 ;\n /*3f70*/ MOV R24, R24 ;\n /*3f80*/ MOV R27, R27 ;\n /*3f90*/ MOV R28, R28 ;\n.L_x_32:\n /*3fa0*/ MOV R18, R21 ;\n /*3fb0*/ MOV R19, R24 ;\n /*3fc0*/ MOV R18, R18 ;\n /*3fd0*/ MOV R19, R19 ;\n /*3fe0*/ R2UR UR4, R30 ;\n /*3ff0*/ R2UR UR5, R31 ;\n /*4000*/ LDG.E.CONSTANT R18, [R18.64] ;\n /*4010*/ IMAD.U32 R19, R18, R20, RZ ;\n /*4020*/ IMAD.HI.U32 R18, R18, R20, RZ ;\n /*4030*/ MOV R19, R19 ;\n /*4040*/ MOV R26, R18 ;\n /*4050*/ IADD3 R18, P0, R19, R25, RZ ;\n /*4060*/ IADD3.X R26, R26, R29, RZ, P0, !PT ;\n /*4070*/ SHF.R.U64 R25, R18, 0x20, R26 ;\n /*4080*/ SHF.R.U32.HI R26, RZ, 0x20, R26 ;\n /*4090*/ MOV R19, R27 ;\n /*40a0*/ MOV R28, R28 ;\n /*40b0*/ MOV R18, R18 ;\n /*40c0*/ STL [R19], R18 ;\n /*40d0*/ IADD3 R21, P0, R21, 0x4, RZ ;\n /*40e0*/ IADD3.X R24, R24, RZ, RZ, P0, !PT ;\n /*40f0*/ IADD3 R18, P0, R27, 0x4, RZ ;\n /*4100*/ IADD3.X R19, R28, RZ, RZ, P0, !PT ;\n /*4110*/ IADD3 R9, R9, 0x1, RZ ;\n /*4120*/ ISETP.NE.AND P0, PT, R9, 0x6, PT ;\n /*4130*/ MOV R25, R25 ;\n /*4140*/ MOV R29, R26 ;\n /*4150*/ MOV R21, R21 ;\n /*4160*/ MOV R24, R24 ;\n /*4170*/ MOV R27, R18 ;\n /*4180*/ MOV R28, R19 ;\n /*4190*/ MOV R9, R9 ;\n /*41a0*/ @P0 BRA `(.L_x_32) ;\n /*41b0*/ IADD3 R18, P0, R22, 0x18, RZ ;\n /*41c0*/ IADD3.X R9, R23, RZ, RZ, P0, !PT ;\n /*41d0*/ MOV R18, R18 ;\n /*41e0*/ MOV R9, R9 ;\n /*41f0*/ MOV R9, R25 ;\n /*4200*/ STL [R18], R9 ;\n /*4210*/ MOV R9, 0x4 ;\n /*4220*/ IADD3 R18, R9, -R8, RZ ;\n /*4230*/ MOV R9, 0x6 ;\n /*4240*/ IADD3 R9, R9, -R8, RZ ;\n /*4250*/ IMAD.WIDE R8, R9, 0x4, RZ ;\n /*4260*/ MOV R19, R8 ;\n /*4270*/ MOV R8, R9 ;\n /*4280*/ IADD3 R9, P0, R22, R19, RZ ;\n /*4290*/ IADD3.X R19, R23, R8, RZ, P0, !PT ;\n /*42a0*/ MOV R8, R9 ;\n /*42b0*/ MOV R19, R19 ;\n /*42c0*/ LDL R8, [R8] ;\n /*42d0*/ IADD3 R9, P0, R9, -0x4, RZ ;\n /*42e0*/ IADD3.X R19, R19, -0x1, RZ, P0, !PT ;\n /*42f0*/ MOV R9, R9 ;\n /*4300*/ MOV R19, R19 ;\n /*4310*/ LDL R9, [R9] ;\n /*4320*/ LOP3.LUT R5, R5, 0x1f, RZ, 0xc0, !PT ;\n /*4330*/ ISETP.EQ.AND P0, PT, R5, RZ, PT ;\n /*4340*/ MOV R18, R18 ;\n /*4350*/ MOV R8, R8 ;\n /*4360*/ MOV R19, R9 ;\n /*4370*/ MOV R5, R5 ;\n /*4380*/ BSSY B2, `(.L_x_33) ;\n /*4390*/ @P0 BRA `(.L_x_34) ;\n /*43a0*/ MOV R9, 0x20 ;\n /*43b0*/ IADD3 R20, R9, -R5, RZ ;\n /*43c0*/ SHF.R.U32.HI R9, RZ, R20, R19 ;\n /*43d0*/ SHF.L.U32 R8, R8, R5, RZ ;\n /*43e0*/ IADD3 R21, R9, R8, RZ ;\n /*43f0*/ IMAD.WIDE R8, R18, 0x4, RZ ;\n /*4400*/ MOV R18, R8 ;\n /*4410*/ MOV R9, R9 ;\n /*4420*/ IADD3 R8, P0, R22, R18, RZ ;\n /*4430*/ IADD3.X R9, R23, R9, RZ, P0, !PT ;\n /*4440*/ MOV R8, R8 ;\n /*4450*/ MOV R9, R9 ;\n /*4460*/ LDL R8, [R8] ;\n /*4470*/ SHF.R.U32.HI R8, RZ, R20, R8 ;\n /*4480*/ SHF.L.U32 R5, R19, R5, RZ ;\n /*4490*/ IADD3 R5, R8, R5, RZ ;\n /*44a0*/ MOV R8, R21 ;\n /*44b0*/ MOV R19, R5 ;\n.L_x_34:\n /*44c0*/ BSYNC B2 ;\n.L_x_33:\n /*44d0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;\n /*44e0*/ SHF.R.U32.HI R5, RZ, 0x1e, R19 ;\n /*44f0*/ SHF.L.U32 R9, R8, 0x2, RZ ;\n /*4500*/ LOP3.LUT R5, R5, R9, RZ, 0xfc, !PT ;\n /*4510*/ SHF.R.U32.HI R18, RZ, 0x1f, R5 ;\n /*4520*/ SHF.R.U32.HI R8, RZ, 0x1e, R8 ;\n /*4530*/ IADD3 R8, R18, R8, RZ ;\n /*4540*/ IADD3 R9, RZ, -R8, RZ ;\n /*4550*/ MOV R9, R9 ;\n /*4560*/ MOV R9, R9 ;\n /*4570*/ ISETP.EQ.AND P0, PT, R3, RZ, PT ;\n /*4580*/ SEL R20, R8, R9, P0 ;\n /*4590*/ ISETP.NE.AND P0, PT, R18, RZ, PT ;\n /*45a0*/ LOP3.LUT R8, R3, 0x80000000, RZ, 0x3c, !PT ;\n /*45b0*/ SEL R21, R8, R3, P0 ;\n /*45c0*/ SEL R3, RZ, 0xffffffff, !P0 ;\n /*45d0*/ LOP3.LUT R5, R5, R3, RZ, 0x3c, !PT ;\n /*45e0*/ SHF.L.U32 R19, R19, 0x2, RZ ;\n /*45f0*/ LOP3.LUT R19, R19, R3, RZ, 0x3c, !PT ;\n /*4600*/ MOV R5, R5 ;\n /*4610*/ MOV R8, R5 ;\n /*4620*/ MOV R9, RZ ;\n /*4630*/ MOV R19, R19 ;\n /*4640*/ MOV R18, R19 ;\n /*4650*/ MOV R19, RZ ;\n /*4660*/ MOV R8, R8 ;\n /*4670*/ MOV R9, R9 ;\n /*4680*/ MOV R18, R18 ;\n /*4690*/ MOV R19, R19 ;\n /*46a0*/ MOV R22, 0x20 ;\n /*46b0*/ MOV R23, 0x20 ;\n /*46c0*/ MOV R3, R20 ;\n /*46d0*/ MOV R5, R21 ;\n /*46e0*/ MOV R8, R8 ;\n /*46f0*/ MOV R9, R9 ;\n /*4700*/ MOV R18, R18 ;\n /*4710*/ MOV R19, R19 ;\n /*4720*/ MOV R22, R22 ;\n /*4730*/ MOV R23, R23 ;\n /*4740*/ MOV R20, R8 ;\n /*4750*/ MOV R26, R9 ;\n /*4760*/ MOV R9, R20 ;\n /*4770*/ MOV R26, R26 ;\n /*4780*/ MOV R24, R18 ;\n /*4790*/ MOV R25, R19 ;\n /*47a0*/ MOV R24, R24 ;\n /*47b0*/ MOV R25, R25 ;\n /*47c0*/ MOV R22, R22 ;\n /*47d0*/ MOV R23, R23 ;\n /*47e0*/ MOV R23, R23 ;\n /*47f0*/ SHF.R.S32.HI R8, RZ, 0x1f, R23 ;\n /*4800*/ MOV R20, R23 ;\n /*4810*/ MOV R8, R8 ;\n /*4820*/ MOV R21, 0x1 ;\n /*4830*/ SHF.L.U64.HI R21, R21, R20, RZ ;\n /*4840*/ MOV R8, 0x1 ;\n /*4850*/ SHF.L.U32 R20, R8, R20, RZ ;\n /*4860*/ IADD3 R20, P0, R20, -0x1, RZ ;\n /*4870*/ IADD3.X R21, R21, -0x1, RZ, P0, !PT ;\n /*4880*/ LOP3.LUT R18, R20, R9, RZ, 0xc0, !PT ;\n /*4890*/ LOP3.LUT R19, R21, R26, RZ, 0xc0, !PT ;\n /*48a0*/ MOV R8, R22 ;\n /*48b0*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ;\n /*48c0*/ MOV R8, R8 ;\n /*48d0*/ MOV R9, R9 ;\n /*48e0*/ SHF.L.U64.HI R19, R18, R8, R19 ;\n /*48f0*/ SHF.L.U32 R18, R18, R8, RZ ;\n /*4900*/ MOV R22, R22 ;\n /*4910*/ SHF.R.S32.HI R8, RZ, 0x1f, R22 ;\n /*4920*/ MOV R22, R22 ;\n /*4930*/ MOV R8, R8 ;\n /*4940*/ SHF.L.U64.HI R9, R20, R22, R21 ;\n /*4950*/ SHF.L.U32 R8, R20, R22, RZ ;\n /*4960*/ LOP3.LUT R8, RZ, R8, RZ, 0x33, !PT ;\n /*4970*/ LOP3.LUT R9, RZ, R9, RZ, 0x33, !PT ;\n /*4980*/ LOP3.LUT R8, R24, R8, RZ, 0xc0, !PT ;\n /*4990*/ LOP3.LUT R9, R25, R9, RZ, 0xc0, !PT ;\n /*49a0*/ LOP3.LUT R8, R18, R8, RZ, 0xfc, !PT ;\n /*49b0*/ LOP3.LUT R9, R19, R9, RZ, 0xfc, !PT ;\n /*49c0*/ MOV R8, R8 ;\n /*49d0*/ MOV R9, R9 ;\n /*49e0*/ MOV R8, R8 ;\n /*49f0*/ MOV R9, R9 ;\n /*4a00*/ MOV R8, R8 ;\n /*4a10*/ MOV R9, R9 ;\n /*4a20*/ I2F.F64.S64 R8, R8 ;\n /*4a30*/ DMUL R8, R8, c[0x2][0x0] ;\n /*4a40*/ F2F.F32.F64 R8, R8 ;\n /*4a50*/ ISETP.EQ.AND P0, PT, R5, RZ, PT ;\n /*4a60*/ FADD R5, -RZ, -R8 ;\n /*4a70*/ MOV R5, R5 ;\n /*4a80*/ FSEL R5, R8, R5, P0 ;\n /*4a90*/ MOV R9, R5 ;\n /*4aa0*/ BRA `(.L_x_29) ;\n.L_x_29:\n /*4ab0*/ BSYNC B1 ;\n.L_x_28:\n /*4ac0*/ LOP3.LUT R5, R3, 0x1, RZ, 0xc0, !PT ;\n /*4ad0*/ ISETP.EQ.AND P0, PT, R5, RZ, PT ;\n /*4ae0*/ FSEL R5, R9, 1, P0 ;\n /*4af0*/ FMUL R9, R9, R9 ;\n /*4b00*/ MOV R8, 0xb94d4153 ;\n /*4b10*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x80, 0x0 ;\n /*4b20*/ MOV R5, R5 ;\n /*4b30*/ MOV R9, R9 ;\n /*4b40*/ MOV R8, R8 ;\n /*4b50*/ BSSY B1, `(.L_x_35) ;\n /*4b60*/ @P0 BRA `(.L_x_36) ;\n /*4b70*/ MOV R8, 0xbab607ed ;\n /*4b80*/ MOV R18, 0x37cbac00 ;\n /*4b90*/ FFMA R8, R18, R9, R8 ;\n /*4ba0*/ MOV R8, R8 ;\n.L_x_36:\n /*4bb0*/ BSYNC B1 ;\n.L_x_35:\n /*4bc0*/ MOV R18, 0x3c0885e4 ;\n /*4bd0*/ FSEL R18, R18, 0.041666727513074874878, P0 ;\n /*4be0*/ FFMA R8, R8, R9, R18 ;\n /*4bf0*/ MOV R18, 0x3e2aaaa8 ;\n /*4c00*/ FSEL R18, -R18, -0.4999999701976776123, P0 ;\n /*4c10*/ FFMA R8, R8, R9, R18 ;\n /*4c20*/ MOV R18, RZ ;\n /*4c30*/ FFMA R9, R9, R5, R18 ;\n /*4c40*/ FFMA R8, R8, R9, R5 ;\n /*4c50*/ LOP3.LUT R3, R3, 0x2, RZ, 0xc0, !PT ;\n /*4c60*/ ISETP.EQ.AND P0, PT, R3, RZ, PT ;\n /*4c70*/ MOV R18, R18 ;\n /*4c80*/ MOV R8, R8 ;\n /*4c90*/ BSSY B1, `(.L_x_37) ;\n /*4ca0*/ @P0 BRA `(.L_x_38) ;\n /*4cb0*/ MOV R3, 0xbf800000 ;\n /*4cc0*/ FFMA R3, R8, R3, R18 ;\n /*4cd0*/ MOV R8, R3 ;\n.L_x_38:\n /*4ce0*/ BSYNC B1 ;\n.L_x_37:\n /*4cf0*/ MOV R3, 0x3e3c1e79 ;\n /*4d00*/ MOV R3, R3 ;\n /*4d10*/ MOV R8, R8 ;\n /*4d20*/ MOV R3, R3 ;\n /*4d30*/ MOV R8, R8 ;\n /*4d40*/ MOV R5, R8 ;\n /*4d50*/ MUFU.RCP R9, R5 ;\n /*4d60*/ FADD R5, -RZ, -R5 ;\n /*4d70*/ MOV R5, R5 ;\n /*4d80*/ MOV R18, 0x3f800000 ;\n /*4d90*/ FFMA R18, R5, R9, R18 ;\n /*4da0*/ FCHK P0, R3, R8 ;\n /*4db0*/ FFMA R18, R9, R18, R9 ;\n /*4dc0*/ MOV R9, RZ ;\n /*4dd0*/ MOV R3, R3 ;\n /*4de0*/ FFMA R9, R3, R18, R9 ;\n /*4df0*/ FFMA R5, R5, R9, R3 ;\n /*4e00*/ FFMA R5, R5, R18, R9 ;\n /*4e10*/ MOV R5, R5 ;\n /*4e20*/ MOV R3, R3 ;\n /*4e30*/ MOV R8, R8 ;\n /*4e40*/ MOV R5, R5 ;\n /*4e50*/ BSSY B2, `(.L_x_39) ;\n /*4e60*/ @P0 BRA `(.L_x_40) ;\n /*4e70*/ BRA `(.L_x_41) ;\n.L_x_40:\n /*4e80*/ MOV R3, R3 ;\n /*4e90*/ MOV R8, R8 ;\n /*4ea0*/ MOV R41, R3 ;\n /*4eb0*/ MOV R27, R8 ;\n /*4ec0*/ MOV R26, 0x4ee0 ;\n /*4ed0*/ CALL.REL.NOINC `($__internal_2_$__cuda_sm3x_div_rn_noftz_f32_slowpath) ;\n /*4ee0*/ MOV R3, R25 ;\n /*4ef0*/ MOV R3, R3 ;\n /*4f00*/ MOV R5, R3 ;\n.L_x_41:\n /*4f10*/ BSYNC B2 ;\n.L_x_39:\n /*4f20*/ MOV R5, R5 ;\n /*4f30*/ FADD R4, R5, R4 ;\n /*4f40*/ FADD R4, R4, 1.9453000163805458316e-36 ;\n /*4f50*/ FMUL R4, R4, 2.8430516607613753877e-08 ;\n /*4f60*/ MOV R34, R4 ;\n.L_x_22:\n /*4f70*/ BSYNC B0 ;\n.L_x_21:\n /*4f80*/ FADD R10, R10, -R11 ;\n /*4f90*/ FADD R10, R10, -INF ;\n /*4fa0*/ FSETP.NEU.AND P0, PT, R34, R10, PT ;\n /*4fb0*/ BSSY B0, `(.L_x_42) ;\n /*4fc0*/ @P0 BRA `(.L_x_43) ;\n /*4fd0*/ FADD R14, R14, R15 ;\n /*4fe0*/ FSETP.LT.AND P0, PT, R14, 1.175494350822287508e-38, PT ;\n /*4ff0*/ FMUL R3, R14, 8388608 ;\n /*5000*/ FSEL R3, R3, R14, P0 ;\n /*5010*/ FSEL R4, RZ, -23, !P0 ;\n /*5020*/ MOV R3, R3 ;\n /*5030*/ IADD3 R5, R3, -0x3f2aaaab, RZ ;\n /*5040*/ LOP3.LUT R5, R5, 0xff800000, RZ, 0xc0, !PT ;\n /*5050*/ IADD3 R8, R3, -R5, RZ ;\n /*5060*/ MOV R8, R8 ;\n /*5070*/ I2FP.F32.S32 R5, R5 ;\n /*5080*/ MOV R9, 0x34000000 ;\n /*5090*/ FFMA R4, R5, R9, R4 ;\n /*50a0*/ FADD R8, R8, -1 ;\n /*50b0*/ MOV R5, 0x3e1039f6 ;\n /*50c0*/ MOV R9, 0xbe055027 ;\n /*50d0*/ FFMA R5, R9, R8, R5 ;\n /*50e0*/ MOV R9, 0xbdf8cdcc ;\n /*50f0*/ FFMA R5, R5, R8, R9 ;\n /*5100*/ MOV R9, 0x3e0f2955 ;\n /*5110*/ FFMA R5, R5, R8, R9 ;\n /*5120*/ MOV R9, 0xbe2ad8b9 ;\n /*5130*/ FFMA R5, R5, R8, R9 ;\n /*5140*/ MOV R9, 0x3e4ced0b ;\n /*5150*/ FFMA R5, R5, R8, R9 ;\n /*5160*/ MOV R9, 0xbe7fff22 ;\n /*5170*/ FFMA R5, R5, R8, R9 ;\n /*5180*/ MOV R9, 0x3eaaaa78 ;\n /*5190*/ FFMA R5, R5, R8, R9 ;\n /*51a0*/ MOV R9, 0xbf000000 ;\n /*51b0*/ FFMA R5, R5, R8, R9 ;\n /*51c0*/ FMUL R5, R8, R5 ;\n /*51d0*/ FFMA R5, R5, R8, R8 ;\n /*51e0*/ MOV R8, 0x3f317218 ;\n /*51f0*/ FFMA R4, R4, R8, R5 ;\n /*5200*/ ISETP.LT.U32.AND P0, PT, R3, 0x7f800000, PT ;\n /*5210*/ MOV R3, R3 ;\n /*5220*/ MOV R4, R4 ;\n /*5230*/ @P0 BRA `(.L_x_44) ;\n /*5240*/ MOV R4, 0x7f800000 ;\n /*5250*/ FFMA R4, R3, R4, R4 ;\n /*5260*/ MOV R4, R4 ;\n.L_x_44:\n /*5270*/ FMUL R4, R4, 0.43429449200630187988 ;\n /*5280*/ FSETP.EQ.AND P0, PT, R3, RZ, PT ;\n /*5290*/ FSEL R3, R4, -INF , !P0 ;\n /*52a0*/ MOV R4, 0xf9b6f2ac ;\n /*52b0*/ MOV R4, R4 ;\n /*52c0*/ MOV R5, RZ ;\n /*52d0*/ MOV R4, R4 ;\n /*52e0*/ MOV R11, R5 ;\n /*52f0*/ MOV R5, R5 ;\n /*5300*/ MUFU.RCP R8, R5 ;\n /*5310*/ FADD R9, -RZ, -R5 ;\n /*5320*/ MOV R9, R9 ;\n /*5330*/ MOV R10, 0x3f800000 ;\n /*5340*/ FFMA R10, R9, R8, R10 ;\n /*5350*/ FCHK P0, R4, R11 ;\n /*5360*/ FFMA R10, R8, R10, R8 ;\n /*5370*/ MOV R8, RZ ;\n /*5380*/ MOV R4, R4 ;\n /*5390*/ FFMA R8, R4, R10, R8 ;\n /*53a0*/ FFMA R9, R9, R8, R4 ;\n /*53b0*/ FFMA R9, R9, R10, R8 ;\n /*53c0*/ MOV R9, R9 ;\n /*53d0*/ MOV R3, R3 ;\n /*53e0*/ MOV R4, R4 ;\n /*53f0*/ MOV R5, R5 ;\n /*5400*/ MOV R9, R9 ;\n /*5410*/ @P0 BRA `(.L_x_45) ;\n /*5420*/ BRA `(.L_x_46) ;\n.L_x_45:\n /*5430*/ MOV R4, R4 ;\n /*5440*/ MOV R5, R5 ;\n /*5450*/ MOV R41, R4 ;\n /*5460*/ MOV R27, R5 ;\n /*5470*/ MOV R26, 0x5490 ;\n /*5480*/ CALL.REL.NOINC `($__internal_2_$__cuda_sm3x_div_rn_noftz_f32_slowpath) ;\n /*5490*/ MOV R4, R25 ;\n /*54a0*/ MOV R4, R4 ;\n /*54b0*/ MOV R9, R4 ;\n.L_x_46:\n /*54c0*/ MOV R9, R9 ;\n /*54d0*/ MOV R9, R9 ;\n /*54e0*/ MOV R4, 0xd526120 ;\n /*54f0*/ MOV R9, R9 ;\n /*5500*/ MOV R11, R4 ;\n /*5510*/ MOV R4, R4 ;\n /*5520*/ MUFU.RCP R5, R4 ;\n /*5530*/ FADD R8, -RZ, -R4 ;\n /*5540*/ MOV R8, R8 ;\n /*5550*/ MOV R10, 0x3f800000 ;\n /*5560*/ FFMA R10, R8, R5, R10 ;\n /*5570*/ FCHK P0, R9, R11 ;\n /*5580*/ FFMA R10, R5, R10, R5 ;\n /*5590*/ MOV R5, RZ ;\n /*55a0*/ MOV R9, R9 ;\n /*55b0*/ FFMA R5, R9, R10, R5 ;\n /*55c0*/ FFMA R8, R8, R5, R9 ;\n /*55d0*/ FFMA R8, R8, R10, R5 ;\n /*55e0*/ MOV R8, R8 ;\n /*55f0*/ MOV R9, R9 ;\n /*5600*/ MOV R4, R4 ;\n /*5610*/ MOV R8, R8 ;\n /*5620*/ BSSY B2, `(.L_x_47) ;\n /*5630*/ @P0 BRA `(.L_x_48) ;\n /*5640*/ BRA `(.L_x_49) ;\n.L_x_48:\n /*5650*/ MOV R9, R9 ;\n /*5660*/ MOV R4, R4 ;\n /*5670*/ MOV R41, R9 ;\n /*5680*/ MOV R27, R4 ;\n /*5690*/ MOV R26, 0x56b0 ;\n /*56a0*/ CALL.REL.NOINC `($__internal_2_$__cuda_sm3x_div_rn_noftz_f32_slowpath) ;\n /*56b0*/ MOV R4, R25 ;\n /*56c0*/ MOV R4, R4 ;\n /*56d0*/ MOV R8, R4 ;\n.L_x_49:\n /*56e0*/ BSYNC B2 ;\n.L_x_47:\n /*56f0*/ MOV R8, R8 ;\n /*5700*/ FADD R8, R16, R8 ;\n /*5710*/ FRND.CEIL R8, R8 ;\n /*5720*/ MOV R4, 0x6cb07d44 ;\n /*5730*/ MOV R4, R4 ;\n /*5740*/ MOV R8, R8 ;\n /*5750*/ MOV R4, R4 ;\n /*5760*/ MOV R8, R8 ;\n /*5770*/ MOV R5, R8 ;\n /*5780*/ MUFU.RCP R9, R5 ;\n /*5790*/ FADD R5, -RZ, -R5 ;\n /*57a0*/ MOV R5, R5 ;\n /*57b0*/ MOV R10, 0x3f800000 ;\n /*57c0*/ FFMA R10, R5, R9, R10 ;\n /*57d0*/ FCHK P0, R4, R8 ;\n /*57e0*/ FFMA R10, R9, R10, R9 ;\n /*57f0*/ MOV R9, RZ ;\n /*5800*/ MOV R4, R4 ;\n /*5810*/ FFMA R9, R4, R10, R9 ;\n /*5820*/ FFMA R5, R5, R9, R4 ;\n /*5830*/ FFMA R5, R5, R10, R9 ;\n /*5840*/ MOV R5, R5 ;\n /*5850*/ MOV R4, R4 ;\n /*5860*/ MOV R8, R8 ;\n /*5870*/ MOV R5, R5 ;\n /*5880*/ BSSY B2, `(.L_x_50) ;\n /*5890*/ @P0 BRA `(.L_x_51) ;\n /*58a0*/ BRA `(.L_x_52) ;\n.L_x_51:\n /*58b0*/ MOV R4, R4 ;\n /*58c0*/ MOV R8, R8 ;\n /*58d0*/ MOV R41, R4 ;\n /*58e0*/ MOV R27, R8 ;\n /*58f0*/ MOV R26, 0x5910 ;\n /*5900*/ CALL.REL.NOINC `($__internal_2_$__cuda_sm3x_div_rn_noftz_f32_slowpath) ;\n /*5910*/ MOV R4, R25 ;\n /*5920*/ MOV R4, R4 ;\n /*5930*/ MOV R5, R4 ;\n.L_x_52:\n /*5940*/ BSYNC B2 ;\n.L_x_50:\n /*5950*/ MOV R5, R5 ;\n /*5960*/ FADD R8, -RZ, |R5| ;\n /*5970*/ MOV R8, R8 ;\n /*5980*/ FADD R9, -RZ, |R3| ;\n /*5990*/ MOV R9, R9 ;\n /*59a0*/ FSETP.EQ.AND P0, PT, R8, RZ, PT ;\n /*59b0*/ FSETP.EQ.AND P1, PT, R9, RZ, PT ;\n /*59c0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x80, 0x0 ;\n /*59d0*/ MOV R4, R5 ;\n /*59e0*/ MOV R5, R8 ;\n /*59f0*/ MOV R8, R9 ;\n /*5a00*/ BSSY B2, `(.L_x_53) ;\n /*5a10*/ @P0 BRA `(.L_x_54) ;\n /*5a20*/ BRA `(.L_x_55) ;\n.L_x_54:\n /*5a30*/ MOV R4, R4 ;\n /*5a40*/ SHF.R.S32.HI R4, RZ, 0x1f, R4 ;\n /*5a50*/ LOP3.LUT R4, R4, 0x40490fdb, RZ, 0xc0, !PT ;\n /*5a60*/ MOV R3, R3 ;\n /*5a70*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;\n /*5a80*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ;\n /*5a90*/ MOV R3, R3 ;\n /*5aa0*/ MOV R3, R3 ;\n /*5ab0*/ BRA `(.L_x_56) ;\n.L_x_55:\n /*5ac0*/ FSETP.EQ.AND P0, PT, R5, +INF , PT ;\n /*5ad0*/ FSETP.EQ.AND P1, PT, R8, +INF , PT ;\n /*5ae0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x80, 0x0 ;\n /*5af0*/ @P0 BRA `(.L_x_57) ;\n /*5b00*/ BRA `(.L_x_58) ;\n.L_x_57:\n /*5b10*/ MOV R4, R4 ;\n /*5b20*/ ISETP.LT.AND P0, PT, R4, RZ, PT ;\n /*5b30*/ MOV R4, 0x4016cbe4 ;\n /*5b40*/ SEL R4, R4, 0x3f490fdb, P0 ;\n /*5b50*/ MOV R3, R3 ;\n /*5b60*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;\n /*5b70*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ;\n /*5b80*/ MOV R3, R3 ;\n /*5b90*/ MOV R3, R3 ;\n /*5ba0*/ BRA `(.L_x_56) ;\n.L_x_58:\n /*5bb0*/ FMNMX R9, R8, R5, !PT ;\n /*5bc0*/ FMNMX R10, R8, R5, PT ;\n /*5bd0*/ MOV R10, R10 ;\n /*5be0*/ MOV R9, R9 ;\n /*5bf0*/ MOV R10, R10 ;\n /*5c00*/ MOV R16, R9 ;\n /*5c10*/ MOV R9, R9 ;\n /*5c20*/ MUFU.RCP R11, R9 ;\n /*5c30*/ FADD R14, -RZ, -R9 ;\n /*5c40*/ MOV R14, R14 ;\n /*5c50*/ MOV R15, 0x3f800000 ;\n /*5c60*/ FFMA R15, R14, R11, R15 ;\n /*5c70*/ FCHK P0, R10, R16 ;\n /*5c80*/ FFMA R15, R11, R15, R11 ;\n /*5c90*/ MOV R11, RZ ;\n /*5ca0*/ MOV R10, R10 ;\n /*5cb0*/ FFMA R11, R10, R15, R11 ;\n /*5cc0*/ FFMA R14, R14, R11, R10 ;\n /*5cd0*/ FFMA R14, R14, R15, R11 ;\n /*5ce0*/ MOV R14, R14 ;\n /*5cf0*/ MOV R10, R10 ;\n /*5d00*/ MOV R9, R9 ;\n /*5d10*/ MOV R14, R14 ;\n /*5d20*/ BSSY B3, `(.L_x_59) ;\n /*5d30*/ @P0 BRA `(.L_x_60) ;\n /*5d40*/ BRA `(.L_x_61) ;\n.L_x_60:\n /*5d50*/ MOV R10, R10 ;\n /*5d60*/ MOV R9, R9 ;\n /*5d70*/ MOV R41, R10 ;\n /*5d80*/ MOV R27, R9 ;\n /*5d90*/ MOV R26, 0x5db0 ;\n /*5da0*/ CALL.REL.NOINC `($__internal_2_$__cuda_sm3x_div_rn_noftz_f32_slowpath) ;\n /*5db0*/ MOV R9, R25 ;\n /*5dc0*/ MOV R9, R9 ;\n /*5dd0*/ MOV R14, R9 ;\n.L_x_61:\n /*5de0*/ BSYNC B3 ;\n.L_x_59:\n /*5df0*/ MOV R14, R14 ;\n /*5e00*/ FMUL R9, R14, R14 ;\n /*5e10*/ MOV R10, 0xc0b59883 ;\n /*5e20*/ MOV R11, 0xbf52c7ea ;\n /*5e30*/ FFMA R10, R9, R11, R10 ;\n /*5e40*/ MOV R11, 0xc0d21907 ;\n /*5e50*/ FFMA R10, R10, R9, R11 ;\n /*5e60*/ FMUL R10, R9, R10 ;\n /*5e70*/ FMUL R10, R14, R10 ;\n /*5e80*/ FADD R11, R9, 11.33538818359375 ;\n /*5e90*/ MOV R15, 0x41e6bd60 ;\n /*5ea0*/ FFMA R11, R11, R9, R15 ;\n /*5eb0*/ MOV R15, 0x419d92c8 ;\n /*5ec0*/ FFMA R11, R11, R9, R15 ;\n /*5ed0*/ MOV R11, R11 ;\n /*5ee0*/ MOV R9, R14 ;\n /*5ef0*/ MOV R10, R10 ;\n /*5f00*/ MOV R11, R11 ;\n /*5f10*/ MOV R11, R11 ;\n /*5f20*/ MOV R11, R11 ;\n /*5f30*/ MOV R11, R11 ;\n /*5f40*/ IADD3 R14, R11, 0x1800000, RZ ;\n /*5f50*/ LOP3.LUT R14, R14, 0x7f800000, RZ, 0xc0, !PT ;\n /*5f60*/ MOV R15, 0x1ffffff ;\n /*5f70*/ ISETP.GT.U32.AND P0, PT, R14, R15, PT ;\n /*5f80*/ MOV R11, R11 ;\n /*5f90*/ BSSY B1, `(.L_x_62) ;\n /*5fa0*/ @P0 BRA `(.L_x_63) ;\n /*5fb0*/ MOV R11, R11 ;\n /*5fc0*/ MOV R14, R11 ;\n /*5fd0*/ MOV R11, 0x5ff0 ;\n /*5fe0*/ CALL.REL.NOINC `($__internal_0_$__cuda_sm20_rcp_rn_f32_slowpath) ;\n /*5ff0*/ MOV R11, R16 ;\n /*6000*/ MOV R11, R11 ;\n /*6010*/ MOV R11, R11 ;\n /*6020*/ MOV R11, R11 ;\n /*6030*/ BRA `(.L_x_64) ;\n.L_x_63:\n /*6040*/ MUFU.RCP R14, R11 ;\n /*6050*/ MOV R15, 0xbf800000 ;\n /*6060*/ FFMA R15, R11, R14, R15 ;\n /*6070*/ FADD.FTZ R15, -RZ, -R15 ;\n /*6080*/ FFMA R15, R14, R15, R14 ;\n /*6090*/ MOV R11, R15 ;\n.L_x_64:\n /*60a0*/ BSYNC B1 ;\n.L_x_62:\n /*60b0*/ MOV R11, R11 ;\n /*60c0*/ MOV R11, R11 ;\n /*60d0*/ MOV R11, R11 ;\n /*60e0*/ MOV R11, R11 ;\n /*60f0*/ FFMA R9, R10, R11, R9 ;\n /*6100*/ MOV R10, 0x3fc90fdb ;\n /*6110*/ FADD R10, R10, -R9 ;\n /*6120*/ FSETP.GT.AND P0, PT, R8, R5, PT ;\n /*6130*/ FSEL R10, R10, R9, P0 ;\n /*6140*/ MOV R4, R4 ;\n /*6150*/ ISETP.LT.AND P0, PT, R4, RZ, PT ;\n /*6160*/ MOV R4, 0x40490fdb ;\n /*6170*/ FADD R4, R4, -R10 ;\n /*6180*/ FSEL R4, R4, R10, P0 ;\n /*6190*/ MOV R4, R4 ;\n /*61a0*/ MOV R3, R3 ;\n /*61b0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;\n /*61c0*/ LOP3.LUT R3, R3, R4, RZ, 0xfc, !PT ;\n /*61d0*/ MOV R3, R3 ;\n /*61e0*/ FADD R5, R5, R8 ;\n /*61f0*/ FSETP.LE.AND P0, PT, R5, +INF , PT ;\n /*6200*/ FSEL R3, R3, R5, P0 ;\n /*6210*/ MOV R3, R3 ;\n /*6220*/ BRA `(.L_x_56) ;\n.L_x_56:\n /*6230*/ BSYNC B2 ;\n.L_x_53:\n /*6240*/ MOV R4, RZ ;\n /*6250*/ FADD R17, R4, -R17 ;\n /*6260*/ FADD R5, -RZ, |R17| ;\n /*6270*/ MOV R5, R5 ;\n /*6280*/ FADD R4, -RZ, -R5 ;\n /*6290*/ MOV R4, R4 ;\n /*62a0*/ MOV R8, 0x3f000000 ;\n /*62b0*/ FFMA R4, R8, R4, R8 ;\n /*62c0*/ MUFU.RSQ R9, R4 ;\n /*62d0*/ FMUL R4, R4, R9 ;\n /*62e0*/ FMUL R9, R9, 0.5 ;\n /*62f0*/ FADD R10, -RZ, -R4 ;\n /*6300*/ MOV R10, R10 ;\n /*6310*/ FFMA R9, R10, R9, R8 ;\n /*6320*/ FFMA R9, R4, R9, R4 ;\n /*6330*/ FSETP.EQ.AND P0, PT, R5, 1, PT ;\n /*6340*/ MOV R4, 0x3f800000 ;\n /*6350*/ FSEL R9, RZ, R9, P0 ;\n /*6360*/ FSETP.GT.AND P0, PT, R5, 0.56000000238418579102, PT ;\n /*6370*/ FSEL R9, R9, R5, P0 ;\n /*6380*/ MOV R9, R9 ;\n /*6390*/ MOV R5, R17 ;\n /*63a0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ;\n /*63b0*/ LOP3.LUT R5, R5, R9, RZ, 0xfc, !PT ;\n /*63c0*/ MOV R5, R5 ;\n /*63d0*/ FMUL R8, R5, R5 ;\n /*63e0*/ MOV R9, 0x3c8b1abb ;\n /*63f0*/ MOV R10, 0x3d10ecef ;\n /*6400*/ FFMA R9, R10, R8, R9 ;\n /*6410*/ MOV R10, 0x3cfc028c ;\n /*6420*/ FFMA R9, R9, R8, R10 ;\n /*6430*/ MOV R10, 0x3d372139 ;\n /*6440*/ FFMA R9, R9, R8, R10 ;\n /*6450*/ MOV R10, 0x3d9993db ;\n /*6460*/ FFMA R9, R9, R8, R10 ;\n /*6470*/ MOV R10, 0x3e2aaac6 ;\n /*6480*/ FFMA R9, R9, R8, R10 ;\n /*6490*/ FMUL R9, R9, R8 ;\n /*64a0*/ FFMA R9, R9, R5, R5 ;\n /*64b0*/ FADD R5, -RZ, -R9 ;\n /*64c0*/ MOV R5, R5 ;\n /*64d0*/ FSEL R5, R9, R5, P0 ;\n /*64e0*/ MOV R8, 0x3fd774eb ;\n /*64f0*/ MOV R10, 0x3f6ee581 ;\n /*6500*/ FFMA R5, R10, R8, R5 ;\n /*6510*/ FSETP.GT.AND P1, PT, R17, 0.56000000238418579102, PT ;\n /*6520*/ FSEL R5, R9, R5, P1 ;\n /*6530*/ FADD R8, R5, R5 ;\n /*6540*/ FSEL R5, R8, R5, P0 ;\n /*6550*/ FMUL R8, R5, 0.5 ;\n /*6560*/ FRND.TRUNC R8, R8 ;\n /*6570*/ FADD R8, R8, R8 ;\n /*6580*/ FADD R8, R5, -R8 ;\n /*6590*/ FADD R8, -RZ, |R8| ;\n /*65a0*/ MOV R8, R8 ;\n /*65b0*/ FADD R9, -RZ, |R3| ;\n /*65c0*/ MOV R9, R9 ;\n /*65d0*/ FSETP.LT.AND P0, PT, R9, 1.175494350822287508e-38, PT ;\n /*65e0*/ FMUL R10, R9, 16777216 ;\n /*65f0*/ FSEL R10, R10, R9, P0 ;\n /*6600*/ FSEL R11, RZ, -24, !P0 ;\n /*6610*/ MOV R10, R10 ;\n /*6620*/ IADD3 R14, R10, -0x3f3504f3, RZ ;\n /*6630*/ LOP3.LUT R14, R14, 0xff800000, RZ, 0xc0, !PT ;\n /*6640*/ IADD3 R10, R10, -R14, RZ ;\n /*6650*/ MOV R10, R10 ;\n /*6660*/ I2FP.F32.S32 R14, R14 ;\n /*6670*/ MOV R15, 0x34000000 ;\n /*6680*/ FFMA R11, R14, R15, R11 ;\n /*6690*/ FADD R14, R10, -1 ;\n /*66a0*/ FADD R10, R10, 1 ;\n /*66b0*/ MUFU.RCP R10, R10 ;\n /*66c0*/ FADD R15, R14, R14 ;\n /*66d0*/ FMUL R15, R15, R10 ;\n /*66e0*/ FMUL R16, R15, R15 ;\n /*66f0*/ FADD R17, R14, -R15 ;\n /*6700*/ FADD R17, R17, R17 ;\n /*6710*/ FADD R18, -RZ, -R15 ;\n /*6720*/ MOV R18, R18 ;\n /*6730*/ FFMA R17, R18, R14, R17 ;\n /*6740*/ FMUL R17, R10, R17 ;\n /*6750*/ MOV R10, 0x3b52e7db ;\n /*6760*/ MOV R14, 0x3a2c32e4 ;\n /*6770*/ FFMA R10, R14, R16, R10 ;\n /*6780*/ MOV R14, 0x3c93bb73 ;\n /*6790*/ FFMA R10, R10, R16, R14 ;\n /*67a0*/ MOV R14, 0x3df6384f ;\n /*67b0*/ FFMA R10, R10, R16, R14 ;\n /*67c0*/ FMUL R10, R10, R16 ;\n /*67d0*/ MOV R14, 0x3fb8aa3b ;\n /*67e0*/ FFMA R16, R15, R14, R11 ;\n /*67f0*/ FADD R11, R11, -R16 ;\n /*6800*/ FFMA R11, R15, R14, R11 ;\n /*6810*/ FFMA R11, R17, R14, R11 ;\n /*6820*/ MOV R14, 0x32a55e34 ;\n /*6830*/ FFMA R11, R15, R14, R11 ;\n /*6840*/ FMUL R14, R10, 3 ;\n /*6850*/ FFMA R11, R14, R17, R11 ;\n /*6860*/ FFMA R11, R10, R15, R11 ;\n /*6870*/ FADD R10, R16, R11 ;\n /*6880*/ FADD R14, -RZ, -R16 ;\n /*6890*/ MOV R14, R14 ;\n /*68a0*/ FADD R14, R10, R14 ;\n /*68b0*/ FADD R14, -RZ, -R14 ;\n /*68c0*/ MOV R14, R14 ;\n /*68d0*/ FADD R14, R11, R14 ;\n /*68e0*/ FMUL R16, R10, R5 ;\n /*68f0*/ FADD R11, -RZ, -R16 ;\n /*6900*/ MOV R11, R11 ;\n /*6910*/ FFMA R11, R10, R5, R11 ;\n /*6920*/ FFMA R11, R14, R5, R11 ;\n /*6930*/ FRND R15, R16 ;\n /*6940*/ FADD R10, R16, -R15 ;\n /*6950*/ FADD R10, R11, R10 ;\n /*6960*/ MOV R11, 0x3aaf85ed ;\n /*6970*/ MOV R14, 0x391fcb8e ;\n /*6980*/ FFMA R11, R14, R10, R11 ;\n /*6990*/ MOV R14, 0x3c1d9856 ;\n /*69a0*/ FFMA R11, R11, R10, R14 ;\n /*69b0*/ MOV R14, 0x3d6357bb ;\n /*69c0*/ FFMA R11, R11, R10, R14 ;\n /*69d0*/ MOV R14, 0x3e75fdec ;\n /*69e0*/ FFMA R11, R11, R10, R14 ;\n /*69f0*/ MOV R14, 0x3f317218 ;\n /*6a00*/ FFMA R11, R11, R10, R14 ;\n /*6a10*/ FFMA R11, R11, R10, R4 ;\n /*6a20*/ F2I.TRUNC.NTZ R10, R15 ;\n /*6a30*/ FSETP.GT.AND P0, PT, R15, RZ, PT ;\n /*6a40*/ SEL R14, RZ, 0x83000000, P0 ;\n /*6a50*/ IADD3 R15, R14, 0x7f000000, RZ ;\n /*6a60*/ MOV R15, R15 ;\n /*6a70*/ FMUL R11, R11, R15 ;\n /*6a80*/ SHF.L.U32 R10, R10, 0x17, RZ ;\n /*6a90*/ IADD3 R10, R10, -R14, RZ ;\n /*6aa0*/ MOV R10, R10 ;\n /*6ab0*/ FMUL R10, R11, R10 ;\n /*6ac0*/ FADD R11, -RZ, |R16| ;\n /*6ad0*/ MOV R11, R11 ;\n /*6ae0*/ FSETP.GT.AND P0, PT, R11, 152, PT ;\n /*6af0*/ FSETP.LT.AND P1, PT, R16, RZ, PT ;\n /*6b00*/ FSEL R11, RZ, +INF , P1 ;\n /*6b10*/ FSEL R10, R11, R10, P0 ;\n /*6b20*/ FSETP.EQ.AND P0, PT, R5, RZ, PT ;\n /*6b30*/ FSETP.EQ.AND P1, PT, R3, 1, PT ;\n /*6b40*/ PLOP3.LUT P0, PT, P1, P0, PT, 0xa8, 0x0 ;\n /*6b50*/ MOV R4, R4 ;\n /*6b60*/ MOV R5, R5 ;\n /*6b70*/ MOV R8, R8 ;\n /*6b80*/ MOV R9, R9 ;\n /*6b90*/ MOV R10, R10 ;\n /*6ba0*/ BSSY B1, `(.L_x_65) ;\n /*6bb0*/ @P0 BRA `(.L_x_66) ;\n /*6bc0*/ FSETP.GTU.AND P0, PT, R9, +INF , PT ;\n /*6bd0*/ @P0 BRA `(.L_x_67) ;\n /*6be0*/ FADD R11, -RZ, |R5| ;\n /*6bf0*/ MOV R11, R11 ;\n /*6c00*/ FSETP.GTU.AND P0, PT, R11, +INF , PT ;\n /*6c10*/ MOV R11, R11 ;\n /*6c20*/ @P0 BRA `(.L_x_67) ;\n /*6c30*/ BRA `(.L_x_68) ;\n.L_x_67:\n /*6c40*/ FADD R3, R3, R5 ;\n /*6c50*/ MOV R4, R3 ;\n /*6c60*/ BRA `(.L_x_66) ;\n.L_x_66:\n /*6c70*/ BSYNC B1 ;\n.L_x_65:\n /*6c80*/ FFMA R4, R12, R13, R4 ;\n /*6c90*/ FADD R4, R4, 1.5707963705062866211 ;\n /*6ca0*/ MOV R34, R4 ;\n.L_x_43:\n /*6cb0*/ BSYNC B0 ;\n.L_x_42:\n /*6cc0*/ F2F.F64.F32 R34, R34 ;\n /*6cd0*/ IADD3 R6, P0, R6, 0x20, RZ ;\n /*6ce0*/ IADD3.X R7, R7, RZ, RZ, P0, !PT ;\n /*6cf0*/ IADD3 R0, P0, R0, 0x20, RZ ;\n /*6d00*/ IADD3.X R2, R2, RZ, RZ, P0, !PT ;\n /*6d10*/ MOV R0, R0 ;\n /*6d20*/ MOV R2, R2 ;\n /*6d30*/ STL.64 [R0], R34 ;\n /*6d40*/ MOV R4, c[0x4][0x8] ;\n /*6d50*/ MOV R5, c[0x4][0xc] ;\n /*6d60*/ MOV R4, R4 ;\n /*6d70*/ MOV R5, R5 ;\n /*6d80*/ MOV R4, R4 ;\n /*6d90*/ MOV R5, R5 ;\n /*6da0*/ MOV R6, R6 ;\n /*6db0*/ MOV R7, R7 ;\n /*6dc0*/ MOV R0, 0x0 ;\n /*6dd0*/ MOV R0, R0 ;\n /*6de0*/ LDC.64 R2, c[0x4][R0] ;\n /*6df0*/ MOV R10, R2 ;\n /*6e00*/ MOV R11, R3 ;\n /*6e10*/ MOV R10, R10 ;\n /*6e20*/ MOV R11, R11 ;\n /*6e30*/ MOV R10, R10 ;\n /*6e40*/ MOV R11, R11 ;\n /*6e50*/ LEPC R2 ;\n /*6e60*/ MOV R20, 0x6ed0 ;\n /*6e70*/ MOV R21, 0x0 ;\n /*6e80*/ MOV R0, 0x6e50 ;\n /*6e90*/ MOV R8, 0x0 ;\n /*6ea0*/ IADD3 R20, P0, P1, -R0, R20, R2 ;\n /*6eb0*/ IADD3.X R21, ~R8, R21, R3, P0, P1 ;\n /*6ec0*/ CALL.ABS.NOINC R10 ;\n /*6ed0*/ EXIT ;\n.L_x_68:\n /*6ee0*/ FSETP.EQ.AND P0, PT, R3, RZ, PT ;\n /*6ef0*/ FSETP.EQ.AND P1, PT, R9, +INF , PT ;\n /*6f00*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;\n /*6f10*/ @P0 BRA `(.L_x_69) ;\n /*6f20*/ BRA `(.L_x_70) ;\n.L_x_69:\n /*6f30*/ FSETP.EQ.AND P0, PT, R8, 1, PT ;\n /*6f40*/ FADD R3, R3, R3 ;\n /*6f50*/ MOV R3, R3 ;\n /*6f60*/ LOP3.LUT R4, R3, 0x7f800000, RZ, 0x3c, !PT ;\n /*6f70*/ FSETP.LT.AND P1, PT, R5, RZ, PT ;\n /*6f80*/ SEL R4, R4, R3, P1 ;\n /*6f90*/ LOP3.LUT R3, R4, 0x7fffffff, RZ, 0xc0, !PT ;\n /*6fa0*/ SEL R3, R4, R3, P0 ;\n /*6fb0*/ MOV R3, R3 ;\n /*6fc0*/ MOV R4, R3 ;\n /*6fd0*/ BRA `(.L_x_66) ;\n.L_x_70:\n /*6fe0*/ FSETP.EQ.AND P0, PT, R3, -1, PT ;\n /*6ff0*/ FSETP.EQ.AND P1, PT, R11, +INF , PT ;\n /*7000*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x80, 0x0 ;\n /*7010*/ @P0 BRA `(.L_x_66) ;\n /*7020*/ FSETP.GEU.AND P0, PT, R3, RZ, PT ;\n /*7030*/ MOV R4, R10 ;\n /*7040*/ MOV R4, R4 ;\n /*7050*/ @P0 BRA `(.L_x_66) ;\n /*7060*/ FSETP.EQ.AND P0, PT, R8, 1, PT ;\n /*7070*/ FADD R3, -RZ, -R10 ;\n /*7080*/ MOV R3, R3 ;\n /*7090*/ FSEL R3, R3, R10, P0 ;\n /*70a0*/ FRND.FLOOR R4, R5 ;\n /*70b0*/ FSETP.NEU.AND P0, PT, R4, R5, PT ;\n /*70c0*/ FSEL R3, R3, +QNAN , !P0 ;\n /*70d0*/ MOV R4, R3 ;\n /*70e0*/ BRA `(.L_x_66) ;\n /*70f0*/ EXIT ;\n\n\n\n\n .weak $__internal_0_$__cuda_sm20_rcp_rn_f32_slowpath\n .type $__internal_0_$__cuda_sm20_rcp_rn_f32_slowpath,@function\n .size $__internal_0_$__cuda_sm20_rcp_rn_f32_slowpath,($__internal_1_$__cuda_sm20_sqrt_rn_f32_slowpath - $__internal_0_$__cuda_sm20_rcp_rn_f32_slowpath)\n$__internal_0_$__cuda_sm20_rcp_rn_f32_slowpath:\n /*7100*/ MOV R14, R14 ;\n /*7110*/ MOV R14, R14 ;\n /*7120*/ MOV R14, R14 ;\n /*7130*/ MOV R14, R14 ;\n /*7140*/ MOV R14, R14 ;\n /*7150*/ SHF.L.U32 R15, R14, 0x1, RZ ;\n /*7160*/ SHF.R.U32.HI R15, RZ, 0x18, R15 ;\n /*7170*/ MOV R16, RZ ;\n /*7180*/ ISETP.NE.U32.AND P0, PT, R15, R16, PT ;\n /*7190*/ MOV R16, R14 ;\n /*71a0*/ MOV R14, R14 ;\n /*71b0*/ MOV R15, R15 ;\n /*71c0*/ BSSY B3, `(.L_x_71) ;\n /*71d0*/ @P0 BRA `(.L_x_72) ;\n /*71e0*/ SHF.L.U32 R14, R14, 0x1, RZ ;\n /*71f0*/ MOV R15, RZ ;\n /*7200*/ ISETP.NE.AND P0, PT, R14, R15, PT ;\n /*7210*/ @P0 BRA `(.L_x_73) ;\n /*7220*/ MUFU.RCP R16, R16 ;\n /*7230*/ MOV R16, R16 ;\n /*7240*/ BRA `(.L_x_74) ;\n.L_x_73:\n /*7250*/ MOV R14, 0x5f800000 ;\n /*7260*/ MOV R15, RZ ;\n /*7270*/ FFMA R14, R16, R14, R15 ;\n /*7280*/ MUFU.RCP R15, R14 ;\n /*7290*/ MOV R16, 0xbf800000 ;\n /*72a0*/ FFMA R16, R14, R15, R16 ;\n /*72b0*/ FADD.FTZ R16, -RZ, -R16 ;\n /*72c0*/ FFMA R16, R15, R16, R15 ;\n /*72d0*/ MOV R15, 0x5f800000 ;\n /*72e0*/ MOV R18, RZ ;\n /*72f0*/ FFMA R15, R16, R15, R18 ;\n /*7300*/ MOV R16, R14 ;\n /*7310*/ MOV R16, R15 ;\n /*7320*/ BRA `(.L_x_74) ;\n.L_x_72:\n /*7330*/ IADD3 R18, R15, -0xfd, RZ ;\n /*7340*/ MOV R19, 0x1 ;\n /*7350*/ ISETP.GT.U32.AND P0, PT, R18, R19, PT ;\n /*7360*/ MOV R18, R18 ;\n /*7370*/ @P0 BRA `(.L_x_75) ;\n /*7380*/ LOP3.LUT R21, R14, 0x7fffff, RZ, 0xc0, !PT ;\n /*7390*/ LOP3.LUT R16, R21, 0x3f800000, RZ, 0xfc, !PT ;\n /*73a0*/ MOV R16, R16 ;\n /*73b0*/ MUFU.RCP R19, R16 ;\n /*73c0*/ MOV R20, 0xbf800000 ;\n /*73d0*/ FFMA R20, R16, R19, R20 ;\n /*73e0*/ FADD.FTZ R20, -RZ, -R20 ;\n /*73f0*/ FFMA.RM R22, R19, R20, R19 ;\n /*7400*/ MOV R16, R22 ;\n /*7410*/ LOP3.LUT R16, R16, 0x7fffff, RZ, 0xc0, !PT ;\n /*7420*/ LOP3.LUT R16, R16, 0x800000, RZ, 0xfc, !PT ;\n /*7430*/ FFMA.RP R19, R19, R20, R19 ;\n /*7440*/ FSETP.NEU.FTZ.AND P0, PT, R22, R19, PT ;\n /*7450*/ SEL R19, RZ, 0xffffffff, !P0 ;\n /*7460*/ IADD3 R19, RZ, -R19, RZ ;\n /*7470*/ MOV R19, R19 ;\n /*7480*/ MOV R19, R19 ;\n /*7490*/ LOP3.LUT R20, R18, R16, RZ, 0xc0, !PT ;\n /*74a0*/ LOP3.LUT R19, R19, R20, RZ, 0xfc, !PT ;\n /*74b0*/ MOV R20, 0x3 ;\n /*74c0*/ SHF.L.U32 R20, R20, R18, RZ ;\n /*74d0*/ LOP3.LUT R20, R20, R16, RZ, 0xc0, !PT ;\n /*74e0*/ SHF.R.U32.HI R20, RZ, R18, R20 ;\n /*74f0*/ LOP3.LUT R18, R20, 0x1, RZ, 0xc0, !PT ;\n /*7500*/ LOP3.LUT R20, R20, 0x2, RZ, 0xc0, !PT ;\n /*7510*/ IADD3 R15, R15, -0xfc, RZ ;\n /*7520*/ SHF.R.U32.HI R15, RZ, R15, R16 ;\n /*7530*/ IADD3 R16, R15, 0x1, RZ ;\n /*7540*/ MOV R22, RZ ;\n /*7550*/ ISETP.NE.U32.AND P0, PT, R18, R22, PT ;\n /*7560*/ SEL R18, RZ, 0xffffffff, !P0 ;\n /*7570*/ IADD3 R18, RZ, -R18, RZ ;\n /*7580*/ MOV R18, R18 ;\n /*7590*/ MOV R18, R18 ;\n /*75a0*/ MOV R22, RZ ;\n /*75b0*/ ISETP.NE.U32.AND P0, PT, R19, R22, PT ;\n /*75c0*/ SEL R19, RZ, 0xffffffff, !P0 ;\n /*75d0*/ IADD3 R19, RZ, -R19, RZ ;\n /*75e0*/ MOV R19, R19 ;\n /*75f0*/ MOV R19, R19 ;\n /*7600*/ MOV R22, RZ ;\n /*7610*/ ISETP.NE.U32.AND P0, PT, R20, R22, PT ;\n /*7620*/ SEL R20, RZ, 0xffffffff, !P0 ;\n /*7630*/ IADD3 R20, RZ, -R20, RZ ;\n /*7640*/ MOV R20, R20 ;\n /*7650*/ MOV R20, R20 ;\n /*7660*/ LOP3.LUT R19, R19, R20, RZ, 0xfc, !PT ;\n /*7670*/ LOP3.LUT R18, R18, R19, RZ, 0xc0, !PT ;\n /*7680*/ IADD3 R18, RZ, -R18, RZ ;\n /*7690*/ MOV R18, R18 ;\n /*76a0*/ MOV R18, R18 ;\n /*76b0*/ ISETP.GE.AND P0, PT, R18, RZ, PT ;\n /*76c0*/ SEL R16, R15, R16, P0 ;\n /*76d0*/ SHF.L.U32 R15, R16, 0x1, RZ ;\n /*76e0*/ MOV R18, RZ ;\n /*76f0*/ ISETP.EQ.U32.AND P0, PT, R21, R18, PT ;\n /*7700*/ SEL R15, R15, R16, P0 ;\n /*7710*/ LOP3.LUT R14, R14, 0x80000000, RZ, 0xc0, !PT ;\n /*7720*/ LOP3.LUT R14, R15, R14, RZ, 0xfc, !PT ;\n /*7730*/ MOV R14, R14 ;\n /*7740*/ MOV R16, R14 ;\n /*7750*/ BRA `(.L_x_74) ;\n.L_x_75:\n /*7760*/ MUFU.RCP R16, R16 ;\n /*7770*/ MOV R16, R16 ;\n /*7780*/ BRA `(.L_x_74) ;\n.L_x_74:\n /*7790*/ BSYNC B3 ;\n.L_x_71:\n /*77a0*/ MOV R16, R16 ;\n /*77b0*/ MOV R16, R16 ;\n /*77c0*/ MOV R16, R16 ;\n /*77d0*/ MOV R14, R11 ;\n /*77e0*/ MOV R15, 0x0 ;\n /*77f0*/ RET.REL.NODEC R14 `(_Z7computefiffPfS_fffffffffffffffffff) ;\n\n\n\n\n .weak $__internal_1_$__cuda_sm20_sqrt_rn_f32_slowpath\n .type $__internal_1_$__cuda_sm20_sqrt_rn_f32_slowpath,@function\n .size $__internal_1_$__cuda_sm20_sqrt_rn_f32_slowpath,($__internal_2_$__cuda_sm3x_div_rn_noftz_f32_slowpath - $__internal_1_$__cuda_sm20_sqrt_rn_f32_slowpath)\n$__internal_1_$__cuda_sm20_sqrt_rn_f32_slowpath:\n /*7800*/ MOV R3, R3 ;\n /*7810*/ MOV R3, R3 ;\n /*7820*/ MOV R3, R3 ;\n /*7830*/ MOV R3, R3 ;\n /*7840*/ MOV R3, R3 ;\n /*7850*/ LOP3.LUT R8, R3, 0x7fffffff, RZ, 0xc0, !PT ;\n /*7860*/ MOV R9, RZ ;\n /*7870*/ ISETP.NE.AND P0, PT, R8, R9, PT ;\n /*7880*/ MOV R3, R3 ;\n /*7890*/ BSSY B2, `(.L_x_76) ;\n /*78a0*/ @P0 BRA `(.L_x_77) ;\n /*78b0*/ MOV R3, R3 ;\n /*78c0*/ MOV R3, R3 ;\n /*78d0*/ BRA `(.L_x_78) ;\n.L_x_77:\n /*78e0*/ MOV R8, RZ ;\n /*78f0*/ FSETP.LT.FTZ.AND P0, PT, R3, R8, PT ;\n /*7900*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ;\n /*7910*/ @P0 BRA `(.L_x_79) ;\n /*7920*/ MOV R3, 0x7fffffff ;\n /*7930*/ MOV R3, R3 ;\n /*7940*/ BRA `(.L_x_78) ;\n.L_x_79:\n /*7950*/ FADD.FTZ R8, -RZ, |R3| ;\n /*7960*/ MOV R9, 0x7f800000 ;\n /*7970*/ FSETP.LE.FTZ.AND P0, PT, R8, R9, PT ;\n /*7980*/ MOV R8, R8 ;\n /*7990*/ @P0 BRA `(.L_x_80) ;\n /*79a0*/ MOV R8, 0x3f800000 ;\n /*79b0*/ FADD.FTZ R3, R3, R8 ;\n /*79c0*/ MOV R3, R3 ;\n /*79d0*/ BRA `(.L_x_78) ;\n.L_x_80:\n /*79e0*/ MOV R9, 0x7f800000 ;\n /*79f0*/ FSETP.EQ.FTZ.AND P0, PT, R8, R9, PT ;\n /*7a00*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ;\n /*7a10*/ @P0 BRA `(.L_x_81) ;\n /*7a20*/ MOV R3, R3 ;\n /*7a30*/ MOV R3, R3 ;\n /*7a40*/ BRA `(.L_x_78) ;\n.L_x_81:\n /*7a50*/ MOV R8, 0x5f800000 ;\n /*7a60*/ MOV R9, RZ ;\n /*7a70*/ FFMA R3, R3, R8, R9 ;\n /*7a80*/ MUFU.RSQ R8, R3 ;\n /*7a90*/ FMUL.FTZ R9, R8, R3 ;\n /*7aa0*/ FADD.FTZ R18, -RZ, -R9 ;\n /*7ab0*/ FFMA R18, R18, R9, R3 ;\n /*7ac0*/ MOV R19, 0x3f000000 ;\n /*7ad0*/ FMUL.FTZ R19, R8, R19 ;\n /*7ae0*/ FFMA R18, R18, R19, R9 ;\n /*7af0*/ MOV R8, 0x2f800000 ;\n /*7b00*/ FMUL.FTZ R8, R18, R8 ;\n /*7b10*/ MOV R3, R3 ;\n /*7b20*/ MOV R3, R8 ;\n /*7b30*/ BRA `(.L_x_78) ;\n.L_x_78:\n /*7b40*/ BSYNC B2 ;\n.L_x_76:\n /*7b50*/ MOV R3, R3 ;\n /*7b60*/ MOV R3, R3 ;\n /*7b70*/ MOV R3, R3 ;\n /*7b80*/ MOV R8, R20 ;\n /*7b90*/ MOV R9, 0x0 ;\n /*7ba0*/ RET.REL.NODEC R8 `(_Z7computefiffPfS_fffffffffffffffffff) ;\n\n\n\n\n .weak $__internal_2_$__cuda_sm3x_div_rn_noftz_f32_slowpath\n .type $__internal_2_$__cuda_sm3x_div_rn_noftz_f32_slowpath,@function\n .size $__internal_2_$__cuda_sm3x_div_rn_noftz_f32_slowpath,(.L_x_103 - $__internal_2_$__cuda_sm3x_div_rn_noftz_f32_slowpath)\n$__internal_2_$__cuda_sm3x_div_rn_noftz_f32_slowpath:\n /*7bb0*/ MOV R41, R41 ;\n /*7bc0*/ MOV R27, R27 ;\n /*7bd0*/ MOV R25, R41 ;\n /*7be0*/ MOV R27, R27 ;\n /*7bf0*/ MOV R25, R25 ;\n /*7c00*/ SHF.R.U32.HI R39, RZ, 0x17, R25 ;\n /*7c10*/ LOP3.LUT R39, R39, 0xff, RZ, 0xc0, !PT ;\n /*7c20*/ IADD3 R43, R39, -0x1, RZ ;\n /*7c30*/ MOV R42, R27 ;\n /*7c40*/ SHF.R.U32.HI R40, RZ, 0x17, R42 ;\n /*7c50*/ LOP3.LUT R44, R40, 0xff, RZ, 0xc0, !PT ;\n /*7c60*/ IADD3 R45, R44, -0x1, RZ ;\n /*7c70*/ ISETP.GT.U32.AND P0, PT, R43, 0xfd, PT ;\n /*7c80*/ ISETP.GT.U32.AND P2, PT, R45, 0xfd, PT ;\n /*7c90*/ PLOP3.LUT P0, PT, P0, P2, PT, 0xa8, 0x0 ;\n /*7ca0*/ MOV R41, R41 ;\n /*7cb0*/ MOV R27, R27 ;\n /*7cc0*/ MOV R25, R25 ;\n /*7cd0*/ MOV R40, R39 ;\n /*7ce0*/ MOV R43, R43 ;\n /*7cf0*/ MOV R42, R42 ;\n /*7d00*/ MOV R39, R44 ;\n /*7d10*/ MOV R44, R45 ;\n /*7d20*/ BSSY B1, `(.L_x_82) ;\n /*7d30*/ @P0 BRA `(.L_x_83) ;\n /*7d40*/ MOV R41, RZ ;\n /*7d50*/ MOV R41, R41 ;\n /*7d60*/ BRA `(.L_x_84) ;\n.L_x_83:\n /*7d70*/ MOV R41, R41 ;\n /*7d80*/ FADD.FTZ R45, -RZ, |R41| ;\n /*7d90*/ MOV R46, 0x7f800000 ;\n /*7da0*/ MOV R46, R46 ;\n /*7db0*/ FSETP.GTU.FTZ.AND P0, PT, R45, R46, PT ;\n /*7dc0*/ MOV R45, R45 ;\n /*7dd0*/ MOV R46, R46 ;\n /*7de0*/ @P0 BRA `(.L_x_85) ;\n /*7df0*/ MOV R27, R27 ;\n /*7e00*/ FADD.FTZ R47, -RZ, |R27| ;\n /*7e10*/ FSETP.GTU.FTZ.AND P0, PT, R47, R46, PT ;\n /*7e20*/ MOV R47, R47 ;\n /*7e30*/ @P0 BRA `(.L_x_85) ;\n /*7e40*/ LOP3.LUT R48, R42, R25, RZ, 0xfc, !PT ;\n /*7e50*/ LOP3.LUT R48, R48, 0x7fffffff, RZ, 0xc0, !PT ;\n /*7e60*/ ISETP.EQ.AND P0, PT, R48, RZ, PT ;\n /*7e70*/ @P0 BRA `(.L_x_86) ;\n /*7e80*/ FSETP.EQ.FTZ.AND P0, PT, R45, R46, PT ;\n /*7e90*/ FSETP.EQ.FTZ.AND P2, PT, R47, R46, PT ;\n /*7ea0*/ PLOP3.LUT P3, PT, P0, P2, PT, 0x80, 0x0 ;\n /*7eb0*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x80, 0x0 ;\n /*7ec0*/ PLOP3.LUT P2, PT, P2, PT, PT, 0x80, 0x0 ;\n /*7ed0*/ @P3 BRA `(.L_x_86) ;\n /*7ee0*/ LOP3.LUT R45, R25, 0x7fffffff, RZ, 0xc0, !PT ;\n /*7ef0*/ ISETP.EQ.AND P3, PT, R45, RZ, PT ;\n /*7f00*/ PLOP3.LUT P2, PT, P2, P3, PT, 0xa8, 0x0 ;\n /*7f10*/ @P2 BRA `(.L_x_87) ;\n /*7f20*/ LOP3.LUT R45, R42, 0x7fffffff, RZ, 0xc0, !PT ;\n /*7f30*/ ISETP.EQ.AND P2, PT, R45, RZ, PT ;\n /*7f40*/ PLOP3.LUT P0, PT, P0, P2, PT, 0xa8, 0x0 ;\n /*7f50*/ @P0 BRA `(.L_x_88) ;\n /*7f60*/ ISETP.LT.AND P0, PT, R43, RZ, PT ;\n /*7f70*/ BSSY B4, `(.L_x_89) ;\n /*7f80*/ @P0 BRA `(.L_x_90) ;\n /*7f90*/ MOV R41, RZ ;\n /*7fa0*/ MOV R41, R41 ;\n /*7fb0*/ BRA `(.L_x_91) ;\n.L_x_90:\n /*7fc0*/ MOV R25, RZ ;\n /*7fd0*/ MOV R43, 0x5f800000 ;\n /*7fe0*/ MOV R41, R41 ;\n /*7ff0*/ FFMA R25, R41, R43, R25 ;\n /*8000*/ MOV R25, R25 ;\n /*8010*/ MOV R41, 0xffffffc0 ;\n /*8020*/ MOV R25, R25 ;\n /*8030*/ MOV R41, R41 ;\n.L_x_91:\n /*8040*/ BSYNC B4 ;\n.L_x_89:\n /*8050*/ ISETP.LT.AND P0, PT, R44, RZ, PT ;\n /*8060*/ BSSY B4, `(.L_x_84) ;\n /*8070*/ @P0 BRA `(.L_x_92) ;\n /*8080*/ BRA `(.L_x_93) ;\n.L_x_92:\n /*8090*/ MOV R42, RZ ;\n /*80a0*/ MOV R43, 0x5f800000 ;\n /*80b0*/ MOV R27, R27 ;\n /*80c0*/ FFMA R27, R27, R43, R42 ;\n /*80d0*/ MOV R27, R27 ;\n /*80e0*/ IADD3 R41, R41, 0x40, RZ ;\n /*80f0*/ MOV R42, R27 ;\n /*8100*/ MOV R41, R41 ;\n.L_x_93:\n /*8110*/ BSYNC B4 ;\n.L_x_84:\n /*8120*/ IADD3 R40, R40, -0x7f, RZ ;\n /*8130*/ SHF.L.U32 R27, R40, 0x17, RZ ;\n /*8140*/ IADD3 R27, R25, -R27, RZ ;\n /*8150*/ MOV R43, R27 ;\n /*8160*/ SHF.L.U32 R25, R39, 0x17, RZ ;\n /*8170*/ IADD3 R25, R25, -0x3f800000, RZ ;\n /*8180*/ IADD3 R25, R42, -R25, RZ ;\n /*8190*/ MOV R25, R25 ;\n /*81a0*/ MUFU.RCP R27, R25 ;\n /*81b0*/ FADD.FTZ R42, -RZ, -R25 ;\n /*81c0*/ MOV R25, 0x3f800000 ;\n /*81d0*/ FFMA R25, R42, R27, R25 ;\n /*81e0*/ FFMA R25, R27, R25, R27 ;\n /*81f0*/ MOV R27, RZ ;\n /*8200*/ FFMA R27, R43, R25, R27 ;\n /*8210*/ FFMA R44, R42, R27, R43 ;\n /*8220*/ FFMA R27, R44, R25, R27 ;\n /*8230*/ FFMA R42, R42, R27, R43 ;\n /*8240*/ FFMA R43, R42, R25, R27 ;\n /*8250*/ MOV R43, R43 ;\n /*8260*/ SHF.R.U32.HI R44, RZ, 0x17, R43 ;\n /*8270*/ LOP3.LUT R44, R44, 0xff, RZ, 0xc0, !PT ;\n /*8280*/ MOV R45, 0x7f ;\n /*8290*/ IADD3 R45, R45, -R39, RZ ;\n /*82a0*/ IADD3 R45, R45, R40, RZ ;\n /*82b0*/ IADD3 R45, R45, R41, RZ ;\n /*82c0*/ IADD3 R44, R45, R44, RZ ;\n /*82d0*/ IADD3 R39, R44, -0x1, RZ ;\n /*82e0*/ ISETP.LT.U32.AND P0, PT, R39, 0xfe, PT ;\n /*82f0*/ MOV R39, R25 ;\n /*8300*/ MOV R40, R27 ;\n /*8310*/ MOV R42, R42 ;\n /*8320*/ MOV R25, R43 ;\n /*8330*/ MOV R45, R45 ;\n /*8340*/ MOV R27, R44 ;\n /*8350*/ BSSY B4, `(.L_x_94) ;\n /*8360*/ @P0 BRA `(.L_x_95) ;\n /*8370*/ ISETP.GT.AND P0, PT, R27, 0xfe, PT ;\n /*8380*/ @P0 BRA `(.L_x_96) ;\n /*8390*/ ISETP.LT.AND P0, PT, R27, 0x1, PT ;\n /*83a0*/ @P0 BRA `(.L_x_97) ;\n /*83b0*/ BRA `(.L_x_98) ;\n.L_x_97:\n /*83c0*/ ISETP.LT.AND P0, PT, R27, -0x18, PT ;\n /*83d0*/ LOP3.LUT R25, R25, 0x80000000, RZ, 0xc0, !PT ;\n /*83e0*/ MOV R25, R25 ;\n /*83f0*/ @P0 BRA `(.L_x_98) ;\n /*8400*/ FFMA.RP R41, R42, R39, R40 ;\n /*8410*/ FFMA.RM R43, R42, R39, R40 ;\n /*8420*/ FSETP.NEU.FTZ.AND P0, PT, R41, R43, PT ;\n /*8430*/ FFMA.RZ R39, R42, R39, R40 ;\n /*8440*/ MOV R39, R39 ;\n /*8450*/ LOP3.LUT R39, R39, 0x7fffff, RZ, 0xc0, !PT ;\n /*8460*/ LOP3.LUT R39, R39, 0x800000, RZ, 0xfc, !PT ;\n /*8470*/ IADD3 R40, R27, 0x20, RZ ;\n /*8480*/ SHF.L.U32 R40, R39, R40, RZ ;\n /*8490*/ ISETP.NE.AND P2, PT, R40, RZ, PT ;\n /*84a0*/ ISETP.EQ.AND P3, PT, R27, RZ, PT ;\n /*84b0*/ IADD3 R40, RZ, -R27, RZ ;\n /*84c0*/ MOV R40, R40 ;\n /*84d0*/ MOV R40, R40 ;\n /*84e0*/ SEL R40, RZ, R40, P3 ;\n /*84f0*/ SHF.R.U32.HI R40, RZ, R40, R39 ;\n /*8500*/ ISETP.NE.AND P3, PT, R27, RZ, PT ;\n /*8510*/ PLOP3.LUT P2, PT, P2, P3, PT, 0x80, 0x0 ;\n /*8520*/ PLOP3.LUT P0, PT, P0, P2, PT, 0xa8, 0x0 ;\n /*8530*/ SEL R27, RZ, 0x1, !P0 ;\n /*8540*/ SHF.R.U32.HI R39, RZ, 0x1, R40 ;\n /*8550*/ LOP3.LUT R41, R39, 0x1, RZ, 0xc0, !PT ;\n /*8560*/ LOP3.LUT R27, R27, R41, RZ, 0xfc, !PT ;\n /*8570*/ LOP3.LUT R27, R27, R40, RZ, 0xc0, !PT ;\n /*8580*/ IADD3 R27, R27, R39, RZ ;\n /*8590*/ LOP3.LUT R25, R27, R25, RZ, 0xfc, !PT ;\n /*85a0*/ MOV R25, R25 ;\n /*85b0*/ BRA `(.L_x_98) ;\n.L_x_96:\n /*85c0*/ LOP3.LUT R25, R25, 0x80000000, RZ, 0xc0, !PT ;\n /*85d0*/ LOP3.LUT R25, R25, 0x7f800000, RZ, 0xfc, !PT ;\n /*85e0*/ MOV R25, R25 ;\n /*85f0*/ BRA `(.L_x_98) ;\n.L_x_95:\n /*8600*/ SHF.L.U32 R45, R45, 0x17, RZ ;\n /*8610*/ IADD3 R25, R45, R25, RZ ;\n /*8620*/ MOV R25, R25 ;\n /*8630*/ BRA `(.L_x_98) ;\n.L_x_98:\n /*8640*/ BSYNC B4 ;\n.L_x_94:\n /*8650*/ MOV R25, R25 ;\n /*8660*/ MOV R25, R25 ;\n /*8670*/ MOV R25, R25 ;\n /*8680*/ BRA `(.L_x_99) ;\n.L_x_88:\n /*8690*/ LOP3.LUT R25, R42, R25, RZ, 0x3c, !PT ;\n /*86a0*/ LOP3.LUT R25, R25, 0x80000000, RZ, 0xc0, !PT ;\n /*86b0*/ LOP3.LUT R25, R25, 0x7f800000, RZ, 0xfc, !PT ;\n /*86c0*/ MOV R25, R25 ;\n /*86d0*/ MOV R25, R25 ;\n /*86e0*/ MOV R25, R25 ;\n /*86f0*/ BRA `(.L_x_99) ;\n.L_x_87:\n /*8700*/ LOP3.LUT R25, R42, R25, RZ, 0x3c, !PT ;\n /*8710*/ LOP3.LUT R25, R25, 0x80000000, RZ, 0xc0, !PT ;\n /*8720*/ MOV R25, R25 ;\n /*8730*/ MOV R25, R25 ;\n /*8740*/ MOV R25, R25 ;\n /*8750*/ BRA `(.L_x_99) ;\n.L_x_86:\n /*8760*/ MOV R25, 0xffc00000 ;\n /*8770*/ MOV R25, R25 ;\n /*8780*/ MUFU.RSQ R25, R25 ;\n /*8790*/ MOV R25, R25 ;\n /*87a0*/ MOV R25, R25 ;\n /*87b0*/ BRA `(.L_x_99) ;\n.L_x_85:\n /*87c0*/ MOV R41, R41 ;\n /*87d0*/ MOV R27, R27 ;\n /*87e0*/ FADD.FTZ R27, R41, R27 ;\n /*87f0*/ MOV R27, R27 ;\n /*8800*/ MOV R25, R27 ;\n /*8810*/ BRA `(.L_x_99) ;\n.L_x_99:\n /*8820*/ BSYNC B1 ;\n.L_x_82:\n /*8830*/ MOV R25, R25 ;\n /*8840*/ MOV R26, R26 ;\n /*8850*/ MOV R27, 0x0 ;\n /*8860*/ RET.REL.NODEC R26 `(_Z7computefiffPfS_fffffffffffffffffff) ;\n.L_x_100:\n /*8870*/ BRA `(.L_x_100);\n /*8880*/ NOP;\n /*8890*/ NOP;\n /*88a0*/ NOP;\n /*88b0*/ NOP;\n /*88c0*/ NOP;\n /*88d0*/ NOP;\n /*88e0*/ NOP;\n /*88f0*/ NOP;\n.L_x_103:\n\n\n//--------------------- SYMBOLS --------------------------\n\n .type vprintf,@function\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.protected\t_Z7computefiffPfS_fffffffffffffffffff ; -- Begin function _Z7computefiffPfS_fffffffffffffffffff\n\t.globl\t_Z7computefiffPfS_fffffffffffffffffff\n\t.p2align\t8\n\t.type\t_Z7computefiffPfS_fffffffffffffffffff,@function\n_Z7computefiffPfS_fffffffffffffffffff: ; @_Z7computefiffPfS_fffffffffffffffffff\n; %bb.0:\n\ts_clause 0x1\n\ts_load_b128 s[20:23], s[0:1], 0x4\n\ts_load_b512 s[4:19], s[0:1], 0x20\n\ts_waitcnt lgkmcnt(0)\n\tv_div_scale_f32 v0, null, s22, s22, 0\n\ts_cmp_lt_i32 s20, 1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_rcp_f32_e32 v1, v0\n\ts_waitcnt_depctr 0xfff\n\tv_fma_f32 v2, -v0, v1, 1.0\n\tv_fmac_f32_e32 v1, v2, v1\n\tv_div_scale_f32 v2, vcc_lo, 0, s22, 0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mul_f32_e32 v3, v2, v1\n\tv_fma_f32 v4, -v0, v3, v2\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmac_f32_e32 v3, v4, v1\n\tv_fma_f32 v0, -v0, v3, v2\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_div_fmas_f32 v0, v0, v1, v3\n\tv_div_fixup_f32 v0, v0, s22, 0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_add_f32_e64 v0, -s21, v0\n\tv_add_f32_e32 v0, 10, v0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_mul_f32_e32 v31, 0x826cee8b, v0\n\ts_cbranch_scc1 .LBB0_3\n; %bb.1:\n\ts_mov_b32 s2, 0x82215231\n\tv_div_scale_f32 v0, null, s5, s5, s4\n\tv_div_scale_f32 v1, null, s2, s2, s8\n\tv_add_f32_e64 v4, 0x6e214cdb, s6\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_rcp_f32_e32 v2, v0\n\tv_div_scale_f32 v9, s3, s8, 0x82215231, s8\n\tv_rcp_f32_e32 v3, v1\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)\n\tv_cmp_gt_f32_e64 s2, 0x800000, v4\n\tv_div_scale_f32 v5, vcc_lo, s4, s5, s4\n\ts_load_b128 s[24:27], s[0:1], 0x10\n\tv_cndmask_b32_e64 v7, 1.0, 0x4f800000, s2\n\ts_waitcnt_depctr 0xfff\n\tv_fma_f32 v6, -v0, v2, 1.0\n\tv_fma_f32 v8, -v1, v3, 1.0\n\tv_mul_f32_e32 v4, v4, v7\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_dual_fmac_f32 v2, v6, v2 :: v_dual_fmac_f32 v3, v8, v3\n\tv_mul_f32_e32 v7, v9, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fma_f32 v10, -v1, v7, v9\n\tv_dual_mul_f32 v6, v5, v2 :: v_dual_fmac_f32 v7, v10, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_fma_f32 v8, -v0, v6, v5\n\tv_fma_f32 v1, -v1, v7, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmac_f32_e32 v6, v8, v2\n\tv_fma_f32 v0, -v0, v6, v5\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)\n\tv_div_fmas_f32 v0, v0, v2, v6\n\ts_mov_b32 vcc_lo, s3\n\tv_div_fmas_f32 v1, v1, v3, v7\n\tv_cndmask_b32_e64 v3, 0, 0x41b17218, s2\n\tv_div_fixup_f32 v1, v1, 0x82215231, s8\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)\n\tv_add_f32_e32 v1, 0xce76aaf9, v1\n\tv_log_f32_e32 v4, v4\n\ts_waitcnt_depctr 0xfff\n\tv_mul_f32_e32 v8, 0x3f317217, v4\n\tv_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v4|\n\tv_fma_f32 v5, 0x3f317217, v4, -v8\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmamk_f32 v2, v4, 0x3377d1cf, v5\n\tv_dual_fmamk_f32 v5, s9, 0x80000000, v1 :: v_dual_add_f32 v2, v8, v2\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_cndmask_b32_e32 v2, v4, v2, vcc_lo\n\tv_div_fixup_f32 v4, v0, s5, s4\n\tv_dual_mov_b32 v0, 0 :: v_dual_sub_f32 v1, v2, v3\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_dual_add_f32 v2, 0xc334828f, v4 :: v_dual_sub_f32 v3, s7, v5\n\tv_mov_b32_e32 v4, 0x7b4476d0\n\t.p2align\t6\n.LBB0_2: ; =>This Inner Loop Header: Depth=1\n\ts_waitcnt lgkmcnt(0)\n\ts_clause 0x1\n\tglobal_store_b32 v0, v2, s[24:25]\n\tglobal_store_b32 v0, v4, s[26:27]\n\tglobal_load_b32 v5, v0, s[24:25]\n\ts_add_i32 s20, s20, -1\n\ts_add_u32 s24, s24, 4\n\ts_addc_u32 s25, s25, 0\n\ts_add_u32 s26, s26, 4\n\ts_addc_u32 s27, s27, 0\n\ts_cmp_eq_u32 s20, 0\n\ts_waitcnt vmcnt(0)\n\tv_add_f32_e32 v5, 0x7b4476d0, v5\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_add_f32_e32 v5, v1, v5\n\tv_add_f32_e32 v5, v31, v5\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_f32_e32 v31, v3, v5\n\ts_cbranch_scc0 .LBB0_2\n.LBB0_3:\n\tv_mul_f32_e64 v0, s10, 0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmp_gt_f32_e32 vcc_lo, v31, v0\n\ts_cbranch_vccz .LBB0_10\n; %bb.4:\n\tv_add_f32_e64 v0, s14, 0\n\ts_mov_b32 s3, -1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mul_f32_e32 v0, 0x419f76c9, v0\n\tv_div_scale_f32 v1, null, v0, v0, s13\n\tv_div_scale_f32 v4, vcc_lo, s13, v0, s13\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_rcp_f32_e32 v2, v1\n\ts_waitcnt_depctr 0xfff\n\tv_fma_f32 v3, -v1, v2, 1.0\n\tv_fmac_f32_e32 v2, v3, v2\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mul_f32_e32 v3, v4, v2\n\tv_fma_f32 v5, -v1, v3, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmac_f32_e32 v3, v5, v2\n\tv_fma_f32 v1, -v1, v3, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_div_fmas_f32 v1, v1, v2, v3\n\tv_div_fixup_f32 v0, v1, v0, s13\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_add_f32_e32 v0, 0x40630bb, v0\n\tv_mul_f32_e32 v1, 0x4f800000, v0\n\tv_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cndmask_b32_e32 v0, v0, v1, vcc_lo\n\tv_sqrt_f32_e32 v1, v0\n\ts_waitcnt_depctr 0xfff\n\tv_add_nc_u32_e32 v2, -1, v1\n\tv_add_nc_u32_e32 v3, 1, v1\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_fma_f32 v4, -v2, v1, v0\n\tv_fma_f32 v5, -v3, v1, v0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cmp_ge_f32_e64 s2, 0, v4\n\tv_cndmask_b32_e64 v1, v1, v2, s2\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cmp_lt_f32_e64 s2, 0, v5\n\tv_cndmask_b32_e64 v1, v1, v3, s2\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mul_f32_e32 v2, 0x37800000, v1\n\tv_cndmask_b32_e32 v1, v1, v2, vcc_lo\n\tv_cmp_class_f32_e64 vcc_lo, v0, 0x260\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cndmask_b32_e32 v0, v1, v0, vcc_lo\n\tv_add_f32_e32 v0, s12, v0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_cmp_ngt_f32_e64 s2, 0x48000000, |v0|\n\tv_readfirstlane_b32 s4, v0\n\ts_and_b32 vcc_lo, exec_lo, s2\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b32 s2, s4, 0x7fffffff\n\ts_cbranch_vccz .LBB0_6\n; %bb.5:\n\ts_and_b32 s3, s2, 0x7fffff\n\ts_lshr_b32 s4, s2, 23\n\ts_bitset1_b32 s3, 23\n\ts_addk_i32 s4, 0xff88\n\ts_mul_hi_u32 s5, s3, 0xfe5163ab\n\ts_mul_i32 s6, s3, 0x3c439041\n\ts_mul_hi_u32 s7, s3, 0x3c439041\n\ts_add_u32 s5, s5, s6\n\ts_addc_u32 s6, 0, s7\n\ts_mul_i32 s7, s3, 0xdb629599\n\ts_mul_hi_u32 s8, s3, 0xdb629599\n\ts_add_u32 s6, s6, s7\n\ts_addc_u32 s7, 0, s8\n\ts_mul_i32 s8, s3, 0xf534ddc0\n\ts_mul_hi_u32 s9, s3, 0xf534ddc0\n\ts_add_u32 s7, s7, s8\n\ts_addc_u32 s8, 0, s9\n\ts_mul_i32 s9, s3, 0xfc2757d1\n\ts_mul_hi_u32 s10, s3, 0xfc2757d1\n\ts_add_u32 s8, s8, s9\n\ts_addc_u32 s9, 0, s10\n\ts_mul_i32 s10, s3, 0x4e441529\n\ts_mul_hi_u32 s12, s3, 0x4e441529\n\ts_add_u32 s9, s9, s10\n\ts_addc_u32 s10, 0, s12\n\ts_cmp_gt_u32 s4, 63\n\ts_mul_i32 s12, s3, 0xfe5163ab\n\ts_mul_hi_u32 s13, s3, 0xa2f9836e\n\ts_mul_i32 s3, s3, 0xa2f9836e\n\ts_cselect_b32 s14, s6, s8\n\ts_cselect_b32 s5, s5, s7\n\ts_cselect_b32 s6, s12, s6\n\ts_add_u32 s3, s10, s3\n\ts_addc_u32 s10, 0, s13\n\ts_cmp_gt_u32 s4, 63\n\ts_cselect_b32 s12, 0xffffffc0, 0\n\ts_cselect_b32 s7, s7, s9\n\ts_cselect_b32 s3, s8, s3\n\ts_cselect_b32 s8, s9, s10\n\ts_add_i32 s12, s12, s4\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_cmp_gt_u32 s12, 31\n\ts_cselect_b32 s4, 0xffffffe0, 0\n\ts_cselect_b32 s9, s7, s3\n\ts_cselect_b32 s3, s3, s8\n\ts_cselect_b32 s7, s14, s7\n\ts_cselect_b32 s8, s5, s14\n\ts_cselect_b32 s5, s6, s5\n\ts_add_i32 s4, s4, s12\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_cmp_gt_u32 s4, 31\n\ts_cselect_b32 s6, 0xffffffe0, 0\n\ts_cselect_b32 s3, s9, s3\n\ts_cselect_b32 s9, s7, s9\n\ts_cselect_b32 s7, s8, s7\n\ts_cselect_b32 s5, s5, s8\n\ts_add_i32 s6, s6, s4\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\ts_sub_i32 s4, 32, s6\n\ts_cmp_eq_u32 s6, 0\n\tv_mov_b32_e32 v1, s4\n\ts_cselect_b32 s6, -1, 0\n\tv_alignbit_b32 v2, s3, s9, v1\n\tv_alignbit_b32 v3, s9, s7, v1\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_readfirstlane_b32 s4, v2\n\tv_cndmask_b32_e64 v2, v3, s9, s6\n\ts_delay_alu instid0(VALU_DEP_2)\n\ts_cselect_b32 s3, s3, s4\n\ts_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)\n\tv_alignbit_b32 v3, s3, v2, 30\n\ts_bfe_u32 s4, s3, 0x1001d\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_sub_i32 s8, 0, s4\n\ts_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)\n\tv_xor_b32_e32 v3, s8, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_clz_i32_u32_e32 v4, v3\n\tv_min_u32_e32 v4, 32, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)\n\tv_lshlrev_b32_e32 v6, 23, v4\n\tv_alignbit_b32 v1, s7, s5, v1\n\tv_sub_nc_u32_e32 v5, 31, v4\n\tv_cndmask_b32_e64 v1, v1, s7, s6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)\n\tv_alignbit_b32 v2, v2, v1, 30\n\tv_alignbit_b32 v1, v1, s5, 30\n\ts_lshr_b32 s5, s3, 29\n\ts_lshl_b32 s5, s5, 31\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_xor_b32_e32 v2, s8, v2\n\tv_xor_b32_e32 v1, s8, v1\n\ts_or_b32 s6, s5, 0.5\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)\n\tv_sub_nc_u32_e32 v6, s6, v6\n\tv_alignbit_b32 v3, v3, v2, v5\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_alignbit_b32 v1, v2, v1, v5\n\tv_alignbit_b32 v2, v3, v1, 9\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_clz_i32_u32_e32 v5, v2\n\tv_min_u32_e32 v5, 32, v5\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_sub_nc_u32_e32 v7, 31, v5\n\tv_alignbit_b32 v1, v2, v1, v7\n\tv_lshrrev_b32_e32 v2, 9, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_lshrrev_b32_e32 v1, 9, v1\n\tv_or_b32_e32 v2, v2, v6\n\tv_add_nc_u32_e32 v4, v5, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_lshlrev_b32_e32 v3, 23, v4\n\tv_sub_nc_u32_e32 v1, v1, v3\n\ts_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_f32_e32 v3, 0x3fc90fda, v2\n\tv_add_nc_u32_e32 v1, 0x33000000, v1\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_fma_f32 v4, 0x3fc90fda, v2, -v3\n\tv_or_b32_e32 v1, s5, v1\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_fmamk_f32 v2, v2, 0x33a22168, v4\n\ts_lshr_b32 s5, s3, 30\n\ts_mov_b32 s3, 0\n\ts_add_i32 s4, s4, s5\n\tv_fmac_f32_e32 v2, 0x3fc90fda, v1\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_f32_e32 v1, v3, v2\n\ts_branch .LBB0_7\n.LBB0_6:\n ; implicit-def: $sgpr4\n ; implicit-def: $vgpr1\n.LBB0_7:\n\tv_mov_b32_e32 v2, s4\n\ts_and_not1_b32 vcc_lo, exec_lo, s3\n\ts_cbranch_vccnz .LBB0_9\n; %bb.8:\n\tv_mul_f32_e64 v1, 0x3f22f983, |v0|\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_rndne_f32_e32 v2, v1\n\tv_fma_f32 v1, 0xbfc90fda, v2, |v0|\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmamk_f32 v1, v2, 0xb3a22168, v1\n\tv_fmamk_f32 v1, v2, 0xa7c234c4, v1\n\tv_cvt_i32_f32_e32 v2, v2\n.LBB0_9:\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)\n\tv_dual_mul_f32 v3, v1, v1 :: v_dual_lshlrev_b32 v6, 30, v2\n\ts_mov_b32 s3, 0xb94c1982\n\ts_mov_b32 s4, 0x37d75334\n\tv_xor_b32_e32 v7, s2, v0\n\tv_fmaak_f32 v4, s3, v3, 0x3c0881c4\n\tv_and_b32_e32 v2, 1, v2\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_fmaak_f32 v4, v3, v4, 0xbe2aaa9d\n\tv_fmaak_f32 v5, s4, v3, 0xbab64f3b\n\tv_cmp_eq_u32_e32 vcc_lo, 0, v2\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)\n\tv_mul_f32_e32 v4, v3, v4\n\tv_fmaak_f32 v5, v3, v5, 0x3d2aabf7\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_dual_fmac_f32 v1, v1, v4 :: v_dual_and_b32 v6, 0x80000000, v6\n\tv_fmaak_f32 v5, v3, v5, 0xbf000004\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_xor_b32_e32 v4, v7, v6\n\tv_fma_f32 v3, v3, v5, 1.0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cndmask_b32_e32 v1, v3, v1, vcc_lo\n\tv_xor_b32_e32 v1, v4, v1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_div_scale_f32 v2, null, v1, v1, 0xbe3c1e79\n\tv_rcp_f32_e32 v3, v2\n\ts_waitcnt_depctr 0xfff\n\tv_fma_f32 v4, -v2, v3, 1.0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_fmac_f32_e32 v3, v4, v3\n\tv_div_scale_f32 v4, vcc_lo, 0xbe3c1e79, v1, 0xbe3c1e79\n\tv_mul_f32_e32 v5, v4, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fma_f32 v6, -v2, v5, v4\n\tv_fmac_f32_e32 v5, v6, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fma_f32 v2, -v2, v5, v4\n\tv_div_fmas_f32 v2, v2, v3, v5\n\tv_cmp_class_f32_e64 vcc_lo, v0, 0x1f8\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_div_fixup_f32 v1, v2, v1, 0xbe3c1e79\n\tv_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_sub_f32_e32 v0, s11, v0\n\tv_add_f32_e32 v0, 0x4257ce2, v0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_mul_f32_e32 v31, 0x32f4375e, v0\n.LBB0_10:\n\tv_sub_f32_e64 v0, s15, s16\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_add_f32_e32 v0, 0xff800000, v0\n\tv_cmp_neq_f32_e32 vcc_lo, v31, v0\n\ts_cbranch_vccnz .LBB0_12\n; %bb.11:\n\ts_load_b128 s[4:7], s[0:1], 0x60\n\ts_waitcnt lgkmcnt(0)\n\tv_add_f32_e64 v0, 0xff800000, s5\n\tv_add_f32_e64 v1, s19, s4\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_ceil_f32_e32 v0, v0\n\tv_cmp_gt_f32_e32 vcc_lo, 0x800000, v1\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)\n\tv_div_scale_f32 v2, null, v0, v0, 0x6cb07d44\n\tv_cndmask_b32_e64 v3, 1.0, 0x4f800000, vcc_lo\n\tv_div_scale_f32 v5, s2, 0x6cb07d44, v0, 0x6cb07d44\n\tv_rcp_f32_e32 v4, v2\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_mul_f32_e32 v1, v1, v3\n\ts_waitcnt_depctr 0xfff\n\tv_fma_f32 v3, -v2, v4, 1.0\n\tv_fmac_f32_e32 v4, v3, v4\n\tv_log_f32_e32 v1, v1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mul_f32_e32 v6, v5, v4\n\tv_fma_f32 v7, -v2, v6, v5\n\ts_waitcnt_depctr 0xfff\n\tv_dual_mul_f32 v3, 0x3e9a209a, v1 :: v_dual_fmac_f32 v6, v7, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)\n\tv_fma_f32 v3, 0x3e9a209a, v1, -v3\n\tv_cndmask_b32_e64 v7, 0, 0x411a209b, vcc_lo\n\tv_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|\n\tv_fma_f32 v2, -v2, v6, v5\n\ts_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmamk_f32 v3, v1, 0x3284fbcf, v3\n\tv_fmac_f32_e32 v3, 0x3e9a209a, v1\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cndmask_b32_e32 v1, v1, v3, vcc_lo\n\ts_mov_b32 vcc_lo, s2\n\ts_mov_b32 s2, 0x3b2d2a58\n\tv_div_fmas_f32 v2, v2, v4, v6\n\tv_mul_f32_e64 v6, -s6, -s6\n\tv_sub_f32_e32 v1, v1, v7\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_div_fixup_f32 v0, v2, v0, 0x6cb07d44\n\tv_max_f32_e64 v2, |v0|, |v1|\n\tv_min_f32_e64 v4, |v0|, |v1|\n\tv_cmp_gt_i32_e64 s3, 0, v0\n\tv_cmp_class_f32_e64 s4, v0, 0x204\n\ts_delay_alu instid0(VALU_DEP_4)\n\tv_frexp_mant_f32_e32 v3, v2\n\tv_frexp_exp_i32_f32_e32 v2, v2\n\tv_frexp_exp_i32_f32_e32 v5, v4\n\tv_frexp_mant_f32_e32 v4, v4\n\tv_cndmask_b32_e64 v8, 0, 0x40490fdb, s3\n\tv_rcp_f32_e32 v3, v3\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_sub_nc_u32_e32 v2, v5, v2\n\tv_sub_f32_e64 v5, 0, s6\n\tv_fma_f32 v7, |v5|, -0.5, 0.5\n\tv_cmp_gt_f32_e64 vcc_lo, |v5|, 0.5\n\ts_waitcnt_depctr 0xfff\n\tv_mul_f32_e32 v3, v4, v3\n\tv_cndmask_b32_e32 v6, v6, v7, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_ldexp_f32 v2, v3, v2\n\tv_mul_f32_e32 v3, v2, v2\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_fmaak_f32 v4, s2, v3, 0xbc7a590c\n\ts_mov_b32 s2, 0x3d1c21a7\n\tv_fmaak_f32 v4, v3, v4, 0x3d29fb3f\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_fmaak_f32 v4, v3, v4, 0xbd97d4d7\n\tv_cmp_class_f32_e64 s3, v1, 0x204\n\tv_fmaak_f32 v4, v3, v4, 0x3dd931b2\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmaak_f32 v4, v3, v4, 0xbe1160e6\n\tv_fmaak_f32 v4, v3, v4, 0x3e4cb8bf\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmaak_f32 v4, v3, v4, 0xbeaaaa62\n\tv_mul_f32_e32 v3, v3, v4\n\tv_fmaak_f32 v7, s2, v6, 0x3c5fc5da\n\tv_cmp_gt_f32_e64 s2, |v1|, |v0|\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)\n\tv_fmac_f32_e32 v2, v2, v3\n\tv_fmaak_f32 v7, v6, v7, 0x3d034c3c\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmaak_f32 v4, v6, v7, 0x3d3641b1\n\tv_fmaak_f32 v3, v6, v4, 0x3d999bc8\n\tv_sqrt_f32_e32 v4, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmaak_f32 v3, v6, v3, 0x3e2aaaac\n\tv_mul_f32_e32 v3, v6, v3\n\tv_sub_f32_e32 v7, 0x3fc90fdb, v2\n\tv_mov_b32_e32 v6, 0x4016cbe4\n\ts_waitcnt_depctr 0xfff\n\tv_fmac_f32_e32 v4, v4, v3\n\tv_cndmask_b32_e64 v2, v2, v7, s2\n\tv_cmp_gt_f32_e64 s2, 0, v0\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)\n\tv_dual_fmac_f32 v5, v5, v3 :: v_dual_add_f32 v4, v4, v4\n\tv_sub_f32_e32 v7, 0x40490fdb, v2\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)\n\tv_cndmask_b32_e64 v6, 0x3f490fdb, v6, s2\n\tv_sub_f32_e32 v5, 0x3fc90fdb, v5\n\ts_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)\n\tv_sub_f32_e32 v3, 0x40490fdb, v4\n\tv_cndmask_b32_e64 v2, v2, v7, s2\n\tv_cmp_eq_f32_e64 s2, 0, v1\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cndmask_b32_e64 v2, v2, v8, s2\n\ts_and_b32 s2, s3, s4\n\ts_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)\n\tv_cndmask_b32_e64 v2, v2, v6, s2\n\tv_cmp_o_f32_e64 s2, v0, v1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_cndmask_b32_e64 v0, 0x7fc00000, v2, s2\n\tv_cmp_lt_f32_e64 s2, -s6, 0\n\tv_bfi_b32 v0, 0x7fffffff, v0, v1\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cndmask_b32_e64 v2, v4, v3, s2\n\ts_mov_b32 s2, 0x3e76c4e1\n\tv_cndmask_b32_e32 v1, v5, v2, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_cmp_neq_f32_e32 vcc_lo, 1.0, v0\n\tv_cndmask_b32_e32 v1, 1.0, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_cmp_neq_f32_e32 vcc_lo, 0, v1\n\tv_cmp_neq_f32_e64 s5, v1, |v1|\n\tv_cndmask_b32_e32 v0, 1.0, v0, vcc_lo\n\tv_frexp_mant_f32_e64 v2, |v0|\n\tv_cmp_lt_f32_e64 s6, |v0|, 1.0\n\tv_cmp_eq_f32_e64 s4, 0, v0\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)\n\tv_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v2\n\ts_xor_b32 s5, s5, s6\n\tv_cndmask_b32_e64 v3, 0, 1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_ldexp_f32 v2, v2, v3\n\tv_add_f32_e32 v3, 1.0, v2\n\tv_add_f32_e32 v5, -1.0, v2\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_rcp_f32_e32 v4, v3\n\tv_add_f32_e32 v7, -1.0, v3\n\tv_sub_f32_e32 v2, v2, v7\n\ts_waitcnt_depctr 0xfff\n\tv_mul_f32_e32 v6, v5, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mul_f32_e32 v8, v3, v6\n\tv_fma_f32 v3, v6, v3, -v8\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmac_f32_e32 v3, v6, v2\n\tv_add_f32_e32 v2, v8, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_dual_sub_f32 v8, v2, v8 :: v_dual_sub_f32 v7, v5, v2\n\tv_sub_f32_e32 v3, v8, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_sub_f32_e32 v5, v5, v7\n\tv_sub_f32_e32 v2, v5, v2\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_add_f32_e32 v2, v3, v2\n\tv_add_f32_e32 v2, v7, v2\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mul_f32_e32 v2, v4, v2\n\tv_add_f32_e32 v3, v6, v2\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_sub_f32_e32 v4, v3, v6\n\tv_dual_mul_f32 v5, v3, v3 :: v_dual_sub_f32 v2, v2, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_fma_f32 v4, v3, v3, -v5\n\tv_add_f32_e32 v6, v2, v2\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmac_f32_e32 v4, v3, v6\n\tv_add_f32_e32 v6, v5, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_sub_f32_e32 v5, v6, v5\n\tv_dual_fmaak_f32 v7, s2, v6, 0x3e91f4c4 :: v_dual_sub_f32 v4, v4, v5\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_dual_fmaak_f32 v7, v6, v7, 0x3ecccdef :: v_dual_mul_f32 v10, v3, v6\n\tv_mul_f32_e32 v8, v6, v7\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_fma_f32 v11, v6, v3, -v10\n\tv_fma_f32 v5, v6, v7, -v8\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_fmac_f32_e32 v11, v6, v2\n\tv_ldexp_f32 v2, v2, 1\n\tv_fmac_f32_e32 v5, v4, v7\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_fmac_f32_e32 v11, v4, v3\n\tv_ldexp_f32 v3, v3, 1\n\tv_dual_add_f32 v7, v8, v5 :: v_dual_add_f32 v6, v10, v11\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_dual_sub_f32 v8, v7, v8 :: v_dual_add_f32 v9, 0x3f2aaaaa, v7\n\tv_dual_sub_f32 v5, v5, v8 :: v_dual_add_f32 v8, 0xbf2aaaaa, v9\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_f32_e32 v5, 0x31739010, v5\n\tv_sub_f32_e32 v7, v7, v8\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_add_f32_e32 v5, v5, v7\n\tv_add_f32_e32 v4, v9, v5\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)\n\tv_mul_f32_e32 v8, v6, v4\n\tv_sub_f32_e32 v7, v9, v4\n\tv_sub_f32_e32 v9, v6, v10\n\tv_add_f32_e32 v5, v5, v7\n\ts_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)\n\tv_fma_f32 v7, v6, v4, -v8\n\tv_sub_f32_e32 v9, v11, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_fmac_f32_e32 v7, v6, v5\n\tv_frexp_exp_i32_f32_e32 v5, v0\n\tv_fmac_f32_e32 v7, v9, v4\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo\n\tv_add_f32_e32 v5, v8, v7\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_cvt_f32_i32_e32 v4, v4\n\tv_add_f32_e32 v6, v3, v5\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_dual_sub_f32 v8, v5, v8 :: v_dual_sub_f32 v3, v6, v3\n\tv_sub_f32_e32 v7, v7, v8\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_sub_f32_e32 v3, v5, v3\n\tv_add_f32_e32 v2, v2, v7\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_add_f32_e32 v2, v2, v3\n\tv_add_f32_e32 v5, v6, v2\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_sub_f32_e32 v6, v5, v6\n\tv_dual_sub_f32 v2, v2, v6 :: v_dual_mul_f32 v9, 0x3f317218, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fma_f32 v8, 0x3f317218, v4, -v9\n\tv_fmamk_f32 v4, v4, 0xb102e308, v8\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_add_f32_e32 v3, v9, v4\n\tv_add_f32_e32 v7, v3, v5\n\tv_sub_f32_e32 v9, v3, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_sub_f32_e32 v8, v7, v3\n\tv_sub_f32_e32 v4, v4, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_sub_f32_e32 v10, v7, v8\n\tv_dual_sub_f32 v5, v5, v8 :: v_dual_add_f32 v6, v4, v2\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_sub_f32_e32 v3, v3, v10\n\tv_add_f32_e32 v3, v5, v3\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_sub_f32_e32 v5, v6, v4\n\tv_add_f32_e32 v3, v6, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_sub_f32_e32 v6, v6, v5\n\tv_sub_f32_e32 v2, v2, v5\n\tv_sub_f32_e32 v4, v4, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_add_f32_e32 v2, v2, v4\n\tv_add_f32_e32 v8, v7, v3\n\tv_sub_f32_e32 v5, v8, v7\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_sub_f32_e32 v3, v3, v5\n\tv_add_f32_e32 v2, v2, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_add_f32_e32 v3, v8, v2\n\tv_dual_sub_f32 v4, v3, v8 :: v_dual_mul_f32 v5, v1, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_sub_f32_e32 v2, v2, v4\n\tv_fma_f32 v3, v1, v3, -v5\n\tv_cmp_class_f32_e64 vcc_lo, v5, 0x204\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmac_f32_e32 v3, v1, v2\n\tv_add_f32_e32 v2, v5, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cndmask_b32_e32 v4, v2, v5, vcc_lo\n\tv_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v4\n\tv_cndmask_b32_e64 v6, 0, 0x37000000, vcc_lo\n\tv_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v4|\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_dual_sub_f32 v7, v4, v6 :: v_dual_sub_f32 v2, v2, v5\n\tv_trunc_f32_e32 v4, v1\n\tv_mul_f32_e32 v8, 0x3fb8aa3b, v7\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_sub_f32_e32 v2, v3, v2\n\tv_fma_f32 v9, 0x3fb8aa3b, v7, -v8\n\tv_rndne_f32_e32 v10, v8\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_cndmask_b32_e32 v2, 0, v2, vcc_lo\n\tv_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v7\n\tv_dual_fmamk_f32 v9, v7, 0x32a5705f, v9 :: v_dual_sub_f32 v8, v8, v10\n\tv_cvt_i32_f32_e32 v5, v10\n\ts_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)\n\tv_add_f32_e32 v2, v6, v2\n\tv_add_f32_e32 v8, v8, v9\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_exp_f32_e32 v8, v8\n\ts_waitcnt_depctr 0xfff\n\tv_ldexp_f32 v3, v8, v5\n\tv_cndmask_b32_e32 v3, 0, v3, vcc_lo\n\tv_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v7\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)\n\tv_cndmask_b32_e32 v3, 0x7f800000, v3, vcc_lo\n\tv_cmp_eq_f32_e32 vcc_lo, v4, v1\n\tv_mul_f32_e32 v5, 0.5, v1\n\tv_fma_f32 v2, v3, v2, v3\n\tv_cmp_eq_f32_e64 s3, 0x7f800000, v3\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_trunc_f32_e32 v8, v5\n\tv_cndmask_b32_e64 v2, v2, v3, s3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)\n\tv_cmp_neq_f32_e64 s2, v8, v5\n\tv_cmp_gt_f32_e64 s3, 0, v1\n\tv_cndmask_b32_e64 v3, |v1|, 0, s5\n\ts_and_b32 s2, vcc_lo, s2\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)\n\ts_xor_b32 s3, s3, s4\n\tv_cndmask_b32_e64 v4, 1.0, v0, s2\n\tv_cndmask_b32_e64 v5, 0x7f800000, 0, s3\n\tv_cmp_eq_f32_e64 s3, |v0|, 1.0\n\tv_bfi_b32 v2, 0x7fffffff, v2, v4\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_cndmask_b32_e64 v3, v3, |v0|, s3\n\tv_cndmask_b32_e32 v4, 0x7fc00000, v2, vcc_lo\n\tv_cmp_gt_f32_e32 vcc_lo, 0, v0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)\n\tv_cndmask_b32_e32 v2, v2, v4, vcc_lo\n\tv_cndmask_b32_e64 v4, 0, v0, s2\n\tv_cmp_class_f32_e64 vcc_lo, v1, 0x204\n\tv_cmp_class_f32_e64 s2, v0, 0x204\n\tv_cndmask_b32_e32 v2, v2, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)\n\tv_bfi_b32 v3, 0x7fffffff, v5, v4\n\ts_or_b32 vcc_lo, s4, s2\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_cndmask_b32_e32 v2, v2, v3, vcc_lo\n\tv_cmp_o_f32_e32 vcc_lo, v0, v1\n\tv_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmac_f32_e64 v0, s17, s18\n\tv_add_f32_e32 v31, 0x3fc90fdb, v0\n.LBB0_12:\n\ts_load_b64 s[2:3], s[0:1], 0xc0\n\tv_mbcnt_lo_u32_b32 v28, -1, 0\n\tv_mov_b32_e32 v6, 0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v28\n\t;;#ASMSTART\n\t;;#ASMEND\n\tv_readfirstlane_b32 s0, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u32_e64 s0, s0, v4\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB0_18\n; %bb.13:\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s4, exec_lo\n\ts_waitcnt lgkmcnt(0)\n\tglobal_load_b64 v[8:9], v0, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[2:3] offset:40\n\tglobal_load_b64 v[5:6], v0, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v2, v2, v9\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v3, v1, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v3, v2\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, v5, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo\n\tglobal_load_b64 v[6:7], v[1:2], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[6:7], v[8:9]\n\ts_cbranch_execz .LBB0_17\n; %bb.14:\n\ts_mov_b32 s5, 0\n\t.p2align\t6\n.LBB0_15: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[1:2], v0, s[2:3] offset:40\n\tglobal_load_b64 v[10:11], v0, s[2:3]\n\tv_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v7, v2, v9\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]\n\tv_mov_b32_e32 v1, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]\n\tv_mov_b32_e32 v6, v2\n\tglobal_load_b64 v[6:7], v[5:6], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]\n\ts_or_b32 s5, vcc_lo, s5\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s5\n\ts_cbranch_execnz .LBB0_15\n; %bb.16:\n\ts_or_b32 exec_lo, exec_lo, s5\n.LBB0_17:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s4\n.LBB0_18:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v5, 0\n\tv_readfirstlane_b32 s4, v6\n\tv_readfirstlane_b32 s5, v7\n\ts_mov_b32 s10, exec_lo\n\ts_waitcnt lgkmcnt(0)\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v5, s[2:3] offset:40\n\tglobal_load_b128 v[0:3], v5, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s6, v8\n\tv_readfirstlane_b32 s7, v9\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[6:7], s[4:5], s[6:7]\n\ts_mul_i32 s1, s7, 24\n\ts_mul_hi_u32 s8, s6, 24\n\ts_mul_i32 s9, s6, 24\n\ts_and_saveexec_b32 s11, s0\n\ts_cbranch_execz .LBB0_20\n; %bb.19:\n\tv_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, v5\n\ts_add_i32 s10, s8, s1\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v10, vcc_lo, v0, s9\n\tv_add_co_ci_u32_e32 v11, vcc_lo, s10, v1, vcc_lo\n\tv_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1\n\tglobal_store_b128 v[10:11], v[6:9], off offset:8\n.LBB0_20:\n\ts_or_b32 exec_lo, exec_lo, s11\n\ts_lshl_b64 s[6:7], s[6:7], 12\n\tv_lshlrev_b64 v[6:7], 6, v[4:5]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v2, vcc_lo, v2, s6\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo\n\ts_mov_b32 s12, 0\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_u32 v8, vcc_lo, v2, v6\n\ts_mov_b32 s13, s12\n\ts_mov_b32 s14, s12\n\ts_mov_b32 s15, s12\n\tv_add_co_ci_u32_e32 v9, vcc_lo, v3, v7, vcc_lo\n\tv_dual_mov_b32 v4, 33 :: v_dual_mov_b32 v7, v5\n\tv_mov_b32_e32 v6, v5\n\tv_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v13, s15\n\tv_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v12, s14\n\ts_clause 0x3\n\tglobal_store_b128 v[8:9], v[4:7], off\n\tglobal_store_b128 v[8:9], v[10:13], off offset:16\n\tglobal_store_b128 v[8:9], v[10:13], off offset:32\n\tglobal_store_b128 v[8:9], v[10:13], off offset:48\n\ts_and_saveexec_b32 s6, s0\n\ts_cbranch_execz .LBB0_28\n; %bb.21:\n\tv_mov_b32_e32 v10, 0\n\ts_mov_b32 s7, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[13:14], v10, s[2:3] offset:32 glc\n\tglobal_load_b64 v[2:3], v10, s[2:3] offset:40\n\tv_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v3, s5, v3\n\tv_and_b32_e32 v2, s4, v2\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v3, v3, 24\n\tv_mul_hi_u32 v4, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v3, v4, v3\n\tv_add_co_u32 v6, vcc_lo, v0, v2\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v1, v3, vcc_lo\n\tglobal_store_b64 v[6:7], v[13:14], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[13:14]\n\ts_cbranch_execz .LBB0_24\n; %bb.22:\n\ts_mov_b32 s10, 0\n.LBB0_23: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s10, vcc_lo, s10\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s10\n\ts_cbranch_execnz .LBB0_23\n.LBB0_24:\n\ts_or_b32 exec_lo, exec_lo, s7\n\tv_mov_b32_e32 v5, 0\n\ts_mov_b32 s10, exec_lo\n\ts_mov_b32 s7, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s10, 0\n\tglobal_load_b64 v[2:3], v5, s[2:3] offset:16\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB0_26\n; %bb.25:\n\ts_bcnt1_i32_b32 s10, s10\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_mov_b32_e32 v4, s10\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[4:5], off offset:8\n.LBB0_26:\n\ts_or_b32 exec_lo, exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB0_28\n; %bb.27:\n\tglobal_load_b32 v2, v[2:3], off offset:24\n\tv_mov_b32_e32 v3, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s7, v2\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_and_b32 m0, s7, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB0_28:\n\ts_or_b32 exec_lo, exec_lo, s6\n\ts_add_i32 s8, s8, s1\n\tv_add_co_u32 v0, vcc_lo, v0, s9\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s8, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB0_32\n\t.p2align\t6\n.LBB0_29: ; in Loop: Header=BB0_32 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB0_31\n; %bb.30: ; in Loop: Header=BB0_32 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB0_32\n\ts_branch .LBB0_34\n\t.p2align\t6\n.LBB0_31:\n\ts_branch .LBB0_34\n.LBB0_32: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB0_29\n; %bb.33: ; in Loop: Header=BB0_32 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB0_29\n.LBB0_34:\n\tglobal_load_b64 v[0:1], v[8:9], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB0_38\n; %bb.35:\n\tv_mov_b32_e32 v8, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[4:5], v8, s[2:3] offset:40\n\tglobal_load_b64 v[9:10], v8, s[2:3] offset:24 glc\n\tglobal_load_b64 v[6:7], v8, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v11, vcc_lo, v4, 1\n\tv_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, v11, s4\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\tv_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11\n\tv_and_b32_e32 v5, v3, v5\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v4, v2, v4\n\tv_mul_lo_u32 v5, v5, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v11, v4, 24\n\tv_mul_lo_u32 v4, v4, 24\n\tv_add_nc_u32_e32 v5, v11, v5\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v6, vcc_lo, v6, v4\n\tv_mov_b32_e32 v4, v9\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo\n\tv_mov_b32_e32 v5, v10\n\tglobal_store_b64 v[6:7], v[9:10], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB0_38\n; %bb.36:\n\ts_mov_b32 s0, 0\n.LBB0_37: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[6:7], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]\n\tv_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB0_37\n.LBB0_38:\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_getpc_b64 s[4:5]\n\ts_add_u32 s4, s4, .str@rel32@lo+4\n\ts_addc_u32 s5, s5, .str@rel32@hi+12\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_cmp_lg_u64 s[4:5], 0\n\ts_cbranch_scc0 .LBB0_116\n; %bb.39:\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v3, v1 :: v_dual_and_b32 v32, 2, v0\n\tv_dual_mov_b32 v30, 0 :: v_dual_mov_b32 v7, 1\n\tv_and_b32_e32 v2, -3, v0\n\tv_mov_b32_e32 v6, 2\n\ts_mov_b64 s[6:7], 7\n\ts_branch .LBB0_41\n.LBB0_40: ; in Loop: Header=BB0_41 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_sub_u32 s6, s6, s8\n\ts_subb_u32 s7, s7, s9\n\ts_add_u32 s4, s4, s8\n\ts_addc_u32 s5, s5, s9\n\ts_cmp_lg_u64 s[6:7], 0\n\ts_cbranch_scc0 .LBB0_117\n.LBB0_41: ; =>This Loop Header: Depth=1\n ; Child Loop BB0_44 Depth 2\n ; Child Loop BB0_51 Depth 2\n ; Child Loop BB0_58 Depth 2\n ; Child Loop BB0_65 Depth 2\n ; Child Loop BB0_72 Depth 2\n ; Child Loop BB0_79 Depth 2\n ; Child Loop BB0_86 Depth 2\n ; Child Loop BB0_93 Depth 2\n ; Child Loop BB0_101 Depth 2\n ; Child Loop BB0_110 Depth 2\n ; Child Loop BB0_115 Depth 2\n\tv_cmp_lt_u64_e64 s0, s[6:7], 56\n ; implicit-def: $vgpr10_vgpr11\n ; implicit-def: $sgpr15\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b32 s0, s0, exec_lo\n\ts_cselect_b32 s8, s6, 56\n\ts_cselect_b32 s9, s7, 0\n\ts_cmp_gt_u32 s8, 7\n\ts_mov_b32 s0, -1\n\ts_cbranch_scc1 .LBB0_46\n; %bb.42: ; in Loop: Header=BB0_41 Depth=1\n\tv_mov_b32_e32 v10, 0\n\tv_mov_b32_e32 v11, 0\n\ts_cmp_eq_u32 s8, 0\n\ts_cbranch_scc1 .LBB0_45\n; %bb.43: ; in Loop: Header=BB0_41 Depth=1\n\ts_lshl_b64 s[0:1], s[8:9], 3\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], s[4:5]\n.LBB0_44: ; Parent Loop BB0_41 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v4, v30, s[12:13]\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v29, 0xffff, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[4:5], s10, v[29:30]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_add_u32 s12, s12, 1\n\ts_addc_u32 s13, s13, 0\n\ts_cmp_lg_u32 s0, s10\n\tv_or_b32_e32 v10, v4, v10\n\tv_or_b32_e32 v11, v5, v11\n\ts_cbranch_scc1 .LBB0_44\n.LBB0_45: ; in Loop: Header=BB0_41 Depth=1\n\ts_mov_b32 s0, 0\n\ts_mov_b32 s15, 0\n.LBB0_46: ; in Loop: Header=BB0_41 Depth=1\n\ts_and_not1_b32 vcc_lo, exec_lo, s0\n\ts_mov_b64 s[0:1], s[4:5]\n\ts_cbranch_vccnz .LBB0_48\n; %bb.47: ; in Loop: Header=BB0_41 Depth=1\n\tglobal_load_b64 v[10:11], v30, s[4:5]\n\ts_add_i32 s15, s8, -8\n\ts_add_u32 s0, s4, 8\n\ts_addc_u32 s1, s5, 0\n.LBB0_48: ; in Loop: Header=BB0_41 Depth=1\n\ts_cmp_gt_u32 s15, 7\n\ts_cbranch_scc1 .LBB0_53\n; %bb.49: ; in Loop: Header=BB0_41 Depth=1\n\tv_mov_b32_e32 v12, 0\n\tv_mov_b32_e32 v13, 0\n\ts_cmp_eq_u32 s15, 0\n\ts_cbranch_scc1 .LBB0_52\n; %bb.50: ; in Loop: Header=BB0_41 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB0_51: ; Parent Loop BB0_41 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s16, s0, s12\n\ts_addc_u32 s17, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v4, v30, s[16:17]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v29, 0xffff, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[4:5], s10, v[29:30]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s15, s12\n\tv_or_b32_e32 v12, v4, v12\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v13, v5, v13\n\ts_cbranch_scc1 .LBB0_51\n.LBB0_52: ; in Loop: Header=BB0_41 Depth=1\n\ts_mov_b32 s14, 0\n\ts_cbranch_execz .LBB0_54\n\ts_branch .LBB0_55\n.LBB0_53: ; in Loop: Header=BB0_41 Depth=1\n ; implicit-def: $vgpr12_vgpr13\n ; implicit-def: $sgpr14\n.LBB0_54: ; in Loop: Header=BB0_41 Depth=1\n\tglobal_load_b64 v[12:13], v30, s[0:1]\n\ts_add_i32 s14, s15, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB0_55: ; in Loop: Header=BB0_41 Depth=1\n\ts_cmp_gt_u32 s14, 7\n\ts_cbranch_scc1 .LBB0_60\n; %bb.56: ; in Loop: Header=BB0_41 Depth=1\n\tv_mov_b32_e32 v14, 0\n\tv_mov_b32_e32 v15, 0\n\ts_cmp_eq_u32 s14, 0\n\ts_cbranch_scc1 .LBB0_59\n; %bb.57: ; in Loop: Header=BB0_41 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB0_58: ; Parent Loop BB0_41 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s16, s0, s12\n\ts_addc_u32 s17, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v4, v30, s[16:17]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v29, 0xffff, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[4:5], s10, v[29:30]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s14, s12\n\tv_or_b32_e32 v14, v4, v14\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v15, v5, v15\n\ts_cbranch_scc1 .LBB0_58\n.LBB0_59: ; in Loop: Header=BB0_41 Depth=1\n\ts_mov_b32 s15, 0\n\ts_cbranch_execz .LBB0_61\n\ts_branch .LBB0_62\n.LBB0_60: ; in Loop: Header=BB0_41 Depth=1\n ; implicit-def: $sgpr15\n.LBB0_61: ; in Loop: Header=BB0_41 Depth=1\n\tglobal_load_b64 v[14:15], v30, s[0:1]\n\ts_add_i32 s15, s14, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB0_62: ; in Loop: Header=BB0_41 Depth=1\n\ts_cmp_gt_u32 s15, 7\n\ts_cbranch_scc1 .LBB0_67\n; %bb.63: ; in Loop: Header=BB0_41 Depth=1\n\tv_mov_b32_e32 v16, 0\n\tv_mov_b32_e32 v17, 0\n\ts_cmp_eq_u32 s15, 0\n\ts_cbranch_scc1 .LBB0_66\n; %bb.64: ; in Loop: Header=BB0_41 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB0_65: ; Parent Loop BB0_41 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s16, s0, s12\n\ts_addc_u32 s17, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v4, v30, s[16:17]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v29, 0xffff, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[4:5], s10, v[29:30]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s15, s12\n\tv_or_b32_e32 v16, v4, v16\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v17, v5, v17\n\ts_cbranch_scc1 .LBB0_65\n.LBB0_66: ; in Loop: Header=BB0_41 Depth=1\n\ts_mov_b32 s14, 0\n\ts_cbranch_execz .LBB0_68\n\ts_branch .LBB0_69\n.LBB0_67: ; in Loop: Header=BB0_41 Depth=1\n ; implicit-def: $vgpr16_vgpr17\n ; implicit-def: $sgpr14\n.LBB0_68: ; in Loop: Header=BB0_41 Depth=1\n\tglobal_load_b64 v[16:17], v30, s[0:1]\n\ts_add_i32 s14, s15, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB0_69: ; in Loop: Header=BB0_41 Depth=1\n\ts_cmp_gt_u32 s14, 7\n\ts_cbranch_scc1 .LBB0_74\n; %bb.70: ; in Loop: Header=BB0_41 Depth=1\n\tv_mov_b32_e32 v18, 0\n\tv_mov_b32_e32 v19, 0\n\ts_cmp_eq_u32 s14, 0\n\ts_cbranch_scc1 .LBB0_73\n; %bb.71: ; in Loop: Header=BB0_41 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB0_72: ; Parent Loop BB0_41 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s16, s0, s12\n\ts_addc_u32 s17, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v4, v30, s[16:17]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v29, 0xffff, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[4:5], s10, v[29:30]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s14, s12\n\tv_or_b32_e32 v18, v4, v18\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v19, v5, v19\n\ts_cbranch_scc1 .LBB0_72\n.LBB0_73: ; in Loop: Header=BB0_41 Depth=1\n\ts_mov_b32 s15, 0\n\ts_cbranch_execz .LBB0_75\n\ts_branch .LBB0_76\n.LBB0_74: ; in Loop: Header=BB0_41 Depth=1\n ; implicit-def: $sgpr15\n.LBB0_75: ; in Loop: Header=BB0_41 Depth=1\n\tglobal_load_b64 v[18:19], v30, s[0:1]\n\ts_add_i32 s15, s14, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB0_76: ; in Loop: Header=BB0_41 Depth=1\n\ts_cmp_gt_u32 s15, 7\n\ts_cbranch_scc1 .LBB0_81\n; %bb.77: ; in Loop: Header=BB0_41 Depth=1\n\tv_mov_b32_e32 v20, 0\n\tv_mov_b32_e32 v21, 0\n\ts_cmp_eq_u32 s15, 0\n\ts_cbranch_scc1 .LBB0_80\n; %bb.78: ; in Loop: Header=BB0_41 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], 0\n.LBB0_79: ; Parent Loop BB0_41 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_add_u32 s16, s0, s12\n\ts_addc_u32 s17, s1, s13\n\ts_add_u32 s12, s12, 1\n\tglobal_load_u8 v4, v30, s[16:17]\n\ts_addc_u32 s13, s13, 0\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v29, 0xffff, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[4:5], s10, v[29:30]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_lg_u32 s15, s12\n\tv_or_b32_e32 v20, v4, v20\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_or_b32_e32 v21, v5, v21\n\ts_cbranch_scc1 .LBB0_79\n.LBB0_80: ; in Loop: Header=BB0_41 Depth=1\n\ts_mov_b32 s14, 0\n\ts_cbranch_execz .LBB0_82\n\ts_branch .LBB0_83\n.LBB0_81: ; in Loop: Header=BB0_41 Depth=1\n ; implicit-def: $vgpr20_vgpr21\n ; implicit-def: $sgpr14\n.LBB0_82: ; in Loop: Header=BB0_41 Depth=1\n\tglobal_load_b64 v[20:21], v30, s[0:1]\n\ts_add_i32 s14, s15, -8\n\ts_add_u32 s0, s0, 8\n\ts_addc_u32 s1, s1, 0\n.LBB0_83: ; in Loop: Header=BB0_41 Depth=1\n\ts_cmp_gt_u32 s14, 7\n\ts_cbranch_scc1 .LBB0_88\n; %bb.84: ; in Loop: Header=BB0_41 Depth=1\n\tv_mov_b32_e32 v22, 0\n\tv_mov_b32_e32 v23, 0\n\ts_cmp_eq_u32 s14, 0\n\ts_cbranch_scc1 .LBB0_87\n; %bb.85: ; in Loop: Header=BB0_41 Depth=1\n\ts_mov_b64 s[10:11], 0\n\ts_mov_b64 s[12:13], s[0:1]\n.LBB0_86: ; Parent Loop BB0_41 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_u8 v4, v30, s[12:13]\n\ts_add_i32 s14, s14, -1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e32 v29, 0xffff, v4\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_lshlrev_b64 v[4:5], s10, v[29:30]\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_add_u32 s12, s12, 1\n\ts_addc_u32 s13, s13, 0\n\ts_cmp_lg_u32 s14, 0\n\tv_or_b32_e32 v22, v4, v22\n\tv_or_b32_e32 v23, v5, v23\n\ts_cbranch_scc1 .LBB0_86\n.LBB0_87: ; in Loop: Header=BB0_41 Depth=1\n\ts_cbranch_execz .LBB0_89\n\ts_branch .LBB0_90\n.LBB0_88: ; in Loop: Header=BB0_41 Depth=1\n.LBB0_89: ; in Loop: Header=BB0_41 Depth=1\n\tglobal_load_b64 v[22:23], v30, s[0:1]\n.LBB0_90: ; in Loop: Header=BB0_41 Depth=1\n\ts_waitcnt vmcnt(0)\n\tv_dual_mov_b32 v29, v28 :: v_dual_mov_b32 v4, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_readfirstlane_b32 s0, v29\n\tv_mov_b32_e32 v5, 0\n\tv_cmp_eq_u32_e64 s0, s0, v29\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB0_96\n; %bb.91: ; in Loop: Header=BB0_41 Depth=1\n\tglobal_load_b64 v[26:27], v30, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[4:5], v30, s[2:3] offset:40\n\tglobal_load_b64 v[8:9], v30, s[2:3]\n\ts_mov_b32 s10, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v5, v5, v27\n\tv_and_b32_e32 v4, v4, v26\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v5, v5, 24\n\tv_mul_hi_u32 v24, v4, 24\n\tv_mul_lo_u32 v4, v4, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v5, v24, v5\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v4, vcc_lo, v8, v4\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo\n\tglobal_load_b64 v[24:25], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[4:5], v30, v[24:27], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[4:5], v[26:27]\n\ts_cbranch_execz .LBB0_95\n; %bb.92: ; in Loop: Header=BB0_41 Depth=1\n\ts_mov_b32 s11, 0\n\t.p2align\t6\n.LBB0_93: ; Parent Loop BB0_41 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v30, s[2:3] offset:40\n\tglobal_load_b64 v[24:25], v30, s[2:3]\n\tv_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v8, v8, v26\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[4:5], null, v8, 24, v[24:25]\n\tv_and_b32_e32 v24, v9, v27\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[8:9], null, v24, 24, v[5:6]\n\tv_mov_b32_e32 v5, v8\n\tglobal_load_b64 v[24:25], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[4:5], v30, v[24:27], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[4:5], v[26:27]\n\ts_or_b32 s11, vcc_lo, s11\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s11\n\ts_cbranch_execnz .LBB0_93\n; %bb.94: ; in Loop: Header=BB0_41 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s11\n.LBB0_95: ; in Loop: Header=BB0_41 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s10\n.LBB0_96: ; in Loop: Header=BB0_41 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_clause 0x1\n\tglobal_load_b64 v[8:9], v30, s[2:3] offset:40\n\tglobal_load_b128 v[24:27], v30, s[2:3]\n\tv_readfirstlane_b32 s10, v4\n\tv_readfirstlane_b32 s11, v5\n\ts_mov_b32 s16, exec_lo\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s12, v8\n\tv_readfirstlane_b32 s13, v9\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[12:13], s[10:11], s[12:13]\n\ts_mul_i32 s1, s13, 24\n\ts_mul_hi_u32 s14, s12, 24\n\ts_mul_i32 s15, s12, 24\n\ts_and_saveexec_b32 s17, s0\n\ts_cbranch_execz .LBB0_98\n; %bb.97: ; in Loop: Header=BB0_41 Depth=1\n\tv_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, v30\n\ts_add_i32 s16, s14, s1\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v8, vcc_lo, v24, s15\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s16, v25, vcc_lo\n\tglobal_store_b128 v[8:9], v[4:7], off offset:8\n.LBB0_98: ; in Loop: Header=BB0_41 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s17\n\tv_cmp_gt_u64_e64 vcc_lo, s[6:7], 56\n\tv_or_b32_e32 v4, 0, v3\n\tv_or_b32_e32 v5, v2, v32\n\ts_lshl_b64 s[12:13], s[12:13], 12\n\ts_lshl_b32 s16, s8, 2\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\ts_add_i32 s16, s16, 28\n\tv_dual_cndmask_b32 v9, v4, v3 :: v_dual_cndmask_b32 v4, v5, v2\n\tv_lshlrev_b64 v[2:3], 6, v[29:30]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v5, vcc_lo, v26, s12\n\tv_add_co_ci_u32_e32 v27, vcc_lo, s13, v27, vcc_lo\n\ts_and_b32 s16, s16, 0x1e0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v26, vcc_lo, v5, v2\n\tv_and_or_b32 v8, 0xffffff1f, v4, s16\n\tv_add_co_ci_u32_e32 v27, vcc_lo, v27, v3, vcc_lo\n\ts_clause 0x3\n\tglobal_store_b128 v[26:27], v[8:11], off\n\tglobal_store_b128 v[26:27], v[12:15], off offset:16\n\tglobal_store_b128 v[26:27], v[16:19], off offset:32\n\tglobal_store_b128 v[26:27], v[20:23], off offset:48\n\ts_and_saveexec_b32 s12, s0\n\ts_cbranch_execz .LBB0_106\n; %bb.99: ; in Loop: Header=BB0_41 Depth=1\n\ts_clause 0x1\n\tglobal_load_b64 v[12:13], v30, s[2:3] offset:32 glc\n\tglobal_load_b64 v[2:3], v30, s[2:3] offset:40\n\tv_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s16, v2\n\tv_readfirstlane_b32 s17, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[16:17], s[16:17], s[10:11]\n\ts_mul_i32 s13, s17, 24\n\ts_mul_hi_u32 s17, s16, 24\n\ts_mul_i32 s16, s16, 24\n\ts_add_i32 s17, s17, s13\n\tv_add_co_u32 v8, vcc_lo, v24, s16\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s17, v25, vcc_lo\n\ts_mov_b32 s13, exec_lo\n\tglobal_store_b64 v[8:9], v[12:13], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[4:5], v30, v[10:13], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[4:5], v[12:13]\n\ts_cbranch_execz .LBB0_102\n; %bb.100: ; in Loop: Header=BB0_41 Depth=1\n\ts_mov_b32 s16, 0\n.LBB0_101: ; Parent Loop BB0_41 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11\n\ts_sleep 1\n\tglobal_store_b64 v[8:9], v[4:5], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v30, v[2:5], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]\n\tv_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2\n\ts_or_b32 s16, vcc_lo, s16\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s16\n\ts_cbranch_execnz .LBB0_101\n.LBB0_102: ; in Loop: Header=BB0_41 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s13\n\tglobal_load_b64 v[2:3], v30, s[2:3] offset:16\n\ts_mov_b32 s16, exec_lo\n\ts_mov_b32 s13, exec_lo\n\tv_mbcnt_lo_u32_b32 v4, s16, 0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_eq_u32_e32 0, v4\n\ts_cbranch_execz .LBB0_104\n; %bb.103: ; in Loop: Header=BB0_41 Depth=1\n\ts_bcnt1_i32_b32 s16, s16\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_mov_b32_e32 v29, s16\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[2:3], v[29:30], off offset:8\n.LBB0_104: ; in Loop: Header=BB0_41 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s13\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[4:5], v[2:3], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\ts_cbranch_vccnz .LBB0_106\n; %bb.105: ; in Loop: Header=BB0_41 Depth=1\n\tglobal_load_b32 v29, v[2:3], off offset:24\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s13, v29\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[4:5], v[29:30], off\n\ts_and_b32 m0, s13, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB0_106: ; in Loop: Header=BB0_41 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s12\n\ts_add_i32 s14, s14, s1\n\tv_add_co_u32 v2, vcc_lo, v24, s15\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s14, v25, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, v2, 20\n\tv_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo\n\ts_branch .LBB0_110\n\t.p2align\t6\n.LBB0_107: ; in Loop: Header=BB0_110 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v4\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB0_109\n; %bb.108: ; in Loop: Header=BB0_110 Depth=2\n\ts_sleep 1\n\ts_cbranch_execnz .LBB0_110\n\ts_branch .LBB0_112\n\t.p2align\t6\n.LBB0_109: ; in Loop: Header=BB0_41 Depth=1\n\ts_branch .LBB0_112\n.LBB0_110: ; Parent Loop BB0_41 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_mov_b32_e32 v4, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB0_107\n; %bb.111: ; in Loop: Header=BB0_110 Depth=2\n\tglobal_load_b32 v4, v[2:3], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v4, 1, v4\n\ts_branch .LBB0_107\n.LBB0_112: ; in Loop: Header=BB0_41 Depth=1\n\tglobal_load_b128 v[2:5], v[26:27], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB0_40\n; %bb.113: ; in Loop: Header=BB0_41 Depth=1\n\ts_clause 0x2\n\tglobal_load_b64 v[4:5], v30, s[2:3] offset:40\n\tglobal_load_b64 v[12:13], v30, s[2:3] offset:24 glc\n\tglobal_load_b64 v[10:11], v30, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v14, vcc_lo, v4, 1\n\tv_add_co_ci_u32_e32 v15, vcc_lo, 0, v5, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v8, vcc_lo, v14, s10\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s11, v15, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]\n\tv_dual_cndmask_b32 v9, v9, v15 :: v_dual_cndmask_b32 v8, v8, v14\n\tv_and_b32_e32 v5, v9, v5\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v4, v8, v4\n\tv_mul_hi_u32 v14, v4, 24\n\tv_mul_lo_u32 v4, v4, 24\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_add_co_u32 v4, vcc_lo, v10, v4\n\tv_mov_b32_e32 v10, v12\n\tv_mul_lo_u32 v5, v5, 24\n\tv_add_nc_u32_e32 v5, v14, v5\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v11, v5, vcc_lo\n\tv_mov_b32_e32 v11, v13\n\tglobal_store_b64 v[4:5], v[12:13], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[10:11], v30, v[8:11], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[10:11], v[12:13]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB0_40\n; %bb.114: ; in Loop: Header=BB0_41 Depth=1\n\ts_mov_b32 s0, 0\n.LBB0_115: ; Parent Loop BB0_41 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[10:11], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[12:13], v30, v[8:11], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[12:13], v[10:11]\n\tv_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB0_115\n\ts_branch .LBB0_40\n.LBB0_116:\n ; implicit-def: $vgpr2_vgpr3\n\ts_cbranch_execnz .LBB0_118\n\ts_branch .LBB0_145\n.LBB0_117:\n\ts_branch .LBB0_145\n.LBB0_118:\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v28\n\tv_mov_b32_e32 v8, 0\n\tv_mov_b32_e32 v9, 0\n\t;;#ASMSTART\n\t;;#ASMEND\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s0, v2\n\tv_cmp_eq_u32_e64 s0, s0, v2\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB0_124\n; %bb.119:\n\tv_mov_b32_e32 v3, 0\n\ts_mov_b32 s4, exec_lo\n\tglobal_load_b64 v[6:7], v3, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[4:5], v3, s[2:3] offset:40\n\tglobal_load_b64 v[8:9], v3, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v4, v4, v6\n\tv_and_b32_e32 v5, v5, v7\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v10, v4, 24\n\tv_mul_lo_u32 v5, v5, 24\n\tv_mul_lo_u32 v4, v4, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v5, v10, v5\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v4, vcc_lo, v8, v4\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo\n\tglobal_load_b64 v[4:5], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[8:9], v[6:7]\n\ts_cbranch_execz .LBB0_123\n; %bb.120:\n\ts_mov_b32 s5, 0\n\t.p2align\t6\n.LBB0_121: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[4:5], v3, s[2:3] offset:40\n\tglobal_load_b64 v[10:11], v3, s[2:3]\n\tv_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v4, v4, v6\n\tv_and_b32_e32 v5, v5, v7\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[8:9], null, v4, 24, v[10:11]\n\tv_mov_b32_e32 v4, v9\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_mad_u64_u32 v[9:10], null, v5, 24, v[4:5]\n\tglobal_load_b64 v[4:5], v[8:9], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7]\n\ts_or_b32 s5, vcc_lo, s5\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s5\n\ts_cbranch_execnz .LBB0_121\n; %bb.122:\n\ts_or_b32 exec_lo, exec_lo, s5\n.LBB0_123:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s4\n.LBB0_124:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v3, 0\n\tv_readfirstlane_b32 s4, v8\n\tv_readfirstlane_b32 s5, v9\n\ts_mov_b32 s10, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[10:11], v3, s[2:3] offset:40\n\tglobal_load_b128 v[4:7], v3, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s6, v10\n\tv_readfirstlane_b32 s7, v11\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[6:7], s[4:5], s[6:7]\n\ts_mul_i32 s1, s7, 24\n\ts_mul_hi_u32 s8, s6, 24\n\ts_mul_i32 s9, s6, 24\n\ts_and_saveexec_b32 s11, s0\n\ts_cbranch_execz .LBB0_126\n; %bb.125:\n\tv_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, v3\n\ts_add_i32 s10, s8, s1\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v12, vcc_lo, v4, s9\n\tv_add_co_ci_u32_e32 v13, vcc_lo, s10, v5, vcc_lo\n\tv_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1\n\tglobal_store_b128 v[12:13], v[8:11], off offset:8\n.LBB0_126:\n\ts_or_b32 exec_lo, exec_lo, s11\n\ts_lshl_b64 s[6:7], s[6:7], 12\n\tv_lshlrev_b64 v[8:9], 6, v[2:3]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v2, vcc_lo, v6, s6\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo\n\ts_mov_b32 s12, 0\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_u32 v6, vcc_lo, v2, v8\n\ts_mov_b32 s13, s12\n\ts_mov_b32 s14, s12\n\ts_mov_b32 s15, s12\n\tv_and_or_b32 v0, 0xffffff1f, v0, 32\n\tv_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo\n\tv_mov_b32_e32 v2, v3\n\tv_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s15\n\tv_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14\n\ts_clause 0x3\n\tglobal_store_b128 v[6:7], v[0:3], off\n\tglobal_store_b128 v[6:7], v[8:11], off offset:16\n\tglobal_store_b128 v[6:7], v[8:11], off offset:32\n\tglobal_store_b128 v[6:7], v[8:11], off offset:48\n\ts_and_saveexec_b32 s6, s0\n\ts_cbranch_execz .LBB0_134\n; %bb.127:\n\tv_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4\n\tv_mov_b32_e32 v12, s5\n\ts_clause 0x1\n\tglobal_load_b64 v[13:14], v10, s[2:3] offset:32 glc\n\tglobal_load_b64 v[0:1], v10, s[2:3] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s10, v0\n\tv_readfirstlane_b32 s11, v1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[10:11], s[10:11], s[4:5]\n\ts_mul_i32 s7, s11, 24\n\ts_mul_hi_u32 s11, s10, 24\n\ts_mul_i32 s10, s10, 24\n\ts_add_i32 s11, s11, s7\n\tv_add_co_u32 v8, vcc_lo, v4, s10\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s11, v5, vcc_lo\n\ts_mov_b32 s7, exec_lo\n\tglobal_store_b64 v[8:9], v[13:14], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[2:3], v[13:14]\n\ts_cbranch_execz .LBB0_130\n; %bb.128:\n\ts_mov_b32 s10, 0\n.LBB0_129: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5\n\ts_sleep 1\n\tglobal_store_b64 v[8:9], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]\n\tv_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0\n\ts_or_b32 s10, vcc_lo, s10\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s10\n\ts_cbranch_execnz .LBB0_129\n.LBB0_130:\n\ts_or_b32 exec_lo, exec_lo, s7\n\tv_mov_b32_e32 v3, 0\n\ts_mov_b32 s10, exec_lo\n\ts_mov_b32 s7, exec_lo\n\tv_mbcnt_lo_u32_b32 v2, s10, 0\n\tglobal_load_b64 v[0:1], v3, s[2:3] offset:16\n\tv_cmpx_eq_u32_e32 0, v2\n\ts_cbranch_execz .LBB0_132\n; %bb.131:\n\ts_bcnt1_i32_b32 s10, s10\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_mov_b32_e32 v2, s10\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off offset:8\n.LBB0_132:\n\ts_or_b32 exec_lo, exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\ts_cbranch_vccnz .LBB0_134\n; %bb.133:\n\tglobal_load_b32 v0, v[0:1], off offset:24\n\tv_mov_b32_e32 v1, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s7, v0\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[2:3], v[0:1], off\n\ts_and_b32 m0, s7, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB0_134:\n\ts_or_b32 exec_lo, exec_lo, s6\n\ts_add_i32 s8, s8, s1\n\tv_add_co_u32 v0, vcc_lo, v4, s9\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s8, v5, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB0_138\n\t.p2align\t6\n.LBB0_135: ; in Loop: Header=BB0_138 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB0_137\n; %bb.136: ; in Loop: Header=BB0_138 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB0_138\n\ts_branch .LBB0_140\n\t.p2align\t6\n.LBB0_137:\n\ts_branch .LBB0_140\n.LBB0_138: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB0_135\n; %bb.139: ; in Loop: Header=BB0_138 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB0_135\n.LBB0_140:\n\tglobal_load_b128 v[2:5], v[6:7], off\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB0_144\n; %bb.141:\n\tv_mov_b32_e32 v8, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[0:1], v8, s[2:3] offset:40\n\tglobal_load_b64 v[9:10], v8, s[2:3] offset:24 glc\n\tglobal_load_b64 v[6:7], v8, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v11, vcc_lo, v0, 1\n\tv_add_co_ci_u32_e32 v12, vcc_lo, 0, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v4, vcc_lo, v11, s4\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s5, v12, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]\n\tv_dual_cndmask_b32 v5, v5, v12 :: v_dual_cndmask_b32 v4, v4, v11\n\tv_and_b32_e32 v1, v5, v1\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v0, v4, v0\n\tv_mul_lo_u32 v1, v1, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v11, v0, 24\n\tv_mul_lo_u32 v0, v0, 24\n\tv_add_nc_u32_e32 v1, v11, v1\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v0, vcc_lo, v6, v0\n\tv_mov_b32_e32 v6, v9\n\tv_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo\n\tv_mov_b32_e32 v7, v10\n\tglobal_store_b64 v[0:1], v[9:10], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[6:7], v8, v[4:7], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[6:7], v[9:10]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB0_144\n; %bb.142:\n\ts_mov_b32 s0, 0\n.LBB0_143: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[0:1], v[6:7], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[9:10], v8, v[4:7], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[9:10], v[6:7]\n\tv_dual_mov_b32 v6, v9 :: v_dual_mov_b32 v7, v10\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB0_143\n.LBB0_144:\n\ts_or_b32 exec_lo, exec_lo, s1\n.LBB0_145:\n\t;;#ASMSTART\n\t;;#ASMEND\n\tv_readfirstlane_b32 s0, v28\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, 0\n\tv_mov_b32_e32 v1, 0\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u32_e64 s0, s0, v28\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB0_151\n; %bb.146:\n\tv_mov_b32_e32 v4, 0\n\ts_mov_b32 s4, exec_lo\n\tglobal_load_b64 v[7:8], v4, s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_clause 0x1\n\tglobal_load_b64 v[0:1], v4, s[2:3] offset:40\n\tglobal_load_b64 v[5:6], v4, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_and_b32_e32 v1, v1, v8\n\tv_and_b32_e32 v0, v0, v7\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v1, v1, 24\n\tv_mul_hi_u32 v9, v0, 24\n\tv_mul_lo_u32 v0, v0, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v1, v9, v1\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v0, vcc_lo, v5, v0\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v1, vcc_lo, v6, v1, vcc_lo\n\tglobal_load_b64 v[5:6], v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[0:1], v4, v[5:8], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmpx_ne_u64_e64 v[0:1], v[7:8]\n\ts_cbranch_execz .LBB0_150\n; %bb.147:\n\ts_mov_b32 s5, 0\n\t.p2align\t6\n.LBB0_148: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\ts_clause 0x1\n\tglobal_load_b64 v[5:6], v4, s[2:3] offset:40\n\tglobal_load_b64 v[9:10], v4, s[2:3]\n\tv_dual_mov_b32 v8, v1 :: v_dual_mov_b32 v7, v0\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_and_b32_e32 v5, v5, v7\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[0:1], null, v5, 24, v[9:10]\n\tv_and_b32_e32 v9, v6, v8\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[5:6], null, v9, 24, v[1:2]\n\tv_mov_b32_e32 v1, v5\n\tglobal_load_b64 v[5:6], v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_cmpswap_b64 v[0:1], v4, v[5:8], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e32 vcc_lo, v[0:1], v[7:8]\n\ts_or_b32 s5, vcc_lo, s5\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s5\n\ts_cbranch_execnz .LBB0_148\n; %bb.149:\n\ts_or_b32 exec_lo, exec_lo, s5\n.LBB0_150:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s4\n.LBB0_151:\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_mov_b32_e32 v29, 0\n\tv_readfirstlane_b32 s4, v0\n\tv_readfirstlane_b32 s5, v1\n\ts_mov_b32 s10, exec_lo\n\ts_clause 0x1\n\tglobal_load_b64 v[4:5], v29, s[2:3] offset:40\n\tglobal_load_b128 v[6:9], v29, s[2:3]\n\ts_waitcnt vmcnt(1)\n\tv_readfirstlane_b32 s6, v4\n\tv_readfirstlane_b32 s7, v5\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[6:7], s[4:5], s[6:7]\n\ts_mul_i32 s1, s7, 24\n\ts_mul_hi_u32 s8, s6, 24\n\ts_mul_i32 s9, s6, 24\n\ts_and_saveexec_b32 s11, s0\n\ts_cbranch_execz .LBB0_153\n; %bb.152:\n\tv_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, v29\n\ts_add_i32 s10, s8, s1\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v0, vcc_lo, v6, s9\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s10, v7, vcc_lo\n\tv_dual_mov_b32 v12, 2 :: v_dual_mov_b32 v13, 1\n\tglobal_store_b128 v[0:1], v[10:13], off offset:8\n.LBB0_153:\n\ts_or_b32 exec_lo, exec_lo, s11\n\tv_cvt_f64_f32_e32 v[4:5], v31\n\ts_lshl_b64 s[6:7], s[6:7], 12\n\tv_lshlrev_b64 v[0:1], 6, v[28:29]\n\ts_waitcnt vmcnt(0)\n\tv_add_co_u32 v8, vcc_lo, v8, s6\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo\n\ts_mov_b32 s12, 0\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v8, v0\n\ts_mov_b32 s13, s12\n\ts_mov_b32 s14, s12\n\ts_mov_b32 s15, s12\n\tv_and_or_b32 v2, 0xffffff1d, v2, 34\n\tv_add_co_ci_u32_e32 v1, vcc_lo, v9, v1, vcc_lo\n\tv_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13\n\tv_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15\n\ts_clause 0x3\n\tglobal_store_b128 v[0:1], v[2:5], off\n\tglobal_store_b128 v[0:1], v[8:11], off offset:16\n\tglobal_store_b128 v[0:1], v[8:11], off offset:32\n\tglobal_store_b128 v[0:1], v[8:11], off offset:48\n\ts_and_saveexec_b32 s6, s0\n\ts_cbranch_execz .LBB0_161\n; %bb.154:\n\tv_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4\n\tv_mov_b32_e32 v10, s5\n\ts_clause 0x1\n\tglobal_load_b64 v[11:12], v8, s[2:3] offset:32 glc\n\tglobal_load_b64 v[0:1], v8, s[2:3] offset:40\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s10, v0\n\tv_readfirstlane_b32 s11, v1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b64 s[10:11], s[10:11], s[4:5]\n\ts_mul_i32 s7, s11, 24\n\ts_mul_hi_u32 s11, s10, 24\n\ts_mul_i32 s10, s10, 24\n\ts_add_i32 s11, s11, s7\n\tv_add_co_u32 v4, vcc_lo, v6, s10\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s11, v7, vcc_lo\n\ts_mov_b32 s7, exec_lo\n\tglobal_store_b64 v[4:5], v[11:12], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u64_e64 v[2:3], v[11:12]\n\ts_cbranch_execz .LBB0_157\n; %bb.155:\n\ts_mov_b32 s10, 0\n.LBB0_156: ; =>This Inner Loop Header: Depth=1\n\tv_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[2:3] offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]\n\tv_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0\n\ts_or_b32 s10, vcc_lo, s10\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s10\n\ts_cbranch_execnz .LBB0_156\n.LBB0_157:\n\ts_or_b32 exec_lo, exec_lo, s7\n\tv_mov_b32_e32 v3, 0\n\ts_mov_b32 s10, exec_lo\n\ts_mov_b32 s7, exec_lo\n\tv_mbcnt_lo_u32_b32 v2, s10, 0\n\tglobal_load_b64 v[0:1], v3, s[2:3] offset:16\n\tv_cmpx_eq_u32_e32 0, v2\n\ts_cbranch_execz .LBB0_159\n; %bb.158:\n\ts_bcnt1_i32_b32 s10, s10\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_mov_b32_e32 v2, s10\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off offset:8\n.LBB0_159:\n\ts_or_b32 exec_lo, exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]\n\ts_cbranch_vccnz .LBB0_161\n; %bb.160:\n\tglobal_load_b32 v0, v[0:1], off offset:24\n\tv_mov_b32_e32 v1, 0\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s7, v0\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[2:3], v[0:1], off\n\ts_and_b32 m0, s7, 0xff\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB0_161:\n\ts_or_b32 exec_lo, exec_lo, s6\n\ts_add_i32 s8, s8, s1\n\tv_add_co_u32 v0, vcc_lo, v6, s9\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s8, v7, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, 20\n\tv_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo\n\ts_branch .LBB0_165\n\t.p2align\t6\n.LBB0_162: ; in Loop: Header=BB0_165 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_readfirstlane_b32 s1, v2\n\ts_cmp_eq_u32 s1, 0\n\ts_cbranch_scc1 .LBB0_164\n; %bb.163: ; in Loop: Header=BB0_165 Depth=1\n\ts_sleep 1\n\ts_cbranch_execnz .LBB0_165\n\ts_branch .LBB0_167\n\t.p2align\t6\n.LBB0_164:\n\ts_branch .LBB0_167\n.LBB0_165: ; =>This Inner Loop Header: Depth=1\n\tv_mov_b32_e32 v2, 1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB0_162\n; %bb.166: ; in Loop: Header=BB0_165 Depth=1\n\tglobal_load_b32 v2, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_and_b32_e32 v2, 1, v2\n\ts_branch .LBB0_162\n.LBB0_167:\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB0_171\n; %bb.168:\n\tv_mov_b32_e32 v6, 0\n\ts_clause 0x2\n\tglobal_load_b64 v[2:3], v6, s[2:3] offset:40\n\tglobal_load_b64 v[7:8], v6, s[2:3] offset:24 glc\n\tglobal_load_b64 v[4:5], v6, s[2:3]\n\ts_waitcnt vmcnt(2)\n\tv_add_co_u32 v9, vcc_lo, v2, 1\n\tv_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v9, s4\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]\n\tv_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9\n\tv_and_b32_e32 v3, v1, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_and_b32_e32 v2, v0, v2\n\tv_mul_lo_u32 v3, v3, 24\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v9, v2, 24\n\tv_mul_lo_u32 v2, v2, 24\n\tv_add_nc_u32_e32 v3, v9, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v4, vcc_lo, v4, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo\n\tv_mov_b32_e32 v3, v8\n\tglobal_store_b64 v[4:5], v[7:8], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB0_171\n; %bb.169:\n\ts_mov_b32 s0, 0\n.LBB0_170: ; =>This Inner Loop Header: Depth=1\n\ts_sleep 1\n\tglobal_store_b64 v[4:5], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]\n\tv_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8\n\ts_or_b32 s0, vcc_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB0_170\n.LBB0_171:\n\ts_nop 0\n\ts_sendmsg sendmsg(MSG_DEALLOC_VGPRS)\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z7computefiffPfS_fffffffffffffffffff\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 368\n\t\t.amdhsa_user_sgpr_count 15\n\t\t.amdhsa_user_sgpr_dispatch_ptr 0\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 0\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 0\n\t\t.amdhsa_next_free_vgpr 33\n\t\t.amdhsa_next_free_sgpr 28\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end0:\n\t.size\t_Z7computefiffPfS_fffffffffffffffffff, .Lfunc_end0-_Z7computefiffPfS_fffffffffffffffffff\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 10492\n; NumSgprs: 30\n; NumVgprs: 33\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 3\n; VGPRBlocks: 4\n; NumSGPRsForWavesPerEU: 30\n; NumVGPRsForWavesPerEU: 33\n; Occupancy: 16\n; WaveLimiterHint : 1\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 15\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t.str,@object ; @.str\n\t.section\t.rodata.str1.1,\"aMS\",@progbits,1\n.str:\n\t.asciz\t\"%.17g\\n\"\n\t.size\t.str, 7\n\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .offset: 0\n .size: 4\n .value_kind: by_value\n - .offset: 4\n .size: 4\n .value_kind: by_value\n - .offset: 8\n .size: 4\n .value_kind: by_value\n - .offset: 12\n .size: 4\n .value_kind: by_value\n - .address_space: global\n .offset: 16\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 24\n .size: 8\n .value_kind: global_buffer\n - .offset: 32\n .size: 4\n .value_kind: by_value\n - .offset: 36\n .size: 4\n .value_kind: by_value\n - .offset: 40\n .size: 4\n .value_kind: by_value\n - .offset: 44\n .size: 4\n .value_kind: by_value\n - .offset: 48\n .size: 4\n .value_kind: by_value\n - .offset: 52\n .size: 4\n .value_kind: by_value\n - .offset: 56\n .size: 4\n .value_kind: by_value\n - .offset: 60\n .size: 4\n .value_kind: by_value\n - .offset: 64\n .size: 4\n .value_kind: by_value\n - .offset: 68\n .size: 4\n .value_kind: by_value\n - .offset: 72\n .size: 4\n .value_kind: by_value\n - .offset: 76\n .size: 4\n .value_kind: by_value\n - .offset: 80\n .size: 4\n .value_kind: by_value\n - .offset: 84\n .size: 4\n .value_kind: by_value\n - .offset: 88\n .size: 4\n .value_kind: by_value\n - .offset: 92\n .size: 4\n .value_kind: by_value\n - .offset: 96\n .size: 4\n .value_kind: by_value\n - .offset: 100\n .size: 4\n .value_kind: by_value\n - .offset: 104\n .size: 4\n .value_kind: by_value\n - .offset: 112\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 116\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 120\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 124\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 126\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 128\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 130\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 132\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 134\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 152\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 160\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 168\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 176\n .size: 2\n .value_kind: hidden_grid_dims\n - .offset: 192\n .size: 8\n .value_kind: hidden_hostcall_buffer\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 368\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z7computefiffPfS_fffffffffffffffffff\n .private_segment_fixed_size: 0\n .sgpr_count: 30\n .sgpr_spill_count: 0\n .symbol: _Z7computefiffPfS_fffffffffffffffffff.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 33\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162575,"cells":{"id":{"kind":"string","value":"88ce57f0c8b1396007b3ae5a18d42bdb4b509218_O2"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z18heatEquationKernelPfS_if --------------------------\n .section .text._Z18heatEquationKernelPfS_if,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=12\"\n .align 128\n\n\n\n\n .global _Z18heatEquationKernelPfS_if\n .type _Z18heatEquationKernelPfS_if,@function\n .size _Z18heatEquationKernelPfS_if,(.L_x_1 - _Z18heatEquationKernelPfS_if)\n .other _Z18heatEquationKernelPfS_if,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z18heatEquationKernelPfS_if:\n.text._Z18heatEquationKernelPfS_if:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ S2R R4, SR_CTAID.X ;\n /*0020*/ ULDC UR4, c[0x0][0x170] ;\n /*0030*/ UIADD3 UR4, UR4, -0x1, URZ ;\n /*0040*/ S2R R3, SR_TID.X ;\n /*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ;\n /*0060*/ ISETP.GE.AND P0, PT, R4, UR4, PT ;\n /*0070*/ ISETP.LT.OR P0, PT, R4, 0x1, P0 ;\n /*0080*/ @P0 EXIT ;\n /*0090*/ MOV R9, 0x4 ;\n /*00a0*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*00b0*/ IMAD.WIDE R2, R4, R9, c[0x0][0x168] ;\n /*00c0*/ LDG.E R0, [R2.64] ;\n /*00d0*/ LDG.E R5, [R2.64+0x4] ;\n /*00e0*/ LDG.E R8, [R2.64+-0x4] ;\n /*00f0*/ FADD R6, R0, R0 ;\n /*0100*/ FADD R5, R5, -R6 ;\n /*0110*/ FADD R7, R5, R8 ;\n /*0120*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ;\n /*0130*/ FFMA R7, R7, c[0x0][0x174], R0 ;\n /*0140*/ STG.E [R4.64], R7 ;\n /*0150*/ EXIT ;\n.L_x_0:\n /*0160*/ BRA `(.L_x_0);\n /*0170*/ NOP;\n /*0180*/ NOP;\n /*0190*/ NOP;\n /*01a0*/ NOP;\n /*01b0*/ NOP;\n /*01c0*/ NOP;\n /*01d0*/ NOP;\n /*01e0*/ NOP;\n /*01f0*/ NOP;\n.L_x_1:\n"},"hip":{"kind":"string","value":"\t.text\n\t.file\t\"cuda_code_078126.hip\"\n\t.globl\t_Z33__device_stub__heatEquationKernelPfS_if # -- Begin function _Z33__device_stub__heatEquationKernelPfS_if\n\t.p2align\t4, 0x90\n\t.type\t_Z33__device_stub__heatEquationKernelPfS_if,@function\n_Z33__device_stub__heatEquationKernelPfS_if: # @_Z33__device_stub__heatEquationKernelPfS_if\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$120, %rsp\n\t.cfi_def_cfa_offset 128\n\tmovq\t%rdi, 72(%rsp)\n\tmovq\t%rsi, 64(%rsp)\n\tmovl\t%edx, 12(%rsp)\n\tmovss\t%xmm0, 8(%rsp)\n\tleaq\t72(%rsp), %rax\n\tmovq\t%rax, 80(%rsp)\n\tleaq\t64(%rsp), %rax\n\tmovq\t%rax, 88(%rsp)\n\tleaq\t12(%rsp), %rax\n\tmovq\t%rax, 96(%rsp)\n\tleaq\t8(%rsp), %rax\n\tmovq\t%rax, 104(%rsp)\n\tleaq\t48(%rsp), %rdi\n\tleaq\t32(%rsp), %rsi\n\tleaq\t24(%rsp), %rdx\n\tleaq\t16(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t48(%rsp), %rsi\n\tmovl\t56(%rsp), %edx\n\tmovq\t32(%rsp), %rcx\n\tmovl\t40(%rsp), %r8d\n\tleaq\t80(%rsp), %r9\n\tmovl\t$_Z18heatEquationKernelPfS_if, %edi\n\tpushq\t16(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t32(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$136, %rsp\n\t.cfi_adjust_cfa_offset -136\n\tretq\n.Lfunc_end0:\n\t.size\t_Z33__device_stub__heatEquationKernelPfS_if, .Lfunc_end0-_Z33__device_stub__heatEquationKernelPfS_if\n\t.cfi_endproc\n # -- End function\n\t.section\t.rodata.cst8,\"aM\",@progbits,8\n\t.p2align\t3, 0x0 # -- Begin function main\n.LCPI1_0:\n\t.quad\t0x401921fb54442d18 # double 6.2831853071795862\n.LCPI1_1:\n\t.quad\t0x3f70000000000000 # double 0.00390625\n\t.text\n\t.globl\tmain\n\t.p2align\t4, 0x90\n\t.type\tmain,@function\nmain: # @main\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rbp\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r15\n\t.cfi_def_cfa_offset 24\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 32\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 40\n\tsubq\t$136, %rsp\n\t.cfi_def_cfa_offset 176\n\t.cfi_offset %rbx, -40\n\t.cfi_offset %r14, -32\n\t.cfi_offset %r15, -24\n\t.cfi_offset %rbp, -16\n\tmovl\t$1024, %edi # imm = 0x400\n\tcallq\t_Znam\n\tmovq\t%rax, %rbx\n\tmovl\t$1024, %edi # imm = 0x400\n\tcallq\t_Znam\n\tmovq\t%rax, %r14\n\txorl\t%r15d, %r15d\n\t.p2align\t4, 0x90\n.LBB1_1: # =>This Inner Loop Header: Depth=1\n\txorps\t%xmm0, %xmm0\n\tcvtsi2sd\t%r15d, %xmm0\n\tmovsd\t.LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero\n\tmulsd\t%xmm1, %xmm0\n\tmovsd\t.LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero\n\tmulsd\t%xmm1, %xmm0\n\tcvtsd2ss\t%xmm0, %xmm0\n\tcallq\tsinf\n\tmovss\t%xmm0, (%rbx,%r15,4)\n\tleal\t1(%r15), %eax\n\txorps\t%xmm0, %xmm0\n\tcvtsi2sd\t%eax, %xmm0\n\tmulsd\t.LCPI1_0(%rip), %xmm0\n\tmulsd\t.LCPI1_1(%rip), %xmm0\n\tcvtsd2ss\t%xmm0, %xmm0\n\tcallq\tsinf\n\tmovss\t%xmm0, 4(%rbx,%r15,4)\n\taddq\t$2, %r15\n\tcmpq\t$256, %r15 # imm = 0x100\n\tjne\t.LBB1_1\n# %bb.2:\n\tleaq\t16(%rsp), %rdi\n\tmovl\t$1024, %esi # imm = 0x400\n\tcallq\thipMalloc\n\tleaq\t8(%rsp), %rdi\n\tmovl\t$1024, %esi # imm = 0x400\n\tcallq\thipMalloc\n\tmovq\t16(%rsp), %rdi\n\tmovl\t$1024, %edx # imm = 0x400\n\tmovq\t%rbx, %rsi\n\tmovl\t$1, %ecx\n\tcallq\thipMemcpy\n\tmovabsq\t$4294967304, %rdi # imm = 0x100000008\n\tleaq\t24(%rdi), %rdx\n\tmovl\t$1, %esi\n\tmovl\t$1, %ecx\n\txorl\t%r8d, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipPushCallConfiguration\n\ttestl\t%eax, %eax\n\tjne\t.LBB1_4\n# %bb.3:\n\tmovq\t8(%rsp), %rax\n\tmovq\t16(%rsp), %rcx\n\tmovq\t%rax, 88(%rsp)\n\tmovq\t%rcx, 80(%rsp)\n\tmovl\t$256, 28(%rsp) # imm = 0x100\n\tmovl\t$1008981770, 24(%rsp) # imm = 0x3C23D70A\n\tleaq\t88(%rsp), %rax\n\tmovq\t%rax, 96(%rsp)\n\tleaq\t80(%rsp), %rax\n\tmovq\t%rax, 104(%rsp)\n\tleaq\t28(%rsp), %rax\n\tmovq\t%rax, 112(%rsp)\n\tleaq\t24(%rsp), %rax\n\tmovq\t%rax, 120(%rsp)\n\tleaq\t64(%rsp), %rdi\n\tleaq\t48(%rsp), %rsi\n\tleaq\t40(%rsp), %rdx\n\tleaq\t32(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t64(%rsp), %rsi\n\tmovl\t72(%rsp), %edx\n\tmovq\t48(%rsp), %rcx\n\tmovl\t56(%rsp), %r8d\n\tleaq\t96(%rsp), %r9\n\tmovl\t$_Z18heatEquationKernelPfS_if, %edi\n\tpushq\t32(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t48(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$16, %rsp\n\t.cfi_adjust_cfa_offset -16\n.LBB1_4:\n\tcallq\thipGetLastError\n\ttestl\t%eax, %eax\n\tje\t.LBB1_13\n# %bb.5:\n\tmovl\t%eax, %ebp\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$27, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n\tmovl\t%ebp, %edi\n\tcallq\thipGetErrorString\n\ttestq\t%rax, %rax\n\tje\t.LBB1_6\n# %bb.7:\n\tmovq\t%rax, %rdi\n\tmovq\t%rax, %rbx\n\tcallq\tstrlen\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rbx, %rsi\n\tmovq\t%rax, %rdx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n\tjmp\t.LBB1_8\n.LBB1_13:\n\tmovq\t8(%rsp), %rsi\n\tmovl\t$1024, %edx # imm = 0x400\n\tmovq\t%r14, %rdi\n\tmovl\t$2, %ecx\n\tcallq\thipMemcpy\n\tmovq\t16(%rsp), %rdi\n\tcallq\thipFree\n\tmovq\t8(%rsp), %rdi\n\tcallq\thipFree\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZdaPv\n\tmovq\t%r14, %rdi\n\tcallq\t_ZdaPv\n\txorl\t%eax, %eax\n\tjmp\t.LBB1_14\n.LBB1_6:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tleaq\t_ZSt4cerr(%rax), %rdi\n\tmovl\t_ZSt4cerr+32(%rax), %esi\n\torl\t$1, %esi\n\tcallq\t_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate\n.LBB1_8:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tmovq\t_ZSt4cerr+240(%rax), %rbx\n\ttestq\t%rbx, %rbx\n\tje\t.LBB1_15\n# %bb.9:\n\tcmpb\t$0, 56(%rbx)\n\tje\t.LBB1_11\n# %bb.10:\n\tmovzbl\t67(%rbx), %eax\n\tjmp\t.LBB1_12\n.LBB1_11:\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZNKSt5ctypeIcE13_M_widen_initEv\n\tmovq\t(%rbx), %rax\n\tmovq\t%rbx, %rdi\n\tmovl\t$10, %esi\n\tcallq\t*48(%rax)\n.LBB1_12:\n\tmovsbl\t%al, %esi\n\tmovl\t$_ZSt4cerr, %edi\n\tcallq\t_ZNSo3putEc\n\tmovq\t%rax, %rdi\n\tcallq\t_ZNSo5flushEv\n\tmovl\t$-1, %eax\n.LBB1_14:\n\taddq\t$136, %rsp\n\t.cfi_def_cfa_offset 40\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 32\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r15\n\t.cfi_def_cfa_offset 16\n\tpopq\t%rbp\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB1_15:\n\t.cfi_def_cfa_offset 176\n\tcallq\t_ZSt16__throw_bad_castv\n.Lfunc_end1:\n\t.size\tmain, .Lfunc_end1-main\n\t.cfi_endproc\n # -- End function\n\t.section\t.text.startup,\"ax\",@progbits\n\t.p2align\t4, 0x90 # -- Begin function _GLOBAL__sub_I_cuda_code_078126.hip\n\t.type\t_GLOBAL__sub_I_cuda_code_078126.hip,@function\n_GLOBAL__sub_I_cuda_code_078126.hip: # @_GLOBAL__sub_I_cuda_code_078126.hip\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 16\n\tmovl\t$_ZStL8__ioinit, %edi\n\tcallq\t_ZNSt8ios_base4InitC1Ev\n\tmovl\t$_ZNSt8ios_base4InitD1Ev, %edi\n\tmovl\t$_ZStL8__ioinit, %esi\n\tmovl\t$__dso_handle, %edx\n\tpopq\t%rax\n\t.cfi_def_cfa_offset 8\n\tjmp\t__cxa_atexit # TAILCALL\n.Lfunc_end2:\n\t.size\t_GLOBAL__sub_I_cuda_code_078126.hip, .Lfunc_end2-_GLOBAL__sub_I_cuda_code_078126.hip\n\t.cfi_endproc\n # -- End function\n\t.text\n\t.p2align\t4, 0x90 # -- Begin function __hip_module_ctor\n\t.type\t__hip_module_ctor,@function\n__hip_module_ctor: # @__hip_module_ctor\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$40, %rsp\n\t.cfi_def_cfa_offset 48\n\tmovq\t__hip_gpubin_handle(%rip), %rdi\n\ttestq\t%rdi, %rdi\n\tjne\t.LBB3_2\n# %bb.1:\n\tmovl\t$__hip_fatbin_wrapper, %edi\n\tcallq\t__hipRegisterFatBinary\n\tmovq\t%rax, %rdi\n\tmovq\t%rax, __hip_gpubin_handle(%rip)\n.LBB3_2:\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, 16(%rsp)\n\tmovups\t%xmm0, (%rsp)\n\tmovl\t$_Z18heatEquationKernelPfS_if, %esi\n\tmovl\t$.L__unnamed_1, %edx\n\tmovl\t$.L__unnamed_1, %ecx\n\tmovl\t$-1, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipRegisterFunction\n\tmovl\t$__hip_module_dtor, %edi\n\taddq\t$40, %rsp\n\t.cfi_def_cfa_offset 8\n\tjmp\tatexit # TAILCALL\n.Lfunc_end3:\n\t.size\t__hip_module_ctor, .Lfunc_end3-__hip_module_ctor\n\t.cfi_endproc\n # -- End function\n\t.p2align\t4, 0x90 # -- Begin function __hip_module_dtor\n\t.type\t__hip_module_dtor,@function\n__hip_module_dtor: # @__hip_module_dtor\n\t.cfi_startproc\n# %bb.0:\n\tmovq\t__hip_gpubin_handle(%rip), %rdi\n\ttestq\t%rdi, %rdi\n\tje\t.LBB4_2\n# %bb.1:\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 16\n\tcallq\t__hipUnregisterFatBinary\n\tmovq\t$0, __hip_gpubin_handle(%rip)\n\taddq\t$8, %rsp\n\t.cfi_def_cfa_offset 8\n.LBB4_2:\n\tretq\n.Lfunc_end4:\n\t.size\t__hip_module_dtor, .Lfunc_end4-__hip_module_dtor\n\t.cfi_endproc\n # -- End function\n\t.type\t_ZStL8__ioinit,@object # @_ZStL8__ioinit\n\t.local\t_ZStL8__ioinit\n\t.comm\t_ZStL8__ioinit,1,1\n\t.hidden\t__dso_handle\n\t.type\t_Z18heatEquationKernelPfS_if,@object # @_Z18heatEquationKernelPfS_if\n\t.section\t.rodata,\"a\",@progbits\n\t.globl\t_Z18heatEquationKernelPfS_if\n\t.p2align\t3, 0x0\n_Z18heatEquationKernelPfS_if:\n\t.quad\t_Z33__device_stub__heatEquationKernelPfS_if\n\t.size\t_Z18heatEquationKernelPfS_if, 8\n\n\t.type\t.L.str,@object # @.str\n\t.section\t.rodata.str1.1,\"aMS\",@progbits,1\n.L.str:\n\t.asciz\t\"CUDA kernel launch failed: \"\n\t.size\t.L.str, 28\n\n\t.type\t.L__unnamed_1,@object # @0\n.L__unnamed_1:\n\t.asciz\t\"_Z18heatEquationKernelPfS_if\"\n\t.size\t.L__unnamed_1, 29\n\n\t.type\t__hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper\n\t.section\t.hipFatBinSegment,\"a\",@progbits\n\t.p2align\t3, 0x0\n__hip_fatbin_wrapper:\n\t.long\t1212764230 # 0x48495046\n\t.long\t1 # 0x1\n\t.quad\t__hip_fatbin\n\t.quad\t0\n\t.size\t__hip_fatbin_wrapper, 24\n\n\t.type\t__hip_gpubin_handle,@object # @__hip_gpubin_handle\n\t.local\t__hip_gpubin_handle\n\t.comm\t__hip_gpubin_handle,8,8\n\t.section\t.init_array,\"aw\",@init_array\n\t.p2align\t3, 0x0\n\t.quad\t_GLOBAL__sub_I_cuda_code_078126.hip\n\t.quad\t__hip_module_ctor\n\t.type\t__hip_cuid_,@object # @__hip_cuid_\n\t.bss\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 # 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n"}}},{"rowIdx":162576,"cells":{"id":{"kind":"string","value":"3fd068f20ed5a7708016b7e4c7c204c315b59a20_O1"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text.lessthanorequal_scalar_float --------------------------\n .section .text.lessthanorequal_scalar_float,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=24\"\n .align 128\n\n\n\n\n .global lessthanorequal_scalar_float\n .type lessthanorequal_scalar_float,@function\n .size lessthanorequal_scalar_float,(.L_x_5 - lessthanorequal_scalar_float)\n .other lessthanorequal_scalar_float,@\"STO_CUDA_ENTRY STV_DEFAULT\"\nlessthanorequal_scalar_float:\n.text.lessthanorequal_scalar_float:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ S2R R3, SR_CTAID.X ;\n /*0020*/ S2R R0, SR_TID.X ;\n /*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ;\n /*0040*/ MOV R0, c[0x0][0x0] ;\n /*0050*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ;\n /*0060*/ IMAD R0, R0, c[0x0][0xc], RZ ;\n /*0070*/ @P0 EXIT ;\n /*0080*/ I2F.U32.RP R6, R0 ;\n /*0090*/ IMAD.MOV R7, RZ, RZ, -R0 ;\n /*00a0*/ ISETP.NE.U32.AND P2, PT, R0.reuse, RZ, PT ;\n /*00b0*/ IMAD.IADD R2, R0, 0x1, R3 ;\n /*00c0*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*00d0*/ BSSY B0, `(.L_x_0) ;\n /*00e0*/ MUFU.RCP R6, R6 ;\n /*00f0*/ IADD3 R4, R6, 0xffffffe, RZ ;\n /*0100*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ;\n /*0110*/ MOV R4, RZ ;\n /*0120*/ IMAD R7, R7, R5, RZ ;\n /*0130*/ IMAD.HI.U32 R8, R5, R7, R4 ;\n /*0140*/ LOP3.LUT R5, RZ, R2, RZ, 0x33, !PT ;\n /*0150*/ IADD3 R5, R5, c[0x0][0x160], R0 ;\n /*0160*/ IMAD.HI.U32 R8, R8, R5, RZ ;\n /*0170*/ IADD3 R2, -R8, RZ, RZ ;\n /*0180*/ IMAD R5, R0, R2, R5 ;\n /*0190*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ;\n /*01a0*/ @P0 IMAD.IADD R5, R5, 0x1, -R0 ;\n /*01b0*/ @P0 IADD3 R8, R8, 0x1, RZ ;\n /*01c0*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ;\n /*01d0*/ @P1 IADD3 R8, R8, 0x1, RZ ;\n /*01e0*/ @!P2 LOP3.LUT R8, RZ, R0, RZ, 0x33, !PT ;\n /*01f0*/ IADD3 R2, R8, 0x1, RZ ;\n /*0200*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ;\n /*0210*/ @!P0 BRA `(.L_x_1) ;\n /*0220*/ MOV R7, 0x4 ;\n /*0230*/ IMAD R6, R3, c[0x0][0x178], RZ ;\n /*0240*/ IMAD R9, R0, c[0x0][0x178], RZ ;\n /*0250*/ IMAD.WIDE R4, R6, R7, c[0x0][0x188] ;\n /*0260*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ;\n.L_x_2:\n /*0270*/ LDG.E R10, [R6.64] ;\n /*0280*/ IADD3 R2, R2, -0x1, RZ ;\n /*0290*/ IMAD.IADD R3, R0, 0x1, R3 ;\n /*02a0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ;\n /*02b0*/ IMAD.WIDE R6, R9, 0x4, R6 ;\n /*02c0*/ FSET.BF.LE.AND R11, R10, c[0x0][0x168], PT ;\n /*02d0*/ STG.E [R4.64], R11 ;\n /*02e0*/ IMAD.WIDE R4, R9, 0x4, R4 ;\n /*02f0*/ @P0 BRA `(.L_x_2) ;\n.L_x_1:\n /*0300*/ BSYNC B0 ;\n.L_x_0:\n /*0310*/ ISETP.GE.U32.AND P0, PT, R8, 0x3, PT ;\n /*0320*/ @!P0 EXIT ;\n /*0330*/ MOV R2, c[0x0][0x0] ;\n /*0340*/ IMAD R2, R2, c[0x0][0xc], RZ ;\n /*0350*/ IMAD R15, R2, c[0x0][0x178], RZ ;\n.L_x_3:\n /*0360*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ;\n /*0370*/ IMAD R6, R3, c[0x0][0x178], RZ ;\n /*0380*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ;\n /*0390*/ LDG.E R2, [R4.64] ;\n /*03a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x188] ;\n /*03b0*/ IMAD.WIDE R8, R15, 0x4, R4 ;\n /*03c0*/ FSET.BF.LE.AND R17, R2, c[0x0][0x168], PT ;\n /*03d0*/ STG.E [R6.64], R17 ;\n /*03e0*/ LDG.E R2, [R8.64] ;\n /*03f0*/ IMAD.WIDE R10, R15, 0x4, R6 ;\n /*0400*/ IMAD.WIDE R12, R15, 0x4, R8 ;\n /*0410*/ FSET.BF.LE.AND R19, R2, c[0x0][0x168], PT ;\n /*0420*/ STG.E [R10.64], R19 ;\n /*0430*/ LDG.E R2, [R12.64] ;\n /*0440*/ IMAD.WIDE R4, R15, 0x4, R10 ;\n /*0450*/ IMAD.WIDE R6, R15, 0x4, R12 ;\n /*0460*/ FSET.BF.LE.AND R21, R2, c[0x0][0x168], PT ;\n /*0470*/ STG.E [R4.64], R21 ;\n /*0480*/ LDG.E R6, [R6.64] ;\n /*0490*/ IMAD.WIDE R8, R15, 0x4, R4 ;\n /*04a0*/ IADD3 R3, R0, R3, R0 ;\n /*04b0*/ IADD3 R3, R0, R3, R0 ;\n /*04c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ;\n /*04d0*/ FSET.BF.LE.AND R17, R6, c[0x0][0x168], PT ;\n /*04e0*/ STG.E [R8.64], R17 ;\n /*04f0*/ @!P0 BRA `(.L_x_3) ;\n /*0500*/ EXIT ;\n.L_x_4:\n /*0510*/ BRA `(.L_x_4);\n /*0520*/ NOP;\n /*0530*/ NOP;\n /*0540*/ NOP;\n /*0550*/ NOP;\n /*0560*/ NOP;\n /*0570*/ NOP;\n /*0580*/ NOP;\n /*0590*/ NOP;\n /*05a0*/ NOP;\n /*05b0*/ NOP;\n /*05c0*/ NOP;\n /*05d0*/ NOP;\n /*05e0*/ NOP;\n /*05f0*/ NOP;\n.L_x_5:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.protected\tlessthanorequal_scalar_float ; -- Begin function lessthanorequal_scalar_float\n\t.globl\tlessthanorequal_scalar_float\n\t.p2align\t8\n\t.type\tlessthanorequal_scalar_float,@function\nlessthanorequal_scalar_float: ; @lessthanorequal_scalar_float\n; %bb.0:\n\ts_clause 0x1\n\ts_load_b32 s8, s[0:1], 0x30\n\ts_load_b32 s6, s[0:1], 0x0\n\ts_add_u32 s2, s0, 48\n\ts_addc_u32 s3, s1, 0\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_u32 s15, s8\n\ts_cselect_b32 s4, 12, 18\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)\n\tv_mov_b32_e32 v1, s4\n\tglobal_load_u16 v3, v1, s[2:3]\n\ts_mov_b32 s2, exec_lo\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[1:2], null, s15, v3, v[0:1]\n\tv_cmpx_gt_i32_e64 s6, v1\n\ts_cbranch_execz .LBB0_3\n; %bb.1:\n\ts_clause 0x3\n\ts_load_b32 s9, s[0:1], 0x18\n\ts_load_b32 s7, s[0:1], 0x8\n\ts_load_b64 s[2:3], s[0:1], 0x10\n\ts_load_b64 s[4:5], s[0:1], 0x28\n\tv_mul_lo_u32 v0, s8, v3\n\ts_mov_b32 s1, 0\n\ts_waitcnt lgkmcnt(0)\n\tv_mul_lo_u32 v2, s9, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_mul_lo_u32 v4, v0, s9\n\t.p2align\t6\n.LBB0_2: ; =>This Inner Loop Header: Depth=1\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_ashrrev_i32_e32 v3, 31, v2\n\tv_add_nc_u32_e32 v1, v1, v0\n\tv_lshlrev_b64 v[5:6], 2, v[2:3]\n\ts_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v2, v2, v4\n\tv_add_co_u32 v7, vcc_lo, s2, v5\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_add_co_ci_u32_e32 v8, vcc_lo, s3, v6, vcc_lo\n\tv_cmp_le_i32_e32 vcc_lo, s6, v1\n\tglobal_load_b32 v3, v[7:8], off\n\ts_or_b32 s1, vcc_lo, s1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_nge_f32_e64 s0, s7, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cndmask_b32_e64 v3, 1.0, 0, s0\n\tv_add_co_u32 v5, s0, s4, v5\n\tv_add_co_ci_u32_e64 v6, s0, s5, v6, s0\n\tglobal_store_b32 v[5:6], v3, off\n\ts_and_not1_b32 exec_lo, exec_lo, s1\n\ts_cbranch_execnz .LBB0_2\n.LBB0_3:\n\ts_nop 0\n\ts_sendmsg sendmsg(MSG_DEALLOC_VGPRS)\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel lessthanorequal_scalar_float\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 304\n\t\t.amdhsa_user_sgpr_count 15\n\t\t.amdhsa_user_sgpr_dispatch_ptr 0\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 0\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 0\n\t\t.amdhsa_next_free_vgpr 9\n\t\t.amdhsa_next_free_sgpr 16\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end0:\n\t.size\tlessthanorequal_scalar_float, .Lfunc_end0-lessthanorequal_scalar_float\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 284\n; NumSgprs: 18\n; NumVgprs: 9\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 2\n; VGPRBlocks: 1\n; NumSGPRsForWavesPerEU: 18\n; NumVGPRsForWavesPerEU: 9\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 15\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .offset: 0\n .size: 4\n .value_kind: by_value\n - .offset: 4\n .size: 4\n .value_kind: by_value\n - .offset: 8\n .size: 4\n .value_kind: by_value\n - .address_space: global\n .offset: 16\n .size: 8\n .value_kind: global_buffer\n - .offset: 24\n .size: 4\n .value_kind: by_value\n - .address_space: global\n .offset: 32\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 40\n .size: 8\n .value_kind: global_buffer\n - .offset: 48\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 52\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 56\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 60\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 62\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 64\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 66\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 68\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 70\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 88\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 96\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 104\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 112\n .size: 2\n .value_kind: hidden_grid_dims\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 304\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: lessthanorequal_scalar_float\n .private_segment_fixed_size: 0\n .sgpr_count: 18\n .sgpr_spill_count: 0\n .symbol: lessthanorequal_scalar_float.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 9\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162577,"cells":{"id":{"kind":"string","value":"c631448dff8c851f685cebbeb34db3e0dffe6787_O2"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z21clothSimulationKernelPfS_fii --------------------------\n .section .text._Z21clothSimulationKernelPfS_fii,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=10\"\n .align 128\n\n\n\n\n .global _Z21clothSimulationKernelPfS_fii\n .type _Z21clothSimulationKernelPfS_fii,@function\n .size _Z21clothSimulationKernelPfS_fii,(.L_x_1 - _Z21clothSimulationKernelPfS_fii)\n .other _Z21clothSimulationKernelPfS_fii,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z21clothSimulationKernelPfS_fii:\n.text._Z21clothSimulationKernelPfS_fii:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ S2R R3, SR_CTAID.Y ;\n /*0020*/ S2R R2, SR_TID.Y ;\n /*0030*/ S2R R0, SR_CTAID.X ;\n /*0040*/ S2R R5, SR_TID.X ;\n /*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ;\n /*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ;\n /*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ;\n /*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x174], P0 ;\n /*0090*/ @P0 EXIT ;\n /*00a0*/ MOV R5, 0x4 ;\n /*00b0*/ IMAD R0, R3, c[0x0][0x174], R0 ;\n /*00c0*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*00d0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ;\n /*00e0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ;\n /*00f0*/ LDG.E R2, [R2.64] ;\n /*0100*/ LDG.E R7, [R4.64] ;\n /*0110*/ FFMA R7, R2, c[0x0][0x170], R7 ;\n /*0120*/ STG.E [R4.64], R7 ;\n /*0130*/ EXIT ;\n.L_x_0:\n /*0140*/ BRA `(.L_x_0);\n /*0150*/ NOP;\n /*0160*/ NOP;\n /*0170*/ NOP;\n /*0180*/ NOP;\n /*0190*/ NOP;\n /*01a0*/ NOP;\n /*01b0*/ NOP;\n /*01c0*/ NOP;\n /*01d0*/ NOP;\n /*01e0*/ NOP;\n /*01f0*/ NOP;\n.L_x_1:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.protected\t_Z21clothSimulationKernelPfS_fii ; -- Begin function _Z21clothSimulationKernelPfS_fii\n\t.globl\t_Z21clothSimulationKernelPfS_fii\n\t.p2align\t8\n\t.type\t_Z21clothSimulationKernelPfS_fii,@function\n_Z21clothSimulationKernelPfS_fii: ; @_Z21clothSimulationKernelPfS_fii\n; %bb.0:\n\ts_clause 0x1\n\ts_load_b32 s2, s[0:1], 0x2c\n\ts_load_b128 s[4:7], s[0:1], 0x10\n\tv_and_b32_e32 v2, 0x3ff, v0\n\tv_bfe_u32 v3, v0, 10, 10\n\ts_waitcnt lgkmcnt(0)\n\ts_lshr_b32 s3, s2, 16\n\ts_and_b32 s2, s2, 0xffff\n\ts_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)\n\tv_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]\n\tv_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_cmp_gt_i32_e32 vcc_lo, s5, v0\n\tv_cmp_gt_i32_e64 s2, s6, v1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b32 s2, vcc_lo, s2\n\ts_and_saveexec_b32 s3, s2\n\ts_cbranch_execz .LBB0_2\n; %bb.1:\n\ts_load_b128 s[0:3], s[0:1], 0x0\n\tv_mad_u64_u32 v[2:3], null, v1, s5, v[0:1]\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_ashrrev_i32_e32 v3, 31, v2\n\tv_lshlrev_b64 v[0:1], 2, v[2:3]\n\ts_waitcnt lgkmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, s2, v0\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo\n\tv_add_co_u32 v0, vcc_lo, s0, v0\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo\n\tglobal_load_b32 v2, v[2:3], off\n\tglobal_load_b32 v3, v[0:1], off\n\ts_waitcnt vmcnt(0)\n\tv_fmac_f32_e32 v3, s4, v2\n\tglobal_store_b32 v[0:1], v3, off\n.LBB0_2:\n\ts_nop 0\n\ts_sendmsg sendmsg(MSG_DEALLOC_VGPRS)\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z21clothSimulationKernelPfS_fii\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 288\n\t\t.amdhsa_user_sgpr_count 14\n\t\t.amdhsa_user_sgpr_dispatch_ptr 0\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 1\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 1\n\t\t.amdhsa_next_free_vgpr 5\n\t\t.amdhsa_next_free_sgpr 16\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end0:\n\t.size\t_Z21clothSimulationKernelPfS_fii, .Lfunc_end0-_Z21clothSimulationKernelPfS_fii\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 212\n; NumSgprs: 18\n; NumVgprs: 5\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 2\n; VGPRBlocks: 0\n; NumSGPRsForWavesPerEU: 18\n; NumVGPRsForWavesPerEU: 5\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 14\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .offset: 16\n .size: 4\n .value_kind: by_value\n - .offset: 20\n .size: 4\n .value_kind: by_value\n - .offset: 24\n .size: 4\n .value_kind: by_value\n - .offset: 32\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 36\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 40\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 44\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 46\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 48\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 50\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 52\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 54\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 72\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 80\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 88\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 96\n .size: 2\n .value_kind: hidden_grid_dims\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 288\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z21clothSimulationKernelPfS_fii\n .private_segment_fixed_size: 0\n .sgpr_count: 18\n .sgpr_spill_count: 0\n .symbol: _Z21clothSimulationKernelPfS_fii.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 5\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162578,"cells":{"id":{"kind":"string","value":"675f2df748f1cccf84a2ac77563f2494c94a7ee5_O0"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z17convolutionRowGPUPfS_S_iii --------------------------\n .section .text._Z17convolutionRowGPUPfS_S_iii,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=28\"\n .align 128\n\n\n\n\n .global _Z17convolutionRowGPUPfS_S_iii\n .type _Z17convolutionRowGPUPfS_S_iii,@function\n .size _Z17convolutionRowGPUPfS_S_iii,(.L_x_5 - _Z17convolutionRowGPUPfS_S_iii)\n .other _Z17convolutionRowGPUPfS_S_iii,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z17convolutionRowGPUPfS_S_iii:\n.text._Z17convolutionRowGPUPfS_S_iii:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ MOV R18, c[0x0][0x118] ;\n /*0020*/ MOV R19, c[0x0][0x11c] ;\n /*0030*/ MOV R2, RZ ;\n /*0040*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0050*/ MOV R10, R2 ;\n /*0060*/ MOV R9, R3 ;\n /*0070*/ MOV R10, R10 ;\n /*0080*/ MOV R9, R9 ;\n /*0090*/ MOV R2, 0x8 ;\n /*00a0*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*00b0*/ MOV R13, R2 ;\n /*00c0*/ MOV R12, R3 ;\n /*00d0*/ MOV R13, R13 ;\n /*00e0*/ MOV R12, R12 ;\n /*00f0*/ MOV R2, 0x10 ;\n /*0100*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0110*/ MOV R7, R2 ;\n /*0120*/ MOV R6, R3 ;\n /*0130*/ MOV R7, R7 ;\n /*0140*/ MOV R6, R6 ;\n /*0150*/ MOV R0, 0x18 ;\n /*0160*/ LDC R0, c[0x0][R0+0x160] ;\n /*0170*/ MOV R0, R0 ;\n /*0180*/ MOV R2, 0x20 ;\n /*0190*/ LDC R2, c[0x0][R2+0x160] ;\n /*01a0*/ MOV R2, R2 ;\n /*01b0*/ MOV R7, R7 ;\n /*01c0*/ MOV R6, R6 ;\n /*01d0*/ MOV R13, R13 ;\n /*01e0*/ MOV R12, R12 ;\n /*01f0*/ S2R R3, SR_CTAID.Y ;\n /*0200*/ MOV R3, R3 ;\n /*0210*/ MOV R4, c[0x0][0x4] ;\n /*0220*/ S2R R5, SR_TID.Y ;\n /*0230*/ MOV R5, R5 ;\n /*0240*/ IMAD R3, R4, R3, R5 ;\n /*0250*/ IADD3 R3, R3, R2, RZ ;\n /*0260*/ S2R R4, SR_CTAID.X ;\n /*0270*/ MOV R4, R4 ;\n /*0280*/ MOV R5, c[0x0][0x0] ;\n /*0290*/ IMAD R4, R5, R4, RZ ;\n /*02a0*/ S2R R15, SR_TID.X ;\n /*02b0*/ MOV R15, R15 ;\n /*02c0*/ IADD3 R11, R4, R15, RZ ;\n /*02d0*/ SHF.L.U32 R16, R2, 0x1, RZ ;\n /*02e0*/ IADD3 R0, R16, R0, RZ ;\n /*02f0*/ IADD3 R17, RZ, -R2, RZ ;\n /*0300*/ MOV R17, R17 ;\n /*0310*/ MOV R17, R17 ;\n /*0320*/ ISETP.GT.AND P0, PT, R17, R2, PT ;\n /*0330*/ MOV R20, RZ ;\n /*0340*/ MOV R10, R10 ;\n /*0350*/ MOV R9, R9 ;\n /*0360*/ MOV R8, R2 ;\n /*0370*/ MOV R7, R7 ;\n /*0380*/ MOV R6, R6 ;\n /*0390*/ MOV R13, R13 ;\n /*03a0*/ MOV R12, R12 ;\n /*03b0*/ MOV R5, R3 ;\n /*03c0*/ MOV R14, R4 ;\n /*03d0*/ MOV R15, R15 ;\n /*03e0*/ MOV R4, R11 ;\n /*03f0*/ MOV R2, R16 ;\n /*0400*/ MOV R0, R0 ;\n /*0410*/ MOV R16, R17 ;\n /*0420*/ MOV R11, R20 ;\n /*0430*/ @P0 BRA `(.L_x_0) ;\n /*0440*/ IMNMX R3, R16, R8, !PT ;\n /*0450*/ IADD3 R3, R3, R8, RZ ;\n /*0460*/ IADD3 R11, R3, 0x1, RZ ;\n /*0470*/ LOP3.LUT R11, R11, 0x3, RZ, 0xc0, !PT ;\n /*0480*/ ISETP.EQ.AND P0, PT, R11, RZ, PT ;\n /*0490*/ MOV R21, RZ ;\n /*04a0*/ MOV R17, R3 ;\n /*04b0*/ MOV R20, R11 ;\n /*04c0*/ MOV R11, R21 ;\n /*04d0*/ @P0 BRA `(.L_x_1) ;\n /*04e0*/ IADD3 R2, RZ, -R2, RZ ;\n /*04f0*/ MOV R2, R2 ;\n /*0500*/ MOV R2, R2 ;\n /*0510*/ IMAD.WIDE R2, R2, 0x4, RZ ;\n /*0520*/ MOV R22, R2 ;\n /*0530*/ MOV R21, R3 ;\n /*0540*/ IADD3 R22, P0, R7, -R22, RZ ;\n /*0550*/ IADD3.X R21, R6, ~R21, RZ, P0, !PT ;\n /*0560*/ IMAD R2, R5, R0, R4 ;\n /*0570*/ IMAD.WIDE R2, R2, 0x4, RZ ;\n /*0580*/ MOV R23, R2 ;\n /*0590*/ MOV R24, R3 ;\n /*05a0*/ IADD3 R23, P0, R13, R23, RZ ;\n /*05b0*/ IADD3.X R24, R12, R24, RZ, P0, !PT ;\n /*05c0*/ MOV R11, RZ ;\n /*05d0*/ MOV R22, R22 ;\n /*05e0*/ MOV R21, R21 ;\n /*05f0*/ MOV R23, R23 ;\n /*0600*/ MOV R24, R24 ;\n /*0610*/ MOV R11, R11 ;\n.L_x_2:\n /*0620*/ MOV R2, R22 ;\n /*0630*/ MOV R3, R21 ;\n /*0640*/ MOV R2, R2 ;\n /*0650*/ MOV R3, R3 ;\n /*0660*/ R2UR UR4, R18 ;\n /*0670*/ R2UR UR5, R19 ;\n /*0680*/ LDG.E R25, [R2.64] ;\n /*0690*/ MOV R2, R23 ;\n /*06a0*/ MOV R3, R24 ;\n /*06b0*/ MOV R2, R2 ;\n /*06c0*/ MOV R3, R3 ;\n /*06d0*/ R2UR UR4, R18 ;\n /*06e0*/ R2UR UR5, R19 ;\n /*06f0*/ LDG.E R2, [R2.64] ;\n /*0700*/ FFMA R2, R2, R25, R11 ;\n /*0710*/ IADD3 R16, R16, 0x1, RZ ;\n /*0720*/ IADD3 R22, P0, R22, -0x4, RZ ;\n /*0730*/ IADD3.X R21, R21, -0x1, RZ, P0, !PT ;\n /*0740*/ IADD3 R23, P0, R23, 0x4, RZ ;\n /*0750*/ IADD3.X R24, R24, RZ, RZ, P0, !PT ;\n /*0760*/ IADD3 R20, R20, -0x1, RZ ;\n /*0770*/ ISETP.NE.AND P0, PT, R20, RZ, PT ;\n /*0780*/ MOV R11, R2 ;\n /*0790*/ MOV R16, R16 ;\n /*07a0*/ MOV R22, R22 ;\n /*07b0*/ MOV R21, R21 ;\n /*07c0*/ MOV R23, R23 ;\n /*07d0*/ MOV R24, R24 ;\n /*07e0*/ MOV R20, R20 ;\n /*07f0*/ @P0 BRA `(.L_x_2) ;\n.L_x_1:\n /*0800*/ ISETP.LT.U32.AND P0, PT, R17, 0x3, PT ;\n /*0810*/ @P0 BRA `(.L_x_0) ;\n /*0820*/ IADD3 R17, R16, -0x1, RZ ;\n /*0830*/ IADD3 R15, R15, R16, RZ ;\n /*0840*/ IADD3 R15, R15, R8, RZ ;\n /*0850*/ IADD3 R14, R15, R14, RZ ;\n /*0860*/ IMAD R14, R5, R0, R14 ;\n /*0870*/ IADD3 R2, R16, -R8, RZ ;\n /*0880*/ IMAD.WIDE R2, R2, 0x4, RZ ;\n /*0890*/ MOV R15, R2 ;\n /*08a0*/ MOV R2, R3 ;\n /*08b0*/ IADD3 R15, P0, -R15, RZ, RZ ;\n /*08c0*/ IADD3.X R2, ~R2, RZ, RZ, P0, !PT ;\n /*08d0*/ MOV R15, R15 ;\n /*08e0*/ MOV R20, R2 ;\n /*08f0*/ IMAD.WIDE R2, R14, 0x4, RZ ;\n /*0900*/ MOV R14, R2 ;\n /*0910*/ MOV R2, R3 ;\n /*0920*/ IADD3 R13, P0, R13, R14, RZ ;\n /*0930*/ IADD3.X R2, R12, R2, RZ, P0, !PT ;\n /*0940*/ MOV R16, R17 ;\n /*0950*/ MOV R14, R15 ;\n /*0960*/ MOV R15, R20 ;\n /*0970*/ MOV R12, R13 ;\n /*0980*/ MOV R13, R2 ;\n.L_x_3:\n /*0990*/ IADD3 R17, P0, R7, R14, RZ ;\n /*09a0*/ IADD3.X R20, R6, R15, RZ, P0, !PT ;\n /*09b0*/ MOV R2, R17 ;\n /*09c0*/ MOV R3, R20 ;\n /*09d0*/ MOV R2, R2 ;\n /*09e0*/ MOV R3, R3 ;\n /*09f0*/ R2UR UR4, R18 ;\n /*0a00*/ R2UR UR5, R19 ;\n /*0a10*/ LDG.E R21, [R2.64] ;\n /*0a20*/ MOV R2, R12 ;\n /*0a30*/ MOV R3, R13 ;\n /*0a40*/ MOV R2, R2 ;\n /*0a50*/ MOV R3, R3 ;\n /*0a60*/ R2UR UR4, R18 ;\n /*0a70*/ R2UR UR5, R19 ;\n /*0a80*/ LDG.E R2, [R2.64] ;\n /*0a90*/ FFMA R21, R2, R21, R11 ;\n /*0aa0*/ IADD3 R2, P0, R17, -0x4, RZ ;\n /*0ab0*/ IADD3.X R3, R20, -0x1, RZ, P0, !PT ;\n /*0ac0*/ MOV R2, R2 ;\n /*0ad0*/ MOV R3, R3 ;\n /*0ae0*/ MOV R2, R2 ;\n /*0af0*/ MOV R3, R3 ;\n /*0b00*/ R2UR UR4, R18 ;\n /*0b10*/ R2UR UR5, R19 ;\n /*0b20*/ LDG.E R11, [R2.64] ;\n /*0b30*/ IADD3 R2, P0, R12, 0x4, RZ ;\n /*0b40*/ IADD3.X R3, R13, RZ, RZ, P0, !PT ;\n /*0b50*/ MOV R2, R2 ;\n /*0b60*/ MOV R3, R3 ;\n /*0b70*/ MOV R2, R2 ;\n /*0b80*/ MOV R3, R3 ;\n /*0b90*/ R2UR UR4, R18 ;\n /*0ba0*/ R2UR UR5, R19 ;\n /*0bb0*/ LDG.E R2, [R2.64] ;\n /*0bc0*/ FFMA R11, R2, R11, R21 ;\n /*0bd0*/ IADD3 R2, P0, R17, -0x8, RZ ;\n /*0be0*/ IADD3.X R3, R20, -0x1, RZ, P0, !PT ;\n /*0bf0*/ MOV R2, R2 ;\n /*0c00*/ MOV R3, R3 ;\n /*0c10*/ MOV R2, R2 ;\n /*0c20*/ MOV R3, R3 ;\n /*0c30*/ R2UR UR4, R18 ;\n /*0c40*/ R2UR UR5, R19 ;\n /*0c50*/ LDG.E R21, [R2.64] ;\n /*0c60*/ IADD3 R2, P0, R12, 0x8, RZ ;\n /*0c70*/ IADD3.X R3, R13, RZ, RZ, P0, !PT ;\n /*0c80*/ MOV R2, R2 ;\n /*0c90*/ MOV R3, R3 ;\n /*0ca0*/ MOV R2, R2 ;\n /*0cb0*/ MOV R3, R3 ;\n /*0cc0*/ R2UR UR4, R18 ;\n /*0cd0*/ R2UR UR5, R19 ;\n /*0ce0*/ LDG.E R2, [R2.64] ;\n /*0cf0*/ FFMA R11, R2, R21, R11 ;\n /*0d00*/ IADD3 R2, P0, R17, -0xc, RZ ;\n /*0d10*/ IADD3.X R3, R20, -0x1, RZ, P0, !PT ;\n /*0d20*/ MOV R2, R2 ;\n /*0d30*/ MOV R3, R3 ;\n /*0d40*/ MOV R2, R2 ;\n /*0d50*/ MOV R3, R3 ;\n /*0d60*/ R2UR UR4, R18 ;\n /*0d70*/ R2UR UR5, R19 ;\n /*0d80*/ LDG.E R17, [R2.64] ;\n /*0d90*/ IADD3 R2, P0, R12, 0xc, RZ ;\n /*0da0*/ IADD3.X R3, R13, RZ, RZ, P0, !PT ;\n /*0db0*/ MOV R2, R2 ;\n /*0dc0*/ MOV R3, R3 ;\n /*0dd0*/ MOV R2, R2 ;\n /*0de0*/ MOV R3, R3 ;\n /*0df0*/ R2UR UR4, R18 ;\n /*0e00*/ R2UR UR5, R19 ;\n /*0e10*/ LDG.E R2, [R2.64] ;\n /*0e20*/ FFMA R11, R2, R17, R11 ;\n /*0e30*/ IADD3 R7, P0, R7, -0x10, RZ ;\n /*0e40*/ IADD3.X R6, R6, -0x1, RZ, P0, !PT ;\n /*0e50*/ IADD3 R12, P0, R12, 0x10, RZ ;\n /*0e60*/ IADD3.X R13, R13, RZ, RZ, P0, !PT ;\n /*0e70*/ IADD3 R16, R16, 0x4, RZ ;\n /*0e80*/ ISETP.LT.AND P0, PT, R16, R8, PT ;\n /*0e90*/ MOV R11, R11 ;\n /*0ea0*/ MOV R7, R7 ;\n /*0eb0*/ MOV R6, R6 ;\n /*0ec0*/ MOV R12, R12 ;\n /*0ed0*/ MOV R13, R13 ;\n /*0ee0*/ MOV R16, R16 ;\n /*0ef0*/ @P0 BRA `(.L_x_3) ;\n.L_x_0:\n /*0f00*/ IADD3 R4, R4, R8, RZ ;\n /*0f10*/ IMAD R2, R0, R5, R4 ;\n /*0f20*/ MOV R10, R10 ;\n /*0f30*/ MOV R9, R9 ;\n /*0f40*/ IMAD.WIDE R2, R2, 0x4, RZ ;\n /*0f50*/ MOV R0, R2 ;\n /*0f60*/ MOV R3, R3 ;\n /*0f70*/ IADD3 R2, P0, R10, R0, RZ ;\n /*0f80*/ IADD3.X R3, R9, R3, RZ, P0, !PT ;\n /*0f90*/ MOV R2, R2 ;\n /*0fa0*/ MOV R3, R3 ;\n /*0fb0*/ MOV R2, R2 ;\n /*0fc0*/ MOV R3, R3 ;\n /*0fd0*/ R2UR UR4, R18 ;\n /*0fe0*/ R2UR UR5, R19 ;\n /*0ff0*/ STG.E [R2.64], R11 ;\n /*1000*/ EXIT ;\n.L_x_4:\n /*1010*/ BRA `(.L_x_4);\n /*1020*/ NOP;\n /*1030*/ NOP;\n /*1040*/ NOP;\n /*1050*/ NOP;\n /*1060*/ NOP;\n /*1070*/ NOP;\n /*1080*/ NOP;\n /*1090*/ NOP;\n /*10a0*/ NOP;\n /*10b0*/ NOP;\n /*10c0*/ NOP;\n /*10d0*/ NOP;\n /*10e0*/ NOP;\n /*10f0*/ NOP;\n.L_x_5:\n"},"hip":{"kind":"string","value":"\t.text\n\t.file\t\"convolutionRowGPU.hip\"\n\t.globl\t_Z32__device_stub__convolutionRowGPUPfS_S_iii # -- Begin function _Z32__device_stub__convolutionRowGPUPfS_S_iii\n\t.p2align\t4, 0x90\n\t.type\t_Z32__device_stub__convolutionRowGPUPfS_S_iii,@function\n_Z32__device_stub__convolutionRowGPUPfS_S_iii: # @_Z32__device_stub__convolutionRowGPUPfS_S_iii\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$152, %rsp\n\t.cfi_def_cfa_offset 160\n\tmovq\t%rdi, 88(%rsp)\n\tmovq\t%rsi, 80(%rsp)\n\tmovq\t%rdx, 72(%rsp)\n\tmovl\t%ecx, 20(%rsp)\n\tmovl\t%r8d, 16(%rsp)\n\tmovl\t%r9d, 12(%rsp)\n\tleaq\t88(%rsp), %rax\n\tmovq\t%rax, 96(%rsp)\n\tleaq\t80(%rsp), %rax\n\tmovq\t%rax, 104(%rsp)\n\tleaq\t72(%rsp), %rax\n\tmovq\t%rax, 112(%rsp)\n\tleaq\t20(%rsp), %rax\n\tmovq\t%rax, 120(%rsp)\n\tleaq\t16(%rsp), %rax\n\tmovq\t%rax, 128(%rsp)\n\tleaq\t12(%rsp), %rax\n\tmovq\t%rax, 136(%rsp)\n\tleaq\t56(%rsp), %rdi\n\tleaq\t40(%rsp), %rsi\n\tleaq\t32(%rsp), %rdx\n\tleaq\t24(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t56(%rsp), %rsi\n\tmovl\t64(%rsp), %edx\n\tmovq\t40(%rsp), %rcx\n\tmovl\t48(%rsp), %r8d\n\tleaq\t96(%rsp), %r9\n\tmovl\t$_Z17convolutionRowGPUPfS_S_iii, %edi\n\tpushq\t24(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t40(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$168, %rsp\n\t.cfi_adjust_cfa_offset -168\n\tretq\n.Lfunc_end0:\n\t.size\t_Z32__device_stub__convolutionRowGPUPfS_S_iii, .Lfunc_end0-_Z32__device_stub__convolutionRowGPUPfS_S_iii\n\t.cfi_endproc\n # -- End function\n\t.p2align\t4, 0x90 # -- Begin function __hip_module_ctor\n\t.type\t__hip_module_ctor,@function\n__hip_module_ctor: # @__hip_module_ctor\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$40, %rsp\n\t.cfi_def_cfa_offset 48\n\tmovq\t__hip_gpubin_handle(%rip), %rdi\n\ttestq\t%rdi, %rdi\n\tjne\t.LBB1_2\n# %bb.1:\n\tmovl\t$__hip_fatbin_wrapper, %edi\n\tcallq\t__hipRegisterFatBinary\n\tmovq\t%rax, %rdi\n\tmovq\t%rax, __hip_gpubin_handle(%rip)\n.LBB1_2:\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, 16(%rsp)\n\tmovups\t%xmm0, (%rsp)\n\tmovl\t$_Z17convolutionRowGPUPfS_S_iii, %esi\n\tmovl\t$.L__unnamed_1, %edx\n\tmovl\t$.L__unnamed_1, %ecx\n\tmovl\t$-1, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipRegisterFunction\n\tmovl\t$__hip_module_dtor, %edi\n\taddq\t$40, %rsp\n\t.cfi_def_cfa_offset 8\n\tjmp\tatexit # TAILCALL\n.Lfunc_end1:\n\t.size\t__hip_module_ctor, .Lfunc_end1-__hip_module_ctor\n\t.cfi_endproc\n # -- End function\n\t.p2align\t4, 0x90 # -- Begin function __hip_module_dtor\n\t.type\t__hip_module_dtor,@function\n__hip_module_dtor: # @__hip_module_dtor\n\t.cfi_startproc\n# %bb.0:\n\tmovq\t__hip_gpubin_handle(%rip), %rdi\n\ttestq\t%rdi, %rdi\n\tje\t.LBB2_2\n# %bb.1:\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 16\n\tcallq\t__hipUnregisterFatBinary\n\tmovq\t$0, __hip_gpubin_handle(%rip)\n\taddq\t$8, %rsp\n\t.cfi_def_cfa_offset 8\n.LBB2_2:\n\tretq\n.Lfunc_end2:\n\t.size\t__hip_module_dtor, .Lfunc_end2-__hip_module_dtor\n\t.cfi_endproc\n # -- End function\n\t.type\t_Z17convolutionRowGPUPfS_S_iii,@object # @_Z17convolutionRowGPUPfS_S_iii\n\t.section\t.rodata,\"a\",@progbits\n\t.globl\t_Z17convolutionRowGPUPfS_S_iii\n\t.p2align\t3, 0x0\n_Z17convolutionRowGPUPfS_S_iii:\n\t.quad\t_Z32__device_stub__convolutionRowGPUPfS_S_iii\n\t.size\t_Z17convolutionRowGPUPfS_S_iii, 8\n\n\t.type\t.L__unnamed_1,@object # @0\n\t.section\t.rodata.str1.1,\"aMS\",@progbits,1\n.L__unnamed_1:\n\t.asciz\t\"_Z17convolutionRowGPUPfS_S_iii\"\n\t.size\t.L__unnamed_1, 31\n\n\t.type\t__hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper\n\t.section\t.hipFatBinSegment,\"a\",@progbits\n\t.p2align\t3, 0x0\n__hip_fatbin_wrapper:\n\t.long\t1212764230 # 0x48495046\n\t.long\t1 # 0x1\n\t.quad\t__hip_fatbin\n\t.quad\t0\n\t.size\t__hip_fatbin_wrapper, 24\n\n\t.type\t__hip_gpubin_handle,@object # @__hip_gpubin_handle\n\t.local\t__hip_gpubin_handle\n\t.comm\t__hip_gpubin_handle,8,8\n\t.section\t.init_array,\"aw\",@init_array\n\t.p2align\t3, 0x0\n\t.quad\t__hip_module_ctor\n\t.type\t__hip_cuid_,@object # @__hip_cuid_\n\t.bss\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 # 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n"}}},{"rowIdx":162579,"cells":{"id":{"kind":"string","value":"e06f8d2a35fdcef7a315b3eb9396f5845cfe0c47_O0"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_ --------------------------\n .section .text._ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=15\"\n .align 128\n\n\n\n\n .global _ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_\n .type _ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_,@function\n .size _ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_,(.L_x_85 - _ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_)\n .other _ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_:\n.text._ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ MOV R4, c[0x0][0x118] ;\n /*0020*/ MOV R5, c[0x0][0x11c] ;\n /*0030*/ MOV R2, RZ ;\n /*0040*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0050*/ MOV R7, R2 ;\n /*0060*/ MOV R8, R3 ;\n /*0070*/ MOV R7, R7 ;\n /*0080*/ MOV R8, R8 ;\n /*0090*/ MOV R0, 0x8 ;\n /*00a0*/ IADD3 R0, R0, 0x8, RZ ;\n /*00b0*/ MOV R0, R0 ;\n /*00c0*/ LDC R0, c[0x0][R0+0x160] ;\n /*00d0*/ MOV R0, R0 ;\n /*00e0*/ MOV R2, 0x8 ;\n /*00f0*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0100*/ MOV R6, R2 ;\n /*0110*/ MOV R11, R3 ;\n /*0120*/ MOV R6, R6 ;\n /*0130*/ MOV R11, R11 ;\n /*0140*/ S2R R2, SR_CTAID.X ;\n /*0150*/ MOV R2, R2 ;\n /*0160*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ;\n /*0170*/ MOV R9, R2 ;\n /*0180*/ MOV R10, R3 ;\n /*0190*/ IADD3 R7, P0, R7, -R9, RZ ;\n /*01a0*/ IADD3.X R8, R8, ~R10, RZ, P0, !PT ;\n /*01b0*/ ISETP.GT.U32.AND P0, PT, R7, 0x1ff, PT ;\n /*01c0*/ ISETP.GT.U32.AND.EX P0, PT, R8, RZ, PT, P0 ;\n /*01d0*/ MOV R3, R6 ;\n /*01e0*/ MOV R6, R11 ;\n /*01f0*/ S2R R2, SR_TID.X ;\n /*0200*/ MOV R2, R2 ;\n /*0210*/ MOV R2, R2 ;\n /*0220*/ MOV R11, R2 ;\n /*0230*/ MOV R12, RZ ;\n /*0240*/ IADD3 R9, P1, R9, R11, RZ ;\n /*0250*/ IADD3.X R10, R10, R12, RZ, P1, !PT ;\n /*0260*/ SHF.L.U64.HI R10, R9, 0x2, R10 ;\n /*0270*/ SHF.L.U32 R9, R9, 0x2, RZ ;\n /*0280*/ IADD3 R9, P1, R3, R9, RZ ;\n /*0290*/ IADD3.X R10, R6, R10, RZ, P1, !PT ;\n /*02a0*/ MOV R0, R0 ;\n /*02b0*/ MOV R3, R7 ;\n /*02c0*/ MOV R6, R8 ;\n /*02d0*/ MOV R6, R2 ;\n /*02e0*/ MOV R11, R11 ;\n /*02f0*/ MOV R12, R12 ;\n /*0300*/ MOV R9, R9 ;\n /*0310*/ MOV R10, R10 ;\n /*0320*/ @P0 BRA `(.L_x_0) ;\n /*0330*/ BRA `(.L_x_1) ;\n.L_x_0:\n /*0340*/ MOV R2, R9 ;\n /*0350*/ MOV R3, R10 ;\n /*0360*/ MOV R2, R2 ;\n /*0370*/ MOV R3, R3 ;\n /*0380*/ R2UR UR4, R4 ;\n /*0390*/ R2UR UR5, R5 ;\n /*03a0*/ STG.E [R2.64], R0 ;\n /*03b0*/ IADD3 R2, P0, R9, 0x400, RZ ;\n /*03c0*/ IADD3.X R3, R10, RZ, RZ, P0, !PT ;\n /*03d0*/ MOV R2, R2 ;\n /*03e0*/ MOV R3, R3 ;\n /*03f0*/ MOV R2, R2 ;\n /*0400*/ MOV R3, R3 ;\n /*0410*/ R2UR UR4, R4 ;\n /*0420*/ R2UR UR5, R5 ;\n /*0430*/ STG.E [R2.64], R0 ;\n /*0440*/ BRA `(.L_x_2) ;\n.L_x_1:\n /*0450*/ MOV R2, R3 ;\n /*0460*/ MOV R2, R2 ;\n /*0470*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ;\n /*0480*/ MOV R2, R2 ;\n /*0490*/ MOV R3, R3 ;\n /*04a0*/ MOV R7, R2 ;\n /*04b0*/ MOV R8, R3 ;\n /*04c0*/ MOV R7, R7 ;\n /*04d0*/ MOV R8, R8 ;\n /*04e0*/ ISETP.LE.U32.AND P0, PT, R7, R11, PT ;\n /*04f0*/ ISETP.LE.U32.AND.EX P0, PT, R8, R12, PT, P0 ;\n /*0500*/ MOV R7, R7 ;\n /*0510*/ MOV R8, R8 ;\n /*0520*/ BSSY B0, `(.L_x_3) ;\n /*0530*/ @P0 BRA `(.L_x_4) ;\n /*0540*/ MOV R2, R9 ;\n /*0550*/ MOV R3, R10 ;\n /*0560*/ MOV R2, R2 ;\n /*0570*/ MOV R3, R3 ;\n /*0580*/ R2UR UR4, R4 ;\n /*0590*/ R2UR UR5, R5 ;\n /*05a0*/ STG.E [R2.64], R0 ;\n.L_x_4:\n /*05b0*/ BSYNC B0 ;\n.L_x_3:\n /*05c0*/ IADD3 R6, R6, 0x100, RZ ;\n /*05d0*/ MOV R6, R6 ;\n /*05e0*/ MOV R6, R6 ;\n /*05f0*/ MOV R2, RZ ;\n /*0600*/ ISETP.LE.U32.AND P0, PT, R7, R6, PT ;\n /*0610*/ ISETP.LE.U32.AND.EX P0, PT, R8, R2, PT, P0 ;\n /*0620*/ @P0 BRA `(.L_x_2) ;\n /*0630*/ IADD3 R2, P0, R9, 0x400, RZ ;\n /*0640*/ IADD3.X R3, R10, RZ, RZ, P0, !PT ;\n /*0650*/ MOV R2, R2 ;\n /*0660*/ MOV R3, R3 ;\n /*0670*/ MOV R2, R2 ;\n /*0680*/ MOV R3, R3 ;\n /*0690*/ R2UR UR4, R4 ;\n /*06a0*/ R2UR UR5, R5 ;\n /*06b0*/ STG.E [R2.64], R0 ;\n /*06c0*/ BRA `(.L_x_2) ;\n.L_x_2:\n /*06d0*/ EXIT ;\n.L_x_5:\n /*06e0*/ BRA `(.L_x_5);\n /*06f0*/ NOP;\n /*0700*/ NOP;\n /*0710*/ NOP;\n /*0720*/ NOP;\n /*0730*/ NOP;\n /*0740*/ NOP;\n /*0750*/ NOP;\n /*0760*/ NOP;\n /*0770*/ NOP;\n.L_x_85:\n\n\n//--------------------- .text._ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_ --------------------------\n .section .text._ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=15\"\n .align 128\n\n\n\n\n .global _ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_\n .type _ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_,@function\n .size _ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_,(.L_x_86 - _ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_)\n .other _ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_:\n.text._ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ MOV R4, c[0x0][0x118] ;\n /*0020*/ MOV R5, c[0x0][0x11c] ;\n /*0030*/ MOV R2, RZ ;\n /*0040*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0050*/ MOV R7, R2 ;\n /*0060*/ MOV R8, R3 ;\n /*0070*/ MOV R7, R7 ;\n /*0080*/ MOV R8, R8 ;\n /*0090*/ MOV R0, 0x8 ;\n /*00a0*/ IADD3 R0, R0, 0x8, RZ ;\n /*00b0*/ MOV R0, R0 ;\n /*00c0*/ LDC R0, c[0x0][R0+0x160] ;\n /*00d0*/ MOV R0, R0 ;\n /*00e0*/ MOV R2, 0x8 ;\n /*00f0*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0100*/ MOV R6, R2 ;\n /*0110*/ MOV R11, R3 ;\n /*0120*/ MOV R6, R6 ;\n /*0130*/ MOV R11, R11 ;\n /*0140*/ S2R R2, SR_CTAID.X ;\n /*0150*/ MOV R2, R2 ;\n /*0160*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ;\n /*0170*/ MOV R9, R2 ;\n /*0180*/ MOV R10, R3 ;\n /*0190*/ IADD3 R7, P0, R7, -R9, RZ ;\n /*01a0*/ IADD3.X R8, R8, ~R10, RZ, P0, !PT ;\n /*01b0*/ ISETP.GT.U32.AND P0, PT, R7, 0x1ff, PT ;\n /*01c0*/ ISETP.GT.U32.AND.EX P0, PT, R8, RZ, PT, P0 ;\n /*01d0*/ MOV R3, R6 ;\n /*01e0*/ MOV R6, R11 ;\n /*01f0*/ S2R R2, SR_TID.X ;\n /*0200*/ MOV R2, R2 ;\n /*0210*/ MOV R2, R2 ;\n /*0220*/ MOV R11, R2 ;\n /*0230*/ MOV R12, RZ ;\n /*0240*/ IADD3 R9, P1, R9, R11, RZ ;\n /*0250*/ IADD3.X R10, R10, R12, RZ, P1, !PT ;\n /*0260*/ SHF.L.U64.HI R10, R9, 0x2, R10 ;\n /*0270*/ SHF.L.U32 R9, R9, 0x2, RZ ;\n /*0280*/ IADD3 R9, P1, R3, R9, RZ ;\n /*0290*/ IADD3.X R10, R6, R10, RZ, P1, !PT ;\n /*02a0*/ MOV R0, R0 ;\n /*02b0*/ MOV R3, R7 ;\n /*02c0*/ MOV R6, R8 ;\n /*02d0*/ MOV R6, R2 ;\n /*02e0*/ MOV R11, R11 ;\n /*02f0*/ MOV R12, R12 ;\n /*0300*/ MOV R9, R9 ;\n /*0310*/ MOV R10, R10 ;\n /*0320*/ @P0 BRA `(.L_x_6) ;\n /*0330*/ BRA `(.L_x_7) ;\n.L_x_6:\n /*0340*/ MOV R2, R9 ;\n /*0350*/ MOV R3, R10 ;\n /*0360*/ MOV R2, R2 ;\n /*0370*/ MOV R3, R3 ;\n /*0380*/ R2UR UR4, R4 ;\n /*0390*/ R2UR UR5, R5 ;\n /*03a0*/ STG.E [R2.64], R0 ;\n /*03b0*/ IADD3 R2, P0, R9, 0x400, RZ ;\n /*03c0*/ IADD3.X R3, R10, RZ, RZ, P0, !PT ;\n /*03d0*/ MOV R2, R2 ;\n /*03e0*/ MOV R3, R3 ;\n /*03f0*/ MOV R2, R2 ;\n /*0400*/ MOV R3, R3 ;\n /*0410*/ R2UR UR4, R4 ;\n /*0420*/ R2UR UR5, R5 ;\n /*0430*/ STG.E [R2.64], R0 ;\n /*0440*/ BRA `(.L_x_8) ;\n.L_x_7:\n /*0450*/ MOV R2, R3 ;\n /*0460*/ MOV R2, R2 ;\n /*0470*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ;\n /*0480*/ MOV R2, R2 ;\n /*0490*/ MOV R3, R3 ;\n /*04a0*/ MOV R7, R2 ;\n /*04b0*/ MOV R8, R3 ;\n /*04c0*/ MOV R7, R7 ;\n /*04d0*/ MOV R8, R8 ;\n /*04e0*/ ISETP.LE.U32.AND P0, PT, R7, R11, PT ;\n /*04f0*/ ISETP.LE.U32.AND.EX P0, PT, R8, R12, PT, P0 ;\n /*0500*/ MOV R7, R7 ;\n /*0510*/ MOV R8, R8 ;\n /*0520*/ BSSY B0, `(.L_x_9) ;\n /*0530*/ @P0 BRA `(.L_x_10) ;\n /*0540*/ MOV R2, R9 ;\n /*0550*/ MOV R3, R10 ;\n /*0560*/ MOV R2, R2 ;\n /*0570*/ MOV R3, R3 ;\n /*0580*/ R2UR UR4, R4 ;\n /*0590*/ R2UR UR5, R5 ;\n /*05a0*/ STG.E [R2.64], R0 ;\n.L_x_10:\n /*05b0*/ BSYNC B0 ;\n.L_x_9:\n /*05c0*/ IADD3 R6, R6, 0x100, RZ ;\n /*05d0*/ MOV R6, R6 ;\n /*05e0*/ MOV R6, R6 ;\n /*05f0*/ MOV R2, RZ ;\n /*0600*/ ISETP.LE.U32.AND P0, PT, R7, R6, PT ;\n /*0610*/ ISETP.LE.U32.AND.EX P0, PT, R8, R2, PT, P0 ;\n /*0620*/ @P0 BRA `(.L_x_8) ;\n /*0630*/ IADD3 R2, P0, R9, 0x400, RZ ;\n /*0640*/ IADD3.X R3, R10, RZ, RZ, P0, !PT ;\n /*0650*/ MOV R2, R2 ;\n /*0660*/ MOV R3, R3 ;\n /*0670*/ MOV R2, R2 ;\n /*0680*/ MOV R3, R3 ;\n /*0690*/ R2UR UR4, R4 ;\n /*06a0*/ R2UR UR5, R5 ;\n /*06b0*/ STG.E [R2.64], R0 ;\n /*06c0*/ BRA `(.L_x_8) ;\n.L_x_8:\n /*06d0*/ EXIT ;\n.L_x_11:\n /*06e0*/ BRA `(.L_x_11);\n /*06f0*/ NOP;\n /*0700*/ NOP;\n /*0710*/ NOP;\n /*0720*/ NOP;\n /*0730*/ NOP;\n /*0740*/ NOP;\n /*0750*/ NOP;\n /*0760*/ NOP;\n /*0770*/ NOP;\n.L_x_86:\n\n\n//--------------------- .text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv --------------------------\n .section .text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=4\"\n .align 128\n\n\n\n\n .global _ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv\n .type _ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv,@function\n .size _ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv,(.L_x_87 - _ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv)\n .other _ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv:\n.text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ EXIT ;\n.L_x_12:\n /*0020*/ BRA `(.L_x_12);\n /*0030*/ NOP;\n /*0040*/ NOP;\n /*0050*/ NOP;\n /*0060*/ NOP;\n /*0070*/ NOP;\n /*0080*/ NOP;\n /*0090*/ NOP;\n /*00a0*/ NOP;\n /*00b0*/ NOP;\n /*00c0*/ NOP;\n /*00d0*/ NOP;\n /*00e0*/ NOP;\n /*00f0*/ NOP;\n.L_x_87:\n\n\n//--------------------- .text._Z25sparse_convolution_kernelPKiPKfiS2_Pfi --------------------------\n .section .text._Z25sparse_convolution_kernelPKiPKfiS2_Pfi,\"ax\",@progbits\n .sectionflags @\"SHF_BARRIERS=1\"\n .sectioninfo @\"SHI_REGISTERS=21\"\n .align 128\n\n\n\n\n .global _Z25sparse_convolution_kernelPKiPKfiS2_Pfi\n .type _Z25sparse_convolution_kernelPKiPKfiS2_Pfi,@function\n .size _Z25sparse_convolution_kernelPKiPKfiS2_Pfi,(.L_x_88 - _Z25sparse_convolution_kernelPKiPKfiS2_Pfi)\n .other _Z25sparse_convolution_kernelPKiPKfiS2_Pfi,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z25sparse_convolution_kernelPKiPKfiS2_Pfi:\n.text._Z25sparse_convolution_kernelPKiPKfiS2_Pfi:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ MOV R12, c[0x0][0x118] ;\n /*0020*/ MOV R13, c[0x0][0x11c] ;\n /*0030*/ MOV R2, RZ ;\n /*0040*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0050*/ MOV R7, R2 ;\n /*0060*/ MOV R6, R3 ;\n /*0070*/ MOV R7, R7 ;\n /*0080*/ MOV R6, R6 ;\n /*0090*/ MOV R2, 0x8 ;\n /*00a0*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*00b0*/ MOV R5, R2 ;\n /*00c0*/ MOV R8, R3 ;\n /*00d0*/ MOV R5, R5 ;\n /*00e0*/ MOV R8, R8 ;\n /*00f0*/ MOV R0, 0x10 ;\n /*0100*/ LDC R0, c[0x0][R0+0x160] ;\n /*0110*/ MOV R0, R0 ;\n /*0120*/ MOV R2, 0x18 ;\n /*0130*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0140*/ MOV R17, R2 ;\n /*0150*/ MOV R18, R3 ;\n /*0160*/ MOV R17, R17 ;\n /*0170*/ MOV R18, R18 ;\n /*0180*/ MOV R2, 0x20 ;\n /*0190*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*01a0*/ MOV R4, R2 ;\n /*01b0*/ MOV R10, R3 ;\n /*01c0*/ MOV R3, R4 ;\n /*01d0*/ MOV R10, R10 ;\n /*01e0*/ MOV R2, 0x28 ;\n /*01f0*/ LDC R2, c[0x0][R2+0x160] ;\n /*0200*/ MOV R2, R2 ;\n /*0210*/ MOV R3, R3 ;\n /*0220*/ MOV R10, R10 ;\n /*0230*/ S2R R9, SR_TID.X ;\n /*0240*/ MOV R9, R9 ;\n /*0250*/ ISETP.GE.AND P0, PT, R9, R2, PT ;\n /*0260*/ MOV R7, R7 ;\n /*0270*/ MOV R6, R6 ;\n /*0280*/ MOV R5, R5 ;\n /*0290*/ MOV R4, R8 ;\n /*02a0*/ MOV R8, R0 ;\n /*02b0*/ MOV R17, R17 ;\n /*02c0*/ MOV R18, R18 ;\n /*02d0*/ MOV R0, R2 ;\n /*02e0*/ MOV R2, R3 ;\n /*02f0*/ MOV R3, R10 ;\n /*0300*/ MOV R9, R9 ;\n /*0310*/ @P0 BRA `(.L_x_13) ;\n /*0320*/ MOV R10, c[0x0][0x0] ;\n /*0330*/ MOV R17, R17 ;\n /*0340*/ MOV R18, R18 ;\n /*0350*/ MOV R9, R9 ;\n /*0360*/ MOV R14, R10 ;\n /*0370*/ MOV R17, R17 ;\n /*0380*/ MOV R18, R18 ;\n /*0390*/ MOV R15, R9 ;\n.L_x_14:\n /*03a0*/ IMAD.WIDE R10, R15, 0x4, RZ ;\n /*03b0*/ MOV R16, R10 ;\n /*03c0*/ MOV R11, R11 ;\n /*03d0*/ IADD3 R10, P0, R17, R16, RZ ;\n /*03e0*/ IADD3.X R11, R18, R11, RZ, P0, !PT ;\n /*03f0*/ MOV R10, R10 ;\n /*0400*/ MOV R11, R11 ;\n /*0410*/ MOV R10, R10 ;\n /*0420*/ MOV R11, R11 ;\n /*0430*/ R2UR UR4, R12 ;\n /*0440*/ R2UR UR5, R13 ;\n /*0450*/ LDG.E R10, [R10.64] ;\n /*0460*/ SHF.L.U32 R11, R15, 0x2, RZ ;\n /*0470*/ MOV R16, RZ ;\n /*0480*/ IADD3 R11, R16, R11, RZ ;\n /*0490*/ MOV R11, R11 ;\n /*04a0*/ STS [R11], R10 ;\n /*04b0*/ IADD3 R15, R15, R14, RZ ;\n /*04c0*/ ISETP.LT.AND P0, PT, R15, R0, PT ;\n /*04d0*/ MOV R15, R15 ;\n /*04e0*/ @P0 BRA `(.L_x_14) ;\n.L_x_13:\n /*04f0*/ WARPSYNC 0xffffffff ;\n /*0500*/ BAR.SYNC.DEFER_BLOCKING 0x0 ;\n /*0510*/ ISETP.GE.AND P0, PT, R9, R8, PT ;\n /*0520*/ @P0 BRA `(.L_x_15) ;\n /*0530*/ MOV R8, R7 ;\n /*0540*/ MOV R11, R6 ;\n /*0550*/ IMAD.WIDE R6, R9, 0x4, RZ ;\n /*0560*/ MOV R9, R6 ;\n /*0570*/ MOV R10, R7 ;\n /*0580*/ IADD3 R7, P0, R8, R9, RZ ;\n /*0590*/ IADD3.X R8, R11, R10, RZ, P0, !PT ;\n /*05a0*/ MOV R5, R5 ;\n /*05b0*/ MOV R6, R4 ;\n /*05c0*/ IADD3 R4, P0, R5, R9, RZ ;\n /*05d0*/ IADD3.X R5, R6, R10, RZ, P0, !PT ;\n /*05e0*/ MOV R4, R4 ;\n /*05f0*/ MOV R5, R5 ;\n /*0600*/ MOV R4, R4 ;\n /*0610*/ MOV R5, R5 ;\n /*0620*/ R2UR UR4, R12 ;\n /*0630*/ R2UR UR5, R13 ;\n /*0640*/ LDG.E R6, [R4.64] ;\n /*0650*/ MOV R4, R7 ;\n /*0660*/ MOV R5, R8 ;\n /*0670*/ MOV R4, R4 ;\n /*0680*/ MOV R5, R5 ;\n /*0690*/ R2UR UR4, R12 ;\n /*06a0*/ R2UR UR5, R13 ;\n /*06b0*/ LDG.E R5, [R4.64] ;\n /*06c0*/ MOV R7, R5 ;\n /*06d0*/ MOV R0, R0 ;\n /*06e0*/ MOV R4, R6 ;\n /*06f0*/ MOV R5, R5 ;\n /*0700*/ MOV R7, R7 ;\n /*0710*/ MOV R6, R0 ;\n /*0720*/ MOV R7, R7 ;\n /*0730*/ MOV R6, R6 ;\n /*0740*/ MOV R7, R7 ;\n /*0750*/ MOV R6, R6 ;\n /*0760*/ IABS R8, R6 ;\n /*0770*/ MOV R8, R8 ;\n /*0780*/ MOV R8, R8 ;\n /*0790*/ I2F.U32.RP R9, R8 ;\n /*07a0*/ MUFU.RCP R9, R9 ;\n /*07b0*/ MOV R9, R9 ;\n /*07c0*/ IADD3 R9, R9, 0xffffffe, RZ ;\n /*07d0*/ MOV R9, R9 ;\n /*07e0*/ F2I.FTZ.U32.TRUNC.NTZ R9, R9 ;\n /*07f0*/ IMAD.U32 R10, R8, R9, RZ ;\n /*0800*/ IADD3 R10, RZ, -R10, RZ ;\n /*0810*/ MOV R10, R10 ;\n /*0820*/ MOV R10, R10 ;\n /*0830*/ IMAD.HI.U32 R10, R9, R10, RZ ;\n /*0840*/ IADD3 R10, R9, R10, RZ ;\n /*0850*/ IABS R9, R7 ;\n /*0860*/ MOV R9, R9 ;\n /*0870*/ MOV R9, R9 ;\n /*0880*/ IMAD.HI.U32 R10, R10, R9, RZ ;\n /*0890*/ IMAD.U32 R11, R8, R10, RZ ;\n /*08a0*/ IADD3 R14, R10, 0x1, RZ ;\n /*08b0*/ IADD3 R11, R9, -R11, RZ ;\n /*08c0*/ ISETP.LE.U32.AND P0, PT, R8, R11, PT ;\n /*08d0*/ SEL R14, R14, R10, P0 ;\n /*08e0*/ IADD3 R9, R14, 0x1, RZ ;\n /*08f0*/ IADD3 R10, R11, -R8, RZ ;\n /*0900*/ SEL R10, R10, R11, P0 ;\n /*0910*/ ISETP.GE.U32.AND P0, PT, R10, R8, PT ;\n /*0920*/ SEL R9, R9, R14, P0 ;\n /*0930*/ LOP3.LUT R7, R7, R6, RZ, 0x3c, !PT ;\n /*0940*/ MOV R8, RZ ;\n /*0950*/ ISETP.GE.AND P0, PT, R7, R8, PT ;\n /*0960*/ MOV R6, R6 ;\n /*0970*/ MOV R9, R9 ;\n /*0980*/ BSSY B0, `(.L_x_16) ;\n /*0990*/ @P0 BRA `(.L_x_17) ;\n /*09a0*/ IADD3 R9, RZ, -R9, RZ ;\n /*09b0*/ MOV R9, R9 ;\n /*09c0*/ MOV R9, R9 ;\n /*09d0*/ MOV R9, R9 ;\n.L_x_17:\n /*09e0*/ BSYNC B0 ;\n.L_x_16:\n /*09f0*/ MOV R7, RZ ;\n /*0a00*/ ISETP.NE.AND P0, PT, R6, R7, PT ;\n /*0a10*/ LOP3.LUT R6, RZ, R6, RZ, 0x33, !PT ;\n /*0a20*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ;\n /*0a30*/ SEL R6, R6, R9, P0 ;\n /*0a40*/ MOV R6, R6 ;\n /*0a50*/ MOV R7, R6 ;\n /*0a60*/ MOV R7, R7 ;\n /*0a70*/ IMAD R8, R7, R0, RZ ;\n /*0a80*/ IADD3 R5, R5, -R8, RZ ;\n /*0a90*/ ISETP.LT.AND P0, PT, R0, 0x1, PT ;\n /*0aa0*/ MOV R9, R6 ;\n /*0ab0*/ MOV R6, R7 ;\n /*0ac0*/ MOV R7, R5 ;\n /*0ad0*/ @P0 BRA `(.L_x_15) ;\n /*0ae0*/ IADD3 R8, R0, -0x1, RZ ;\n /*0af0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ;\n /*0b00*/ ISETP.LT.U32.AND P0, PT, R8, 0x3, PT ;\n /*0b10*/ MOV R8, RZ ;\n /*0b20*/ MOV R5, R5 ;\n /*0b30*/ MOV R8, R8 ;\n /*0b40*/ @P0 BRA `(.L_x_18) ;\n /*0b50*/ IADD3 R9, R0, -R5, RZ ;\n /*0b60*/ MOV R8, RZ ;\n /*0b70*/ MOV R9, R9 ;\n /*0b80*/ MOV R8, R8 ;\n.L_x_35:\n /*0b90*/ YIELD ;\n /*0ba0*/ IADD3 R10, R8, R6, RZ ;\n /*0bb0*/ MOV R10, R10 ;\n /*0bc0*/ MOV R0, R0 ;\n /*0bd0*/ MOV R10, R10 ;\n /*0be0*/ MOV R11, R0 ;\n /*0bf0*/ MOV R10, R10 ;\n /*0c00*/ MOV R11, R11 ;\n /*0c10*/ MOV R10, R10 ;\n /*0c20*/ MOV R11, R11 ;\n /*0c30*/ IABS R14, R11 ;\n /*0c40*/ MOV R14, R14 ;\n /*0c50*/ MOV R14, R14 ;\n /*0c60*/ I2F.U32.RP R15, R14 ;\n /*0c70*/ MUFU.RCP R15, R15 ;\n /*0c80*/ MOV R15, R15 ;\n /*0c90*/ IADD3 R15, R15, 0xffffffe, RZ ;\n /*0ca0*/ MOV R15, R15 ;\n /*0cb0*/ F2I.FTZ.U32.TRUNC.NTZ R15, R15 ;\n /*0cc0*/ IMAD.U32 R16, R14, R15, RZ ;\n /*0cd0*/ IADD3 R16, RZ, -R16, RZ ;\n /*0ce0*/ MOV R16, R16 ;\n /*0cf0*/ MOV R16, R16 ;\n /*0d00*/ IMAD.HI.U32 R16, R15, R16, RZ ;\n /*0d10*/ IADD3 R16, R15, R16, RZ ;\n /*0d20*/ IABS R15, R10 ;\n /*0d30*/ MOV R15, R15 ;\n /*0d40*/ MOV R15, R15 ;\n /*0d50*/ IMAD.HI.U32 R16, R16, R15, RZ ;\n /*0d60*/ IMAD.U32 R16, R14, R16, RZ ;\n /*0d70*/ IADD3 R16, R15, -R16, RZ ;\n /*0d80*/ ISETP.LE.U32.AND P0, PT, R14, R16, PT ;\n /*0d90*/ IADD3 R15, R16, -R14, RZ ;\n /*0da0*/ SEL R15, R15, R16, P0 ;\n /*0db0*/ IADD3 R16, R15, -R14, RZ ;\n /*0dc0*/ ISETP.LE.U32.AND P0, PT, R14, R15, PT ;\n /*0dd0*/ SEL R16, R16, R15, P0 ;\n /*0de0*/ MOV R14, RZ ;\n /*0df0*/ ISETP.GE.AND P0, PT, R10, R14, PT ;\n /*0e00*/ MOV R11, R11 ;\n /*0e10*/ MOV R16, R16 ;\n /*0e20*/ BSSY B0, `(.L_x_19) ;\n /*0e30*/ @P0 BRA `(.L_x_20) ;\n /*0e40*/ IADD3 R16, RZ, -R16, RZ ;\n /*0e50*/ MOV R16, R16 ;\n /*0e60*/ MOV R16, R16 ;\n /*0e70*/ MOV R16, R16 ;\n.L_x_20:\n /*0e80*/ BSYNC B0 ;\n.L_x_19:\n /*0e90*/ MOV R10, RZ ;\n /*0ea0*/ ISETP.NE.AND P0, PT, R11, R10, PT ;\n /*0eb0*/ LOP3.LUT R11, RZ, R11, RZ, 0x33, !PT ;\n /*0ec0*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ;\n /*0ed0*/ SEL R11, R11, R16, P0 ;\n /*0ee0*/ MOV R10, R11 ;\n /*0ef0*/ MOV R10, R10 ;\n /*0f00*/ MOV R10, R10 ;\n /*0f10*/ IADD3 R14, R8, R7, RZ ;\n /*0f20*/ MOV R14, R14 ;\n /*0f30*/ MOV R0, R0 ;\n /*0f40*/ MOV R16, R11 ;\n /*0f50*/ MOV R10, R10 ;\n /*0f60*/ MOV R14, R14 ;\n /*0f70*/ MOV R11, R0 ;\n /*0f80*/ MOV R14, R14 ;\n /*0f90*/ MOV R15, R11 ;\n /*0fa0*/ MOV R11, R14 ;\n /*0fb0*/ MOV R14, R15 ;\n /*0fc0*/ IABS R15, R14 ;\n /*0fd0*/ MOV R15, R15 ;\n /*0fe0*/ MOV R15, R15 ;\n /*0ff0*/ I2F.U32.RP R16, R15 ;\n /*1000*/ MUFU.RCP R16, R16 ;\n /*1010*/ MOV R16, R16 ;\n /*1020*/ IADD3 R16, R16, 0xffffffe, RZ ;\n /*1030*/ MOV R16, R16 ;\n /*1040*/ F2I.FTZ.U32.TRUNC.NTZ R16, R16 ;\n /*1050*/ IMAD.U32 R17, R15, R16, RZ ;\n /*1060*/ IADD3 R17, RZ, -R17, RZ ;\n /*1070*/ MOV R17, R17 ;\n /*1080*/ MOV R17, R17 ;\n /*1090*/ IMAD.HI.U32 R17, R16, R17, RZ ;\n /*10a0*/ IADD3 R17, R16, R17, RZ ;\n /*10b0*/ IABS R16, R11 ;\n /*10c0*/ MOV R16, R16 ;\n /*10d0*/ MOV R16, R16 ;\n /*10e0*/ IMAD.HI.U32 R17, R17, R16, RZ ;\n /*10f0*/ IMAD.U32 R17, R15, R17, RZ ;\n /*1100*/ IADD3 R17, R16, -R17, RZ ;\n /*1110*/ ISETP.LE.U32.AND P0, PT, R15, R17, PT ;\n /*1120*/ IADD3 R16, R17, -R15, RZ ;\n /*1130*/ SEL R16, R16, R17, P0 ;\n /*1140*/ IADD3 R17, R16, -R15, RZ ;\n /*1150*/ ISETP.LE.U32.AND P0, PT, R15, R16, PT ;\n /*1160*/ SEL R17, R17, R16, P0 ;\n /*1170*/ MOV R15, RZ ;\n /*1180*/ ISETP.GE.AND P0, PT, R11, R15, PT ;\n /*1190*/ MOV R14, R14 ;\n /*11a0*/ MOV R17, R17 ;\n /*11b0*/ BSSY B0, `(.L_x_21) ;\n /*11c0*/ @P0 BRA `(.L_x_22) ;\n /*11d0*/ IADD3 R17, RZ, -R17, RZ ;\n /*11e0*/ MOV R17, R17 ;\n /*11f0*/ MOV R17, R17 ;\n /*1200*/ MOV R17, R17 ;\n.L_x_22:\n /*1210*/ BSYNC B0 ;\n.L_x_21:\n /*1220*/ MOV R11, RZ ;\n /*1230*/ ISETP.NE.AND P0, PT, R14, R11, PT ;\n /*1240*/ LOP3.LUT R14, RZ, R14, RZ, 0x33, !PT ;\n /*1250*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ;\n /*1260*/ SEL R14, R14, R17, P0 ;\n /*1270*/ MOV R11, R14 ;\n /*1280*/ MOV R11, R11 ;\n /*1290*/ MOV R11, R11 ;\n /*12a0*/ IMAD R15, R10, R0, R11 ;\n /*12b0*/ IMAD.WIDE R10, R15, 0x4, RZ ;\n /*12c0*/ MOV R16, R10 ;\n /*12d0*/ MOV R11, R11 ;\n /*12e0*/ IADD3 R10, P0, R2, R16, RZ ;\n /*12f0*/ IADD3.X R11, R3, R11, RZ, P0, !PT ;\n /*1300*/ SHF.L.U32 R15, R15, 0x2, RZ ;\n /*1310*/ MOV R16, RZ ;\n /*1320*/ IADD3 R15, R16, R15, RZ ;\n /*1330*/ MOV R15, R15 ;\n /*1340*/ LDS R15, [R15] ;\n /*1350*/ FMUL R15, R4, R15 ;\n /*1360*/ MOV R10, R10 ;\n /*1370*/ MOV R11, R11 ;\n /*1380*/ MOV R10, R10 ;\n /*1390*/ MOV R11, R11 ;\n /*13a0*/ R2UR UR4, R12 ;\n /*13b0*/ R2UR UR5, R13 ;\n /*13c0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R10.64], R15 ;\n /*13d0*/ IADD3 R11, R8, 0x1, RZ ;\n /*13e0*/ IADD3 R10, R11, R6, RZ ;\n /*13f0*/ MOV R15, R10 ;\n /*1400*/ MOV R0, R0 ;\n /*1410*/ MOV R17, R14 ;\n /*1420*/ MOV R10, R16 ;\n /*1430*/ MOV R11, R11 ;\n /*1440*/ MOV R15, R15 ;\n /*1450*/ MOV R14, R0 ;\n /*1460*/ MOV R15, R15 ;\n /*1470*/ MOV R16, R14 ;\n /*1480*/ MOV R14, R15 ;\n /*1490*/ MOV R15, R16 ;\n /*14a0*/ IABS R16, R15 ;\n /*14b0*/ MOV R16, R16 ;\n /*14c0*/ MOV R16, R16 ;\n /*14d0*/ I2F.U32.RP R17, R16 ;\n /*14e0*/ MUFU.RCP R17, R17 ;\n /*14f0*/ MOV R17, R17 ;\n /*1500*/ IADD3 R17, R17, 0xffffffe, RZ ;\n /*1510*/ MOV R17, R17 ;\n /*1520*/ F2I.FTZ.U32.TRUNC.NTZ R17, R17 ;\n /*1530*/ IMAD.U32 R18, R16, R17, RZ ;\n /*1540*/ IADD3 R18, RZ, -R18, RZ ;\n /*1550*/ MOV R18, R18 ;\n /*1560*/ MOV R18, R18 ;\n /*1570*/ IMAD.HI.U32 R18, R17, R18, RZ ;\n /*1580*/ IADD3 R18, R17, R18, RZ ;\n /*1590*/ IABS R17, R14 ;\n /*15a0*/ MOV R17, R17 ;\n /*15b0*/ MOV R17, R17 ;\n /*15c0*/ IMAD.HI.U32 R18, R18, R17, RZ ;\n /*15d0*/ IMAD.U32 R18, R16, R18, RZ ;\n /*15e0*/ IADD3 R18, R17, -R18, RZ ;\n /*15f0*/ ISETP.LE.U32.AND P0, PT, R16, R18, PT ;\n /*1600*/ IADD3 R17, R18, -R16, RZ ;\n /*1610*/ SEL R17, R17, R18, P0 ;\n /*1620*/ IADD3 R18, R17, -R16, RZ ;\n /*1630*/ ISETP.LE.U32.AND P0, PT, R16, R17, PT ;\n /*1640*/ SEL R18, R18, R17, P0 ;\n /*1650*/ MOV R16, RZ ;\n /*1660*/ ISETP.GE.AND P0, PT, R14, R16, PT ;\n /*1670*/ MOV R15, R15 ;\n /*1680*/ MOV R18, R18 ;\n /*1690*/ BSSY B0, `(.L_x_23) ;\n /*16a0*/ @P0 BRA `(.L_x_24) ;\n /*16b0*/ IADD3 R18, RZ, -R18, RZ ;\n /*16c0*/ MOV R18, R18 ;\n /*16d0*/ MOV R18, R18 ;\n /*16e0*/ MOV R18, R18 ;\n.L_x_24:\n /*16f0*/ BSYNC B0 ;\n.L_x_23:\n /*1700*/ MOV R14, RZ ;\n /*1710*/ ISETP.NE.AND P0, PT, R15, R14, PT ;\n /*1720*/ LOP3.LUT R15, RZ, R15, RZ, 0x33, !PT ;\n /*1730*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ;\n /*1740*/ SEL R15, R15, R18, P0 ;\n /*1750*/ MOV R14, R15 ;\n /*1760*/ MOV R14, R14 ;\n /*1770*/ MOV R14, R14 ;\n /*1780*/ IADD3 R11, R11, R7, RZ ;\n /*1790*/ MOV R16, R11 ;\n /*17a0*/ MOV R0, R0 ;\n /*17b0*/ MOV R18, R15 ;\n /*17c0*/ MOV R11, R14 ;\n /*17d0*/ MOV R16, R16 ;\n /*17e0*/ MOV R14, R0 ;\n /*17f0*/ MOV R16, R16 ;\n /*1800*/ MOV R15, R14 ;\n /*1810*/ MOV R14, R16 ;\n /*1820*/ MOV R15, R15 ;\n /*1830*/ IABS R16, R15 ;\n /*1840*/ MOV R16, R16 ;\n /*1850*/ MOV R16, R16 ;\n /*1860*/ I2F.U32.RP R17, R16 ;\n /*1870*/ MUFU.RCP R17, R17 ;\n /*1880*/ MOV R17, R17 ;\n /*1890*/ IADD3 R17, R17, 0xffffffe, RZ ;\n /*18a0*/ MOV R17, R17 ;\n /*18b0*/ F2I.FTZ.U32.TRUNC.NTZ R17, R17 ;\n /*18c0*/ IMAD.U32 R18, R16, R17, RZ ;\n /*18d0*/ IADD3 R18, RZ, -R18, RZ ;\n /*18e0*/ MOV R18, R18 ;\n /*18f0*/ MOV R18, R18 ;\n /*1900*/ IMAD.HI.U32 R18, R17, R18, RZ ;\n /*1910*/ IADD3 R18, R17, R18, RZ ;\n /*1920*/ IABS R17, R14 ;\n /*1930*/ MOV R17, R17 ;\n /*1940*/ MOV R17, R17 ;\n /*1950*/ IMAD.HI.U32 R18, R18, R17, RZ ;\n /*1960*/ IMAD.U32 R18, R16, R18, RZ ;\n /*1970*/ IADD3 R18, R17, -R18, RZ ;\n /*1980*/ ISETP.LE.U32.AND P0, PT, R16, R18, PT ;\n /*1990*/ IADD3 R17, R18, -R16, RZ ;\n /*19a0*/ SEL R17, R17, R18, P0 ;\n /*19b0*/ IADD3 R18, R17, -R16, RZ ;\n /*19c0*/ ISETP.LE.U32.AND P0, PT, R16, R17, PT ;\n /*19d0*/ SEL R18, R18, R17, P0 ;\n /*19e0*/ MOV R16, RZ ;\n /*19f0*/ ISETP.GE.AND P0, PT, R14, R16, PT ;\n /*1a00*/ MOV R15, R15 ;\n /*1a10*/ MOV R18, R18 ;\n /*1a20*/ BSSY B0, `(.L_x_25) ;\n /*1a30*/ @P0 BRA `(.L_x_26) ;\n /*1a40*/ IADD3 R18, RZ, -R18, RZ ;\n /*1a50*/ MOV R18, R18 ;\n /*1a60*/ MOV R18, R18 ;\n /*1a70*/ MOV R18, R18 ;\n.L_x_26:\n /*1a80*/ BSYNC B0 ;\n.L_x_25:\n /*1a90*/ MOV R14, RZ ;\n /*1aa0*/ ISETP.NE.AND P0, PT, R15, R14, PT ;\n /*1ab0*/ LOP3.LUT R15, RZ, R15, RZ, 0x33, !PT ;\n /*1ac0*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ;\n /*1ad0*/ SEL R18, R15, R18, P0 ;\n /*1ae0*/ MOV R14, R18 ;\n /*1af0*/ MOV R14, R14 ;\n /*1b00*/ MOV R14, R14 ;\n /*1b10*/ IMAD R11, R11, R0, R14 ;\n /*1b20*/ IMAD.WIDE R14, R11, 0x4, RZ ;\n /*1b30*/ MOV R16, R14 ;\n /*1b40*/ MOV R15, R15 ;\n /*1b50*/ IADD3 R14, P0, R2, R16, RZ ;\n /*1b60*/ IADD3.X R15, R3, R15, RZ, P0, !PT ;\n /*1b70*/ SHF.L.U32 R11, R11, 0x2, RZ ;\n /*1b80*/ IADD3 R11, R10, R11, RZ ;\n /*1b90*/ MOV R11, R11 ;\n /*1ba0*/ LDS R11, [R11] ;\n /*1bb0*/ FMUL R11, R4, R11 ;\n /*1bc0*/ MOV R14, R14 ;\n /*1bd0*/ MOV R15, R15 ;\n /*1be0*/ MOV R14, R14 ;\n /*1bf0*/ MOV R15, R15 ;\n /*1c00*/ R2UR UR4, R12 ;\n /*1c10*/ R2UR UR5, R13 ;\n /*1c20*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64], R11 ;\n /*1c30*/ IADD3 R11, R8, 0x2, RZ ;\n /*1c40*/ IADD3 R14, R11, R6, RZ ;\n /*1c50*/ MOV R14, R14 ;\n /*1c60*/ MOV R0, R0 ;\n /*1c70*/ MOV R18, R18 ;\n /*1c80*/ MOV R11, R11 ;\n /*1c90*/ MOV R14, R14 ;\n /*1ca0*/ MOV R15, R0 ;\n /*1cb0*/ MOV R14, R14 ;\n /*1cc0*/ MOV R15, R15 ;\n /*1cd0*/ MOV R14, R14 ;\n /*1ce0*/ MOV R15, R15 ;\n /*1cf0*/ IABS R16, R15 ;\n /*1d00*/ MOV R16, R16 ;\n /*1d10*/ MOV R16, R16 ;\n /*1d20*/ I2F.U32.RP R17, R16 ;\n /*1d30*/ MUFU.RCP R17, R17 ;\n /*1d40*/ MOV R17, R17 ;\n /*1d50*/ IADD3 R17, R17, 0xffffffe, RZ ;\n /*1d60*/ MOV R17, R17 ;\n /*1d70*/ F2I.FTZ.U32.TRUNC.NTZ R17, R17 ;\n /*1d80*/ IMAD.U32 R18, R16, R17, RZ ;\n /*1d90*/ IADD3 R18, RZ, -R18, RZ ;\n /*1da0*/ MOV R18, R18 ;\n /*1db0*/ MOV R18, R18 ;\n /*1dc0*/ IMAD.HI.U32 R18, R17, R18, RZ ;\n /*1dd0*/ IADD3 R18, R17, R18, RZ ;\n /*1de0*/ IABS R17, R14 ;\n /*1df0*/ MOV R17, R17 ;\n /*1e00*/ MOV R17, R17 ;\n /*1e10*/ IMAD.HI.U32 R18, R18, R17, RZ ;\n /*1e20*/ IMAD.U32 R18, R16, R18, RZ ;\n /*1e30*/ IADD3 R18, R17, -R18, RZ ;\n /*1e40*/ ISETP.LE.U32.AND P0, PT, R16, R18, PT ;\n /*1e50*/ IADD3 R17, R18, -R16, RZ ;\n /*1e60*/ SEL R17, R17, R18, P0 ;\n /*1e70*/ IADD3 R18, R17, -R16, RZ ;\n /*1e80*/ ISETP.LE.U32.AND P0, PT, R16, R17, PT ;\n /*1e90*/ SEL R18, R18, R17, P0 ;\n /*1ea0*/ MOV R16, RZ ;\n /*1eb0*/ ISETP.GE.AND P0, PT, R14, R16, PT ;\n /*1ec0*/ MOV R15, R15 ;\n /*1ed0*/ MOV R18, R18 ;\n /*1ee0*/ BSSY B0, `(.L_x_27) ;\n /*1ef0*/ @P0 BRA `(.L_x_28) ;\n /*1f00*/ IADD3 R18, RZ, -R18, RZ ;\n /*1f10*/ MOV R18, R18 ;\n /*1f20*/ MOV R18, R18 ;\n /*1f30*/ MOV R18, R18 ;\n.L_x_28:\n /*1f40*/ BSYNC B0 ;\n.L_x_27:\n /*1f50*/ MOV R14, RZ ;\n /*1f60*/ ISETP.NE.AND P0, PT, R15, R14, PT ;\n /*1f70*/ LOP3.LUT R15, RZ, R15, RZ, 0x33, !PT ;\n /*1f80*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ;\n /*1f90*/ SEL R15, R15, R18, P0 ;\n /*1fa0*/ MOV R14, R15 ;\n /*1fb0*/ MOV R14, R14 ;\n /*1fc0*/ MOV R14, R14 ;\n /*1fd0*/ IADD3 R11, R11, R7, RZ ;\n /*1fe0*/ MOV R16, R11 ;\n /*1ff0*/ MOV R0, R0 ;\n /*2000*/ MOV R18, R15 ;\n /*2010*/ MOV R11, R14 ;\n /*2020*/ MOV R16, R16 ;\n /*2030*/ MOV R14, R0 ;\n /*2040*/ MOV R16, R16 ;\n /*2050*/ MOV R15, R14 ;\n /*2060*/ MOV R14, R16 ;\n /*2070*/ MOV R15, R15 ;\n /*2080*/ IABS R16, R15 ;\n /*2090*/ MOV R16, R16 ;\n /*20a0*/ MOV R16, R16 ;\n /*20b0*/ I2F.U32.RP R17, R16 ;\n /*20c0*/ MUFU.RCP R17, R17 ;\n /*20d0*/ MOV R17, R17 ;\n /*20e0*/ IADD3 R17, R17, 0xffffffe, RZ ;\n /*20f0*/ MOV R17, R17 ;\n /*2100*/ F2I.FTZ.U32.TRUNC.NTZ R17, R17 ;\n /*2110*/ IMAD.U32 R18, R16, R17, RZ ;\n /*2120*/ IADD3 R18, RZ, -R18, RZ ;\n /*2130*/ MOV R18, R18 ;\n /*2140*/ MOV R18, R18 ;\n /*2150*/ IMAD.HI.U32 R18, R17, R18, RZ ;\n /*2160*/ IADD3 R18, R17, R18, RZ ;\n /*2170*/ IABS R17, R14 ;\n /*2180*/ MOV R17, R17 ;\n /*2190*/ MOV R17, R17 ;\n /*21a0*/ IMAD.HI.U32 R18, R18, R17, RZ ;\n /*21b0*/ IMAD.U32 R18, R16, R18, RZ ;\n /*21c0*/ IADD3 R18, R17, -R18, RZ ;\n /*21d0*/ ISETP.LE.U32.AND P0, PT, R16, R18, PT ;\n /*21e0*/ IADD3 R17, R18, -R16, RZ ;\n /*21f0*/ SEL R17, R17, R18, P0 ;\n /*2200*/ IADD3 R18, R17, -R16, RZ ;\n /*2210*/ ISETP.LE.U32.AND P0, PT, R16, R17, PT ;\n /*2220*/ SEL R18, R18, R17, P0 ;\n /*2230*/ MOV R16, RZ ;\n /*2240*/ ISETP.GE.AND P0, PT, R14, R16, PT ;\n /*2250*/ MOV R15, R15 ;\n /*2260*/ MOV R18, R18 ;\n /*2270*/ BSSY B0, `(.L_x_29) ;\n /*2280*/ @P0 BRA `(.L_x_30) ;\n /*2290*/ IADD3 R18, RZ, -R18, RZ ;\n /*22a0*/ MOV R18, R18 ;\n /*22b0*/ MOV R18, R18 ;\n /*22c0*/ MOV R18, R18 ;\n.L_x_30:\n /*22d0*/ BSYNC B0 ;\n.L_x_29:\n /*22e0*/ MOV R14, RZ ;\n /*22f0*/ ISETP.NE.AND P0, PT, R15, R14, PT ;\n /*2300*/ LOP3.LUT R15, RZ, R15, RZ, 0x33, !PT ;\n /*2310*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ;\n /*2320*/ SEL R18, R15, R18, P0 ;\n /*2330*/ MOV R14, R18 ;\n /*2340*/ MOV R14, R14 ;\n /*2350*/ MOV R14, R14 ;\n /*2360*/ IMAD R11, R11, R0, R14 ;\n /*2370*/ IMAD.WIDE R14, R11, 0x4, RZ ;\n /*2380*/ MOV R16, R14 ;\n /*2390*/ MOV R15, R15 ;\n /*23a0*/ IADD3 R14, P0, R2, R16, RZ ;\n /*23b0*/ IADD3.X R15, R3, R15, RZ, P0, !PT ;\n /*23c0*/ SHF.L.U32 R11, R11, 0x2, RZ ;\n /*23d0*/ IADD3 R11, R10, R11, RZ ;\n /*23e0*/ MOV R11, R11 ;\n /*23f0*/ LDS R11, [R11] ;\n /*2400*/ FMUL R11, R4, R11 ;\n /*2410*/ MOV R14, R14 ;\n /*2420*/ MOV R15, R15 ;\n /*2430*/ MOV R14, R14 ;\n /*2440*/ MOV R15, R15 ;\n /*2450*/ R2UR UR4, R12 ;\n /*2460*/ R2UR UR5, R13 ;\n /*2470*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R14.64], R11 ;\n /*2480*/ IADD3 R11, R8, 0x3, RZ ;\n /*2490*/ IADD3 R14, R11, R6, RZ ;\n /*24a0*/ MOV R14, R14 ;\n /*24b0*/ MOV R0, R0 ;\n /*24c0*/ MOV R18, R18 ;\n /*24d0*/ MOV R11, R11 ;\n /*24e0*/ MOV R14, R14 ;\n /*24f0*/ MOV R15, R0 ;\n /*2500*/ MOV R14, R14 ;\n /*2510*/ MOV R15, R15 ;\n /*2520*/ MOV R14, R14 ;\n /*2530*/ MOV R15, R15 ;\n /*2540*/ IABS R16, R15 ;\n /*2550*/ MOV R16, R16 ;\n /*2560*/ MOV R16, R16 ;\n /*2570*/ I2F.U32.RP R17, R16 ;\n /*2580*/ MUFU.RCP R17, R17 ;\n /*2590*/ MOV R17, R17 ;\n /*25a0*/ IADD3 R17, R17, 0xffffffe, RZ ;\n /*25b0*/ MOV R17, R17 ;\n /*25c0*/ F2I.FTZ.U32.TRUNC.NTZ R17, R17 ;\n /*25d0*/ IMAD.U32 R18, R16, R17, RZ ;\n /*25e0*/ IADD3 R18, RZ, -R18, RZ ;\n /*25f0*/ MOV R18, R18 ;\n /*2600*/ MOV R18, R18 ;\n /*2610*/ IMAD.HI.U32 R18, R17, R18, RZ ;\n /*2620*/ IADD3 R18, R17, R18, RZ ;\n /*2630*/ IABS R17, R14 ;\n /*2640*/ MOV R17, R17 ;\n /*2650*/ MOV R17, R17 ;\n /*2660*/ IMAD.HI.U32 R18, R18, R17, RZ ;\n /*2670*/ IMAD.U32 R18, R16, R18, RZ ;\n /*2680*/ IADD3 R18, R17, -R18, RZ ;\n /*2690*/ ISETP.LE.U32.AND P0, PT, R16, R18, PT ;\n /*26a0*/ IADD3 R17, R18, -R16, RZ ;\n /*26b0*/ SEL R17, R17, R18, P0 ;\n /*26c0*/ IADD3 R18, R17, -R16, RZ ;\n /*26d0*/ ISETP.LE.U32.AND P0, PT, R16, R17, PT ;\n /*26e0*/ SEL R18, R18, R17, P0 ;\n /*26f0*/ MOV R16, RZ ;\n /*2700*/ ISETP.GE.AND P0, PT, R14, R16, PT ;\n /*2710*/ MOV R15, R15 ;\n /*2720*/ MOV R18, R18 ;\n /*2730*/ BSSY B0, `(.L_x_31) ;\n /*2740*/ @P0 BRA `(.L_x_32) ;\n /*2750*/ IADD3 R18, RZ, -R18, RZ ;\n /*2760*/ MOV R18, R18 ;\n /*2770*/ MOV R18, R18 ;\n /*2780*/ MOV R18, R18 ;\n.L_x_32:\n /*2790*/ BSYNC B0 ;\n.L_x_31:\n /*27a0*/ MOV R14, RZ ;\n /*27b0*/ ISETP.NE.AND P0, PT, R15, R14, PT ;\n /*27c0*/ LOP3.LUT R15, RZ, R15, RZ, 0x33, !PT ;\n /*27d0*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ;\n /*27e0*/ SEL R15, R15, R18, P0 ;\n /*27f0*/ MOV R14, R15 ;\n /*2800*/ MOV R14, R14 ;\n /*2810*/ MOV R14, R14 ;\n /*2820*/ IADD3 R11, R11, R7, RZ ;\n /*2830*/ MOV R16, R11 ;\n /*2840*/ MOV R0, R0 ;\n /*2850*/ MOV R18, R15 ;\n /*2860*/ MOV R11, R14 ;\n /*2870*/ MOV R16, R16 ;\n /*2880*/ MOV R14, R0 ;\n /*2890*/ MOV R16, R16 ;\n /*28a0*/ MOV R15, R14 ;\n /*28b0*/ MOV R14, R16 ;\n /*28c0*/ MOV R15, R15 ;\n /*28d0*/ IABS R16, R15 ;\n /*28e0*/ MOV R16, R16 ;\n /*28f0*/ MOV R16, R16 ;\n /*2900*/ I2F.U32.RP R17, R16 ;\n /*2910*/ MUFU.RCP R17, R17 ;\n /*2920*/ MOV R17, R17 ;\n /*2930*/ IADD3 R17, R17, 0xffffffe, RZ ;\n /*2940*/ MOV R17, R17 ;\n /*2950*/ F2I.FTZ.U32.TRUNC.NTZ R17, R17 ;\n /*2960*/ IMAD.U32 R18, R16, R17, RZ ;\n /*2970*/ IADD3 R18, RZ, -R18, RZ ;\n /*2980*/ MOV R18, R18 ;\n /*2990*/ MOV R18, R18 ;\n /*29a0*/ IMAD.HI.U32 R18, R17, R18, RZ ;\n /*29b0*/ IADD3 R18, R17, R18, RZ ;\n /*29c0*/ IABS R17, R14 ;\n /*29d0*/ MOV R17, R17 ;\n /*29e0*/ MOV R17, R17 ;\n /*29f0*/ IMAD.HI.U32 R18, R18, R17, RZ ;\n /*2a00*/ IMAD.U32 R18, R16, R18, RZ ;\n /*2a10*/ IADD3 R18, R17, -R18, RZ ;\n /*2a20*/ ISETP.LE.U32.AND P0, PT, R16, R18, PT ;\n /*2a30*/ IADD3 R17, R18, -R16, RZ ;\n /*2a40*/ SEL R17, R17, R18, P0 ;\n /*2a50*/ IADD3 R18, R17, -R16, RZ ;\n /*2a60*/ ISETP.LE.U32.AND P0, PT, R16, R17, PT ;\n /*2a70*/ SEL R18, R18, R17, P0 ;\n /*2a80*/ MOV R16, RZ ;\n /*2a90*/ ISETP.GE.AND P0, PT, R14, R16, PT ;\n /*2aa0*/ MOV R15, R15 ;\n /*2ab0*/ MOV R18, R18 ;\n /*2ac0*/ BSSY B0, `(.L_x_33) ;\n /*2ad0*/ @P0 BRA `(.L_x_34) ;\n /*2ae0*/ IADD3 R18, RZ, -R18, RZ ;\n /*2af0*/ MOV R18, R18 ;\n /*2b00*/ MOV R18, R18 ;\n /*2b10*/ MOV R18, R18 ;\n.L_x_34:\n /*2b20*/ BSYNC B0 ;\n.L_x_33:\n /*2b30*/ MOV R14, RZ ;\n /*2b40*/ ISETP.NE.AND P0, PT, R15, R14, PT ;\n /*2b50*/ LOP3.LUT R15, RZ, R15, RZ, 0x33, !PT ;\n /*2b60*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ;\n /*2b70*/ SEL R18, R15, R18, P0 ;\n /*2b80*/ MOV R14, R18 ;\n /*2b90*/ MOV R14, R14 ;\n /*2ba0*/ MOV R14, R14 ;\n /*2bb0*/ IMAD R11, R11, R0, R14 ;\n /*2bc0*/ IMAD.WIDE R14, R11, 0x4, RZ ;\n /*2bd0*/ MOV R16, R14 ;\n /*2be0*/ MOV R14, R15 ;\n /*2bf0*/ IADD3 R15, P0, R2, R16, RZ ;\n /*2c00*/ IADD3.X R16, R3, R14, RZ, P0, !PT ;\n /*2c10*/ SHF.L.U32 R11, R11, 0x2, RZ ;\n /*2c20*/ IADD3 R11, R10, R11, RZ ;\n /*2c30*/ MOV R11, R11 ;\n /*2c40*/ LDS R11, [R11] ;\n /*2c50*/ FMUL R14, R4, R11 ;\n /*2c60*/ MOV R10, R15 ;\n /*2c70*/ MOV R11, R16 ;\n /*2c80*/ MOV R10, R10 ;\n /*2c90*/ MOV R11, R11 ;\n /*2ca0*/ R2UR UR4, R12 ;\n /*2cb0*/ R2UR UR5, R13 ;\n /*2cc0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R10.64], R14 ;\n /*2cd0*/ IADD3 R8, R8, 0x4, RZ ;\n /*2ce0*/ IADD3 R9, R9, -0x4, RZ ;\n /*2cf0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ;\n /*2d00*/ MOV R18, R18 ;\n /*2d10*/ MOV R8, R8 ;\n /*2d20*/ MOV R9, R9 ;\n /*2d30*/ @P0 BRA `(.L_x_35) ;\n.L_x_18:\n /*2d40*/ ISETP.EQ.AND P0, PT, R5, RZ, PT ;\n /*2d50*/ @P0 BRA `(.L_x_15) ;\n /*2d60*/ IADD3 R7, R8, R7, RZ ;\n /*2d70*/ IADD3 R8, R8, R6, RZ ;\n /*2d80*/ MOV R6, R7 ;\n /*2d90*/ MOV R7, R8 ;\n.L_x_40:\n /*2da0*/ YIELD ;\n /*2db0*/ MOV R7, R7 ;\n /*2dc0*/ MOV R0, R0 ;\n /*2dd0*/ MOV R8, R7 ;\n /*2de0*/ MOV R9, R0 ;\n /*2df0*/ MOV R8, R8 ;\n /*2e00*/ MOV R9, R9 ;\n /*2e10*/ MOV R8, R8 ;\n /*2e20*/ MOV R9, R9 ;\n /*2e30*/ IABS R10, R9 ;\n /*2e40*/ MOV R10, R10 ;\n /*2e50*/ MOV R10, R10 ;\n /*2e60*/ I2F.U32.RP R11, R10 ;\n /*2e70*/ MUFU.RCP R11, R11 ;\n /*2e80*/ MOV R11, R11 ;\n /*2e90*/ IADD3 R11, R11, 0xffffffe, RZ ;\n /*2ea0*/ MOV R11, R11 ;\n /*2eb0*/ F2I.FTZ.U32.TRUNC.NTZ R11, R11 ;\n /*2ec0*/ IMAD.U32 R14, R10, R11, RZ ;\n /*2ed0*/ IADD3 R14, RZ, -R14, RZ ;\n /*2ee0*/ MOV R14, R14 ;\n /*2ef0*/ MOV R14, R14 ;\n /*2f00*/ IMAD.HI.U32 R14, R11, R14, RZ ;\n /*2f10*/ IADD3 R14, R11, R14, RZ ;\n /*2f20*/ IABS R11, R8 ;\n /*2f30*/ MOV R11, R11 ;\n /*2f40*/ MOV R11, R11 ;\n /*2f50*/ IMAD.HI.U32 R14, R14, R11, RZ ;\n /*2f60*/ IMAD.U32 R14, R10, R14, RZ ;\n /*2f70*/ IADD3 R14, R11, -R14, RZ ;\n /*2f80*/ ISETP.LE.U32.AND P0, PT, R10, R14, PT ;\n /*2f90*/ IADD3 R11, R14, -R10, RZ ;\n /*2fa0*/ SEL R11, R11, R14, P0 ;\n /*2fb0*/ IADD3 R14, R11, -R10, RZ ;\n /*2fc0*/ ISETP.LE.U32.AND P0, PT, R10, R11, PT ;\n /*2fd0*/ SEL R14, R14, R11, P0 ;\n /*2fe0*/ MOV R10, RZ ;\n /*2ff0*/ ISETP.GE.AND P0, PT, R8, R10, PT ;\n /*3000*/ MOV R9, R9 ;\n /*3010*/ MOV R14, R14 ;\n /*3020*/ BSSY B0, `(.L_x_36) ;\n /*3030*/ @P0 BRA `(.L_x_37) ;\n /*3040*/ IADD3 R14, RZ, -R14, RZ ;\n /*3050*/ MOV R14, R14 ;\n /*3060*/ MOV R14, R14 ;\n /*3070*/ MOV R14, R14 ;\n.L_x_37:\n /*3080*/ BSYNC B0 ;\n.L_x_36:\n /*3090*/ MOV R8, RZ ;\n /*30a0*/ ISETP.NE.AND P0, PT, R9, R8, PT ;\n /*30b0*/ LOP3.LUT R9, RZ, R9, RZ, 0x33, !PT ;\n /*30c0*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ;\n /*30d0*/ SEL R9, R9, R14, P0 ;\n /*30e0*/ MOV R8, R9 ;\n /*30f0*/ MOV R8, R8 ;\n /*3100*/ MOV R8, R8 ;\n /*3110*/ MOV R6, R6 ;\n /*3120*/ MOV R0, R0 ;\n /*3130*/ MOV R14, R9 ;\n /*3140*/ MOV R8, R8 ;\n /*3150*/ MOV R9, R6 ;\n /*3160*/ MOV R10, R0 ;\n /*3170*/ MOV R9, R9 ;\n /*3180*/ MOV R10, R10 ;\n /*3190*/ MOV R9, R9 ;\n /*31a0*/ MOV R10, R10 ;\n /*31b0*/ IABS R11, R10 ;\n /*31c0*/ MOV R11, R11 ;\n /*31d0*/ MOV R11, R11 ;\n /*31e0*/ I2F.U32.RP R14, R11 ;\n /*31f0*/ MUFU.RCP R14, R14 ;\n /*3200*/ MOV R14, R14 ;\n /*3210*/ IADD3 R14, R14, 0xffffffe, RZ ;\n /*3220*/ MOV R14, R14 ;\n /*3230*/ F2I.FTZ.U32.TRUNC.NTZ R14, R14 ;\n /*3240*/ IMAD.U32 R15, R11, R14, RZ ;\n /*3250*/ IADD3 R15, RZ, -R15, RZ ;\n /*3260*/ MOV R15, R15 ;\n /*3270*/ MOV R15, R15 ;\n /*3280*/ IMAD.HI.U32 R15, R14, R15, RZ ;\n /*3290*/ IADD3 R15, R14, R15, RZ ;\n /*32a0*/ IABS R14, R9 ;\n /*32b0*/ MOV R14, R14 ;\n /*32c0*/ MOV R14, R14 ;\n /*32d0*/ IMAD.HI.U32 R15, R15, R14, RZ ;\n /*32e0*/ IMAD.U32 R15, R11, R15, RZ ;\n /*32f0*/ IADD3 R15, R14, -R15, RZ ;\n /*3300*/ ISETP.LE.U32.AND P0, PT, R11, R15, PT ;\n /*3310*/ IADD3 R14, R15, -R11, RZ ;\n /*3320*/ SEL R14, R14, R15, P0 ;\n /*3330*/ IADD3 R15, R14, -R11, RZ ;\n /*3340*/ ISETP.LE.U32.AND P0, PT, R11, R14, PT ;\n /*3350*/ SEL R15, R15, R14, P0 ;\n /*3360*/ MOV R11, RZ ;\n /*3370*/ ISETP.GE.AND P0, PT, R9, R11, PT ;\n /*3380*/ MOV R10, R10 ;\n /*3390*/ MOV R15, R15 ;\n /*33a0*/ BSSY B0, `(.L_x_38) ;\n /*33b0*/ @P0 BRA `(.L_x_39) ;\n /*33c0*/ IADD3 R15, RZ, -R15, RZ ;\n /*33d0*/ MOV R15, R15 ;\n /*33e0*/ MOV R15, R15 ;\n /*33f0*/ MOV R15, R15 ;\n.L_x_39:\n /*3400*/ BSYNC B0 ;\n.L_x_38:\n /*3410*/ MOV R9, RZ ;\n /*3420*/ ISETP.NE.AND P0, PT, R10, R9, PT ;\n /*3430*/ LOP3.LUT R10, RZ, R10, RZ, 0x33, !PT ;\n /*3440*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ;\n /*3450*/ SEL R10, R10, R15, P0 ;\n /*3460*/ MOV R9, R10 ;\n /*3470*/ MOV R9, R9 ;\n /*3480*/ MOV R9, R9 ;\n /*3490*/ IMAD R11, R8, R0, R9 ;\n /*34a0*/ IMAD.WIDE R8, R11, 0x4, RZ ;\n /*34b0*/ MOV R14, R8 ;\n /*34c0*/ MOV R8, R9 ;\n /*34d0*/ IADD3 R9, P0, R2, R14, RZ ;\n /*34e0*/ IADD3.X R14, R3, R8, RZ, P0, !PT ;\n /*34f0*/ SHF.L.U32 R11, R11, 0x2, RZ ;\n /*3500*/ MOV R8, RZ ;\n /*3510*/ IADD3 R8, R8, R11, RZ ;\n /*3520*/ MOV R8, R8 ;\n /*3530*/ LDS R8, [R8] ;\n /*3540*/ FMUL R11, R4, R8 ;\n /*3550*/ MOV R8, R9 ;\n /*3560*/ MOV R9, R14 ;\n /*3570*/ MOV R8, R8 ;\n /*3580*/ MOV R9, R9 ;\n /*3590*/ R2UR UR4, R12 ;\n /*35a0*/ R2UR UR5, R13 ;\n /*35b0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R8.64], R11 ;\n /*35c0*/ IADD3 R6, R6, 0x1, RZ ;\n /*35d0*/ IADD3 R7, R7, 0x1, RZ ;\n /*35e0*/ IADD3 R5, R5, -0x1, RZ ;\n /*35f0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ;\n /*3600*/ MOV R15, R10 ;\n /*3610*/ MOV R6, R6 ;\n /*3620*/ MOV R7, R7 ;\n /*3630*/ MOV R5, R5 ;\n /*3640*/ @P0 BRA `(.L_x_40) ;\n.L_x_15:\n /*3650*/ EXIT ;\n.L_x_41:\n /*3660*/ BRA `(.L_x_41);\n /*3670*/ NOP;\n /*3680*/ NOP;\n /*3690*/ NOP;\n /*36a0*/ NOP;\n /*36b0*/ NOP;\n /*36c0*/ NOP;\n /*36d0*/ NOP;\n /*36e0*/ NOP;\n /*36f0*/ NOP;\n.L_x_88:\n\n\n//--------------------- .text._Z21generate_sparse_inputPiPfP17curandStateXORWOWi --------------------------\n .section .text._Z21generate_sparse_inputPiPfP17curandStateXORWOWi,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=27\"\n .align 128\n\n\n\n\n .global _Z21generate_sparse_inputPiPfP17curandStateXORWOWi\n .type _Z21generate_sparse_inputPiPfP17curandStateXORWOWi,@function\n .size _Z21generate_sparse_inputPiPfP17curandStateXORWOWi,(.L_x_89 - _Z21generate_sparse_inputPiPfP17curandStateXORWOWi)\n .other _Z21generate_sparse_inputPiPfP17curandStateXORWOWi,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z21generate_sparse_inputPiPfP17curandStateXORWOWi:\n.text._Z21generate_sparse_inputPiPfP17curandStateXORWOWi:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ MOV R20, c[0x0][0x118] ;\n /*0020*/ MOV R21, c[0x0][0x11c] ;\n /*0030*/ MOV R2, RZ ;\n /*0040*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0050*/ MOV R16, R2 ;\n /*0060*/ MOV R11, R3 ;\n /*0070*/ MOV R16, R16 ;\n /*0080*/ MOV R11, R11 ;\n /*0090*/ MOV R2, 0x8 ;\n /*00a0*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*00b0*/ MOV R12, R2 ;\n /*00c0*/ MOV R7, R3 ;\n /*00d0*/ MOV R12, R12 ;\n /*00e0*/ MOV R7, R7 ;\n /*00f0*/ MOV R2, 0x10 ;\n /*0100*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0110*/ MOV R5, R2 ;\n /*0120*/ MOV R6, R3 ;\n /*0130*/ MOV R5, R5 ;\n /*0140*/ MOV R6, R6 ;\n /*0150*/ MOV R0, 0x18 ;\n /*0160*/ LDC R0, c[0x0][R0+0x160] ;\n /*0170*/ MOV R0, R0 ;\n /*0180*/ S2R R2, SR_TID.X ;\n /*0190*/ MOV R2, R2 ;\n /*01a0*/ MOV R3, c[0x0][0x0] ;\n /*01b0*/ S2R R4, SR_CTAID.X ;\n /*01c0*/ MOV R4, R4 ;\n /*01d0*/ IMAD R2, R4, R3, R2 ;\n /*01e0*/ ISETP.GE.AND P0, PT, R2, R0, PT ;\n /*01f0*/ MOV R16, R16 ;\n /*0200*/ MOV R11, R11 ;\n /*0210*/ MOV R12, R12 ;\n /*0220*/ MOV R0, R7 ;\n /*0230*/ MOV R4, R5 ;\n /*0240*/ MOV R5, R6 ;\n /*0250*/ MOV R17, R2 ;\n /*0260*/ @P0 BRA `(.L_x_42) ;\n /*0270*/ MOV R4, R4 ;\n /*0280*/ MOV R5, R5 ;\n /*0290*/ IMAD.WIDE R2, R17, 0x30, RZ ;\n /*02a0*/ MOV R14, R2 ;\n /*02b0*/ MOV R13, R3 ;\n /*02c0*/ IADD3 R14, P0, R4, R14, RZ ;\n /*02d0*/ IADD3.X R13, R5, R13, RZ, P0, !PT ;\n /*02e0*/ MOV R2, R14 ;\n /*02f0*/ MOV R3, R13 ;\n /*0300*/ MOV R2, R2 ;\n /*0310*/ MOV R3, R3 ;\n /*0320*/ R2UR UR4, R20 ;\n /*0330*/ R2UR UR5, R21 ;\n /*0340*/ LDG.E.64 R2, [R2.64] ;\n /*0350*/ MOV R2, R2 ;\n /*0360*/ MOV R10, R3 ;\n /*0370*/ IADD3 R4, P0, R14, 0x8, RZ ;\n /*0380*/ IADD3.X R5, R13, RZ, RZ, P0, !PT ;\n /*0390*/ MOV R4, R4 ;\n /*03a0*/ MOV R5, R5 ;\n /*03b0*/ MOV R4, R4 ;\n /*03c0*/ MOV R5, R5 ;\n /*03d0*/ R2UR UR4, R20 ;\n /*03e0*/ R2UR UR5, R21 ;\n /*03f0*/ LDG.E.64 R4, [R4.64] ;\n /*0400*/ MOV R18, R4 ;\n /*0410*/ MOV R3, R5 ;\n /*0420*/ IADD3 R4, P0, R14, 0x10, RZ ;\n /*0430*/ IADD3.X R5, R13, RZ, RZ, P0, !PT ;\n /*0440*/ MOV R4, R4 ;\n /*0450*/ MOV R5, R5 ;\n /*0460*/ MOV R4, R4 ;\n /*0470*/ MOV R5, R5 ;\n /*0480*/ R2UR UR4, R20 ;\n /*0490*/ R2UR UR5, R21 ;\n /*04a0*/ LDG.E.64 R4, [R4.64] ;\n /*04b0*/ MOV R4, R4 ;\n /*04c0*/ MOV R5, R5 ;\n /*04d0*/ IADD3 R6, P0, R14, 0x18, RZ ;\n /*04e0*/ IADD3.X R7, R13, RZ, RZ, P0, !PT ;\n /*04f0*/ MOV R6, R6 ;\n /*0500*/ MOV R7, R7 ;\n /*0510*/ MOV R6, R6 ;\n /*0520*/ MOV R7, R7 ;\n /*0530*/ R2UR UR4, R20 ;\n /*0540*/ R2UR UR5, R21 ;\n /*0550*/ LDG.E.64 R6, [R6.64] ;\n /*0560*/ MOV R6, R6 ;\n /*0570*/ MOV R7, R7 ;\n /*0580*/ IADD3 R8, P0, R14, 0x20, RZ ;\n /*0590*/ IADD3.X R9, R13, RZ, RZ, P0, !PT ;\n /*05a0*/ MOV R8, R8 ;\n /*05b0*/ MOV R9, R9 ;\n /*05c0*/ MOV R8, R8 ;\n /*05d0*/ MOV R9, R9 ;\n /*05e0*/ R2UR UR4, R20 ;\n /*05f0*/ R2UR UR5, R21 ;\n /*0600*/ LDG.E R15, [R8.64] ;\n /*0610*/ IADD3 R8, P0, R14, 0x28, RZ ;\n /*0620*/ IADD3.X R9, R13, RZ, RZ, P0, !PT ;\n /*0630*/ MOV R8, R8 ;\n /*0640*/ MOV R9, R9 ;\n /*0650*/ MOV R8, R8 ;\n /*0660*/ MOV R9, R9 ;\n /*0670*/ R2UR UR4, R20 ;\n /*0680*/ R2UR UR5, R21 ;\n /*0690*/ LDG.E.64 R8, [R8.64] ;\n /*06a0*/ SHF.R.U32.HI R19, RZ, 0x2, R10 ;\n /*06b0*/ LOP3.LUT R19, R19, R10, RZ, 0x3c, !PT ;\n /*06c0*/ SHF.L.U32 R10, R5, 0x4, RZ ;\n /*06d0*/ SHF.L.U32 R22, R19, 0x1, RZ ;\n /*06e0*/ LOP3.LUT R10, R10, R5, RZ, 0x3c, !PT ;\n /*06f0*/ LOP3.LUT R10, R10, R19, RZ, 0x3c, !PT ;\n /*0700*/ LOP3.LUT R10, R10, R22, RZ, 0x3c, !PT ;\n /*0710*/ IADD3 R19, R2, R10, RZ ;\n /*0720*/ IADD3 R19, R19, 0x587c5, RZ ;\n /*0730*/ LOP3.LUT R19, R19, 0xfffffff, RZ, 0xc0, !PT ;\n /*0740*/ MOV R24, R16 ;\n /*0750*/ MOV R11, R11 ;\n /*0760*/ IMAD.WIDE R22, R17, 0x4, RZ ;\n /*0770*/ MOV R16, R22 ;\n /*0780*/ MOV R17, R23 ;\n /*0790*/ IADD3 R22, P0, R24, R16, RZ ;\n /*07a0*/ IADD3.X R23, R11, R17, RZ, P0, !PT ;\n /*07b0*/ MOV R22, R22 ;\n /*07c0*/ MOV R23, R23 ;\n /*07d0*/ MOV R22, R22 ;\n /*07e0*/ MOV R23, R23 ;\n /*07f0*/ R2UR UR4, R20 ;\n /*0800*/ R2UR UR5, R21 ;\n /*0810*/ STG.E [R22.64], R19 ;\n /*0820*/ SHF.R.U32.HI R11, RZ, 0x2, R18 ;\n /*0830*/ LOP3.LUT R11, R11, R18, RZ, 0x3c, !PT ;\n /*0840*/ SHF.L.U32 R18, R10, 0x4, RZ ;\n /*0850*/ SHF.L.U32 R19, R11, 0x1, RZ ;\n /*0860*/ LOP3.LUT R19, R19, R11, RZ, 0x3c, !PT ;\n /*0870*/ LOP3.LUT R11, R19, R10, RZ, 0x3c, !PT ;\n /*0880*/ IADD3 R2, R2, 0xb0f8a, RZ ;\n /*0890*/ LOP3.LUT R11, R11, R18, RZ, 0x3c, !PT ;\n /*08a0*/ IADD3 R18, R11, R2, RZ ;\n /*08b0*/ I2FP.F32.U32 R18, R18 ;\n /*08c0*/ MOV R19, 0x2f800000 ;\n /*08d0*/ FFMA R18, R18, R19, 1.1641532182693481445e-10 ;\n /*08e0*/ MOV R12, R12 ;\n /*08f0*/ MOV R0, R0 ;\n /*0900*/ IADD3 R16, P0, R12, R16, RZ ;\n /*0910*/ IADD3.X R17, R0, R17, RZ, P0, !PT ;\n /*0920*/ MOV R16, R16 ;\n /*0930*/ MOV R17, R17 ;\n /*0940*/ MOV R16, R16 ;\n /*0950*/ MOV R17, R17 ;\n /*0960*/ R2UR UR4, R20 ;\n /*0970*/ R2UR UR5, R21 ;\n /*0980*/ STG.E [R16.64], R18 ;\n /*0990*/ MOV R16, R14 ;\n /*09a0*/ MOV R17, R13 ;\n /*09b0*/ MOV R16, R16 ;\n /*09c0*/ MOV R17, R17 ;\n /*09d0*/ R2UR UR4, R20 ;\n /*09e0*/ R2UR UR5, R21 ;\n /*09f0*/ STG.E.64 [R16.64], R2 ;\n /*0a00*/ IADD3 R2, P0, R14, 0x8, RZ ;\n /*0a10*/ IADD3.X R3, R13, RZ, RZ, P0, !PT ;\n /*0a20*/ MOV R2, R2 ;\n /*0a30*/ MOV R3, R3 ;\n /*0a40*/ MOV R2, R2 ;\n /*0a50*/ MOV R3, R3 ;\n /*0a60*/ R2UR UR4, R20 ;\n /*0a70*/ R2UR UR5, R21 ;\n /*0a80*/ STG.E.64 [R2.64], R4 ;\n /*0a90*/ IADD3 R2, P0, R14, 0x10, RZ ;\n /*0aa0*/ IADD3.X R3, R13, RZ, RZ, P0, !PT ;\n /*0ab0*/ MOV R2, R2 ;\n /*0ac0*/ MOV R3, R3 ;\n /*0ad0*/ MOV R2, R2 ;\n /*0ae0*/ MOV R3, R3 ;\n /*0af0*/ R2UR UR4, R20 ;\n /*0b00*/ R2UR UR5, R21 ;\n /*0b10*/ STG.E.64 [R2.64], R10 ;\n /*0b20*/ IADD3 R2, P0, R14, 0x18, RZ ;\n /*0b30*/ IADD3.X R3, R13, RZ, RZ, P0, !PT ;\n /*0b40*/ MOV R2, R2 ;\n /*0b50*/ MOV R3, R3 ;\n /*0b60*/ MOV R2, R2 ;\n /*0b70*/ MOV R3, R3 ;\n /*0b80*/ R2UR UR4, R20 ;\n /*0b90*/ R2UR UR5, R21 ;\n /*0ba0*/ STG.E.64 [R2.64], R6 ;\n /*0bb0*/ IADD3 R2, P0, R14, 0x20, RZ ;\n /*0bc0*/ IADD3.X R3, R13, RZ, RZ, P0, !PT ;\n /*0bd0*/ MOV R2, R2 ;\n /*0be0*/ MOV R3, R3 ;\n /*0bf0*/ MOV R2, R2 ;\n /*0c00*/ MOV R3, R3 ;\n /*0c10*/ R2UR UR4, R20 ;\n /*0c20*/ R2UR UR5, R21 ;\n /*0c30*/ STG.E [R2.64], R15 ;\n /*0c40*/ IADD3 R2, P0, R14, 0x28, RZ ;\n /*0c50*/ IADD3.X R3, R13, RZ, RZ, P0, !PT ;\n /*0c60*/ MOV R2, R2 ;\n /*0c70*/ MOV R3, R3 ;\n /*0c80*/ MOV R2, R2 ;\n /*0c90*/ MOV R3, R3 ;\n /*0ca0*/ R2UR UR4, R20 ;\n /*0cb0*/ R2UR UR5, R21 ;\n /*0cc0*/ STG.E.64 [R2.64], R8 ;\n.L_x_42:\n /*0cd0*/ EXIT ;\n.L_x_43:\n /*0ce0*/ BRA `(.L_x_43);\n /*0cf0*/ NOP;\n /*0d00*/ NOP;\n /*0d10*/ NOP;\n /*0d20*/ NOP;\n /*0d30*/ NOP;\n /*0d40*/ NOP;\n /*0d50*/ NOP;\n /*0d60*/ NOP;\n /*0d70*/ NOP;\n.L_x_89:\n\n\n//--------------------- .text._Z17initialize_randomP17curandStateXORWOWm --------------------------\n .section .text._Z17initialize_randomP17curandStateXORWOWm,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=31\"\n .align 128\n\n\n\n\n .global _Z17initialize_randomP17curandStateXORWOWm\n .type _Z17initialize_randomP17curandStateXORWOWm,@function\n .size _Z17initialize_randomP17curandStateXORWOWm,(.L_x_90 - _Z17initialize_randomP17curandStateXORWOWm)\n .other _Z17initialize_randomP17curandStateXORWOWm,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z17initialize_randomP17curandStateXORWOWm:\n.text._Z17initialize_randomP17curandStateXORWOWm:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ MOV R18, c[0x0][0x118] ;\n /*0020*/ MOV R19, c[0x0][0x11c] ;\n /*0030*/ MOV R2, RZ ;\n /*0040*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0050*/ MOV R0, R2 ;\n /*0060*/ MOV R4, R3 ;\n /*0070*/ MOV R0, R0 ;\n /*0080*/ MOV R4, R4 ;\n /*0090*/ MOV R2, 0x8 ;\n /*00a0*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*00b0*/ MOV R7, R2 ;\n /*00c0*/ MOV R8, R3 ;\n /*00d0*/ MOV R7, R7 ;\n /*00e0*/ MOV R8, R8 ;\n /*00f0*/ MOV R0, R0 ;\n /*0100*/ MOV R2, R4 ;\n /*0110*/ MOV R3, c[0x0][0x0] ;\n /*0120*/ S2R R4, SR_CTAID.X ;\n /*0130*/ MOV R4, R4 ;\n /*0140*/ S2R R5, SR_TID.X ;\n /*0150*/ MOV R5, R5 ;\n /*0160*/ IMAD R3, R4, R3, R5 ;\n /*0170*/ MOV R4, R3 ;\n /*0180*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ;\n /*0190*/ MOV R4, R4 ;\n /*01a0*/ MOV R5, R5 ;\n /*01b0*/ MOV R4, R4 ;\n /*01c0*/ MOV R5, R5 ;\n /*01d0*/ MOV R6, R7 ;\n /*01e0*/ LOP3.LUT R6, R6, 0xaad26b49, RZ, 0x3c, !PT ;\n /*01f0*/ IMAD R10, R6, 0x4182bed5, RZ ;\n /*0200*/ SHF.R.U64 R6, R7, 0x20, R8 ;\n /*0210*/ SHF.R.U32.HI R7, RZ, 0x20, R8 ;\n /*0220*/ MOV R6, R6 ;\n /*0230*/ LOP3.LUT R6, R6, 0xf7dcefdd, RZ, 0x3c, !PT ;\n /*0240*/ IMAD R11, R6, -0x658354e5, RZ ;\n /*0250*/ IADD3 R8, R10, R11, RZ ;\n /*0260*/ IMAD.WIDE R6, R3, 0x30, RZ ;\n /*0270*/ MOV R9, R6 ;\n /*0280*/ MOV R7, R7 ;\n /*0290*/ IADD3 R6, P0, R0, R9, RZ ;\n /*02a0*/ IADD3.X R7, R2, R7, RZ, P0, !PT ;\n /*02b0*/ IADD3 R12, R8, 0x64f0c9, RZ ;\n /*02c0*/ IADD3 R13, R10, 0x75bcd15, RZ ;\n /*02d0*/ MOV R8, R6 ;\n /*02e0*/ MOV R9, R7 ;\n /*02f0*/ MOV R8, R8 ;\n /*0300*/ MOV R9, R9 ;\n /*0310*/ R2UR UR4, R18 ;\n /*0320*/ R2UR UR5, R19 ;\n /*0330*/ STG.E.64 [R8.64], R12 ;\n /*0340*/ LOP3.LUT R12, R10, 0x159a55e5, RZ, 0x3c, !PT ;\n /*0350*/ IADD3 R13, R11, 0x1f123bb5, RZ ;\n /*0360*/ IADD3 R8, P0, R6, 0x8, RZ ;\n /*0370*/ IADD3.X R9, R7, RZ, RZ, P0, !PT ;\n /*0380*/ MOV R8, R8 ;\n /*0390*/ MOV R9, R9 ;\n /*03a0*/ MOV R8, R8 ;\n /*03b0*/ MOV R9, R9 ;\n /*03c0*/ R2UR UR4, R18 ;\n /*03d0*/ R2UR UR5, R19 ;\n /*03e0*/ STG.E.64 [R8.64], R12 ;\n /*03f0*/ IADD3 R13, R10, 0x583f19, RZ ;\n /*0400*/ LOP3.LUT R12, R11, 0x5491333, RZ, 0x3c, !PT ;\n /*0410*/ IADD3 R8, P0, R6, 0x10, RZ ;\n /*0420*/ IADD3.X R9, R7, RZ, RZ, P0, !PT ;\n /*0430*/ MOV R8, R8 ;\n /*0440*/ MOV R9, R9 ;\n /*0450*/ MOV R8, R8 ;\n /*0460*/ MOV R9, R9 ;\n /*0470*/ R2UR UR4, R18 ;\n /*0480*/ R2UR UR5, R19 ;\n /*0490*/ STG.E.64 [R8.64], R12 ;\n /*04a0*/ ISETP.EQ.AND P0, PT, R3, RZ, PT ;\n /*04b0*/ MOV R0, R0 ;\n /*04c0*/ MOV R2, R2 ;\n /*04d0*/ MOV R3, R4 ;\n /*04e0*/ MOV R4, R5 ;\n /*04f0*/ MOV R3, R3 ;\n /*0500*/ MOV R4, R4 ;\n /*0510*/ MOV R5, R6 ;\n /*0520*/ MOV R6, R7 ;\n /*0530*/ BSSY B1, `(.L_x_44) ;\n /*0540*/ @P0 BRA `(.L_x_45) ;\n /*0550*/ MOV R7, RZ ;\n /*0560*/ MOV R8, R3 ;\n /*0570*/ MOV R9, R4 ;\n /*0580*/ MOV R8, R8 ;\n /*0590*/ MOV R9, R9 ;\n /*05a0*/ MOV R7, R7 ;\n /*05b0*/ MOV R10, R8 ;\n /*05c0*/ MOV R9, R9 ;\n /*05d0*/ MOV R8, R10 ;\n /*05e0*/ MOV R9, R9 ;\n.L_x_83:\n /*05f0*/ LOP3.LUT R10, R8, 0x3, RZ, 0xc0, !PT ;\n /*0600*/ LOP3.LUT R11, R9, RZ, RZ, 0xc0, !PT ;\n /*0610*/ ISETP.EQ.U32.AND P0, PT, R10, RZ, PT ;\n /*0620*/ ISETP.EQ.AND.EX P0, PT, R11, RZ, PT, P0 ;\n /*0630*/ BSSY B0, `(.L_x_46) ;\n /*0640*/ @P0 BRA `(.L_x_47) ;\n /*0650*/ MOV R10, RZ ;\n /*0660*/ MOV R10, R10 ;\n.L_x_82:\n /*0670*/ MOV R13, RZ ;\n /*0680*/ MOV R14, R13 ;\n /*0690*/ MOV R15, R13 ;\n /*06a0*/ MOV R12, R13 ;\n /*06b0*/ MOV R24, R13 ;\n /*06c0*/ MOV R16, R13 ;\n /*06d0*/ MOV R13, R13 ;\n /*06e0*/ MOV R14, R14 ;\n /*06f0*/ MOV R15, R15 ;\n /*0700*/ MOV R12, R12 ;\n /*0710*/ MOV R24, R24 ;\n /*0720*/ MOV R16, R16 ;\n.L_x_81:\n /*0730*/ MOV R20, RZ ;\n /*0740*/ MOV R21, RZ ;\n /*0750*/ MOV R20, R20 ;\n /*0760*/ MOV R21, R21 ;\n /*0770*/ IMAD.WIDE.U32 R20, R3, 0x30, R20 ;\n /*0780*/ MOV R11, R20 ;\n /*0790*/ MOV R22, R21 ;\n /*07a0*/ MOV R11, R11 ;\n /*07b0*/ IMAD.WIDE.U32 R20, R4, 0x30, RZ ;\n /*07c0*/ MOV R17, R20 ;\n /*07d0*/ MOV R20, R21 ;\n /*07e0*/ MOV R21, R20 ;\n /*07f0*/ MOV R20, R17 ;\n /*0800*/ IMAD.WIDE.U32 R20, P0, R3, RZ, R20 ;\n /*0810*/ MOV R17, R20 ;\n /*0820*/ MOV R20, R21 ;\n /*0830*/ IADD3 R22, P1, R17, R22, RZ ;\n /*0840*/ IADD3 R20, RZ, R20, RZ ;\n /*0850*/ IADD3.X R17, RZ, RZ, RZ, P0, !PT ;\n /*0860*/ MOV R20, R20 ;\n /*0870*/ MOV R17, R17 ;\n /*0880*/ MOV R20, R20 ;\n /*0890*/ MOV R21, R17 ;\n /*08a0*/ IMAD.WIDE.U32.X R20, R4, RZ, R20, P1 ;\n /*08b0*/ MOV R17, R20 ;\n /*08c0*/ MOV R20, R21 ;\n /*08d0*/ IADD3 R17, P0, R0, R11, RZ ;\n /*08e0*/ IADD3.X R22, R2, R22, RZ, P0, !PT ;\n /*08f0*/ IMAD.WIDE R20, R16, 0x4, RZ ;\n /*0900*/ MOV R11, R20 ;\n /*0910*/ MOV R21, R21 ;\n /*0920*/ IADD3 R20, P0, R17, R11, RZ ;\n /*0930*/ IADD3.X R21, R22, R21, RZ, P0, !PT ;\n /*0940*/ IADD3 R20, P0, R20, 0x4, RZ ;\n /*0950*/ IADD3.X R21, R21, RZ, RZ, P0, !PT ;\n /*0960*/ MOV R20, R20 ;\n /*0970*/ MOV R21, R21 ;\n /*0980*/ MOV R20, R20 ;\n /*0990*/ MOV R21, R21 ;\n /*09a0*/ R2UR UR4, R18 ;\n /*09b0*/ R2UR UR5, R19 ;\n /*09c0*/ LDG.E R17, [R20.64] ;\n /*09d0*/ MOV R22, RZ ;\n /*09e0*/ MOV R17, R17 ;\n /*09f0*/ MOV R22, R22 ;\n.L_x_80:\n /*0a00*/ MOV R20, R7 ;\n /*0a10*/ SHF.R.S32.HI R21, RZ, 0x1f, R20 ;\n /*0a20*/ MOV R20, R20 ;\n /*0a30*/ MOV R21, R21 ;\n /*0a40*/ MOV R25, R20 ;\n /*0a50*/ MOV R23, R21 ;\n /*0a60*/ MOV R25, R25 ;\n /*0a70*/ MOV R23, R23 ;\n /*0a80*/ SHF.L.U32 R11, R16, 0x5, RZ ;\n /*0a90*/ MOV R20, 0x1 ;\n /*0aa0*/ SHF.L.U32 R20, R20, R22, RZ ;\n /*0ab0*/ LOP3.LUT R20, R17, R20, RZ, 0xc0, !PT ;\n /*0ac0*/ ISETP.EQ.AND P0, PT, R20, RZ, PT ;\n /*0ad0*/ IADD3 R11, R22, R11, RZ ;\n /*0ae0*/ IMAD R11, R11, 0x5, RZ ;\n /*0af0*/ MOV R20, RZ ;\n /*0b00*/ MOV R21, RZ ;\n /*0b10*/ MOV R20, R20 ;\n /*0b20*/ MOV R21, R21 ;\n /*0b30*/ IMAD.WIDE.U32 R20, R25, 0xc80, R20 ;\n /*0b40*/ MOV R26, R20 ;\n /*0b50*/ MOV R27, R21 ;\n /*0b60*/ MOV R26, R26 ;\n /*0b70*/ IMAD.WIDE.U32 R20, R23, 0xc80, RZ ;\n /*0b80*/ MOV R28, R20 ;\n /*0b90*/ MOV R20, R21 ;\n /*0ba0*/ MOV R21, R20 ;\n /*0bb0*/ MOV R20, R28 ;\n /*0bc0*/ IMAD.WIDE.U32 R20, P1, R25, RZ, R20 ;\n /*0bd0*/ MOV R25, R20 ;\n /*0be0*/ MOV R20, R21 ;\n /*0bf0*/ IADD3 R25, P2, R25, R27, RZ ;\n /*0c00*/ IADD3 R20, RZ, R20, RZ ;\n /*0c10*/ IADD3.X R21, RZ, RZ, RZ, P1, !PT ;\n /*0c20*/ MOV R20, R20 ;\n /*0c30*/ MOV R21, R21 ;\n /*0c40*/ MOV R20, R20 ;\n /*0c50*/ MOV R21, R21 ;\n /*0c60*/ IMAD.WIDE.U32.X R20, R23, RZ, R20, P2 ;\n /*0c70*/ MOV R23, R20 ;\n /*0c80*/ MOV R20, R21 ;\n /*0c90*/ MOV R20, c[0x4][0x0] ;\n /*0ca0*/ MOV R21, c[0x4][0x4] ;\n /*0cb0*/ IADD3 R26, P1, R20, R26, RZ ;\n /*0cc0*/ IADD3.X R25, R21, R25, RZ, P1, !PT ;\n /*0cd0*/ IMAD.WIDE R20, R11, 0x4, RZ ;\n /*0ce0*/ MOV R23, R20 ;\n /*0cf0*/ MOV R11, R21 ;\n /*0d00*/ IADD3 R23, P1, R26, R23, RZ ;\n /*0d10*/ IADD3.X R11, R25, R11, RZ, P1, !PT ;\n /*0d20*/ MOV R23, R23 ;\n /*0d30*/ MOV R11, R11 ;\n /*0d40*/ BSSY B2, `(.L_x_48) ;\n /*0d50*/ @P0 BRA `(.L_x_49) ;\n /*0d60*/ MOV R20, R23 ;\n /*0d70*/ MOV R21, R11 ;\n /*0d80*/ MOV R20, R20 ;\n /*0d90*/ MOV R21, R21 ;\n /*0da0*/ R2UR UR4, R18 ;\n /*0db0*/ R2UR UR5, R19 ;\n /*0dc0*/ LDG.E R20, [R20.64] ;\n /*0dd0*/ LOP3.LUT R24, R24, R20, RZ, 0x3c, !PT ;\n /*0de0*/ IADD3 R20, P0, R23, 0x4, RZ ;\n /*0df0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*0e00*/ MOV R20, R20 ;\n /*0e10*/ MOV R21, R21 ;\n /*0e20*/ MOV R20, R20 ;\n /*0e30*/ MOV R21, R21 ;\n /*0e40*/ R2UR UR4, R18 ;\n /*0e50*/ R2UR UR5, R19 ;\n /*0e60*/ LDG.E R20, [R20.64] ;\n /*0e70*/ LOP3.LUT R12, R12, R20, RZ, 0x3c, !PT ;\n /*0e80*/ IADD3 R20, P0, R23, 0x8, RZ ;\n /*0e90*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*0ea0*/ MOV R20, R20 ;\n /*0eb0*/ MOV R21, R21 ;\n /*0ec0*/ MOV R20, R20 ;\n /*0ed0*/ MOV R21, R21 ;\n /*0ee0*/ R2UR UR4, R18 ;\n /*0ef0*/ R2UR UR5, R19 ;\n /*0f00*/ LDG.E R20, [R20.64] ;\n /*0f10*/ LOP3.LUT R25, R15, R20, RZ, 0x3c, !PT ;\n /*0f20*/ IADD3 R20, P0, R23, 0xc, RZ ;\n /*0f30*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*0f40*/ MOV R20, R20 ;\n /*0f50*/ MOV R21, R21 ;\n /*0f60*/ MOV R20, R20 ;\n /*0f70*/ MOV R21, R21 ;\n /*0f80*/ R2UR UR4, R18 ;\n /*0f90*/ R2UR UR5, R19 ;\n /*0fa0*/ LDG.E R20, [R20.64] ;\n /*0fb0*/ LOP3.LUT R20, R14, R20, RZ, 0x3c, !PT ;\n /*0fc0*/ IADD3 R14, P0, R23, 0x10, RZ ;\n /*0fd0*/ IADD3.X R15, R11, RZ, RZ, P0, !PT ;\n /*0fe0*/ MOV R14, R14 ;\n /*0ff0*/ MOV R15, R15 ;\n /*1000*/ MOV R14, R14 ;\n /*1010*/ MOV R15, R15 ;\n /*1020*/ R2UR UR4, R18 ;\n /*1030*/ R2UR UR5, R19 ;\n /*1040*/ LDG.E R14, [R14.64] ;\n /*1050*/ LOP3.LUT R13, R13, R14, RZ, 0x3c, !PT ;\n /*1060*/ MOV R24, R24 ;\n /*1070*/ MOV R12, R12 ;\n /*1080*/ MOV R15, R25 ;\n /*1090*/ MOV R14, R20 ;\n /*10a0*/ MOV R13, R13 ;\n.L_x_49:\n /*10b0*/ BSYNC B2 ;\n.L_x_48:\n /*10c0*/ MOV R20, 0x2 ;\n /*10d0*/ SHF.L.U32 R20, R20, R22, RZ ;\n /*10e0*/ LOP3.LUT R20, R17, R20, RZ, 0xc0, !PT ;\n /*10f0*/ ISETP.EQ.AND P0, PT, R20, RZ, PT ;\n /*1100*/ BSSY B2, `(.L_x_50) ;\n /*1110*/ @P0 BRA `(.L_x_51) ;\n /*1120*/ IADD3 R20, P0, R23, 0x14, RZ ;\n /*1130*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*1140*/ MOV R20, R20 ;\n /*1150*/ MOV R21, R21 ;\n /*1160*/ MOV R20, R20 ;\n /*1170*/ MOV R21, R21 ;\n /*1180*/ R2UR UR4, R18 ;\n /*1190*/ R2UR UR5, R19 ;\n /*11a0*/ LDG.E R20, [R20.64] ;\n /*11b0*/ LOP3.LUT R24, R24, R20, RZ, 0x3c, !PT ;\n /*11c0*/ IADD3 R20, P0, R23, 0x18, RZ ;\n /*11d0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*11e0*/ MOV R20, R20 ;\n /*11f0*/ MOV R21, R21 ;\n /*1200*/ MOV R20, R20 ;\n /*1210*/ MOV R21, R21 ;\n /*1220*/ R2UR UR4, R18 ;\n /*1230*/ R2UR UR5, R19 ;\n /*1240*/ LDG.E R20, [R20.64] ;\n /*1250*/ LOP3.LUT R12, R12, R20, RZ, 0x3c, !PT ;\n /*1260*/ IADD3 R20, P0, R23, 0x1c, RZ ;\n /*1270*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*1280*/ MOV R20, R20 ;\n /*1290*/ MOV R21, R21 ;\n /*12a0*/ MOV R20, R20 ;\n /*12b0*/ MOV R21, R21 ;\n /*12c0*/ R2UR UR4, R18 ;\n /*12d0*/ R2UR UR5, R19 ;\n /*12e0*/ LDG.E R20, [R20.64] ;\n /*12f0*/ LOP3.LUT R25, R15, R20, RZ, 0x3c, !PT ;\n /*1300*/ IADD3 R20, P0, R23, 0x20, RZ ;\n /*1310*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*1320*/ MOV R20, R20 ;\n /*1330*/ MOV R21, R21 ;\n /*1340*/ MOV R20, R20 ;\n /*1350*/ MOV R21, R21 ;\n /*1360*/ R2UR UR4, R18 ;\n /*1370*/ R2UR UR5, R19 ;\n /*1380*/ LDG.E R20, [R20.64] ;\n /*1390*/ LOP3.LUT R20, R14, R20, RZ, 0x3c, !PT ;\n /*13a0*/ IADD3 R14, P0, R23, 0x24, RZ ;\n /*13b0*/ IADD3.X R15, R11, RZ, RZ, P0, !PT ;\n /*13c0*/ MOV R14, R14 ;\n /*13d0*/ MOV R15, R15 ;\n /*13e0*/ MOV R14, R14 ;\n /*13f0*/ MOV R15, R15 ;\n /*1400*/ R2UR UR4, R18 ;\n /*1410*/ R2UR UR5, R19 ;\n /*1420*/ LDG.E R14, [R14.64] ;\n /*1430*/ LOP3.LUT R13, R13, R14, RZ, 0x3c, !PT ;\n /*1440*/ MOV R24, R24 ;\n /*1450*/ MOV R12, R12 ;\n /*1460*/ MOV R15, R25 ;\n /*1470*/ MOV R14, R20 ;\n /*1480*/ MOV R13, R13 ;\n.L_x_51:\n /*1490*/ BSYNC B2 ;\n.L_x_50:\n /*14a0*/ MOV R20, 0x4 ;\n /*14b0*/ SHF.L.U32 R20, R20, R22, RZ ;\n /*14c0*/ LOP3.LUT R20, R17, R20, RZ, 0xc0, !PT ;\n /*14d0*/ ISETP.EQ.AND P0, PT, R20, RZ, PT ;\n /*14e0*/ BSSY B2, `(.L_x_52) ;\n /*14f0*/ @P0 BRA `(.L_x_53) ;\n /*1500*/ IADD3 R20, P0, R23, 0x28, RZ ;\n /*1510*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*1520*/ MOV R20, R20 ;\n /*1530*/ MOV R21, R21 ;\n /*1540*/ MOV R20, R20 ;\n /*1550*/ MOV R21, R21 ;\n /*1560*/ R2UR UR4, R18 ;\n /*1570*/ R2UR UR5, R19 ;\n /*1580*/ LDG.E R20, [R20.64] ;\n /*1590*/ LOP3.LUT R24, R24, R20, RZ, 0x3c, !PT ;\n /*15a0*/ IADD3 R20, P0, R23, 0x2c, RZ ;\n /*15b0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*15c0*/ MOV R20, R20 ;\n /*15d0*/ MOV R21, R21 ;\n /*15e0*/ MOV R20, R20 ;\n /*15f0*/ MOV R21, R21 ;\n /*1600*/ R2UR UR4, R18 ;\n /*1610*/ R2UR UR5, R19 ;\n /*1620*/ LDG.E R20, [R20.64] ;\n /*1630*/ LOP3.LUT R12, R12, R20, RZ, 0x3c, !PT ;\n /*1640*/ IADD3 R20, P0, R23, 0x30, RZ ;\n /*1650*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*1660*/ MOV R20, R20 ;\n /*1670*/ MOV R21, R21 ;\n /*1680*/ MOV R20, R20 ;\n /*1690*/ MOV R21, R21 ;\n /*16a0*/ R2UR UR4, R18 ;\n /*16b0*/ R2UR UR5, R19 ;\n /*16c0*/ LDG.E R20, [R20.64] ;\n /*16d0*/ LOP3.LUT R25, R15, R20, RZ, 0x3c, !PT ;\n /*16e0*/ IADD3 R20, P0, R23, 0x34, RZ ;\n /*16f0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*1700*/ MOV R20, R20 ;\n /*1710*/ MOV R21, R21 ;\n /*1720*/ MOV R20, R20 ;\n /*1730*/ MOV R21, R21 ;\n /*1740*/ R2UR UR4, R18 ;\n /*1750*/ R2UR UR5, R19 ;\n /*1760*/ LDG.E R20, [R20.64] ;\n /*1770*/ LOP3.LUT R20, R14, R20, RZ, 0x3c, !PT ;\n /*1780*/ IADD3 R14, P0, R23, 0x38, RZ ;\n /*1790*/ IADD3.X R15, R11, RZ, RZ, P0, !PT ;\n /*17a0*/ MOV R14, R14 ;\n /*17b0*/ MOV R15, R15 ;\n /*17c0*/ MOV R14, R14 ;\n /*17d0*/ MOV R15, R15 ;\n /*17e0*/ R2UR UR4, R18 ;\n /*17f0*/ R2UR UR5, R19 ;\n /*1800*/ LDG.E R14, [R14.64] ;\n /*1810*/ LOP3.LUT R13, R13, R14, RZ, 0x3c, !PT ;\n /*1820*/ MOV R24, R24 ;\n /*1830*/ MOV R12, R12 ;\n /*1840*/ MOV R15, R25 ;\n /*1850*/ MOV R14, R20 ;\n /*1860*/ MOV R13, R13 ;\n.L_x_53:\n /*1870*/ BSYNC B2 ;\n.L_x_52:\n /*1880*/ MOV R20, 0x8 ;\n /*1890*/ SHF.L.U32 R20, R20, R22, RZ ;\n /*18a0*/ LOP3.LUT R20, R17, R20, RZ, 0xc0, !PT ;\n /*18b0*/ ISETP.EQ.AND P0, PT, R20, RZ, PT ;\n /*18c0*/ BSSY B2, `(.L_x_54) ;\n /*18d0*/ @P0 BRA `(.L_x_55) ;\n /*18e0*/ IADD3 R20, P0, R23, 0x3c, RZ ;\n /*18f0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*1900*/ MOV R20, R20 ;\n /*1910*/ MOV R21, R21 ;\n /*1920*/ MOV R20, R20 ;\n /*1930*/ MOV R21, R21 ;\n /*1940*/ R2UR UR4, R18 ;\n /*1950*/ R2UR UR5, R19 ;\n /*1960*/ LDG.E R20, [R20.64] ;\n /*1970*/ LOP3.LUT R24, R24, R20, RZ, 0x3c, !PT ;\n /*1980*/ IADD3 R20, P0, R23, 0x40, RZ ;\n /*1990*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*19a0*/ MOV R20, R20 ;\n /*19b0*/ MOV R21, R21 ;\n /*19c0*/ MOV R20, R20 ;\n /*19d0*/ MOV R21, R21 ;\n /*19e0*/ R2UR UR4, R18 ;\n /*19f0*/ R2UR UR5, R19 ;\n /*1a00*/ LDG.E R20, [R20.64] ;\n /*1a10*/ LOP3.LUT R12, R12, R20, RZ, 0x3c, !PT ;\n /*1a20*/ IADD3 R20, P0, R23, 0x44, RZ ;\n /*1a30*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*1a40*/ MOV R20, R20 ;\n /*1a50*/ MOV R21, R21 ;\n /*1a60*/ MOV R20, R20 ;\n /*1a70*/ MOV R21, R21 ;\n /*1a80*/ R2UR UR4, R18 ;\n /*1a90*/ R2UR UR5, R19 ;\n /*1aa0*/ LDG.E R20, [R20.64] ;\n /*1ab0*/ LOP3.LUT R25, R15, R20, RZ, 0x3c, !PT ;\n /*1ac0*/ IADD3 R20, P0, R23, 0x48, RZ ;\n /*1ad0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*1ae0*/ MOV R20, R20 ;\n /*1af0*/ MOV R21, R21 ;\n /*1b00*/ MOV R20, R20 ;\n /*1b10*/ MOV R21, R21 ;\n /*1b20*/ R2UR UR4, R18 ;\n /*1b30*/ R2UR UR5, R19 ;\n /*1b40*/ LDG.E R20, [R20.64] ;\n /*1b50*/ LOP3.LUT R20, R14, R20, RZ, 0x3c, !PT ;\n /*1b60*/ IADD3 R14, P0, R23, 0x4c, RZ ;\n /*1b70*/ IADD3.X R15, R11, RZ, RZ, P0, !PT ;\n /*1b80*/ MOV R14, R14 ;\n /*1b90*/ MOV R15, R15 ;\n /*1ba0*/ MOV R14, R14 ;\n /*1bb0*/ MOV R15, R15 ;\n /*1bc0*/ R2UR UR4, R18 ;\n /*1bd0*/ R2UR UR5, R19 ;\n /*1be0*/ LDG.E R14, [R14.64] ;\n /*1bf0*/ LOP3.LUT R13, R13, R14, RZ, 0x3c, !PT ;\n /*1c00*/ MOV R24, R24 ;\n /*1c10*/ MOV R12, R12 ;\n /*1c20*/ MOV R15, R25 ;\n /*1c30*/ MOV R14, R20 ;\n /*1c40*/ MOV R13, R13 ;\n.L_x_55:\n /*1c50*/ BSYNC B2 ;\n.L_x_54:\n /*1c60*/ MOV R20, 0x10 ;\n /*1c70*/ SHF.L.U32 R20, R20, R22, RZ ;\n /*1c80*/ LOP3.LUT R20, R17, R20, RZ, 0xc0, !PT ;\n /*1c90*/ ISETP.EQ.AND P0, PT, R20, RZ, PT ;\n /*1ca0*/ BSSY B2, `(.L_x_56) ;\n /*1cb0*/ @P0 BRA `(.L_x_57) ;\n /*1cc0*/ IADD3 R20, P0, R23, 0x50, RZ ;\n /*1cd0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*1ce0*/ MOV R20, R20 ;\n /*1cf0*/ MOV R21, R21 ;\n /*1d00*/ MOV R20, R20 ;\n /*1d10*/ MOV R21, R21 ;\n /*1d20*/ R2UR UR4, R18 ;\n /*1d30*/ R2UR UR5, R19 ;\n /*1d40*/ LDG.E R20, [R20.64] ;\n /*1d50*/ LOP3.LUT R24, R24, R20, RZ, 0x3c, !PT ;\n /*1d60*/ IADD3 R20, P0, R23, 0x54, RZ ;\n /*1d70*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*1d80*/ MOV R20, R20 ;\n /*1d90*/ MOV R21, R21 ;\n /*1da0*/ MOV R20, R20 ;\n /*1db0*/ MOV R21, R21 ;\n /*1dc0*/ R2UR UR4, R18 ;\n /*1dd0*/ R2UR UR5, R19 ;\n /*1de0*/ LDG.E R20, [R20.64] ;\n /*1df0*/ LOP3.LUT R12, R12, R20, RZ, 0x3c, !PT ;\n /*1e00*/ IADD3 R20, P0, R23, 0x58, RZ ;\n /*1e10*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*1e20*/ MOV R20, R20 ;\n /*1e30*/ MOV R21, R21 ;\n /*1e40*/ MOV R20, R20 ;\n /*1e50*/ MOV R21, R21 ;\n /*1e60*/ R2UR UR4, R18 ;\n /*1e70*/ R2UR UR5, R19 ;\n /*1e80*/ LDG.E R20, [R20.64] ;\n /*1e90*/ LOP3.LUT R25, R15, R20, RZ, 0x3c, !PT ;\n /*1ea0*/ IADD3 R20, P0, R23, 0x5c, RZ ;\n /*1eb0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*1ec0*/ MOV R20, R20 ;\n /*1ed0*/ MOV R21, R21 ;\n /*1ee0*/ MOV R20, R20 ;\n /*1ef0*/ MOV R21, R21 ;\n /*1f00*/ R2UR UR4, R18 ;\n /*1f10*/ R2UR UR5, R19 ;\n /*1f20*/ LDG.E R20, [R20.64] ;\n /*1f30*/ LOP3.LUT R20, R14, R20, RZ, 0x3c, !PT ;\n /*1f40*/ IADD3 R14, P0, R23, 0x60, RZ ;\n /*1f50*/ IADD3.X R15, R11, RZ, RZ, P0, !PT ;\n /*1f60*/ MOV R14, R14 ;\n /*1f70*/ MOV R15, R15 ;\n /*1f80*/ MOV R14, R14 ;\n /*1f90*/ MOV R15, R15 ;\n /*1fa0*/ R2UR UR4, R18 ;\n /*1fb0*/ R2UR UR5, R19 ;\n /*1fc0*/ LDG.E R14, [R14.64] ;\n /*1fd0*/ LOP3.LUT R13, R13, R14, RZ, 0x3c, !PT ;\n /*1fe0*/ MOV R24, R24 ;\n /*1ff0*/ MOV R12, R12 ;\n /*2000*/ MOV R15, R25 ;\n /*2010*/ MOV R14, R20 ;\n /*2020*/ MOV R13, R13 ;\n.L_x_57:\n /*2030*/ BSYNC B2 ;\n.L_x_56:\n /*2040*/ MOV R20, 0x20 ;\n /*2050*/ SHF.L.U32 R20, R20, R22, RZ ;\n /*2060*/ LOP3.LUT R20, R17, R20, RZ, 0xc0, !PT ;\n /*2070*/ ISETP.EQ.AND P0, PT, R20, RZ, PT ;\n /*2080*/ BSSY B2, `(.L_x_58) ;\n /*2090*/ @P0 BRA `(.L_x_59) ;\n /*20a0*/ IADD3 R20, P0, R23, 0x64, RZ ;\n /*20b0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*20c0*/ MOV R20, R20 ;\n /*20d0*/ MOV R21, R21 ;\n /*20e0*/ MOV R20, R20 ;\n /*20f0*/ MOV R21, R21 ;\n /*2100*/ R2UR UR4, R18 ;\n /*2110*/ R2UR UR5, R19 ;\n /*2120*/ LDG.E R20, [R20.64] ;\n /*2130*/ LOP3.LUT R24, R24, R20, RZ, 0x3c, !PT ;\n /*2140*/ IADD3 R20, P0, R23, 0x68, RZ ;\n /*2150*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*2160*/ MOV R20, R20 ;\n /*2170*/ MOV R21, R21 ;\n /*2180*/ MOV R20, R20 ;\n /*2190*/ MOV R21, R21 ;\n /*21a0*/ R2UR UR4, R18 ;\n /*21b0*/ R2UR UR5, R19 ;\n /*21c0*/ LDG.E R20, [R20.64] ;\n /*21d0*/ LOP3.LUT R12, R12, R20, RZ, 0x3c, !PT ;\n /*21e0*/ IADD3 R20, P0, R23, 0x6c, RZ ;\n /*21f0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*2200*/ MOV R20, R20 ;\n /*2210*/ MOV R21, R21 ;\n /*2220*/ MOV R20, R20 ;\n /*2230*/ MOV R21, R21 ;\n /*2240*/ R2UR UR4, R18 ;\n /*2250*/ R2UR UR5, R19 ;\n /*2260*/ LDG.E R20, [R20.64] ;\n /*2270*/ LOP3.LUT R25, R15, R20, RZ, 0x3c, !PT ;\n /*2280*/ IADD3 R20, P0, R23, 0x70, RZ ;\n /*2290*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*22a0*/ MOV R20, R20 ;\n /*22b0*/ MOV R21, R21 ;\n /*22c0*/ MOV R20, R20 ;\n /*22d0*/ MOV R21, R21 ;\n /*22e0*/ R2UR UR4, R18 ;\n /*22f0*/ R2UR UR5, R19 ;\n /*2300*/ LDG.E R20, [R20.64] ;\n /*2310*/ LOP3.LUT R20, R14, R20, RZ, 0x3c, !PT ;\n /*2320*/ IADD3 R14, P0, R23, 0x74, RZ ;\n /*2330*/ IADD3.X R15, R11, RZ, RZ, P0, !PT ;\n /*2340*/ MOV R14, R14 ;\n /*2350*/ MOV R15, R15 ;\n /*2360*/ MOV R14, R14 ;\n /*2370*/ MOV R15, R15 ;\n /*2380*/ R2UR UR4, R18 ;\n /*2390*/ R2UR UR5, R19 ;\n /*23a0*/ LDG.E R14, [R14.64] ;\n /*23b0*/ LOP3.LUT R13, R13, R14, RZ, 0x3c, !PT ;\n /*23c0*/ MOV R24, R24 ;\n /*23d0*/ MOV R12, R12 ;\n /*23e0*/ MOV R15, R25 ;\n /*23f0*/ MOV R14, R20 ;\n /*2400*/ MOV R13, R13 ;\n.L_x_59:\n /*2410*/ BSYNC B2 ;\n.L_x_58:\n /*2420*/ MOV R20, 0x40 ;\n /*2430*/ SHF.L.U32 R20, R20, R22, RZ ;\n /*2440*/ LOP3.LUT R20, R17, R20, RZ, 0xc0, !PT ;\n /*2450*/ ISETP.EQ.AND P0, PT, R20, RZ, PT ;\n /*2460*/ BSSY B2, `(.L_x_60) ;\n /*2470*/ @P0 BRA `(.L_x_61) ;\n /*2480*/ IADD3 R20, P0, R23, 0x78, RZ ;\n /*2490*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*24a0*/ MOV R20, R20 ;\n /*24b0*/ MOV R21, R21 ;\n /*24c0*/ MOV R20, R20 ;\n /*24d0*/ MOV R21, R21 ;\n /*24e0*/ R2UR UR4, R18 ;\n /*24f0*/ R2UR UR5, R19 ;\n /*2500*/ LDG.E R20, [R20.64] ;\n /*2510*/ LOP3.LUT R24, R24, R20, RZ, 0x3c, !PT ;\n /*2520*/ IADD3 R20, P0, R23, 0x7c, RZ ;\n /*2530*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*2540*/ MOV R20, R20 ;\n /*2550*/ MOV R21, R21 ;\n /*2560*/ MOV R20, R20 ;\n /*2570*/ MOV R21, R21 ;\n /*2580*/ R2UR UR4, R18 ;\n /*2590*/ R2UR UR5, R19 ;\n /*25a0*/ LDG.E R20, [R20.64] ;\n /*25b0*/ LOP3.LUT R12, R12, R20, RZ, 0x3c, !PT ;\n /*25c0*/ IADD3 R20, P0, R23, 0x80, RZ ;\n /*25d0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*25e0*/ MOV R20, R20 ;\n /*25f0*/ MOV R21, R21 ;\n /*2600*/ MOV R20, R20 ;\n /*2610*/ MOV R21, R21 ;\n /*2620*/ R2UR UR4, R18 ;\n /*2630*/ R2UR UR5, R19 ;\n /*2640*/ LDG.E R20, [R20.64] ;\n /*2650*/ LOP3.LUT R25, R15, R20, RZ, 0x3c, !PT ;\n /*2660*/ IADD3 R20, P0, R23, 0x84, RZ ;\n /*2670*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*2680*/ MOV R20, R20 ;\n /*2690*/ MOV R21, R21 ;\n /*26a0*/ MOV R20, R20 ;\n /*26b0*/ MOV R21, R21 ;\n /*26c0*/ R2UR UR4, R18 ;\n /*26d0*/ R2UR UR5, R19 ;\n /*26e0*/ LDG.E R20, [R20.64] ;\n /*26f0*/ LOP3.LUT R20, R14, R20, RZ, 0x3c, !PT ;\n /*2700*/ IADD3 R14, P0, R23, 0x88, RZ ;\n /*2710*/ IADD3.X R15, R11, RZ, RZ, P0, !PT ;\n /*2720*/ MOV R14, R14 ;\n /*2730*/ MOV R15, R15 ;\n /*2740*/ MOV R14, R14 ;\n /*2750*/ MOV R15, R15 ;\n /*2760*/ R2UR UR4, R18 ;\n /*2770*/ R2UR UR5, R19 ;\n /*2780*/ LDG.E R14, [R14.64] ;\n /*2790*/ LOP3.LUT R13, R13, R14, RZ, 0x3c, !PT ;\n /*27a0*/ MOV R24, R24 ;\n /*27b0*/ MOV R12, R12 ;\n /*27c0*/ MOV R15, R25 ;\n /*27d0*/ MOV R14, R20 ;\n /*27e0*/ MOV R13, R13 ;\n.L_x_61:\n /*27f0*/ BSYNC B2 ;\n.L_x_60:\n /*2800*/ MOV R20, 0x80 ;\n /*2810*/ SHF.L.U32 R20, R20, R22, RZ ;\n /*2820*/ LOP3.LUT R20, R17, R20, RZ, 0xc0, !PT ;\n /*2830*/ ISETP.EQ.AND P0, PT, R20, RZ, PT ;\n /*2840*/ BSSY B2, `(.L_x_62) ;\n /*2850*/ @P0 BRA `(.L_x_63) ;\n /*2860*/ IADD3 R20, P0, R23, 0x8c, RZ ;\n /*2870*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*2880*/ MOV R20, R20 ;\n /*2890*/ MOV R21, R21 ;\n /*28a0*/ MOV R20, R20 ;\n /*28b0*/ MOV R21, R21 ;\n /*28c0*/ R2UR UR4, R18 ;\n /*28d0*/ R2UR UR5, R19 ;\n /*28e0*/ LDG.E R20, [R20.64] ;\n /*28f0*/ LOP3.LUT R24, R24, R20, RZ, 0x3c, !PT ;\n /*2900*/ IADD3 R20, P0, R23, 0x90, RZ ;\n /*2910*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*2920*/ MOV R20, R20 ;\n /*2930*/ MOV R21, R21 ;\n /*2940*/ MOV R20, R20 ;\n /*2950*/ MOV R21, R21 ;\n /*2960*/ R2UR UR4, R18 ;\n /*2970*/ R2UR UR5, R19 ;\n /*2980*/ LDG.E R20, [R20.64] ;\n /*2990*/ LOP3.LUT R12, R12, R20, RZ, 0x3c, !PT ;\n /*29a0*/ IADD3 R20, P0, R23, 0x94, RZ ;\n /*29b0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*29c0*/ MOV R20, R20 ;\n /*29d0*/ MOV R21, R21 ;\n /*29e0*/ MOV R20, R20 ;\n /*29f0*/ MOV R21, R21 ;\n /*2a00*/ R2UR UR4, R18 ;\n /*2a10*/ R2UR UR5, R19 ;\n /*2a20*/ LDG.E R20, [R20.64] ;\n /*2a30*/ LOP3.LUT R25, R15, R20, RZ, 0x3c, !PT ;\n /*2a40*/ IADD3 R20, P0, R23, 0x98, RZ ;\n /*2a50*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*2a60*/ MOV R20, R20 ;\n /*2a70*/ MOV R21, R21 ;\n /*2a80*/ MOV R20, R20 ;\n /*2a90*/ MOV R21, R21 ;\n /*2aa0*/ R2UR UR4, R18 ;\n /*2ab0*/ R2UR UR5, R19 ;\n /*2ac0*/ LDG.E R20, [R20.64] ;\n /*2ad0*/ LOP3.LUT R20, R14, R20, RZ, 0x3c, !PT ;\n /*2ae0*/ IADD3 R14, P0, R23, 0x9c, RZ ;\n /*2af0*/ IADD3.X R15, R11, RZ, RZ, P0, !PT ;\n /*2b00*/ MOV R14, R14 ;\n /*2b10*/ MOV R15, R15 ;\n /*2b20*/ MOV R14, R14 ;\n /*2b30*/ MOV R15, R15 ;\n /*2b40*/ R2UR UR4, R18 ;\n /*2b50*/ R2UR UR5, R19 ;\n /*2b60*/ LDG.E R14, [R14.64] ;\n /*2b70*/ LOP3.LUT R13, R13, R14, RZ, 0x3c, !PT ;\n /*2b80*/ MOV R24, R24 ;\n /*2b90*/ MOV R12, R12 ;\n /*2ba0*/ MOV R15, R25 ;\n /*2bb0*/ MOV R14, R20 ;\n /*2bc0*/ MOV R13, R13 ;\n.L_x_63:\n /*2bd0*/ BSYNC B2 ;\n.L_x_62:\n /*2be0*/ MOV R20, 0x100 ;\n /*2bf0*/ SHF.L.U32 R20, R20, R22, RZ ;\n /*2c00*/ LOP3.LUT R20, R17, R20, RZ, 0xc0, !PT ;\n /*2c10*/ ISETP.EQ.AND P0, PT, R20, RZ, PT ;\n /*2c20*/ BSSY B2, `(.L_x_64) ;\n /*2c30*/ @P0 BRA `(.L_x_65) ;\n /*2c40*/ IADD3 R20, P0, R23, 0xa0, RZ ;\n /*2c50*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*2c60*/ MOV R20, R20 ;\n /*2c70*/ MOV R21, R21 ;\n /*2c80*/ MOV R20, R20 ;\n /*2c90*/ MOV R21, R21 ;\n /*2ca0*/ R2UR UR4, R18 ;\n /*2cb0*/ R2UR UR5, R19 ;\n /*2cc0*/ LDG.E R20, [R20.64] ;\n /*2cd0*/ LOP3.LUT R24, R24, R20, RZ, 0x3c, !PT ;\n /*2ce0*/ IADD3 R20, P0, R23, 0xa4, RZ ;\n /*2cf0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*2d00*/ MOV R20, R20 ;\n /*2d10*/ MOV R21, R21 ;\n /*2d20*/ MOV R20, R20 ;\n /*2d30*/ MOV R21, R21 ;\n /*2d40*/ R2UR UR4, R18 ;\n /*2d50*/ R2UR UR5, R19 ;\n /*2d60*/ LDG.E R20, [R20.64] ;\n /*2d70*/ LOP3.LUT R12, R12, R20, RZ, 0x3c, !PT ;\n /*2d80*/ IADD3 R20, P0, R23, 0xa8, RZ ;\n /*2d90*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*2da0*/ MOV R20, R20 ;\n /*2db0*/ MOV R21, R21 ;\n /*2dc0*/ MOV R20, R20 ;\n /*2dd0*/ MOV R21, R21 ;\n /*2de0*/ R2UR UR4, R18 ;\n /*2df0*/ R2UR UR5, R19 ;\n /*2e00*/ LDG.E R20, [R20.64] ;\n /*2e10*/ LOP3.LUT R25, R15, R20, RZ, 0x3c, !PT ;\n /*2e20*/ IADD3 R20, P0, R23, 0xac, RZ ;\n /*2e30*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*2e40*/ MOV R20, R20 ;\n /*2e50*/ MOV R21, R21 ;\n /*2e60*/ MOV R20, R20 ;\n /*2e70*/ MOV R21, R21 ;\n /*2e80*/ R2UR UR4, R18 ;\n /*2e90*/ R2UR UR5, R19 ;\n /*2ea0*/ LDG.E R20, [R20.64] ;\n /*2eb0*/ LOP3.LUT R20, R14, R20, RZ, 0x3c, !PT ;\n /*2ec0*/ IADD3 R14, P0, R23, 0xb0, RZ ;\n /*2ed0*/ IADD3.X R15, R11, RZ, RZ, P0, !PT ;\n /*2ee0*/ MOV R14, R14 ;\n /*2ef0*/ MOV R15, R15 ;\n /*2f00*/ MOV R14, R14 ;\n /*2f10*/ MOV R15, R15 ;\n /*2f20*/ R2UR UR4, R18 ;\n /*2f30*/ R2UR UR5, R19 ;\n /*2f40*/ LDG.E R14, [R14.64] ;\n /*2f50*/ LOP3.LUT R13, R13, R14, RZ, 0x3c, !PT ;\n /*2f60*/ MOV R24, R24 ;\n /*2f70*/ MOV R12, R12 ;\n /*2f80*/ MOV R15, R25 ;\n /*2f90*/ MOV R14, R20 ;\n /*2fa0*/ MOV R13, R13 ;\n.L_x_65:\n /*2fb0*/ BSYNC B2 ;\n.L_x_64:\n /*2fc0*/ MOV R20, 0x200 ;\n /*2fd0*/ SHF.L.U32 R20, R20, R22, RZ ;\n /*2fe0*/ LOP3.LUT R20, R17, R20, RZ, 0xc0, !PT ;\n /*2ff0*/ ISETP.EQ.AND P0, PT, R20, RZ, PT ;\n /*3000*/ BSSY B2, `(.L_x_66) ;\n /*3010*/ @P0 BRA `(.L_x_67) ;\n /*3020*/ IADD3 R20, P0, R23, 0xb4, RZ ;\n /*3030*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*3040*/ MOV R20, R20 ;\n /*3050*/ MOV R21, R21 ;\n /*3060*/ MOV R20, R20 ;\n /*3070*/ MOV R21, R21 ;\n /*3080*/ R2UR UR4, R18 ;\n /*3090*/ R2UR UR5, R19 ;\n /*30a0*/ LDG.E R20, [R20.64] ;\n /*30b0*/ LOP3.LUT R24, R24, R20, RZ, 0x3c, !PT ;\n /*30c0*/ IADD3 R20, P0, R23, 0xb8, RZ ;\n /*30d0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*30e0*/ MOV R20, R20 ;\n /*30f0*/ MOV R21, R21 ;\n /*3100*/ MOV R20, R20 ;\n /*3110*/ MOV R21, R21 ;\n /*3120*/ R2UR UR4, R18 ;\n /*3130*/ R2UR UR5, R19 ;\n /*3140*/ LDG.E R20, [R20.64] ;\n /*3150*/ LOP3.LUT R12, R12, R20, RZ, 0x3c, !PT ;\n /*3160*/ IADD3 R20, P0, R23, 0xbc, RZ ;\n /*3170*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*3180*/ MOV R20, R20 ;\n /*3190*/ MOV R21, R21 ;\n /*31a0*/ MOV R20, R20 ;\n /*31b0*/ MOV R21, R21 ;\n /*31c0*/ R2UR UR4, R18 ;\n /*31d0*/ R2UR UR5, R19 ;\n /*31e0*/ LDG.E R20, [R20.64] ;\n /*31f0*/ LOP3.LUT R25, R15, R20, RZ, 0x3c, !PT ;\n /*3200*/ IADD3 R20, P0, R23, 0xc0, RZ ;\n /*3210*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*3220*/ MOV R20, R20 ;\n /*3230*/ MOV R21, R21 ;\n /*3240*/ MOV R20, R20 ;\n /*3250*/ MOV R21, R21 ;\n /*3260*/ R2UR UR4, R18 ;\n /*3270*/ R2UR UR5, R19 ;\n /*3280*/ LDG.E R20, [R20.64] ;\n /*3290*/ LOP3.LUT R20, R14, R20, RZ, 0x3c, !PT ;\n /*32a0*/ IADD3 R14, P0, R23, 0xc4, RZ ;\n /*32b0*/ IADD3.X R15, R11, RZ, RZ, P0, !PT ;\n /*32c0*/ MOV R14, R14 ;\n /*32d0*/ MOV R15, R15 ;\n /*32e0*/ MOV R14, R14 ;\n /*32f0*/ MOV R15, R15 ;\n /*3300*/ R2UR UR4, R18 ;\n /*3310*/ R2UR UR5, R19 ;\n /*3320*/ LDG.E R14, [R14.64] ;\n /*3330*/ LOP3.LUT R13, R13, R14, RZ, 0x3c, !PT ;\n /*3340*/ MOV R24, R24 ;\n /*3350*/ MOV R12, R12 ;\n /*3360*/ MOV R15, R25 ;\n /*3370*/ MOV R14, R20 ;\n /*3380*/ MOV R13, R13 ;\n.L_x_67:\n /*3390*/ BSYNC B2 ;\n.L_x_66:\n /*33a0*/ MOV R20, 0x400 ;\n /*33b0*/ SHF.L.U32 R20, R20, R22, RZ ;\n /*33c0*/ LOP3.LUT R20, R17, R20, RZ, 0xc0, !PT ;\n /*33d0*/ ISETP.EQ.AND P0, PT, R20, RZ, PT ;\n /*33e0*/ BSSY B2, `(.L_x_68) ;\n /*33f0*/ @P0 BRA `(.L_x_69) ;\n /*3400*/ IADD3 R20, P0, R23, 0xc8, RZ ;\n /*3410*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*3420*/ MOV R20, R20 ;\n /*3430*/ MOV R21, R21 ;\n /*3440*/ MOV R20, R20 ;\n /*3450*/ MOV R21, R21 ;\n /*3460*/ R2UR UR4, R18 ;\n /*3470*/ R2UR UR5, R19 ;\n /*3480*/ LDG.E R20, [R20.64] ;\n /*3490*/ LOP3.LUT R24, R24, R20, RZ, 0x3c, !PT ;\n /*34a0*/ IADD3 R20, P0, R23, 0xcc, RZ ;\n /*34b0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*34c0*/ MOV R20, R20 ;\n /*34d0*/ MOV R21, R21 ;\n /*34e0*/ MOV R20, R20 ;\n /*34f0*/ MOV R21, R21 ;\n /*3500*/ R2UR UR4, R18 ;\n /*3510*/ R2UR UR5, R19 ;\n /*3520*/ LDG.E R20, [R20.64] ;\n /*3530*/ LOP3.LUT R12, R12, R20, RZ, 0x3c, !PT ;\n /*3540*/ IADD3 R20, P0, R23, 0xd0, RZ ;\n /*3550*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*3560*/ MOV R20, R20 ;\n /*3570*/ MOV R21, R21 ;\n /*3580*/ MOV R20, R20 ;\n /*3590*/ MOV R21, R21 ;\n /*35a0*/ R2UR UR4, R18 ;\n /*35b0*/ R2UR UR5, R19 ;\n /*35c0*/ LDG.E R20, [R20.64] ;\n /*35d0*/ LOP3.LUT R25, R15, R20, RZ, 0x3c, !PT ;\n /*35e0*/ IADD3 R20, P0, R23, 0xd4, RZ ;\n /*35f0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*3600*/ MOV R20, R20 ;\n /*3610*/ MOV R21, R21 ;\n /*3620*/ MOV R20, R20 ;\n /*3630*/ MOV R21, R21 ;\n /*3640*/ R2UR UR4, R18 ;\n /*3650*/ R2UR UR5, R19 ;\n /*3660*/ LDG.E R20, [R20.64] ;\n /*3670*/ LOP3.LUT R20, R14, R20, RZ, 0x3c, !PT ;\n /*3680*/ IADD3 R14, P0, R23, 0xd8, RZ ;\n /*3690*/ IADD3.X R15, R11, RZ, RZ, P0, !PT ;\n /*36a0*/ MOV R14, R14 ;\n /*36b0*/ MOV R15, R15 ;\n /*36c0*/ MOV R14, R14 ;\n /*36d0*/ MOV R15, R15 ;\n /*36e0*/ R2UR UR4, R18 ;\n /*36f0*/ R2UR UR5, R19 ;\n /*3700*/ LDG.E R14, [R14.64] ;\n /*3710*/ LOP3.LUT R13, R13, R14, RZ, 0x3c, !PT ;\n /*3720*/ MOV R24, R24 ;\n /*3730*/ MOV R12, R12 ;\n /*3740*/ MOV R15, R25 ;\n /*3750*/ MOV R14, R20 ;\n /*3760*/ MOV R13, R13 ;\n.L_x_69:\n /*3770*/ BSYNC B2 ;\n.L_x_68:\n /*3780*/ MOV R20, 0x800 ;\n /*3790*/ SHF.L.U32 R20, R20, R22, RZ ;\n /*37a0*/ LOP3.LUT R20, R17, R20, RZ, 0xc0, !PT ;\n /*37b0*/ ISETP.EQ.AND P0, PT, R20, RZ, PT ;\n /*37c0*/ BSSY B2, `(.L_x_70) ;\n /*37d0*/ @P0 BRA `(.L_x_71) ;\n /*37e0*/ IADD3 R20, P0, R23, 0xdc, RZ ;\n /*37f0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*3800*/ MOV R20, R20 ;\n /*3810*/ MOV R21, R21 ;\n /*3820*/ MOV R20, R20 ;\n /*3830*/ MOV R21, R21 ;\n /*3840*/ R2UR UR4, R18 ;\n /*3850*/ R2UR UR5, R19 ;\n /*3860*/ LDG.E R20, [R20.64] ;\n /*3870*/ LOP3.LUT R24, R24, R20, RZ, 0x3c, !PT ;\n /*3880*/ IADD3 R20, P0, R23, 0xe0, RZ ;\n /*3890*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*38a0*/ MOV R20, R20 ;\n /*38b0*/ MOV R21, R21 ;\n /*38c0*/ MOV R20, R20 ;\n /*38d0*/ MOV R21, R21 ;\n /*38e0*/ R2UR UR4, R18 ;\n /*38f0*/ R2UR UR5, R19 ;\n /*3900*/ LDG.E R20, [R20.64] ;\n /*3910*/ LOP3.LUT R12, R12, R20, RZ, 0x3c, !PT ;\n /*3920*/ IADD3 R20, P0, R23, 0xe4, RZ ;\n /*3930*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*3940*/ MOV R20, R20 ;\n /*3950*/ MOV R21, R21 ;\n /*3960*/ MOV R20, R20 ;\n /*3970*/ MOV R21, R21 ;\n /*3980*/ R2UR UR4, R18 ;\n /*3990*/ R2UR UR5, R19 ;\n /*39a0*/ LDG.E R20, [R20.64] ;\n /*39b0*/ LOP3.LUT R25, R15, R20, RZ, 0x3c, !PT ;\n /*39c0*/ IADD3 R20, P0, R23, 0xe8, RZ ;\n /*39d0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*39e0*/ MOV R20, R20 ;\n /*39f0*/ MOV R21, R21 ;\n /*3a00*/ MOV R20, R20 ;\n /*3a10*/ MOV R21, R21 ;\n /*3a20*/ R2UR UR4, R18 ;\n /*3a30*/ R2UR UR5, R19 ;\n /*3a40*/ LDG.E R20, [R20.64] ;\n /*3a50*/ LOP3.LUT R20, R14, R20, RZ, 0x3c, !PT ;\n /*3a60*/ IADD3 R14, P0, R23, 0xec, RZ ;\n /*3a70*/ IADD3.X R15, R11, RZ, RZ, P0, !PT ;\n /*3a80*/ MOV R14, R14 ;\n /*3a90*/ MOV R15, R15 ;\n /*3aa0*/ MOV R14, R14 ;\n /*3ab0*/ MOV R15, R15 ;\n /*3ac0*/ R2UR UR4, R18 ;\n /*3ad0*/ R2UR UR5, R19 ;\n /*3ae0*/ LDG.E R14, [R14.64] ;\n /*3af0*/ LOP3.LUT R13, R13, R14, RZ, 0x3c, !PT ;\n /*3b00*/ MOV R24, R24 ;\n /*3b10*/ MOV R12, R12 ;\n /*3b20*/ MOV R15, R25 ;\n /*3b30*/ MOV R14, R20 ;\n /*3b40*/ MOV R13, R13 ;\n.L_x_71:\n /*3b50*/ BSYNC B2 ;\n.L_x_70:\n /*3b60*/ MOV R20, 0x1000 ;\n /*3b70*/ SHF.L.U32 R20, R20, R22, RZ ;\n /*3b80*/ LOP3.LUT R20, R17, R20, RZ, 0xc0, !PT ;\n /*3b90*/ ISETP.EQ.AND P0, PT, R20, RZ, PT ;\n /*3ba0*/ BSSY B2, `(.L_x_72) ;\n /*3bb0*/ @P0 BRA `(.L_x_73) ;\n /*3bc0*/ IADD3 R20, P0, R23, 0xf0, RZ ;\n /*3bd0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*3be0*/ MOV R20, R20 ;\n /*3bf0*/ MOV R21, R21 ;\n /*3c00*/ MOV R20, R20 ;\n /*3c10*/ MOV R21, R21 ;\n /*3c20*/ R2UR UR4, R18 ;\n /*3c30*/ R2UR UR5, R19 ;\n /*3c40*/ LDG.E R20, [R20.64] ;\n /*3c50*/ LOP3.LUT R24, R24, R20, RZ, 0x3c, !PT ;\n /*3c60*/ IADD3 R20, P0, R23, 0xf4, RZ ;\n /*3c70*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*3c80*/ MOV R20, R20 ;\n /*3c90*/ MOV R21, R21 ;\n /*3ca0*/ MOV R20, R20 ;\n /*3cb0*/ MOV R21, R21 ;\n /*3cc0*/ R2UR UR4, R18 ;\n /*3cd0*/ R2UR UR5, R19 ;\n /*3ce0*/ LDG.E R20, [R20.64] ;\n /*3cf0*/ LOP3.LUT R12, R12, R20, RZ, 0x3c, !PT ;\n /*3d00*/ IADD3 R20, P0, R23, 0xf8, RZ ;\n /*3d10*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*3d20*/ MOV R20, R20 ;\n /*3d30*/ MOV R21, R21 ;\n /*3d40*/ MOV R20, R20 ;\n /*3d50*/ MOV R21, R21 ;\n /*3d60*/ R2UR UR4, R18 ;\n /*3d70*/ R2UR UR5, R19 ;\n /*3d80*/ LDG.E R20, [R20.64] ;\n /*3d90*/ LOP3.LUT R25, R15, R20, RZ, 0x3c, !PT ;\n /*3da0*/ IADD3 R20, P0, R23, 0xfc, RZ ;\n /*3db0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*3dc0*/ MOV R20, R20 ;\n /*3dd0*/ MOV R21, R21 ;\n /*3de0*/ MOV R20, R20 ;\n /*3df0*/ MOV R21, R21 ;\n /*3e00*/ R2UR UR4, R18 ;\n /*3e10*/ R2UR UR5, R19 ;\n /*3e20*/ LDG.E R20, [R20.64] ;\n /*3e30*/ LOP3.LUT R20, R14, R20, RZ, 0x3c, !PT ;\n /*3e40*/ IADD3 R14, P0, R23, 0x100, RZ ;\n /*3e50*/ IADD3.X R15, R11, RZ, RZ, P0, !PT ;\n /*3e60*/ MOV R14, R14 ;\n /*3e70*/ MOV R15, R15 ;\n /*3e80*/ MOV R14, R14 ;\n /*3e90*/ MOV R15, R15 ;\n /*3ea0*/ R2UR UR4, R18 ;\n /*3eb0*/ R2UR UR5, R19 ;\n /*3ec0*/ LDG.E R14, [R14.64] ;\n /*3ed0*/ LOP3.LUT R13, R13, R14, RZ, 0x3c, !PT ;\n /*3ee0*/ MOV R24, R24 ;\n /*3ef0*/ MOV R12, R12 ;\n /*3f00*/ MOV R15, R25 ;\n /*3f10*/ MOV R14, R20 ;\n /*3f20*/ MOV R13, R13 ;\n.L_x_73:\n /*3f30*/ BSYNC B2 ;\n.L_x_72:\n /*3f40*/ MOV R20, 0x2000 ;\n /*3f50*/ SHF.L.U32 R20, R20, R22, RZ ;\n /*3f60*/ LOP3.LUT R20, R17, R20, RZ, 0xc0, !PT ;\n /*3f70*/ ISETP.EQ.AND P0, PT, R20, RZ, PT ;\n /*3f80*/ BSSY B2, `(.L_x_74) ;\n /*3f90*/ @P0 BRA `(.L_x_75) ;\n /*3fa0*/ IADD3 R20, P0, R23, 0x104, RZ ;\n /*3fb0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*3fc0*/ MOV R20, R20 ;\n /*3fd0*/ MOV R21, R21 ;\n /*3fe0*/ MOV R20, R20 ;\n /*3ff0*/ MOV R21, R21 ;\n /*4000*/ R2UR UR4, R18 ;\n /*4010*/ R2UR UR5, R19 ;\n /*4020*/ LDG.E R20, [R20.64] ;\n /*4030*/ LOP3.LUT R24, R24, R20, RZ, 0x3c, !PT ;\n /*4040*/ IADD3 R20, P0, R23, 0x108, RZ ;\n /*4050*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*4060*/ MOV R20, R20 ;\n /*4070*/ MOV R21, R21 ;\n /*4080*/ MOV R20, R20 ;\n /*4090*/ MOV R21, R21 ;\n /*40a0*/ R2UR UR4, R18 ;\n /*40b0*/ R2UR UR5, R19 ;\n /*40c0*/ LDG.E R20, [R20.64] ;\n /*40d0*/ LOP3.LUT R12, R12, R20, RZ, 0x3c, !PT ;\n /*40e0*/ IADD3 R20, P0, R23, 0x10c, RZ ;\n /*40f0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*4100*/ MOV R20, R20 ;\n /*4110*/ MOV R21, R21 ;\n /*4120*/ MOV R20, R20 ;\n /*4130*/ MOV R21, R21 ;\n /*4140*/ R2UR UR4, R18 ;\n /*4150*/ R2UR UR5, R19 ;\n /*4160*/ LDG.E R20, [R20.64] ;\n /*4170*/ LOP3.LUT R25, R15, R20, RZ, 0x3c, !PT ;\n /*4180*/ IADD3 R20, P0, R23, 0x110, RZ ;\n /*4190*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*41a0*/ MOV R20, R20 ;\n /*41b0*/ MOV R21, R21 ;\n /*41c0*/ MOV R20, R20 ;\n /*41d0*/ MOV R21, R21 ;\n /*41e0*/ R2UR UR4, R18 ;\n /*41f0*/ R2UR UR5, R19 ;\n /*4200*/ LDG.E R20, [R20.64] ;\n /*4210*/ LOP3.LUT R20, R14, R20, RZ, 0x3c, !PT ;\n /*4220*/ IADD3 R14, P0, R23, 0x114, RZ ;\n /*4230*/ IADD3.X R15, R11, RZ, RZ, P0, !PT ;\n /*4240*/ MOV R14, R14 ;\n /*4250*/ MOV R15, R15 ;\n /*4260*/ MOV R14, R14 ;\n /*4270*/ MOV R15, R15 ;\n /*4280*/ R2UR UR4, R18 ;\n /*4290*/ R2UR UR5, R19 ;\n /*42a0*/ LDG.E R14, [R14.64] ;\n /*42b0*/ LOP3.LUT R13, R13, R14, RZ, 0x3c, !PT ;\n /*42c0*/ MOV R24, R24 ;\n /*42d0*/ MOV R12, R12 ;\n /*42e0*/ MOV R15, R25 ;\n /*42f0*/ MOV R14, R20 ;\n /*4300*/ MOV R13, R13 ;\n.L_x_75:\n /*4310*/ BSYNC B2 ;\n.L_x_74:\n /*4320*/ MOV R20, 0x4000 ;\n /*4330*/ SHF.L.U32 R20, R20, R22, RZ ;\n /*4340*/ LOP3.LUT R20, R17, R20, RZ, 0xc0, !PT ;\n /*4350*/ ISETP.EQ.AND P0, PT, R20, RZ, PT ;\n /*4360*/ BSSY B2, `(.L_x_76) ;\n /*4370*/ @P0 BRA `(.L_x_77) ;\n /*4380*/ IADD3 R20, P0, R23, 0x118, RZ ;\n /*4390*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*43a0*/ MOV R20, R20 ;\n /*43b0*/ MOV R21, R21 ;\n /*43c0*/ MOV R20, R20 ;\n /*43d0*/ MOV R21, R21 ;\n /*43e0*/ R2UR UR4, R18 ;\n /*43f0*/ R2UR UR5, R19 ;\n /*4400*/ LDG.E R20, [R20.64] ;\n /*4410*/ LOP3.LUT R24, R24, R20, RZ, 0x3c, !PT ;\n /*4420*/ IADD3 R20, P0, R23, 0x11c, RZ ;\n /*4430*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*4440*/ MOV R20, R20 ;\n /*4450*/ MOV R21, R21 ;\n /*4460*/ MOV R20, R20 ;\n /*4470*/ MOV R21, R21 ;\n /*4480*/ R2UR UR4, R18 ;\n /*4490*/ R2UR UR5, R19 ;\n /*44a0*/ LDG.E R20, [R20.64] ;\n /*44b0*/ LOP3.LUT R12, R12, R20, RZ, 0x3c, !PT ;\n /*44c0*/ IADD3 R20, P0, R23, 0x120, RZ ;\n /*44d0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*44e0*/ MOV R20, R20 ;\n /*44f0*/ MOV R21, R21 ;\n /*4500*/ MOV R20, R20 ;\n /*4510*/ MOV R21, R21 ;\n /*4520*/ R2UR UR4, R18 ;\n /*4530*/ R2UR UR5, R19 ;\n /*4540*/ LDG.E R20, [R20.64] ;\n /*4550*/ LOP3.LUT R25, R15, R20, RZ, 0x3c, !PT ;\n /*4560*/ IADD3 R20, P0, R23, 0x124, RZ ;\n /*4570*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*4580*/ MOV R20, R20 ;\n /*4590*/ MOV R21, R21 ;\n /*45a0*/ MOV R20, R20 ;\n /*45b0*/ MOV R21, R21 ;\n /*45c0*/ R2UR UR4, R18 ;\n /*45d0*/ R2UR UR5, R19 ;\n /*45e0*/ LDG.E R20, [R20.64] ;\n /*45f0*/ LOP3.LUT R20, R14, R20, RZ, 0x3c, !PT ;\n /*4600*/ IADD3 R14, P0, R23, 0x128, RZ ;\n /*4610*/ IADD3.X R15, R11, RZ, RZ, P0, !PT ;\n /*4620*/ MOV R14, R14 ;\n /*4630*/ MOV R15, R15 ;\n /*4640*/ MOV R14, R14 ;\n /*4650*/ MOV R15, R15 ;\n /*4660*/ R2UR UR4, R18 ;\n /*4670*/ R2UR UR5, R19 ;\n /*4680*/ LDG.E R14, [R14.64] ;\n /*4690*/ LOP3.LUT R13, R13, R14, RZ, 0x3c, !PT ;\n /*46a0*/ MOV R24, R24 ;\n /*46b0*/ MOV R12, R12 ;\n /*46c0*/ MOV R15, R25 ;\n /*46d0*/ MOV R14, R20 ;\n /*46e0*/ MOV R13, R13 ;\n.L_x_77:\n /*46f0*/ BSYNC B2 ;\n.L_x_76:\n /*4700*/ MOV R20, 0x8000 ;\n /*4710*/ SHF.L.U32 R20, R20, R22, RZ ;\n /*4720*/ LOP3.LUT R20, R17, R20, RZ, 0xc0, !PT ;\n /*4730*/ ISETP.EQ.AND P0, PT, R20, RZ, PT ;\n /*4740*/ BSSY B2, `(.L_x_78) ;\n /*4750*/ @P0 BRA `(.L_x_79) ;\n /*4760*/ IADD3 R20, P0, R23, 0x12c, RZ ;\n /*4770*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*4780*/ MOV R20, R20 ;\n /*4790*/ MOV R21, R21 ;\n /*47a0*/ MOV R20, R20 ;\n /*47b0*/ MOV R21, R21 ;\n /*47c0*/ R2UR UR4, R18 ;\n /*47d0*/ R2UR UR5, R19 ;\n /*47e0*/ LDG.E R20, [R20.64] ;\n /*47f0*/ LOP3.LUT R24, R24, R20, RZ, 0x3c, !PT ;\n /*4800*/ IADD3 R20, P0, R23, 0x130, RZ ;\n /*4810*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*4820*/ MOV R20, R20 ;\n /*4830*/ MOV R21, R21 ;\n /*4840*/ MOV R20, R20 ;\n /*4850*/ MOV R21, R21 ;\n /*4860*/ R2UR UR4, R18 ;\n /*4870*/ R2UR UR5, R19 ;\n /*4880*/ LDG.E R20, [R20.64] ;\n /*4890*/ LOP3.LUT R12, R12, R20, RZ, 0x3c, !PT ;\n /*48a0*/ IADD3 R20, P0, R23, 0x134, RZ ;\n /*48b0*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*48c0*/ MOV R20, R20 ;\n /*48d0*/ MOV R21, R21 ;\n /*48e0*/ MOV R20, R20 ;\n /*48f0*/ MOV R21, R21 ;\n /*4900*/ R2UR UR4, R18 ;\n /*4910*/ R2UR UR5, R19 ;\n /*4920*/ LDG.E R20, [R20.64] ;\n /*4930*/ LOP3.LUT R25, R15, R20, RZ, 0x3c, !PT ;\n /*4940*/ IADD3 R20, P0, R23, 0x138, RZ ;\n /*4950*/ IADD3.X R21, R11, RZ, RZ, P0, !PT ;\n /*4960*/ MOV R20, R20 ;\n /*4970*/ MOV R21, R21 ;\n /*4980*/ MOV R20, R20 ;\n /*4990*/ MOV R21, R21 ;\n /*49a0*/ R2UR UR4, R18 ;\n /*49b0*/ R2UR UR5, R19 ;\n /*49c0*/ LDG.E R20, [R20.64] ;\n /*49d0*/ LOP3.LUT R20, R14, R20, RZ, 0x3c, !PT ;\n /*49e0*/ IADD3 R14, P0, R23, 0x13c, RZ ;\n /*49f0*/ IADD3.X R15, R11, RZ, RZ, P0, !PT ;\n /*4a00*/ MOV R14, R14 ;\n /*4a10*/ MOV R15, R15 ;\n /*4a20*/ MOV R14, R14 ;\n /*4a30*/ MOV R15, R15 ;\n /*4a40*/ R2UR UR4, R18 ;\n /*4a50*/ R2UR UR5, R19 ;\n /*4a60*/ LDG.E R14, [R14.64] ;\n /*4a70*/ LOP3.LUT R13, R13, R14, RZ, 0x3c, !PT ;\n /*4a80*/ MOV R24, R24 ;\n /*4a90*/ MOV R12, R12 ;\n /*4aa0*/ MOV R15, R25 ;\n /*4ab0*/ MOV R14, R20 ;\n /*4ac0*/ MOV R13, R13 ;\n.L_x_79:\n /*4ad0*/ BSYNC B2 ;\n.L_x_78:\n /*4ae0*/ IADD3 R22, R22, 0x10, RZ ;\n /*4af0*/ ISETP.NE.AND P0, PT, R22, 0x20, PT ;\n /*4b00*/ MOV R22, R22 ;\n /*4b10*/ @P0 BRA `(.L_x_80) ;\n /*4b20*/ IADD3 R16, R16, 0x1, RZ ;\n /*4b30*/ ISETP.LT.U32.AND P0, PT, R16, 0x5, PT ;\n /*4b40*/ MOV R16, R16 ;\n /*4b50*/ @P0 BRA `(.L_x_81) ;\n /*4b60*/ LOP3.LUT R20, R8, 0x3, RZ, 0xc0, !PT ;\n /*4b70*/ LOP3.LUT R21, R9, RZ, RZ, 0xc0, !PT ;\n /*4b80*/ IADD3 R16, P0, R5, 0x4, RZ ;\n /*4b90*/ IADD3.X R17, R6, RZ, RZ, P0, !PT ;\n /*4ba0*/ MOV R16, R16 ;\n /*4bb0*/ MOV R17, R17 ;\n /*4bc0*/ MOV R16, R16 ;\n /*4bd0*/ MOV R17, R17 ;\n /*4be0*/ R2UR UR4, R18 ;\n /*4bf0*/ R2UR UR5, R19 ;\n /*4c00*/ STG.E [R16.64], R24 ;\n /*4c10*/ IADD3 R16, P0, R5, 0x8, RZ ;\n /*4c20*/ IADD3.X R17, R6, RZ, RZ, P0, !PT ;\n /*4c30*/ MOV R16, R16 ;\n /*4c40*/ MOV R17, R17 ;\n /*4c50*/ MOV R16, R16 ;\n /*4c60*/ MOV R17, R17 ;\n /*4c70*/ R2UR UR4, R18 ;\n /*4c80*/ R2UR UR5, R19 ;\n /*4c90*/ STG.E [R16.64], R12 ;\n /*4ca0*/ IADD3 R16, P0, R5, 0xc, RZ ;\n /*4cb0*/ IADD3.X R17, R6, RZ, RZ, P0, !PT ;\n /*4cc0*/ MOV R16, R16 ;\n /*4cd0*/ MOV R17, R17 ;\n /*4ce0*/ MOV R16, R16 ;\n /*4cf0*/ MOV R17, R17 ;\n /*4d00*/ R2UR UR4, R18 ;\n /*4d10*/ R2UR UR5, R19 ;\n /*4d20*/ STG.E [R16.64], R15 ;\n /*4d30*/ IADD3 R16, P0, R5, 0x10, RZ ;\n /*4d40*/ IADD3.X R17, R6, RZ, RZ, P0, !PT ;\n /*4d50*/ MOV R16, R16 ;\n /*4d60*/ MOV R17, R17 ;\n /*4d70*/ MOV R16, R16 ;\n /*4d80*/ MOV R17, R17 ;\n /*4d90*/ R2UR UR4, R18 ;\n /*4da0*/ R2UR UR5, R19 ;\n /*4db0*/ STG.E [R16.64], R14 ;\n /*4dc0*/ IADD3 R14, P0, R5, 0x14, RZ ;\n /*4dd0*/ IADD3.X R15, R6, RZ, RZ, P0, !PT ;\n /*4de0*/ MOV R14, R14 ;\n /*4df0*/ MOV R15, R15 ;\n /*4e00*/ MOV R14, R14 ;\n /*4e10*/ MOV R15, R15 ;\n /*4e20*/ R2UR UR4, R18 ;\n /*4e30*/ R2UR UR5, R19 ;\n /*4e40*/ STG.E [R14.64], R13 ;\n /*4e50*/ IADD3 R10, R10, 0x1, RZ ;\n /*4e60*/ MOV R10, R10 ;\n /*4e70*/ MOV R11, R10 ;\n /*4e80*/ MOV R12, RZ ;\n /*4e90*/ ISETP.GT.U32.AND P0, PT, R20, R11, PT ;\n /*4ea0*/ ISETP.GT.U32.AND.EX P0, PT, R21, R12, PT, P0 ;\n /*4eb0*/ MOV R10, R10 ;\n /*4ec0*/ @P0 BRA `(.L_x_82) ;\n.L_x_47:\n /*4ed0*/ BSYNC B0 ;\n.L_x_46:\n /*4ee0*/ SHF.R.U64 R8, R8, 0x2, R9 ;\n /*4ef0*/ SHF.R.U32.HI R9, RZ, 0x2, R9 ;\n /*4f00*/ IADD3 R7, R7, 0x1, RZ ;\n /*4f10*/ ISETP.NE.U32.AND P0, PT, R8, RZ, PT ;\n /*4f20*/ ISETP.NE.AND.EX P0, PT, R9, RZ, PT, P0 ;\n /*4f30*/ MOV R8, R8 ;\n /*4f40*/ MOV R9, R9 ;\n /*4f50*/ MOV R7, R7 ;\n /*4f60*/ @P0 BRA `(.L_x_83) ;\n.L_x_45:\n /*4f70*/ BSYNC B1 ;\n.L_x_44:\n /*4f80*/ MOV R8, RZ ;\n /*4f90*/ IADD3 R2, P0, R5, 0x18, RZ ;\n /*4fa0*/ IADD3.X R3, R6, RZ, RZ, P0, !PT ;\n /*4fb0*/ MOV R2, R2 ;\n /*4fc0*/ MOV R3, R3 ;\n /*4fd0*/ MOV R2, R2 ;\n /*4fe0*/ MOV R3, R3 ;\n /*4ff0*/ R2UR UR4, R18 ;\n /*5000*/ R2UR UR5, R19 ;\n /*5010*/ MOV R9, RZ ;\n /*5020*/ STG.E.64 [R2.64], R8 ;\n /*5030*/ IADD3 R2, P0, R5, 0x20, RZ ;\n /*5040*/ IADD3.X R3, R6, RZ, RZ, P0, !PT ;\n /*5050*/ MOV R2, R2 ;\n /*5060*/ MOV R3, R3 ;\n /*5070*/ MOV R2, R2 ;\n /*5080*/ MOV R3, R3 ;\n /*5090*/ R2UR UR4, R18 ;\n /*50a0*/ R2UR UR5, R19 ;\n /*50b0*/ STG.E [R2.64], R8 ;\n /*50c0*/ CS2R R8, SRZ ;\n /*50d0*/ IADD3 R2, P0, R5, 0x28, RZ ;\n /*50e0*/ IADD3.X R3, R6, RZ, RZ, P0, !PT ;\n /*50f0*/ MOV R2, R2 ;\n /*5100*/ MOV R3, R3 ;\n /*5110*/ MOV R2, R2 ;\n /*5120*/ MOV R3, R3 ;\n /*5130*/ R2UR UR4, R18 ;\n /*5140*/ R2UR UR5, R19 ;\n /*5150*/ STG.E.64 [R2.64], R8 ;\n /*5160*/ EXIT ;\n.L_x_84:\n /*5170*/ BRA `(.L_x_84);\n /*5180*/ NOP;\n /*5190*/ NOP;\n /*51a0*/ NOP;\n /*51b0*/ NOP;\n /*51c0*/ NOP;\n /*51d0*/ NOP;\n /*51e0*/ NOP;\n /*51f0*/ NOP;\n.L_x_90:\n"},"hip":{"kind":"string","value":"\t.text\n\t.file\t\"cuda_code_004697.hip\"\n\t.globl\t_Z32__device_stub__initialize_randomP12hiprandStatem # -- Begin function _Z32__device_stub__initialize_randomP12hiprandStatem\n\t.p2align\t4, 0x90\n\t.type\t_Z32__device_stub__initialize_randomP12hiprandStatem,@function\n_Z32__device_stub__initialize_randomP12hiprandStatem: # @_Z32__device_stub__initialize_randomP12hiprandStatem\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$88, %rsp\n\t.cfi_def_cfa_offset 96\n\tmovq\t%rdi, 56(%rsp)\n\tmovq\t%rsi, 48(%rsp)\n\tleaq\t56(%rsp), %rax\n\tmovq\t%rax, 64(%rsp)\n\tleaq\t48(%rsp), %rax\n\tmovq\t%rax, 72(%rsp)\n\tleaq\t32(%rsp), %rdi\n\tleaq\t16(%rsp), %rsi\n\tleaq\t8(%rsp), %rdx\n\tmovq\t%rsp, %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t32(%rsp), %rsi\n\tmovl\t40(%rsp), %edx\n\tmovq\t16(%rsp), %rcx\n\tmovl\t24(%rsp), %r8d\n\tleaq\t64(%rsp), %r9\n\tmovl\t$_Z17initialize_randomP12hiprandStatem, %edi\n\tpushq\t(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t16(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$104, %rsp\n\t.cfi_adjust_cfa_offset -104\n\tretq\n.Lfunc_end0:\n\t.size\t_Z32__device_stub__initialize_randomP12hiprandStatem, .Lfunc_end0-_Z32__device_stub__initialize_randomP12hiprandStatem\n\t.cfi_endproc\n # -- End function\n\t.globl\t_Z36__device_stub__generate_sparse_inputPiPfP12hiprandStatei # -- Begin function _Z36__device_stub__generate_sparse_inputPiPfP12hiprandStatei\n\t.p2align\t4, 0x90\n\t.type\t_Z36__device_stub__generate_sparse_inputPiPfP12hiprandStatei,@function\n_Z36__device_stub__generate_sparse_inputPiPfP12hiprandStatei: # @_Z36__device_stub__generate_sparse_inputPiPfP12hiprandStatei\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$120, %rsp\n\t.cfi_def_cfa_offset 128\n\tmovq\t%rdi, 72(%rsp)\n\tmovq\t%rsi, 64(%rsp)\n\tmovq\t%rdx, 56(%rsp)\n\tmovl\t%ecx, 4(%rsp)\n\tleaq\t72(%rsp), %rax\n\tmovq\t%rax, 80(%rsp)\n\tleaq\t64(%rsp), %rax\n\tmovq\t%rax, 88(%rsp)\n\tleaq\t56(%rsp), %rax\n\tmovq\t%rax, 96(%rsp)\n\tleaq\t4(%rsp), %rax\n\tmovq\t%rax, 104(%rsp)\n\tleaq\t40(%rsp), %rdi\n\tleaq\t24(%rsp), %rsi\n\tleaq\t16(%rsp), %rdx\n\tleaq\t8(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t40(%rsp), %rsi\n\tmovl\t48(%rsp), %edx\n\tmovq\t24(%rsp), %rcx\n\tmovl\t32(%rsp), %r8d\n\tleaq\t80(%rsp), %r9\n\tmovl\t$_Z21generate_sparse_inputPiPfP12hiprandStatei, %edi\n\tpushq\t8(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t24(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$136, %rsp\n\t.cfi_adjust_cfa_offset -136\n\tretq\n.Lfunc_end1:\n\t.size\t_Z36__device_stub__generate_sparse_inputPiPfP12hiprandStatei, .Lfunc_end1-_Z36__device_stub__generate_sparse_inputPiPfP12hiprandStatei\n\t.cfi_endproc\n # -- End function\n\t.globl\t_Z40__device_stub__sparse_convolution_kernelPKiPKfiS2_Pfi # -- Begin function _Z40__device_stub__sparse_convolution_kernelPKiPKfiS2_Pfi\n\t.p2align\t4, 0x90\n\t.type\t_Z40__device_stub__sparse_convolution_kernelPKiPKfiS2_Pfi,@function\n_Z40__device_stub__sparse_convolution_kernelPKiPKfiS2_Pfi: # @_Z40__device_stub__sparse_convolution_kernelPKiPKfiS2_Pfi\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$152, %rsp\n\t.cfi_def_cfa_offset 160\n\tmovq\t%rdi, 88(%rsp)\n\tmovq\t%rsi, 80(%rsp)\n\tmovl\t%edx, 12(%rsp)\n\tmovq\t%rcx, 72(%rsp)\n\tmovq\t%r8, 64(%rsp)\n\tmovl\t%r9d, 8(%rsp)\n\tleaq\t88(%rsp), %rax\n\tmovq\t%rax, 96(%rsp)\n\tleaq\t80(%rsp), %rax\n\tmovq\t%rax, 104(%rsp)\n\tleaq\t12(%rsp), %rax\n\tmovq\t%rax, 112(%rsp)\n\tleaq\t72(%rsp), %rax\n\tmovq\t%rax, 120(%rsp)\n\tleaq\t64(%rsp), %rax\n\tmovq\t%rax, 128(%rsp)\n\tleaq\t8(%rsp), %rax\n\tmovq\t%rax, 136(%rsp)\n\tleaq\t48(%rsp), %rdi\n\tleaq\t32(%rsp), %rsi\n\tleaq\t24(%rsp), %rdx\n\tleaq\t16(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t48(%rsp), %rsi\n\tmovl\t56(%rsp), %edx\n\tmovq\t32(%rsp), %rcx\n\tmovl\t40(%rsp), %r8d\n\tleaq\t96(%rsp), %r9\n\tmovl\t$_Z25sparse_convolution_kernelPKiPKfiS2_Pfi, %edi\n\tpushq\t16(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t32(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$168, %rsp\n\t.cfi_adjust_cfa_offset -168\n\tretq\n.Lfunc_end2:\n\t.size\t_Z40__device_stub__sparse_convolution_kernelPKiPKfiS2_Pfi, .Lfunc_end2-_Z40__device_stub__sparse_convolution_kernelPKiPKfiS2_Pfi\n\t.cfi_endproc\n # -- End function\n\t.globl\tmain # -- Begin function main\n\t.p2align\t4, 0x90\n\t.type\tmain,@function\nmain: # @main\n.Lfunc_begin0:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception0\n# %bb.0:\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 16\n\tsubq\t$272, %rsp # imm = 0x110\n\t.cfi_def_cfa_offset 288\n\t.cfi_offset %rbx, -16\n\t.cfi_escape 0x2e, 0x00\n\tleaq\t80(%rsp), %rdi\n\tmovl\t$49152, %esi # imm = 0xC000\n\tcallq\thipMalloc\n\tmovabsq\t$4294967300, %rdi # imm = 0x100000004\n\tleaq\t252(%rdi), %rdx\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %esi\n\tmovl\t$1, %ecx\n\txorl\t%r8d, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipPushCallConfiguration\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_2\n# %bb.1:\n\tmovq\t80(%rsp), %rbx\n\t.cfi_escape 0x2e, 0x00\n\txorl\t%edi, %edi\n\tcallq\ttime\n\tmovq\t%rbx, 160(%rsp)\n\tmovq\t%rax, 128(%rsp)\n\tleaq\t160(%rsp), %rax\n\tmovq\t%rax, (%rsp)\n\tleaq\t128(%rsp), %rax\n\tmovq\t%rax, 8(%rsp)\n\t.cfi_escape 0x2e, 0x00\n\tleaq\t224(%rsp), %rdi\n\tleaq\t192(%rsp), %rsi\n\tleaq\t64(%rsp), %rdx\n\tleaq\t48(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t224(%rsp), %rsi\n\tmovl\t232(%rsp), %edx\n\tmovq\t192(%rsp), %rcx\n\tmovl\t200(%rsp), %r8d\n\t.cfi_escape 0x2e, 0x10\n\tmovq\t%rsp, %r9\n\tmovl\t$_Z17initialize_randomP12hiprandStatem, %edi\n\tpushq\t48(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t72(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$16, %rsp\n\t.cfi_adjust_cfa_offset -16\n.LBB3_2:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipDeviceSynchronize\n\t.cfi_escape 0x2e, 0x00\n\tleaq\t224(%rsp), %rdi\n\tmovl\t$1024, %esi # imm = 0x400\n\tcallq\t_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em\n.Ltmp0:\n\t.cfi_escape 0x2e, 0x00\n\tleaq\t192(%rsp), %rdi\n\tmovl\t$1024, %esi # imm = 0x400\n\tcallq\t_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2Em\n.Ltmp1:\n# %bb.3:\n.Ltmp3:\n\t.cfi_escape 0x2e, 0x00\n\tmovabsq\t$4294967300, %rdi # imm = 0x100000004\n\tmovabsq\t$4294967552, %rdx # imm = 0x100000100\n\tmovl\t$1, %esi\n\tmovl\t$1, %ecx\n\txorl\t%r8d, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipPushCallConfiguration\n.Ltmp4:\n# %bb.4:\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_7\n# %bb.5:\n\tmovq\t232(%rsp), %rax\n\tmovq\t200(%rsp), %rcx\n\tmovq\t80(%rsp), %rdx\n\tmovq\t%rax, 64(%rsp)\n\tmovq\t%rcx, 48(%rsp)\n\tmovq\t%rdx, 112(%rsp)\n\tmovl\t$1024, 88(%rsp) # imm = 0x400\n\tleaq\t64(%rsp), %rax\n\tmovq\t%rax, (%rsp)\n\tleaq\t48(%rsp), %rax\n\tmovq\t%rax, 8(%rsp)\n\tleaq\t112(%rsp), %rax\n\tmovq\t%rax, 16(%rsp)\n\tleaq\t88(%rsp), %rax\n\tmovq\t%rax, 24(%rsp)\n.Ltmp5:\n\t.cfi_escape 0x2e, 0x00\n\tleaq\t160(%rsp), %rdi\n\tleaq\t128(%rsp), %rsi\n\tleaq\t104(%rsp), %rdx\n\tleaq\t96(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n.Ltmp6:\n# %bb.6:\n\tmovq\t160(%rsp), %rsi\n\tmovl\t168(%rsp), %edx\n\tmovq\t128(%rsp), %rcx\n\tmovl\t136(%rsp), %r8d\n.Ltmp7:\n\t.cfi_escape 0x2e, 0x10\n\tmovq\t%rsp, %r9\n\tmovl\t$_Z21generate_sparse_inputPiPfP12hiprandStatei, %edi\n\tpushq\t96(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t112(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$16, %rsp\n\t.cfi_adjust_cfa_offset -16\n.Ltmp8:\n.LBB3_7:\n.Ltmp9:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipDeviceSynchronize\n.Ltmp10:\n# %bb.8:\n\tmovl\t$1065353216, (%rsp) # imm = 0x3F800000\n.Ltmp12:\n\t.cfi_escape 0x2e, 0x00\n\tleaq\t160(%rsp), %rdi\n\tmovq\t%rsp, %rdx\n\tmovl\t$268435456, %esi # imm = 0x10000000\n\tcallq\t_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2EmRKf\n.Ltmp13:\n# %bb.9:\n\tmovl\t$0, (%rsp)\n.Ltmp15:\n\t.cfi_escape 0x2e, 0x00\n\tleaq\t128(%rsp), %rdi\n\tmovq\t%rsp, %rdx\n\tmovl\t$268435456, %esi # imm = 0x10000000\n\tcallq\t_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2EmRKf\n.Ltmp16:\n# %bb.10:\n.Ltmp18:\n\t.cfi_escape 0x2e, 0x00\n\tmovabsq\t$4294967300, %rdi # imm = 0x100000004\n\tmovabsq\t$4294967552, %rdx # imm = 0x100000100\n\tmovl\t$1024, %r8d # imm = 0x400\n\tmovl\t$1, %esi\n\tmovl\t$1, %ecx\n\txorl\t%r9d, %r9d\n\tcallq\t__hipPushCallConfiguration\n.Ltmp19:\n# %bb.11:\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_14\n# %bb.12:\n\tmovq\t232(%rsp), %rax\n\tmovq\t200(%rsp), %rcx\n\tmovq\t168(%rsp), %rdx\n\tmovq\t136(%rsp), %rsi\n\tmovq\t%rax, 112(%rsp)\n\tmovq\t%rcx, 104(%rsp)\n\tmovl\t$1024, 124(%rsp) # imm = 0x400\n\tmovq\t%rdx, 96(%rsp)\n\tmovq\t%rsi, 88(%rsp)\n\tmovl\t$16384, 120(%rsp) # imm = 0x4000\n\tleaq\t112(%rsp), %rax\n\tmovq\t%rax, (%rsp)\n\tleaq\t104(%rsp), %rax\n\tmovq\t%rax, 8(%rsp)\n\tleaq\t124(%rsp), %rax\n\tmovq\t%rax, 16(%rsp)\n\tleaq\t96(%rsp), %rax\n\tmovq\t%rax, 24(%rsp)\n\tleaq\t88(%rsp), %rax\n\tmovq\t%rax, 32(%rsp)\n\tleaq\t120(%rsp), %rax\n\tmovq\t%rax, 40(%rsp)\n.Ltmp20:\n\t.cfi_escape 0x2e, 0x00\n\tleaq\t64(%rsp), %rdi\n\tleaq\t48(%rsp), %rsi\n\tleaq\t264(%rsp), %rdx\n\tleaq\t256(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n.Ltmp21:\n# %bb.13:\n\tmovq\t64(%rsp), %rsi\n\tmovl\t72(%rsp), %edx\n\tmovq\t48(%rsp), %rcx\n\tmovl\t56(%rsp), %r8d\n.Ltmp22:\n\t.cfi_escape 0x2e, 0x10\n\tmovq\t%rsp, %r9\n\tmovl\t$_Z25sparse_convolution_kernelPKiPKfiS2_Pfi, %edi\n\tpushq\t256(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t272(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$16, %rsp\n\t.cfi_adjust_cfa_offset -16\n.Ltmp23:\n.LBB3_14:\n.Ltmp24:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipDeviceSynchronize\n.Ltmp25:\n# %bb.15:\n.Ltmp27:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipGetLastError\n.Ltmp28:\n# %bb.16:\n\tmovl\t%eax, %ebx\n\ttestl\t%eax, %eax\n\tje\t.LBB3_45\n# %bb.17:\n.Ltmp29:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$12, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp30:\n# %bb.18:\n.Ltmp31:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%ebx, %edi\n\tcallq\thipGetErrorString\n.Ltmp32:\n# %bb.19:\n\ttestq\t%rax, %rax\n\tje\t.LBB3_20\n# %bb.25:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tmovq\t%rax, %rbx\n\tcallq\tstrlen\n.Ltmp33:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rbx, %rsi\n\tmovq\t%rax, %rdx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp34:\n\tjmp\t.LBB3_26\n.LBB3_45:\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, 8(%rsp)\n\tmovq\t$0, 24(%rsp)\n\tmovq\t136(%rsp), %rdx\n\tmovq\t152(%rsp), %rbx\n\tleaq\t(%rdx,%rbx,4), %rcx\n.Ltmp48:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rsp, %rdi\n\tmovq\t%rbx, %rsi\n\tmovq\t%rdi, %r8\n\tcallq\t_ZN6thrust6detail11vector_baseIfSaIfEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKfEEEEEEvmT_SA_RNS0_18contiguous_storageIfS2_EE\n.Ltmp49:\n# %bb.46:\n\tmovq\t%rbx, 24(%rsp)\n.Ltmp51:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cout, %edi\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$29, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp52:\n# %bb.47:\n\tmovq\t8(%rsp), %rax\n\tmovss\t(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero\n\tcvtss2sd\t%xmm0, %xmm0\n.Ltmp53:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cout, %edi\n\tcallq\t_ZNSo9_M_insertIdEERSoT_\n.Ltmp54:\n# %bb.48:\n.Ltmp55:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$1, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp56:\n# %bb.49:\n\tmovq\t8(%rsp), %rax\n\tmovss\t4(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero\n\tcvtss2sd\t%xmm0, %xmm0\n.Ltmp57:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cout, %edi\n\tcallq\t_ZNSo9_M_insertIdEERSoT_\n.Ltmp58:\n# %bb.50:\n.Ltmp59:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$1, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp60:\n# %bb.51:\n\tmovq\t8(%rsp), %rax\n\tmovss\t8(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero\n\tcvtss2sd\t%xmm0, %xmm0\n.Ltmp61:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cout, %edi\n\tcallq\t_ZNSo9_M_insertIdEERSoT_\n.Ltmp62:\n# %bb.52:\n.Ltmp63:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$1, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp64:\n# %bb.53:\n\tmovq\t8(%rsp), %rax\n\tmovss\t12(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero\n\tcvtss2sd\t%xmm0, %xmm0\n.Ltmp65:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cout, %edi\n\tcallq\t_ZNSo9_M_insertIdEERSoT_\n.Ltmp66:\n# %bb.54:\n.Ltmp67:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$1, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp68:\n# %bb.55:\n\tmovq\t8(%rsp), %rax\n\tmovss\t16(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero\n\tcvtss2sd\t%xmm0, %xmm0\n.Ltmp69:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cout, %edi\n\tcallq\t_ZNSo9_M_insertIdEERSoT_\n.Ltmp70:\n# %bb.56:\n.Ltmp71:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$1, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp72:\n# %bb.57:\n\tmovq\t8(%rsp), %rax\n\tmovss\t20(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero\n\tcvtss2sd\t%xmm0, %xmm0\n.Ltmp73:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cout, %edi\n\tcallq\t_ZNSo9_M_insertIdEERSoT_\n.Ltmp74:\n# %bb.58:\n.Ltmp75:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$1, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp76:\n# %bb.59:\n\tmovq\t8(%rsp), %rax\n\tmovss\t24(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero\n\tcvtss2sd\t%xmm0, %xmm0\n.Ltmp77:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cout, %edi\n\tcallq\t_ZNSo9_M_insertIdEERSoT_\n.Ltmp78:\n# %bb.60:\n.Ltmp79:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$1, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp80:\n# %bb.61:\n\tmovq\t8(%rsp), %rax\n\tmovss\t28(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero\n\tcvtss2sd\t%xmm0, %xmm0\n.Ltmp81:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cout, %edi\n\tcallq\t_ZNSo9_M_insertIdEERSoT_\n.Ltmp82:\n# %bb.62:\n.Ltmp83:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$1, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp84:\n# %bb.63:\n\tmovq\t8(%rsp), %rax\n\tmovss\t32(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero\n\tcvtss2sd\t%xmm0, %xmm0\n.Ltmp85:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cout, %edi\n\tcallq\t_ZNSo9_M_insertIdEERSoT_\n.Ltmp86:\n# %bb.64:\n.Ltmp87:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$1, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp88:\n# %bb.65:\n\tmovq\t8(%rsp), %rax\n\tmovss\t36(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero\n\tcvtss2sd\t%xmm0, %xmm0\n.Ltmp89:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cout, %edi\n\tcallq\t_ZNSo9_M_insertIdEERSoT_\n.Ltmp90:\n# %bb.66:\n.Ltmp91:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$1, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp92:\n# %bb.67:\n\tmovq\t_ZSt4cout(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tmovq\t_ZSt4cout+240(%rax), %rbx\n\ttestq\t%rbx, %rbx\n\tje\t.LBB3_68\n# %bb.70:\n\tcmpb\t$0, 56(%rbx)\n\tje\t.LBB3_72\n# %bb.71:\n\tmovzbl\t67(%rbx), %eax\n\tjmp\t.LBB3_74\n.LBB3_20:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tleaq\t_ZSt4cerr(%rax), %rdi\n\tmovl\t_ZSt4cerr+32(%rax), %esi\n\torl\t$1, %esi\n.Ltmp35:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\t_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate\n.Ltmp36:\n.LBB3_26:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tmovq\t_ZSt4cerr+240(%rax), %rbx\n\ttestq\t%rbx, %rbx\n\tje\t.LBB3_27\n# %bb.29:\n\tcmpb\t$0, 56(%rbx)\n\tje\t.LBB3_31\n# %bb.30:\n\tmovzbl\t67(%rbx), %eax\n\tjmp\t.LBB3_33\n.LBB3_31:\n.Ltmp37:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZNKSt5ctypeIcE13_M_widen_initEv\n.Ltmp38:\n# %bb.32:\n\tmovq\t(%rbx), %rax\n.Ltmp39:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tmovl\t$10, %esi\n\tcallq\t*48(%rax)\n.Ltmp40:\n.LBB3_33:\n.Ltmp41:\n\t.cfi_escape 0x2e, 0x00\n\tmovsbl\t%al, %esi\n\tmovl\t$_ZSt4cerr, %edi\n\tcallq\t_ZNSo3putEc\n.Ltmp42:\n# %bb.34:\n\tmovl\t$-1, %ebx\n.Ltmp43:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZNSo5flushEv\n.Ltmp44:\n\tjmp\t.LBB3_35\n.LBB3_72:\n.Ltmp94:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZNKSt5ctypeIcE13_M_widen_initEv\n.Ltmp95:\n# %bb.73:\n\tmovq\t(%rbx), %rax\n.Ltmp96:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tmovl\t$10, %esi\n\tcallq\t*48(%rax)\n.Ltmp97:\n.LBB3_74:\n.Ltmp98:\n\t.cfi_escape 0x2e, 0x00\n\tmovsbl\t%al, %esi\n\tmovl\t$_ZSt4cout, %edi\n\tcallq\t_ZNSo3putEc\n.Ltmp99:\n# %bb.75:\n.Ltmp100:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZNSo5flushEv\n.Ltmp101:\n# %bb.76:\n\tmovq\t80(%rsp), %rdi\n.Ltmp102:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipFree\n.Ltmp103:\n# %bb.77:\n\tcmpq\t$0, 16(%rsp)\n\tje\t.LBB3_79\n# %bb.78:\n\tmovq\t8(%rsp), %rdi\n\t.cfi_escape 0x2e, 0x00\n\tcallq\t_ZdlPv\n.LBB3_79:\n\txorl\t%ebx, %ebx\n.LBB3_35:\n\tmovq\t144(%rsp), %rdx\n\ttestq\t%rdx, %rdx\n\tje\t.LBB3_37\n# %bb.36:\n\tmovq\t128(%rsp), %rax\n\tmovq\t136(%rsp), %rsi\n\tshlq\t$2, %rdx\n\tmovq\t8(%rax), %rdi\n.Ltmp104:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$4, %ecx\n\tcallq\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm\n.Ltmp105:\n.LBB3_37:\n\tmovq\t176(%rsp), %rdx\n\ttestq\t%rdx, %rdx\n\tje\t.LBB3_39\n# %bb.38:\n\tmovq\t160(%rsp), %rax\n\tmovq\t168(%rsp), %rsi\n\tshlq\t$2, %rdx\n\tmovq\t8(%rax), %rdi\n.Ltmp107:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$4, %ecx\n\tcallq\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm\n.Ltmp108:\n.LBB3_39:\n\tmovq\t208(%rsp), %rdx\n\ttestq\t%rdx, %rdx\n\tje\t.LBB3_41\n# %bb.40:\n\tmovq\t192(%rsp), %rax\n\tmovq\t200(%rsp), %rsi\n\tshlq\t$2, %rdx\n\tmovq\t8(%rax), %rdi\n.Ltmp110:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$4, %ecx\n\tcallq\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm\n.Ltmp111:\n.LBB3_41:\n\tmovq\t240(%rsp), %rdx\n\ttestq\t%rdx, %rdx\n\tje\t.LBB3_43\n# %bb.42:\n\tmovq\t224(%rsp), %rax\n\tmovq\t232(%rsp), %rsi\n\tshlq\t$2, %rdx\n\tmovq\t8(%rax), %rdi\n.Ltmp113:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$4, %ecx\n\tcallq\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm\n.Ltmp114:\n.LBB3_43:\n\tmovl\t%ebx, %eax\n\taddq\t$272, %rsp # imm = 0x110\n\t.cfi_def_cfa_offset 16\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB3_27:\n\t.cfi_def_cfa_offset 288\n.Ltmp45:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\t_ZSt16__throw_bad_castv\n.Ltmp46:\n# %bb.28:\n.LBB3_68:\n.Ltmp116:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\t_ZSt16__throw_bad_castv\n.Ltmp117:\n# %bb.69:\n.LBB3_82:\n.Ltmp50:\n\tjmp\t.LBB3_83\n.LBB3_88:\n.Ltmp115:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t__clang_call_terminate\n.LBB3_87:\n.Ltmp112:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t__clang_call_terminate\n.LBB3_86:\n.Ltmp109:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t__clang_call_terminate\n.LBB3_85:\n.Ltmp106:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t__clang_call_terminate\n.LBB3_24:\n.Ltmp17:\n\tmovq\t%rax, %rbx\n\tjmp\t.LBB3_92\n.LBB3_23:\n.Ltmp14:\n\tmovq\t%rax, %rbx\n\tjmp\t.LBB3_93\n.LBB3_21:\n.Ltmp2:\n\tmovq\t%rax, %rbx\n\tjmp\t.LBB3_94\n.LBB3_80:\n.Ltmp118:\n\tjmp\t.LBB3_83\n.LBB3_89:\n.Ltmp26:\n\tjmp\t.LBB3_90\n.LBB3_22:\n.Ltmp11:\n\tmovq\t%rax, %rbx\n\tjmp\t.LBB3_93\n.LBB3_44:\n.Ltmp47:\n.LBB3_90:\n\tmovq\t%rax, %rbx\n\tjmp\t.LBB3_91\n.LBB3_81:\n.Ltmp93:\n.LBB3_83:\n\tmovq\t%rax, %rbx\n\tcmpq\t$0, 16(%rsp)\n\tje\t.LBB3_91\n# %bb.84:\n\tmovq\t8(%rsp), %rdi\n\t.cfi_escape 0x2e, 0x00\n\tcallq\t_ZdlPv\n.LBB3_91:\n\t.cfi_escape 0x2e, 0x00\n\tleaq\t128(%rsp), %rdi\n\tcallq\t_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEED2Ev\n.LBB3_92:\n\t.cfi_escape 0x2e, 0x00\n\tleaq\t160(%rsp), %rdi\n\tcallq\t_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEED2Ev\n.LBB3_93:\n\t.cfi_escape 0x2e, 0x00\n\tleaq\t192(%rsp), %rdi\n\tcallq\t_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEED2Ev\n.LBB3_94:\n\t.cfi_escape 0x2e, 0x00\n\tleaq\t224(%rsp), %rdi\n\tcallq\t_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tcallq\t_Unwind_Resume@PLT\n.Lfunc_end3:\n\t.size\tmain, .Lfunc_end3-main\n\t.cfi_endproc\n\t.section\t.gcc_except_table,\"a\",@progbits\n\t.p2align\t2, 0x0\nGCC_except_table3:\n.Lexception0:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t3 # @TType Encoding = udata4\n\t.uleb128 .Lttbase0-.Lttbaseref0\n.Lttbaseref0:\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end0-.Lcst_begin0\n.Lcst_begin0:\n\t.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<\n\t.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<\n\t.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1\n\t.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<\n\t.uleb128 .Ltmp10-.Ltmp3 # Call between .Ltmp3 and .Ltmp10\n\t.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 4 <<\n\t.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13\n\t.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 5 <<\n\t.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16\n\t.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 6 <<\n\t.uleb128 .Ltmp25-.Ltmp18 # Call between .Ltmp18 and .Ltmp25\n\t.uleb128 .Ltmp26-.Lfunc_begin0 # jumps to .Ltmp26\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 7 <<\n\t.uleb128 .Ltmp34-.Ltmp27 # Call between .Ltmp27 and .Ltmp34\n\t.uleb128 .Ltmp47-.Lfunc_begin0 # jumps to .Ltmp47\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp48-.Lfunc_begin0 # >> Call Site 8 <<\n\t.uleb128 .Ltmp49-.Ltmp48 # Call between .Ltmp48 and .Ltmp49\n\t.uleb128 .Ltmp50-.Lfunc_begin0 # jumps to .Ltmp50\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp51-.Lfunc_begin0 # >> Call Site 9 <<\n\t.uleb128 .Ltmp52-.Ltmp51 # Call between .Ltmp51 and .Ltmp52\n\t.uleb128 .Ltmp118-.Lfunc_begin0 # jumps to .Ltmp118\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp53-.Lfunc_begin0 # >> Call Site 10 <<\n\t.uleb128 .Ltmp92-.Ltmp53 # Call between .Ltmp53 and .Ltmp92\n\t.uleb128 .Ltmp93-.Lfunc_begin0 # jumps to .Ltmp93\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp35-.Lfunc_begin0 # >> Call Site 11 <<\n\t.uleb128 .Ltmp44-.Ltmp35 # Call between .Ltmp35 and .Ltmp44\n\t.uleb128 .Ltmp47-.Lfunc_begin0 # jumps to .Ltmp47\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp94-.Lfunc_begin0 # >> Call Site 12 <<\n\t.uleb128 .Ltmp103-.Ltmp94 # Call between .Ltmp94 and .Ltmp103\n\t.uleb128 .Ltmp118-.Lfunc_begin0 # jumps to .Ltmp118\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp104-.Lfunc_begin0 # >> Call Site 13 <<\n\t.uleb128 .Ltmp105-.Ltmp104 # Call between .Ltmp104 and .Ltmp105\n\t.uleb128 .Ltmp106-.Lfunc_begin0 # jumps to .Ltmp106\n\t.byte\t1 # On action: 1\n\t.uleb128 .Ltmp107-.Lfunc_begin0 # >> Call Site 14 <<\n\t.uleb128 .Ltmp108-.Ltmp107 # Call between .Ltmp107 and .Ltmp108\n\t.uleb128 .Ltmp109-.Lfunc_begin0 # jumps to .Ltmp109\n\t.byte\t1 # On action: 1\n\t.uleb128 .Ltmp110-.Lfunc_begin0 # >> Call Site 15 <<\n\t.uleb128 .Ltmp111-.Ltmp110 # Call between .Ltmp110 and .Ltmp111\n\t.uleb128 .Ltmp112-.Lfunc_begin0 # jumps to .Ltmp112\n\t.byte\t1 # On action: 1\n\t.uleb128 .Ltmp113-.Lfunc_begin0 # >> Call Site 16 <<\n\t.uleb128 .Ltmp114-.Ltmp113 # Call between .Ltmp113 and .Ltmp114\n\t.uleb128 .Ltmp115-.Lfunc_begin0 # jumps to .Ltmp115\n\t.byte\t1 # On action: 1\n\t.uleb128 .Ltmp45-.Lfunc_begin0 # >> Call Site 17 <<\n\t.uleb128 .Ltmp46-.Ltmp45 # Call between .Ltmp45 and .Ltmp46\n\t.uleb128 .Ltmp47-.Lfunc_begin0 # jumps to .Ltmp47\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp116-.Lfunc_begin0 # >> Call Site 18 <<\n\t.uleb128 .Ltmp117-.Ltmp116 # Call between .Ltmp116 and .Ltmp117\n\t.uleb128 .Ltmp118-.Lfunc_begin0 # jumps to .Ltmp118\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp117-.Lfunc_begin0 # >> Call Site 19 <<\n\t.uleb128 .Lfunc_end3-.Ltmp117 # Call between .Ltmp117 and .Lfunc_end3\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n.Lcst_end0:\n\t.byte\t1 # >> Action Record 1 <<\n # Catch TypeInfo 1\n\t.byte\t0 # No further actions\n\t.p2align\t2, 0x0\n # >> Catch TypeInfos <<\n\t.long\t0 # TypeInfo 1\n.Lttbase0:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text._ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEED2Ev,\"axG\",@progbits,_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEED2Ev,comdat\n\t.weak\t_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEED2Ev # -- Begin function _ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEED2Ev\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEED2Ev,@function\n_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEED2Ev: # @_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEED2Ev\n.Lfunc_begin1:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception1\n# %bb.0:\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 16\n\t.cfi_offset %rbx, -16\n\tmovq\t16(%rdi), %rdx\n\ttestq\t%rdx, %rdx\n\tje\t.LBB4_3\n# %bb.1:\n\tmovq\t%rdi, %rbx\n\tmovq\t(%rdi), %rax\n\tmovq\t8(%rdi), %rsi\n\tshlq\t$2, %rdx\n\tmovq\t8(%rax), %rdi\n.Ltmp119:\n\tmovl\t$4, %ecx\n\tcallq\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm\n.Ltmp120:\n# %bb.2:\n\taddq\t$8, %rbx\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, (%rbx)\n.LBB4_3:\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB4_4:\n\t.cfi_def_cfa_offset 16\n.Ltmp121:\n\tmovq\t%rax, %rdi\n\tcallq\t__clang_call_terminate\n.Lfunc_end4:\n\t.size\t_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEED2Ev, .Lfunc_end4-_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEED2Ev\n\t.cfi_endproc\n\t.section\t.gcc_except_table._ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEED2Ev,\"aG\",@progbits,_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEED2Ev,comdat\n\t.p2align\t2, 0x0\nGCC_except_table4:\n.Lexception1:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t3 # @TType Encoding = udata4\n\t.uleb128 .Lttbase1-.Lttbaseref1\n.Lttbaseref1:\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end1-.Lcst_begin1\n.Lcst_begin1:\n\t.uleb128 .Ltmp119-.Lfunc_begin1 # >> Call Site 1 <<\n\t.uleb128 .Ltmp120-.Ltmp119 # Call between .Ltmp119 and .Ltmp120\n\t.uleb128 .Ltmp121-.Lfunc_begin1 # jumps to .Ltmp121\n\t.byte\t1 # On action: 1\n.Lcst_end1:\n\t.byte\t1 # >> Action Record 1 <<\n # Catch TypeInfo 1\n\t.byte\t0 # No further actions\n\t.p2align\t2, 0x0\n # >> Catch TypeInfos <<\n\t.long\t0 # TypeInfo 1\n.Lttbase1:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text._ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev,\"axG\",@progbits,_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev,comdat\n\t.weak\t_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev # -- Begin function _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev,@function\n_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev: # @_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev\n.Lfunc_begin2:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception2\n# %bb.0:\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 16\n\t.cfi_offset %rbx, -16\n\tmovq\t16(%rdi), %rdx\n\ttestq\t%rdx, %rdx\n\tje\t.LBB5_3\n# %bb.1:\n\tmovq\t%rdi, %rbx\n\tmovq\t(%rdi), %rax\n\tmovq\t8(%rdi), %rsi\n\tshlq\t$2, %rdx\n\tmovq\t8(%rax), %rdi\n.Ltmp122:\n\tmovl\t$4, %ecx\n\tcallq\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm\n.Ltmp123:\n# %bb.2:\n\taddq\t$8, %rbx\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, (%rbx)\n.LBB5_3:\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB5_4:\n\t.cfi_def_cfa_offset 16\n.Ltmp124:\n\tmovq\t%rax, %rdi\n\tcallq\t__clang_call_terminate\n.Lfunc_end5:\n\t.size\t_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev, .Lfunc_end5-_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev\n\t.cfi_endproc\n\t.section\t.gcc_except_table._ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev,\"aG\",@progbits,_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEED2Ev,comdat\n\t.p2align\t2, 0x0\nGCC_except_table5:\n.Lexception2:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t3 # @TType Encoding = udata4\n\t.uleb128 .Lttbase2-.Lttbaseref2\n.Lttbaseref2:\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end2-.Lcst_begin2\n.Lcst_begin2:\n\t.uleb128 .Ltmp122-.Lfunc_begin2 # >> Call Site 1 <<\n\t.uleb128 .Ltmp123-.Ltmp122 # Call between .Ltmp122 and .Ltmp123\n\t.uleb128 .Ltmp124-.Lfunc_begin2 # jumps to .Ltmp124\n\t.byte\t1 # On action: 1\n.Lcst_end2:\n\t.byte\t1 # >> Action Record 1 <<\n # Catch TypeInfo 1\n\t.byte\t0 # No further actions\n\t.p2align\t2, 0x0\n # >> Catch TypeInfos <<\n\t.long\t0 # TypeInfo 1\n.Lttbase2:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text._ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em,\"axG\",@progbits,_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em,comdat\n\t.weak\t_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em # -- Begin function _ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em,@function\n_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em: # @_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em\n.Lfunc_begin3:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception3\n# %bb.0:\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 16\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 24\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 32\n\t.cfi_offset %rbx, -24\n\t.cfi_offset %r14, -16\n\tmovq\t%rsi, %r14\n\tmovq\t%rdi, %rbx\n\tmovzbl\t_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource(%rip), %eax\n\ttestb\t%al, %al\n\tje\t.LBB6_1\n.LBB6_4:\n\tmovq\t$_ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, (%rbx)\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, 8(%rbx)\n\tmovq\t$0, 24(%rbx)\n\ttestq\t%r14, %r14\n\tje\t.LBB6_7\n# %bb.5:\n\tleaq\t(,%r14,4), %rsi\n\tmovq\t_ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource+8(%rip), %rdi\n.Ltmp128:\n\tmovl\t$4, %edx\n\tcallq\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm\n.Ltmp129:\n# %bb.6:\n\tmovq\t%rax, 8(%rbx)\n\tmovq\t%r14, 16(%rbx)\n\tmovq\t%r14, 24(%rbx)\n.Ltmp130:\n\tleaq\t7(%rsp), %rdi\n\tmovq\t%rax, %rsi\n\txorl\t%edx, %edx\n\tmovq\t%r14, %rcx\n\tcallq\t_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m\n.Ltmp131:\n.LBB6_7:\n\taddq\t$8, %rsp\n\t.cfi_def_cfa_offset 24\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 16\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB6_1:\n\t.cfi_def_cfa_offset 32\n\tmovl\t$_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, %edi\n\tcallq\t__cxa_guard_acquire\n\ttestl\t%eax, %eax\n\tje\t.LBB6_4\n# %bb.2:\n.Ltmp125:\n\tmovl\t$_ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, %edi\n\tcallq\t_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEC2Ev\n.Ltmp126:\n# %bb.3:\n\tmovl\t$_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, %edi\n\tcallq\t__cxa_guard_release\n\tjmp\t.LBB6_4\n.LBB6_8:\n.Ltmp127:\n\tmovq\t%rax, %r14\n\tmovl\t$_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, %edi\n\tcallq\t__cxa_guard_abort\n\tmovq\t%r14, %rdi\n\tcallq\t_Unwind_Resume@PLT\n.LBB6_10:\n.Ltmp132:\n\tmovq\t%rax, %r14\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev\n\tmovq\t%r14, %rdi\n\tcallq\t_Unwind_Resume@PLT\n.Lfunc_end6:\n\t.size\t_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em, .Lfunc_end6-_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em\n\t.cfi_endproc\n\t.section\t.gcc_except_table._ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em,\"aG\",@progbits,_ZN6thrust6detail11vector_baseIiNS_16device_allocatorIiEEEC2Em,comdat\n\t.p2align\t2, 0x0\nGCC_except_table6:\n.Lexception3:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t255 # @TType Encoding = omit\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end3-.Lcst_begin3\n.Lcst_begin3:\n\t.uleb128 .Ltmp128-.Lfunc_begin3 # >> Call Site 1 <<\n\t.uleb128 .Ltmp131-.Ltmp128 # Call between .Ltmp128 and .Ltmp131\n\t.uleb128 .Ltmp132-.Lfunc_begin3 # jumps to .Ltmp132\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp125-.Lfunc_begin3 # >> Call Site 2 <<\n\t.uleb128 .Ltmp126-.Ltmp125 # Call between .Ltmp125 and .Ltmp126\n\t.uleb128 .Ltmp127-.Lfunc_begin3 # jumps to .Ltmp127\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp126-.Lfunc_begin3 # >> Call Site 3 <<\n\t.uleb128 .Lfunc_end6-.Ltmp126 # Call between .Ltmp126 and .Lfunc_end6\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n.Lcst_end3:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text._ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev,\"axG\",@progbits,_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev,comdat\n\t.weak\t_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev # -- Begin function _ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev,@function\n_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev: # @_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev\n.Lfunc_begin4:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception4\n# %bb.0:\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 16\n\t.cfi_offset %rbx, -16\n\tmovq\t16(%rdi), %rdx\n\ttestq\t%rdx, %rdx\n\tje\t.LBB7_3\n# %bb.1:\n\tmovq\t%rdi, %rbx\n\tmovq\t(%rdi), %rax\n\tmovq\t8(%rdi), %rsi\n\tshlq\t$2, %rdx\n\tmovq\t8(%rax), %rdi\n.Ltmp133:\n\tmovl\t$4, %ecx\n\tcallq\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm\n.Ltmp134:\n# %bb.2:\n\taddq\t$8, %rbx\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, (%rbx)\n.LBB7_3:\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB7_4:\n\t.cfi_def_cfa_offset 16\n.Ltmp135:\n\tmovq\t%rax, %rdi\n\tcallq\t__clang_call_terminate\n.Lfunc_end7:\n\t.size\t_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev, .Lfunc_end7-_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev\n\t.cfi_endproc\n\t.section\t.gcc_except_table._ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev,\"aG\",@progbits,_ZN6thrust6detail18contiguous_storageIiNS_16device_allocatorIiEEED2Ev,comdat\n\t.p2align\t2, 0x0\nGCC_except_table7:\n.Lexception4:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t3 # @TType Encoding = udata4\n\t.uleb128 .Lttbase3-.Lttbaseref3\n.Lttbaseref3:\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end4-.Lcst_begin4\n.Lcst_begin4:\n\t.uleb128 .Ltmp133-.Lfunc_begin4 # >> Call Site 1 <<\n\t.uleb128 .Ltmp134-.Ltmp133 # Call between .Ltmp133 and .Ltmp134\n\t.uleb128 .Ltmp135-.Lfunc_begin4 # jumps to .Ltmp135\n\t.byte\t1 # On action: 1\n.Lcst_end4:\n\t.byte\t1 # >> Action Record 1 <<\n # Catch TypeInfo 1\n\t.byte\t0 # No further actions\n\t.p2align\t2, 0x0\n # >> Catch TypeInfos <<\n\t.long\t0 # TypeInfo 1\n.Lttbase3:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text._ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEC2Ev,\"axG\",@progbits,_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEC2Ev,comdat\n\t.weak\t_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEC2Ev # -- Begin function _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEC2Ev\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEC2Ev,@function\n_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEC2Ev: # @_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEC2Ev\n\t.cfi_startproc\n# %bb.0:\n\tmovq\t$_ZTVN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE+16, (%rdi)\n\tmovzbl\t_ZGVZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource(%rip), %eax\n\ttestb\t%al, %al\n\tje\t.LBB8_1\n# %bb.4:\n\tmovq\t$_ZZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource, 8(%rdi)\n\tretq\n.LBB8_1:\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 16\n\t.cfi_offset %rbx, -16\n\tmovq\t%rdi, %rbx\n\tmovl\t$_ZGVZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource, %edi\n\tcallq\t__cxa_guard_acquire\n\tmovq\t%rbx, %rdi\n\ttestl\t%eax, %eax\n\tje\t.LBB8_3\n# %bb.2:\n\tmovl\t$_ZGVZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource, %edi\n\tcallq\t__cxa_guard_release\n\tmovq\t%rbx, %rdi\n.LBB8_3:\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 8\n\t.cfi_restore %rbx\n\tmovq\t$_ZZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource, 8(%rdi)\n\tretq\n.Lfunc_end8:\n\t.size\t_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEC2Ev, .Lfunc_end8-_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEC2Ev\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev,\"axG\",@progbits,_ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev,comdat\n\t.weak\t_ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev # -- Begin function _ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev,@function\n_ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev: # @_ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev\n\t.cfi_startproc\n# %bb.0:\n\tretq\n.Lfunc_end9:\n\t.size\t_ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev, .Lfunc_end9-_ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev,\"axG\",@progbits,_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev,comdat\n\t.weak\t_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev # -- Begin function _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev,@function\n_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev: # @_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev\n\t.cfi_startproc\n# %bb.0:\n\tjmp\t_ZdlPv # TAILCALL\n.Lfunc_end10:\n\t.size\t_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev, .Lfunc_end10-_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm,\"axG\",@progbits,_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm,comdat\n\t.weak\t_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm # -- Begin function _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm,@function\n_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm: # @_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm\n\t.cfi_startproc\n# %bb.0:\n\tmovq\t8(%rdi), %rdi\n\tjmp\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm # TAILCALL\n.Lfunc_end11:\n\t.size\t_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm, .Lfunc_end11-_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm,\"axG\",@progbits,_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm,comdat\n\t.weak\t_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm # -- Begin function _ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm,@function\n_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm: # @_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm\n\t.cfi_startproc\n# %bb.0:\n\tmovq\t8(%rdi), %rdi\n\tjmp\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm # TAILCALL\n.Lfunc_end12:\n\t.size\t_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm, .Lfunc_end12-_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_,\"axG\",@progbits,_ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_,comdat\n\t.weak\t_ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_ # -- Begin function _ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_\n\t.p2align\t4, 0x90\n\t.type\t_ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_,@function\n_ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_: # @_ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_\n\t.cfi_startproc\n# %bb.0:\n\tcmpq\t%rsi, %rdi\n\tsete\t%al\n\tretq\n.Lfunc_end13:\n\t.size\t_ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_, .Lfunc_end13-_ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEED2Ev,\"axG\",@progbits,_ZN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEED2Ev,comdat\n\t.weak\t_ZN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEED2Ev # -- Begin function _ZN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEED2Ev\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEED2Ev,@function\n_ZN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEED2Ev: # @_ZN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEED2Ev\n\t.cfi_startproc\n# %bb.0:\n\tretq\n.Lfunc_end14:\n\t.size\t_ZN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEED2Ev, .Lfunc_end14-_ZN6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEED2Ev\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEED0Ev,\"axG\",@progbits,_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEED0Ev,comdat\n\t.weak\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEED0Ev # -- Begin function _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEED0Ev\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEED0Ev,@function\n_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEED0Ev: # @_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEED0Ev\n\t.cfi_startproc\n# %bb.0:\n\tjmp\t_ZdlPv # TAILCALL\n.Lfunc_end15:\n\t.size\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEED0Ev, .Lfunc_end15-_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEED0Ev\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm,\"axG\",@progbits,_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm,comdat\n\t.weak\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm # -- Begin function _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm,@function\n_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm: # @_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm\n.Lfunc_begin5:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception5\n# %bb.0:\n\tpushq\t%rbp\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 32\n\tsubq\t$80, %rsp\n\t.cfi_def_cfa_offset 112\n\t.cfi_offset %rbx, -32\n\t.cfi_offset %r14, -24\n\t.cfi_offset %rbp, -16\n\tleaq\t8(%rsp), %rdi\n\tcallq\thipMalloc\n\ttestl\t%eax, %eax\n\tjne\t.LBB16_1\n# %bb.16:\n\tmovq\t8(%rsp), %rax\n\taddq\t$80, %rsp\n\t.cfi_def_cfa_offset 32\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 16\n\tpopq\t%rbp\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB16_1:\n\t.cfi_def_cfa_offset 112\n\tmovl\t%eax, %ebp\n\tcallq\thipGetLastError\n\tmovl\t$40, %edi\n\tcallq\t__cxa_allocate_exception\n\tmovq\t%rax, %rbx\n.Ltmp136:\n\tcallq\t_ZN6thrust6system12hip_categoryEv\n.Ltmp137:\n# %bb.2:\n\tmovq\t(%rax), %rcx\n.Ltmp138:\n\tleaq\t16(%rsp), %rdi\n\tmovq\t%rax, %rsi\n\tmovl\t%ebp, %edx\n\tcallq\t*48(%rcx)\n.Ltmp139:\n# %bb.3:\n\tmovq\t16(%rsp), %rsi\n.Ltmp141:\n\tleaq\t48(%rsp), %rdi\n\tleaq\t7(%rsp), %rdx\n\tcallq\t_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_\n.Ltmp142:\n# %bb.4:\n\tmovb\t$1, %bpl\n.Ltmp144:\n\tleaq\t48(%rsp), %rsi\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE\n.Ltmp145:\n# %bb.5:\n\txorl\t%ebp, %ebp\n.Ltmp146:\n\tmovl\t$_ZTIN6thrust6system6detail9bad_allocE, %esi\n\tmovl\t$_ZN6thrust6system6detail9bad_allocD2Ev, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t__cxa_throw\n.Ltmp147:\n# %bb.17:\n.LBB16_7:\n.Ltmp148:\n\tmovq\t%rax, %r14\n\tmovq\t48(%rsp), %rdi\n\tleaq\t64(%rsp), %rax\n\tcmpq\t%rax, %rdi\n\tje\t.LBB16_9\n# %bb.8:\n\tcallq\t_ZdlPv\n.LBB16_9:\n\tmovq\t16(%rsp), %rdi\n\tleaq\t32(%rsp), %rax\n\tcmpq\t%rax, %rdi\n\tje\t.LBB16_11\n# %bb.10:\n\tcallq\t_ZdlPv\n.LBB16_11:\n\ttestb\t%bpl, %bpl\n\tjne\t.LBB16_14\n\tjmp\t.LBB16_15\n.LBB16_12:\n.Ltmp143:\n\tmovq\t%rax, %r14\n\tmovq\t16(%rsp), %rdi\n\tleaq\t32(%rsp), %rax\n\tcmpq\t%rax, %rdi\n\tje\t.LBB16_14\n# %bb.13:\n\tcallq\t_ZdlPv\n\tjmp\t.LBB16_14\n.LBB16_6:\n.Ltmp140:\n\tmovq\t%rax, %r14\n.LBB16_14:\n\tmovq\t%rbx, %rdi\n\tcallq\t__cxa_free_exception\n.LBB16_15:\n\tmovq\t%r14, %rdi\n\tcallq\t_Unwind_Resume@PLT\n.Lfunc_end16:\n\t.size\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm, .Lfunc_end16-_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm\n\t.cfi_endproc\n\t.section\t.gcc_except_table._ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm,\"aG\",@progbits,_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm,comdat\n\t.p2align\t2, 0x0\nGCC_except_table16:\n.Lexception5:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t255 # @TType Encoding = omit\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end5-.Lcst_begin5\n.Lcst_begin5:\n\t.uleb128 .Lfunc_begin5-.Lfunc_begin5 # >> Call Site 1 <<\n\t.uleb128 .Ltmp136-.Lfunc_begin5 # Call between .Lfunc_begin5 and .Ltmp136\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp136-.Lfunc_begin5 # >> Call Site 2 <<\n\t.uleb128 .Ltmp139-.Ltmp136 # Call between .Ltmp136 and .Ltmp139\n\t.uleb128 .Ltmp140-.Lfunc_begin5 # jumps to .Ltmp140\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp141-.Lfunc_begin5 # >> Call Site 3 <<\n\t.uleb128 .Ltmp142-.Ltmp141 # Call between .Ltmp141 and .Ltmp142\n\t.uleb128 .Ltmp143-.Lfunc_begin5 # jumps to .Ltmp143\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp144-.Lfunc_begin5 # >> Call Site 4 <<\n\t.uleb128 .Ltmp147-.Ltmp144 # Call between .Ltmp144 and .Ltmp147\n\t.uleb128 .Ltmp148-.Lfunc_begin5 # jumps to .Ltmp148\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp147-.Lfunc_begin5 # >> Call Site 5 <<\n\t.uleb128 .Lfunc_end16-.Ltmp147 # Call between .Ltmp147 and .Lfunc_end16\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n.Lcst_end5:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text._ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm,\"axG\",@progbits,_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm,comdat\n\t.weak\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm # -- Begin function _ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm,@function\n_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm: # @_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm\n.Lfunc_begin6:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception6\n# %bb.0:\n\tpushq\t%rbp\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 32\n\t.cfi_offset %rbx, -32\n\t.cfi_offset %r14, -24\n\t.cfi_offset %rbp, -16\n\tmovq\t%rsi, %rdi\n\tcallq\thipFree\n\ttestl\t%eax, %eax\n\tjne\t.LBB17_1\n# %bb.5:\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 16\n\tpopq\t%rbp\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB17_1:\n\t.cfi_def_cfa_offset 32\n\tmovl\t%eax, %ebp\n\tcallq\thipGetLastError\n\tmovl\t$64, %edi\n\tcallq\t__cxa_allocate_exception\n\tmovq\t%rax, %rbx\n.Ltmp149:\n\tcallq\t_ZN6thrust6system12hip_categoryEv\n.Ltmp150:\n# %bb.2:\n.Ltmp151:\n\tmovl\t$.L.str.12, %ecx\n\tmovq\t%rbx, %rdi\n\tmovl\t%ebp, %esi\n\tmovq\t%rax, %rdx\n\tcallq\t_ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc\n.Ltmp152:\n# %bb.3:\n\tmovl\t$_ZTIN6thrust6system12system_errorE, %esi\n\tmovl\t$_ZN6thrust6system12system_errorD2Ev, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t__cxa_throw\n.LBB17_4:\n.Ltmp153:\n\tmovq\t%rax, %r14\n\tmovq\t%rbx, %rdi\n\tcallq\t__cxa_free_exception\n\tmovq\t%r14, %rdi\n\tcallq\t_Unwind_Resume@PLT\n.Lfunc_end17:\n\t.size\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm, .Lfunc_end17-_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm\n\t.cfi_endproc\n\t.section\t.gcc_except_table._ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm,\"aG\",@progbits,_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm,comdat\n\t.p2align\t2, 0x0\nGCC_except_table17:\n.Lexception6:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t255 # @TType Encoding = omit\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end6-.Lcst_begin6\n.Lcst_begin6:\n\t.uleb128 .Lfunc_begin6-.Lfunc_begin6 # >> Call Site 1 <<\n\t.uleb128 .Ltmp149-.Lfunc_begin6 # Call between .Lfunc_begin6 and .Ltmp149\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp149-.Lfunc_begin6 # >> Call Site 2 <<\n\t.uleb128 .Ltmp152-.Ltmp149 # Call between .Ltmp149 and .Ltmp152\n\t.uleb128 .Ltmp153-.Lfunc_begin6 # jumps to .Ltmp153\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp152-.Lfunc_begin6 # >> Call Site 3 <<\n\t.uleb128 .Lfunc_end17-.Ltmp152 # Call between .Ltmp152 and .Lfunc_end17\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n.Lcst_end6:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text._ZNK6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEE11do_is_equalERKS9_,\"axG\",@progbits,_ZNK6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEE11do_is_equalERKS9_,comdat\n\t.weak\t_ZNK6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEE11do_is_equalERKS9_ # -- Begin function _ZNK6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEE11do_is_equalERKS9_\n\t.p2align\t4, 0x90\n\t.type\t_ZNK6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEE11do_is_equalERKS9_,@function\n_ZNK6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEE11do_is_equalERKS9_: # @_ZNK6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEE11do_is_equalERKS9_\n\t.cfi_startproc\n# %bb.0:\n\tcmpq\t%rsi, %rdi\n\tsete\t%al\n\tretq\n.Lfunc_end18:\n\t.size\t_ZNK6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEE11do_is_equalERKS9_, .Lfunc_end18-_ZNK6thrust2mr15memory_resourceINS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS4_EENS_11use_defaultEEEE11do_is_equalERKS9_\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust6system12hip_categoryEv,\"axG\",@progbits,_ZN6thrust6system12hip_categoryEv,comdat\n\t.weak\t_ZN6thrust6system12hip_categoryEv # -- Begin function _ZN6thrust6system12hip_categoryEv\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6system12hip_categoryEv,@function\n_ZN6thrust6system12hip_categoryEv: # @_ZN6thrust6system12hip_categoryEv\n\t.cfi_startproc\n# %bb.0:\n\tmovzbl\t_ZGVZN6thrust6system12hip_categoryEvE6result(%rip), %eax\n\ttestb\t%al, %al\n\tje\t.LBB19_1\n# %bb.4:\n\tmovl\t$_ZZN6thrust6system12hip_categoryEvE6result, %eax\n\tretq\n.LBB19_1:\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 16\n\tmovl\t$_ZGVZN6thrust6system12hip_categoryEvE6result, %edi\n\tcallq\t__cxa_guard_acquire\n\ttestl\t%eax, %eax\n\tje\t.LBB19_3\n# %bb.2:\n\tmovq\t$_ZTVN6thrust6system11hip_rocprim6detail18hip_error_categoryE+16, _ZZN6thrust6system12hip_categoryEvE6result(%rip)\n\tmovl\t$_ZN6thrust6system14error_categoryD2Ev, %edi\n\tmovl\t$_ZZN6thrust6system12hip_categoryEvE6result, %esi\n\tmovl\t$__dso_handle, %edx\n\tcallq\t__cxa_atexit\n\tmovl\t$_ZGVZN6thrust6system12hip_categoryEvE6result, %edi\n\tcallq\t__cxa_guard_release\n.LBB19_3:\n\taddq\t$8, %rsp\n\t.cfi_def_cfa_offset 8\n\tmovl\t$_ZZN6thrust6system12hip_categoryEvE6result, %eax\n\tretq\n.Lfunc_end19:\n\t.size\t_ZN6thrust6system12hip_categoryEv, .Lfunc_end19-_ZN6thrust6system12hip_categoryEv\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,\"axG\",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,comdat\n\t.weak\t_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_ # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_\n\t.p2align\t4, 0x90\n\t.type\t_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,@function\n_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%r15\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpushq\t%r12\n\t.cfi_def_cfa_offset 32\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 40\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 48\n\t.cfi_offset %rbx, -40\n\t.cfi_offset %r12, -32\n\t.cfi_offset %r14, -24\n\t.cfi_offset %r15, -16\n\tleaq\t16(%rdi), %r12\n\tmovq\t%r12, (%rdi)\n\ttestq\t%rsi, %rsi\n\tje\t.LBB20_8\n# %bb.1:\n\tmovq\t%rsi, %r14\n\tmovq\t%rdi, %rbx\n\tmovq\t%rsi, %rdi\n\tcallq\tstrlen\n\tmovq\t%rax, %r15\n\tmovq\t%rax, (%rsp)\n\tcmpq\t$16, %rax\n\tjb\t.LBB20_3\n# %bb.2:\n\tmovq\t%rsp, %rsi\n\tmovq\t%rbx, %rdi\n\txorl\t%edx, %edx\n\tcallq\t_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm\n\tmovq\t%rax, %r12\n\tmovq\t%rax, (%rbx)\n\tmovq\t(%rsp), %rax\n\tmovq\t%rax, 16(%rbx)\n.LBB20_3:\n\ttestq\t%r15, %r15\n\tje\t.LBB20_7\n# %bb.4:\n\tcmpq\t$1, %r15\n\tjne\t.LBB20_6\n# %bb.5:\n\tmovzbl\t(%r14), %eax\n\tmovb\t%al, (%r12)\n\tjmp\t.LBB20_7\n.LBB20_6:\n\tmovq\t%r12, %rdi\n\tmovq\t%r14, %rsi\n\tmovq\t%r15, %rdx\n\tcallq\tmemcpy@PLT\n.LBB20_7:\n\tmovq\t(%rsp), %rax\n\tmovq\t%rax, 8(%rbx)\n\tmovq\t(%rbx), %rcx\n\tmovb\t$0, (%rcx,%rax)\n\taddq\t$8, %rsp\n\t.cfi_def_cfa_offset 40\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 32\n\tpopq\t%r12\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 16\n\tpopq\t%r15\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB20_8:\n\t.cfi_def_cfa_offset 48\n\tmovl\t$.L.str.11, %edi\n\tcallq\t_ZSt19__throw_logic_errorPKc\n.Lfunc_end20:\n\t.size\t_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .Lfunc_end20-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,\"axG\",@progbits,_ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat\n\t.weak\t_ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE # -- Begin function _ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,@function\n_ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE: # @_ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE\n.Lfunc_begin7:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception7\n# %bb.0:\n\tpushq\t%rbp\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r15\n\t.cfi_def_cfa_offset 24\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 32\n\tpushq\t%r13\n\t.cfi_def_cfa_offset 40\n\tpushq\t%r12\n\t.cfi_def_cfa_offset 48\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 56\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 64\n\t.cfi_offset %rbx, -56\n\t.cfi_offset %r12, -48\n\t.cfi_offset %r13, -40\n\t.cfi_offset %r14, -32\n\t.cfi_offset %r15, -24\n\t.cfi_offset %rbp, -16\n\tmovq\t%rsi, %r15\n\tmovq\t%rdi, %rbx\n\tmovq\t$_ZTVN6thrust6system6detail9bad_allocE+16, (%rdi)\n\tleaq\t8(%rdi), %r14\n\tleaq\t24(%rdi), %rbp\n\tmovq\t%rbp, 8(%rdi)\n\tmovq\t$0, 16(%rdi)\n\tmovb\t$0, 24(%rdi)\n\tcallq\t_ZNKSt9bad_alloc4whatEv\n\tmovq\t%rax, %r12\n\tmovq\t16(%rbx), %r13\n\tmovq\t%rax, %rdi\n\tcallq\tstrlen\n.Ltmp154:\n\tmovq\t%r14, %rdi\n\txorl\t%esi, %esi\n\tmovq\t%r13, %rdx\n\tmovq\t%r12, %rcx\n\tmovq\t%rax, %r8\n\tcallq\t_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm\n.Ltmp155:\n# %bb.1:\n\tmovq\t16(%rbx), %rax\n\tshrq\t%rax\n\tmovabsq\t$2305843009213693951, %rcx # imm = 0x1FFFFFFFFFFFFFFF\n\tcmpq\t%rcx, %rax\n\tje\t.LBB21_4\n# %bb.2:\n.Ltmp156:\n\tmovl\t$.L.str.9, %esi\n\tmovl\t$2, %edx\n\tmovq\t%r14, %rdi\n\tcallq\t_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm\n.Ltmp157:\n# %bb.3:\n\tmovabsq\t$4611686018427387902, %rax # imm = 0x3FFFFFFFFFFFFFFE\n\tmovq\t8(%r15), %rdx\n\tsubq\t16(%rbx), %rax\n\tincq\t%rax\n\tcmpq\t%rdx, %rax\n\tjb\t.LBB21_4\n# %bb.6:\n\tmovq\t(%r15), %rsi\n.Ltmp158:\n\tmovq\t%r14, %rdi\n\tcallq\t_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm\n.Ltmp159:\n# %bb.7:\n\taddq\t$8, %rsp\n\t.cfi_def_cfa_offset 56\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 48\n\tpopq\t%r12\n\t.cfi_def_cfa_offset 40\n\tpopq\t%r13\n\t.cfi_def_cfa_offset 32\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r15\n\t.cfi_def_cfa_offset 16\n\tpopq\t%rbp\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB21_4:\n\t.cfi_def_cfa_offset 64\n.Ltmp160:\n\tmovl\t$.L.str.10, %edi\n\tcallq\t_ZSt20__throw_length_errorPKc\n.Ltmp161:\n# %bb.5:\n.LBB21_8:\n.Ltmp162:\n\tmovq\t%rax, %r15\n\tmovq\t(%r14), %rdi\n\tcmpq\t%rbp, %rdi\n\tje\t.LBB21_10\n# %bb.9:\n\tcallq\t_ZdlPv\n.LBB21_10:\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZNSt9bad_allocD2Ev\n\tmovq\t%r15, %rdi\n\tcallq\t_Unwind_Resume@PLT\n.Lfunc_end21:\n\t.size\t_ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .Lfunc_end21-_ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE\n\t.cfi_endproc\n\t.section\t.gcc_except_table._ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,\"aG\",@progbits,_ZN6thrust6system6detail9bad_allocC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat\n\t.p2align\t2, 0x0\nGCC_except_table21:\n.Lexception7:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t255 # @TType Encoding = omit\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end7-.Lcst_begin7\n.Lcst_begin7:\n\t.uleb128 .Ltmp154-.Lfunc_begin7 # >> Call Site 1 <<\n\t.uleb128 .Ltmp161-.Ltmp154 # Call between .Ltmp154 and .Ltmp161\n\t.uleb128 .Ltmp162-.Lfunc_begin7 # jumps to .Ltmp162\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp161-.Lfunc_begin7 # >> Call Site 2 <<\n\t.uleb128 .Lfunc_end21-.Ltmp161 # Call between .Ltmp161 and .Lfunc_end21\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n.Lcst_end7:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text._ZN6thrust6system6detail9bad_allocD2Ev,\"axG\",@progbits,_ZN6thrust6system6detail9bad_allocD2Ev,comdat\n\t.weak\t_ZN6thrust6system6detail9bad_allocD2Ev # -- Begin function _ZN6thrust6system6detail9bad_allocD2Ev\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6system6detail9bad_allocD2Ev,@function\n_ZN6thrust6system6detail9bad_allocD2Ev: # @_ZN6thrust6system6detail9bad_allocD2Ev\n\t.cfi_startproc\n# %bb.0:\n\tmovq\t$_ZTVN6thrust6system6detail9bad_allocE+16, (%rdi)\n\tmovq\t8(%rdi), %rax\n\tleaq\t24(%rdi), %rcx\n\tcmpq\t%rcx, %rax\n\tje\t_ZNSt9bad_allocD2Ev # TAILCALL\n# %bb.1:\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 16\n\t.cfi_offset %rbx, -16\n\tmovq\t%rdi, %rbx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZdlPv\n\tmovq\t%rbx, %rdi\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 8\n\t.cfi_restore %rbx\n\tjmp\t_ZNSt9bad_allocD2Ev # TAILCALL\n.Lfunc_end22:\n\t.size\t_ZN6thrust6system6detail9bad_allocD2Ev, .Lfunc_end22-_ZN6thrust6system6detail9bad_allocD2Ev\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust6system14error_categoryD2Ev,\"axG\",@progbits,_ZN6thrust6system14error_categoryD2Ev,comdat\n\t.weak\t_ZN6thrust6system14error_categoryD2Ev # -- Begin function _ZN6thrust6system14error_categoryD2Ev\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6system14error_categoryD2Ev,@function\n_ZN6thrust6system14error_categoryD2Ev: # @_ZN6thrust6system14error_categoryD2Ev\n\t.cfi_startproc\n# %bb.0:\n\tmovq\t$_ZTVN6thrust6system14error_categoryE+16, (%rdi)\n\tretq\n.Lfunc_end23:\n\t.size\t_ZN6thrust6system14error_categoryD2Ev, .Lfunc_end23-_ZN6thrust6system14error_categoryD2Ev\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust6system11hip_rocprim6detail18hip_error_categoryD0Ev,\"axG\",@progbits,_ZN6thrust6system11hip_rocprim6detail18hip_error_categoryD0Ev,comdat\n\t.weak\t_ZN6thrust6system11hip_rocprim6detail18hip_error_categoryD0Ev # -- Begin function _ZN6thrust6system11hip_rocprim6detail18hip_error_categoryD0Ev\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6system11hip_rocprim6detail18hip_error_categoryD0Ev,@function\n_ZN6thrust6system11hip_rocprim6detail18hip_error_categoryD0Ev: # @_ZN6thrust6system11hip_rocprim6detail18hip_error_categoryD0Ev\n\t.cfi_startproc\n# %bb.0:\n\tjmp\t_ZdlPv # TAILCALL\n.Lfunc_end24:\n\t.size\t_ZN6thrust6system11hip_rocprim6detail18hip_error_categoryD0Ev, .Lfunc_end24-_ZN6thrust6system11hip_rocprim6detail18hip_error_categoryD0Ev\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZNK6thrust6system11hip_rocprim6detail18hip_error_category4nameEv,\"axG\",@progbits,_ZNK6thrust6system11hip_rocprim6detail18hip_error_category4nameEv,comdat\n\t.weak\t_ZNK6thrust6system11hip_rocprim6detail18hip_error_category4nameEv # -- Begin function _ZNK6thrust6system11hip_rocprim6detail18hip_error_category4nameEv\n\t.p2align\t4, 0x90\n\t.type\t_ZNK6thrust6system11hip_rocprim6detail18hip_error_category4nameEv,@function\n_ZNK6thrust6system11hip_rocprim6detail18hip_error_category4nameEv: # @_ZNK6thrust6system11hip_rocprim6detail18hip_error_category4nameEv\n\t.cfi_startproc\n# %bb.0:\n\tmovl\t$.L.str.3, %eax\n\tretq\n.Lfunc_end25:\n\t.size\t_ZNK6thrust6system11hip_rocprim6detail18hip_error_category4nameEv, .Lfunc_end25-_ZNK6thrust6system11hip_rocprim6detail18hip_error_category4nameEv\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZNK6thrust6system11hip_rocprim6detail18hip_error_category23default_error_conditionEi,\"axG\",@progbits,_ZNK6thrust6system11hip_rocprim6detail18hip_error_category23default_error_conditionEi,comdat\n\t.weak\t_ZNK6thrust6system11hip_rocprim6detail18hip_error_category23default_error_conditionEi # -- Begin function _ZNK6thrust6system11hip_rocprim6detail18hip_error_category23default_error_conditionEi\n\t.p2align\t4, 0x90\n\t.type\t_ZNK6thrust6system11hip_rocprim6detail18hip_error_category23default_error_conditionEi,@function\n_ZNK6thrust6system11hip_rocprim6detail18hip_error_category23default_error_conditionEi: # @_ZNK6thrust6system11hip_rocprim6detail18hip_error_category23default_error_conditionEi\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 16\n\t.cfi_offset %rbx, -16\n\tcmpl\t$50, %esi\n\tjg\t.LBB26_5\n# %bb.1:\n\tmovzbl\t_ZGVZN6thrust6system12hip_categoryEvE6result(%rip), %eax\n\ttestb\t%al, %al\n\tje\t.LBB26_2\n.LBB26_4:\n\tmovl\t$_ZZN6thrust6system12hip_categoryEvE6result, %edx\n\tmovl\t%esi, %eax\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB26_5:\n\t.cfi_def_cfa_offset 16\n\tmovzbl\t_ZGVZN6thrust6system15system_categoryEvE6result(%rip), %eax\n\ttestb\t%al, %al\n\tje\t.LBB26_6\n.LBB26_8:\n\tmovq\t_ZZN6thrust6system15system_categoryEvE6result(%rip), %rax\n\tmovq\t24(%rax), %rax\n\tmovl\t$_ZZN6thrust6system15system_categoryEvE6result, %edi\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 8\n\tjmpq\t*%rax # TAILCALL\n.LBB26_2:\n\t.cfi_def_cfa_offset 16\n\tmovl\t$_ZGVZN6thrust6system12hip_categoryEvE6result, %edi\n\tmovl\t%esi, %ebx\n\tcallq\t__cxa_guard_acquire\n\tmovl\t%ebx, %esi\n\ttestl\t%eax, %eax\n\tje\t.LBB26_4\n# %bb.3:\n\tmovq\t$_ZTVN6thrust6system11hip_rocprim6detail18hip_error_categoryE+16, _ZZN6thrust6system12hip_categoryEvE6result(%rip)\n\tmovl\t$_ZN6thrust6system14error_categoryD2Ev, %edi\n\tmovl\t$_ZZN6thrust6system12hip_categoryEvE6result, %esi\n\tmovl\t$__dso_handle, %edx\n\tcallq\t__cxa_atexit\n\tmovl\t$_ZGVZN6thrust6system12hip_categoryEvE6result, %edi\n\tcallq\t__cxa_guard_release\n\tmovl\t%ebx, %esi\n\tjmp\t.LBB26_4\n.LBB26_6:\n\tmovl\t$_ZGVZN6thrust6system15system_categoryEvE6result, %edi\n\tmovl\t%esi, %ebx\n\tcallq\t__cxa_guard_acquire\n\tmovl\t%ebx, %esi\n\ttestl\t%eax, %eax\n\tje\t.LBB26_8\n# %bb.7:\n\tmovq\t$_ZTVN6thrust6system6detail21system_error_categoryE+16, _ZZN6thrust6system15system_categoryEvE6result(%rip)\n\tmovl\t$_ZN6thrust6system14error_categoryD2Ev, %edi\n\tmovl\t$_ZZN6thrust6system15system_categoryEvE6result, %esi\n\tmovl\t$__dso_handle, %edx\n\tcallq\t__cxa_atexit\n\tmovl\t$_ZGVZN6thrust6system15system_categoryEvE6result, %edi\n\tcallq\t__cxa_guard_release\n\tmovl\t%ebx, %esi\n\tjmp\t.LBB26_8\n.Lfunc_end26:\n\t.size\t_ZNK6thrust6system11hip_rocprim6detail18hip_error_category23default_error_conditionEi, .Lfunc_end26-_ZNK6thrust6system11hip_rocprim6detail18hip_error_category23default_error_conditionEi\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE,\"axG\",@progbits,_ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE,comdat\n\t.weak\t_ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE # -- Begin function _ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE\n\t.p2align\t4, 0x90\n\t.type\t_ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE,@function\n_ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE: # @_ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 16\n\t.cfi_offset %rbx, -16\n\tmovq\t%rdx, %rbx\n\tmovq\t(%rdi), %rax\n\tcallq\t*24(%rax)\n\tcmpq\t8(%rbx), %rdx\n\tsete\t%cl\n\tcmpl\t(%rbx), %eax\n\tsete\t%al\n\tandb\t%cl, %al\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 8\n\tretq\n.Lfunc_end27:\n\t.size\t_ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE, .Lfunc_end27-_ZNK6thrust6system14error_category10equivalentEiRKNS0_15error_conditionE\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi,\"axG\",@progbits,_ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi,comdat\n\t.weak\t_ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi # -- Begin function _ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi\n\t.p2align\t4, 0x90\n\t.type\t_ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi,@function\n_ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi: # @_ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi\n\t.cfi_startproc\n# %bb.0:\n\tcmpq\t%rdi, 8(%rsi)\n\tsete\t%cl\n\tcmpl\t%edx, (%rsi)\n\tsete\t%al\n\tandb\t%cl, %al\n\tretq\n.Lfunc_end28:\n\t.size\t_ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi, .Lfunc_end28-_ZNK6thrust6system14error_category10equivalentERKNS0_10error_codeEi\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei,\"axG\",@progbits,_ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei,comdat\n\t.weak\t_ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei # -- Begin function _ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei\n\t.p2align\t4, 0x90\n\t.type\t_ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei,@function\n_ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei: # @_ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei\n.Lfunc_begin8:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception8\n# %bb.0:\n\tpushq\t%rbp\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r15\n\t.cfi_def_cfa_offset 24\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 32\n\tpushq\t%r13\n\t.cfi_def_cfa_offset 40\n\tpushq\t%r12\n\t.cfi_def_cfa_offset 48\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 56\n\tsubq\t$72, %rsp\n\t.cfi_def_cfa_offset 128\n\t.cfi_offset %rbx, -56\n\t.cfi_offset %r12, -48\n\t.cfi_offset %r13, -40\n\t.cfi_offset %r14, -32\n\t.cfi_offset %r15, -24\n\t.cfi_offset %rbp, -16\n\tmovl\t%edx, %ebp\n\tmovq\t%rdi, %rbx\n\tmovl\t%edx, %edi\n\tcallq\thipGetErrorString\n\tmovq\t%rax, %r14\n\tmovl\t%ebp, %edi\n\tcallq\thipGetErrorName\n\ttestq\t%rax, %rax\n\tmovl\t$.L.str.8, %r15d\n\tcmovneq\t%rax, %r15\n\tleaq\t24(%rsp), %r13\n\tmovq\t%r13, 8(%rsp)\n\tmovq\t%r15, %rdi\n\tcallq\tstrlen\n\tmovq\t%rax, %r12\n\tmovq\t%rax, (%rsp)\n\tmovq\t%r13, %rax\n\tcmpq\t$16, %r12\n\tjb\t.LBB29_2\n# %bb.1:\n\tleaq\t8(%rsp), %rdi\n\tmovq\t%rsp, %rsi\n\txorl\t%edx, %edx\n\tcallq\t_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm\n\tmovq\t%rax, 8(%rsp)\n\tmovq\t(%rsp), %rcx\n\tmovq\t%rcx, 24(%rsp)\n.LBB29_2:\n\ttestq\t%r12, %r12\n\tje\t.LBB29_6\n# %bb.3:\n\tcmpq\t$1, %r12\n\tjne\t.LBB29_5\n# %bb.4:\n\tmovzbl\t(%r15), %ecx\n\tmovb\t%cl, (%rax)\n\tjmp\t.LBB29_6\n.LBB29_5:\n\tmovq\t%rax, %rdi\n\tmovq\t%r15, %rsi\n\tmovq\t%r12, %rdx\n\tcallq\tmemcpy@PLT\n.LBB29_6:\n\tmovq\t(%rsp), %rax\n\tmovq\t%rax, 16(%rsp)\n\tmovq\t8(%rsp), %rcx\n\tmovb\t$0, (%rcx,%rax)\n\tmovq\t16(%rsp), %rax\n\tshrq\t%rax\n\tmovabsq\t$2305843009213693951, %rcx # imm = 0x1FFFFFFFFFFFFFFF\n\tcmpq\t%rcx, %rax\n\tje\t.LBB29_7\n# %bb.9:\n.Ltmp163:\n\tleaq\t8(%rsp), %rdi\n\tmovl\t$.L.str.9, %esi\n\tmovl\t$2, %edx\n\tcallq\t_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm\n.Ltmp164:\n# %bb.10:\n\tmovabsq\t$4611686018427387902, %rbp # imm = 0x3FFFFFFFFFFFFFFE\n\tleaq\t56(%rsp), %r15\n\tmovq\t%r15, 40(%rsp)\n\tmovq\t(%rax), %rsi\n\tmovq\t%rax, %r12\n\taddq\t$16, %r12\n\tcmpq\t%r12, %rsi\n\tje\t.LBB29_11\n# %bb.12:\n\tmovq\t%rsi, 40(%rsp)\n\tmovq\t16(%rax), %rcx\n\tmovq\t%rcx, 56(%rsp)\n\tmovq\t8(%rax), %r13\n\tjmp\t.LBB29_13\n.LBB29_11:\n\tmovq\t8(%rax), %r13\n\tleaq\t1(%r13), %rdx\n\tmovq\t%r15, %rdi\n\tmovq\t%rax, %r15\n\tcallq\tmemcpy@PLT\n\tmovq\t%r15, %rax\n\tleaq\t56(%rsp), %r15\n.LBB29_13:\n\tmovq\t%r13, 48(%rsp)\n\tmovq\t%r12, (%rax)\n\tmovq\t$0, 8(%rax)\n\tmovb\t$0, 16(%rax)\n\ttestq\t%r14, %r14\n\tmovl\t$.L.str.7, %r12d\n\tcmovneq\t%r14, %r12\n\tmovq\t%r12, %rdi\n\tcallq\tstrlen\n\tsubq\t%r13, %rbp\n\tincq\t%rbp\n\tcmpq\t%rax, %rbp\n\tjb\t.LBB29_14\n# %bb.16:\n.Ltmp165:\n\tleaq\t40(%rsp), %rdi\n\tmovq\t%r12, %rsi\n\tmovq\t%rax, %rdx\n\tcallq\t_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm\n.Ltmp166:\n# %bb.17:\n\tleaq\t16(%rbx), %rdi\n\tmovq\t%rdi, (%rbx)\n\tmovq\t(%rax), %rsi\n\tmovq\t%rax, %r14\n\taddq\t$16, %r14\n\tcmpq\t%r14, %rsi\n\tje\t.LBB29_18\n# %bb.19:\n\tmovq\t%rsi, (%rbx)\n\tmovq\t16(%rax), %rcx\n\tmovq\t%rcx, 16(%rbx)\n\tmovq\t8(%rax), %r12\n\tjmp\t.LBB29_20\n.LBB29_18:\n\tmovq\t8(%rax), %r12\n\tleaq\t1(%r12), %rdx\n\tmovq\t%r15, %r13\n\tmovq\t%rax, %r15\n\tcallq\tmemcpy@PLT\n\tmovq\t%r15, %rax\n\tmovq\t%r13, %r15\n.LBB29_20:\n\tmovq\t%r12, 8(%rbx)\n\tmovq\t%r14, (%rax)\n\tmovq\t$0, 8(%rax)\n\tmovb\t$0, 16(%rax)\n\tmovq\t40(%rsp), %rdi\n\tcmpq\t%r15, %rdi\n\tje\t.LBB29_22\n# %bb.21:\n\tcallq\t_ZdlPv\n.LBB29_22:\n\tmovq\t8(%rsp), %rdi\n\tleaq\t24(%rsp), %rax\n\tcmpq\t%rax, %rdi\n\tje\t.LBB29_24\n# %bb.23:\n\tcallq\t_ZdlPv\n.LBB29_24:\n\tmovq\t%rbx, %rax\n\taddq\t$72, %rsp\n\t.cfi_def_cfa_offset 56\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 48\n\tpopq\t%r12\n\t.cfi_def_cfa_offset 40\n\tpopq\t%r13\n\t.cfi_def_cfa_offset 32\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r15\n\t.cfi_def_cfa_offset 16\n\tpopq\t%rbp\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB29_7:\n\t.cfi_def_cfa_offset 128\n.Ltmp170:\n\tmovl\t$.L.str.10, %edi\n\tcallq\t_ZSt20__throw_length_errorPKc\n.Ltmp171:\n# %bb.8:\n.LBB29_14:\n.Ltmp167:\n\tmovl\t$.L.str.10, %edi\n\tcallq\t_ZSt20__throw_length_errorPKc\n.Ltmp168:\n# %bb.15:\n.LBB29_26:\n.Ltmp169:\n\tmovq\t%rax, %rbx\n\tmovq\t40(%rsp), %rdi\n\tcmpq\t%r15, %rdi\n\tje\t.LBB29_28\n# %bb.27:\n\tcallq\t_ZdlPv\n\tjmp\t.LBB29_28\n.LBB29_25:\n.Ltmp172:\n\tmovq\t%rax, %rbx\n.LBB29_28:\n\tmovq\t8(%rsp), %rdi\n\tleaq\t24(%rsp), %rax\n\tcmpq\t%rax, %rdi\n\tje\t.LBB29_30\n# %bb.29:\n\tcallq\t_ZdlPv\n.LBB29_30:\n\tmovq\t%rbx, %rdi\n\tcallq\t_Unwind_Resume@PLT\n.Lfunc_end29:\n\t.size\t_ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei, .Lfunc_end29-_ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei\n\t.cfi_endproc\n\t.section\t.gcc_except_table._ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei,\"aG\",@progbits,_ZNK6thrust6system11hip_rocprim6detail18hip_error_category7messageB5cxx11Ei,comdat\n\t.p2align\t2, 0x0\nGCC_except_table29:\n.Lexception8:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t255 # @TType Encoding = omit\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end8-.Lcst_begin8\n.Lcst_begin8:\n\t.uleb128 .Lfunc_begin8-.Lfunc_begin8 # >> Call Site 1 <<\n\t.uleb128 .Ltmp163-.Lfunc_begin8 # Call between .Lfunc_begin8 and .Ltmp163\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp163-.Lfunc_begin8 # >> Call Site 2 <<\n\t.uleb128 .Ltmp164-.Ltmp163 # Call between .Ltmp163 and .Ltmp164\n\t.uleb128 .Ltmp172-.Lfunc_begin8 # jumps to .Ltmp172\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp164-.Lfunc_begin8 # >> Call Site 3 <<\n\t.uleb128 .Ltmp165-.Ltmp164 # Call between .Ltmp164 and .Ltmp165\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp165-.Lfunc_begin8 # >> Call Site 4 <<\n\t.uleb128 .Ltmp166-.Ltmp165 # Call between .Ltmp165 and .Ltmp166\n\t.uleb128 .Ltmp169-.Lfunc_begin8 # jumps to .Ltmp169\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp166-.Lfunc_begin8 # >> Call Site 5 <<\n\t.uleb128 .Ltmp170-.Ltmp166 # Call between .Ltmp166 and .Ltmp170\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp170-.Lfunc_begin8 # >> Call Site 6 <<\n\t.uleb128 .Ltmp171-.Ltmp170 # Call between .Ltmp170 and .Ltmp171\n\t.uleb128 .Ltmp172-.Lfunc_begin8 # jumps to .Ltmp172\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp167-.Lfunc_begin8 # >> Call Site 7 <<\n\t.uleb128 .Ltmp168-.Ltmp167 # Call between .Ltmp167 and .Ltmp168\n\t.uleb128 .Ltmp169-.Lfunc_begin8 # jumps to .Ltmp169\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp168-.Lfunc_begin8 # >> Call Site 8 <<\n\t.uleb128 .Lfunc_end29-.Ltmp168 # Call between .Ltmp168 and .Lfunc_end29\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n.Lcst_end8:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text._ZN6thrust6system14error_categoryD0Ev,\"axG\",@progbits,_ZN6thrust6system14error_categoryD0Ev,comdat\n\t.weak\t_ZN6thrust6system14error_categoryD0Ev # -- Begin function _ZN6thrust6system14error_categoryD0Ev\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6system14error_categoryD0Ev,@function\n_ZN6thrust6system14error_categoryD0Ev: # @_ZN6thrust6system14error_categoryD0Ev\n\t.cfi_startproc\n# %bb.0:\n\tud2\n.Lfunc_end30:\n\t.size\t_ZN6thrust6system14error_categoryD0Ev, .Lfunc_end30-_ZN6thrust6system14error_categoryD0Ev\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZNK6thrust6system14error_category23default_error_conditionEi,\"axG\",@progbits,_ZNK6thrust6system14error_category23default_error_conditionEi,comdat\n\t.weak\t_ZNK6thrust6system14error_category23default_error_conditionEi # -- Begin function _ZNK6thrust6system14error_category23default_error_conditionEi\n\t.p2align\t4, 0x90\n\t.type\t_ZNK6thrust6system14error_category23default_error_conditionEi,@function\n_ZNK6thrust6system14error_category23default_error_conditionEi: # @_ZNK6thrust6system14error_category23default_error_conditionEi\n\t.cfi_startproc\n# %bb.0:\n\tmovl\t%esi, %eax\n\tmovq\t%rdi, %rdx\n\tretq\n.Lfunc_end31:\n\t.size\t_ZNK6thrust6system14error_category23default_error_conditionEi, .Lfunc_end31-_ZNK6thrust6system14error_category23default_error_conditionEi\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust6system15system_categoryEv,\"axG\",@progbits,_ZN6thrust6system15system_categoryEv,comdat\n\t.weak\t_ZN6thrust6system15system_categoryEv # -- Begin function _ZN6thrust6system15system_categoryEv\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6system15system_categoryEv,@function\n_ZN6thrust6system15system_categoryEv: # @_ZN6thrust6system15system_categoryEv\n\t.cfi_startproc\n# %bb.0:\n\tmovzbl\t_ZGVZN6thrust6system15system_categoryEvE6result(%rip), %eax\n\ttestb\t%al, %al\n\tje\t.LBB32_1\n# %bb.4:\n\tmovl\t$_ZZN6thrust6system15system_categoryEvE6result, %eax\n\tretq\n.LBB32_1:\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 16\n\tmovl\t$_ZGVZN6thrust6system15system_categoryEvE6result, %edi\n\tcallq\t__cxa_guard_acquire\n\ttestl\t%eax, %eax\n\tje\t.LBB32_3\n# %bb.2:\n\tmovq\t$_ZTVN6thrust6system6detail21system_error_categoryE+16, _ZZN6thrust6system15system_categoryEvE6result(%rip)\n\tmovl\t$_ZN6thrust6system14error_categoryD2Ev, %edi\n\tmovl\t$_ZZN6thrust6system15system_categoryEvE6result, %esi\n\tmovl\t$__dso_handle, %edx\n\tcallq\t__cxa_atexit\n\tmovl\t$_ZGVZN6thrust6system15system_categoryEvE6result, %edi\n\tcallq\t__cxa_guard_release\n.LBB32_3:\n\taddq\t$8, %rsp\n\t.cfi_def_cfa_offset 8\n\tmovl\t$_ZZN6thrust6system15system_categoryEvE6result, %eax\n\tretq\n.Lfunc_end32:\n\t.size\t_ZN6thrust6system15system_categoryEv, .Lfunc_end32-_ZN6thrust6system15system_categoryEv\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust6system6detail21system_error_categoryD0Ev,\"axG\",@progbits,_ZN6thrust6system6detail21system_error_categoryD0Ev,comdat\n\t.weak\t_ZN6thrust6system6detail21system_error_categoryD0Ev # -- Begin function _ZN6thrust6system6detail21system_error_categoryD0Ev\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6system6detail21system_error_categoryD0Ev,@function\n_ZN6thrust6system6detail21system_error_categoryD0Ev: # @_ZN6thrust6system6detail21system_error_categoryD0Ev\n\t.cfi_startproc\n# %bb.0:\n\tjmp\t_ZdlPv # TAILCALL\n.Lfunc_end33:\n\t.size\t_ZN6thrust6system6detail21system_error_categoryD0Ev, .Lfunc_end33-_ZN6thrust6system6detail21system_error_categoryD0Ev\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZNK6thrust6system6detail21system_error_category4nameEv,\"axG\",@progbits,_ZNK6thrust6system6detail21system_error_category4nameEv,comdat\n\t.weak\t_ZNK6thrust6system6detail21system_error_category4nameEv # -- Begin function _ZNK6thrust6system6detail21system_error_category4nameEv\n\t.p2align\t4, 0x90\n\t.type\t_ZNK6thrust6system6detail21system_error_category4nameEv,@function\n_ZNK6thrust6system6detail21system_error_category4nameEv: # @_ZNK6thrust6system6detail21system_error_category4nameEv\n\t.cfi_startproc\n# %bb.0:\n\tmovl\t$.L.str.4, %eax\n\tretq\n.Lfunc_end34:\n\t.size\t_ZNK6thrust6system6detail21system_error_category4nameEv, .Lfunc_end34-_ZNK6thrust6system6detail21system_error_category4nameEv\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZNK6thrust6system6detail21system_error_category23default_error_conditionEi,\"axG\",@progbits,_ZNK6thrust6system6detail21system_error_category23default_error_conditionEi,comdat\n\t.weak\t_ZNK6thrust6system6detail21system_error_category23default_error_conditionEi # -- Begin function _ZNK6thrust6system6detail21system_error_category23default_error_conditionEi\n\t.p2align\t4, 0x90\n\t.type\t_ZNK6thrust6system6detail21system_error_category23default_error_conditionEi,@function\n_ZNK6thrust6system6detail21system_error_category23default_error_conditionEi: # @_ZNK6thrust6system6detail21system_error_category23default_error_conditionEi\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 16\n\t.cfi_offset %rbx, -16\n\tmovl\t%esi, %ebx\n\tleal\t-9901(%rbx), %eax\n\tcmpl\t$78, %eax\n\tja\t.LBB35_81\n# %bb.1:\n\tjmpq\t*.LJTI35_0(,%rax,8)\n.LBB35_2:\n\tmovl\t$9901, %edi # imm = 0x26AD\n\tjmp\t.LBB35_3\n.LBB35_77:\n\tmovl\t$9979, %edi # imm = 0x26FB\n\tjmp\t.LBB35_3\n.LBB35_33:\n\tmovl\t$9961, %edi # imm = 0x26E9\n\tjmp\t.LBB35_3\n.LBB35_50:\n\tmovl\t$9968, %edi # imm = 0x26F0\n\tjmp\t.LBB35_3\n.LBB35_67:\n\tmovl\t$9974, %edi # imm = 0x26F6\n\tjmp\t.LBB35_3\n.LBB35_75:\n\tmovl\t$9977, %edi # imm = 0x26F9\n\tjmp\t.LBB35_3\n.LBB35_28:\n\tmovl\t$9945, %edi # imm = 0x26D9\n\tjmp\t.LBB35_3\n.LBB35_19:\n\tmovl\t$9952, %edi # imm = 0x26E0\n\tjmp\t.LBB35_3\n.LBB35_29:\n\tmovl\t$9958, %edi # imm = 0x26E6\n\tjmp\t.LBB35_3\n.LBB35_22:\n\tmovl\t$9955, %edi # imm = 0x26E3\n\tjmp\t.LBB35_3\n.LBB35_17:\n\tmovl\t$9951, %edi # imm = 0x26DF\n\tjmp\t.LBB35_3\n.LBB35_66:\n\tmovl\t$9933, %edi # imm = 0x26CD\n\tjmp\t.LBB35_3\n.LBB35_80:\n\tmovl\t$9941, %edi # imm = 0x26D5\n\tjmp\t.LBB35_3\n.LBB35_59:\n\tmovl\t$9928, %edi # imm = 0x26C8\n\tjmp\t.LBB35_3\n.LBB35_79:\n\tmovl\t$9940, %edi # imm = 0x26D4\n\tjmp\t.LBB35_3\n.LBB35_74:\n\tmovl\t$9938, %edi # imm = 0x26D2\n\tjmp\t.LBB35_3\n.LBB35_58:\n\tmovl\t$9927, %edi # imm = 0x26C7\n\tjmp\t.LBB35_3\n.LBB35_45:\n\tmovl\t$9921, %edi # imm = 0x26C1\n\tjmp\t.LBB35_3\n.LBB35_68:\n\tmovl\t$9975, %edi # imm = 0x26F7\n\tjmp\t.LBB35_3\n.LBB35_7:\n\tmovl\t$9946, %edi # imm = 0x26DA\n\tjmp\t.LBB35_3\n.LBB35_39:\n\tmovl\t$9917, %edi # imm = 0x26BD\n\tjmp\t.LBB35_3\n.LBB35_48:\n\tmovl\t$9966, %edi # imm = 0x26EE\n\tjmp\t.LBB35_3\n.LBB35_71:\n\tmovl\t$9934, %edi # imm = 0x26CE\n\tjmp\t.LBB35_3\n.LBB35_13:\n\tmovl\t$9906, %edi # imm = 0x26B2\n\tjmp\t.LBB35_3\n.LBB35_43:\n\tmovl\t$9919, %edi # imm = 0x26BF\n\tjmp\t.LBB35_3\n.LBB35_47:\n\tmovl\t$9922, %edi # imm = 0x26C2\n\tjmp\t.LBB35_3\n.LBB35_25:\n\tmovl\t$9942, %edi # imm = 0x26D6\n\tjmp\t.LBB35_3\n.LBB35_57:\n\tmovl\t$9926, %edi # imm = 0x26C6\n\tjmp\t.LBB35_3\n.LBB35_61:\n\tmovl\t$9929, %edi # imm = 0x26C9\n\tjmp\t.LBB35_3\n.LBB35_4:\n\tmovl\t$9902, %edi # imm = 0x26AE\n\tjmp\t.LBB35_3\n.LBB35_54:\n\tmovl\t$9924, %edi # imm = 0x26C4\n\tjmp\t.LBB35_3\n.LBB35_18:\n\tmovl\t$9910, %edi # imm = 0x26B6\n\tjmp\t.LBB35_3\n.LBB35_56:\n\tmovl\t$9971, %edi # imm = 0x26F3\n\tjmp\t.LBB35_3\n.LBB35_5:\n\tmovl\t$9903, %edi # imm = 0x26AF\n\tjmp\t.LBB35_3\n.LBB35_11:\n\tmovl\t$9905, %edi # imm = 0x26B1\n\tjmp\t.LBB35_3\n.LBB35_36:\n\tmovl\t$9914, %edi # imm = 0x26BA\n\tjmp\t.LBB35_3\n.LBB35_62:\n\tmovl\t$9930, %edi # imm = 0x26CA\n\tjmp\t.LBB35_3\n.LBB35_65:\n\tmovl\t$9932, %edi # imm = 0x26CC\n\tjmp\t.LBB35_3\n.LBB35_15:\n\tmovl\t$9908, %edi # imm = 0x26B4\n\tjmp\t.LBB35_3\n.LBB35_6:\n\tmovl\t$9904, %edi # imm = 0x26B0\n\tjmp\t.LBB35_3\n.LBB35_26:\n\tmovl\t$9911, %edi # imm = 0x26B7\n\tjmp\t.LBB35_3\n.LBB35_31:\n\tmovl\t$9943, %edi # imm = 0x26D7\n\tjmp\t.LBB35_3\n.LBB35_53:\n\tmovl\t$9923, %edi # imm = 0x26C3\n\tjmp\t.LBB35_3\n.LBB35_16:\n\tmovl\t$9909, %edi # imm = 0x26B5\n\tjmp\t.LBB35_3\n.LBB35_8:\n\tmovl\t$9947, %edi # imm = 0x26DB\n\tjmp\t.LBB35_3\n.LBB35_12:\n\tmovl\t$9950, %edi # imm = 0x26DE\n\tjmp\t.LBB35_3\n.LBB35_14:\n\tmovl\t$9907, %edi # imm = 0x26B3\n\tjmp\t.LBB35_3\n.LBB35_44:\n\tmovl\t$9920, %edi # imm = 0x26C0\n\tjmp\t.LBB35_3\n.LBB35_69:\n\tmovl\t$9976, %edi # imm = 0x26F8\n\tjmp\t.LBB35_3\n.LBB35_9:\n\tmovl\t$9948, %edi # imm = 0x26DC\n\tjmp\t.LBB35_3\n.LBB35_78:\n\tmovl\t$9939, %edi # imm = 0x26D3\n\tjmp\t.LBB35_3\n.LBB35_35:\n\tmovl\t$9913, %edi # imm = 0x26B9\n\tjmp\t.LBB35_3\n.LBB35_23:\n\tmovl\t$9956, %edi # imm = 0x26E4\n\tjmp\t.LBB35_3\n.LBB35_55:\n\tmovl\t$9925, %edi # imm = 0x26C5\n\tjmp\t.LBB35_3\n.LBB35_63:\n\tmovl\t$9931, %edi # imm = 0x26CB\n\tjmp\t.LBB35_3\n.LBB35_27:\n\tmovl\t$9912, %edi # imm = 0x26B8\n\tjmp\t.LBB35_3\n.LBB35_72:\n\tmovl\t$9935, %edi # imm = 0x26CF\n\tjmp\t.LBB35_3\n.LBB35_37:\n\tmovl\t$9915, %edi # imm = 0x26BB\n\tjmp\t.LBB35_3\n.LBB35_38:\n\tmovl\t$9916, %edi # imm = 0x26BC\n\tjmp\t.LBB35_3\n.LBB35_24:\n\tmovl\t$9957, %edi # imm = 0x26E5\n\tjmp\t.LBB35_3\n.LBB35_70:\n\tmovl\t$9944, %edi # imm = 0x26D8\n\tjmp\t.LBB35_3\n.LBB35_41:\n\tmovl\t$9918, %edi # imm = 0x26BE\n\tjmp\t.LBB35_3\n.LBB35_42:\n\tmovl\t$9964, %edi # imm = 0x26EC\n\tjmp\t.LBB35_3\n.LBB35_46:\n\tmovl\t$9965, %edi # imm = 0x26ED\n\tjmp\t.LBB35_3\n.LBB35_32:\n\tmovl\t$9960, %edi # imm = 0x26E8\n\tjmp\t.LBB35_3\n.LBB35_64:\n\tmovl\t$9973, %edi # imm = 0x26F5\n\tjmp\t.LBB35_3\n.LBB35_30:\n\tmovl\t$9959, %edi # imm = 0x26E7\n\tjmp\t.LBB35_3\n.LBB35_49:\n\tmovl\t$9967, %edi # imm = 0x26EF\n\tjmp\t.LBB35_3\n.LBB35_21:\n\tmovl\t$9954, %edi # imm = 0x26E2\n\tjmp\t.LBB35_3\n.LBB35_73:\n\tmovl\t$9936, %edi # imm = 0x26D0\n\tjmp\t.LBB35_3\n.LBB35_51:\n\tmovl\t$9969, %edi # imm = 0x26F1\n\tjmp\t.LBB35_3\n.LBB35_10:\n\tmovl\t$9949, %edi # imm = 0x26DD\n\tjmp\t.LBB35_3\n.LBB35_34:\n\tmovl\t$9962, %edi # imm = 0x26EA\n\tjmp\t.LBB35_3\n.LBB35_52:\n\tmovl\t$9970, %edi # imm = 0x26F2\n\tjmp\t.LBB35_3\n.LBB35_20:\n\tmovl\t$9953, %edi # imm = 0x26E1\n\tjmp\t.LBB35_3\n.LBB35_40:\n\tmovl\t$9963, %edi # imm = 0x26EB\n\tjmp\t.LBB35_3\n.LBB35_60:\n\tmovl\t$9972, %edi # imm = 0x26F4\n\tjmp\t.LBB35_3\n.LBB35_76:\n\tmovl\t$9978, %edi # imm = 0x26FA\n.LBB35_3:\n\tcallq\t_ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE\n\tmovl\t%eax, %ebx\n.LBB35_82:\n\tmovl\t%ebx, %eax\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB35_81:\n\t.cfi_def_cfa_offset 16\n\tcallq\t_ZN6thrust6system15system_categoryEv\n\tmovq\t%rax, %rdx\n\tjmp\t.LBB35_82\n.Lfunc_end35:\n\t.size\t_ZNK6thrust6system6detail21system_error_category23default_error_conditionEi, .Lfunc_end35-_ZNK6thrust6system6detail21system_error_category23default_error_conditionEi\n\t.cfi_endproc\n\t.section\t.rodata._ZNK6thrust6system6detail21system_error_category23default_error_conditionEi,\"aG\",@progbits,_ZNK6thrust6system6detail21system_error_category23default_error_conditionEi,comdat\n\t.p2align\t3, 0x0\n.LJTI35_0:\n\t.quad\t.LBB35_2\n\t.quad\t.LBB35_4\n\t.quad\t.LBB35_5\n\t.quad\t.LBB35_6\n\t.quad\t.LBB35_11\n\t.quad\t.LBB35_13\n\t.quad\t.LBB35_14\n\t.quad\t.LBB35_15\n\t.quad\t.LBB35_16\n\t.quad\t.LBB35_18\n\t.quad\t.LBB35_26\n\t.quad\t.LBB35_27\n\t.quad\t.LBB35_35\n\t.quad\t.LBB35_36\n\t.quad\t.LBB35_37\n\t.quad\t.LBB35_38\n\t.quad\t.LBB35_39\n\t.quad\t.LBB35_41\n\t.quad\t.LBB35_43\n\t.quad\t.LBB35_44\n\t.quad\t.LBB35_45\n\t.quad\t.LBB35_47\n\t.quad\t.LBB35_53\n\t.quad\t.LBB35_54\n\t.quad\t.LBB35_55\n\t.quad\t.LBB35_57\n\t.quad\t.LBB35_58\n\t.quad\t.LBB35_59\n\t.quad\t.LBB35_61\n\t.quad\t.LBB35_62\n\t.quad\t.LBB35_63\n\t.quad\t.LBB35_65\n\t.quad\t.LBB35_66\n\t.quad\t.LBB35_71\n\t.quad\t.LBB35_72\n\t.quad\t.LBB35_73\n\t.quad\t.LBB35_81\n\t.quad\t.LBB35_74\n\t.quad\t.LBB35_78\n\t.quad\t.LBB35_79\n\t.quad\t.LBB35_80\n\t.quad\t.LBB35_25\n\t.quad\t.LBB35_31\n\t.quad\t.LBB35_70\n\t.quad\t.LBB35_28\n\t.quad\t.LBB35_7\n\t.quad\t.LBB35_8\n\t.quad\t.LBB35_9\n\t.quad\t.LBB35_10\n\t.quad\t.LBB35_12\n\t.quad\t.LBB35_17\n\t.quad\t.LBB35_19\n\t.quad\t.LBB35_20\n\t.quad\t.LBB35_21\n\t.quad\t.LBB35_22\n\t.quad\t.LBB35_23\n\t.quad\t.LBB35_24\n\t.quad\t.LBB35_29\n\t.quad\t.LBB35_30\n\t.quad\t.LBB35_32\n\t.quad\t.LBB35_33\n\t.quad\t.LBB35_34\n\t.quad\t.LBB35_40\n\t.quad\t.LBB35_42\n\t.quad\t.LBB35_46\n\t.quad\t.LBB35_48\n\t.quad\t.LBB35_49\n\t.quad\t.LBB35_50\n\t.quad\t.LBB35_51\n\t.quad\t.LBB35_52\n\t.quad\t.LBB35_56\n\t.quad\t.LBB35_60\n\t.quad\t.LBB35_64\n\t.quad\t.LBB35_67\n\t.quad\t.LBB35_68\n\t.quad\t.LBB35_69\n\t.quad\t.LBB35_75\n\t.quad\t.LBB35_76\n\t.quad\t.LBB35_77\n # -- End function\n\t.section\t.text._ZNK6thrust6system6detail21system_error_category7messageB5cxx11Ei,\"axG\",@progbits,_ZNK6thrust6system6detail21system_error_category7messageB5cxx11Ei,comdat\n\t.weak\t_ZNK6thrust6system6detail21system_error_category7messageB5cxx11Ei # -- Begin function _ZNK6thrust6system6detail21system_error_category7messageB5cxx11Ei\n\t.p2align\t4, 0x90\n\t.type\t_ZNK6thrust6system6detail21system_error_category7messageB5cxx11Ei,@function\n_ZNK6thrust6system6detail21system_error_category7messageB5cxx11Ei: # @_ZNK6thrust6system6detail21system_error_category7messageB5cxx11Ei\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rbp\n\t.cfi_def_cfa_offset 16\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 24\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 32\n\t.cfi_offset %rbx, -24\n\t.cfi_offset %rbp, -16\n\tmovq\t%rdi, %rbx\n\tmovzbl\t_ZGVZN6thrust6system16generic_categoryEvE6result(%rip), %eax\n\ttestb\t%al, %al\n\tje\t.LBB36_1\n.LBB36_3:\n\tmovq\t_ZZN6thrust6system16generic_categoryEvE6result(%rip), %rax\n\tmovl\t$_ZZN6thrust6system16generic_categoryEvE6result, %esi\n\tmovq\t%rbx, %rdi\n\tcallq\t*48(%rax)\n\tmovq\t%rbx, %rax\n\taddq\t$8, %rsp\n\t.cfi_def_cfa_offset 24\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 16\n\tpopq\t%rbp\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB36_1:\n\t.cfi_def_cfa_offset 32\n\tmovl\t$_ZGVZN6thrust6system16generic_categoryEvE6result, %edi\n\tmovl\t%edx, %ebp\n\tcallq\t__cxa_guard_acquire\n\tmovl\t%ebp, %edx\n\ttestl\t%eax, %eax\n\tje\t.LBB36_3\n# %bb.2:\n\tmovq\t$_ZTVN6thrust6system6detail22generic_error_categoryE+16, _ZZN6thrust6system16generic_categoryEvE6result(%rip)\n\tmovl\t$_ZN6thrust6system14error_categoryD2Ev, %edi\n\tmovl\t$_ZZN6thrust6system16generic_categoryEvE6result, %esi\n\tmovl\t$__dso_handle, %edx\n\tcallq\t__cxa_atexit\n\tmovl\t$_ZGVZN6thrust6system16generic_categoryEvE6result, %edi\n\tcallq\t__cxa_guard_release\n\tmovl\t%ebp, %edx\n\tjmp\t.LBB36_3\n.Lfunc_end36:\n\t.size\t_ZNK6thrust6system6detail21system_error_category7messageB5cxx11Ei, .Lfunc_end36-_ZNK6thrust6system6detail21system_error_category7messageB5cxx11Ei\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE,\"axG\",@progbits,_ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE,comdat\n\t.weak\t_ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE # -- Begin function _ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE,@function\n_ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE: # @_ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE\n\t.cfi_startproc\n# %bb.0:\n\tmovl\t%edi, %eax\n\tmovzbl\t_ZGVZN6thrust6system16generic_categoryEvE6result(%rip), %ecx\n\ttestb\t%cl, %cl\n\tje\t.LBB37_1\n# %bb.4:\n\tmovl\t$_ZZN6thrust6system16generic_categoryEvE6result, %edx\n\tretq\n.LBB37_1:\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 16\n\t.cfi_offset %rbx, -16\n\tmovl\t$_ZGVZN6thrust6system16generic_categoryEvE6result, %edi\n\tmovl\t%eax, %ebx\n\tcallq\t__cxa_guard_acquire\n\tmovl\t%eax, %ecx\n\tmovl\t%ebx, %eax\n\ttestl\t%ecx, %ecx\n\tje\t.LBB37_3\n# %bb.2:\n\tmovq\t$_ZTVN6thrust6system6detail22generic_error_categoryE+16, _ZZN6thrust6system16generic_categoryEvE6result(%rip)\n\tmovl\t$_ZN6thrust6system14error_categoryD2Ev, %edi\n\tmovl\t$_ZZN6thrust6system16generic_categoryEvE6result, %esi\n\tmovl\t$__dso_handle, %edx\n\tcallq\t__cxa_atexit\n\tmovl\t$_ZGVZN6thrust6system16generic_categoryEvE6result, %edi\n\tcallq\t__cxa_guard_release\n\tmovl\t%ebx, %eax\n.LBB37_3:\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 8\n\t.cfi_restore %rbx\n\tmovl\t$_ZZN6thrust6system16generic_categoryEvE6result, %edx\n\tretq\n.Lfunc_end37:\n\t.size\t_ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE, .Lfunc_end37-_ZN6thrust6system20make_error_conditionENS0_4errc6errc_tE\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust6system6detail22generic_error_categoryD0Ev,\"axG\",@progbits,_ZN6thrust6system6detail22generic_error_categoryD0Ev,comdat\n\t.weak\t_ZN6thrust6system6detail22generic_error_categoryD0Ev # -- Begin function _ZN6thrust6system6detail22generic_error_categoryD0Ev\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6system6detail22generic_error_categoryD0Ev,@function\n_ZN6thrust6system6detail22generic_error_categoryD0Ev: # @_ZN6thrust6system6detail22generic_error_categoryD0Ev\n\t.cfi_startproc\n# %bb.0:\n\tjmp\t_ZdlPv # TAILCALL\n.Lfunc_end38:\n\t.size\t_ZN6thrust6system6detail22generic_error_categoryD0Ev, .Lfunc_end38-_ZN6thrust6system6detail22generic_error_categoryD0Ev\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZNK6thrust6system6detail22generic_error_category4nameEv,\"axG\",@progbits,_ZNK6thrust6system6detail22generic_error_category4nameEv,comdat\n\t.weak\t_ZNK6thrust6system6detail22generic_error_category4nameEv # -- Begin function _ZNK6thrust6system6detail22generic_error_category4nameEv\n\t.p2align\t4, 0x90\n\t.type\t_ZNK6thrust6system6detail22generic_error_category4nameEv,@function\n_ZNK6thrust6system6detail22generic_error_category4nameEv: # @_ZNK6thrust6system6detail22generic_error_category4nameEv\n\t.cfi_startproc\n# %bb.0:\n\tmovl\t$.L.str.5, %eax\n\tretq\n.Lfunc_end39:\n\t.size\t_ZNK6thrust6system6detail22generic_error_category4nameEv, .Lfunc_end39-_ZNK6thrust6system6detail22generic_error_category4nameEv\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei,\"axG\",@progbits,_ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei,comdat\n\t.weak\t_ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei # -- Begin function _ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei\n\t.p2align\t4, 0x90\n\t.type\t_ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei,@function\n_ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei: # @_ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei\n.Lfunc_begin9:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception9\n# %bb.0:\n\tpushq\t%rbp\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r15\n\t.cfi_def_cfa_offset 24\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 32\n\tpushq\t%r12\n\t.cfi_def_cfa_offset 40\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 48\n\tsubq\t$16, %rsp\n\t.cfi_def_cfa_offset 64\n\t.cfi_offset %rbx, -48\n\t.cfi_offset %r12, -40\n\t.cfi_offset %r14, -32\n\t.cfi_offset %r15, -24\n\t.cfi_offset %rbp, -16\n\tmovl\t%edx, %ebp\n\tmovq\t%rdi, %rbx\n\tmovzbl\t_ZGVZNK6thrust6system6detail22generic_error_category7messageB5cxx11EiE11unknown_errB5cxx11(%rip), %eax\n\ttestb\t%al, %al\n\tje\t.LBB40_1\n.LBB40_4:\n\tmovl\t%ebp, %edi\n\tcallq\tstrerror\n\tleaq\t16(%rbx), %r14\n\tmovq\t%r14, (%rbx)\n\ttestq\t%rax, %rax\n\tje\t.LBB40_10\n# %bb.5:\n\tmovq\t%rax, %r15\n\tmovq\t%rax, %rdi\n\tcallq\tstrlen\n\tmovq\t%rax, %r12\n\tmovq\t%rax, 8(%rsp)\n\tcmpq\t$16, %rax\n\tjb\t.LBB40_7\n.LBB40_6:\n\tleaq\t8(%rsp), %rsi\n\tmovq\t%rbx, %rdi\n\txorl\t%edx, %edx\n\tcallq\t_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm\n\tmovq\t%rax, %r14\n\tmovq\t%rax, (%rbx)\n\tmovq\t8(%rsp), %rax\n\tmovq\t%rax, 16(%rbx)\n.LBB40_7:\n\ttestq\t%r12, %r12\n\tje\t.LBB40_12\n# %bb.8:\n\tcmpq\t$1, %r12\n\tjne\t.LBB40_11\n# %bb.9:\n\tmovzbl\t(%r15), %eax\n\tmovb\t%al, (%r14)\n\tjmp\t.LBB40_12\n.LBB40_10:\n\tmovq\t_ZZNK6thrust6system6detail22generic_error_category7messageB5cxx11EiE11unknown_errB5cxx11(%rip), %r15\n\tmovq\t_ZZNK6thrust6system6detail22generic_error_category7messageB5cxx11EiE11unknown_errB5cxx11+8(%rip), %r12\n\tmovq\t%r12, 8(%rsp)\n\tcmpq\t$16, %r12\n\tjae\t.LBB40_6\n\tjmp\t.LBB40_7\n.LBB40_11:\n\tmovq\t%r14, %rdi\n\tmovq\t%r15, %rsi\n\tmovq\t%r12, %rdx\n\tcallq\tmemcpy@PLT\n.LBB40_12:\n\tmovq\t8(%rsp), %rax\n\tmovq\t%rax, 8(%rbx)\n\tmovq\t(%rbx), %rcx\n\tmovb\t$0, (%rcx,%rax)\n\tmovq\t%rbx, %rax\n\taddq\t$16, %rsp\n\t.cfi_def_cfa_offset 48\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 40\n\tpopq\t%r12\n\t.cfi_def_cfa_offset 32\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r15\n\t.cfi_def_cfa_offset 16\n\tpopq\t%rbp\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB40_1:\n\t.cfi_def_cfa_offset 64\n\tmovl\t$_ZGVZNK6thrust6system6detail22generic_error_category7messageB5cxx11EiE11unknown_errB5cxx11, %edi\n\tcallq\t__cxa_guard_acquire\n\ttestl\t%eax, %eax\n\tje\t.LBB40_4\n# %bb.2:\n.Ltmp173:\n\tleaq\t8(%rsp), %rdx\n\tmovl\t$_ZZNK6thrust6system6detail22generic_error_category7messageB5cxx11EiE11unknown_errB5cxx11, %edi\n\tmovl\t$.L.str.6, %esi\n\tcallq\t_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_\n.Ltmp174:\n# %bb.3:\n\tmovl\t$_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev, %edi\n\tmovl\t$_ZZNK6thrust6system6detail22generic_error_category7messageB5cxx11EiE11unknown_errB5cxx11, %esi\n\tmovl\t$__dso_handle, %edx\n\tcallq\t__cxa_atexit\n\tmovl\t$_ZGVZNK6thrust6system6detail22generic_error_category7messageB5cxx11EiE11unknown_errB5cxx11, %edi\n\tcallq\t__cxa_guard_release\n\tjmp\t.LBB40_4\n.LBB40_13:\n.Ltmp175:\n\tmovq\t%rax, %rbx\n\tmovl\t$_ZGVZNK6thrust6system6detail22generic_error_category7messageB5cxx11EiE11unknown_errB5cxx11, %edi\n\tcallq\t__cxa_guard_abort\n\tmovq\t%rbx, %rdi\n\tcallq\t_Unwind_Resume@PLT\n.Lfunc_end40:\n\t.size\t_ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei, .Lfunc_end40-_ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei\n\t.cfi_endproc\n\t.section\t.gcc_except_table._ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei,\"aG\",@progbits,_ZNK6thrust6system6detail22generic_error_category7messageB5cxx11Ei,comdat\n\t.p2align\t2, 0x0\nGCC_except_table40:\n.Lexception9:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t255 # @TType Encoding = omit\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end9-.Lcst_begin9\n.Lcst_begin9:\n\t.uleb128 .Lfunc_begin9-.Lfunc_begin9 # >> Call Site 1 <<\n\t.uleb128 .Ltmp173-.Lfunc_begin9 # Call between .Lfunc_begin9 and .Ltmp173\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp173-.Lfunc_begin9 # >> Call Site 2 <<\n\t.uleb128 .Ltmp174-.Ltmp173 # Call between .Ltmp173 and .Ltmp174\n\t.uleb128 .Ltmp175-.Lfunc_begin9 # jumps to .Ltmp175\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp174-.Lfunc_begin9 # >> Call Site 3 <<\n\t.uleb128 .Lfunc_end40-.Ltmp174 # Call between .Ltmp174 and .Lfunc_end40\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n.Lcst_end9:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text.__clang_call_terminate,\"axG\",@progbits,__clang_call_terminate,comdat\n\t.hidden\t__clang_call_terminate # -- Begin function __clang_call_terminate\n\t.weak\t__clang_call_terminate\n\t.p2align\t4, 0x90\n\t.type\t__clang_call_terminate,@function\n__clang_call_terminate: # @__clang_call_terminate\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 16\n\tcallq\t__cxa_begin_catch\n\tcallq\t_ZSt9terminatev\n.Lfunc_end41:\n\t.size\t__clang_call_terminate, .Lfunc_end41-__clang_call_terminate\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust6system6detail9bad_allocD0Ev,\"axG\",@progbits,_ZN6thrust6system6detail9bad_allocD0Ev,comdat\n\t.weak\t_ZN6thrust6system6detail9bad_allocD0Ev # -- Begin function _ZN6thrust6system6detail9bad_allocD0Ev\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6system6detail9bad_allocD0Ev,@function\n_ZN6thrust6system6detail9bad_allocD0Ev: # @_ZN6thrust6system6detail9bad_allocD0Ev\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 16\n\t.cfi_offset %rbx, -16\n\tmovq\t%rdi, %rbx\n\tmovq\t$_ZTVN6thrust6system6detail9bad_allocE+16, (%rdi)\n\tmovq\t8(%rdi), %rdi\n\tleaq\t24(%rbx), %rax\n\tcmpq\t%rax, %rdi\n\tje\t.LBB42_2\n# %bb.1:\n\tcallq\t_ZdlPv\n.LBB42_2:\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZNSt9bad_allocD2Ev\n\tmovq\t%rbx, %rdi\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 8\n\tjmp\t_ZdlPv # TAILCALL\n.Lfunc_end42:\n\t.size\t_ZN6thrust6system6detail9bad_allocD0Ev, .Lfunc_end42-_ZN6thrust6system6detail9bad_allocD0Ev\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZNK6thrust6system6detail9bad_alloc4whatEv,\"axG\",@progbits,_ZNK6thrust6system6detail9bad_alloc4whatEv,comdat\n\t.weak\t_ZNK6thrust6system6detail9bad_alloc4whatEv # -- Begin function _ZNK6thrust6system6detail9bad_alloc4whatEv\n\t.p2align\t4, 0x90\n\t.type\t_ZNK6thrust6system6detail9bad_alloc4whatEv,@function\n_ZNK6thrust6system6detail9bad_alloc4whatEv: # @_ZNK6thrust6system6detail9bad_alloc4whatEv\n\t.cfi_startproc\n# %bb.0:\n\tmovq\t8(%rdi), %rax\n\tretq\n.Lfunc_end43:\n\t.size\t_ZNK6thrust6system6detail9bad_alloc4whatEv, .Lfunc_end43-_ZNK6thrust6system6detail9bad_alloc4whatEv\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc,\"axG\",@progbits,_ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc,comdat\n\t.weak\t_ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc # -- Begin function _ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc,@function\n_ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc: # @_ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rbp\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 32\n\t.cfi_offset %rbx, -32\n\t.cfi_offset %r14, -24\n\t.cfi_offset %rbp, -16\n\tmovq\t%rdx, %rbx\n\tmovl\t%esi, %ebp\n\tmovq\t%rdi, %r14\n\tmovq\t%rcx, %rsi\n\tcallq\t_ZNSt13runtime_errorC2EPKc\n\tmovq\t$_ZTVN6thrust6system12system_errorE+16, (%r14)\n\tmovl\t%ebp, 16(%r14)\n\tmovq\t%rbx, 24(%r14)\n\tleaq\t48(%r14), %rax\n\tmovq\t%rax, 32(%r14)\n\tmovq\t$0, 40(%r14)\n\tmovb\t$0, 48(%r14)\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 16\n\tpopq\t%rbp\n\t.cfi_def_cfa_offset 8\n\tretq\n.Lfunc_end44:\n\t.size\t_ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc, .Lfunc_end44-_ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust6system12system_errorD2Ev,\"axG\",@progbits,_ZN6thrust6system12system_errorD2Ev,comdat\n\t.weak\t_ZN6thrust6system12system_errorD2Ev # -- Begin function _ZN6thrust6system12system_errorD2Ev\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6system12system_errorD2Ev,@function\n_ZN6thrust6system12system_errorD2Ev: # @_ZN6thrust6system12system_errorD2Ev\n\t.cfi_startproc\n# %bb.0:\n\tmovq\t$_ZTVN6thrust6system12system_errorE+16, (%rdi)\n\tmovq\t32(%rdi), %rax\n\tleaq\t48(%rdi), %rcx\n\tcmpq\t%rcx, %rax\n\tje\t_ZNSt13runtime_errorD2Ev # TAILCALL\n# %bb.1:\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 16\n\t.cfi_offset %rbx, -16\n\tmovq\t%rdi, %rbx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZdlPv\n\tmovq\t%rbx, %rdi\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 8\n\t.cfi_restore %rbx\n\tjmp\t_ZNSt13runtime_errorD2Ev # TAILCALL\n.Lfunc_end45:\n\t.size\t_ZN6thrust6system12system_errorD2Ev, .Lfunc_end45-_ZN6thrust6system12system_errorD2Ev\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust6system12system_errorD0Ev,\"axG\",@progbits,_ZN6thrust6system12system_errorD0Ev,comdat\n\t.weak\t_ZN6thrust6system12system_errorD0Ev # -- Begin function _ZN6thrust6system12system_errorD0Ev\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6system12system_errorD0Ev,@function\n_ZN6thrust6system12system_errorD0Ev: # @_ZN6thrust6system12system_errorD0Ev\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 16\n\t.cfi_offset %rbx, -16\n\tmovq\t%rdi, %rbx\n\tmovq\t$_ZTVN6thrust6system12system_errorE+16, (%rdi)\n\tmovq\t32(%rdi), %rdi\n\tleaq\t48(%rbx), %rax\n\tcmpq\t%rax, %rdi\n\tje\t.LBB46_2\n# %bb.1:\n\tcallq\t_ZdlPv\n.LBB46_2:\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZNSt13runtime_errorD2Ev\n\tmovq\t%rbx, %rdi\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 8\n\tjmp\t_ZdlPv # TAILCALL\n.Lfunc_end46:\n\t.size\t_ZN6thrust6system12system_errorD0Ev, .Lfunc_end46-_ZN6thrust6system12system_errorD0Ev\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZNK6thrust6system12system_error4whatEv,\"axG\",@progbits,_ZNK6thrust6system12system_error4whatEv,comdat\n\t.weak\t_ZNK6thrust6system12system_error4whatEv # -- Begin function _ZNK6thrust6system12system_error4whatEv\n\t.p2align\t4, 0x90\n\t.type\t_ZNK6thrust6system12system_error4whatEv,@function\n_ZNK6thrust6system12system_error4whatEv: # @_ZNK6thrust6system12system_error4whatEv\n.Lfunc_begin10:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception10\n# %bb.0:\n\tpushq\t%r15\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpushq\t%r12\n\t.cfi_def_cfa_offset 32\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 40\n\tsubq\t$40, %rsp\n\t.cfi_def_cfa_offset 80\n\t.cfi_offset %rbx, -40\n\t.cfi_offset %r12, -32\n\t.cfi_offset %r14, -24\n\t.cfi_offset %r15, -16\n\tleaq\t32(%rdi), %r14\n\tcmpq\t$0, 40(%rdi)\n\tje\t.LBB47_3\n.LBB47_1:\n\tmovq\t(%r14), %rax\n.LBB47_2:\n\taddq\t$40, %rsp\n\t.cfi_def_cfa_offset 40\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 32\n\tpopq\t%r12\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 16\n\tpopq\t%r15\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB47_3:\n\t.cfi_def_cfa_offset 80\n\tmovq\t%rdi, %rbx\n\tcallq\t_ZNKSt13runtime_error4whatEv\n\tmovq\t%rax, %r15\n\tmovq\t40(%rbx), %r12\n\tmovq\t%rax, %rdi\n\tcallq\tstrlen\n.Ltmp176:\n\tmovq\t%r14, %rdi\n\txorl\t%esi, %esi\n\tmovq\t%r12, %rdx\n\tmovq\t%r15, %rcx\n\tmovq\t%rax, %r8\n\tcallq\t_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm\n.Ltmp177:\n# %bb.4:\n\tmovl\t16(%rbx), %edx\n\ttestl\t%edx, %edx\n\tje\t.LBB47_1\n# %bb.5:\n\tmovabsq\t$4611686018427387902, %r15 # imm = 0x3FFFFFFFFFFFFFFE\n\tmovq\t40(%rbx), %rax\n\ttestq\t%rax, %rax\n\tje\t.LBB47_9\n# %bb.6:\n\tandq\t$-2, %rax\n\tcmpq\t%r15, %rax\n\tje\t.LBB47_16\n# %bb.7:\n.Ltmp178:\n\tmovl\t$.L.str.9, %esi\n\tmovl\t$2, %edx\n\tmovq\t%r14, %rdi\n\tcallq\t_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm\n.Ltmp179:\n# %bb.8:\n\tmovl\t16(%rbx), %edx\n.LBB47_9:\n\tmovq\t24(%rbx), %rsi\n\tmovq\t(%rsi), %rax\n.Ltmp183:\n\tleaq\t8(%rsp), %rdi\n\tcallq\t*48(%rax)\n.Ltmp184:\n# %bb.10:\n\tmovq\t16(%rsp), %rdx\n\tsubq\t40(%rbx), %r15\n\tincq\t%r15\n\tcmpq\t%rdx, %r15\n\tjb\t.LBB47_14\n# %bb.11:\n\tmovq\t8(%rsp), %rsi\n.Ltmp186:\n\tmovq\t%r14, %rdi\n\tcallq\t_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm\n.Ltmp187:\n# %bb.12:\n\tmovq\t8(%rsp), %rdi\n\tleaq\t24(%rsp), %rax\n\tcmpq\t%rax, %rdi\n\tje\t.LBB47_1\n# %bb.13:\n\tcallq\t_ZdlPv\n\tjmp\t.LBB47_1\n.LBB47_14:\n.Ltmp188:\n\tmovl\t$.L.str.10, %edi\n\tcallq\t_ZSt20__throw_length_errorPKc\n.Ltmp189:\n# %bb.15:\n.LBB47_16:\n.Ltmp180:\n\tmovl\t$.L.str.10, %edi\n\tcallq\t_ZSt20__throw_length_errorPKc\n.Ltmp181:\n# %bb.17:\n.LBB47_18:\n.Ltmp185:\n\tjmp\t.LBB47_22\n.LBB47_19:\n.Ltmp190:\n\tmovq\t%rax, %r14\n\tmovq\t8(%rsp), %rdi\n\tleaq\t24(%rsp), %rax\n\tcmpq\t%rax, %rdi\n\tje\t.LBB47_23\n# %bb.20:\n\tcallq\t_ZdlPv\n\tjmp\t.LBB47_23\n.LBB47_21:\n.Ltmp182:\n.LBB47_22:\n\tmovq\t%rax, %r14\n.LBB47_23:\n\tmovq\t%r14, %rdi\n\tcallq\t__cxa_begin_catch\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZNKSt13runtime_error4whatEv\n\tmovq\t%rax, %rbx\n.Ltmp191:\n\tcallq\t__cxa_end_catch\n.Ltmp192:\n# %bb.24:\n\tmovq\t%rbx, %rax\n\tjmp\t.LBB47_2\n.LBB47_25:\n.Ltmp193:\n\tmovq\t%rax, %rdi\n\tcallq\t__clang_call_terminate\n.Lfunc_end47:\n\t.size\t_ZNK6thrust6system12system_error4whatEv, .Lfunc_end47-_ZNK6thrust6system12system_error4whatEv\n\t.cfi_endproc\n\t.section\t.gcc_except_table._ZNK6thrust6system12system_error4whatEv,\"aG\",@progbits,_ZNK6thrust6system12system_error4whatEv,comdat\n\t.p2align\t2, 0x0\nGCC_except_table47:\n.Lexception10:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t3 # @TType Encoding = udata4\n\t.uleb128 .Lttbase4-.Lttbaseref4\n.Lttbaseref4:\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end10-.Lcst_begin10\n.Lcst_begin10:\n\t.uleb128 .Ltmp176-.Lfunc_begin10 # >> Call Site 1 <<\n\t.uleb128 .Ltmp179-.Ltmp176 # Call between .Ltmp176 and .Ltmp179\n\t.uleb128 .Ltmp182-.Lfunc_begin10 # jumps to .Ltmp182\n\t.byte\t1 # On action: 1\n\t.uleb128 .Ltmp183-.Lfunc_begin10 # >> Call Site 2 <<\n\t.uleb128 .Ltmp184-.Ltmp183 # Call between .Ltmp183 and .Ltmp184\n\t.uleb128 .Ltmp185-.Lfunc_begin10 # jumps to .Ltmp185\n\t.byte\t1 # On action: 1\n\t.uleb128 .Ltmp186-.Lfunc_begin10 # >> Call Site 3 <<\n\t.uleb128 .Ltmp189-.Ltmp186 # Call between .Ltmp186 and .Ltmp189\n\t.uleb128 .Ltmp190-.Lfunc_begin10 # jumps to .Ltmp190\n\t.byte\t1 # On action: 1\n\t.uleb128 .Ltmp180-.Lfunc_begin10 # >> Call Site 4 <<\n\t.uleb128 .Ltmp181-.Ltmp180 # Call between .Ltmp180 and .Ltmp181\n\t.uleb128 .Ltmp182-.Lfunc_begin10 # jumps to .Ltmp182\n\t.byte\t1 # On action: 1\n\t.uleb128 .Ltmp181-.Lfunc_begin10 # >> Call Site 5 <<\n\t.uleb128 .Ltmp191-.Ltmp181 # Call between .Ltmp181 and .Ltmp191\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp191-.Lfunc_begin10 # >> Call Site 6 <<\n\t.uleb128 .Ltmp192-.Ltmp191 # Call between .Ltmp191 and .Ltmp192\n\t.uleb128 .Ltmp193-.Lfunc_begin10 # jumps to .Ltmp193\n\t.byte\t1 # On action: 1\n.Lcst_end10:\n\t.byte\t1 # >> Action Record 1 <<\n # Catch TypeInfo 1\n\t.byte\t0 # No further actions\n\t.p2align\t2, 0x0\n # >> Catch TypeInfos <<\n\t.long\t0 # TypeInfo 1\n.Lttbase4:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text._ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m,\"axG\",@progbits,_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m,comdat\n\t.weak\t_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m # -- Begin function _ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m\n\t.p2align\t4, 0x90\n\t.type\t_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m,@function\n_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m: # @_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m\n.Lfunc_begin11:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception11\n# %bb.0:\n\tpushq\t%rbp\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r15\n\t.cfi_def_cfa_offset 24\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 32\n\tpushq\t%r13\n\t.cfi_def_cfa_offset 40\n\tpushq\t%r12\n\t.cfi_def_cfa_offset 48\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 56\n\tsubq\t$136, %rsp\n\t.cfi_def_cfa_offset 192\n\t.cfi_offset %rbx, -56\n\t.cfi_offset %r12, -48\n\t.cfi_offset %r13, -40\n\t.cfi_offset %r14, -32\n\t.cfi_offset %r15, -24\n\t.cfi_offset %rbp, -16\n\tmovl\t%edx, 12(%rsp) # 4-byte Spill\n\tmovq\t%rsi, 24(%rsp) # 8-byte Spill\n\tmovl\t$4294967040, %r13d # imm = 0xFFFFFF00\n\tmovq\t%rcx, 16(%rsp) # 8-byte Spill\n\taddq\t%r13, %rcx\n\tdecq\t%rcx\n\tshrq\t$8, %rcx\n\tmovabsq\t$72057598332895489, %rdx # imm = 0x100000100000101\n\tmovq\t%rcx, %rax\n\tmulq\t%rdx\n\tcmpq\t$16777215, %rcx # imm = 0xFFFFFF\n\tjae\t.LBB48_1\n.LBB48_5:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipPeekAtLastError\n\tmovl\t%eax, %ebp\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipGetLastError\n\ttestl\t%ebp, %ebp\n\tjne\t.LBB48_6\n# %bb.12:\n\t.cfi_escape 0x2e, 0x00\n\txorl\t%edi, %edi\n\tcallq\thipStreamSynchronize\n\tmovl\t%eax, %ebp\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipGetLastError\n\ttestl\t%ebp, %ebp\n\tjne\t.LBB48_13\n# %bb.17:\n\taddq\t$136, %rsp\n\t.cfi_def_cfa_offset 56\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 48\n\tpopq\t%r12\n\t.cfi_def_cfa_offset 40\n\tpopq\t%r13\n\t.cfi_def_cfa_offset 32\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r15\n\t.cfi_def_cfa_offset 16\n\tpopq\t%rbp\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB48_1:\n\t.cfi_def_cfa_offset 192\n\tmovq\t%rdx, %r15\n\tshrq\t$16, %r15\n\txorl\t%ebp, %ebp\n\tleaq\t512(%r13), %r12\n\tmovabsq\t$-4294967040, %r14 # imm = 0xFFFFFFFF00000100\n\tmovq\t16(%rsp), %rbx # 8-byte Reload\n\tjmp\t.LBB48_2\n\t.p2align\t4, 0x90\n.LBB48_4: # in Loop: Header=BB48_2 Depth=1\n\taddq\t%r13, %rbp\n\taddq\t%r14, %rbx\n\tdecq\t%r15\n\tje\t.LBB48_5\n.LBB48_2: # =>This Inner Loop Header: Depth=1\n\tcmpq\t%r13, %rbx\n\tmovl\t$4294967040, %eax # imm = 0xFFFFFF00\n\tcmovbq\t%rbx, %rax\n\taddq\t$255, %rax\n\tshrq\t$8, %rax\n\tleaq\t(%rax,%r13), %rdi\n\taddq\t$256, %rdi # imm = 0x100\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %esi\n\tmovq\t%r12, %rdx\n\tmovl\t$1, %ecx\n\txorl\t%r8d, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipPushCallConfiguration\n\ttestl\t%eax, %eax\n\tjne\t.LBB48_4\n# %bb.3: # in Loop: Header=BB48_2 Depth=1\n\tmovq\t24(%rsp), %rax # 8-byte Reload\n\tmovq\t%rax, 96(%rsp)\n\tmovl\t12(%rsp), %eax # 4-byte Reload\n\tmovl\t%eax, 104(%rsp)\n\tmovq\t16(%rsp), %rax # 8-byte Reload\n\tmovq\t%rax, 88(%rsp)\n\tmovq\t%rbp, 80(%rsp)\n\tleaq\t96(%rsp), %rax\n\tmovq\t%rax, 112(%rsp)\n\tleaq\t88(%rsp), %rax\n\tmovq\t%rax, 120(%rsp)\n\tleaq\t80(%rsp), %rax\n\tmovq\t%rax, 128(%rsp)\n\t.cfi_escape 0x2e, 0x00\n\tleaq\t64(%rsp), %rdi\n\tleaq\t48(%rsp), %rsi\n\tleaq\t40(%rsp), %rdx\n\tleaq\t32(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t64(%rsp), %rsi\n\tmovl\t72(%rsp), %edx\n\tmovq\t48(%rsp), %rcx\n\tmovl\t56(%rsp), %r8d\n\t.cfi_escape 0x2e, 0x10\n\tmovl\t$_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, %edi\n\tleaq\t112(%rsp), %r9\n\tpushq\t32(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t48(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$16, %rsp\n\t.cfi_adjust_cfa_offset -16\n\tjmp\t.LBB48_4\n.LBB48_6:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$64, %edi\n\tcallq\t__cxa_allocate_exception\n\tmovq\t%rax, %rbx\n.Ltmp194:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\t_ZN6thrust6system12hip_categoryEv\n.Ltmp195:\n# %bb.7:\n.Ltmp196:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.13, %ecx\n\tmovq\t%rbx, %rdi\n\tmovl\t%ebp, %esi\n\tmovq\t%rax, %rdx\n\tcallq\t_ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc\n.Ltmp197:\n# %bb.8:\n\t.cfi_escape 0x2e, 0x00\n\tjmp\t.LBB48_9\n.LBB48_13:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$64, %edi\n\tcallq\t__cxa_allocate_exception\n\tmovq\t%rax, %rbx\n.Ltmp199:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\t_ZN6thrust6system12hip_categoryEv\n.Ltmp200:\n# %bb.14:\n.Ltmp201:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.14, %ecx\n\tmovq\t%rbx, %rdi\n\tmovl\t%ebp, %esi\n\tmovq\t%rax, %rdx\n\tcallq\t_ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc\n.Ltmp202:\n# %bb.15:\n\t.cfi_escape 0x2e, 0x00\n.LBB48_9:\n\tmovl\t$_ZTIN6thrust6system12system_errorE, %esi\n\tmovl\t$_ZN6thrust6system12system_errorD2Ev, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t__cxa_throw\n.LBB48_16:\n.Ltmp203:\n\tjmp\t.LBB48_11\n.LBB48_10:\n.Ltmp198:\n.LBB48_11:\n\tmovq\t%rax, %r14\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tcallq\t__cxa_free_exception\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%r14, %rdi\n\tcallq\t_Unwind_Resume@PLT\n.Lfunc_end48:\n\t.size\t_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m, .Lfunc_end48-_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m\n\t.cfi_endproc\n\t.section\t.gcc_except_table._ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m,\"aG\",@progbits,_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m,comdat\n\t.p2align\t2, 0x0\nGCC_except_table48:\n.Lexception11:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t255 # @TType Encoding = omit\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end11-.Lcst_begin11\n.Lcst_begin11:\n\t.uleb128 .Lfunc_begin11-.Lfunc_begin11 # >> Call Site 1 <<\n\t.uleb128 .Ltmp194-.Lfunc_begin11 # Call between .Lfunc_begin11 and .Ltmp194\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp194-.Lfunc_begin11 # >> Call Site 2 <<\n\t.uleb128 .Ltmp197-.Ltmp194 # Call between .Ltmp194 and .Ltmp197\n\t.uleb128 .Ltmp198-.Lfunc_begin11 # jumps to .Ltmp198\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp197-.Lfunc_begin11 # >> Call Site 3 <<\n\t.uleb128 .Ltmp199-.Ltmp197 # Call between .Ltmp197 and .Ltmp199\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp199-.Lfunc_begin11 # >> Call Site 4 <<\n\t.uleb128 .Ltmp202-.Ltmp199 # Call between .Ltmp199 and .Ltmp202\n\t.uleb128 .Ltmp203-.Lfunc_begin11 # jumps to .Ltmp203\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp202-.Lfunc_begin11 # >> Call Site 5 <<\n\t.uleb128 .Lfunc_end48-.Ltmp202 # Call between .Ltmp202 and .Lfunc_end48\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n.Lcst_end11:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text._ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,\"axG\",@progbits,_ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat\n\t.weak\t_ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ # -- Begin function _ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,@function\n_ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_: # @_ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$104, %rsp\n\t.cfi_def_cfa_offset 112\n\tmovq\t%rdi, 64(%rsp)\n\tmovl\t%esi, 72(%rsp)\n\tmovq\t%rdx, 56(%rsp)\n\tmovq\t%rcx, 48(%rsp)\n\tleaq\t64(%rsp), %rax\n\tmovq\t%rax, 80(%rsp)\n\tleaq\t56(%rsp), %rax\n\tmovq\t%rax, 88(%rsp)\n\tleaq\t48(%rsp), %rax\n\tmovq\t%rax, 96(%rsp)\n\tleaq\t32(%rsp), %rdi\n\tleaq\t16(%rsp), %rsi\n\tleaq\t8(%rsp), %rdx\n\tmovq\t%rsp, %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t32(%rsp), %rsi\n\tmovl\t40(%rsp), %edx\n\tmovq\t16(%rsp), %rcx\n\tmovl\t24(%rsp), %r8d\n\tleaq\t80(%rsp), %r9\n\tmovl\t$_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, %edi\n\tpushq\t(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t16(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$120, %rsp\n\t.cfi_adjust_cfa_offset -120\n\tretq\n.Lfunc_end49:\n\t.size\t_ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, .Lfunc_end49-_ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2Em,\"axG\",@progbits,_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2Em,comdat\n\t.weak\t_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2Em # -- Begin function _ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2Em\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2Em,@function\n_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2Em: # @_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2Em\n.Lfunc_begin12:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception12\n# %bb.0:\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 16\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 24\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 32\n\t.cfi_offset %rbx, -24\n\t.cfi_offset %r14, -16\n\tmovq\t%rsi, %r14\n\tmovq\t%rdi, %rbx\n\tmovzbl\t_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource(%rip), %eax\n\ttestb\t%al, %al\n\tje\t.LBB50_1\n.LBB50_4:\n\tmovq\t$_ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, (%rbx)\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, 8(%rbx)\n\tmovq\t$0, 24(%rbx)\n\ttestq\t%r14, %r14\n\tje\t.LBB50_7\n# %bb.5:\n\tleaq\t(,%r14,4), %rsi\n\tmovq\t_ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource+8(%rip), %rdi\n.Ltmp207:\n\tmovl\t$4, %edx\n\tcallq\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm\n.Ltmp208:\n# %bb.6:\n\tmovq\t%rax, 8(%rbx)\n\tmovq\t%r14, 16(%rbx)\n\tmovq\t%r14, 24(%rbx)\n.Ltmp209:\n\tleaq\t7(%rsp), %rdi\n\txorps\t%xmm0, %xmm0\n\tmovq\t%rax, %rsi\n\tmovq\t%r14, %rdx\n\tcallq\t_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m\n.Ltmp210:\n.LBB50_7:\n\taddq\t$8, %rsp\n\t.cfi_def_cfa_offset 24\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 16\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB50_1:\n\t.cfi_def_cfa_offset 32\n\tmovl\t$_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, %edi\n\tcallq\t__cxa_guard_acquire\n\ttestl\t%eax, %eax\n\tje\t.LBB50_4\n# %bb.2:\n.Ltmp204:\n\tmovl\t$_ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, %edi\n\tcallq\t_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEC2Ev\n.Ltmp205:\n# %bb.3:\n\tmovl\t$_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, %edi\n\tcallq\t__cxa_guard_release\n\tjmp\t.LBB50_4\n.LBB50_8:\n.Ltmp206:\n\tmovq\t%rax, %r14\n\tmovl\t$_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, %edi\n\tcallq\t__cxa_guard_abort\n\tmovq\t%r14, %rdi\n\tcallq\t_Unwind_Resume@PLT\n.LBB50_10:\n.Ltmp211:\n\tmovq\t%rax, %r14\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZN6thrust6detail18contiguous_storageIfNS_16device_allocatorIfEEED2Ev\n\tmovq\t%r14, %rdi\n\tcallq\t_Unwind_Resume@PLT\n.Lfunc_end50:\n\t.size\t_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2Em, .Lfunc_end50-_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2Em\n\t.cfi_endproc\n\t.section\t.gcc_except_table._ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2Em,\"aG\",@progbits,_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2Em,comdat\n\t.p2align\t2, 0x0\nGCC_except_table50:\n.Lexception12:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t255 # @TType Encoding = omit\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end12-.Lcst_begin12\n.Lcst_begin12:\n\t.uleb128 .Ltmp207-.Lfunc_begin12 # >> Call Site 1 <<\n\t.uleb128 .Ltmp210-.Ltmp207 # Call between .Ltmp207 and .Ltmp210\n\t.uleb128 .Ltmp211-.Lfunc_begin12 # jumps to .Ltmp211\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp204-.Lfunc_begin12 # >> Call Site 2 <<\n\t.uleb128 .Ltmp205-.Ltmp204 # Call between .Ltmp204 and .Ltmp205\n\t.uleb128 .Ltmp206-.Lfunc_begin12 # jumps to .Ltmp206\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp205-.Lfunc_begin12 # >> Call Site 3 <<\n\t.uleb128 .Lfunc_end50-.Ltmp205 # Call between .Ltmp205 and .Lfunc_end50\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n.Lcst_end12:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text._ZN6thrust6detail18contiguous_storageIfNS_16device_allocatorIfEEED2Ev,\"axG\",@progbits,_ZN6thrust6detail18contiguous_storageIfNS_16device_allocatorIfEEED2Ev,comdat\n\t.weak\t_ZN6thrust6detail18contiguous_storageIfNS_16device_allocatorIfEEED2Ev # -- Begin function _ZN6thrust6detail18contiguous_storageIfNS_16device_allocatorIfEEED2Ev\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6detail18contiguous_storageIfNS_16device_allocatorIfEEED2Ev,@function\n_ZN6thrust6detail18contiguous_storageIfNS_16device_allocatorIfEEED2Ev: # @_ZN6thrust6detail18contiguous_storageIfNS_16device_allocatorIfEEED2Ev\n.Lfunc_begin13:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception13\n# %bb.0:\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 16\n\t.cfi_offset %rbx, -16\n\tmovq\t16(%rdi), %rdx\n\ttestq\t%rdx, %rdx\n\tje\t.LBB51_3\n# %bb.1:\n\tmovq\t%rdi, %rbx\n\tmovq\t(%rdi), %rax\n\tmovq\t8(%rdi), %rsi\n\tshlq\t$2, %rdx\n\tmovq\t8(%rax), %rdi\n.Ltmp212:\n\tmovl\t$4, %ecx\n\tcallq\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE13do_deallocateESA_mm\n.Ltmp213:\n# %bb.2:\n\taddq\t$8, %rbx\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, (%rbx)\n.LBB51_3:\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB51_4:\n\t.cfi_def_cfa_offset 16\n.Ltmp214:\n\tmovq\t%rax, %rdi\n\tcallq\t__clang_call_terminate\n.Lfunc_end51:\n\t.size\t_ZN6thrust6detail18contiguous_storageIfNS_16device_allocatorIfEEED2Ev, .Lfunc_end51-_ZN6thrust6detail18contiguous_storageIfNS_16device_allocatorIfEEED2Ev\n\t.cfi_endproc\n\t.section\t.gcc_except_table._ZN6thrust6detail18contiguous_storageIfNS_16device_allocatorIfEEED2Ev,\"aG\",@progbits,_ZN6thrust6detail18contiguous_storageIfNS_16device_allocatorIfEEED2Ev,comdat\n\t.p2align\t2, 0x0\nGCC_except_table51:\n.Lexception13:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t3 # @TType Encoding = udata4\n\t.uleb128 .Lttbase5-.Lttbaseref5\n.Lttbaseref5:\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end13-.Lcst_begin13\n.Lcst_begin13:\n\t.uleb128 .Ltmp212-.Lfunc_begin13 # >> Call Site 1 <<\n\t.uleb128 .Ltmp213-.Ltmp212 # Call between .Ltmp212 and .Ltmp213\n\t.uleb128 .Ltmp214-.Lfunc_begin13 # jumps to .Ltmp214\n\t.byte\t1 # On action: 1\n.Lcst_end13:\n\t.byte\t1 # >> Action Record 1 <<\n # Catch TypeInfo 1\n\t.byte\t0 # No further actions\n\t.p2align\t2, 0x0\n # >> Catch TypeInfos <<\n\t.long\t0 # TypeInfo 1\n.Lttbase5:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text._ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m,\"axG\",@progbits,_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m,comdat\n\t.weak\t_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m # -- Begin function _ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m\n\t.p2align\t4, 0x90\n\t.type\t_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m,@function\n_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m: # @_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m\n.Lfunc_begin14:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception14\n# %bb.0:\n\tpushq\t%rbp\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r15\n\t.cfi_def_cfa_offset 24\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 32\n\tpushq\t%r13\n\t.cfi_def_cfa_offset 40\n\tpushq\t%r12\n\t.cfi_def_cfa_offset 48\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 56\n\tsubq\t$136, %rsp\n\t.cfi_def_cfa_offset 192\n\t.cfi_offset %rbx, -56\n\t.cfi_offset %r12, -48\n\t.cfi_offset %r13, -40\n\t.cfi_offset %r14, -32\n\t.cfi_offset %r15, -24\n\t.cfi_offset %rbp, -16\n\tmovss\t%xmm0, 12(%rsp) # 4-byte Spill\n\tmovq\t%rsi, 24(%rsp) # 8-byte Spill\n\tmovl\t$4294967040, %ebp # imm = 0xFFFFFF00\n\tmovq\t%rdx, 16(%rsp) # 8-byte Spill\n\tleaq\t(%rdx,%rbp), %rcx\n\tdecq\t%rcx\n\tshrq\t$8, %rcx\n\tmovabsq\t$72057598332895489, %rdx # imm = 0x100000100000101\n\tmovq\t%rcx, %rax\n\tmulq\t%rdx\n\tcmpq\t$16777215, %rcx # imm = 0xFFFFFF\n\tjae\t.LBB52_1\n.LBB52_5:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipPeekAtLastError\n\tmovl\t%eax, %ebp\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipGetLastError\n\ttestl\t%ebp, %ebp\n\tjne\t.LBB52_6\n# %bb.12:\n\t.cfi_escape 0x2e, 0x00\n\txorl\t%edi, %edi\n\tcallq\thipStreamSynchronize\n\tmovl\t%eax, %ebp\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipGetLastError\n\ttestl\t%ebp, %ebp\n\tjne\t.LBB52_13\n# %bb.17:\n\taddq\t$136, %rsp\n\t.cfi_def_cfa_offset 56\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 48\n\tpopq\t%r12\n\t.cfi_def_cfa_offset 40\n\tpopq\t%r13\n\t.cfi_def_cfa_offset 32\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r15\n\t.cfi_def_cfa_offset 16\n\tpopq\t%rbp\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB52_1:\n\t.cfi_def_cfa_offset 192\n\tmovq\t%rdx, %r15\n\tshrq\t$16, %r15\n\txorl\t%r13d, %r13d\n\tleaq\t512(%rbp), %r12\n\tmovabsq\t$-4294967040, %r14 # imm = 0xFFFFFFFF00000100\n\tmovq\t16(%rsp), %rbx # 8-byte Reload\n\tjmp\t.LBB52_2\n\t.p2align\t4, 0x90\n.LBB52_4: # in Loop: Header=BB52_2 Depth=1\n\taddq\t%rbp, %r13\n\taddq\t%r14, %rbx\n\tdecq\t%r15\n\tje\t.LBB52_5\n.LBB52_2: # =>This Inner Loop Header: Depth=1\n\tcmpq\t%rbp, %rbx\n\tmovl\t$4294967040, %eax # imm = 0xFFFFFF00\n\tcmovbq\t%rbx, %rax\n\taddq\t$255, %rax\n\tshrq\t$8, %rax\n\tleaq\t(%rax,%rbp), %rdi\n\taddq\t$256, %rdi # imm = 0x100\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %esi\n\tmovq\t%r12, %rdx\n\tmovl\t$1, %ecx\n\txorl\t%r8d, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipPushCallConfiguration\n\ttestl\t%eax, %eax\n\tjne\t.LBB52_4\n# %bb.3: # in Loop: Header=BB52_2 Depth=1\n\tmovq\t24(%rsp), %rax # 8-byte Reload\n\tmovq\t%rax, 96(%rsp)\n\tmovss\t12(%rsp), %xmm0 # 4-byte Reload\n # xmm0 = mem[0],zero,zero,zero\n\tmovss\t%xmm0, 104(%rsp)\n\tmovq\t16(%rsp), %rax # 8-byte Reload\n\tmovq\t%rax, 88(%rsp)\n\tmovq\t%r13, 80(%rsp)\n\tleaq\t96(%rsp), %rax\n\tmovq\t%rax, 112(%rsp)\n\tleaq\t88(%rsp), %rax\n\tmovq\t%rax, 120(%rsp)\n\tleaq\t80(%rsp), %rax\n\tmovq\t%rax, 128(%rsp)\n\t.cfi_escape 0x2e, 0x00\n\tleaq\t64(%rsp), %rdi\n\tleaq\t48(%rsp), %rsi\n\tleaq\t40(%rsp), %rdx\n\tleaq\t32(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t64(%rsp), %rsi\n\tmovl\t72(%rsp), %edx\n\tmovq\t48(%rsp), %rcx\n\tmovl\t56(%rsp), %r8d\n\t.cfi_escape 0x2e, 0x10\n\tmovl\t$_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, %edi\n\tleaq\t112(%rsp), %r9\n\tpushq\t32(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t48(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$16, %rsp\n\t.cfi_adjust_cfa_offset -16\n\tjmp\t.LBB52_4\n.LBB52_6:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$64, %edi\n\tcallq\t__cxa_allocate_exception\n\tmovq\t%rax, %rbx\n.Ltmp215:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\t_ZN6thrust6system12hip_categoryEv\n.Ltmp216:\n# %bb.7:\n.Ltmp217:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.13, %ecx\n\tmovq\t%rbx, %rdi\n\tmovl\t%ebp, %esi\n\tmovq\t%rax, %rdx\n\tcallq\t_ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc\n.Ltmp218:\n# %bb.8:\n\t.cfi_escape 0x2e, 0x00\n\tjmp\t.LBB52_9\n.LBB52_13:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$64, %edi\n\tcallq\t__cxa_allocate_exception\n\tmovq\t%rax, %rbx\n.Ltmp220:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\t_ZN6thrust6system12hip_categoryEv\n.Ltmp221:\n# %bb.14:\n.Ltmp222:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.14, %ecx\n\tmovq\t%rbx, %rdi\n\tmovl\t%ebp, %esi\n\tmovq\t%rax, %rdx\n\tcallq\t_ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc\n.Ltmp223:\n# %bb.15:\n\t.cfi_escape 0x2e, 0x00\n.LBB52_9:\n\tmovl\t$_ZTIN6thrust6system12system_errorE, %esi\n\tmovl\t$_ZN6thrust6system12system_errorD2Ev, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t__cxa_throw\n.LBB52_16:\n.Ltmp224:\n\tjmp\t.LBB52_11\n.LBB52_10:\n.Ltmp219:\n.LBB52_11:\n\tmovq\t%rax, %r14\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tcallq\t__cxa_free_exception\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%r14, %rdi\n\tcallq\t_Unwind_Resume@PLT\n.Lfunc_end52:\n\t.size\t_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m, .Lfunc_end52-_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m\n\t.cfi_endproc\n\t.section\t.gcc_except_table._ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m,\"aG\",@progbits,_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m,comdat\n\t.p2align\t2, 0x0\nGCC_except_table52:\n.Lexception14:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t255 # @TType Encoding = omit\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end14-.Lcst_begin14\n.Lcst_begin14:\n\t.uleb128 .Lfunc_begin14-.Lfunc_begin14 # >> Call Site 1 <<\n\t.uleb128 .Ltmp215-.Lfunc_begin14 # Call between .Lfunc_begin14 and .Ltmp215\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp215-.Lfunc_begin14 # >> Call Site 2 <<\n\t.uleb128 .Ltmp218-.Ltmp215 # Call between .Ltmp215 and .Ltmp218\n\t.uleb128 .Ltmp219-.Lfunc_begin14 # jumps to .Ltmp219\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp218-.Lfunc_begin14 # >> Call Site 3 <<\n\t.uleb128 .Ltmp220-.Ltmp218 # Call between .Ltmp218 and .Ltmp220\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp220-.Lfunc_begin14 # >> Call Site 4 <<\n\t.uleb128 .Ltmp223-.Ltmp220 # Call between .Ltmp220 and .Ltmp223\n\t.uleb128 .Ltmp224-.Lfunc_begin14 # jumps to .Ltmp224\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp223-.Lfunc_begin14 # >> Call Site 5 <<\n\t.uleb128 .Lfunc_end52-.Ltmp223 # Call between .Ltmp223 and .Lfunc_end52\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n.Lcst_end14:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text._ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,\"axG\",@progbits,_ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat\n\t.weak\t_ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ # -- Begin function _ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,@function\n_ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_: # @_ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$104, %rsp\n\t.cfi_def_cfa_offset 112\n\tmovq\t%rdi, 64(%rsp)\n\tmovss\t%xmm0, 72(%rsp)\n\tmovq\t%rsi, 56(%rsp)\n\tmovq\t%rdx, 48(%rsp)\n\tleaq\t64(%rsp), %rax\n\tmovq\t%rax, 80(%rsp)\n\tleaq\t56(%rsp), %rax\n\tmovq\t%rax, 88(%rsp)\n\tleaq\t48(%rsp), %rax\n\tmovq\t%rax, 96(%rsp)\n\tleaq\t32(%rsp), %rdi\n\tleaq\t16(%rsp), %rsi\n\tleaq\t8(%rsp), %rdx\n\tmovq\t%rsp, %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t32(%rsp), %rsi\n\tmovl\t40(%rsp), %edx\n\tmovq\t16(%rsp), %rcx\n\tmovl\t24(%rsp), %r8d\n\tleaq\t80(%rsp), %r9\n\tmovl\t$_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, %edi\n\tpushq\t(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t16(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$120, %rsp\n\t.cfi_adjust_cfa_offset -120\n\tretq\n.Lfunc_end53:\n\t.size\t_ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, .Lfunc_end53-_ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_\n\t.cfi_endproc\n # -- End function\n\t.section\t.text._ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2EmRKf,\"axG\",@progbits,_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2EmRKf,comdat\n\t.weak\t_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2EmRKf # -- Begin function _ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2EmRKf\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2EmRKf,@function\n_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2EmRKf: # @_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2EmRKf\n.Lfunc_begin15:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception15\n# %bb.0:\n\tpushq\t%r15\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 32\n\tsubq\t$16, %rsp\n\t.cfi_def_cfa_offset 48\n\t.cfi_offset %rbx, -32\n\t.cfi_offset %r14, -24\n\t.cfi_offset %r15, -16\n\tmovq\t%rdx, %r15\n\tmovq\t%rsi, %r14\n\tmovq\t%rdi, %rbx\n\tmovzbl\t_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource(%rip), %eax\n\ttestb\t%al, %al\n\tje\t.LBB54_1\n.LBB54_4:\n\tmovq\t$_ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, (%rbx)\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, 8(%rbx)\n\tmovq\t$0, 24(%rbx)\n\ttestq\t%r14, %r14\n\tje\t.LBB54_7\n# %bb.5:\n\tleaq\t(,%r14,4), %rsi\n\tmovq\t_ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource+8(%rip), %rdi\n.Ltmp228:\n\tmovl\t$4, %edx\n\tcallq\t_ZN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEE11do_allocateEmm\n.Ltmp229:\n# %bb.6:\n\tmovq\t%rax, 8(%rbx)\n\tmovq\t%r14, 16(%rbx)\n\tmovq\t%r14, 24(%rbx)\n\tmovss\t(%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero\n.Ltmp230:\n\tleaq\t15(%rsp), %rdi\n\tmovq\t%rax, %rsi\n\tmovq\t%r14, %rdx\n\tcallq\t_ZZN6thrust11hip_rocprim12parallel_forINS0_3tagENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmEEvRNS0_16execution_policyIT_EET0_T1_EN10workaround3parERNS8_IS2_EES7_m\n.Ltmp231:\n.LBB54_7:\n\taddq\t$16, %rsp\n\t.cfi_def_cfa_offset 32\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 16\n\tpopq\t%r15\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB54_1:\n\t.cfi_def_cfa_offset 48\n\tmovl\t$_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, %edi\n\tcallq\t__cxa_guard_acquire\n\ttestl\t%eax, %eax\n\tje\t.LBB54_4\n# %bb.2:\n.Ltmp225:\n\tmovl\t$_ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, %edi\n\tcallq\t_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEC2Ev\n.Ltmp226:\n# %bb.3:\n\tmovl\t$_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, %edi\n\tcallq\t__cxa_guard_release\n\tjmp\t.LBB54_4\n.LBB54_8:\n.Ltmp227:\n\tmovq\t%rax, %r14\n\tmovl\t$_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, %edi\n\tcallq\t__cxa_guard_abort\n\tmovq\t%r14, %rdi\n\tcallq\t_Unwind_Resume@PLT\n.LBB54_10:\n.Ltmp232:\n\tmovq\t%rax, %r14\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZN6thrust6detail18contiguous_storageIfNS_16device_allocatorIfEEED2Ev\n\tmovq\t%r14, %rdi\n\tcallq\t_Unwind_Resume@PLT\n.Lfunc_end54:\n\t.size\t_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2EmRKf, .Lfunc_end54-_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2EmRKf\n\t.cfi_endproc\n\t.section\t.gcc_except_table._ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2EmRKf,\"aG\",@progbits,_ZN6thrust6detail11vector_baseIfNS_16device_allocatorIfEEEC2EmRKf,comdat\n\t.p2align\t2, 0x0\nGCC_except_table54:\n.Lexception15:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t255 # @TType Encoding = omit\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end15-.Lcst_begin15\n.Lcst_begin15:\n\t.uleb128 .Ltmp228-.Lfunc_begin15 # >> Call Site 1 <<\n\t.uleb128 .Ltmp231-.Ltmp228 # Call between .Ltmp228 and .Ltmp231\n\t.uleb128 .Ltmp232-.Lfunc_begin15 # jumps to .Ltmp232\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp225-.Lfunc_begin15 # >> Call Site 2 <<\n\t.uleb128 .Ltmp226-.Ltmp225 # Call between .Ltmp225 and .Ltmp226\n\t.uleb128 .Ltmp227-.Lfunc_begin15 # jumps to .Ltmp227\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp226-.Lfunc_begin15 # >> Call Site 3 <<\n\t.uleb128 .Lfunc_end54-.Ltmp226 # Call between .Ltmp226 and .Lfunc_end54\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n.Lcst_end15:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text._ZN6thrust6detail11vector_baseIfSaIfEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKfEEEEEEvmT_SA_RNS0_18contiguous_storageIfS2_EE,\"axG\",@progbits,_ZN6thrust6detail11vector_baseIfSaIfEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKfEEEEEEvmT_SA_RNS0_18contiguous_storageIfS2_EE,comdat\n\t.weak\t_ZN6thrust6detail11vector_baseIfSaIfEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKfEEEEEEvmT_SA_RNS0_18contiguous_storageIfS2_EE # -- Begin function _ZN6thrust6detail11vector_baseIfSaIfEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKfEEEEEEvmT_SA_RNS0_18contiguous_storageIfS2_EE\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust6detail11vector_baseIfSaIfEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKfEEEEEEvmT_SA_RNS0_18contiguous_storageIfS2_EE,@function\n_ZN6thrust6detail11vector_baseIfSaIfEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKfEEEEEEvmT_SA_RNS0_18contiguous_storageIfS2_EE: # @_ZN6thrust6detail11vector_baseIfSaIfEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKfEEEEEEvmT_SA_RNS0_18contiguous_storageIfS2_EE\n.Lfunc_begin16:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception16\n# %bb.0:\n\tpushq\t%r15\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpushq\t%r13\n\t.cfi_def_cfa_offset 32\n\tpushq\t%r12\n\t.cfi_def_cfa_offset 40\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 48\n\tsubq\t$16, %rsp\n\t.cfi_def_cfa_offset 64\n\t.cfi_offset %rbx, -48\n\t.cfi_offset %r12, -40\n\t.cfi_offset %r13, -32\n\t.cfi_offset %r14, -24\n\t.cfi_offset %r15, -16\n\tmovq\t%r8, %rbx\n\ttestq\t%rsi, %rsi\n\tje\t.LBB55_1\n# %bb.4:\n\tmovq\t%rsi, %rax\n\tshrq\t$61, %rax\n\tjne\t.LBB55_5\n# %bb.7:\n\tmovq\t%rcx, %r14\n\tmovq\t%rdx, %r15\n\tmovq\t16(%rdi), %r13\n\taddq\t%r13, %r13\n\tcmpq\t%r13, %rsi\n\tcmovaq\t%rsi, %r13\n\tmovabsq\t$2305843009213693951, %rax # imm = 0x1FFFFFFFFFFFFFFF\n\tcmpq\t%rax, %r13\n\tcmovaeq\t%rax, %r13\n\tleaq\t(,%r13,4), %rdi\n\tcallq\t_Znwm\n\tleaq\t8(%rbx), %r12\n\tmovq\t%rax, 8(%rbx)\n\tmovq\t%r13, 16(%rbx)\n\tsubq\t%r15, %r14\n\tsarq\t$2, %r14\n.Ltmp233:\n\tleaq\t14(%rsp), %rdi\n\tleaq\t15(%rsp), %rsi\n\tmovq\t%r15, %rdx\n\tmovq\t%r14, %rcx\n\tmovq\t%rax, %r8\n\tcallq\t_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKfEEEEmPfEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE\n.Ltmp234:\n\tjmp\t.LBB55_3\n.LBB55_1:\n\tcmpq\t$0, 16(%rbx)\n\tje\t.LBB55_3\n# %bb.2:\n\tmovq\t8(%rbx), %rdi\n\tcallq\t_ZdlPv\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, 8(%rbx)\n.LBB55_3:\n\taddq\t$16, %rsp\n\t.cfi_def_cfa_offset 48\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 40\n\tpopq\t%r12\n\t.cfi_def_cfa_offset 32\n\tpopq\t%r13\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 16\n\tpopq\t%r15\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB55_5:\n\t.cfi_def_cfa_offset 64\n\tmovl\t$16, %edi\n\tcallq\t__cxa_allocate_exception\n\tmovq\t%rax, %rbx\n.Ltmp242:\n\tmovl\t$.L.str.15, %esi\n\tmovq\t%rax, %rdi\n\tcallq\t_ZNSt12length_errorC1EPKc\n.Ltmp243:\n# %bb.6:\n\tmovl\t$_ZTISt12length_error, %esi\n\tmovl\t$_ZNSt12length_errorD1Ev, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t__cxa_throw\n.LBB55_12:\n.Ltmp244:\n\tmovq\t%rax, %r14\n\tmovq\t%rbx, %rdi\n\tcallq\t__cxa_free_exception\n\tmovq\t%r14, %rdi\n\tcallq\t_Unwind_Resume@PLT\n.LBB55_8:\n.Ltmp235:\n\tmovq\t%rax, %rdi\n\tcallq\t__cxa_begin_catch\n\tcmpq\t$0, 16(%rbx)\n\tje\t.LBB55_10\n# %bb.9:\n\tmovq\t(%r12), %rdi\n\tcallq\t_ZdlPv\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, (%r12)\n.LBB55_10:\n.Ltmp236:\n\tcallq\t__cxa_rethrow\n.Ltmp237:\n# %bb.15:\n.LBB55_11:\n.Ltmp238:\n\tmovq\t%rax, %r14\n.Ltmp239:\n\tcallq\t__cxa_end_catch\n.Ltmp240:\n# %bb.13:\n\tmovq\t%r14, %rdi\n\tcallq\t_Unwind_Resume@PLT\n.LBB55_14:\n.Ltmp241:\n\tmovq\t%rax, %rdi\n\tcallq\t__clang_call_terminate\n.Lfunc_end55:\n\t.size\t_ZN6thrust6detail11vector_baseIfSaIfEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKfEEEEEEvmT_SA_RNS0_18contiguous_storageIfS2_EE, .Lfunc_end55-_ZN6thrust6detail11vector_baseIfSaIfEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKfEEEEEEvmT_SA_RNS0_18contiguous_storageIfS2_EE\n\t.cfi_endproc\n\t.section\t.gcc_except_table._ZN6thrust6detail11vector_baseIfSaIfEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKfEEEEEEvmT_SA_RNS0_18contiguous_storageIfS2_EE,\"aG\",@progbits,_ZN6thrust6detail11vector_baseIfSaIfEE17allocate_and_copyINS0_15normal_iteratorINS_10device_ptrIKfEEEEEEvmT_SA_RNS0_18contiguous_storageIfS2_EE,comdat\n\t.p2align\t2, 0x0\nGCC_except_table55:\n.Lexception16:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t3 # @TType Encoding = udata4\n\t.uleb128 .Lttbase6-.Lttbaseref6\n.Lttbaseref6:\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end16-.Lcst_begin16\n.Lcst_begin16:\n\t.uleb128 .Lfunc_begin16-.Lfunc_begin16 # >> Call Site 1 <<\n\t.uleb128 .Ltmp233-.Lfunc_begin16 # Call between .Lfunc_begin16 and .Ltmp233\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp233-.Lfunc_begin16 # >> Call Site 2 <<\n\t.uleb128 .Ltmp234-.Ltmp233 # Call between .Ltmp233 and .Ltmp234\n\t.uleb128 .Ltmp235-.Lfunc_begin16 # jumps to .Ltmp235\n\t.byte\t1 # On action: 1\n\t.uleb128 .Ltmp234-.Lfunc_begin16 # >> Call Site 3 <<\n\t.uleb128 .Ltmp242-.Ltmp234 # Call between .Ltmp234 and .Ltmp242\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp242-.Lfunc_begin16 # >> Call Site 4 <<\n\t.uleb128 .Ltmp243-.Ltmp242 # Call between .Ltmp242 and .Ltmp243\n\t.uleb128 .Ltmp244-.Lfunc_begin16 # jumps to .Ltmp244\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp243-.Lfunc_begin16 # >> Call Site 5 <<\n\t.uleb128 .Ltmp236-.Ltmp243 # Call between .Ltmp243 and .Ltmp236\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp236-.Lfunc_begin16 # >> Call Site 6 <<\n\t.uleb128 .Ltmp237-.Ltmp236 # Call between .Ltmp236 and .Ltmp237\n\t.uleb128 .Ltmp238-.Lfunc_begin16 # jumps to .Ltmp238\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp239-.Lfunc_begin16 # >> Call Site 7 <<\n\t.uleb128 .Ltmp240-.Ltmp239 # Call between .Ltmp239 and .Ltmp240\n\t.uleb128 .Ltmp241-.Lfunc_begin16 # jumps to .Ltmp241\n\t.byte\t1 # On action: 1\n\t.uleb128 .Ltmp240-.Lfunc_begin16 # >> Call Site 8 <<\n\t.uleb128 .Lfunc_end55-.Ltmp240 # Call between .Ltmp240 and .Lfunc_end55\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n.Lcst_end16:\n\t.byte\t1 # >> Action Record 1 <<\n # Catch TypeInfo 1\n\t.byte\t0 # No further actions\n\t.p2align\t2, 0x0\n # >> Catch TypeInfos <<\n\t.long\t0 # TypeInfo 1\n.Lttbase6:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text._ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKfEEEEmPfEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE,\"axG\",@progbits,_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKfEEEEmPfEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE,comdat\n\t.weak\t_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKfEEEEmPfEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE # -- Begin function _ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKfEEEEmPfEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE\n\t.p2align\t4, 0x90\n\t.type\t_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKfEEEEmPfEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE,@function\n_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKfEEEEmPfEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE: # @_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKfEEEEmPfEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE\n.Lfunc_begin17:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception17\n# %bb.0:\n\tpushq\t%rbp\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 32\n\t.cfi_offset %rbx, -32\n\t.cfi_offset %r14, -24\n\t.cfi_offset %rbp, -16\n\tmovq\t%r8, %rbx\n\tmovq\t%rcx, %r14\n\ttestq\t%rcx, %rcx\n\tje\t.LBB56_6\n# %bb.1:\n\tleaq\t(,%r14,4), %rax\n\tmovq\t%rbx, %rdi\n\tmovq\t%rdx, %rsi\n\tmovq\t%rax, %rdx\n\tmovl\t$2, %ecx\n\txorl\t%r8d, %r8d\n\tcallq\thipMemcpyWithStream\n\tmovl\t%eax, %ebp\n\tcallq\thipGetLastError\n\ttestl\t%ebp, %ebp\n\tjne\t.LBB56_2\n.LBB56_6:\n\tleaq\t(%rbx,%r14,4), %rax\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 16\n\tpopq\t%rbp\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB56_2:\n\t.cfi_def_cfa_offset 32\n\tmovl\t$64, %edi\n\tcallq\t__cxa_allocate_exception\n\tmovq\t%rax, %rbx\n.Ltmp245:\n\tcallq\t_ZN6thrust6system12hip_categoryEv\n.Ltmp246:\n# %bb.3:\n.Ltmp247:\n\tmovl\t$.L.str.16, %ecx\n\tmovq\t%rbx, %rdi\n\tmovl\t%ebp, %esi\n\tmovq\t%rax, %rdx\n\tcallq\t_ZN6thrust6system12system_errorC2EiRKNS0_14error_categoryEPKc\n.Ltmp248:\n# %bb.4:\n\tmovl\t$_ZTIN6thrust6system12system_errorE, %esi\n\tmovl\t$_ZN6thrust6system12system_errorD2Ev, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t__cxa_throw\n.LBB56_5:\n.Ltmp249:\n\tmovq\t%rax, %r14\n\tmovq\t%rbx, %rdi\n\tcallq\t__cxa_free_exception\n\tmovq\t%r14, %rdi\n\tcallq\t_Unwind_Resume@PLT\n.Lfunc_end56:\n\t.size\t_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKfEEEEmPfEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE, .Lfunc_end56-_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKfEEEEmPfEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE\n\t.cfi_endproc\n\t.section\t.gcc_except_table._ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKfEEEEmPfEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE,\"aG\",@progbits,_ZN6thrust11hip_rocprim6__copy19cross_system_copy_nINS0_3tagENS_6system3cpp6detail3tagENS_6detail15normal_iteratorINS_10device_ptrIKfEEEEmPfEET3_RNS_16execution_policyIT_EERNSG_IT0_EET1_T2_SF_NS8_17integral_constantIbLb1EEE,comdat\n\t.p2align\t2, 0x0\nGCC_except_table56:\n.Lexception17:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t255 # @TType Encoding = omit\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end17-.Lcst_begin17\n.Lcst_begin17:\n\t.uleb128 .Lfunc_begin17-.Lfunc_begin17 # >> Call Site 1 <<\n\t.uleb128 .Ltmp245-.Lfunc_begin17 # Call between .Lfunc_begin17 and .Ltmp245\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp245-.Lfunc_begin17 # >> Call Site 2 <<\n\t.uleb128 .Ltmp248-.Ltmp245 # Call between .Ltmp245 and .Ltmp248\n\t.uleb128 .Ltmp249-.Lfunc_begin17 # jumps to .Ltmp249\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp248-.Lfunc_begin17 # >> Call Site 3 <<\n\t.uleb128 .Lfunc_end56-.Ltmp248 # Call between .Ltmp248 and .Lfunc_end56\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n.Lcst_end17:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text.startup,\"ax\",@progbits\n\t.p2align\t4, 0x90 # -- Begin function _GLOBAL__sub_I_cuda_code_004697.hip\n\t.type\t_GLOBAL__sub_I_cuda_code_004697.hip,@function\n_GLOBAL__sub_I_cuda_code_004697.hip: # @_GLOBAL__sub_I_cuda_code_004697.hip\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 16\n\tmovl\t$_ZStL8__ioinit, %edi\n\tcallq\t_ZNSt8ios_base4InitC1Ev\n\tmovl\t$_ZNSt8ios_base4InitD1Ev, %edi\n\tmovl\t$_ZStL8__ioinit, %esi\n\tmovl\t$__dso_handle, %edx\n\tpopq\t%rax\n\t.cfi_def_cfa_offset 8\n\tjmp\t__cxa_atexit # TAILCALL\n.Lfunc_end57:\n\t.size\t_GLOBAL__sub_I_cuda_code_004697.hip, .Lfunc_end57-_GLOBAL__sub_I_cuda_code_004697.hip\n\t.cfi_endproc\n # -- End function\n\t.text\n\t.p2align\t4, 0x90 # -- Begin function __hip_module_ctor\n\t.type\t__hip_module_ctor,@function\n__hip_module_ctor: # @__hip_module_ctor\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 16\n\tsubq\t$32, %rsp\n\t.cfi_def_cfa_offset 48\n\t.cfi_offset %rbx, -16\n\tmovq\t__hip_gpubin_handle(%rip), %rbx\n\ttestq\t%rbx, %rbx\n\tjne\t.LBB58_2\n# %bb.1:\n\tmovl\t$__hip_fatbin_wrapper, %edi\n\tcallq\t__hipRegisterFatBinary\n\tmovq\t%rax, %rbx\n\tmovq\t%rax, __hip_gpubin_handle(%rip)\n.LBB58_2:\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, 16(%rsp)\n\tmovups\t%xmm0, (%rsp)\n\tmovl\t$_Z17initialize_randomP12hiprandStatem, %esi\n\tmovl\t$.L__unnamed_1, %edx\n\tmovl\t$.L__unnamed_1, %ecx\n\tmovq\t%rbx, %rdi\n\tmovl\t$-1, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipRegisterFunction\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, 16(%rsp)\n\tmovups\t%xmm0, (%rsp)\n\tmovl\t$_Z21generate_sparse_inputPiPfP12hiprandStatei, %esi\n\tmovl\t$.L__unnamed_2, %edx\n\tmovl\t$.L__unnamed_2, %ecx\n\tmovq\t%rbx, %rdi\n\tmovl\t$-1, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipRegisterFunction\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, 16(%rsp)\n\tmovups\t%xmm0, (%rsp)\n\tmovl\t$_Z25sparse_convolution_kernelPKiPKfiS2_Pfi, %esi\n\tmovl\t$.L__unnamed_3, %edx\n\tmovl\t$.L__unnamed_3, %ecx\n\tmovq\t%rbx, %rdi\n\tmovl\t$-1, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipRegisterFunction\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, 16(%rsp)\n\tmovups\t%xmm0, (%rsp)\n\tmovl\t$_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, %esi\n\tmovl\t$.L__unnamed_4, %edx\n\tmovl\t$.L__unnamed_4, %ecx\n\tmovq\t%rbx, %rdi\n\tmovl\t$-1, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipRegisterFunction\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, 16(%rsp)\n\tmovups\t%xmm0, (%rsp)\n\tmovl\t$_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, %esi\n\tmovl\t$.L__unnamed_5, %edx\n\tmovl\t$.L__unnamed_5, %ecx\n\tmovq\t%rbx, %rdi\n\tmovl\t$-1, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipRegisterFunction\n\tmovl\t$__hip_module_dtor, %edi\n\taddq\t$32, %rsp\n\t.cfi_def_cfa_offset 16\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 8\n\tjmp\tatexit # TAILCALL\n.Lfunc_end58:\n\t.size\t__hip_module_ctor, .Lfunc_end58-__hip_module_ctor\n\t.cfi_endproc\n # -- End function\n\t.p2align\t4, 0x90 # -- Begin function __hip_module_dtor\n\t.type\t__hip_module_dtor,@function\n__hip_module_dtor: # @__hip_module_dtor\n\t.cfi_startproc\n# %bb.0:\n\tmovq\t__hip_gpubin_handle(%rip), %rdi\n\ttestq\t%rdi, %rdi\n\tje\t.LBB59_2\n# %bb.1:\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 16\n\tcallq\t__hipUnregisterFatBinary\n\tmovq\t$0, __hip_gpubin_handle(%rip)\n\taddq\t$8, %rsp\n\t.cfi_def_cfa_offset 8\n.LBB59_2:\n\tretq\n.Lfunc_end59:\n\t.size\t__hip_module_dtor, .Lfunc_end59-__hip_module_dtor\n\t.cfi_endproc\n # -- End function\n\t.type\t_ZStL8__ioinit,@object # @_ZStL8__ioinit\n\t.local\t_ZStL8__ioinit\n\t.comm\t_ZStL8__ioinit,1,1\n\t.hidden\t__dso_handle\n\t.type\t_Z17initialize_randomP12hiprandStatem,@object # @_Z17initialize_randomP12hiprandStatem\n\t.section\t.rodata,\"a\",@progbits\n\t.globl\t_Z17initialize_randomP12hiprandStatem\n\t.p2align\t3, 0x0\n_Z17initialize_randomP12hiprandStatem:\n\t.quad\t_Z32__device_stub__initialize_randomP12hiprandStatem\n\t.size\t_Z17initialize_randomP12hiprandStatem, 8\n\n\t.type\t_Z21generate_sparse_inputPiPfP12hiprandStatei,@object # @_Z21generate_sparse_inputPiPfP12hiprandStatei\n\t.globl\t_Z21generate_sparse_inputPiPfP12hiprandStatei\n\t.p2align\t3, 0x0\n_Z21generate_sparse_inputPiPfP12hiprandStatei:\n\t.quad\t_Z36__device_stub__generate_sparse_inputPiPfP12hiprandStatei\n\t.size\t_Z21generate_sparse_inputPiPfP12hiprandStatei, 8\n\n\t.type\t_Z25sparse_convolution_kernelPKiPKfiS2_Pfi,@object # @_Z25sparse_convolution_kernelPKiPKfiS2_Pfi\n\t.globl\t_Z25sparse_convolution_kernelPKiPKfiS2_Pfi\n\t.p2align\t3, 0x0\n_Z25sparse_convolution_kernelPKiPKfiS2_Pfi:\n\t.quad\t_Z40__device_stub__sparse_convolution_kernelPKiPKfiS2_Pfi\n\t.size\t_Z25sparse_convolution_kernelPKiPKfiS2_Pfi, 8\n\n\t.type\t.L.str,@object # @.str\n\t.section\t.rodata.str1.1,\"aMS\",@progbits,1\n.L.str:\n\t.asciz\t\"CUDA error: \"\n\t.size\t.L.str, 13\n\n\t.type\t.L.str.1,@object # @.str.1\n.L.str.1:\n\t.asciz\t\"First 10 elements of output: \"\n\t.size\t.L.str.1, 30\n\n\t.type\t.L.str.2,@object # @.str.2\n.L.str.2:\n\t.asciz\t\" \"\n\t.size\t.L.str.2, 2\n\n\t.type\t_ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource,@object # @_ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource\n\t.section\t.bss._ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource,\"awG\",@nobits,_ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource,comdat\n\t.weak\t_ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource\n\t.p2align\t3, 0x0\n_ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource:\n\t.zero\t16\n\t.size\t_ZZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, 16\n\n\t.type\t_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource,@object # @_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource\n\t.section\t.bss._ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource,\"awG\",@nobits,_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource,comdat\n\t.weak\t_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource\n\t.p2align\t3, 0x0\n_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource:\n\t.quad\t0 # 0x0\n\t.size\t_ZGVZN6thrust2mr19get_global_resourceINS_26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS9_EENS_11use_defaultEEEEEEEEEPT_vE8resource, 8\n\n\t.type\t_ZTVN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE,@object # @_ZTVN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE\n\t.section\t.rodata._ZTVN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE,\"aG\",@progbits,_ZTVN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE,comdat\n\t.weak\t_ZTVN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE\n\t.p2align\t3, 0x0\n_ZTVN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE:\n\t.quad\t0\n\t.quad\t_ZTIN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE\n\t.quad\t_ZN6thrust2mr15memory_resourceINS_10device_ptrIvEEED2Ev\n\t.quad\t_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEED0Ev\n\t.quad\t_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE11do_allocateEmm\n\t.quad\t_ZN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEE13do_deallocateENS_10device_ptrIvEEmm\n\t.quad\t_ZNK6thrust2mr15memory_resourceINS_10device_ptrIvEEE11do_is_equalERKS4_\n\t.size\t_ZTVN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE, 56\n\n\t.type\t_ZTSN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE,@object # @_ZTSN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE\n\t.section\t.rodata._ZTSN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE,\"aG\",@progbits,_ZTSN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE,comdat\n\t.weak\t_ZTSN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE\n_ZTSN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE:\n\t.asciz\t\"N6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE\"\n\t.size\t_ZTSN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE, 200\n\n\t.type\t_ZTSN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE,@object # @_ZTSN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE\n\t.section\t.rodata._ZTSN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE,\"aG\",@progbits,_ZTSN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE,comdat\n\t.weak\t_ZTSN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE\n_ZTSN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE:\n\t.asciz\t\"N6thrust2mr15memory_resourceINS_10device_ptrIvEEEE\"\n\t.size\t_ZTSN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE, 51\n\n\t.type\t_ZTIN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE,@object # @_ZTIN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE\n\t.section\t.rodata._ZTIN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE,\"aG\",@progbits,_ZTIN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE,comdat\n\t.weak\t_ZTIN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE\n\t.p2align\t3, 0x0\n_ZTIN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE:\n\t.quad\t_ZTVN10__cxxabiv117__class_type_infoE+16\n\t.quad\t_ZTSN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE\n\t.size\t_ZTIN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE, 16\n\n\t.type\t_ZTIN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE,@object # @_ZTIN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE\n\t.section\t.rodata._ZTIN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE,\"aG\",@progbits,_ZTIN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE,comdat\n\t.weak\t_ZTIN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE\n\t.p2align\t3, 0x0\n_ZTIN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE:\n\t.quad\t_ZTVN10__cxxabiv120__si_class_type_infoE+16\n\t.quad\t_ZTSN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE\n\t.quad\t_ZTIN6thrust2mr15memory_resourceINS_10device_ptrIvEEEE\n\t.size\t_ZTIN6thrust26device_ptr_memory_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS7_EENS_11use_defaultEEEEEEE, 24\n\n\t.type\t_ZZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource,@object # @_ZZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource\n\t.section\t.data._ZZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource,\"awG\",@progbits,_ZZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource,comdat\n\t.weak\t_ZZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource\n\t.p2align\t3, 0x0\n_ZZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource:\n\t.quad\t_ZTVN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE+16\n\t.size\t_ZZN6thrust2mr19get_global_resourceINS_6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS8_EENS_11use_defaultEEEEEEEPT_vE8resource, 8\n\n\t.type\t_ZTVN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE,@object # @_ZTVN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE\n\t.section\t.rodata._ZTVN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE,\"aG\",@progbits,_ZTVN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE,comdat\n\t.weak\t_ZTVN6thrust6system3hip6detail19hip_memory_resourceIXadL_Z9hipMallocEEXadL_Z7hipFreeEENS_7pointerIvNS_11hip_rocprim3tagENS_16tagged_referenceIvS6_EENS_11use_defaultEEEEE\n\t.p2align\t3, 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0x0\n_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_:\n\t.quad\t_ZN6thrust11hip_rocprim14__parallel_for21__device_stub__kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_\n\t.size\t_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, 8\n\n\t.type\t.L.str.15,@object # @.str.15\n\t.section\t.rodata.str1.1,\"aMS\",@progbits,1\n.L.str.15:\n\t.asciz\t\"assignment exceeds max_size().\"\n\t.size\t.L.str.15, 31\n\n\t.type\t.L.str.16,@object # @.str.16\n.L.str.16:\n\t.asciz\t\"trivial_device_copy D->H failed\"\n\t.size\t.L.str.16, 32\n\n\t.type\t.L__unnamed_1,@object # @0\n.L__unnamed_1:\n\t.asciz\t\"_Z17initialize_randomP12hiprandStatem\"\n\t.size\t.L__unnamed_1, 38\n\n\t.type\t.L__unnamed_2,@object # @1\n.L__unnamed_2:\n\t.asciz\t\"_Z21generate_sparse_inputPiPfP12hiprandStatei\"\n\t.size\t.L__unnamed_2, 46\n\n\t.type\t.L__unnamed_3,@object # @2\n.L__unnamed_3:\n\t.asciz\t\"_Z25sparse_convolution_kernelPKiPKfiS2_Pfi\"\n\t.size\t.L__unnamed_3, 43\n\n\t.type\t.L__unnamed_4,@object # @3\n.L__unnamed_4:\n\t.asciz\t\"_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_\"\n\t.size\t.L__unnamed_4, 128\n\n\t.type\t.L__unnamed_5,@object # @4\n.L__unnamed_5:\n\t.asciz\t\"_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_\"\n\t.size\t.L__unnamed_5, 128\n\n\t.type\t__hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper\n\t.section\t.hipFatBinSegment,\"a\",@progbits\n\t.p2align\t3, 0x0\n__hip_fatbin_wrapper:\n\t.long\t1212764230 # 0x48495046\n\t.long\t1 # 0x1\n\t.quad\t__hip_fatbin\n\t.quad\t0\n\t.size\t__hip_fatbin_wrapper, 24\n\n\t.type\t__hip_gpubin_handle,@object # @__hip_gpubin_handle\n\t.local\t__hip_gpubin_handle\n\t.comm\t__hip_gpubin_handle,8,8\n\t.section\t.init_array,\"aw\",@init_array\n\t.p2align\t3, 0x0\n\t.quad\t_GLOBAL__sub_I_cuda_code_004697.hip\n\t.quad\t__hip_module_ctor\n\t.type\t__hip_cuid_,@object # @__hip_cuid_\n\t.bss\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 # 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n"}}},{"rowIdx":162580,"cells":{"id":{"kind":"string","value":"e035bddad58a987c9319f68003a2f1ce5e62f9f8_O1"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z14rmsprop_kernelPfS_S_fff --------------------------\n .section .text._Z14rmsprop_kernelPfS_S_fff,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=16\"\n .align 128\n\n\n\n\n .global _Z14rmsprop_kernelPfS_S_fff\n .type _Z14rmsprop_kernelPfS_S_fff,@function\n .size _Z14rmsprop_kernelPfS_S_fff,(.L_x_19 - _Z14rmsprop_kernelPfS_S_fff)\n .other _Z14rmsprop_kernelPfS_S_fff,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z14rmsprop_kernelPfS_S_fff:\n.text._Z14rmsprop_kernelPfS_S_fff:\n /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;\n /*0010*/ S2R R4, SR_CTAID.X ;\n /*0020*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*0030*/ S2R R3, SR_TID.X ;\n /*0040*/ IMAD R4, R4, c[0x0][0x0], R3 ;\n /*0050*/ ISETP.GT.AND P0, PT, R4, 0x1f, PT ;\n /*0060*/ @P0 EXIT ;\n /*0070*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ;\n /*0080*/ IMAD.WIDE R2, R4, R7, c[0x0][0x160] ;\n /*0090*/ LDG.E R0, [R2.64] ;\n /*00a0*/ IMAD.WIDE R6, R4, R7, c[0x0][0x170] ;\n /*00b0*/ FMUL R5, R0, R0 ;\n /*00c0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R6.64], R5 ;\n /*00d0*/ LDG.E R0, [R6.64] ;\n /*00e0*/ BSSY B0, `(.L_x_0) ;\n /*00f0*/ FADD R0, R0, c[0x0][0x180] ;\n /*0100*/ MUFU.RSQ R9, R0 ;\n /*0110*/ IADD3 R8, R0, -0xd000000, RZ ;\n /*0120*/ ISETP.GT.U32.AND P0, PT, R8, 0x727fffff, PT ;\n /*0130*/ @!P0 BRA `(.L_x_1) ;\n /*0140*/ MOV R9, 0x160 ;\n /*0150*/ CALL.REL.NOINC `($__internal_0_$__cuda_sm20_sqrt_rn_f32_slowpath) ;\n /*0160*/ BRA `(.L_x_2) ;\n.L_x_1:\n /*0170*/ FMUL.FTZ R5, R0, R9 ;\n /*0180*/ FMUL.FTZ R9, R9, 0.5 ;\n /*0190*/ FFMA R0, -R5, R5, R0 ;\n /*01a0*/ FFMA R5, R0, R9, R5 ;\n.L_x_2:\n /*01b0*/ BSYNC B0 ;\n.L_x_0:\n /*01c0*/ LDG.E R0, [R2.64] ;\n /*01d0*/ MUFU.RCP R6, R5 ;\n /*01e0*/ BSSY B0, `(.L_x_3) ;\n /*01f0*/ FFMA R7, R6, -R5, 1 ;\n /*0200*/ FFMA R7, R6, R7, R6 ;\n /*0210*/ FMUL R0, R0, c[0x0][0x178] ;\n /*0220*/ FCHK P0, R0, R5 ;\n /*0230*/ FFMA R6, R0, R7, RZ ;\n /*0240*/ FFMA R8, R6, -R5, R0 ;\n /*0250*/ FFMA R6, R7, R8, R6 ;\n /*0260*/ @!P0 BRA `(.L_x_4) ;\n /*0270*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ;\n /*0280*/ MOV R2, 0x2a0 ;\n /*0290*/ CALL.REL.NOINC `($__internal_1_$__cuda_sm3x_div_rn_noftz_f32_slowpath) ;\n.L_x_4:\n /*02a0*/ BSYNC B0 ;\n.L_x_3:\n /*02b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ;\n /*02c0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ;\n /*02d0*/ LDG.E R3, [R4.64] ;\n /*02e0*/ FADD R3, R3, -R6 ;\n /*02f0*/ STG.E [R4.64], R3 ;\n /*0300*/ EXIT ;\n\n\n\n\n .weak $__internal_0_$__cuda_sm20_sqrt_rn_f32_slowpath\n .type $__internal_0_$__cuda_sm20_sqrt_rn_f32_slowpath,@function\n .size $__internal_0_$__cuda_sm20_sqrt_rn_f32_slowpath,($__internal_1_$__cuda_sm3x_div_rn_noftz_f32_slowpath - $__internal_0_$__cuda_sm20_sqrt_rn_f32_slowpath)\n$__internal_0_$__cuda_sm20_sqrt_rn_f32_slowpath:\n /*0310*/ LOP3.LUT P0, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ;\n /*0320*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R0 ;\n /*0330*/ @!P0 BRA `(.L_x_5) ;\n /*0340*/ FSETP.GEU.FTZ.AND P0, PT, R0, RZ, PT ;\n /*0350*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, 0x7fffffff ;\n /*0360*/ @!P0 BRA `(.L_x_5) ;\n /*0370*/ FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ;\n /*0380*/ @P0 FADD.FTZ R5, R0, 1 ;\n /*0390*/ @P0 BRA `(.L_x_5) ;\n /*03a0*/ FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ;\n /*03b0*/ @P0 FFMA R6, R0, 1.84467440737095516160e+19, RZ ;\n /*03c0*/ @P0 MUFU.RSQ R5, R6 ;\n /*03d0*/ @P0 FMUL.FTZ R7, R6, R5 ;\n /*03e0*/ @P0 FMUL.FTZ R5, R5, 0.5 ;\n /*03f0*/ @P0 FADD.FTZ R8, -R7, -RZ ;\n /*0400*/ @P0 FFMA R8, R7, R8, R6 ;\n /*0410*/ @P0 FFMA R8, R8, R5, R7 ;\n /*0420*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R0 ;\n /*0430*/ @P0 FMUL.FTZ R5, R8, 2.3283064365386962891e-10 ;\n.L_x_5:\n /*0440*/ IMAD.MOV.U32 R6, RZ, RZ, R9 ;\n /*0450*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ;\n /*0460*/ RET.REL.NODEC R6 `(_Z14rmsprop_kernelPfS_S_fff) ;\n\n\n\n\n .weak $__internal_1_$__cuda_sm3x_div_rn_noftz_f32_slowpath\n .type $__internal_1_$__cuda_sm3x_div_rn_noftz_f32_slowpath,@function\n .size $__internal_1_$__cuda_sm3x_div_rn_noftz_f32_slowpath,(.L_x_19 - $__internal_1_$__cuda_sm3x_div_rn_noftz_f32_slowpath)\n$__internal_1_$__cuda_sm3x_div_rn_noftz_f32_slowpath:\n /*0470*/ SHF.R.U32.HI R6, RZ, 0x17, R3 ;\n /*0480*/ BSSY B1, `(.L_x_6) ;\n /*0490*/ SHF.R.U32.HI R5, RZ, 0x17, R0.reuse ;\n /*04a0*/ LOP3.LUT R10, R6, 0xff, RZ, 0xc0, !PT ;\n /*04b0*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ;\n /*04c0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ;\n /*04d0*/ IADD3 R9, R10, -0x1, RZ ;\n /*04e0*/ IADD3 R8, R5, -0x1, RZ ;\n /*04f0*/ ISETP.GT.U32.AND P0, PT, R9, 0xfd, PT ;\n /*0500*/ ISETP.GT.U32.OR P0, PT, R8, 0xfd, P0 ;\n /*0510*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ;\n /*0520*/ @!P0 BRA `(.L_x_7) ;\n /*0530*/ FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ;\n /*0540*/ FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ;\n /*0550*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;\n /*0560*/ @P0 BRA `(.L_x_8) ;\n /*0570*/ LOP3.LUT P0, RZ, R3, 0x7fffffff, R6, 0xc8, !PT ;\n /*0580*/ @!P0 BRA `(.L_x_9) ;\n /*0590*/ FSETP.NEU.FTZ.AND P2, PT, |R0|.reuse, +INF , PT ;\n /*05a0*/ FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ;\n /*05b0*/ FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ;\n /*05c0*/ @!P1 BRA !P2, `(.L_x_9) ;\n /*05d0*/ LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ;\n /*05e0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ;\n /*05f0*/ @P1 BRA `(.L_x_10) ;\n /*0600*/ LOP3.LUT P1, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ;\n /*0610*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ;\n /*0620*/ @P0 BRA `(.L_x_11) ;\n /*0630*/ ISETP.GE.AND P0, PT, R8, RZ, PT ;\n /*0640*/ ISETP.GE.AND P1, PT, R9, RZ, PT ;\n /*0650*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ;\n /*0660*/ @!P0 FFMA R6, R0, 1.84467440737095516160e+19, RZ ;\n /*0670*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ;\n /*0680*/ @!P1 FFMA R3, R3, 1.84467440737095516160e+19, RZ ;\n /*0690*/ @!P1 IADD3 R7, R7, 0x40, RZ ;\n.L_x_7:\n /*06a0*/ LEA R0, R10, 0xc0800000, 0x17 ;\n /*06b0*/ BSSY B2, `(.L_x_12) ;\n /*06c0*/ IADD3 R5, R5, -0x7f, RZ ;\n /*06d0*/ IMAD.IADD R3, R3, 0x1, -R0 ;\n /*06e0*/ IMAD R0, R5, -0x800000, R6 ;\n /*06f0*/ MUFU.RCP R8, R3 ;\n /*0700*/ FADD.FTZ R9, -R3, -RZ ;\n /*0710*/ FFMA R11, R8, R9, 1 ;\n /*0720*/ FFMA R13, R8, R11, R8 ;\n /*0730*/ FFMA R6, R0, R13, RZ ;\n /*0740*/ FFMA R11, R9, R6, R0 ;\n /*0750*/ FFMA R6, R13, R11, R6 ;\n /*0760*/ FFMA R9, R9, R6, R0 ;\n /*0770*/ IADD3 R0, R5, 0x7f, -R10 ;\n /*0780*/ FFMA R3, R13, R9, R6 ;\n /*0790*/ IMAD.IADD R7, R0, 0x1, R7 ;\n /*07a0*/ SHF.R.U32.HI R0, RZ, 0x17, R3 ;\n /*07b0*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ;\n /*07c0*/ IMAD.IADD R8, R0, 0x1, R7 ;\n /*07d0*/ IADD3 R0, R8, -0x1, RZ ;\n /*07e0*/ ISETP.GE.U32.AND P0, PT, R0, 0xfe, PT ;\n /*07f0*/ @!P0 BRA `(.L_x_13) ;\n /*0800*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ;\n /*0810*/ @P0 BRA `(.L_x_14) ;\n /*0820*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ;\n /*0830*/ @P0 BRA `(.L_x_15) ;\n /*0840*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ;\n /*0850*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;\n /*0860*/ @!P0 BRA `(.L_x_15) ;\n /*0870*/ FFMA.RP R0, R13.reuse, R9.reuse, R6.reuse ;\n /*0880*/ FFMA.RM R5, R13, R9, R6 ;\n /*0890*/ IMAD.MOV R7, RZ, RZ, -R8 ;\n /*08a0*/ ISETP.NE.AND P1, PT, R8, RZ, PT ;\n /*08b0*/ FSETP.NEU.FTZ.AND P0, PT, R0, R5, PT ;\n /*08c0*/ FFMA.RZ R0, R13, R9, R6 ;\n /*08d0*/ IADD3 R5, R8, 0x20, RZ ;\n /*08e0*/ SEL R7, R7, RZ, P1 ;\n /*08f0*/ LOP3.LUT R0, R0, 0x7fffff, RZ, 0xc0, !PT ;\n /*0900*/ ISETP.NE.AND P1, PT, R8, RZ, PT ;\n /*0910*/ LOP3.LUT R0, R0, 0x800000, RZ, 0xfc, !PT ;\n /*0920*/ SHF.L.U32 R5, R0, R5, RZ ;\n /*0930*/ SHF.R.U32.HI R7, RZ, R7, R0 ;\n /*0940*/ ISETP.NE.AND P1, PT, R5, RZ, P1 ;\n /*0950*/ SHF.R.U32.HI R5, RZ, 0x1, R7 ;\n /*0960*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;\n /*0970*/ SEL R0, RZ, 0x1, !P0 ;\n /*0980*/ LOP3.LUT R0, R0, 0x1, R5, 0xf8, !PT ;\n /*0990*/ LOP3.LUT R0, R0, R7, RZ, 0xc0, !PT ;\n /*09a0*/ IMAD.IADD R0, R5, 0x1, R0 ;\n /*09b0*/ LOP3.LUT R3, R0, R3, RZ, 0xfc, !PT ;\n /*09c0*/ BRA `(.L_x_15) ;\n.L_x_14:\n /*09d0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;\n /*09e0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;\n /*09f0*/ BRA `(.L_x_15) ;\n.L_x_13:\n /*0a00*/ IMAD R3, R7, 0x800000, R3 ;\n.L_x_15:\n /*0a10*/ BSYNC B2 ;\n.L_x_12:\n /*0a20*/ BRA `(.L_x_16) ;\n.L_x_11:\n /*0a30*/ LOP3.LUT R3, R3, 0x80000000, R6, 0x48, !PT ;\n /*0a40*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;\n /*0a50*/ BRA `(.L_x_16) ;\n.L_x_10:\n /*0a60*/ LOP3.LUT R3, R3, 0x80000000, R6, 0x48, !PT ;\n /*0a70*/ BRA `(.L_x_16) ;\n.L_x_9:\n /*0a80*/ MUFU.RSQ R3, -QNAN ;\n /*0a90*/ BRA `(.L_x_16) ;\n.L_x_8:\n /*0aa0*/ FADD.FTZ R3, R0, R3 ;\n.L_x_16:\n /*0ab0*/ BSYNC B1 ;\n.L_x_6:\n /*0ac0*/ IMAD.MOV.U32 R6, RZ, RZ, R3 ;\n /*0ad0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ;\n /*0ae0*/ RET.REL.NODEC R2 `(_Z14rmsprop_kernelPfS_S_fff) ;\n.L_x_17:\n /*0af0*/ BRA `(.L_x_17);\n /*0b00*/ NOP;\n /*0b10*/ NOP;\n /*0b20*/ NOP;\n /*0b30*/ NOP;\n /*0b40*/ NOP;\n /*0b50*/ NOP;\n /*0b60*/ NOP;\n /*0b70*/ NOP;\n.L_x_19:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.protected\t_Z14rmsprop_kernelPfS_S_fff ; -- Begin function _Z14rmsprop_kernelPfS_S_fff\n\t.globl\t_Z14rmsprop_kernelPfS_S_fff\n\t.p2align\t8\n\t.type\t_Z14rmsprop_kernelPfS_S_fff,@function\n_Z14rmsprop_kernelPfS_S_fff: ; @_Z14rmsprop_kernelPfS_S_fff\n; %bb.0:\n\ts_load_b32 s2, s[0:1], 0x34\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s2, s2, 0xffff\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]\n\ts_mov_b32 s2, exec_lo\n\tv_cmpx_gt_i32_e32 32, v1\n\ts_cbranch_execz .LBB0_4\n; %bb.1:\n\ts_clause 0x1\n\ts_load_b64 s[2:3], s[0:1], 0x0\n\ts_load_b64 s[4:5], s[0:1], 0x10\n\tv_ashrrev_i32_e32 v2, 31, v1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[5:6], 2, v[1:2]\n\ts_waitcnt lgkmcnt(0)\n\tv_add_co_u32 v3, vcc_lo, s2, v5\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v4, vcc_lo, s3, v6, vcc_lo\n\tv_add_co_u32 v5, vcc_lo, s4, v5\n\tv_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo\n\tglobal_load_b32 v0, v[3:4], off\n\ts_mov_b32 s2, 0\n\tglobal_load_b32 v8, v[5:6], off\n\ts_waitcnt vmcnt(1)\n\tv_mul_f32_e32 v0, v0, v0\n.LBB0_2: ; =>This Inner Loop Header: Depth=1\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_add_f32_e32 v7, v8, v0\n\tglobal_atomic_cmpswap_b32 v7, v[5:6], v[7:8], off glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e32 vcc_lo, v7, v8\n\tv_mov_b32_e32 v8, v7\n\ts_or_b32 s2, vcc_lo, s2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s2\n\ts_cbranch_execnz .LBB0_2\n; %bb.3:\n\ts_or_b32 exec_lo, exec_lo, s2\n\tglobal_load_b32 v5, v[5:6], off\n\tglobal_load_b32 v3, v[3:4], off\n\ts_load_b64 s[2:3], s[0:1], 0x8\n\tv_lshlrev_b64 v[0:1], 2, v[1:2]\n\ts_clause 0x1\n\ts_load_b32 s4, s[0:1], 0x18\n\ts_load_b32 s0, s[0:1], 0x20\n\ts_waitcnt lgkmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)\n\tv_add_co_u32 v0, vcc_lo, s2, v0\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo\n\tglobal_load_b32 v2, v[0:1], off\n\ts_waitcnt vmcnt(1)\n\tv_dual_add_f32 v4, s0, v5 :: v_dual_mul_f32 v3, s4, v3\n\tv_mul_f32_e32 v5, 0x4f800000, v4\n\tv_cmp_gt_f32_e32 vcc_lo, 0xf800000, v4\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cndmask_b32_e32 v4, v4, v5, vcc_lo\n\tv_sqrt_f32_e32 v5, v4\n\ts_waitcnt_depctr 0xfff\n\tv_add_nc_u32_e32 v6, -1, v5\n\tv_add_nc_u32_e32 v7, 1, v5\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_fma_f32 v8, -v6, v5, v4\n\tv_fma_f32 v9, -v7, v5, v4\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cmp_ge_f32_e64 s0, 0, v8\n\tv_cndmask_b32_e64 v5, v5, v6, s0\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cmp_lt_f32_e64 s0, 0, v9\n\tv_cndmask_b32_e64 v5, v5, v7, s0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mul_f32_e32 v6, 0x37800000, v5\n\tv_cndmask_b32_e32 v5, v5, v6, vcc_lo\n\tv_cmp_class_f32_e64 vcc_lo, v4, 0x260\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_cndmask_b32_e32 v4, v5, v4, vcc_lo\n\tv_div_scale_f32 v5, null, v4, v4, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_rcp_f32_e32 v6, v5\n\ts_waitcnt_depctr 0xfff\n\tv_fma_f32 v7, -v5, v6, 1.0\n\tv_fmac_f32_e32 v6, v7, v6\n\tv_div_scale_f32 v7, vcc_lo, v3, v4, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mul_f32_e32 v8, v7, v6\n\tv_fma_f32 v9, -v5, v8, v7\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmac_f32_e32 v8, v9, v6\n\tv_fma_f32 v5, -v5, v8, v7\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_div_fmas_f32 v5, v5, v6, v8\n\tv_div_fixup_f32 v3, v5, v4, v3\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_sub_f32_e32 v2, v2, v3\n\tglobal_store_b32 v[0:1], v2, off\n.LBB0_4:\n\ts_nop 0\n\ts_sendmsg sendmsg(MSG_DEALLOC_VGPRS)\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z14rmsprop_kernelPfS_S_fff\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 296\n\t\t.amdhsa_user_sgpr_count 15\n\t\t.amdhsa_user_sgpr_dispatch_ptr 0\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 0\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 0\n\t\t.amdhsa_next_free_vgpr 10\n\t\t.amdhsa_next_free_sgpr 16\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end0:\n\t.size\t_Z14rmsprop_kernelPfS_S_fff, .Lfunc_end0-_Z14rmsprop_kernelPfS_S_fff\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 544\n; NumSgprs: 18\n; NumVgprs: 10\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 2\n; VGPRBlocks: 1\n; NumSGPRsForWavesPerEU: 18\n; NumVGPRsForWavesPerEU: 10\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 15\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 16\n .size: 8\n .value_kind: global_buffer\n - .offset: 24\n .size: 4\n .value_kind: by_value\n - .offset: 28\n .size: 4\n .value_kind: by_value\n - .offset: 32\n .size: 4\n .value_kind: by_value\n - .offset: 40\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 44\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 48\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 52\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 54\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 56\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 58\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 60\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 62\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 80\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 88\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 96\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 104\n .size: 2\n .value_kind: hidden_grid_dims\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 296\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z14rmsprop_kernelPfS_S_fff\n .private_segment_fixed_size: 0\n .sgpr_count: 18\n .sgpr_spill_count: 0\n .symbol: _Z14rmsprop_kernelPfS_S_fff.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 10\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162581,"cells":{"id":{"kind":"string","value":"a3704e34a38394d5fc7cfe72e08a6f69c746da04_O0"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z6squarePiS_ --------------------------\n .section .text._Z6squarePiS_,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=16\"\n .align 128\n\n\n\n\n .global _Z6squarePiS_\n .type _Z6squarePiS_,@function\n .size _Z6squarePiS_,(.L_x_5 - _Z6squarePiS_)\n .other _Z6squarePiS_,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z6squarePiS_:\n.text._Z6squarePiS_:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ MOV R10, c[0x0][0x118] ;\n /*0020*/ MOV R11, c[0x0][0x11c] ;\n /*0030*/ MOV R2, RZ ;\n /*0040*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0050*/ MOV R9, R2 ;\n /*0060*/ MOV R13, R3 ;\n /*0070*/ MOV R9, R9 ;\n /*0080*/ MOV R13, R13 ;\n /*0090*/ MOV R2, 0x8 ;\n /*00a0*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*00b0*/ MOV R7, R2 ;\n /*00c0*/ MOV R8, R3 ;\n /*00d0*/ MOV R7, R7 ;\n /*00e0*/ MOV R8, R8 ;\n /*00f0*/ MOV R7, R7 ;\n /*0100*/ MOV R8, R8 ;\n /*0110*/ MOV R0, c[0x0][0x0] ;\n /*0120*/ S2R R6, SR_CTAID.X ;\n /*0130*/ MOV R6, R6 ;\n /*0140*/ S2R R2, SR_TID.X ;\n /*0150*/ MOV R2, R2 ;\n /*0160*/ IMAD R0, R6, R0, R2 ;\n /*0170*/ MOV R2, R0 ;\n /*0180*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ;\n /*0190*/ MOV R2, R2 ;\n /*01a0*/ MOV R3, R3 ;\n /*01b0*/ MOV R2, R2 ;\n /*01c0*/ MOV R3, R3 ;\n /*01d0*/ IMAD.WIDE R4, R0, 0x4, RZ ;\n /*01e0*/ MOV R0, R4 ;\n /*01f0*/ MOV R12, R5 ;\n /*0200*/ IADD3 R0, P0, R7, R0, RZ ;\n /*0210*/ IADD3.X R12, R8, R12, RZ, P0, !PT ;\n /*0220*/ MOV R7, 0x1 ;\n /*0230*/ MOV R4, R0 ;\n /*0240*/ MOV R5, R12 ;\n /*0250*/ MOV R4, R4 ;\n /*0260*/ MOV R5, R5 ;\n /*0270*/ R2UR UR4, R10 ;\n /*0280*/ R2UR UR5, R11 ;\n /*0290*/ STG.E [R4.64], R7 ;\n /*02a0*/ ISETP.LT.AND P0, PT, R6, RZ, PT ;\n /*02b0*/ MOV R5, R9 ;\n /*02c0*/ MOV R9, R13 ;\n /*02d0*/ MOV R6, R6 ;\n /*02e0*/ MOV R4, R2 ;\n /*02f0*/ MOV R8, R3 ;\n /*0300*/ MOV R4, R4 ;\n /*0310*/ MOV R8, R8 ;\n /*0320*/ MOV R0, R0 ;\n /*0330*/ MOV R2, R12 ;\n /*0340*/ MOV R12, R7 ;\n /*0350*/ @P0 BRA `(.L_x_0) ;\n /*0360*/ MOV R3, R5 ;\n /*0370*/ MOV R5, R9 ;\n /*0380*/ SHF.L.U64.HI R7, R4, 0x2, R8 ;\n /*0390*/ SHF.L.U32 R4, R4, 0x2, RZ ;\n /*03a0*/ IADD3 R4, P0, R3, R4, RZ ;\n /*03b0*/ IADD3.X R7, R5, R7, RZ, P0, !PT ;\n /*03c0*/ IADD3 R3, R6, 0x1, RZ ;\n /*03d0*/ LOP3.LUT R5, R3, 0x3, RZ, 0xc0, !PT ;\n /*03e0*/ ISETP.LT.U32.AND P0, PT, R6, 0x3, PT ;\n /*03f0*/ MOV R3, R4 ;\n /*0400*/ MOV R4, R7 ;\n /*0410*/ MOV R5, R5 ;\n /*0420*/ @P0 BRA `(.L_x_1) ;\n /*0430*/ IADD3 R6, R6, -R5, RZ ;\n /*0440*/ MOV R12, 0x1 ;\n /*0450*/ MOV R6, R6 ;\n /*0460*/ MOV R12, R12 ;\n.L_x_2:\n /*0470*/ MOV R8, R3 ;\n /*0480*/ MOV R9, R4 ;\n /*0490*/ MOV R8, R8 ;\n /*04a0*/ MOV R9, R9 ;\n /*04b0*/ R2UR UR4, R10 ;\n /*04c0*/ R2UR UR5, R11 ;\n /*04d0*/ LDG.E R8, [R8.64] ;\n /*04e0*/ IMAD R12, R12, R8, RZ ;\n /*04f0*/ MOV R8, R0 ;\n /*0500*/ MOV R9, R2 ;\n /*0510*/ MOV R8, R8 ;\n /*0520*/ MOV R9, R9 ;\n /*0530*/ R2UR UR4, R10 ;\n /*0540*/ R2UR UR5, R11 ;\n /*0550*/ STG.E [R8.64], R12 ;\n /*0560*/ MOV R8, R3 ;\n /*0570*/ MOV R9, R4 ;\n /*0580*/ MOV R8, R8 ;\n /*0590*/ MOV R9, R9 ;\n /*05a0*/ R2UR UR4, R10 ;\n /*05b0*/ R2UR UR5, R11 ;\n /*05c0*/ LDG.E R8, [R8.64] ;\n /*05d0*/ IMAD R12, R12, R8, RZ ;\n /*05e0*/ MOV R8, R0 ;\n /*05f0*/ MOV R9, R2 ;\n /*0600*/ MOV R8, R8 ;\n /*0610*/ MOV R9, R9 ;\n /*0620*/ R2UR UR4, R10 ;\n /*0630*/ R2UR UR5, R11 ;\n /*0640*/ STG.E [R8.64], R12 ;\n /*0650*/ MOV R8, R3 ;\n /*0660*/ MOV R9, R4 ;\n /*0670*/ MOV R8, R8 ;\n /*0680*/ MOV R9, R9 ;\n /*0690*/ R2UR UR4, R10 ;\n /*06a0*/ R2UR UR5, R11 ;\n /*06b0*/ LDG.E R8, [R8.64] ;\n /*06c0*/ IMAD R12, R12, R8, RZ ;\n /*06d0*/ MOV R8, R0 ;\n /*06e0*/ MOV R9, R2 ;\n /*06f0*/ MOV R8, R8 ;\n /*0700*/ MOV R9, R9 ;\n /*0710*/ R2UR UR4, R10 ;\n /*0720*/ R2UR UR5, R11 ;\n /*0730*/ STG.E [R8.64], R12 ;\n /*0740*/ MOV R8, R3 ;\n /*0750*/ MOV R9, R4 ;\n /*0760*/ MOV R8, R8 ;\n /*0770*/ MOV R9, R9 ;\n /*0780*/ R2UR UR4, R10 ;\n /*0790*/ R2UR UR5, R11 ;\n /*07a0*/ LDG.E R8, [R8.64] ;\n /*07b0*/ IMAD R12, R12, R8, RZ ;\n /*07c0*/ MOV R8, R0 ;\n /*07d0*/ MOV R9, R2 ;\n /*07e0*/ MOV R8, R8 ;\n /*07f0*/ MOV R9, R9 ;\n /*0800*/ R2UR UR4, R10 ;\n /*0810*/ R2UR UR5, R11 ;\n /*0820*/ STG.E [R8.64], R12 ;\n /*0830*/ IADD3 R6, R6, -0x4, RZ ;\n /*0840*/ ISETP.NE.AND P0, PT, R6, -0x1, PT ;\n /*0850*/ MOV R12, R12 ;\n /*0860*/ MOV R6, R6 ;\n /*0870*/ @P0 BRA `(.L_x_2) ;\n.L_x_1:\n /*0880*/ ISETP.EQ.AND P0, PT, R5, RZ, PT ;\n /*0890*/ @P0 BRA `(.L_x_0) ;\n.L_x_3:\n /*08a0*/ MOV R6, R3 ;\n /*08b0*/ MOV R7, R4 ;\n /*08c0*/ MOV R6, R6 ;\n /*08d0*/ MOV R7, R7 ;\n /*08e0*/ R2UR UR4, R10 ;\n /*08f0*/ R2UR UR5, R11 ;\n /*0900*/ LDG.E R6, [R6.64] ;\n /*0910*/ IMAD R12, R12, R6, RZ ;\n /*0920*/ MOV R6, R0 ;\n /*0930*/ MOV R7, R2 ;\n /*0940*/ MOV R6, R6 ;\n /*0950*/ MOV R7, R7 ;\n /*0960*/ R2UR UR4, R10 ;\n /*0970*/ R2UR UR5, R11 ;\n /*0980*/ STG.E [R6.64], R12 ;\n /*0990*/ IADD3 R5, R5, -0x1, RZ ;\n /*09a0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ;\n /*09b0*/ MOV R12, R12 ;\n /*09c0*/ MOV R5, R5 ;\n /*09d0*/ @P0 BRA `(.L_x_3) ;\n.L_x_0:\n /*09e0*/ EXIT ;\n.L_x_4:\n /*09f0*/ BRA `(.L_x_4);\n /*0a00*/ NOP;\n /*0a10*/ NOP;\n /*0a20*/ NOP;\n /*0a30*/ NOP;\n /*0a40*/ NOP;\n /*0a50*/ NOP;\n /*0a60*/ NOP;\n /*0a70*/ NOP;\n.L_x_5:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.protected\t_Z6squarePiS_ ; -- Begin function _Z6squarePiS_\n\t.globl\t_Z6squarePiS_\n\t.p2align\t8\n\t.type\t_Z6squarePiS_,@function\n_Z6squarePiS_: ; @_Z6squarePiS_\n; %bb.0:\n\ts_clause 0x1\n\ts_load_b32 s4, s[0:1], 0x1c\n\ts_load_b64 s[2:3], s[0:1], 0x8\n\tv_mov_b32_e32 v4, 1\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s4, s4, 0xffff\n\ts_cmp_lt_i32 s15, 0\n\tv_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_ashrrev_i32_e32 v2, 31, v1\n\tv_lshlrev_b64 v[2:3], 2, v[1:2]\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, s2, v2\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo\n\tglobal_store_b32 v[0:1], v4, off\n\ts_cbranch_scc1 .LBB0_3\n; %bb.1:\n\ts_load_b64 s[0:1], s[0:1], 0x0\n\ts_waitcnt lgkmcnt(0)\n\tv_add_co_u32 v2, vcc_lo, s0, v2\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo\n\ts_add_i32 s0, s15, 1\n.LBB0_2: ; =>This Inner Loop Header: Depth=1\n\tglobal_load_b32 v4, v[2:3], off\n\tglobal_load_b32 v5, v[0:1], off\n\ts_add_i32 s0, s0, -1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_cmp_eq_u32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v4, v5, v4\n\tglobal_store_b32 v[0:1], v4, off\n\ts_cbranch_scc0 .LBB0_2\n.LBB0_3:\n\ts_nop 0\n\ts_sendmsg sendmsg(MSG_DEALLOC_VGPRS)\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z6squarePiS_\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 272\n\t\t.amdhsa_user_sgpr_count 15\n\t\t.amdhsa_user_sgpr_dispatch_ptr 0\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 0\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 0\n\t\t.amdhsa_next_free_vgpr 6\n\t\t.amdhsa_next_free_sgpr 16\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end0:\n\t.size\t_Z6squarePiS_, .Lfunc_end0-_Z6squarePiS_\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 184\n; NumSgprs: 18\n; NumVgprs: 6\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 2\n; VGPRBlocks: 0\n; NumSGPRsForWavesPerEU: 18\n; NumVGPRsForWavesPerEU: 6\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 15\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .offset: 16\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 20\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 24\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 28\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 30\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 32\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 34\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 36\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 38\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 56\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 64\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 72\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 80\n .size: 2\n .value_kind: hidden_grid_dims\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 272\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z6squarePiS_\n .private_segment_fixed_size: 0\n .sgpr_count: 18\n .sgpr_spill_count: 0\n .symbol: _Z6squarePiS_.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 6\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162582,"cells":{"id":{"kind":"string","value":"13c07395dba1865ae280a4f20b0a0232457782db_O0"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii --------------------------\n .section .text._Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii,\"ax\",@progbits\n .sectionflags @\"SHF_BARRIERS=1\"\n .sectioninfo @\"SHI_REGISTERS=56\"\n .align 128\n\n\n\n\n .global _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii\n .type _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii,@function\n .size _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii,(.L_x_20 - _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii)\n .other _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii:\n.text._Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ MOV R44, c[0x0][0x118] ;\n /*0020*/ MOV R45, c[0x0][0x11c] ;\n /*0030*/ MOV R2, RZ ;\n /*0040*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0050*/ MOV R10, R2 ;\n /*0060*/ MOV R11, R3 ;\n /*0070*/ MOV R10, R10 ;\n /*0080*/ MOV R11, R11 ;\n /*0090*/ MOV R2, 0x10 ;\n /*00a0*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*00b0*/ MOV R8, R2 ;\n /*00c0*/ MOV R9, R3 ;\n /*00d0*/ MOV R8, R8 ;\n /*00e0*/ MOV R9, R9 ;\n /*00f0*/ MOV R2, 0x20 ;\n /*0100*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0110*/ MOV R0, R2 ;\n /*0120*/ MOV R2, R3 ;\n /*0130*/ MOV R0, R0 ;\n /*0140*/ MOV R2, R2 ;\n /*0150*/ MOV R4, 0x28 ;\n /*0160*/ LDC.64 R4, c[0x0][R4+0x160] ;\n /*0170*/ MOV R3, R4 ;\n /*0180*/ MOV R4, R5 ;\n /*0190*/ MOV R3, R3 ;\n /*01a0*/ MOV R4, R4 ;\n /*01b0*/ MOV R6, 0x30 ;\n /*01c0*/ LDC.64 R6, c[0x0][R6+0x160] ;\n /*01d0*/ MOV R5, R6 ;\n /*01e0*/ MOV R6, R7 ;\n /*01f0*/ MOV R5, R5 ;\n /*0200*/ MOV R6, R6 ;\n /*0210*/ MOV R7, 0x38 ;\n /*0220*/ LDC R7, c[0x0][R7+0x160] ;\n /*0230*/ MOV R12, R7 ;\n /*0240*/ MOV R7, 0x40 ;\n /*0250*/ LDC R7, c[0x0][R7+0x160] ;\n /*0260*/ MOV R43, R7 ;\n /*0270*/ MOV R7, R8 ;\n /*0280*/ MOV R8, R9 ;\n /*0290*/ MOV R9, R10 ;\n /*02a0*/ MOV R10, R11 ;\n /*02b0*/ S2R R11, SR_CTAID.Z ;\n /*02c0*/ MOV R11, R11 ;\n /*02d0*/ IMAD R13, R11, R43, RZ ;\n /*02e0*/ S2R R11, SR_CTAID.Y ;\n /*02f0*/ MOV R11, R11 ;\n /*0300*/ MOV R14, c[0x0][0x4] ;\n /*0310*/ IMAD R11, R14, R11, RZ ;\n /*0320*/ S2R R20, SR_CTAID.X ;\n /*0330*/ MOV R20, R20 ;\n /*0340*/ IMAD R16, R20, R12, RZ ;\n /*0350*/ MOV R13, R13 ;\n /*0360*/ SHF.R.S32.HI R12, RZ, 0x1f, R13 ;\n /*0370*/ LOP3.LUT R13, R13, R12, RZ, 0x3c, !PT ;\n /*0380*/ LOP3.LUT R12, R13, R12, RZ, 0x3c, !PT ;\n /*0390*/ LOP3.LUT R13, R13, R12, RZ, 0x3c, !PT ;\n /*03a0*/ MOV R12, R12 ;\n /*03b0*/ MOV R13, R13 ;\n /*03c0*/ MOV R14, R16 ;\n /*03d0*/ SHF.R.S32.HI R15, RZ, 0x1f, R14 ;\n /*03e0*/ MOV R14, R14 ;\n /*03f0*/ MOV R15, R15 ;\n /*0400*/ MOV R14, R14 ;\n /*0410*/ MOV R15, R15 ;\n /*0420*/ IADD3 R16, R16, 0x1, RZ ;\n /*0430*/ MOV R16, R16 ;\n /*0440*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ;\n /*0450*/ MOV R16, R16 ;\n /*0460*/ MOV R17, R17 ;\n /*0470*/ MOV R16, R16 ;\n /*0480*/ MOV R17, R17 ;\n /*0490*/ S2R R21, SR_TID.Y ;\n /*04a0*/ MOV R21, R21 ;\n /*04b0*/ IADD3 R18, R11, R21, RZ ;\n /*04c0*/ MOV R18, R18 ;\n /*04d0*/ SHF.R.S32.HI R19, RZ, 0x1f, R18 ;\n /*04e0*/ MOV R18, R18 ;\n /*04f0*/ MOV R19, R19 ;\n /*0500*/ MOV R18, R18 ;\n /*0510*/ MOV R19, R19 ;\n /*0520*/ ISETP.LT.AND P0, PT, R43, 0x1, PT ;\n /*0530*/ MOV R0, R0 ;\n /*0540*/ MOV R2, R2 ;\n /*0550*/ MOV R3, R3 ;\n /*0560*/ MOV R4, R4 ;\n /*0570*/ MOV R5, R5 ;\n /*0580*/ MOV R6, R6 ;\n /*0590*/ MOV R43, R43 ;\n /*05a0*/ MOV R7, R7 ;\n /*05b0*/ MOV R8, R8 ;\n /*05c0*/ MOV R9, R9 ;\n /*05d0*/ MOV R10, R10 ;\n /*05e0*/ MOV R22, R11 ;\n /*05f0*/ MOV R23, R20 ;\n /*0600*/ MOV R11, R12 ;\n /*0610*/ MOV R12, R13 ;\n /*0620*/ MOV R11, R11 ;\n /*0630*/ MOV R12, R12 ;\n /*0640*/ MOV R13, R14 ;\n /*0650*/ MOV R14, R15 ;\n /*0660*/ MOV R13, R13 ;\n /*0670*/ MOV R14, R14 ;\n /*0680*/ MOV R15, R16 ;\n /*0690*/ MOV R16, R17 ;\n /*06a0*/ MOV R15, R15 ;\n /*06b0*/ MOV R16, R16 ;\n /*06c0*/ MOV R24, R21 ;\n /*06d0*/ MOV R17, R18 ;\n /*06e0*/ MOV R18, R19 ;\n /*06f0*/ MOV R17, R17 ;\n /*0700*/ MOV R18, R18 ;\n /*0710*/ @P0 BRA `(.L_x_0) ;\n /*0720*/ MOV R20, R22 ;\n /*0730*/ SHF.R.S32.HI R21, RZ, 0x1f, R20 ;\n /*0740*/ MOV R20, R20 ;\n /*0750*/ MOV R21, R21 ;\n /*0760*/ MOV R20, R20 ;\n /*0770*/ MOV R21, R21 ;\n /*0780*/ MOV R19, c[0x0][0xc] ;\n /*0790*/ MOV R24, R24 ;\n /*07a0*/ SHF.R.S32.HI R25, RZ, 0x1f, R24 ;\n /*07b0*/ MOV R24, R24 ;\n /*07c0*/ MOV R25, R25 ;\n /*07d0*/ MOV R31, R24 ;\n /*07e0*/ MOV R32, R25 ;\n /*07f0*/ MOV R31, R31 ;\n /*0800*/ MOV R32, R32 ;\n /*0810*/ IMAD.WIDE.U32 R24, R19, 0x2, RZ ;\n /*0820*/ SHF.L.U32 R23, R23, 0x1, RZ ;\n /*0830*/ MOV R23, R23 ;\n /*0840*/ MOV R26, R23 ;\n /*0850*/ MOV R27, RZ ;\n /*0860*/ MOV R22, R22 ;\n /*0870*/ MOV R22, R22 ;\n /*0880*/ MOV R30, RZ ;\n /*0890*/ IADD3 R28, P0, R22, R31, RZ ;\n /*08a0*/ IADD3.X R30, R30, R32, RZ, P0, !PT ;\n /*08b0*/ LOP3.LUT R29, R43, 0x3, RZ, 0xc0, !PT ;\n /*08c0*/ IADD3 R19, R43, -0x1, RZ ;\n /*08d0*/ ISETP.LT.U32.AND P0, PT, R19, 0x3, PT ;\n /*08e0*/ MOV R42, RZ ;\n /*08f0*/ MOV R19, R20 ;\n /*0900*/ MOV R20, R21 ;\n /*0910*/ MOV R19, R19 ;\n /*0920*/ MOV R20, R20 ;\n /*0930*/ MOV R21, R31 ;\n /*0940*/ MOV R22, R32 ;\n /*0950*/ MOV R23, R24 ;\n /*0960*/ MOV R24, R25 ;\n /*0970*/ MOV R23, R23 ;\n /*0980*/ MOV R24, R24 ;\n /*0990*/ MOV R25, R26 ;\n /*09a0*/ MOV R26, R27 ;\n /*09b0*/ MOV R25, R25 ;\n /*09c0*/ MOV R26, R26 ;\n /*09d0*/ MOV R27, R28 ;\n /*09e0*/ MOV R28, R30 ;\n /*09f0*/ MOV R29, R29 ;\n /*0a00*/ MOV R42, R42 ;\n /*0a10*/ @P0 BRA `(.L_x_1) ;\n /*0a20*/ MOV R11, R11 ;\n /*0a30*/ IADD3 R43, R43, -R29, RZ ;\n /*0a40*/ IADD3 R34, P0, R11, 0x3, RZ ;\n /*0a50*/ IADD3.X R32, R12, RZ, RZ, P0, !PT ;\n /*0a60*/ MOV R30, RZ ;\n /*0a70*/ MOV R31, RZ ;\n /*0a80*/ MOV R30, R30 ;\n /*0a90*/ MOV R31, R31 ;\n /*0aa0*/ IMAD.WIDE.U32 R30, R0, R34, R30 ;\n /*0ab0*/ MOV R33, R30 ;\n /*0ac0*/ MOV R35, R31 ;\n /*0ad0*/ MOV R33, R33 ;\n /*0ae0*/ IMAD.WIDE.U32 R30, R2, R34, RZ ;\n /*0af0*/ MOV R34, R30 ;\n /*0b00*/ MOV R30, R31 ;\n /*0b10*/ MOV R31, R30 ;\n /*0b20*/ MOV R30, R34 ;\n /*0b30*/ IMAD.WIDE.U32 R30, P0, R0, R32, R30 ;\n /*0b40*/ MOV R34, R30 ;\n /*0b50*/ MOV R30, R31 ;\n /*0b60*/ IADD3 R34, P1, R34, R35, RZ ;\n /*0b70*/ IADD3 R30, RZ, R30, RZ ;\n /*0b80*/ IADD3.X R31, RZ, RZ, RZ, P0, !PT ;\n /*0b90*/ MOV R30, R30 ;\n /*0ba0*/ MOV R31, R31 ;\n /*0bb0*/ MOV R30, R30 ;\n /*0bc0*/ MOV R31, R31 ;\n /*0bd0*/ IMAD.WIDE.U32.X R30, R2, R32, R30, P1 ;\n /*0be0*/ MOV R32, R30 ;\n /*0bf0*/ MOV R30, R31 ;\n /*0c00*/ IADD3 R33, P0, R33, R21, RZ ;\n /*0c10*/ IADD3.X R32, R34, R22, RZ, P0, !PT ;\n /*0c20*/ IADD3 R34, P0, R33, R19, RZ ;\n /*0c30*/ IADD3.X R32, R32, R20, RZ, P0, !PT ;\n /*0c40*/ MOV R30, RZ ;\n /*0c50*/ MOV R31, RZ ;\n /*0c60*/ MOV R30, R30 ;\n /*0c70*/ MOV R31, R31 ;\n /*0c80*/ IMAD.WIDE.U32 R30, R3, R34, R30 ;\n /*0c90*/ MOV R33, R30 ;\n /*0ca0*/ MOV R46, R31 ;\n /*0cb0*/ MOV R33, R33 ;\n /*0cc0*/ IMAD.WIDE.U32 R30, R4, R34, RZ ;\n /*0cd0*/ MOV R34, R30 ;\n /*0ce0*/ MOV R30, R31 ;\n /*0cf0*/ MOV R31, R30 ;\n /*0d00*/ MOV R30, R34 ;\n /*0d10*/ IMAD.WIDE.U32 R30, P0, R3, R32, R30 ;\n /*0d20*/ MOV R34, R30 ;\n /*0d30*/ MOV R30, R31 ;\n /*0d40*/ IADD3 R46, P1, R34, R46, RZ ;\n /*0d50*/ IADD3 R30, RZ, R30, RZ ;\n /*0d60*/ IADD3.X R31, RZ, RZ, RZ, P0, !PT ;\n /*0d70*/ MOV R30, R30 ;\n /*0d80*/ MOV R31, R31 ;\n /*0d90*/ MOV R30, R30 ;\n /*0da0*/ MOV R31, R31 ;\n /*0db0*/ IMAD.WIDE.U32.X R30, R4, R32, R30, P1 ;\n /*0dc0*/ MOV R32, R30 ;\n /*0dd0*/ MOV R30, R31 ;\n /*0de0*/ IADD3 R33, P0, R33, R13, RZ ;\n /*0df0*/ IADD3.X R46, R46, R14, RZ, P0, !PT ;\n /*0e00*/ SHF.L.U64.HI R46, R33, 0x3, R46 ;\n /*0e10*/ SHF.L.U32 R47, R33, 0x3, RZ ;\n /*0e20*/ IADD3 R47, P0, R9, R47, RZ ;\n /*0e30*/ IADD3.X R46, R10, R46, RZ, P0, !PT ;\n /*0e40*/ IADD3 R47, P0, R47, 0x8, RZ ;\n /*0e50*/ IADD3.X R46, R46, RZ, RZ, P0, !PT ;\n /*0e60*/ MOV R30, RZ ;\n /*0e70*/ MOV R31, RZ ;\n /*0e80*/ MOV R30, R30 ;\n /*0e90*/ MOV R31, R31 ;\n /*0ea0*/ IMAD.WIDE.U32 R30, R3, R0, R30 ;\n /*0eb0*/ MOV R32, R30 ;\n /*0ec0*/ MOV R33, R31 ;\n /*0ed0*/ MOV R32, R32 ;\n /*0ee0*/ IMAD.WIDE.U32 R30, R4, R0, RZ ;\n /*0ef0*/ MOV R34, R30 ;\n /*0f00*/ MOV R30, R31 ;\n /*0f10*/ MOV R31, R30 ;\n /*0f20*/ MOV R30, R34 ;\n /*0f30*/ IMAD.WIDE.U32 R30, P0, R3, R2, R30 ;\n /*0f40*/ MOV R34, R30 ;\n /*0f50*/ MOV R30, R31 ;\n /*0f60*/ IADD3 R33, P1, R34, R33, RZ ;\n /*0f70*/ IADD3 R30, RZ, R30, RZ ;\n /*0f80*/ IADD3.X R31, RZ, RZ, RZ, P0, !PT ;\n /*0f90*/ MOV R30, R30 ;\n /*0fa0*/ MOV R31, R31 ;\n /*0fb0*/ MOV R30, R30 ;\n /*0fc0*/ MOV R31, R31 ;\n /*0fd0*/ IMAD.WIDE.U32.X R30, R4, R2, R30, P1 ;\n /*0fe0*/ MOV R34, R30 ;\n /*0ff0*/ MOV R30, R31 ;\n /*1000*/ SHF.L.U64.HI R33, R32, 0x5, R33 ;\n /*1010*/ SHF.L.U32 R32, R32, 0x5, RZ ;\n /*1020*/ IADD3 R36, P0, R11, 0x2, RZ ;\n /*1030*/ IADD3.X R34, R12, RZ, RZ, P0, !PT ;\n /*1040*/ MOV R30, RZ ;\n /*1050*/ MOV R31, RZ ;\n /*1060*/ MOV R30, R30 ;\n /*1070*/ MOV R31, R31 ;\n /*1080*/ IMAD.WIDE.U32 R30, R0, R36, R30 ;\n /*1090*/ MOV R35, R30 ;\n /*10a0*/ MOV R37, R31 ;\n /*10b0*/ MOV R35, R35 ;\n /*10c0*/ IMAD.WIDE.U32 R30, R2, R36, RZ ;\n /*10d0*/ MOV R36, R30 ;\n /*10e0*/ MOV R30, R31 ;\n /*10f0*/ MOV R31, R30 ;\n /*1100*/ MOV R30, R36 ;\n /*1110*/ IMAD.WIDE.U32 R30, P0, R0, R34, R30 ;\n /*1120*/ MOV R36, R30 ;\n /*1130*/ MOV R30, R31 ;\n /*1140*/ IADD3 R36, P1, R36, R37, RZ ;\n /*1150*/ IADD3 R30, RZ, R30, RZ ;\n /*1160*/ IADD3.X R31, RZ, RZ, RZ, P0, !PT ;\n /*1170*/ MOV R30, R30 ;\n /*1180*/ MOV R31, R31 ;\n /*1190*/ MOV R30, R30 ;\n /*11a0*/ MOV R31, R31 ;\n /*11b0*/ IMAD.WIDE.U32.X R30, R2, R34, R30, P1 ;\n /*11c0*/ MOV R34, R30 ;\n /*11d0*/ MOV R30, R31 ;\n /*11e0*/ IADD3 R35, P0, R35, R21, RZ ;\n /*11f0*/ IADD3.X R34, R36, R22, RZ, P0, !PT ;\n /*1200*/ IADD3 R36, P0, R35, R19, RZ ;\n /*1210*/ IADD3.X R34, R34, R20, RZ, P0, !PT ;\n /*1220*/ MOV R30, RZ ;\n /*1230*/ MOV R31, RZ ;\n /*1240*/ MOV R30, R30 ;\n /*1250*/ MOV R31, R31 ;\n /*1260*/ IMAD.WIDE.U32 R30, R3, R36, R30 ;\n /*1270*/ MOV R35, R30 ;\n /*1280*/ MOV R37, R31 ;\n /*1290*/ MOV R35, R35 ;\n /*12a0*/ IMAD.WIDE.U32 R30, R4, R36, RZ ;\n /*12b0*/ MOV R36, R30 ;\n /*12c0*/ MOV R30, R31 ;\n /*12d0*/ MOV R31, R30 ;\n /*12e0*/ MOV R30, R36 ;\n /*12f0*/ IMAD.WIDE.U32 R30, P0, R3, R34, R30 ;\n /*1300*/ MOV R36, R30 ;\n /*1310*/ MOV R30, R31 ;\n /*1320*/ IADD3 R36, P1, R36, R37, RZ ;\n /*1330*/ IADD3 R30, RZ, R30, RZ ;\n /*1340*/ IADD3.X R31, RZ, RZ, RZ, P0, !PT ;\n /*1350*/ MOV R30, R30 ;\n /*1360*/ MOV R31, R31 ;\n /*1370*/ MOV R30, R30 ;\n /*1380*/ MOV R31, R31 ;\n /*1390*/ IMAD.WIDE.U32.X R30, R4, R34, R30, P1 ;\n /*13a0*/ MOV R34, R30 ;\n /*13b0*/ MOV R30, R31 ;\n /*13c0*/ IADD3 R34, P0, R35, R13, RZ ;\n /*13d0*/ IADD3.X R35, R36, R14, RZ, P0, !PT ;\n /*13e0*/ SHF.L.U64.HI R35, R34, 0x3, R35 ;\n /*13f0*/ SHF.L.U32 R34, R34, 0x3, RZ ;\n /*1400*/ IADD3 R34, P0, R9, R34, RZ ;\n /*1410*/ IADD3.X R35, R10, R35, RZ, P0, !PT ;\n /*1420*/ IADD3 R34, P0, R34, 0x8, RZ ;\n /*1430*/ IADD3.X R35, R35, RZ, RZ, P0, !PT ;\n /*1440*/ IADD3 R30, R11, 0x1, RZ ;\n /*1450*/ MOV R30, R30 ;\n /*1460*/ SHF.R.S32.HI R36, RZ, 0x1f, R30 ;\n /*1470*/ MOV R37, R36 ;\n /*1480*/ MOV R36, R30 ;\n /*1490*/ MOV R36, R36 ;\n /*14a0*/ MOV R37, R37 ;\n /*14b0*/ MOV R30, RZ ;\n /*14c0*/ MOV R31, RZ ;\n /*14d0*/ MOV R30, R30 ;\n /*14e0*/ MOV R31, R31 ;\n /*14f0*/ IMAD.WIDE.U32 R30, R0, R11, R30 ;\n /*1500*/ MOV R38, R30 ;\n /*1510*/ MOV R39, R31 ;\n /*1520*/ MOV R38, R38 ;\n /*1530*/ IMAD.WIDE.U32 R30, R2, R11, RZ ;\n /*1540*/ MOV R40, R30 ;\n /*1550*/ MOV R30, R31 ;\n /*1560*/ MOV R31, R30 ;\n /*1570*/ MOV R30, R40 ;\n /*1580*/ IMAD.WIDE.U32 R30, P0, R0, R12, R30 ;\n /*1590*/ MOV R40, R30 ;\n /*15a0*/ MOV R30, R31 ;\n /*15b0*/ IADD3 R39, P1, R40, R39, RZ ;\n /*15c0*/ IADD3 R30, RZ, R30, RZ ;\n /*15d0*/ IADD3.X R31, RZ, RZ, RZ, P0, !PT ;\n /*15e0*/ MOV R30, R30 ;\n /*15f0*/ MOV R31, R31 ;\n /*1600*/ MOV R30, R30 ;\n /*1610*/ MOV R31, R31 ;\n /*1620*/ IMAD.WIDE.U32.X R30, R2, R12, R30, P1 ;\n /*1630*/ MOV R40, R30 ;\n /*1640*/ MOV R30, R31 ;\n /*1650*/ IADD3 R38, P0, R38, R21, RZ ;\n /*1660*/ IADD3.X R39, R39, R22, RZ, P0, !PT ;\n /*1670*/ IADD3 R41, P0, R38, R19, RZ ;\n /*1680*/ IADD3.X R38, R39, R20, RZ, P0, !PT ;\n /*1690*/ MOV R30, RZ ;\n /*16a0*/ MOV R31, RZ ;\n /*16b0*/ MOV R30, R30 ;\n /*16c0*/ MOV R31, R31 ;\n /*16d0*/ IMAD.WIDE.U32 R30, R3, R41, R30 ;\n /*16e0*/ MOV R39, R30 ;\n /*16f0*/ MOV R40, R31 ;\n /*1700*/ MOV R39, R39 ;\n /*1710*/ IMAD.WIDE.U32 R30, R4, R41, RZ ;\n /*1720*/ MOV R41, R30 ;\n /*1730*/ MOV R30, R31 ;\n /*1740*/ MOV R31, R30 ;\n /*1750*/ MOV R30, R41 ;\n /*1760*/ IMAD.WIDE.U32 R30, P0, R3, R38, R30 ;\n /*1770*/ MOV R41, R30 ;\n /*1780*/ MOV R30, R31 ;\n /*1790*/ IADD3 R40, P1, R41, R40, RZ ;\n /*17a0*/ IADD3 R30, RZ, R30, RZ ;\n /*17b0*/ IADD3.X R31, RZ, RZ, RZ, P0, !PT ;\n /*17c0*/ MOV R30, R30 ;\n /*17d0*/ MOV R31, R31 ;\n /*17e0*/ MOV R30, R30 ;\n /*17f0*/ MOV R31, R31 ;\n /*1800*/ IMAD.WIDE.U32.X R30, R4, R38, R30, P1 ;\n /*1810*/ MOV R38, R30 ;\n /*1820*/ MOV R30, R31 ;\n /*1830*/ IADD3 R38, P0, R39, R13, RZ ;\n /*1840*/ IADD3.X R39, R40, R14, RZ, P0, !PT ;\n /*1850*/ SHF.L.U64.HI R39, R38, 0x3, R39 ;\n /*1860*/ SHF.L.U32 R38, R38, 0x3, RZ ;\n /*1870*/ IADD3 R38, P0, R9, R38, RZ ;\n /*1880*/ IADD3.X R39, R10, R39, RZ, P0, !PT ;\n /*1890*/ IADD3 R38, P0, R38, 0x8, RZ ;\n /*18a0*/ IADD3.X R39, R39, RZ, RZ, P0, !PT ;\n /*18b0*/ IADD3 R48, P0, R11, 0x1, RZ ;\n /*18c0*/ IADD3.X R40, R12, RZ, RZ, P0, !PT ;\n /*18d0*/ MOV R30, RZ ;\n /*18e0*/ MOV R31, RZ ;\n /*18f0*/ MOV R30, R30 ;\n /*1900*/ MOV R31, R31 ;\n /*1910*/ IMAD.WIDE.U32 R30, R0, R48, R30 ;\n /*1920*/ MOV R41, R30 ;\n /*1930*/ MOV R42, R31 ;\n /*1940*/ MOV R41, R41 ;\n /*1950*/ IMAD.WIDE.U32 R30, R2, R48, RZ ;\n /*1960*/ MOV R48, R30 ;\n /*1970*/ MOV R30, R31 ;\n /*1980*/ MOV R31, R30 ;\n /*1990*/ MOV R30, R48 ;\n /*19a0*/ IMAD.WIDE.U32 R30, P0, R0, R40, R30 ;\n /*19b0*/ MOV R48, R30 ;\n /*19c0*/ MOV R30, R31 ;\n /*19d0*/ IADD3 R42, P1, R48, R42, RZ ;\n /*19e0*/ IADD3 R30, RZ, R30, RZ ;\n /*19f0*/ IADD3.X R31, RZ, RZ, RZ, P0, !PT ;\n /*1a00*/ MOV R30, R30 ;\n /*1a10*/ MOV R31, R31 ;\n /*1a20*/ MOV R30, R30 ;\n /*1a30*/ MOV R31, R31 ;\n /*1a40*/ IMAD.WIDE.U32.X R30, R2, R40, R30, P1 ;\n /*1a50*/ MOV R40, R30 ;\n /*1a60*/ MOV R30, R31 ;\n /*1a70*/ IADD3 R41, P0, R41, R21, RZ ;\n /*1a80*/ IADD3.X R40, R42, R22, RZ, P0, !PT ;\n /*1a90*/ IADD3 R42, P0, R41, R19, RZ ;\n /*1aa0*/ IADD3.X R40, R40, R20, RZ, P0, !PT ;\n /*1ab0*/ MOV R30, RZ ;\n /*1ac0*/ MOV R31, RZ ;\n /*1ad0*/ MOV R30, R30 ;\n /*1ae0*/ MOV R31, R31 ;\n /*1af0*/ IMAD.WIDE.U32 R30, R3, R42, R30 ;\n /*1b00*/ MOV R41, R30 ;\n /*1b10*/ MOV R48, R31 ;\n /*1b20*/ MOV R41, R41 ;\n /*1b30*/ IMAD.WIDE.U32 R30, R4, R42, RZ ;\n /*1b40*/ MOV R42, R30 ;\n /*1b50*/ MOV R30, R31 ;\n /*1b60*/ MOV R31, R30 ;\n /*1b70*/ MOV R30, R42 ;\n /*1b80*/ IMAD.WIDE.U32 R30, P0, R3, R40, R30 ;\n /*1b90*/ MOV R42, R30 ;\n /*1ba0*/ MOV R30, R31 ;\n /*1bb0*/ IADD3 R48, P1, R42, R48, RZ ;\n /*1bc0*/ IADD3 R30, RZ, R30, RZ ;\n /*1bd0*/ IADD3.X R31, RZ, RZ, RZ, P0, !PT ;\n /*1be0*/ MOV R30, R30 ;\n /*1bf0*/ MOV R31, R31 ;\n /*1c00*/ MOV R30, R30 ;\n /*1c10*/ MOV R31, R31 ;\n /*1c20*/ IMAD.WIDE.U32.X R30, R4, R40, R30, P1 ;\n /*1c30*/ MOV R40, R30 ;\n /*1c40*/ MOV R30, R31 ;\n /*1c50*/ IADD3 R40, P0, R41, R13, RZ ;\n /*1c60*/ IADD3.X R41, R48, R14, RZ, P0, !PT ;\n /*1c70*/ SHF.L.U64.HI R41, R40, 0x3, R41 ;\n /*1c80*/ SHF.L.U32 R40, R40, 0x3, RZ ;\n /*1c90*/ IADD3 R40, P0, R9, R40, RZ ;\n /*1ca0*/ IADD3.X R41, R10, R41, RZ, P0, !PT ;\n /*1cb0*/ IADD3 R40, P0, R40, 0x8, RZ ;\n /*1cc0*/ IADD3.X R41, R41, RZ, RZ, P0, !PT ;\n /*1cd0*/ MOV R42, RZ ;\n /*1ce0*/ MOV R43, R43 ;\n /*1cf0*/ MOV R30, R47 ;\n /*1d00*/ MOV R31, R46 ;\n /*1d10*/ MOV R32, R32 ;\n /*1d20*/ MOV R33, R33 ;\n /*1d30*/ MOV R34, R34 ;\n /*1d40*/ MOV R35, R35 ;\n /*1d50*/ MOV R46, R36 ;\n /*1d60*/ MOV R37, R37 ;\n /*1d70*/ MOV R36, R46 ;\n /*1d80*/ MOV R37, R37 ;\n /*1d90*/ MOV R38, R38 ;\n /*1da0*/ MOV R39, R39 ;\n /*1db0*/ MOV R40, R40 ;\n /*1dc0*/ MOV R41, R41 ;\n /*1dd0*/ MOV R42, R42 ;\n.L_x_14:\n /*1de0*/ IADD3 R51, P0, R36, -0x1, RZ ;\n /*1df0*/ IADD3.X R50, R37, -0x1, RZ, P0, !PT ;\n /*1e00*/ ISETP.LT.U32.AND P0, PT, R51, R5, PT ;\n /*1e10*/ ISETP.LT.U32.AND.EX P0, PT, R50, R6, PT, P0 ;\n /*1e20*/ MOV R46, RZ ;\n /*1e30*/ MOV R47, RZ ;\n /*1e40*/ MOV R46, R46 ;\n /*1e50*/ MOV R47, R47 ;\n /*1e60*/ IMAD.WIDE.U32 R46, R23, R51, R46 ;\n /*1e70*/ MOV R49, R46 ;\n /*1e80*/ MOV R48, R47 ;\n /*1e90*/ MOV R49, R49 ;\n /*1ea0*/ IMAD.WIDE.U32 R46, R24, R51, RZ ;\n /*1eb0*/ MOV R51, R46 ;\n /*1ec0*/ MOV R46, R47 ;\n /*1ed0*/ MOV R47, R46 ;\n /*1ee0*/ MOV R46, R51 ;\n /*1ef0*/ IMAD.WIDE.U32 R46, P1, R23, R50, R46 ;\n /*1f00*/ MOV R51, R46 ;\n /*1f10*/ MOV R46, R47 ;\n /*1f20*/ IADD3 R48, P2, R51, R48, RZ ;\n /*1f30*/ IADD3 R46, RZ, R46, RZ ;\n /*1f40*/ IADD3.X R47, RZ, RZ, RZ, P1, !PT ;\n /*1f50*/ MOV R46, R46 ;\n /*1f60*/ MOV R47, R47 ;\n /*1f70*/ MOV R46, R46 ;\n /*1f80*/ MOV R47, R47 ;\n /*1f90*/ IMAD.WIDE.U32.X R46, R24, R50, R46, P2 ;\n /*1fa0*/ MOV R50, R46 ;\n /*1fb0*/ MOV R46, R47 ;\n /*1fc0*/ IADD3 R51, P1, R49, R25, RZ ;\n /*1fd0*/ IADD3.X R50, R48, R26, RZ, P1, !PT ;\n /*1fe0*/ MOV R46, RZ ;\n /*1ff0*/ MOV R47, RZ ;\n /*2000*/ MOV R46, R46 ;\n /*2010*/ MOV R47, R47 ;\n /*2020*/ IMAD.WIDE.U32 R46, R51, R0, R46 ;\n /*2030*/ MOV R49, R46 ;\n /*2040*/ MOV R48, R47 ;\n /*2050*/ MOV R49, R49 ;\n /*2060*/ IMAD.WIDE.U32 R46, R50, R0, RZ ;\n /*2070*/ MOV R52, R46 ;\n /*2080*/ MOV R46, R47 ;\n /*2090*/ MOV R47, R46 ;\n /*20a0*/ MOV R46, R52 ;\n /*20b0*/ IMAD.WIDE.U32 R46, P1, R51, R2, R46 ;\n /*20c0*/ MOV R51, R46 ;\n /*20d0*/ MOV R46, R47 ;\n /*20e0*/ IADD3 R48, P2, R51, R48, RZ ;\n /*20f0*/ IADD3 R46, RZ, R46, RZ ;\n /*2100*/ IADD3.X R47, RZ, RZ, RZ, P1, !PT ;\n /*2110*/ MOV R46, R46 ;\n /*2120*/ MOV R47, R47 ;\n /*2130*/ MOV R46, R46 ;\n /*2140*/ MOV R47, R47 ;\n /*2150*/ IMAD.WIDE.U32.X R46, R50, R2, R46, P2 ;\n /*2160*/ MOV R50, R46 ;\n /*2170*/ MOV R46, R47 ;\n /*2180*/ IADD3 R49, P1, R27, R49, RZ ;\n /*2190*/ IADD3.X R48, R28, R48, RZ, P1, !PT ;\n /*21a0*/ ISETP.LT.U32.AND P1, PT, R17, R0, PT ;\n /*21b0*/ ISETP.LT.U32.AND.EX P1, PT, R18, R2, PT, P1 ;\n /*21c0*/ PLOP3.LUT P0, PT, P1, P0, PT, 0x80, 0x0 ;\n /*21d0*/ PLOP3.LUT P2, PT, P0, PT, PT, 0x8, 0x0 ;\n /*21e0*/ MOV R50, R49 ;\n /*21f0*/ MOV R51, R48 ;\n /*2200*/ PLOP3.LUT P0, PT, P1, PT, PT, 0x80, 0x0 ;\n /*2210*/ PLOP3.LUT P1, PT, P2, PT, PT, 0x80, 0x0 ;\n /*2220*/ BSSY B0, `(.L_x_2) ;\n /*2230*/ @P2 BRA `(.L_x_3) ;\n /*2240*/ IADD3 R48, P2, R38, -0x8, RZ ;\n /*2250*/ IADD3.X R49, R39, -0x1, RZ, P2, !PT ;\n /*2260*/ MOV R48, R48 ;\n /*2270*/ MOV R49, R49 ;\n /*2280*/ MOV R48, R48 ;\n /*2290*/ MOV R49, R49 ;\n /*22a0*/ R2UR UR4, R44 ;\n /*22b0*/ R2UR UR5, R45 ;\n /*22c0*/ LDG.E.64 R48, [R48.64] ;\n /*22d0*/ SHF.L.U64.HI R47, R50, 0x3, R51 ;\n /*22e0*/ SHF.L.U32 R46, R50, 0x3, RZ ;\n /*22f0*/ IADD3 R46, P2, R7, R46, RZ ;\n /*2300*/ IADD3.X R47, R8, R47, RZ, P2, !PT ;\n /*2310*/ MOV R46, R46 ;\n /*2320*/ MOV R47, R47 ;\n /*2330*/ MOV R46, R46 ;\n /*2340*/ MOV R47, R47 ;\n /*2350*/ R2UR UR4, R44 ;\n /*2360*/ R2UR UR5, R45 ;\n /*2370*/ STG.E.64 [R46.64], R48 ;\n.L_x_3:\n /*2380*/ BSYNC B0 ;\n.L_x_2:\n /*2390*/ ISETP.GE.U32.AND P2, PT, R15, R3, PT ;\n /*23a0*/ ISETP.GE.U32.AND.EX P2, PT, R16, R4, PT, P2 ;\n /*23b0*/ PLOP3.LUT P3, PT, P2, P1, PT, 0xa8, 0x0 ;\n /*23c0*/ PLOP3.LUT P1, PT, P2, PT, PT, 0x80, 0x0 ;\n /*23d0*/ @P3 BRA `(.L_x_4) ;\n /*23e0*/ MOV R46, R38 ;\n /*23f0*/ MOV R47, R39 ;\n /*2400*/ MOV R46, R46 ;\n /*2410*/ MOV R47, R47 ;\n /*2420*/ R2UR UR4, R44 ;\n /*2430*/ R2UR UR5, R45 ;\n /*2440*/ LDG.E.64 R46, [R46.64] ;\n /*2450*/ IADD3 R48, P2, R50, R0, RZ ;\n /*2460*/ IADD3.X R49, R51, R2, RZ, P2, !PT ;\n /*2470*/ SHF.L.U64.HI R49, R48, 0x3, R49 ;\n /*2480*/ SHF.L.U32 R48, R48, 0x3, RZ ;\n /*2490*/ IADD3 R48, P2, R7, R48, RZ ;\n /*24a0*/ IADD3.X R49, R8, R49, RZ, P2, !PT ;\n /*24b0*/ MOV R48, R48 ;\n /*24c0*/ MOV R49, R49 ;\n /*24d0*/ MOV R48, R48 ;\n /*24e0*/ MOV R49, R49 ;\n /*24f0*/ R2UR UR4, R44 ;\n /*2500*/ R2UR UR5, R45 ;\n /*2510*/ STG.E.64 [R48.64], R46 ;\n.L_x_4:\n /*2520*/ WARPSYNC 0xffffffff ;\n /*2530*/ BAR.SYNC.DEFER_BLOCKING 0x0 ;\n /*2540*/ MOV R46, RZ ;\n /*2550*/ MOV R47, RZ ;\n /*2560*/ MOV R46, R46 ;\n /*2570*/ MOV R47, R47 ;\n /*2580*/ IMAD.WIDE.U32 R46, R23, R36, R46 ;\n /*2590*/ MOV R51, R46 ;\n /*25a0*/ MOV R48, R47 ;\n /*25b0*/ MOV R51, R51 ;\n /*25c0*/ IMAD.WIDE.U32 R46, R24, R36, RZ ;\n /*25d0*/ MOV R49, R46 ;\n /*25e0*/ MOV R46, R47 ;\n /*25f0*/ MOV R47, R46 ;\n /*2600*/ MOV R46, R49 ;\n /*2610*/ IMAD.WIDE.U32 R46, P2, R23, R37, R46 ;\n /*2620*/ MOV R49, R46 ;\n /*2630*/ MOV R46, R47 ;\n /*2640*/ IADD3 R48, P3, R49, R48, RZ ;\n /*2650*/ IADD3 R46, RZ, R46, RZ ;\n /*2660*/ IADD3.X R47, RZ, RZ, RZ, P2, !PT ;\n /*2670*/ MOV R46, R46 ;\n /*2680*/ MOV R47, R47 ;\n /*2690*/ MOV R46, R46 ;\n /*26a0*/ MOV R47, R47 ;\n /*26b0*/ IMAD.WIDE.U32.X R46, R24, R37, R46, P3 ;\n /*26c0*/ MOV R49, R46 ;\n /*26d0*/ MOV R46, R47 ;\n /*26e0*/ IADD3 R51, P2, R51, R25, RZ ;\n /*26f0*/ IADD3.X R50, R48, R26, RZ, P2, !PT ;\n /*2700*/ MOV R46, RZ ;\n /*2710*/ MOV R47, RZ ;\n /*2720*/ MOV R46, R46 ;\n /*2730*/ MOV R47, R47 ;\n /*2740*/ IMAD.WIDE.U32 R46, R51, R0, R46 ;\n /*2750*/ MOV R49, R46 ;\n /*2760*/ MOV R48, R47 ;\n /*2770*/ MOV R49, R49 ;\n /*2780*/ IMAD.WIDE.U32 R46, R50, R0, RZ ;\n /*2790*/ MOV R52, R46 ;\n /*27a0*/ MOV R46, R47 ;\n /*27b0*/ MOV R47, R46 ;\n /*27c0*/ MOV R46, R52 ;\n /*27d0*/ IMAD.WIDE.U32 R46, P2, R51, R2, R46 ;\n /*27e0*/ MOV R51, R46 ;\n /*27f0*/ MOV R46, R47 ;\n /*2800*/ IADD3 R48, P3, R51, R48, RZ ;\n /*2810*/ IADD3 R46, RZ, R46, RZ ;\n /*2820*/ IADD3.X R47, RZ, RZ, RZ, P2, !PT ;\n /*2830*/ MOV R46, R46 ;\n /*2840*/ MOV R47, R47 ;\n /*2850*/ MOV R46, R46 ;\n /*2860*/ MOV R47, R47 ;\n /*2870*/ IMAD.WIDE.U32.X R46, R50, R2, R46, P3 ;\n /*2880*/ MOV R50, R46 ;\n /*2890*/ MOV R46, R47 ;\n /*28a0*/ IADD3 R49, P2, R27, R49, RZ ;\n /*28b0*/ IADD3.X R48, R28, R48, RZ, P2, !PT ;\n /*28c0*/ ISETP.LT.U32.AND P2, PT, R36, R5, PT ;\n /*28d0*/ ISETP.LT.U32.AND.EX P2, PT, R37, R6, PT, P2 ;\n /*28e0*/ PLOP3.LUT P2, PT, P0, P2, PT, 0x80, 0x0 ;\n /*28f0*/ IADD3 R52, P3, R40, -0x8, RZ ;\n /*2900*/ IADD3.X R53, R41, -0x1, RZ, P3, !PT ;\n /*2910*/ PLOP3.LUT P2, PT, P2, PT, PT, 0x8, 0x0 ;\n /*2920*/ MOV R50, R49 ;\n /*2930*/ MOV R51, R48 ;\n /*2940*/ MOV R52, R52 ;\n /*2950*/ MOV R53, R53 ;\n /*2960*/ PLOP3.LUT P2, PT, P2, PT, PT, 0x80, 0x0 ;\n /*2970*/ BSSY B0, `(.L_x_5) ;\n /*2980*/ @P2 BRA `(.L_x_6) ;\n /*2990*/ MOV R48, R52 ;\n /*29a0*/ MOV R49, R53 ;\n /*29b0*/ MOV R48, R48 ;\n /*29c0*/ MOV R49, R49 ;\n /*29d0*/ R2UR UR4, R44 ;\n /*29e0*/ R2UR UR5, R45 ;\n /*29f0*/ LDG.E.64 R48, [R48.64] ;\n /*2a00*/ SHF.L.U64.HI R46, R50, 0x3, R51 ;\n /*2a10*/ SHF.L.U32 R47, R50, 0x3, RZ ;\n /*2a20*/ IADD3 R47, P3, R7, R47, RZ ;\n /*2a30*/ IADD3.X R46, R8, R46, RZ, P3, !PT ;\n /*2a40*/ MOV R47, R47 ;\n /*2a50*/ MOV R46, R46 ;\n /*2a60*/ LOP3.LUT R47, R47, R46, RZ, 0x3c, !PT ;\n /*2a70*/ LOP3.LUT R46, R47, R46, RZ, 0x3c, !PT ;\n /*2a80*/ LOP3.LUT R47, R47, R46, RZ, 0x3c, !PT ;\n /*2a90*/ R2UR UR4, R44 ;\n /*2aa0*/ R2UR UR5, R45 ;\n /*2ab0*/ STG.E.64 [R46.64], R48 ;\n.L_x_6:\n /*2ac0*/ BSYNC B0 ;\n.L_x_5:\n /*2ad0*/ PLOP3.LUT P2, PT, P1, P2, PT, 0xa8, 0x0 ;\n /*2ae0*/ @P2 BRA `(.L_x_7) ;\n /*2af0*/ IADD3 R46, P2, R52, 0x8, RZ ;\n /*2b00*/ IADD3.X R47, R53, RZ, RZ, P2, !PT ;\n /*2b10*/ MOV R46, R46 ;\n /*2b20*/ MOV R47, R47 ;\n /*2b30*/ MOV R46, R46 ;\n /*2b40*/ MOV R47, R47 ;\n /*2b50*/ R2UR UR4, R44 ;\n /*2b60*/ R2UR UR5, R45 ;\n /*2b70*/ LDG.E.64 R46, [R46.64] ;\n /*2b80*/ IADD3 R48, P2, R50, R0, RZ ;\n /*2b90*/ IADD3.X R49, R51, R2, RZ, P2, !PT ;\n /*2ba0*/ SHF.L.U64.HI R49, R48, 0x3, R49 ;\n /*2bb0*/ SHF.L.U32 R48, R48, 0x3, RZ ;\n /*2bc0*/ IADD3 R48, P2, R7, R48, RZ ;\n /*2bd0*/ IADD3.X R49, R8, R49, RZ, P2, !PT ;\n /*2be0*/ MOV R48, R48 ;\n /*2bf0*/ MOV R49, R49 ;\n /*2c00*/ MOV R48, R48 ;\n /*2c10*/ MOV R49, R49 ;\n /*2c20*/ R2UR UR4, R44 ;\n /*2c30*/ R2UR UR5, R45 ;\n /*2c40*/ STG.E.64 [R48.64], R46 ;\n.L_x_7:\n /*2c50*/ WARPSYNC 0xffffffff ;\n /*2c60*/ BAR.SYNC.DEFER_BLOCKING 0x0 ;\n /*2c70*/ IADD3 R51, P2, R36, 0x1, RZ ;\n /*2c80*/ IADD3.X R50, R37, RZ, RZ, P2, !PT ;\n /*2c90*/ ISETP.LT.U32.AND P2, PT, R51, R5, PT ;\n /*2ca0*/ ISETP.LT.U32.AND.EX P2, PT, R50, R6, PT, P2 ;\n /*2cb0*/ MOV R46, RZ ;\n /*2cc0*/ MOV R47, RZ ;\n /*2cd0*/ MOV R46, R46 ;\n /*2ce0*/ MOV R47, R47 ;\n /*2cf0*/ IMAD.WIDE.U32 R46, R23, R51, R46 ;\n /*2d00*/ MOV R49, R46 ;\n /*2d10*/ MOV R48, R47 ;\n /*2d20*/ MOV R49, R49 ;\n /*2d30*/ IMAD.WIDE.U32 R46, R24, R51, RZ ;\n /*2d40*/ MOV R51, R46 ;\n /*2d50*/ MOV R46, R47 ;\n /*2d60*/ MOV R47, R46 ;\n /*2d70*/ MOV R46, R51 ;\n /*2d80*/ IMAD.WIDE.U32 R46, P3, R23, R50, R46 ;\n /*2d90*/ MOV R51, R46 ;\n /*2da0*/ MOV R46, R47 ;\n /*2db0*/ IADD3 R48, P4, R51, R48, RZ ;\n /*2dc0*/ IADD3 R46, RZ, R46, RZ ;\n /*2dd0*/ IADD3.X R47, RZ, RZ, RZ, P3, !PT ;\n /*2de0*/ MOV R46, R46 ;\n /*2df0*/ MOV R47, R47 ;\n /*2e00*/ MOV R46, R46 ;\n /*2e10*/ MOV R47, R47 ;\n /*2e20*/ IMAD.WIDE.U32.X R46, R24, R50, R46, P4 ;\n /*2e30*/ MOV R50, R46 ;\n /*2e40*/ MOV R46, R47 ;\n /*2e50*/ IADD3 R51, P3, R49, R25, RZ ;\n /*2e60*/ IADD3.X R50, R48, R26, RZ, P3, !PT ;\n /*2e70*/ MOV R46, RZ ;\n /*2e80*/ MOV R47, RZ ;\n /*2e90*/ MOV R46, R46 ;\n /*2ea0*/ MOV R47, R47 ;\n /*2eb0*/ IMAD.WIDE.U32 R46, R51, R0, R46 ;\n /*2ec0*/ MOV R49, R46 ;\n /*2ed0*/ MOV R48, R47 ;\n /*2ee0*/ MOV R49, R49 ;\n /*2ef0*/ IMAD.WIDE.U32 R46, R50, R0, RZ ;\n /*2f00*/ MOV R52, R46 ;\n /*2f10*/ MOV R46, R47 ;\n /*2f20*/ MOV R47, R46 ;\n /*2f30*/ MOV R46, R52 ;\n /*2f40*/ IMAD.WIDE.U32 R46, P3, R51, R2, R46 ;\n /*2f50*/ MOV R51, R46 ;\n /*2f60*/ MOV R46, R47 ;\n /*2f70*/ IADD3 R48, P4, R51, R48, RZ ;\n /*2f80*/ IADD3 R46, RZ, R46, RZ ;\n /*2f90*/ IADD3.X R47, RZ, RZ, RZ, P3, !PT ;\n /*2fa0*/ MOV R46, R46 ;\n /*2fb0*/ MOV R47, R47 ;\n /*2fc0*/ MOV R46, R46 ;\n /*2fd0*/ MOV R47, R47 ;\n /*2fe0*/ IMAD.WIDE.U32.X R46, R50, R2, R46, P4 ;\n /*2ff0*/ MOV R50, R46 ;\n /*3000*/ MOV R46, R47 ;\n /*3010*/ IADD3 R49, P3, R27, R49, RZ ;\n /*3020*/ IADD3.X R48, R28, R48, RZ, P3, !PT ;\n /*3030*/ PLOP3.LUT P2, PT, P0, P2, PT, 0x80, 0x0 ;\n /*3040*/ IADD3 R52, P3, R34, -0x8, RZ ;\n /*3050*/ IADD3.X R53, R35, -0x1, RZ, P3, !PT ;\n /*3060*/ PLOP3.LUT P2, PT, P2, PT, PT, 0x8, 0x0 ;\n /*3070*/ MOV R50, R49 ;\n /*3080*/ MOV R51, R48 ;\n /*3090*/ MOV R52, R52 ;\n /*30a0*/ MOV R53, R53 ;\n /*30b0*/ PLOP3.LUT P2, PT, P2, PT, PT, 0x80, 0x0 ;\n /*30c0*/ BSSY B0, `(.L_x_8) ;\n /*30d0*/ @P2 BRA `(.L_x_9) ;\n /*30e0*/ MOV R48, R52 ;\n /*30f0*/ MOV R49, R53 ;\n /*3100*/ MOV R48, R48 ;\n /*3110*/ MOV R49, R49 ;\n /*3120*/ R2UR UR4, R44 ;\n /*3130*/ R2UR UR5, R45 ;\n /*3140*/ LDG.E.64 R48, [R48.64] ;\n /*3150*/ SHF.L.U64.HI R46, R50, 0x3, R51 ;\n /*3160*/ SHF.L.U32 R47, R50, 0x3, RZ ;\n /*3170*/ IADD3 R47, P3, R7, R47, RZ ;\n /*3180*/ IADD3.X R46, R8, R46, RZ, P3, !PT ;\n /*3190*/ MOV R47, R47 ;\n /*31a0*/ MOV R46, R46 ;\n /*31b0*/ LOP3.LUT R47, R47, R46, RZ, 0x3c, !PT ;\n /*31c0*/ LOP3.LUT R46, R47, R46, RZ, 0x3c, !PT ;\n /*31d0*/ LOP3.LUT R47, R47, R46, RZ, 0x3c, !PT ;\n /*31e0*/ R2UR UR4, R44 ;\n /*31f0*/ R2UR UR5, R45 ;\n /*3200*/ STG.E.64 [R46.64], R48 ;\n.L_x_9:\n /*3210*/ BSYNC B0 ;\n.L_x_8:\n /*3220*/ PLOP3.LUT P2, PT, P1, P2, PT, 0xa8, 0x0 ;\n /*3230*/ @P2 BRA `(.L_x_10) ;\n /*3240*/ IADD3 R46, P2, R52, 0x8, RZ ;\n /*3250*/ IADD3.X R47, R53, RZ, RZ, P2, !PT ;\n /*3260*/ MOV R46, R46 ;\n /*3270*/ MOV R47, R47 ;\n /*3280*/ MOV R46, R46 ;\n /*3290*/ MOV R47, R47 ;\n /*32a0*/ R2UR UR4, R44 ;\n /*32b0*/ R2UR UR5, R45 ;\n /*32c0*/ LDG.E.64 R46, [R46.64] ;\n /*32d0*/ IADD3 R48, P2, R50, R0, RZ ;\n /*32e0*/ IADD3.X R49, R51, R2, RZ, P2, !PT ;\n /*32f0*/ SHF.L.U64.HI R49, R48, 0x3, R49 ;\n /*3300*/ SHF.L.U32 R48, R48, 0x3, RZ ;\n /*3310*/ IADD3 R48, P2, R7, R48, RZ ;\n /*3320*/ IADD3.X R49, R8, R49, RZ, P2, !PT ;\n /*3330*/ MOV R48, R48 ;\n /*3340*/ MOV R49, R49 ;\n /*3350*/ MOV R48, R48 ;\n /*3360*/ MOV R49, R49 ;\n /*3370*/ R2UR UR4, R44 ;\n /*3380*/ R2UR UR5, R45 ;\n /*3390*/ STG.E.64 [R48.64], R46 ;\n.L_x_10:\n /*33a0*/ WARPSYNC 0xffffffff ;\n /*33b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ;\n /*33c0*/ IADD3 R51, P2, R36, 0x2, RZ ;\n /*33d0*/ IADD3.X R50, R37, RZ, RZ, P2, !PT ;\n /*33e0*/ ISETP.LT.U32.AND P2, PT, R51, R5, PT ;\n /*33f0*/ ISETP.LT.U32.AND.EX P2, PT, R50, R6, PT, P2 ;\n /*3400*/ MOV R46, RZ ;\n /*3410*/ MOV R47, RZ ;\n /*3420*/ MOV R46, R46 ;\n /*3430*/ MOV R47, R47 ;\n /*3440*/ IMAD.WIDE.U32 R46, R23, R51, R46 ;\n /*3450*/ MOV R49, R46 ;\n /*3460*/ MOV R48, R47 ;\n /*3470*/ MOV R49, R49 ;\n /*3480*/ IMAD.WIDE.U32 R46, R24, R51, RZ ;\n /*3490*/ MOV R51, R46 ;\n /*34a0*/ MOV R46, R47 ;\n /*34b0*/ MOV R47, R46 ;\n /*34c0*/ MOV R46, R51 ;\n /*34d0*/ IMAD.WIDE.U32 R46, P3, R23, R50, R46 ;\n /*34e0*/ MOV R51, R46 ;\n /*34f0*/ MOV R46, R47 ;\n /*3500*/ IADD3 R48, P4, R51, R48, RZ ;\n /*3510*/ IADD3 R46, RZ, R46, RZ ;\n /*3520*/ IADD3.X R47, RZ, RZ, RZ, P3, !PT ;\n /*3530*/ MOV R46, R46 ;\n /*3540*/ MOV R47, R47 ;\n /*3550*/ MOV R46, R46 ;\n /*3560*/ MOV R47, R47 ;\n /*3570*/ IMAD.WIDE.U32.X R46, R24, R50, R46, P4 ;\n /*3580*/ MOV R50, R46 ;\n /*3590*/ MOV R46, R47 ;\n /*35a0*/ IADD3 R51, P3, R49, R25, RZ ;\n /*35b0*/ IADD3.X R50, R48, R26, RZ, P3, !PT ;\n /*35c0*/ MOV R46, RZ ;\n /*35d0*/ MOV R47, RZ ;\n /*35e0*/ MOV R46, R46 ;\n /*35f0*/ MOV R47, R47 ;\n /*3600*/ IMAD.WIDE.U32 R46, R51, R0, R46 ;\n /*3610*/ MOV R49, R46 ;\n /*3620*/ MOV R48, R47 ;\n /*3630*/ MOV R49, R49 ;\n /*3640*/ IMAD.WIDE.U32 R46, R50, R0, RZ ;\n /*3650*/ MOV R52, R46 ;\n /*3660*/ MOV R46, R47 ;\n /*3670*/ MOV R47, R46 ;\n /*3680*/ MOV R46, R52 ;\n /*3690*/ IMAD.WIDE.U32 R46, P3, R51, R2, R46 ;\n /*36a0*/ MOV R51, R46 ;\n /*36b0*/ MOV R46, R47 ;\n /*36c0*/ IADD3 R48, P4, R51, R48, RZ ;\n /*36d0*/ IADD3 R46, RZ, R46, RZ ;\n /*36e0*/ IADD3.X R47, RZ, RZ, RZ, P3, !PT ;\n /*36f0*/ MOV R46, R46 ;\n /*3700*/ MOV R47, R47 ;\n /*3710*/ MOV R46, R46 ;\n /*3720*/ MOV R47, R47 ;\n /*3730*/ IMAD.WIDE.U32.X R46, R50, R2, R46, P4 ;\n /*3740*/ MOV R50, R46 ;\n /*3750*/ MOV R46, R47 ;\n /*3760*/ IADD3 R49, P3, R27, R49, RZ ;\n /*3770*/ IADD3.X R48, R28, R48, RZ, P3, !PT ;\n /*3780*/ PLOP3.LUT P2, PT, P0, P2, PT, 0x80, 0x0 ;\n /*3790*/ IADD3 R52, P0, R30, -0x8, RZ ;\n /*37a0*/ IADD3.X R53, R31, -0x1, RZ, P0, !PT ;\n /*37b0*/ PLOP3.LUT P2, PT, P2, PT, PT, 0x8, 0x0 ;\n /*37c0*/ MOV R50, R49 ;\n /*37d0*/ MOV R51, R48 ;\n /*37e0*/ MOV R52, R52 ;\n /*37f0*/ MOV R53, R53 ;\n /*3800*/ PLOP3.LUT P0, PT, P2, PT, PT, 0x80, 0x0 ;\n /*3810*/ BSSY B0, `(.L_x_11) ;\n /*3820*/ @P2 BRA `(.L_x_12) ;\n /*3830*/ MOV R48, R52 ;\n /*3840*/ MOV R49, R53 ;\n /*3850*/ MOV R48, R48 ;\n /*3860*/ MOV R49, R49 ;\n /*3870*/ R2UR UR4, R44 ;\n /*3880*/ R2UR UR5, R45 ;\n /*3890*/ LDG.E.64 R48, [R48.64] ;\n /*38a0*/ SHF.L.U64.HI R46, R50, 0x3, R51 ;\n /*38b0*/ SHF.L.U32 R47, R50, 0x3, RZ ;\n /*38c0*/ IADD3 R47, P2, R7, R47, RZ ;\n /*38d0*/ IADD3.X R46, R8, R46, RZ, P2, !PT ;\n /*38e0*/ MOV R47, R47 ;\n /*38f0*/ MOV R46, R46 ;\n /*3900*/ LOP3.LUT R47, R47, R46, RZ, 0x3c, !PT ;\n /*3910*/ LOP3.LUT R46, R47, R46, RZ, 0x3c, !PT ;\n /*3920*/ LOP3.LUT R47, R47, R46, RZ, 0x3c, !PT ;\n /*3930*/ R2UR UR4, R44 ;\n /*3940*/ R2UR UR5, R45 ;\n /*3950*/ STG.E.64 [R46.64], R48 ;\n.L_x_12:\n /*3960*/ BSYNC B0 ;\n.L_x_11:\n /*3970*/ PLOP3.LUT P0, PT, P1, P0, PT, 0xa8, 0x0 ;\n /*3980*/ @P0 BRA `(.L_x_13) ;\n /*3990*/ IADD3 R46, P0, R52, 0x8, RZ ;\n /*39a0*/ IADD3.X R47, R53, RZ, RZ, P0, !PT ;\n /*39b0*/ MOV R46, R46 ;\n /*39c0*/ MOV R47, R47 ;\n /*39d0*/ MOV R46, R46 ;\n /*39e0*/ MOV R47, R47 ;\n /*39f0*/ R2UR UR4, R44 ;\n /*3a00*/ R2UR UR5, R45 ;\n /*3a10*/ LDG.E.64 R46, [R46.64] ;\n /*3a20*/ IADD3 R48, P0, R50, R0, RZ ;\n /*3a30*/ IADD3.X R49, R51, R2, RZ, P0, !PT ;\n /*3a40*/ SHF.L.U64.HI R49, R48, 0x3, R49 ;\n /*3a50*/ SHF.L.U32 R48, R48, 0x3, RZ ;\n /*3a60*/ IADD3 R48, P0, R7, R48, RZ ;\n /*3a70*/ IADD3.X R49, R8, R49, RZ, P0, !PT ;\n /*3a80*/ MOV R48, R48 ;\n /*3a90*/ MOV R49, R49 ;\n /*3aa0*/ MOV R48, R48 ;\n /*3ab0*/ MOV R49, R49 ;\n /*3ac0*/ R2UR UR4, R44 ;\n /*3ad0*/ R2UR UR5, R45 ;\n /*3ae0*/ STG.E.64 [R48.64], R46 ;\n.L_x_13:\n /*3af0*/ WARPSYNC 0xffffffff ;\n /*3b00*/ BAR.SYNC.DEFER_BLOCKING 0x0 ;\n /*3b10*/ IADD3 R42, R42, 0x4, RZ ;\n /*3b20*/ IADD3 R30, P0, R30, R32, RZ ;\n /*3b30*/ IADD3.X R31, R31, R33, RZ, P0, !PT ;\n /*3b40*/ IADD3 R34, P0, R34, R32, RZ ;\n /*3b50*/ IADD3.X R35, R35, R33, RZ, P0, !PT ;\n /*3b60*/ IADD3 R36, P0, R36, 0x4, RZ ;\n /*3b70*/ IADD3.X R37, R37, RZ, RZ, P0, !PT ;\n /*3b80*/ IADD3 R38, P0, R38, R32, RZ ;\n /*3b90*/ IADD3.X R39, R39, R33, RZ, P0, !PT ;\n /*3ba0*/ IADD3 R40, P0, R40, R32, RZ ;\n /*3bb0*/ IADD3.X R41, R41, R33, RZ, P0, !PT ;\n /*3bc0*/ IADD3 R43, R43, -0x4, RZ ;\n /*3bd0*/ ISETP.NE.AND P0, PT, R43, RZ, PT ;\n /*3be0*/ MOV R42, R42 ;\n /*3bf0*/ MOV R30, R30 ;\n /*3c00*/ MOV R31, R31 ;\n /*3c10*/ MOV R34, R34 ;\n /*3c20*/ MOV R35, R35 ;\n /*3c30*/ MOV R36, R36 ;\n /*3c40*/ MOV R37, R37 ;\n /*3c50*/ MOV R38, R38 ;\n /*3c60*/ MOV R39, R39 ;\n /*3c70*/ MOV R40, R40 ;\n /*3c80*/ MOV R41, R41 ;\n /*3c90*/ MOV R43, R43 ;\n /*3ca0*/ @P0 BRA `(.L_x_14) ;\n.L_x_1:\n /*3cb0*/ ISETP.EQ.AND P0, PT, R29, RZ, PT ;\n /*3cc0*/ IADD3 R19, P1, R19, R21, RZ ;\n /*3cd0*/ IADD3.X R20, R20, R22, RZ, P1, !PT ;\n /*3ce0*/ MOV R22, R19 ;\n /*3cf0*/ MOV R19, R20 ;\n /*3d00*/ @P0 BRA `(.L_x_0) ;\n /*3d10*/ MOV R11, R11 ;\n /*3d20*/ MOV R20, R42 ;\n /*3d30*/ SHF.R.S32.HI R21, RZ, 0x1f, R20 ;\n /*3d40*/ MOV R20, R20 ;\n /*3d50*/ MOV R21, R21 ;\n /*3d60*/ MOV R30, R20 ;\n /*3d70*/ MOV R20, R21 ;\n /*3d80*/ MOV R30, R30 ;\n /*3d90*/ MOV R20, R20 ;\n /*3da0*/ IADD3 R30, P0, R30, R11, RZ ;\n /*3db0*/ IADD3.X R12, R20, R12, RZ, P0, !PT ;\n /*3dc0*/ IADD3 R11, R42, R11, RZ ;\n /*3dd0*/ MOV R11, R11 ;\n /*3de0*/ SHF.R.S32.HI R20, RZ, 0x1f, R11 ;\n /*3df0*/ MOV R21, R20 ;\n /*3e00*/ MOV R20, R11 ;\n /*3e10*/ MOV R20, R20 ;\n /*3e20*/ MOV R21, R21 ;\n /*3e30*/ MOV R11, R30 ;\n /*3e40*/ MOV R12, R12 ;\n /*3e50*/ MOV R30, R20 ;\n /*3e60*/ MOV R20, R21 ;\n /*3e70*/ MOV R30, R30 ;\n /*3e80*/ MOV R31, R20 ;\n.L_x_18:\n /*3e90*/ MOV R20, RZ ;\n /*3ea0*/ MOV R21, RZ ;\n /*3eb0*/ MOV R20, R20 ;\n /*3ec0*/ MOV R21, R21 ;\n /*3ed0*/ IMAD.WIDE.U32 R20, R11, R0, R20 ;\n /*3ee0*/ MOV R32, R20 ;\n /*3ef0*/ MOV R33, R21 ;\n /*3f00*/ MOV R32, R32 ;\n /*3f10*/ IMAD.WIDE.U32 R20, R12, R0, RZ ;\n /*3f20*/ MOV R34, R20 ;\n /*3f30*/ MOV R20, R21 ;\n /*3f40*/ MOV R21, R20 ;\n /*3f50*/ MOV R20, R34 ;\n /*3f60*/ IMAD.WIDE.U32 R20, P0, R11, R2, R20 ;\n /*3f70*/ MOV R34, R20 ;\n /*3f80*/ MOV R20, R21 ;\n /*3f90*/ IADD3 R33, P1, R34, R33, RZ ;\n /*3fa0*/ IADD3 R20, RZ, R20, RZ ;\n /*3fb0*/ IADD3.X R21, RZ, RZ, RZ, P0, !PT ;\n /*3fc0*/ MOV R20, R20 ;\n /*3fd0*/ MOV R21, R21 ;\n /*3fe0*/ MOV R20, R20 ;\n /*3ff0*/ MOV R21, R21 ;\n /*4000*/ IMAD.WIDE.U32.X R20, R12, R2, R20, P1 ;\n /*4010*/ MOV R34, R20 ;\n /*4020*/ MOV R20, R21 ;\n /*4030*/ IADD3 R34, P0, R22, R32, RZ ;\n /*4040*/ IADD3.X R32, R19, R33, RZ, P0, !PT ;\n /*4050*/ MOV R20, RZ ;\n /*4060*/ MOV R21, RZ ;\n /*4070*/ MOV R20, R20 ;\n /*4080*/ MOV R21, R21 ;\n /*4090*/ IMAD.WIDE.U32 R20, R34, R3, R20 ;\n /*40a0*/ MOV R33, R20 ;\n /*40b0*/ MOV R35, R21 ;\n /*40c0*/ MOV R33, R33 ;\n /*40d0*/ IMAD.WIDE.U32 R20, R32, R3, RZ ;\n /*40e0*/ MOV R36, R20 ;\n /*40f0*/ MOV R20, R21 ;\n /*4100*/ MOV R21, R20 ;\n /*4110*/ MOV R20, R36 ;\n /*4120*/ IMAD.WIDE.U32 R20, P0, R34, R4, R20 ;\n /*4130*/ MOV R34, R20 ;\n /*4140*/ MOV R20, R21 ;\n /*4150*/ IADD3 R34, P1, R34, R35, RZ ;\n /*4160*/ IADD3 R20, RZ, R20, RZ ;\n /*4170*/ IADD3.X R21, RZ, RZ, RZ, P0, !PT ;\n /*4180*/ MOV R20, R20 ;\n /*4190*/ MOV R21, R21 ;\n /*41a0*/ MOV R20, R20 ;\n /*41b0*/ MOV R21, R21 ;\n /*41c0*/ IMAD.WIDE.U32.X R20, R32, R4, R20, P1 ;\n /*41d0*/ MOV R32, R20 ;\n /*41e0*/ MOV R20, R21 ;\n /*41f0*/ IADD3 R33, P0, R33, R13, RZ ;\n /*4200*/ IADD3.X R32, R34, R14, RZ, P0, !PT ;\n /*4210*/ MOV R20, RZ ;\n /*4220*/ MOV R21, RZ ;\n /*4230*/ MOV R20, R20 ;\n /*4240*/ MOV R21, R21 ;\n /*4250*/ IMAD.WIDE.U32 R20, R23, R30, R20 ;\n /*4260*/ MOV R34, R20 ;\n /*4270*/ MOV R35, R21 ;\n /*4280*/ MOV R34, R34 ;\n /*4290*/ IMAD.WIDE.U32 R20, R24, R30, RZ ;\n /*42a0*/ MOV R36, R20 ;\n /*42b0*/ MOV R20, R21 ;\n /*42c0*/ MOV R21, R20 ;\n /*42d0*/ MOV R20, R36 ;\n /*42e0*/ IMAD.WIDE.U32 R20, P0, R23, R31, R20 ;\n /*42f0*/ MOV R36, R20 ;\n /*4300*/ MOV R20, R21 ;\n /*4310*/ IADD3 R35, P1, R36, R35, RZ ;\n /*4320*/ IADD3 R20, RZ, R20, RZ ;\n /*4330*/ IADD3.X R21, RZ, RZ, RZ, P0, !PT ;\n /*4340*/ MOV R20, R20 ;\n /*4350*/ MOV R21, R21 ;\n /*4360*/ MOV R20, R20 ;\n /*4370*/ MOV R21, R21 ;\n /*4380*/ IMAD.WIDE.U32.X R20, R24, R31, R20, P1 ;\n /*4390*/ MOV R36, R20 ;\n /*43a0*/ MOV R20, R21 ;\n /*43b0*/ IADD3 R36, P0, R34, R25, RZ ;\n /*43c0*/ IADD3.X R34, R35, R26, RZ, P0, !PT ;\n /*43d0*/ MOV R20, RZ ;\n /*43e0*/ MOV R21, RZ ;\n /*43f0*/ MOV R20, R20 ;\n /*4400*/ MOV R21, R21 ;\n /*4410*/ IMAD.WIDE.U32 R20, R36, R0, R20 ;\n /*4420*/ MOV R35, R20 ;\n /*4430*/ MOV R37, R21 ;\n /*4440*/ MOV R35, R35 ;\n /*4450*/ IMAD.WIDE.U32 R20, R34, R0, RZ ;\n /*4460*/ MOV R38, R20 ;\n /*4470*/ MOV R20, R21 ;\n /*4480*/ MOV R21, R20 ;\n /*4490*/ MOV R20, R38 ;\n /*44a0*/ IMAD.WIDE.U32 R20, P0, R36, R2, R20 ;\n /*44b0*/ MOV R36, R20 ;\n /*44c0*/ MOV R20, R21 ;\n /*44d0*/ IADD3 R36, P1, R36, R37, RZ ;\n /*44e0*/ IADD3 R20, RZ, R20, RZ ;\n /*44f0*/ IADD3.X R21, RZ, RZ, RZ, P0, !PT ;\n /*4500*/ MOV R20, R20 ;\n /*4510*/ MOV R21, R21 ;\n /*4520*/ MOV R20, R20 ;\n /*4530*/ MOV R21, R21 ;\n /*4540*/ IMAD.WIDE.U32.X R20, R34, R2, R20, P1 ;\n /*4550*/ MOV R34, R20 ;\n /*4560*/ MOV R20, R21 ;\n /*4570*/ IADD3 R35, P0, R27, R35, RZ ;\n /*4580*/ IADD3.X R34, R28, R36, RZ, P0, !PT ;\n /*4590*/ ISETP.LT.U32.AND P0, PT, R30, R5, PT ;\n /*45a0*/ ISETP.LT.U32.AND.EX P0, PT, R31, R6, PT, P0 ;\n /*45b0*/ ISETP.LT.U32.AND P1, PT, R17, R0, PT ;\n /*45c0*/ ISETP.LT.U32.AND.EX P1, PT, R18, R2, PT, P1 ;\n /*45d0*/ PLOP3.LUT P0, PT, P1, P0, PT, 0x80, 0x0 ;\n /*45e0*/ SHF.L.U64.HI R32, R33, 0x3, R32 ;\n /*45f0*/ SHF.L.U32 R36, R33, 0x3, RZ ;\n /*4600*/ IADD3 R36, P1, R9, R36, RZ ;\n /*4610*/ IADD3.X R37, R10, R32, RZ, P1, !PT ;\n /*4620*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ;\n /*4630*/ MOV R35, R35 ;\n /*4640*/ MOV R34, R34 ;\n /*4650*/ MOV R36, R36 ;\n /*4660*/ MOV R37, R37 ;\n /*4670*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x80, 0x0 ;\n /*4680*/ BSSY B0, `(.L_x_15) ;\n /*4690*/ @P0 BRA `(.L_x_16) ;\n /*46a0*/ MOV R32, R36 ;\n /*46b0*/ MOV R33, R37 ;\n /*46c0*/ MOV R32, R32 ;\n /*46d0*/ MOV R33, R33 ;\n /*46e0*/ R2UR UR4, R44 ;\n /*46f0*/ R2UR UR5, R45 ;\n /*4700*/ LDG.E.64 R32, [R32.64] ;\n /*4710*/ SHF.L.U64.HI R21, R35, 0x3, R34 ;\n /*4720*/ SHF.L.U32 R20, R35, 0x3, RZ ;\n /*4730*/ IADD3 R20, P1, R7, R20, RZ ;\n /*4740*/ IADD3.X R21, R8, R21, RZ, P1, !PT ;\n /*4750*/ MOV R20, R20 ;\n /*4760*/ MOV R21, R21 ;\n /*4770*/ MOV R20, R20 ;\n /*4780*/ MOV R21, R21 ;\n /*4790*/ R2UR UR4, R44 ;\n /*47a0*/ R2UR UR5, R45 ;\n /*47b0*/ STG.E.64 [R20.64], R32 ;\n.L_x_16:\n /*47c0*/ BSYNC B0 ;\n.L_x_15:\n /*47d0*/ ISETP.GE.U32.AND P1, PT, R15, R3, PT ;\n /*47e0*/ ISETP.GE.U32.AND.EX P1, PT, R16, R4, PT, P1 ;\n /*47f0*/ PLOP3.LUT P0, PT, P1, P0, PT, 0xa8, 0x0 ;\n /*4800*/ @P0 BRA `(.L_x_17) ;\n /*4810*/ IADD3 R32, P0, R36, 0x8, RZ ;\n /*4820*/ IADD3.X R33, R37, RZ, RZ, P0, !PT ;\n /*4830*/ MOV R32, R32 ;\n /*4840*/ MOV R33, R33 ;\n /*4850*/ MOV R32, R32 ;\n /*4860*/ MOV R33, R33 ;\n /*4870*/ R2UR UR4, R44 ;\n /*4880*/ R2UR UR5, R45 ;\n /*4890*/ LDG.E.64 R32, [R32.64] ;\n /*48a0*/ IADD3 R20, P0, R35, R0, RZ ;\n /*48b0*/ IADD3.X R21, R34, R2, RZ, P0, !PT ;\n /*48c0*/ SHF.L.U64.HI R21, R20, 0x3, R21 ;\n /*48d0*/ SHF.L.U32 R20, R20, 0x3, RZ ;\n /*48e0*/ IADD3 R20, P0, R7, R20, RZ ;\n /*48f0*/ IADD3.X R21, R8, R21, RZ, P0, !PT ;\n /*4900*/ MOV R20, R20 ;\n /*4910*/ MOV R21, R21 ;\n /*4920*/ MOV R20, R20 ;\n /*4930*/ MOV R21, R21 ;\n /*4940*/ R2UR UR4, R44 ;\n /*4950*/ R2UR UR5, R45 ;\n /*4960*/ STG.E.64 [R20.64], R32 ;\n.L_x_17:\n /*4970*/ WARPSYNC 0xffffffff ;\n /*4980*/ BAR.SYNC.DEFER_BLOCKING 0x0 ;\n /*4990*/ IADD3 R11, P0, R11, 0x1, RZ ;\n /*49a0*/ IADD3.X R12, R12, RZ, RZ, P0, !PT ;\n /*49b0*/ IADD3 R30, P0, R30, 0x1, RZ ;\n /*49c0*/ IADD3.X R31, R31, RZ, RZ, P0, !PT ;\n /*49d0*/ IADD3 R29, R29, -0x1, RZ ;\n /*49e0*/ ISETP.NE.AND P0, PT, R29, RZ, PT ;\n /*49f0*/ MOV R11, R11 ;\n /*4a00*/ MOV R12, R12 ;\n /*4a10*/ MOV R30, R30 ;\n /*4a20*/ MOV R31, R31 ;\n /*4a30*/ MOV R29, R29 ;\n /*4a40*/ @P0 BRA `(.L_x_18) ;\n.L_x_0:\n /*4a50*/ WARPSYNC 0xffffffff ;\n /*4a60*/ BAR.SYNC.DEFER_BLOCKING 0x0 ;\n /*4a70*/ EXIT ;\n.L_x_19:\n /*4a80*/ BRA `(.L_x_19);\n /*4a90*/ NOP;\n /*4aa0*/ NOP;\n /*4ab0*/ NOP;\n /*4ac0*/ NOP;\n /*4ad0*/ NOP;\n /*4ae0*/ NOP;\n /*4af0*/ NOP;\n /*4b00*/ NOP;\n /*4b10*/ NOP;\n /*4b20*/ NOP;\n /*4b30*/ NOP;\n /*4b40*/ NOP;\n /*4b50*/ NOP;\n /*4b60*/ NOP;\n /*4b70*/ NOP;\n.L_x_20:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.weak\t__cxa_pure_virtual ; -- Begin function __cxa_pure_virtual\n\t.p2align\t2\n\t.type\t__cxa_pure_virtual,@function\n__cxa_pure_virtual: ; @__cxa_pure_virtual\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB0_1: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB0_1\n.Lfunc_end0:\n\t.size\t__cxa_pure_virtual, .Lfunc_end0-__cxa_pure_virtual\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 56\n; NumSgprs: 1\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.weak\t__cxa_deleted_virtual ; -- Begin function __cxa_deleted_virtual\n\t.p2align\t2\n\t.type\t__cxa_deleted_virtual,@function\n__cxa_deleted_virtual: ; @__cxa_deleted_virtual\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB1_1: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB1_1\n.Lfunc_end1:\n\t.size\t__cxa_deleted_virtual, .Lfunc_end1-__cxa_deleted_virtual\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 56\n; NumSgprs: 1\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hsa_signal_add\n\t.type\t__ockl_hsa_signal_add,@function\n__ockl_hsa_signal_add: ; @__ockl_hsa_signal_add\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v6, s32 offset:48 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v4, s32 offset:36 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v3, s32 offset:32 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v2\n\tscratch_load_b32 v2, off, s32 offset:32 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v1, s32 offset:28 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v1, v0\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[3:4], s32 offset:20 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v3, v1\n\tscratch_store_b64 off, v[3:4], s32 offset:12 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v0, v1\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v1, v2\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v0, s1, v0, s1\n\tv_add_co_ci_u32_e64 v2, s0, v1, s0, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s32 offset:4 ; 8-byte Folded Spill\n; %bb.1:\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 3\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, 0\n ; implicit-def: $vgpr6 : SGPR spill to VGPR lane\n\tv_writelane_b32 v6, s1, 0\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 1\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_3\n; %bb.2:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 4\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s1, 2\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 3\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_17\n\ts_branch .LBB2_4\n.LBB2_3:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 1\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s2, v6, 0\n\tv_writelane_b32 v6, s2, 4\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s2, 5\n\tv_writelane_b32 v6, s1, 6\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 7\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_13\n\ts_branch .LBB2_6\n.LBB2_4:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 5\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, -1\n\tv_writelane_b32 v6, s0, 8\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 9\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_15\n\ts_branch .LBB2_18\n.LBB2_5:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 10\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_readlane_b32 s0, v6, 11\n\ts_and_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 0\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_3\n.LBB2_6:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 12\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_7\n\ts_branch .LBB2_14\n.LBB2_7:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 12\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s2, v6, 4\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s2, 13\n\tv_writelane_b32 v6, s1, 14\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 15\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_9\n; %bb.8:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 4\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_lt_i32_e64 s2, v0, s0\n\ts_mov_b32 s0, -1\n\ts_mov_b32 s0, exec_lo\n\ts_and_not1_b32 s1, s1, exec_lo\n\ts_and_b32 s2, s2, exec_lo\n\ts_or_b32 s1, s1, s2\n\tv_writelane_b32 v6, s1, 13\n\tv_writelane_b32 v6, s0, 14\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n.LBB2_9:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s3, v6, 15\n\ts_or_b32 exec_lo, exec_lo, s3\n\tv_readlane_b32 s1, v6, 4\n\tv_readlane_b32 s2, v6, 13\n\tv_readlane_b32 s0, v6, 14\n\ts_and_b32 s0, s0, exec_lo\n\ts_and_not1_b32 s1, s1, exec_lo\n\ts_and_b32 s2, s2, exec_lo\n\ts_or_b32 s1, s1, s2\n\tv_writelane_b32 v6, s1, 5\n\tv_writelane_b32 v6, s0, 6\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_13\n.LBB2_10:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 16\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 17\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n.LBB2_11:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 18\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v6, 17\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 19\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_19\n; %bb.12:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_branch .LBB2_19\n.LBB2_13:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v6, 7\n\ts_or_b32 exec_lo, exec_lo, s2\n\tv_readlane_b32 s0, v6, 5\n\tv_readlane_b32 s1, v6, 6\n\tv_writelane_b32 v6, s1, 16\n\tv_writelane_b32 v6, s1, 17\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 18\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_11\n\ts_branch .LBB2_10\n.LBB2_14:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_branch .LBB2_7\n.LBB2_15:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 9\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_readlane_b32 s0, v6, 8\n\ts_and_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 2\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_17\n.LBB2_16:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_branch .LBB2_5\n.LBB2_17:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 3\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v6, 2\n\tv_writelane_b32 v6, s1, 11\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 10\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_5\n\ts_branch .LBB2_16\n.LBB2_18:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b32 s0, 0\n\ts_xor_b32 s0, exec_lo, -1\n\tv_writelane_b32 v6, s0, 8\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_15\n.LBB2_19:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 19\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:12 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[0:1], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:40 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_ne_u64_e64 s1, v[0:1], s[0:1]\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 20\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_21\n; %bb.20:\n\tscratch_load_b64 v[1:2], off, s32 offset:40 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s32 offset:12 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b32 v0, v[3:4], off offset:24\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v5, 0\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\tv_mov_b32_e32 v4, v5\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[1:2], v[3:4], off\n\tv_readfirstlane_b32 s0, v0\n\ts_mov_b32 s1, 0xff\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB2_21:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 20\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v6, off, s32 offset:48 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end2:\n\t.size\t__ockl_hsa_signal_add, .Lfunc_end2-__ockl_hsa_signal_add\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 1952\n; NumSgprs: 33\n; NumVgprs: 7\n; ScratchSize: 56\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hostcall_internal\n\t.type\t__ockl_hostcall_internal,@function\n__ockl_hostcall_internal: ; @__ockl_hostcall_internal\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s18, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v24, s33 offset:308 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v25, s33 offset:312 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v26, s33 offset:316 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0x150\n\tv_writelane_b32 v24, s30, 0\n\tv_writelane_b32 v24, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:132 ; 4-byte Folded Spill\n ; implicit-def: $vgpr26 : SGPR spill to VGPR lane\n\tv_writelane_b32 v26, s6, 0\n\tv_writelane_b32 v26, s7, 1\n\tscratch_store_b32 off, v18, s33 offset:128 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v16\n\tscratch_load_b32 v16, off, s33 offset:128 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:124 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v14\n\tscratch_load_b32 v14, off, s33 offset:124 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:120 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v12\n\tscratch_load_b32 v12, off, s33 offset:120 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:116 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v10\n\tscratch_load_b32 v10, off, s33 offset:116 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:112 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v8\n\tscratch_load_b32 v8, off, s33 offset:112 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:108 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v6\n\tscratch_load_b32 v6, off, s33 offset:108 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:104 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v4\n\tscratch_load_b32 v4, off, s33 offset:104 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:100 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v2\n\tscratch_load_b32 v2, off, s33 offset:100 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:96 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v1, s33 offset:92 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v1, v0\n\tscratch_load_b32 v0, off, s33 offset:92 ; 4-byte Folded Reload\n\tv_writelane_b32 v26, s15, 2\n\tv_writelane_b32 v26, s14, 3\n\tv_writelane_b32 v26, s13, 4\n\tv_writelane_b32 v26, s12, 5\n\tv_writelane_b32 v26, s10, 6\n\tv_writelane_b32 v26, s11, 7\n\tv_writelane_b32 v26, s8, 8\n\tv_writelane_b32 v26, s9, 9\n\tv_writelane_b32 v26, s4, 10\n\tv_writelane_b32 v26, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\ts_waitcnt vmcnt(8)\n\tv_mov_b32_e32 v18, v16\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr15 killed $vgpr15 def $vgpr15_vgpr16 killed $exec\n\ts_waitcnt vmcnt(7)\n\tv_mov_b32_e32 v16, v14\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec\n\ts_waitcnt vmcnt(6)\n\tv_mov_b32_e32 v14, v12\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\ts_waitcnt vmcnt(5)\n\tv_mov_b32_e32 v12, v10\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\ts_waitcnt vmcnt(4)\n\tv_mov_b32_e32 v10, v8\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\ts_waitcnt vmcnt(3)\n\tv_mov_b32_e32 v8, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v6, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[17:18], s33 offset:84 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[15:16], s33 offset:76 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[13:14], s33 offset:68 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[11:12], s33 offset:60 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[9:10], s33 offset:52 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[7:8], s33 offset:44 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[5:6], s33 offset:36 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[3:4], s33 offset:28 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s0, -1\n\tv_mbcnt_lo_u32_b32 v0, s0, s1\n\tv_mbcnt_hi_u32_b32 v0, s0, v0\n\t;;#ASMSTART\n\t;;#ASMEND\n\tv_mov_b32_e32 v3, v0\n\tscratch_store_b32 off, v3, s33 offset:24 ; 4-byte Folded Spill\n\tv_readfirstlane_b32 s0, v0\n\tscratch_store_b64 off, v[1:2], s33 offset:16 ; 8-byte Folded Spill\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, s1\n\tv_writelane_b32 v26, s0, 12\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v0, 0\n\tv_mov_b32_e32 v1, 0\n\tscratch_store_b64 off, v[0:1], s33 offset:8 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 13\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_6\n; %bb.1:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_mov_b64 s[2:3], 24\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:160 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b64 s[2:3], 40\n\tv_mov_b32_e32 v4, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v5, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v4, s1, v4, s1\n\tv_add_co_ci_u32_e64 v6, s0, v5, s0, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tscratch_store_b64 off, v[4:5], s33 offset:152 ; 8-byte Folded Spill\n\tglobal_load_b64 v[5:6], v[0:1], off\n\tglobal_load_b64 v[10:11], v[0:1], off offset:40\n\tv_mov_b32_e32 v8, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v11\n\tv_and_b32_e64 v4, v4, v8\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v7, v10\n\tv_and_b32_e64 v12, v7, v9\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_mov_b32_e32 v4, v12\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[10:11], s0, v4, s1, 0\n\tv_mov_b32_e32 v14, v11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec\n\tv_mov_b32_e32 v15, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[12:13], s0, v[12:13]\n\tv_mov_b32_e32 v4, v12\n\tv_mad_u64_u32 v[12:13], s1, v4, s1, v[14:15]\n ; kill: def $vgpr12 killed $vgpr12 killed $vgpr12_vgpr13 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s1\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_lshlrev_b64 v[13:14], s0, v[12:13]\n\tv_mov_b32_e32 v7, v14\n\tv_mov_b32_e32 v11, v10\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\tv_mov_b32_e32 v4, v12\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v10, v13\n\tv_mov_b32_e32 v7, v11\n\tv_or_b32_e64 v10, v7, v10\n ; kill: def $vgpr10 killed $vgpr10 def $vgpr10_vgpr11 killed $exec\n\tv_mov_b32_e32 v11, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v11\n\tv_add_co_u32 v4, s0, v4, v7\n\tv_add_co_ci_u32_e64 v6, s0, v5, v6, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tglobal_load_b64 v[4:5], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v10, v5\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s0, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:144 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:136 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 15\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_5\n.LBB3_2: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 14\n\tscratch_load_b64 v[2:3], off, s33 offset:144 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:160 ; 8-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:152 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[5:6], v[4:5], off\n\tglobal_load_b64 v[10:11], v[7:8], off\n\tv_mov_b32_e32 v8, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v11\n\tv_and_b32_e64 v4, v4, v8\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v7, v10\n\tv_and_b32_e64 v12, v7, v9\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_mov_b32_e32 v4, v12\n\ts_mov_b32 s2, 24\n\tv_mad_u64_u32 v[10:11], s0, v4, s2, 0\n\tv_mov_b32_e32 v14, v11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec\n\tv_mov_b32_e32 v15, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[12:13], s0, v[12:13]\n\tv_mov_b32_e32 v4, v12\n\tv_mad_u64_u32 v[12:13], s2, v4, s2, v[14:15]\n ; kill: def $vgpr12 killed $vgpr12 killed $vgpr12_vgpr13 killed $exec\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s2\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_lshlrev_b64 v[13:14], s0, v[12:13]\n\tv_mov_b32_e32 v7, v14\n\tv_mov_b32_e32 v11, v10\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\tv_mov_b32_e32 v4, v12\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v10, v13\n\tv_mov_b32_e32 v7, v11\n\tv_or_b32_e64 v10, v7, v10\n ; kill: def $vgpr10 killed $vgpr10 def $vgpr10_vgpr11 killed $exec\n\tv_mov_b32_e32 v11, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v11\n\tv_add_co_u32 v4, s0, v4, v7\n\tv_add_co_ci_u32_e64 v6, s0, v5, v6, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tglobal_load_b64 v[4:5], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v10, v5\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e64 s0, v[0:1], v[2:3]\n\ts_or_b32 s0, s0, s1\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:144 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:168 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 16\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_2\n; %bb.3:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 16\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.4:\n\tscratch_load_b64 v[0:1], off, s33 offset:168 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:136 ; 8-byte Folded Spill\n.LBB3_5:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:136 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:8 ; 8-byte Folded Spill\n.LBB3_6:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 13\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:8 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[4:5], s0, v[4:5]\n\tv_mov_b32_e32 v2, v4\n\tv_readfirstlane_b32 s4, v3\n\tv_readfirstlane_b32 s2, v2\n ; implicit-def: $sgpr5\n ; implicit-def: $sgpr3\n ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3\n\ts_mov_b32 s3, s5\n\ts_lshl_b64 s[2:3], s[2:3], s0\n\ts_mov_b32 s0, 0\n ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5\n\ts_mov_b32 s5, s0\n\ts_or_b64 s[2:3], s[2:3], s[4:5]\n\tv_writelane_b32 v26, s2, 17\n\tv_writelane_b32 v26, s3, 18\n\tglobal_load_b64 v[2:3], v[0:1], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:200 ; 8-byte Folded Spill\n\ts_mov_b64 s[6:7], 40\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s7\n\tv_add_co_u32 v2, s4, v2, s4\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s4\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tglobal_load_b64 v[3:4], v[0:1], off offset:40\n\ts_mov_b32 s0, s3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v4\n\tv_and_b32_e64 v2, s0, v2\n\ts_mov_b32 s0, s2\n ; kill: def $vgpr3 killed $vgpr3 killed $vgpr3_vgpr4 killed $exec\n\tv_and_b32_e64 v3, s0, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v5, v3\n\tscratch_store_b64 off, v[5:6], s33 offset:184 ; 8-byte Folded Spill\n\tglobal_load_b64 v[1:2], v[0:1], off offset:8\n\ts_mov_b32 s0, 12\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s0, v0, v3\n\tv_add_co_ci_u32_e64 v2, s0, v1, v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:176 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], exec\n\tv_writelane_b32 v26, s2, 19\n\tv_writelane_b32 v26, s3, 20\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 21\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_8\n; %bb.7:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 19\n\tv_readlane_b32 s1, v26, 20\n\tscratch_load_b32 v2, off, s33 offset:96 ; 4-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v5, v0\n\ts_mov_b32 s3, 24\n\tv_mad_u64_u32 v[3:4], s2, v5, s3, 0\n\tv_mov_b32_e32 v9, v4\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v5, s2\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v5\n\ts_mov_b32 s2, 32\n\tv_lshrrev_b64 v[0:1], s2, v[0:1]\n\tv_mov_b32_e32 v5, v0\n\tv_mad_u64_u32 v[0:1], s3, v5, s3, v[9:10]\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v5, s3\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v5\n\tv_lshlrev_b64 v[9:10], s2, v[0:1]\n\tv_mov_b32_e32 v1, v10\n\tv_mov_b32_e32 v4, v3\n\ts_mov_b32 s2, 0\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v0, v5\n\tv_or_b32_e64 v0, v0, v1\n\tv_mov_b32_e32 v3, v9\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v5, v1, v3\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v0\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v3, v6\n\tv_add_co_u32 v0, s2, v0, v4\n\tv_add_co_ci_u32_e64 v3, s2, v1, v3, s2\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tglobal_store_b32 v[0:1], v2, off offset:16\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tglobal_store_b64 v[0:1], v[2:3], off offset:8\n\tv_mov_b32_e32 v2, 1\n\tglobal_store_b32 v[0:1], v2, off offset:20\n.LBB3_8:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[2:3], off, s33 offset:84 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:76 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:68 ; 8-byte Folded Reload\n\tscratch_load_b64 v[8:9], off, s33 offset:60 ; 8-byte Folded Reload\n\tscratch_load_b64 v[10:11], off, s33 offset:52 ; 8-byte Folded Reload\n\tscratch_load_b64 v[12:13], off, s33 offset:44 ; 8-byte Folded Reload\n\tscratch_load_b64 v[14:15], off, s33 offset:36 ; 8-byte Folded Reload\n\tscratch_load_b64 v[16:17], off, s33 offset:28 ; 8-byte Folded Reload\n\tscratch_load_b64 v[22:23], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:24 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v18, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v18\n\ts_mov_b32 s0, 6\n\ts_waitcnt vmcnt(0)\n\tv_lshlrev_b64 v[20:21], s0, v[0:1]\n\tv_mov_b32_e32 v0, v22\n\tv_mov_b32_e32 v19, v20\n\tv_mov_b32_e32 v1, v23\n\tv_mov_b32_e32 v18, v21\n\tv_add_co_u32 v0, s0, v0, v19\n\tv_add_co_ci_u32_e64 v18, s0, v1, v18, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v18\n\tscratch_store_b64 off, v[0:1], s33 offset:216 ; 8-byte Folded Spill\n\tglobal_store_b64 v[0:1], v[16:17], off\n\ts_mov_b64 s[4:5], 8\n\tv_mov_b32_e32 v16, v0\n\ts_mov_b32 s2, s4\n\tv_mov_b32_e32 v17, v1\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v16, s2, v16, s2\n\tv_add_co_ci_u32_e64 v18, s0, v17, s0, s2\n ; kill: def $vgpr16 killed $vgpr16 def $vgpr16_vgpr17 killed $exec\n\tv_mov_b32_e32 v17, v18\n\tscratch_store_b64 off, v[16:17], s33 offset:208 ; 8-byte Folded Spill\n\tglobal_store_b64 v[0:1], v[14:15], off offset:8\n\tglobal_store_b64 v[0:1], v[12:13], off offset:16\n\tglobal_store_b64 v[0:1], v[10:11], off offset:24\n\tglobal_store_b64 v[0:1], v[8:9], off offset:32\n\tglobal_store_b64 v[0:1], v[6:7], off offset:40\n\tglobal_store_b64 v[0:1], v[4:5], off offset:48\n\tglobal_store_b64 v[0:1], v[2:3], off offset:56\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 22\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_13\n; %bb.9:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[5:6], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:192 ; 8-byte Folded Reload\n\ts_mov_b64 s[4:5], 32\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s4\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:240 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:32 glc\n\ts_waitcnt vmcnt(1)\n\tglobal_load_b64 v[7:8], v[7:8], off\n\ts_mov_b32 s0, s3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v8\n\tv_and_b32_e64 v4, v4, s0\n\ts_mov_b32 s1, s2\n ; kill: def $vgpr7 killed $vgpr7 killed $vgpr7_vgpr8 killed $exec\n\tv_and_b32_e64 v7, v7, s1\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v4\n\tv_mov_b32_e32 v4, v7\n\ts_mov_b32 s3, 24\n\tv_mad_u64_u32 v[9:10], s2, v4, s3, 0\n\tv_mov_b32_e32 v11, v10\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v4, s2\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\ts_mov_b32 s2, 32\n\tv_lshrrev_b64 v[7:8], s2, v[7:8]\n\tv_mov_b32_e32 v4, v7\n\tv_mad_u64_u32 v[7:8], s3, v4, s3, v[11:12]\n ; kill: def $vgpr7 killed $vgpr7 killed $vgpr7_vgpr8 killed $exec\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v4, s3\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v4\n\tv_lshlrev_b64 v[7:8], s2, v[7:8]\n\tv_mov_b32_e32 v11, v8\n ; kill: def $vgpr9 killed $vgpr9 killed $vgpr9_vgpr10 killed $exec\n\ts_mov_b32 s2, 0\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v4, v10\n\tv_or_b32_e64 v4, v4, v11\n\tv_mov_b32_e32 v8, v7\n\tv_mov_b32_e32 v7, v9\n\tv_or_b32_e64 v8, v7, v8\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v8\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v9\n\tv_add_co_u32 v4, s2, v4, v7\n\tv_add_co_ci_u32_e64 v6, s2, v5, v6, s2\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tscratch_store_b64 off, v[4:5], s33 offset:232 ; 8-byte Folded Spill\n\tglobal_store_b64 v[4:5], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s1\n\tv_mov_b32_e32 v10, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s2, v[0:1], v[2:3]\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s2, 23\n\tv_writelane_b32 v26, s0, 24\n\tscratch_store_b64 off, v[0:1], s33 offset:224 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 25\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_14\n.LBB3_10: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 24\n\tv_readlane_b32 s1, v26, 23\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[2:3], off, s33 offset:224 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:240 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:232 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_store_b64 v[4:5], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n\ts_mov_b32 s1, s3\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v10, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s1, v[0:1], v[2:3]\n\ts_or_b32 s0, s1, s0\n\tv_writelane_b32 v26, s1, 23\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 24\n\tscratch_store_b64 off, v[0:1], s33 offset:224 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 26\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_10\n; %bb.11:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 26\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.12:\n\ts_branch .LBB3_14\n.LBB3_13:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_branch .LBB3_15\n.LBB3_14:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 25\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s15, v26, 2\n\tv_readlane_b32 s14, v26, 3\n\tv_readlane_b32 s13, v26, 4\n\tv_readlane_b32 s12, v26, 5\n\tv_readlane_b32 s10, v26, 6\n\tv_readlane_b32 s11, v26, 7\n\tv_readlane_b32 s8, v26, 8\n\tv_readlane_b32 s9, v26, 9\n\tv_readlane_b32 s6, v26, 0\n\tv_readlane_b32 s7, v26, 1\n\tv_readlane_b32 s4, v26, 10\n\tv_readlane_b32 s5, v26, 11\n\tscratch_load_b32 v31, off, s33 offset:132 ; 4-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_mov_b32 s0, 32\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[0:1], s0, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v2\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hsa_signal_add@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hsa_signal_add@rel32@hi+12\n\tv_mov_b32_e32 v2, 1\n\tv_mov_b32_e32 v3, 0\n\tv_mov_b32_e32 v4, 3\n\ts_swappc_b64 s[30:31], s[0:1]\n\ts_branch .LBB3_13\n.LBB3_15:\n\tscratch_load_b64 v[6:7], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[3:4], s0, v2, s1, 0\n\tv_mov_b32_e32 v8, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v2\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[0:1]\n\tv_mov_b32_e32 v2, v0\n\tv_mad_u64_u32 v[0:1], s1, v2, s1, v[8:9]\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_lshlrev_b64 v[1:2], s0, v[0:1]\n\tv_mov_b32_e32 v5, v2\n ; kill: def $vgpr3 killed $vgpr3 killed $vgpr3_vgpr4 killed $exec\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_mov_b32_e32 v0, v4\n\tv_or_b32_e64 v0, v0, v5\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v1, v3\n\tv_or_b32_e64 v4, v1, v2\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v1, v6\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v1, s0, v1, v3\n\tv_add_co_ci_u32_e64 v0, s0, v0, v2, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b64 s[2:3], 20\n\tv_mov_b32_e32 v0, v1\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v1, v2\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v0, s1, v0, s1\n\tv_add_co_ci_u32_e64 v2, s0, v1, s0, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:248 ; 8-byte Folded Spill\n.LBB3_16: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 12\n\ts_mov_b32 s0, 1\n\tv_mov_b32_e32 v0, 1\n\tscratch_store_b32 off, v0, s33 offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 27\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_18\n; %bb.17: ; in Loop: Header=BB3_16 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:248 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b32 v0, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b32 s0, 1\n\tv_and_b32_e64 v0, v0, s0\n\tscratch_store_b32 off, v0, s33 offset:256 ; 4-byte Folded Spill\n.LBB3_18: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 27\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s33 offset:256 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s1, v0\n\ts_mov_b32 s0, -1\n\ts_mov_b32 s2, 0\n\ts_cmp_eq_u32 s1, s2\n\tv_writelane_b32 v26, s0, 28\n\ts_mov_b32 s17, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_cbranch_scc1 .LBB3_20\n; %bb.19: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_sleep 1\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v26, s0, 28\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n.LBB3_20: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 28\n\tv_cndmask_b32_e64 v0, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v0, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n\ts_cbranch_vccnz .LBB3_16\n; %bb.21:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[0:1], off, s33 offset:208 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:216 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[2:3], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:268 ; 8-byte Folded Spill\n\tglobal_load_b64 v[0:1], v[0:1], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:260 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 29\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_27\n; %bb.22:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:192 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[11:12], v[2:3], off\n\ts_mov_b64 s[4:5], 1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v11\n\ts_mov_b32 s1, s4\n\tv_mov_b32_e32 v3, v12\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v4, v2\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v5, v3\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v4, s1, v4, s1\n\tv_add_co_ci_u32_e64 v6, s0, v5, s0, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_eq_u64_e64 s0, v[4:5], s[0:1]\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v6, v5\n\tv_cndmask_b32_e64 v10, v6, v7, s0\n\tv_mov_b32_e32 v3, v2\n\tv_mov_b32_e32 v2, v4\n\tv_cndmask_b32_e64 v4, v2, v3, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v8, v4\n\tv_mov_b32_e32 v9, v10\n\tv_mov_b32_e32 v2, v8\n\tv_mov_b32_e32 v3, v9\n\tscratch_store_b64 off, v[2:3], s33 offset:300 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], 24\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v5, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v5\n\tscratch_store_b64 off, v[2:3], s33 offset:292 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:24 glc\n\tglobal_load_b64 v[6:7], v[0:1], off\n\tv_mov_b32_e32 v5, v9\n\tv_mov_b32_e32 v13, v12\n\tv_and_b32_e64 v5, v5, v13\n ; kill: def $vgpr8 killed $vgpr8 killed $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v11\n\tv_and_b32_e64 v8, v8, v9\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v5\n\tv_mov_b32_e32 v5, v8\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[11:12], s0, v5, s1, 0\n\tv_mov_b32_e32 v13, v12\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v5, s0\n ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec\n\tv_mov_b32_e32 v14, v5\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[8:9], s0, v[8:9]\n\tv_mov_b32_e32 v5, v8\n\tv_mad_u64_u32 v[8:9], s1, v5, s1, v[13:14]\n ; kill: def $vgpr8 killed $vgpr8 killed $vgpr8_vgpr9 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v5, s1\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v5\n\tv_lshlrev_b64 v[8:9], s0, v[8:9]\n\tv_mov_b32_e32 v13, v9\n ; kill: def $vgpr11 killed $vgpr11 killed $vgpr11_vgpr12 killed $exec\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v5, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v5\n\tv_mov_b32_e32 v5, v12\n\tv_or_b32_e64 v5, v5, v13\n\tv_mov_b32_e32 v9, v8\n\tv_mov_b32_e32 v8, v11\n\tv_or_b32_e64 v11, v8, v9\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v5\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v8, v11\n\tv_mov_b32_e32 v6, v7\n\tv_mov_b32_e32 v7, v12\n\tv_add_co_u32 v5, s0, v5, v8\n\tv_add_co_ci_u32_e64 v7, s0, v6, v7, s0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v7\n\tscratch_store_b64 off, v[5:6], s33 offset:284 ; 8-byte Folded Spill\n\tglobal_store_b64 v[5:6], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s2, v[0:1], v[2:3]\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s2, 30\n\tv_writelane_b32 v26, s0, 31\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\tscratch_store_b64 off, v[0:1], s33 offset:276 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n ; implicit-def: $vgpr26 : SGPR spill to VGPR lane\n\tv_writelane_b32 v26, s0, 0\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_26\n.LBB3_23: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v25, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v25, 31\n\tv_readlane_b32 s1, v25, 30\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\tscratch_load_b64 v[2:3], off, s33 offset:276 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:292 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:300 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:284 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_store_b64 v[6:7], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v10, v5\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s1, v[0:1], v[2:3]\n\ts_or_b32 s0, s1, s0\n\tv_writelane_b32 v25, s1, 30\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v25, s1, 31\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v25, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\tscratch_store_b64 off, v[0:1], s33 offset:276 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_23\n; %bb.24:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.25:\n.LBB3_26:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 0\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB3_27:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[3:4], off, s33 offset:260 ; 8-byte Folded Reload\n\tscratch_load_b64 v[1:2], off, s33 offset:268 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v3\n\tv_mov_b32_e32 v3, v4\n\tv_readlane_b32 s30, v24, 0\n\tv_readlane_b32 s31, v24, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v24, off, s33 offset:308 ; 4-byte Folded Reload\n\tscratch_load_b32 v25, off, s33 offset:312 ; 4-byte Folded Reload\n\tscratch_load_b32 v26, off, s33 offset:316 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xfffffeb0\n\ts_mov_b32 s33, s18\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end3:\n\t.size\t__ockl_hostcall_internal, .Lfunc_end3-__ockl_hostcall_internal\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 5344\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 392\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hostcall_preview\n\t.type\t__ockl_hostcall_preview,@function\n__ockl_hostcall_preview: ; @__ockl_hostcall_preview\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v27, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tv_writelane_b32 v27, s33, 0\n\tv_writelane_b32 v27, s30, 1\n\tv_writelane_b32 v27, s31, 2\n\tv_mov_b32_e32 v18, v16\n\tv_mov_b32_e32 v17, v15\n\tv_mov_b32_e32 v16, v14\n\tv_mov_b32_e32 v15, v13\n\tv_mov_b32_e32 v14, v12\n\tv_mov_b32_e32 v13, v11\n\tv_mov_b32_e32 v12, v10\n\tv_mov_b32_e32 v11, v9\n\tv_mov_b32_e32 v10, v8\n\tv_mov_b32_e32 v9, v7\n\tv_mov_b32_e32 v8, v6\n\tv_mov_b32_e32 v7, v5\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v5, v3\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s0, s[0:1], 0x0\n\ts_mov_b32 s1, 0x1f4\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_i32 s0, s1\n\ts_mov_b32 s1, 0x50\n\ts_mov_b32 s0, 24\n\ts_cselect_b32 s0, s0, s1\n\ts_load_b64 s[0:1], s[8:9], s0 offset:0x0\n\ts_waitcnt lgkmcnt(0)\n\ts_mov_b32 s3, s0\n\ts_mov_b32 s2, 32\n\ts_lshr_b64 s[0:1], s[0:1], s2\n\ts_mov_b32 s2, s0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_internal@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_internal@rel32@hi+12\n\tv_mov_b32_e32 v0, s3\n\tv_mov_b32_e32 v1, s2\n\tv_readlane_b32 s30, v27, 1\n\tv_readlane_b32 s31, v27, 2\n\tv_readlane_b32 s33, v27, 0\n\ts_xor_saveexec_b32 s2, -1\n\tscratch_load_b32 v27, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s2\n\ts_setpc_b64 s[0:1]\n.Lfunc_end4:\n\t.size\t__ockl_hostcall_preview, .Lfunc_end4-__ockl_hostcall_preview\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 272\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 400\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_stderr_begin\n\t.type\t__ockl_fprintf_stderr_begin,@function\n__ockl_fprintf_stderr_begin: ; @__ockl_fprintf_stderr_begin\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s16, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v28, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 16\n\tv_writelane_b32 v28, s30, 0\n\tv_writelane_b32 v28, s31, 1\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\tv_mov_b32_e32 v1, 33\n\tv_mov_b32_e32 v3, 1\n\tv_mov_b32_e32 v16, 0\n\tv_mov_b32_e32 v2, v16\n\tv_mov_b32_e32 v4, v16\n\tv_mov_b32_e32 v5, v16\n\tv_mov_b32_e32 v6, v16\n\tv_mov_b32_e32 v7, v16\n\tv_mov_b32_e32 v8, v16\n\tv_mov_b32_e32 v9, v16\n\tv_mov_b32_e32 v10, v16\n\tv_mov_b32_e32 v11, v16\n\tv_mov_b32_e32 v12, v16\n\tv_mov_b32_e32 v13, v16\n\tv_mov_b32_e32 v14, v16\n\tv_mov_b32_e32 v15, v16\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_store_b32 off, v1, s33 ; 4-byte Folded Spill\n ; kill: def $vgpr1 killed $vgpr3 killed $exec\n\tscratch_load_b32 v3, off, s33 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v3\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v28, 0\n\tv_readlane_b32 s31, v28, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v28, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, -16\n\ts_mov_b32 s33, s16\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end5:\n\t.size\t__ockl_fprintf_stderr_begin, .Lfunc_end5-__ockl_fprintf_stderr_begin\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 228\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 416\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_append_string_n\n\t.type\t__ockl_fprintf_append_string_n,@function\n__ockl_fprintf_append_string_n: ; @__ockl_fprintf_append_string_n\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s20, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v32, s33 offset:704 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v33, s33 offset:708 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v34, s33 offset:712 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0x2d0\n\tv_writelane_b32 v32, s30, 0\n\tv_writelane_b32 v32, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:68 ; 4-byte Folded Spill\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\tv_writelane_b32 v34, s6, 0\n\tv_writelane_b32 v34, s7, 1\n\tscratch_store_b32 off, v6, s33 offset:60 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v5, s33 offset:56 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v4, s33 offset:64 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v6, v3\n\tscratch_load_b32 v3, off, s33 offset:64 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v4, v2\n\tscratch_load_b32 v2, off, s33 offset:60 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v4, s33 offset:52 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v7, v1\n\tscratch_load_b32 v1, off, s33 offset:56 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v5, v0\n\tscratch_load_b32 v0, off, s33 offset:52 ; 4-byte Folded Reload\n\tv_writelane_b32 v34, s15, 2\n\tv_writelane_b32 v34, s14, 3\n\tv_writelane_b32 v34, s13, 4\n\tv_writelane_b32 v34, s12, 5\n\tv_writelane_b32 v34, s10, 6\n\tv_writelane_b32 v34, s11, 7\n\tv_writelane_b32 v34, s8, 8\n\tv_writelane_b32 v34, s9, 9\n\tv_writelane_b32 v34, s4, 10\n\tv_writelane_b32 v34, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v1\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v7\n\tscratch_store_b64 off, v[3:4], s33 offset:44 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v3, v0\n\tscratch_store_b64 off, v[3:4], s33 offset:36 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s0, 0\n\tv_cmp_eq_u32_e64 s0, v2, s0\n\tv_mov_b32_e32 v4, v6\n\ts_mov_b64 s[2:3], 2\n\ts_mov_b32 s1, s3\n\tv_or_b32_e64 v2, v4, s1\n\tv_mov_b32_e32 v3, v5\n\ts_mov_b32 s1, s2\n\tv_or_b32_e64 v5, v3, s1\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v2\n\tv_mov_b32_e32 v2, v6\n\tv_cndmask_b32_e64 v4, v2, v4, s0\n\tv_mov_b32_e32 v2, v5\n\tv_cndmask_b32_e64 v2, v2, v3, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:28 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_ne_u64_e64 s0, v[0:1], s[0:1]\n ; implicit-def: $sgpr4_sgpr5_sgpr6_sgpr7\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tv_mov_b32_e32 v2, s6\n\tv_mov_b32_e32 v3, s7\n\tscratch_store_b128 off, v[0:3], s33 offset:12 ; 16-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 12\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_3\n\ts_branch .LBB6_2\n.LBB6_1:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v34, 2\n\tv_readlane_b32 s14, v34, 3\n\tv_readlane_b32 s13, v34, 4\n\tv_readlane_b32 s12, v34, 5\n\tv_readlane_b32 s10, v34, 6\n\tv_readlane_b32 s11, v34, 7\n\tv_readlane_b32 s8, v34, 8\n\tv_readlane_b32 s9, v34, 9\n\tv_readlane_b32 s6, v34, 0\n\tv_readlane_b32 s7, v34, 1\n\tv_readlane_b32 s4, v34, 10\n\tv_readlane_b32 s5, v34, 11\n\tscratch_load_b32 v31, off, s33 offset:68 ; 4-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:28 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v3\n\tv_and_b32_e64 v4, v0, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v0, v2\n\tv_and_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_mov_b32_e32 v4, v1\n\ts_mov_b64 s[0:1], 32\n\ts_mov_b32 s2, s1\n\tv_or_b32_e64 v4, v4, s2\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_or_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_mov_b32_e32 v1, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[2:3], s0, v[2:3]\n ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\tv_mov_b32_e32 v16, 0\n\tscratch_store_b32 off, v16, s33 offset:88 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v16\n\tv_mov_b32_e32 v4, v16\n\tv_mov_b32_e32 v5, v16\n\tv_mov_b32_e32 v6, v16\n\tv_mov_b32_e32 v7, v16\n\tv_mov_b32_e32 v8, v16\n\tv_mov_b32_e32 v9, v16\n\tv_mov_b32_e32 v10, v16\n\tv_mov_b32_e32 v11, v16\n\tv_mov_b32_e32 v12, v16\n\tv_mov_b32_e32 v13, v16\n\tv_mov_b32_e32 v14, v16\n\tv_mov_b32_e32 v15, v16\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_mov_b32_e32 v6, v1\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v4, v3\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v6\n\tv_mov_b32_e32 v2, v5\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b128 off, v[0:3], s33 offset:72 ; 16-byte Folded Spill\n\ts_branch .LBB6_63\n.LBB6_2:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b64 v[4:5], off, s33 offset:36 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:44 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:28 ; 8-byte Folded Reload\n\ts_mov_b64 s[0:1], 2\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v1, v3\n\tv_and_b32_e64 v8, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v0, v2\n\tv_and_b32_e64 v2, v0, s0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v8\n\tscratch_store_b64 off, v[2:3], s33 offset:124 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], -3\n\ts_mov_b32 s2, s1\n\tv_and_b32_e64 v2, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_and_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v10, v1\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\ts_mov_b64 s[2:3], 0\n\ts_mov_b32 s0, s3\n\ts_mov_b32 s1, s2\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v9, s1\n\tv_mov_b32_e32 v8, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v10\n\tv_mov_b32_e32 v2, v9\n\tv_mov_b32_e32 v3, v8\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v34, s0, 13\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[6:7], s33 offset:116 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[4:5], s33 offset:108 ; 8-byte Folded Spill\n\tscratch_store_b128 off, v[0:3], s33 offset:92 ; 16-byte Folded Spill\n\ts_branch .LBB6_4\n.LBB6_3:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 12\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b128 v[0:3], off, s33 offset:12 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:72 ; 16-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 14\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_63\n\ts_branch .LBB6_1\n.LBB6_4: ; =>This Loop Header: Depth=1\n ; Child Loop BB6_8 Depth 2\n ; Child Loop BB6_16 Depth 2\n ; Child Loop BB6_24 Depth 2\n ; Child Loop BB6_32 Depth 2\n ; Child Loop BB6_40 Depth 2\n ; Child Loop BB6_48 Depth 2\n ; Child Loop BB6_56 Depth 2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 13\n\tscratch_load_b64 v[6:7], off, s33 offset:124 ; 8-byte Folded Reload\n\tscratch_load_b128 v[8:11], off, s33 offset:92 ; 16-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:116 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:108 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:176 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[3:4], s33 offset:168 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 15\n\ts_mov_b64 s[2:3], 56\n\tv_cmp_gt_u64_e64 s0, v[3:4], s[2:3]\n\tv_mov_b32_e32 v1, v9\n\tv_mov_b32_e32 v2, v8\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v8, v2\n\tv_mov_b32_e32 v9, v1\n\tv_mov_b32_e32 v0, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or_b32_e64 v0, v0, v5\n\tv_mov_b32_e32 v5, v8\n\tv_or_b32_e64 v5, v5, v6\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v0\n\tv_mov_b32_e32 v0, v6\n\tv_cndmask_b32_e64 v0, v0, v1, s0\n\tv_mov_b32_e32 v1, v5\n\tv_cndmask_b32_e64 v1, v1, v2, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_cmp_lt_u64_e64 s1, v[3:4], s[2:3]\n\tv_mov_b32_e32 v0, v4\n\ts_mov_b32 s0, s3\n\tv_cndmask_b32_e64 v5, s0, v0, s1\n\tv_mov_b32_e32 v0, v3\n\ts_mov_b32 s0, s2\n\tv_cndmask_b32_e64 v0, s0, v0, s1\n\tscratch_store_b32 off, v0, s33 offset:164 ; 4-byte Folded Spill\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v3, v0\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:156 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:148 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:140 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:132 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 16\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_6\n; %bb.5: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:164 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 17\n\tv_writelane_b32 v34, s0, 18\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:184 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_11\n\ts_branch .LBB6_8\n.LBB6_6: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 16\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 20\n\tscratch_load_b64 v[0:1], off, s33 offset:140 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:132 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:212 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:208 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:200 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 21\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_12\n; %bb.7: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:212 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:208 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:200 ; 8-byte Folded Spill\n\ts_branch .LBB6_12\n.LBB6_8: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 18\n\tv_readlane_b32 s2, v34, 17\n\tscratch_load_b64 v[4:5], off, s33 offset:192 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:176 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 17\n\tv_writelane_b32 v34, s1, 18\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:220 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 22\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_8\n; %bb.9: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.10: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:220 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:184 ; 8-byte Folded Spill\n.LBB6_11: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 19\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:140 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 20\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:132 ; 8-byte Folded Spill\n\ts_branch .LBB6_6\n.LBB6_12: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:212 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:208 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:200 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:256 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:252 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:244 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:236 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:228 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 23\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_14\n; %bb.13: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:252 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 24\n\tv_writelane_b32 v34, s0, 25\n\tscratch_store_b64 off, v[2:3], s33 offset:272 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:264 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 26\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_19\n\ts_branch .LBB6_16\n.LBB6_14: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 23\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 27\n\tscratch_load_b64 v[0:1], off, s33 offset:236 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:228 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:292 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:288 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:280 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 28\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_20\n; %bb.15: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:244 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:252 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:292 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:288 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:280 ; 8-byte Folded Spill\n\ts_branch .LBB6_20\n.LBB6_16: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 25\n\tv_readlane_b32 s2, v34, 24\n\tscratch_load_b64 v[4:5], off, s33 offset:272 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:252 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:244 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 24\n\tv_writelane_b32 v34, s1, 25\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:272 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:300 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 29\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_16\n; %bb.17: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.18: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:300 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:264 ; 8-byte Folded Spill\n.LBB6_19: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 26\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:244 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:264 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:236 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 27\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:228 ; 8-byte Folded Spill\n\ts_branch .LBB6_14\n.LBB6_20: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 28\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:292 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:288 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:280 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:336 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:332 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:324 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:316 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:308 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 30\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_22\n; %bb.21: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:332 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v33, s2, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tv_writelane_b32 v34, s0, 0\n\tscratch_store_b64 off, v[2:3], s33 offset:352 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:344 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_27\n\ts_branch .LBB6_24\n.LBB6_22: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v33, 30\n\ts_or_saveexec_b32 s0, s0\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v34, 2\n\tscratch_load_b64 v[0:1], off, s33 offset:316 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:308 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:372 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:368 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:360 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 3\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_28\n; %bb.23: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:324 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:332 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:372 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:368 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:360 ; 8-byte Folded Spill\n\ts_branch .LBB6_28\n.LBB6_24: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 0\n\tv_readlane_b32 s2, v33, 31\n\tscratch_load_b64 v[4:5], off, s33 offset:352 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:332 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:324 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v33, s2, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tv_writelane_b32 v34, s1, 0\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:352 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:380 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 4\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_24\n; %bb.25: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.26: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:380 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:344 ; 8-byte Folded Spill\n.LBB6_27: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:324 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:344 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:316 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:308 ; 8-byte Folded Spill\n\ts_branch .LBB6_22\n.LBB6_28: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 3\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:372 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:368 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:360 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:416 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:412 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:404 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:396 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:388 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 5\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_30\n; %bb.29: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:412 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 6\n\tv_writelane_b32 v34, s0, 7\n\tscratch_store_b64 off, v[2:3], s33 offset:432 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:424 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 8\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_35\n\ts_branch .LBB6_32\n.LBB6_30: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 5\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 9\n\tscratch_load_b64 v[0:1], off, s33 offset:396 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:388 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:452 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:448 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:440 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 10\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_36\n; %bb.31: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:404 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:412 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:452 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:448 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:440 ; 8-byte Folded Spill\n\ts_branch .LBB6_36\n.LBB6_32: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 7\n\tv_readlane_b32 s2, v34, 6\n\tscratch_load_b64 v[4:5], off, s33 offset:432 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:412 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:404 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 6\n\tv_writelane_b32 v34, s1, 7\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:432 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:460 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 11\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_32\n; %bb.33: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 11\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.34: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:460 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:424 ; 8-byte Folded Spill\n.LBB6_35: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 8\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:404 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:424 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:396 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 9\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:388 ; 8-byte Folded Spill\n\ts_branch .LBB6_30\n.LBB6_36: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 10\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:452 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:448 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:440 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:496 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:492 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:484 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:476 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:468 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 12\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_38\n; %bb.37: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:492 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 13\n\tv_writelane_b32 v34, s0, 14\n\tscratch_store_b64 off, v[2:3], s33 offset:512 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:504 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 15\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_43\n\ts_branch .LBB6_40\n.LBB6_38: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 12\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 16\n\tscratch_load_b64 v[0:1], off, s33 offset:476 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:468 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:532 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:528 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:520 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 17\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_44\n; %bb.39: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:484 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:492 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:532 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:528 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:520 ; 8-byte Folded Spill\n\ts_branch .LBB6_44\n.LBB6_40: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 14\n\tv_readlane_b32 s2, v34, 13\n\tscratch_load_b64 v[4:5], off, s33 offset:512 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:492 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:484 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 13\n\tv_writelane_b32 v34, s1, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:512 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:540 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 18\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_40\n; %bb.41: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 18\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.42: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:540 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:504 ; 8-byte Folded Spill\n.LBB6_43: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:484 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:504 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:476 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 16\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:468 ; 8-byte Folded Spill\n\ts_branch .LBB6_38\n.LBB6_44: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 17\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:532 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:528 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:520 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:576 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:572 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:564 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:556 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:548 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_46\n; %bb.45: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:572 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 20\n\tv_writelane_b32 v34, s0, 21\n\tscratch_store_b64 off, v[2:3], s33 offset:592 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:584 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 22\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_51\n\ts_branch .LBB6_48\n.LBB6_46: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 19\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 23\n\tscratch_load_b64 v[0:1], off, s33 offset:556 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:548 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:612 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:608 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:600 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 24\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_52\n; %bb.47: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:564 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:572 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:612 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:608 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:600 ; 8-byte Folded Spill\n\ts_branch .LBB6_52\n.LBB6_48: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 21\n\tv_readlane_b32 s2, v34, 20\n\tscratch_load_b64 v[4:5], off, s33 offset:592 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:572 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:564 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 20\n\tv_writelane_b32 v34, s1, 21\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:592 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:620 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 25\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_48\n; %bb.49: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 25\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.50: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:620 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:584 ; 8-byte Folded Spill\n.LBB6_51: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:564 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:584 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:556 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 23\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:548 ; 8-byte Folded Spill\n\ts_branch .LBB6_46\n.LBB6_52: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 24\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:612 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:608 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:600 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:648 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:644 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:636 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s33 offset:628 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 26\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_54\n; %bb.53: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:644 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 27\n\tv_writelane_b32 v34, s0, 28\n\tscratch_store_b64 off, v[2:3], s33 offset:664 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:656 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 29\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_59\n\ts_branch .LBB6_56\n.LBB6_54: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 26\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:628 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:672 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 30\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_60\n; %bb.55: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[2:3], off, s33 offset:636 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tflat_load_u8 v0, v[2:3]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v4, v[2:3] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v5, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v7, v1\n\tv_mov_b32_e32 v4, v6\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v5\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v4\n\tflat_load_u8 v4, v[2:3] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v8, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v4\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v10, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or3_b32 v4, v4, v5, v10\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v5, v8\n\tv_mov_b32_e32 v1, v6\n\tv_or3_b32 v0, v0, v1, v5\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v4, s1, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[6:7], s2, v[4:5]\n\tflat_load_u8 v4, v[2:3] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v4, s1, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[8:9], s0, v[4:5]\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v10, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or3_b32 v4, v4, v5, v10\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v5, v8\n\tv_mov_b32_e32 v1, v6\n\tv_or3_b32 v0, v0, v1, v5\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:6\n\tv_mov_b32_e32 v6, 0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[4:5], s0, v[4:5]\n\tflat_load_u8 v2, v[2:3] offset:7\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v6\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[6:7], s0, v[2:3]\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v8, v7\n\tv_mov_b32_e32 v3, v5\n\tv_or3_b32 v2, v2, v3, v8\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v3, v6\n\tv_mov_b32_e32 v1, v4\n\tv_or3_b32 v0, v0, v1, v3\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:672 ; 8-byte Folded Spill\n\ts_branch .LBB6_60\n.LBB6_56: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 28\n\tv_readlane_b32 s2, v34, 27\n\tscratch_load_b64 v[4:5], off, s33 offset:664 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:644 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:636 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 27\n\tv_writelane_b32 v34, s1, 28\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:664 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:680 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_56\n; %bb.57: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 31\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.58: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:680 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:656 ; 8-byte Folded Spill\n.LBB6_59: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:656 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:628 ; 8-byte Folded Spill\n\ts_branch .LBB6_54\n.LBB6_60: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v34, 30\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v33, 2\n\tv_readlane_b32 s14, v33, 3\n\tv_readlane_b32 s13, v33, 4\n\tv_readlane_b32 s12, v33, 5\n\tv_readlane_b32 s10, v33, 6\n\tv_readlane_b32 s11, v33, 7\n\tv_readlane_b32 s8, v33, 8\n\tv_readlane_b32 s9, v33, 9\n\tv_readlane_b32 s6, v33, 0\n\tv_readlane_b32 s7, v33, 1\n\tv_readlane_b32 s4, v33, 10\n\tv_readlane_b32 s5, v33, 11\n\tscratch_load_b64 v[0:1], off, s33 offset:156 ; 8-byte Folded Reload\n\tscratch_load_b32 v31, off, s33 offset:68 ; 4-byte Folded Reload\n\tscratch_load_b64 v[19:20], off, s33 offset:648 ; 8-byte Folded Reload\n\tscratch_load_b64 v[21:22], off, s33 offset:576 ; 8-byte Folded Reload\n\tscratch_load_b64 v[23:24], off, s33 offset:496 ; 8-byte Folded Reload\n\tscratch_load_b64 v[25:26], off, s33 offset:416 ; 8-byte Folded Reload\n\tscratch_load_b64 v[27:28], off, s33 offset:336 ; 8-byte Folded Reload\n\tscratch_load_b64 v[29:30], off, s33 offset:256 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:148 ; 8-byte Folded Reload\n\tscratch_load_b64 v[17:18], off, s33 offset:672 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(9)\n\tv_mov_b32_e32 v1, v0\n\ts_mov_b32 s0, 28\n\tv_mov_b32_e32 v0, 2\n\tv_lshl_add_u32 v1, v1, v0, s0\n\ts_mov_b32 s0, 0x1e0\n\tv_and_b32_e64 v5, v1, s0\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v1, 0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v1\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v1, v3\n\tv_and_b32_e64 v1, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v4, v2\n\tv_and_b32_e64 v7, v4, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v4, v6\n\tv_or_b32_e64 v1, v1, v4\n\tv_mov_b32_e32 v4, v7\n ; kill: def $vgpr5 killed $vgpr5 killed $vgpr5_vgpr6 killed $exec\n\tv_or_b32_e64 v4, v4, v5\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v1\n\tv_mov_b32_e32 v1, v4\n\ts_mov_b32 s0, 32\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\tv_writelane_b32 v34, s0, 0\n\tv_lshrrev_b64 v[2:3], s0, v[2:3]\n ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec\n\tv_lshrrev_b64 v[3:4], s0, v[29:30]\n\tv_mov_b32_e32 v4, v3\n\tv_lshrrev_b64 v[5:6], s0, v[27:28]\n\tv_mov_b32_e32 v6, v5\n\tv_lshrrev_b64 v[7:8], s0, v[25:26]\n\tv_mov_b32_e32 v8, v7\n\tv_lshrrev_b64 v[9:10], s0, v[23:24]\n\tv_mov_b32_e32 v10, v9\n\tv_lshrrev_b64 v[11:12], s0, v[21:22]\n\tv_mov_b32_e32 v12, v11\n\tv_lshrrev_b64 v[13:14], s0, v[19:20]\n\tv_mov_b32_e32 v14, v13\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[15:16], s0, v[17:18]\n\tv_mov_b32_e32 v16, v15\n\tv_mov_b32_e32 v3, v29\n\tv_mov_b32_e32 v5, v27\n\tv_mov_b32_e32 v7, v25\n\tv_mov_b32_e32 v9, v23\n\tv_mov_b32_e32 v11, v21\n\tv_mov_b32_e32 v13, v19\n\tv_mov_b32_e32 v15, v17\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b64 v[4:5], off, s33 offset:168 ; 8-byte Folded Reload\n\tscratch_load_b64 v[12:13], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b64 v[10:11], off, s33 offset:156 ; 8-byte Folded Reload\n\tv_readlane_b32 s1, v33, 15\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v7, v2\n\tv_mov_b32_e32 v6, v3\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v2, v7\n\tv_mov_b32_e32 v3, v6\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v6, v4\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v5, v11\n\tv_sub_co_u32 v6, s0, v6, v7\n\tv_sub_co_ci_u32_e64 v4, s0, v4, v5, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v4\n\tv_mov_b32_e32 v4, v12\n\tv_mov_b32_e32 v9, v10\n\tv_mov_b32_e32 v5, v13\n\tv_mov_b32_e32 v8, v11\n\tv_add_co_u32 v4, s0, v4, v9\n\tv_add_co_ci_u32_e64 v8, s0, v5, v8, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v8\n\ts_mov_b64 s[2:3], 0\n\tv_cmp_eq_u64_e64 s0, v[6:7], s[2:3]\n\ts_or_b32 s0, s0, s1\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v33, s1, 13\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[6:7], s33 offset:116 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[4:5], s33 offset:108 ; 8-byte Folded Spill\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v6, v2\n\tv_mov_b32_e32 v5, v1\n\tv_mov_b32_e32 v4, v0\n\tscratch_store_b128 off, v[4:7], s33 offset:92 ; 16-byte Folded Spill\n\tscratch_store_b128 off, v[0:3], s33 offset:688 ; 16-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:8 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_4\n; %bb.61:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:8 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.62:\n\tscratch_load_b128 v[0:3], off, s33 offset:688 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:12 ; 16-byte Folded Spill\n\ts_branch .LBB6_3\n.LBB6_63:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 14\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b128 v[3:6], off, s33 offset:72 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v0, v3\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v32, 0\n\tv_readlane_b32 s31, v32, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v32, off, s33 offset:704 ; 4-byte Folded Reload\n\tscratch_load_b32 v33, off, s33 offset:708 ; 4-byte Folded Reload\n\tscratch_load_b32 v34, off, s33 offset:712 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xfffffd30\n\ts_mov_b32 s33, s20\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end6:\n\t.size\t__ockl_fprintf_append_string_n, .Lfunc_end6-__ockl_fprintf_append_string_n\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 11984\n; NumSgprs: 36\n; NumVgprs: 35\n; ScratchSize: 1120\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_append_args\n\t.type\t__ockl_fprintf_append_args,@function\n__ockl_fprintf_append_args: ; @__ockl_fprintf_append_args\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s19, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v28, s33 offset:8 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v29, s33 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 32\n\tv_writelane_b32 v28, s30, 0\n\tv_writelane_b32 v28, s31, 1\n\tscratch_store_b32 off, v17, s33 offset:4 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v17, v2\n\tv_mov_b32_e32 v18, v0\n\tscratch_load_b32 v0, off, s33 offset:4 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v15\n ; kill: def $vgpr20 killed $vgpr16 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v13\n ; kill: def $vgpr20 killed $vgpr14 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v11\n ; kill: def $vgpr20 killed $vgpr12 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v9\n ; kill: def $vgpr20 killed $vgpr10 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v7\n ; kill: def $vgpr20 killed $vgpr8 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v5\n ; kill: def $vgpr20 killed $vgpr6 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v3\n ; kill: def $vgpr20 killed $vgpr4 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr18 killed $vgpr18 def $vgpr18_vgpr19 killed $exec\n\tv_mov_b32_e32 v19, v1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s0, v0, s0\n\tv_mov_b32_e32 v1, v19\n\ts_mov_b64 s[2:3], 2\n\ts_mov_b32 s1, s3\n\tv_or_b32_e64 v0, v1, s1\n\tv_mov_b32_e32 v2, v18\n\ts_mov_b32 s1, s2\n\tv_or_b32_e64 v18, v2, s1\n ; kill: def $vgpr18 killed $vgpr18 def $vgpr18_vgpr19 killed $exec\n\tv_mov_b32_e32 v19, v0\n\tv_mov_b32_e32 v0, v19\n\tv_cndmask_b32_e64 v0, v0, v1, s0\n\tv_mov_b32_e32 v1, v18\n\tv_cndmask_b32_e64 v1, v1, v2, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v0, v2\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\tv_and_b32_e64 v0, v0, s2\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_and_b32_e64 v1, v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\tv_mov_b32_e32 v18, v0\n\ts_mov_b32 s0, 5\n\tv_lshlrev_b64 v[17:18], s0, v[17:18]\n\tv_mov_b32_e32 v0, v2\n\tv_mov_b32_e32 v19, v18\n\tv_or_b32_e64 v0, v0, v19\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v17\n\tv_or_b32_e64 v17, v1, v2\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\tv_mov_b32_e32 v18, v0\n\tv_mov_b32_e32 v1, v17\n\ts_mov_b32 s0, 32\n ; implicit-def: $vgpr29 : SGPR spill to VGPR lane\n\tv_writelane_b32 v29, s0, 0\n\tv_lshrrev_b64 v[17:18], s0, v[17:18]\n\tv_mov_b32_e32 v2, v17\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v29, 0\n\tscratch_store_b32 off, v1, s33 ; 4-byte Folded Spill\n ; kill: def $vgpr1 killed $vgpr3 killed $exec\n\tscratch_load_b32 v3, off, s33 ; 4-byte Folded Reload\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v1, s1\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v3\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v28, 0\n\tv_readlane_b32 s31, v28, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v28, off, s33 offset:8 ; 4-byte Folded Reload\n\tscratch_load_b32 v29, off, s33 offset:12 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xffffffe0\n\ts_mov_b32 s33, s19\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end7:\n\t.size\t__ockl_fprintf_append_args, .Lfunc_end7-__ockl_fprintf_append_args\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 452\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 432\n; MemoryBound: 0\n\t.text\n\t.hidden\t__assert_fail ; -- Begin function __assert_fail\n\t.weak\t__assert_fail\n\t.p2align\t2\n\t.type\t__assert_fail,@function\n__assert_fail: ; @__assert_fail\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s27, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v35, s33 offset:176 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v36, s33 offset:180 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v37, s33 offset:184 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xc0\n\tv_writelane_b32 v35, s30, 0\n\tv_writelane_b32 v35, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:168 ; 4-byte Folded Spill\n ; implicit-def: $vgpr37 : SGPR spill to VGPR lane\n\tv_writelane_b32 v37, s6, 0\n\tv_writelane_b32 v37, s7, 1\n\tscratch_store_b32 off, v5, s33 offset:164 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v3, s33 offset:160 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v5, v2\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v7, v0\n\tscratch_load_b32 v0, off, s33 offset:160 ; 4-byte Folded Reload\n\tv_writelane_b32 v37, s15, 2\n\tv_writelane_b32 v37, s14, 3\n\tv_writelane_b32 v37, s13, 4\n\tv_writelane_b32 v37, s12, 5\n\tv_writelane_b32 v37, s10, 6\n\tv_writelane_b32 v37, s11, 7\n\tv_writelane_b32 v37, s8, 8\n\tv_writelane_b32 v37, s9, 9\n\tv_writelane_b32 v37, s4, 10\n\tv_writelane_b32 v37, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v6, v0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b64 s[0:1], src_private_base\n\ts_mov_b32 s2, 32\n\ts_lshr_b64 s[0:1], s[0:1], s2\n\ts_mov_b32 s24, s0\n\tv_writelane_b32 v37, s24, 12\n\ts_mov_b32 s20, s33\n ; kill: def $sgpr20 killed $sgpr20 def $sgpr20_sgpr21\n\ts_mov_b32 s21, s24\n\ts_mov_b64 s[0:1], s[20:21]\n\tv_writelane_b32 v37, s0, 13\n\tv_writelane_b32 v37, s1, 14\n\ts_add_i32 s0, s33, 8\n\ts_mov_b32 s18, s0\n ; kill: def $sgpr18 killed $sgpr18 def $sgpr18_sgpr19\n\ts_mov_b32 s19, s24\n\ts_mov_b64 s[0:1], s[18:19]\n\tv_writelane_b32 v37, s0, 15\n\tv_writelane_b32 v37, s1, 16\n\ts_add_i32 s0, s33, 16\n\ts_mov_b32 s2, s0\n ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3\n\ts_mov_b32 s3, s24\n\ts_mov_b64 s[0:1], s[2:3]\n\tv_writelane_b32 v37, s0, 17\n\tv_writelane_b32 v37, s1, 18\n\ts_add_i32 s1, s33, 24\n\ts_mov_b32 s0, s1\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s24\n\ts_mov_b64 s[16:17], s[0:1]\n\tv_writelane_b32 v37, s16, 19\n\tv_writelane_b32 v37, s17, 20\n\ts_add_i32 s17, s33, 32\n\ts_mov_b32 s16, s17\n ; kill: def $sgpr16 killed $sgpr16 def $sgpr16_sgpr17\n\ts_mov_b32 s17, s24\n\tv_writelane_b32 v37, s16, 21\n\tv_writelane_b32 v37, s17, 22\n\ts_mov_b64 s[22:23], s[16:17]\n\tv_writelane_b32 v37, s22, 23\n\tv_writelane_b32 v37, s23, 24\n\ts_add_i32 s23, s33, 0x50\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v37, s22, 25\n\tv_writelane_b32 v37, s23, 26\n\tv_writelane_b32 v37, s22, 27\n\tv_writelane_b32 v37, s23, 28\n\ts_add_i32 s23, s33, 0x58\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v37, s22, 29\n\tv_writelane_b32 v37, s23, 30\n ; implicit-def: $vgpr36 : SGPR spill to VGPR lane\n\tv_writelane_b32 v37, s22, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:148 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_writelane_b32 v36, s23, 0\n\ts_add_i32 s23, s33, 0x60\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 1\n\tv_writelane_b32 v36, s23, 2\n\ts_add_i32 s23, s33, 0x68\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 3\n\tv_writelane_b32 v36, s23, 4\n\ts_add_i32 s23, s33, 0x70\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 5\n\tv_writelane_b32 v36, s23, 6\n\ts_add_i32 s23, s33, 0x78\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 7\n\tv_writelane_b32 v36, s23, 8\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_mov_b32_e32 v0, s20\n\tv_mov_b32_e32 v1, s21\n\tflat_store_b64 v[0:1], v[7:8]\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tflat_store_b64 v[0:1], v[5:6]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b32 v[0:1], v4\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, s33 offset:156 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+35\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+43\n\tglobal_load_b128 v[0:3], v0, s[0:1]\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:128\n\tscratch_load_b64 v[0:1], off, s33 offset:136\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_d16_hi_b8 v[3:4], v2 offset:45\n\ts_mov_b32 s1, 24\n\tv_lshrrev_b32_e64 v5, s1, v2\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v5 offset:46\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v2 offset:43\n\ts_mov_b32 s0, 8\n\tv_lshrrev_b32_e64 v4, s0, v2\n\tv_mov_b32_e32 v2, s16\n\tv_mov_b32_e32 v3, s17\n\tflat_store_b8 v[2:3], v4 offset:44\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_d16_hi_b8 v[1:2], v0 offset:41\n\tv_lshrrev_b32_e64 v3, s1, v0\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v3 offset:42\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v0 offset:39\n\tv_lshrrev_b32_e64 v2, s0, v0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b8 v[0:1], v2 offset:40\n\tscratch_load_b64 v[0:1], off, s33 offset:128\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_d16_hi_b8 v[3:4], v2 offset:37\n\tv_lshrrev_b32_e64 v5, s1, v2\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v5 offset:38\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v2 offset:35\n\tv_lshrrev_b32_e64 v4, s0, v2\n\tv_mov_b32_e32 v2, s16\n\tv_mov_b32_e32 v3, s17\n\tflat_store_b8 v[2:3], v4 offset:36\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_d16_hi_b8 v[1:2], v0 offset:33\n\tv_lshrrev_b32_e64 v3, s1, v0\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v3 offset:34\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v0 offset:31\n\tv_lshrrev_b32_e64 v2, s0, v0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b8 v[0:1], v2 offset:32\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+20\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+28\n\ts_load_b128 s[0:3], s[0:1], 0x0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v5, s3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b128 v[0:1], v[2:5] offset:16\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+4\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+12\n\ts_load_b128 s[0:3], s[0:1], 0x0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v5, s3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b128 v[0:1], v[2:5]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_stderr_begin@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_stderr_begin@rel32@hi+12\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v2, off, s33 offset:156 ; 4-byte Folded Reload\n\tv_readlane_b32 s2, v37, 25\n\tv_readlane_b32 s3, v37, 26\n\tv_readlane_b32 s0, v37, 29\n\tv_readlane_b32 s1, v37, 30\n\tv_mov_b32_e32 v3, v0\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b64 v[0:1], v[3:4]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0)\n\tflat_store_b32 v[0:1], v2\n; %bb.1:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 23\n\tv_readlane_b32 s1, v36, 24\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s3, v37, 2\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 9\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_2: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s3, v37, 2\n\tv_readlane_b32 s0, v37, 10\n\tv_readlane_b32 s1, v37, 9\n\tv_writelane_b32 v37, s1, 11\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 12\n\tv_writelane_b32 v37, s0, 13\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 14\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_4\n; %bb.3: ; in Loop: Header=BB8_2 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 12\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 13\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_4: ; in Loop: Header=BB8_2 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 14\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 11\n\tv_readlane_b32 s1, v37, 13\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 10\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 9\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 15\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_2\n; %bb.5:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.6:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 23\n\tv_readlane_b32 s3, v36, 24\n\tv_readlane_b32 s4, v37, 1\n\tv_readlane_b32 s5, v37, 2\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, s2\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.7:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 23\n\tv_readlane_b32 s1, v37, 24\n\tv_readlane_b32 s2, v37, 31\n\tv_readlane_b32 s3, v36, 0\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v5, v4\n\tv_mov_b32_e32 v6, v0\n\ts_mov_b32 s3, 32\n\ts_lshr_b64 s[16:17], s[0:1], s3\n\ts_mov_b32 s2, s16\n\tv_lshrrev_b64 v[0:1], s3, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[5:6], s3, v[5:6]\n ; kill: def $vgpr5 killed $vgpr5 killed $vgpr5_vgpr6 killed $exec\n\ts_mov_b32 s3, s0\n\tv_mov_b32_e32 v0, v2\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v2, s3\n\tv_mov_b32_e32 v3, s2\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.8:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 3\n\tv_readlane_b32 s1, v37, 4\n\tv_readlane_b32 s2, v36, 15\n\tv_readlane_b32 s3, v36, 16\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 16\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_9: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 3\n\tv_readlane_b32 s3, v37, 4\n\tv_readlane_b32 s0, v37, 17\n\tv_readlane_b32 s1, v37, 16\n\tv_writelane_b32 v37, s1, 18\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 19\n\tv_writelane_b32 v37, s0, 20\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 21\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_11\n; %bb.10: ; in Loop: Header=BB8_9 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 19\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 20\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_11: ; in Loop: Header=BB8_9 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 18\n\tv_readlane_b32 s1, v37, 20\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 17\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 16\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 22\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_9\n; %bb.12:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.13:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 15\n\tv_readlane_b32 s3, v36, 16\n\tv_readlane_b32 s4, v37, 3\n\tv_readlane_b32 s5, v37, 4\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.14:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 15\n\tv_readlane_b32 s3, v37, 16\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_writelane_b32 v36, s0, 23\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\tscratch_store_b32 off, v6, s33 offset:172 ; 4-byte Folded Spill\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tscratch_load_b32 v17, off, s33 offset:172 ; 4-byte Folded Reload\n\tv_readlane_b32 s2, v37, 17\n\tv_readlane_b32 s3, v37, 18\n\tv_readlane_b32 s0, v36, 23\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v3, v[0:1]\n\ts_waitcnt vmcnt(1) lgkmcnt(1)\n\tv_lshrrev_b64 v[0:1], s0, v[4:5]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v4\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_args@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_args@rel32@hi+12\n\tv_mov_b32_e32 v2, 1\n\tv_mov_b32_e32 v4, v17\n\tv_mov_b32_e32 v5, v17\n\tv_mov_b32_e32 v6, v17\n\tv_mov_b32_e32 v7, v17\n\tv_mov_b32_e32 v8, v17\n\tv_mov_b32_e32 v9, v17\n\tv_mov_b32_e32 v10, v17\n\tv_mov_b32_e32 v11, v17\n\tv_mov_b32_e32 v12, v17\n\tv_mov_b32_e32 v13, v17\n\tv_mov_b32_e32 v14, v17\n\tv_mov_b32_e32 v15, v17\n\tv_mov_b32_e32 v16, v17\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.15:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 5\n\tv_readlane_b32 s1, v37, 6\n\tv_readlane_b32 s2, v36, 19\n\tv_readlane_b32 s3, v36, 20\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 24\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_16: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 5\n\tv_readlane_b32 s3, v37, 6\n\tv_readlane_b32 s0, v37, 25\n\tv_readlane_b32 s1, v37, 24\n\tv_writelane_b32 v37, s1, 26\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 27\n\tv_writelane_b32 v37, s0, 28\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 29\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_18\n; %bb.17: ; in Loop: Header=BB8_16 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 27\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 28\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_18: ; in Loop: Header=BB8_16 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 26\n\tv_readlane_b32 s1, v37, 28\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 25\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 24\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 30\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_16\n; %bb.19:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 30\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.20:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 19\n\tv_readlane_b32 s3, v36, 20\n\tv_readlane_b32 s4, v37, 5\n\tv_readlane_b32 s5, v37, 6\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.21:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 19\n\tv_readlane_b32 s3, v37, 20\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.22:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 7\n\tv_readlane_b32 s1, v37, 8\n\tv_readlane_b32 s2, v36, 13\n\tv_readlane_b32 s3, v36, 14\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_23: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v36, 7\n\tv_readlane_b32 s3, v36, 8\n ; implicit-def: $vgpr37 : SGPR spill to VGPR lane\n\tv_readlane_b32 s0, v37, 0\n\tv_readlane_b32 s1, v36, 31\n\tv_writelane_b32 v37, s1, 1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 2\n\tv_writelane_b32 v37, s0, 3\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 4\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_25\n; %bb.24: ; in Loop: Header=BB8_23 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 2\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 3\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_25: ; in Loop: Header=BB8_23 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s1, v37, 3\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 0\n\ts_mov_b32 s1, s0\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v36, s1, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 5\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_23\n; %bb.26:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 5\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.27:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 13\n\tv_readlane_b32 s3, v36, 14\n\tv_readlane_b32 s4, v37, 7\n\tv_readlane_b32 s5, v37, 8\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.28:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 13\n\tv_readlane_b32 s3, v37, 14\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 1\n\ts_swappc_b64 s[30:31], s[0:1]\n\ts_cbranch_execnz .LBB8_30\n; %bb.29:\n\tv_readlane_b32 s30, v35, 0\n\tv_readlane_b32 s31, v35, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v35, off, s33 offset:176 ; 4-byte Folded Reload\n\tscratch_load_b32 v36, off, s33 offset:180 ; 4-byte Folded Reload\n\tscratch_load_b32 v37, off, s33 offset:184 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xffffff40\n\ts_mov_b32 s33, s27\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.LBB8_30:\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB8_31: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB8_31\n.Lfunc_end8:\n\t.size\t__assert_fail, .Lfunc_end8-__assert_fail\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 6148\n; NumSgprs: 36\n; NumVgprs: 38\n; ScratchSize: 1312\n; MemoryBound: 0\n\t.text\n\t.hidden\t__assertfail ; -- Begin function __assertfail\n\t.weak\t__assertfail\n\t.p2align\t2\n\t.type\t__assertfail,@function\n__assertfail: ; @__assertfail\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_cbranch_execnz .LBB9_2\n; %bb.1:\n\ts_setpc_b64 s[30:31]\n.LBB9_2:\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB9_3: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB9_3\n.Lfunc_end9:\n\t.size\t__assertfail, .Lfunc_end9-__assertfail\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 64\n; NumSgprs: 32\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_get_group_id\n\t.type\t__ockl_get_group_id,@function\n__ockl_get_group_id: ; @__ockl_get_group_id\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v2, s32 offset:32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill\n ; implicit-def: $vgpr2 : SGPR spill to VGPR lane\n\tv_writelane_b32 v2, s14, 0\n\tv_writelane_b32 v2, s13, 1\n\tv_writelane_b32 v2, s12, 2\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n; %bb.1:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v2, s1, 3\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_4\n; %bb.2:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v2, s1, 4\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_7\n; %bb.3:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 5\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_10\n\ts_branch .LBB10_9\n.LBB10_4:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 3\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 6\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB10_13\n; %bb.5:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 7\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_12\n; %bb.6:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 2\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_branch .LBB10_12\n.LBB10_7:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 4\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:12 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 8\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB10_11\n; %bb.8:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 1\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_branch .LBB10_11\n.LBB10_9:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 0\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n.LBB10_10:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 5\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:16 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_branch .LBB10_7\n.LBB10_11:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 8\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill\n\ts_branch .LBB10_4\n.LBB10_12:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 7\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:24 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n.LBB10_13:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 6\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:20 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v1, 0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v2, off, s32 offset:32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end10:\n\t.size\t__ockl_get_group_id, .Lfunc_end10-__ockl_get_group_id\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 988\n; NumSgprs: 33\n; NumVgprs: 3\n; ScratchSize: 40\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_get_local_size\n\t.type\t__ockl_get_local_size,@function\n__ockl_get_local_size: ; @__ockl_get_local_size\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v4, s32 offset:104 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill\n ; implicit-def: $vgpr4 : SGPR spill to VGPR lane\n\tv_writelane_b32 v4, s14, 0\n\tv_writelane_b32 v4, s13, 1\n\tv_writelane_b32 v4, s12, 2\n\tv_writelane_b32 v4, s8, 3\n\tv_writelane_b32 v4, s9, 4\n\tv_writelane_b32 v4, s4, 5\n\tv_writelane_b32 v4, s5, 6\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n; %bb.1:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:8 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v4, s1, 7\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_4\n; %bb.2:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:16 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v4, s1, 8\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_10\n; %bb.3:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 1\n\tv_mov_b32_e32 v0, 1\n\tv_mov_b32_e32 v1, 0\n\tscratch_store_b64 off, v[0:1], s32 offset:24 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v4, s0, 9\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_20\n\ts_branch .LBB11_15\n.LBB11_4:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 7\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:8 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:32 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v4, s0, 10\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB11_25\n; %bb.5:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 1\n\tv_mov_b32_e32 v0, 1\n\tv_mov_b32_e32 v1, 0\n\tscratch_store_b64 off, v[0:1], s32 offset:40 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v4, s0, 11\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_24\n; %bb.6:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n ; implicit-def: $sgpr2_sgpr3\n\ts_mov_b32 s4, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s4\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:48 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v4, s0, 12\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB11_9\n.LBB11_7:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 12\n\tscratch_load_b64 v[0:1], off, s32 offset:48 ; 8-byte Folded Reload\n\tv_cndmask_b32_e64 v2, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v2, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n ; kill: def $vgpr0_vgpr1 killed $vgpr0_vgpr1 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:56 ; 8-byte Folded Spill\n\ts_cbranch_vccnz .LBB11_23\n; %bb.8:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v4, 2\n\tv_readlane_b32 s2, v4, 5\n\tv_readlane_b32 s3, v4, 6\n\tv_mov_b32_e32 v0, 0\n\tglobal_load_u16 v1, v0, s[2:3] offset:4\n\ts_load_b32 s0, s[2:3], 0xc\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v0, s1, v1\n\ts_waitcnt lgkmcnt(0)\n\tv_sub_nc_u32_e64 v0, s0, v0\n ; implicit-def: $sgpr0\n\tv_min_u32_e64 v0, v0, v1\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr0_sgpr1\n\tscratch_store_b64 off, v[0:1], s32 offset:56 ; 8-byte Folded Spill\n\ts_branch .LBB11_23\n.LBB11_9:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 3\n\tv_readlane_b32 s1, v4, 4\n\tv_readlane_b32 s2, v4, 2\n\ts_load_b32 s3, s[0:1], 0x0\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_u32 s2, s3\n\ts_mov_b32 s3, 18\n\ts_mov_b32 s2, 12\n\ts_cselect_b32 s2, s2, s3\n\tv_mov_b32_e32 v0, s2\n\tglobal_load_u16 v0, v0, s[0:1]\n\ts_mov_b32 s0, 0xffff\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n ; implicit-def: $sgpr0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr2_sgpr3\n\tscratch_store_b64 off, v[0:1], s32 offset:48 ; 8-byte Folded Spill\n\tv_writelane_b32 v4, s0, 12\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB11_7\n.LBB11_10:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 8\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:16 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:64 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v4, s0, 13\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB11_22\n; %bb.11:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n ; implicit-def: $sgpr2_sgpr3\n\ts_mov_b32 s4, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s4\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:72 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v4, s0, 14\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB11_14\n.LBB11_12:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 14\n\tscratch_load_b64 v[0:1], off, s32 offset:72 ; 8-byte Folded Reload\n\tv_cndmask_b32_e64 v2, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v2, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n ; kill: def $vgpr0_vgpr1 killed $vgpr0_vgpr1 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:80 ; 8-byte Folded Spill\n\ts_cbranch_vccnz .LBB11_21\n; %bb.13:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v4, 1\n\tv_readlane_b32 s2, v4, 5\n\tv_readlane_b32 s3, v4, 6\n\tv_mov_b32_e32 v0, 0\n\tglobal_load_u16 v1, v0, s[2:3] offset:6\n\ts_load_b32 s0, s[2:3], 0x10\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v0, s1, v1\n\ts_waitcnt lgkmcnt(0)\n\tv_sub_nc_u32_e64 v0, s0, v0\n ; implicit-def: $sgpr0\n\tv_min_u32_e64 v0, v0, v1\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr0_sgpr1\n\tscratch_store_b64 off, v[0:1], s32 offset:80 ; 8-byte Folded Spill\n\ts_branch .LBB11_21\n.LBB11_14:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 3\n\tv_readlane_b32 s1, v4, 4\n\tv_readlane_b32 s2, v4, 1\n\ts_load_b32 s3, s[0:1], 0x4\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_u32 s2, s3\n\ts_mov_b32 s3, 20\n\ts_mov_b32 s2, 14\n\ts_cselect_b32 s2, s2, s3\n\tv_mov_b32_e32 v0, s2\n\tglobal_load_u16 v0, v0, s[0:1]\n\ts_mov_b32 s0, 0xffff\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n ; implicit-def: $sgpr0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr2_sgpr3\n\tscratch_store_b64 off, v[0:1], s32 offset:72 ; 8-byte Folded Spill\n\tv_writelane_b32 v4, s0, 14\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB11_12\n.LBB11_15:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n ; implicit-def: $sgpr2_sgpr3\n\ts_mov_b32 s4, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s4\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:88 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v4, s0, 15\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB11_18\n.LBB11_16:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 15\n\tscratch_load_b64 v[0:1], off, s32 offset:88 ; 8-byte Folded Reload\n\tv_cndmask_b32_e64 v2, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v2, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n ; kill: def $vgpr0_vgpr1 killed $vgpr0_vgpr1 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:96 ; 8-byte Folded Spill\n\ts_cbranch_vccnz .LBB11_19\n; %bb.17:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v4, 0\n\tv_readlane_b32 s2, v4, 5\n\tv_readlane_b32 s3, v4, 6\n\tv_mov_b32_e32 v0, 0\n\tglobal_load_u16 v1, v0, s[2:3] offset:8\n\ts_load_b32 s0, s[2:3], 0x14\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v0, s1, v1\n\ts_waitcnt lgkmcnt(0)\n\tv_sub_nc_u32_e64 v0, s0, v0\n ; implicit-def: $sgpr0\n\tv_min_u32_e64 v0, v0, v1\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr0_sgpr1\n\tscratch_store_b64 off, v[0:1], s32 offset:96 ; 8-byte Folded Spill\n\ts_branch .LBB11_19\n.LBB11_18:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 3\n\tv_readlane_b32 s1, v4, 4\n\tv_readlane_b32 s2, v4, 0\n\ts_load_b32 s3, s[0:1], 0x8\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_u32 s2, s3\n\ts_mov_b32 s3, 22\n\ts_mov_b32 s2, 16\n\ts_cselect_b32 s2, s2, s3\n\tv_mov_b32_e32 v0, s2\n\tglobal_load_u16 v0, v0, s[0:1]\n\ts_mov_b32 s0, 0xffff\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n ; implicit-def: $sgpr0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr2_sgpr3\n\tscratch_store_b64 off, v[0:1], s32 offset:88 ; 8-byte Folded Spill\n\tv_writelane_b32 v4, s0, 15\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB11_16\n.LBB11_19:\n\tscratch_load_b64 v[0:1], off, s32 offset:96 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:24 ; 8-byte Folded Spill\n.LBB11_20:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 9\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:24 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:16 ; 8-byte Folded Spill\n\ts_branch .LBB11_10\n.LBB11_21:\n\tscratch_load_b64 v[0:1], off, s32 offset:80 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:64 ; 8-byte Folded Spill\n.LBB11_22:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 13\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:64 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:8 ; 8-byte Folded Spill\n\ts_branch .LBB11_4\n.LBB11_23:\n\tscratch_load_b64 v[0:1], off, s32 offset:56 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:40 ; 8-byte Folded Spill\n.LBB11_24:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 11\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:40 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:32 ; 8-byte Folded Spill\n.LBB11_25:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 10\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[2:3], off, s32 offset:32 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 32\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[0:1], s0, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v2\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v4, off, s32 offset:104 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end11:\n\t.size\t__ockl_get_local_size, .Lfunc_end11-__ockl_get_local_size\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 2384\n; NumSgprs: 35\n; NumVgprs: 5\n; ScratchSize: 112\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_get_num_groups\n\t.type\t__ockl_get_num_groups,@function\n__ockl_get_num_groups: ; @__ockl_get_num_groups\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v5, s32 offset:44 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill\n ; implicit-def: $vgpr5 : SGPR spill to VGPR lane\n\tv_writelane_b32 v5, s8, 0\n\tv_writelane_b32 v5, s9, 1\n\tv_writelane_b32 v5, s4, 2\n\tv_writelane_b32 v5, s5, 3\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v5, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n; %bb.1:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v5, s1, 4\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v5, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_4\n; %bb.2:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v5, s1, 5\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v5, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_12\n; %bb.3:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, 1\n\tv_mov_b32_e32 v0, 1\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v5, s0, 6\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v5, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_23\n\ts_branch .LBB12_19\n.LBB12_4:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v5, 4\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v5, s0, 7\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v5, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB12_25\n; %bb.5:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, 1\n\tv_mov_b32_e32 v0, 1\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v5, s0, 8\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v5, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_10\n; %bb.6:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n\ts_mov_b32 s2, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s2\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v5, s0, 9\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v5, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB12_9\n.LBB12_7:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v5, 9\n\tv_readlane_b32 s1, v5, 10\n\tv_readlane_b32 s0, v5, 11\n\tv_cndmask_b32_e64 v0, 0, 1, s2\n\ts_mov_b32 s2, 1\n ; implicit-def: $sgpr3\n\tv_cmp_ne_u32_e64 s2, v0, s2\n\ts_and_b32 vcc_lo, exec_lo, s2\n\tv_mov_b32_e32 v0, s1\n\tv_writelane_b32 v5, s0, 12\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v5, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_cbranch_vccnz .LBB12_11\n; %bb.8:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v5, 2\n\tv_readlane_b32 s3, v5, 3\n\tv_mov_b32_e32 v0, 0\n\ts_load_b32 s0, s[2:3], 0xc\n\tglobal_load_u16 v1, v0, s[2:3] offset:4\n\ts_mov_b32 s1, 0\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_sub_nc_u32_e64 v2, s1, v1\n\tv_cvt_f32_u32_e32 v0, v1\n\tv_rcp_iflag_f32_e32 v0, v0\n\ts_waitcnt_depctr 0xfff\n\tv_mul_f32_e32 v0, 0x4f7ffffe, v0\n\tv_cvt_u32_f32_e32 v0, v0\n ; implicit-def: $sgpr1\n\tv_mul_lo_u32 v2, v2, v0\n ; implicit-def: $sgpr1\n\tv_mul_hi_u32 v2, v0, v2\n ; implicit-def: $sgpr1\n\tv_add_nc_u32_e64 v0, v0, v2\n\ts_waitcnt lgkmcnt(0)\n\tv_mul_hi_u32 v0, s0, v0\n\ts_mov_b32 s1, 1\n\tv_add_nc_u32_e64 v2, v0, s1\n ; implicit-def: $sgpr2\n\tv_mul_lo_u32 v3, v0, v1\n\tv_sub_nc_u32_e64 v3, s0, v3\n ; implicit-def: $sgpr2\n\tv_sub_nc_u32_e64 v4, v3, v1\n ; implicit-def: $sgpr2\n\tv_cmp_ge_u32_e64 s2, v3, v1\n\tv_cndmask_b32_e64 v3, v3, v4, s2\n\tv_cndmask_b32_e64 v0, v0, v2, s2\n\tv_add_nc_u32_e64 v2, v0, s1\n ; implicit-def: $sgpr1\n\tv_cmp_ge_u32_e64 s1, v3, v1\n\tv_cndmask_b32_e64 v0, v0, v2, s1\n ; implicit-def: $sgpr1\n\tv_mul_lo_u32 v1, v0, v1\n\tv_cmp_gt_u32_e64 s0, s0, v1\n\tv_writelane_b32 v5, s0, 12\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v5, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_branch .LBB12_11\n.LBB12_9:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v5, 0\n\tv_readlane_b32 s1, v5, 1\n\tv_mov_b32_e32 v0, 0\n\ts_load_b32 s2, s[0:1], 0x0\n\tglobal_load_u16 v0, v0, s[0:1] offset:18\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s0\n\ts_mov_b32 s0, 0\n\ts_waitcnt lgkmcnt(0)\n\tv_writelane_b32 v5, s2, 10\n\tv_writelane_b32 v5, s1, 11\n\tv_writelane_b32 v5, s0, 9\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v5, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB12_7\n.LBB12_10:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v5, 8\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:24 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n\ts_branch .LBB12_25\n.LBB12_11:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v5, 12\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n\tv_cndmask_b32_e64 v1, 0, 1, s0\n ; implicit-def: $sgpr0\n\ts_waitcnt vmcnt(0)\n\tv_add_nc_u32_e64 v0, v0, v1\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_branch .LBB12_10\n.LBB12_12:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v5, 5\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:12 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:32 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v5, s0, 13\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v5, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB12_17\n; %bb.13:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n\ts_mov_b32 s2, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s2\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v5, s0, 14\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v5, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB12_16\n.LBB12_14:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v5, 14\n\tv_readlane_b32 s1, v5, 15\n\tv_readlane_b32 s0, v5, 16\n\tv_cndmask_b32_e64 v0, 0, 1, s2\n\ts_mov_b32 s2, 1\n ; implicit-def: $sgpr3\n\tv_cmp_ne_u32_e64 s2, v0, s2\n\ts_and_b32 vcc_lo, exec_lo, s2\n\tv_mov_b32_e32 v0, s1\n\tv_writelane_b32 v5, s0, 17\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v5, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\tscratch_store_b32 off, v0, s32 offset:36 ; 4-byte Folded Spill\n\ts_cbranch_vccnz .LBB12_18\n; %bb.15:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v5, 2\n\tv_readlane_b32 s3, v5, 3\n\tv_mov_b32_e32 v0, 0\n\ts_load_b32 s0, s[2:3], 0x10\n\tglobal_load_u16 v1, v0, s[2:3] offset:6\n\ts_mov_b32 s1, 0\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_sub_nc_u32_e64 v2, s1, v1\n\tv_cvt_f32_u32_e32 v0, v1\n\tv_rcp_iflag_f32_e32 v0, v0\n\ts_waitcnt_depctr 0xfff\n\tv_mul_f32_e32 v0, 0x4f7ffffe, v0\n\tv_cvt_u32_f32_e32 v0, v0\n ; implicit-def: $sgpr1\n\tv_mul_lo_u32 v2, v2, v0\n ; implicit-def: $sgpr1\n\tv_mul_hi_u32 v2, v0, v2\n ; implicit-def: $sgpr1\n\tv_add_nc_u32_e64 v0, v0, v2\n\ts_waitcnt lgkmcnt(0)\n\tv_mul_hi_u32 v0, s0, v0\n\ts_mov_b32 s1, 1\n\tv_add_nc_u32_e64 v2, v0, s1\n ; implicit-def: $sgpr2\n\tv_mul_lo_u32 v3, v0, v1\n\tv_sub_nc_u32_e64 v3, s0, v3\n ; implicit-def: $sgpr2\n\tv_sub_nc_u32_e64 v4, v3, v1\n ; implicit-def: $sgpr2\n\tv_cmp_ge_u32_e64 s2, v3, v1\n\tv_cndmask_b32_e64 v3, v3, v4, s2\n\tv_cndmask_b32_e64 v0, v0, v2, s2\n\tv_add_nc_u32_e64 v2, v0, s1\n ; implicit-def: $sgpr1\n\tv_cmp_ge_u32_e64 s1, v3, v1\n\tv_cndmask_b32_e64 v0, v0, v2, s1\n ; implicit-def: $sgpr1\n\tv_mul_lo_u32 v1, v0, v1\n\tv_cmp_gt_u32_e64 s0, s0, v1\n\tv_writelane_b32 v5, s0, 17\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v5, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\tscratch_store_b32 off, v0, s32 offset:36 ; 4-byte Folded Spill\n\ts_branch .LBB12_18\n.LBB12_16:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v5, 0\n\tv_readlane_b32 s1, v5, 1\n\tv_mov_b32_e32 v0, 0\n\ts_load_b32 s2, s[0:1], 0x4\n\tglobal_load_u16 v0, v0, s[0:1] offset:20\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s0\n\ts_mov_b32 s0, 0\n\ts_waitcnt lgkmcnt(0)\n\tv_writelane_b32 v5, s2, 15\n\tv_writelane_b32 v5, s1, 16\n\tv_writelane_b32 v5, s0, 14\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v5, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB12_14\n.LBB12_17:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v5, 13\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:32 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill\n\ts_branch .LBB12_4\n.LBB12_18:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v5, 17\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\tv_cndmask_b32_e64 v1, 0, 1, s0\n ; implicit-def: $sgpr0\n\ts_waitcnt vmcnt(0)\n\tv_add_nc_u32_e64 v0, v0, v1\n\tscratch_store_b32 off, v0, s32 offset:32 ; 4-byte Folded Spill\n\ts_branch .LBB12_17\n.LBB12_19:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n\ts_mov_b32 s2, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s2\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v5, s0, 18\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v5, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB12_22\n.LBB12_20:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v5, 18\n\tv_readlane_b32 s1, v5, 19\n\tv_readlane_b32 s0, v5, 20\n\tv_cndmask_b32_e64 v0, 0, 1, s2\n\ts_mov_b32 s2, 1\n ; implicit-def: $sgpr3\n\tv_cmp_ne_u32_e64 s2, v0, s2\n\ts_and_b32 vcc_lo, exec_lo, s2\n\tv_mov_b32_e32 v0, s1\n\tv_writelane_b32 v5, s0, 21\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v5, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\tscratch_store_b32 off, v0, s32 offset:40 ; 4-byte Folded Spill\n\ts_cbranch_vccnz .LBB12_24\n; %bb.21:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v5, 2\n\tv_readlane_b32 s3, v5, 3\n\tv_mov_b32_e32 v0, 0\n\ts_load_b32 s0, s[2:3], 0x14\n\tglobal_load_u16 v1, v0, s[2:3] offset:8\n\ts_mov_b32 s1, 0\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_sub_nc_u32_e64 v2, s1, v1\n\tv_cvt_f32_u32_e32 v0, v1\n\tv_rcp_iflag_f32_e32 v0, v0\n\ts_waitcnt_depctr 0xfff\n\tv_mul_f32_e32 v0, 0x4f7ffffe, v0\n\tv_cvt_u32_f32_e32 v0, v0\n ; implicit-def: $sgpr1\n\tv_mul_lo_u32 v2, v2, v0\n ; implicit-def: $sgpr1\n\tv_mul_hi_u32 v2, v0, v2\n ; implicit-def: $sgpr1\n\tv_add_nc_u32_e64 v0, v0, v2\n\ts_waitcnt lgkmcnt(0)\n\tv_mul_hi_u32 v0, s0, v0\n\ts_mov_b32 s1, 1\n\tv_add_nc_u32_e64 v2, v0, s1\n ; implicit-def: $sgpr2\n\tv_mul_lo_u32 v3, v0, v1\n\tv_sub_nc_u32_e64 v3, s0, v3\n ; implicit-def: $sgpr2\n\tv_sub_nc_u32_e64 v4, v3, v1\n ; implicit-def: $sgpr2\n\tv_cmp_ge_u32_e64 s2, v3, v1\n\tv_cndmask_b32_e64 v3, v3, v4, s2\n\tv_cndmask_b32_e64 v0, v0, v2, s2\n\tv_add_nc_u32_e64 v2, v0, s1\n ; implicit-def: $sgpr1\n\tv_cmp_ge_u32_e64 s1, v3, v1\n\tv_cndmask_b32_e64 v0, v0, v2, s1\n ; implicit-def: $sgpr1\n\tv_mul_lo_u32 v1, v0, v1\n\tv_cmp_gt_u32_e64 s0, s0, v1\n\tv_writelane_b32 v5, s0, 21\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v5, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\tscratch_store_b32 off, v0, s32 offset:40 ; 4-byte Folded Spill\n\ts_branch .LBB12_24\n.LBB12_22:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v5, 0\n\tv_readlane_b32 s1, v5, 1\n\tv_mov_b32_e32 v0, 0\n\ts_load_b32 s2, s[0:1], 0x8\n\tglobal_load_u16 v0, v0, s[0:1] offset:22\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s0\n\ts_mov_b32 s0, 0\n\ts_waitcnt lgkmcnt(0)\n\tv_writelane_b32 v5, s2, 19\n\tv_writelane_b32 v5, s1, 20\n\tv_writelane_b32 v5, s0, 18\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v5, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB12_20\n.LBB12_23:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v5, 6\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:16 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_branch .LBB12_12\n.LBB12_24:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v5, 21\n\tscratch_load_b32 v0, off, s32 offset:40 ; 4-byte Folded Reload\n\tv_cndmask_b32_e64 v1, 0, 1, s0\n ; implicit-def: $sgpr0\n\ts_waitcnt vmcnt(0)\n\tv_add_nc_u32_e64 v0, v0, v1\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_branch .LBB12_23\n.LBB12_25:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v5, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v5, 7\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:20 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v1, 0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v5, off, s32 offset:44 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end12:\n\t.size\t__ockl_get_num_groups, .Lfunc_end12-__ockl_get_num_groups\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 2880\n; NumSgprs: 35\n; NumVgprs: 6\n; ScratchSize: 52\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_get_local_id\n\t.type\t__ockl_get_local_id,@function\n__ockl_get_local_id: ; @__ockl_get_local_id\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v2, s32 offset:36 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v31, s32 offset:8 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill\n; %bb.1:\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n ; implicit-def: $vgpr2 : SGPR spill to VGPR lane\n\tv_writelane_b32 v2, s1, 0\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB13_4\n; %bb.2:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v2, s1, 1\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB13_7\n; %bb.3:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 2\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB13_10\n\ts_branch .LBB13_9\n.LBB13_4:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 0\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:12 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 3\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB13_13\n; %bb.5:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 4\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB13_12\n; %bb.6:\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0x3ff\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_branch .LBB13_12\n.LBB13_7:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 1\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:16 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:32 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 5\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB13_11\n; %bb.8:\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_bfe_u32 v0, v0, 10, 10\n\tscratch_store_b32 off, v0, s32 offset:32 ; 4-byte Folded Spill\n\ts_branch .LBB13_11\n.LBB13_9:\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_bfe_u32 v0, v0, 20, 10\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n.LBB13_10:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 2\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:20 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_branch .LBB13_7\n.LBB13_11:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 5\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:32 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_branch .LBB13_4\n.LBB13_12:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n.LBB13_13:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 3\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:24 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v1, 0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v2, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end13:\n\t.size\t__ockl_get_local_id, .Lfunc_end13-__ockl_get_local_id\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 912\n; NumSgprs: 33\n; NumVgprs: 32\n; ScratchSize: 44\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function _ZL20__work_group_barrierj\n\t.type\t_ZL20__work_group_barrierj,@function\n_ZL20__work_group_barrierj: ; @_ZL20__work_group_barrierj\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v3, s32 offset:8 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b64 s[0:1], src_private_base\n\ts_mov_b32 s2, 32\n\ts_lshr_b64 s[0:1], s[0:1], s2\n\ts_mov_b32 s2, s0\n\ts_mov_b32 s0, s32\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v0, v[0:1]\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_eq_u32_e64 s0, v0, s0\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n ; implicit-def: $vgpr3 : SGPR spill to VGPR lane\n\tv_writelane_b32 v3, s1, 0\n\ts_or_saveexec_b32 s4, -1\n\tscratch_store_b32 off, v3, s32 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s4\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB14_1\n\ts_branch .LBB14_3\n.LBB14_1:\n\ts_or_saveexec_b32 s4, -1\n\tscratch_load_b32 v3, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s4\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v3, 0\n\ts_or_saveexec_b32 s0, s0\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v3, s0, 1\n\ts_or_saveexec_b32 s4, -1\n\tscratch_store_b32 off, v3, s32 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s4\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB14_4\n; %bb.2:\n\ts_waitcnt_vscnt null, 0x0\n\ts_barrier\n\tbuffer_gl0_inv\n\ts_branch .LBB14_4\n.LBB14_3:\n\ts_waitcnt_vscnt null, 0x0\n\ts_barrier\n\ts_branch .LBB14_1\n.LBB14_4:\n\ts_or_saveexec_b32 s4, -1\n\tscratch_load_b32 v3, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s4\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v3, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v3, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end14:\n\t.size\t_ZL20__work_group_barrierj, .Lfunc_end14-_ZL20__work_group_barrierj\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 300\n; NumSgprs: 33\n; NumVgprs: 4\n; ScratchSize: 16\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function _ZL9__barrieri\n\t.type\t_ZL9__barrieri,@function\n_ZL9__barrieri: ; @_ZL9__barrieri\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s3, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v4, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 16\n\tv_writelane_b32 v4, s30, 0\n\tv_writelane_b32 v4, s31, 1\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b64 s[0:1], src_private_base\n\ts_mov_b32 s2, 32\n\ts_lshr_b64 s[0:1], s[0:1], s2\n\ts_mov_b32 s2, s0\n\ts_mov_b32 s0, s33\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v0, v[0:1]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, _ZL20__work_group_barrierj@rel32@lo+4\n\ts_addc_u32 s1, s1, _ZL20__work_group_barrierj@rel32@hi+12\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s30, v4, 0\n\tv_readlane_b32 s31, v4, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v4, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, -16\n\ts_mov_b32 s33, s3\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end15:\n\t.size\t_ZL9__barrieri, .Lfunc_end15-_ZL9__barrieri\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 180\n; NumSgprs: 34\n; NumVgprs: 32\n; ScratchSize: 32\n; MemoryBound: 0\n\t.section\t.text._Z13__syncthreadsv,\"axG\",@progbits,_Z13__syncthreadsv,comdat\n\t.hidden\t_Z13__syncthreadsv ; -- Begin function _Z13__syncthreadsv\n\t.weak\t_Z13__syncthreadsv\n\t.p2align\t2\n\t.type\t_Z13__syncthreadsv,@function\n_Z13__syncthreadsv: ; @_Z13__syncthreadsv\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s16, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v5, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 16\n\tv_writelane_b32 v5, s30, 0\n\tv_writelane_b32 v5, s31, 1\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, _ZL9__barrieri@rel32@lo+4\n\ts_addc_u32 s1, s1, _ZL9__barrieri@rel32@hi+12\n\tv_mov_b32_e32 v0, 1\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s30, v5, 0\n\tv_readlane_b32 s31, v5, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v5, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, -16\n\ts_mov_b32 s33, s16\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end16:\n\t.size\t_Z13__syncthreadsv, .Lfunc_end16-_Z13__syncthreadsv\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 124\n; NumSgprs: 34\n; NumVgprs: 32\n; ScratchSize: 48\n; MemoryBound: 0\n\t.text\n\t.protected\t_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii ; -- Begin function _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii\n\t.globl\t_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii\n\t.p2align\t8\n\t.type\t_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii,@function\n_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii: ; @_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii\n; %bb.0:\n\ts_mov_b32 s32, 0x150\n ; implicit-def: $vgpr40 : SGPR spill to VGPR lane\n\tv_writelane_b32 v40, s15, 0\n\ts_mov_b32 s6, s14\n\tv_readlane_b32 s14, v40, 0\n\tv_writelane_b32 v40, s6, 1\n\ts_mov_b32 s12, s13\n\tv_readlane_b32 s13, v40, 1\n\tv_writelane_b32 v40, s12, 2\n\ts_mov_b64 s[10:11], s[4:5]\n\tv_writelane_b32 v40, s10, 3\n\tv_writelane_b32 v40, s11, 4\n\tv_writelane_b32 v40, s2, 5\n\tv_writelane_b32 v40, s3, 6\n\ts_mov_b64 s[4:5], s[0:1]\n\tv_readlane_b32 s0, v40, 5\n\tv_readlane_b32 s1, v40, 6\n\tv_writelane_b32 v40, s4, 7\n\tv_writelane_b32 v40, s5, 8\n\tv_mov_b32_e32 v31, v0\n\tscratch_store_b32 off, v31, off offset:280 ; 4-byte Folded Spill\n\ts_load_b64 s[64:65], s[0:1], 0x0\n\ts_load_b64 s[60:61], s[0:1], 0x8\n\ts_load_b64 s[56:57], s[0:1], 0x10\n\ts_load_b64 s[52:53], s[0:1], 0x18\n\ts_load_b64 s[42:43], s[0:1], 0x20\n\ts_load_b64 s[38:39], s[0:1], 0x28\n\ts_load_b64 s[34:35], s[0:1], 0x30\n\ts_load_b32 s8, s[0:1], 0x38\n\ts_load_b32 s7, s[0:1], 0x3c\n\ts_load_b32 s6, s[0:1], 0x40\n\ts_mov_b64 s[2:3], src_private_base\n\ts_mov_b32 s20, 32\n\tv_writelane_b32 v40, s20, 9\n\ts_lshr_b64 s[2:3], s[2:3], s20\n\ts_mov_b32 s9, s2\n\tv_writelane_b32 v40, s9, 10\n\ts_mov_b32 s62, 0x50\n ; kill: def $sgpr62 killed $sgpr62 def $sgpr62_sgpr63\n\ts_mov_b32 s63, s9\n\ts_mov_b32 s58, 0x58\n ; kill: def $sgpr58 killed $sgpr58 def $sgpr58_sgpr59\n\ts_mov_b32 s59, s9\n\ts_mov_b32 s54, 0x60\n ; kill: def $sgpr54 killed $sgpr54 def $sgpr54_sgpr55\n\ts_mov_b32 s55, s9\n\ts_mov_b32 s50, 0x68\n ; kill: def $sgpr50 killed $sgpr50 def $sgpr50_sgpr51\n\ts_mov_b32 s51, s9\n\ts_mov_b32 s48, 0x70\n ; kill: def $sgpr48 killed $sgpr48 def $sgpr48_sgpr49\n\ts_mov_b32 s49, s9\n\ts_mov_b64 s[2:3], s[48:49]\n\tv_writelane_b32 v40, s2, 11\n\tv_writelane_b32 v40, s3, 12\n\ts_mov_b32 s2, 0x78\n\tv_mov_b32_e32 v6, s2\n\tv_mov_b32_e32 v0, s9\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v0\n\ts_mov_b32 s46, 0x80\n ; kill: def $sgpr46 killed $sgpr46 def $sgpr46_sgpr47\n\ts_mov_b32 s47, s9\n\ts_mov_b64 s[2:3], s[46:47]\n\tv_writelane_b32 v40, s2, 13\n\tv_writelane_b32 v40, s3, 14\n\ts_mov_b32 s2, 0x88\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v0, s9\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s44, 0x90\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s9\n\tv_writelane_b32 v40, s44, 15\n\tv_writelane_b32 v40, s45, 16\n\ts_mov_b64 s[2:3], s[44:45]\n\tv_writelane_b32 v40, s2, 17\n\tv_writelane_b32 v40, s3, 18\n\ts_mov_b32 s40, 0x98\n ; kill: def $sgpr40 killed $sgpr40 def $sgpr40_sgpr41\n\ts_mov_b32 s41, s9\n\tv_writelane_b32 v40, s40, 19\n\tv_writelane_b32 v40, s41, 20\n\ts_mov_b64 s[2:3], s[40:41]\n\tv_writelane_b32 v40, s2, 21\n\tv_writelane_b32 v40, s3, 22\n\ts_mov_b32 s36, 0xa0\n ; kill: def $sgpr36 killed $sgpr36 def $sgpr36_sgpr37\n\ts_mov_b32 s37, s9\n\ts_mov_b64 s[2:3], s[36:37]\n\tv_writelane_b32 v40, s2, 23\n\tv_writelane_b32 v40, s3, 24\n\ts_mov_b32 s30, 0xa8\n ; kill: def $sgpr30 killed $sgpr30 def $sgpr30_sgpr31\n\ts_mov_b32 s31, s9\n\tv_writelane_b32 v40, s30, 25\n\tv_writelane_b32 v40, s31, 26\n\ts_mov_b32 s2, 0xac\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v4, s9\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\ts_mov_b32 s2, 0xb0\n ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3\n\ts_mov_b32 s3, s9\n\ts_mov_b64 s[16:17], s[2:3]\n\tv_writelane_b32 v40, s16, 27\n\tv_writelane_b32 v40, s17, 28\n\ts_mov_b32 s26, 0xb4\n ; kill: def $sgpr26 killed $sgpr26 def $sgpr26_sgpr27\n\ts_mov_b32 s27, s9\n\ts_mov_b64 s[16:17], s[26:27]\n\tv_writelane_b32 v40, s16, 29\n\tv_writelane_b32 v40, s17, 30\n\ts_mov_b32 s22, 0xb8\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s9\n ; implicit-def: $vgpr41 : SGPR spill to VGPR lane\n\tv_writelane_b32 v40, s22, 31\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v40, off offset:264 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\tv_writelane_b32 v41, s23, 0\n\ts_mov_b32 s16, 0xbc\n ; kill: def $sgpr16 killed $sgpr16 def $sgpr16_sgpr17\n\ts_mov_b32 s17, s9\n\ts_mov_b32 s24, 0xc0\n ; kill: def $sgpr24 killed $sgpr24 def $sgpr24_sgpr25\n\ts_mov_b32 s25, s9\n\ts_mov_b64 s[18:19], s[24:25]\n\tv_writelane_b32 v41, s18, 1\n\tv_writelane_b32 v41, s19, 2\n\ts_mov_b32 s28, 0xc8\n ; kill: def $sgpr28 killed $sgpr28 def $sgpr28_sgpr29\n\ts_mov_b32 s29, s9\n\ts_mov_b64 s[18:19], s[28:29]\n\tv_writelane_b32 v41, s18, 3\n\tv_writelane_b32 v41, s19, 4\n\ts_mov_b32 s18, 0xd0\n ; kill: def $sgpr18 killed $sgpr18 def $sgpr18_sgpr19\n\ts_mov_b32 s19, s9\n\ts_mov_b64 s[66:67], s[18:19]\n\tv_writelane_b32 v41, s66, 5\n\tv_writelane_b32 v41, s67, 6\n\ts_mov_b32 s66, 0xd8\n ; kill: def $sgpr66 killed $sgpr66 def $sgpr66_sgpr67\n\ts_mov_b32 s67, s9\n\tv_writelane_b32 v41, s66, 7\n\tv_writelane_b32 v41, s67, 8\n\ts_mov_b32 s66, 0xdc\n ; kill: def $sgpr66 killed $sgpr66 def $sgpr66_sgpr67\n\ts_mov_b32 s67, s9\n\tv_writelane_b32 v41, s66, 9\n\tv_writelane_b32 v41, s67, 10\n\tv_writelane_b32 v41, s66, 11\n\tv_writelane_b32 v41, s67, 12\n\ts_mov_b32 s66, 0xe0\n ; kill: def $sgpr66 killed $sgpr66 def $sgpr66_sgpr67\n\ts_mov_b32 s67, s9\n\tv_writelane_b32 v41, s66, 13\n\tv_writelane_b32 v41, s67, 14\n\tv_writelane_b32 v41, s66, 15\n\tv_writelane_b32 v41, s67, 16\n\ts_mov_b32 s66, 0xe4\n ; kill: def $sgpr66 killed $sgpr66 def $sgpr66_sgpr67\n\ts_mov_b32 s67, s9\n\tv_writelane_b32 v41, s66, 17\n\tv_writelane_b32 v41, s67, 18\n\tv_writelane_b32 v41, s66, 19\n\tv_writelane_b32 v41, s67, 20\n\ts_mov_b32 s66, 0xe8\n ; kill: def $sgpr66 killed $sgpr66 def $sgpr66_sgpr67\n\ts_mov_b32 s67, s9\n\tv_writelane_b32 v41, s66, 21\n\tv_writelane_b32 v41, s67, 22\n\tv_writelane_b32 v41, s66, 23\n\tv_writelane_b32 v41, s67, 24\n\ts_mov_b32 s66, 0xec\n ; kill: def $sgpr66 killed $sgpr66 def $sgpr66_sgpr67\n\ts_mov_b32 s67, s9\n\tv_writelane_b32 v41, s66, 25\n\tv_writelane_b32 v41, s67, 26\n\ts_mov_b32 s66, 0xf0\n ; kill: def $sgpr66 killed $sgpr66 def $sgpr66_sgpr67\n\ts_mov_b32 s67, s9\n\tv_writelane_b32 v41, s66, 27\n\tv_writelane_b32 v41, s67, 28\n\ts_mov_b32 s66, 0xf8\n ; kill: def $sgpr66 killed $sgpr66 def $sgpr66_sgpr67\n\ts_mov_b32 s67, s9\n\tv_writelane_b32 v41, s66, 29\n\tv_writelane_b32 v41, s67, 30\n\tv_mov_b32_e32 v4, s62\n\tv_mov_b32_e32 v5, s63\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v8, s64\n\tv_mov_b32_e32 v9, s65\n\tflat_store_b64 v[4:5], v[8:9]\n\tv_mov_b32_e32 v4, s62\n\tv_mov_b32_e32 v5, s63\n\tflat_load_b64 v[14:15], v[4:5]\n\tv_mov_b32_e32 v4, s58\n\tv_mov_b32_e32 v5, s59\n\tv_mov_b32_e32 v8, s60\n\tv_mov_b32_e32 v9, s61\n\tflat_store_b64 v[4:5], v[8:9]\n\tv_mov_b32_e32 v4, s58\n\tv_mov_b32_e32 v5, s59\n\tflat_load_b64 v[10:11], v[4:5]\n\tv_mov_b32_e32 v4, s54\n\tv_mov_b32_e32 v5, s55\n\tv_mov_b32_e32 v8, s56\n\tv_mov_b32_e32 v9, s57\n\tflat_store_b64 v[4:5], v[8:9]\n\tv_mov_b32_e32 v4, s54\n\tv_mov_b32_e32 v5, s55\n\tflat_load_b64 v[8:9], v[4:5]\n\tv_mov_b32_e32 v4, s50\n\tv_mov_b32_e32 v5, s51\n\tv_mov_b32_e32 v12, s52\n\tv_mov_b32_e32 v13, s53\n\tflat_store_b64 v[4:5], v[12:13]\n\tv_mov_b32_e32 v4, s50\n\tv_mov_b32_e32 v5, s51\n\tflat_load_b64 v[4:5], v[4:5]\n\tv_mov_b32_e32 v12, s48\n\tv_mov_b32_e32 v13, s49\n\ts_waitcnt vmcnt(3) lgkmcnt(6)\n\tflat_store_b64 v[12:13], v[14:15]\n\ts_waitcnt vmcnt(2) lgkmcnt(5)\n\tflat_store_b64 v[6:7], v[10:11]\n\tv_mov_b32_e32 v6, s46\n\tv_mov_b32_e32 v7, s47\n\ts_waitcnt vmcnt(1) lgkmcnt(4)\n\tflat_store_b64 v[6:7], v[8:9]\n\ts_waitcnt vmcnt(0) lgkmcnt(3)\n\tflat_store_b64 v[2:3], v[4:5]\n\tv_mov_b32_e32 v2, s44\n\tv_mov_b32_e32 v3, s45\n\tv_mov_b32_e32 v4, s42\n\tv_mov_b32_e32 v5, s43\n\tflat_store_b64 v[2:3], v[4:5]\n\tv_mov_b32_e32 v2, s40\n\tv_mov_b32_e32 v3, s41\n\tv_mov_b32_e32 v4, s38\n\tv_mov_b32_e32 v5, s39\n\tflat_store_b64 v[2:3], v[4:5]\n\tv_mov_b32_e32 v2, s36\n\tv_mov_b32_e32 v3, s37\n\tv_mov_b32_e32 v4, s34\n\tv_mov_b32_e32 v5, s35\n\tflat_store_b64 v[2:3], v[4:5]\n\tv_mov_b32_e32 v2, s30\n\tv_mov_b32_e32 v3, s31\n\tv_mov_b32_e32 v4, s8\n\tflat_store_b32 v[2:3], v4\n\tv_mov_b32_e32 v2, s7\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tv_mov_b32_e32 v2, s6\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tscratch_store_b32 off, v0, off offset:304 ; 4-byte Folded Spill\n\ts_mov_b64 s[6:7], 0x48\n\ts_mov_b32 s2, s0\n\ts_mov_b32 s0, s1\n\ts_mov_b32 s3, s6\n\ts_mov_b32 s1, s7\n\ts_add_u32 s8, s2, s3\n\ts_addc_u32 s0, s0, s1\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s0\n ; implicit-def: $vgpr42 : SGPR spill to VGPR lane\n\tv_writelane_b32 v41, s8, 31\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v41, off offset:260 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\tv_writelane_b32 v42, s9, 0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_group_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_group_id@rel32@hi+12\n\tv_writelane_b32 v42, s0, 1\n\tv_writelane_b32 v42, s1, 2\n\tv_mov_b32_e32 v0, 2\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:280 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v40, 0\n\tv_readlane_b32 s13, v40, 1\n\tv_readlane_b32 s12, v40, 2\n\tv_readlane_b32 s10, v40, 3\n\tv_readlane_b32 s11, v40, 4\n\tv_readlane_b32 s8, v41, 31\n\tv_readlane_b32 s9, v42, 0\n\tv_readlane_b32 s4, v40, 7\n\tv_readlane_b32 s5, v40, 8\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:304 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:300 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:300 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v2, v0, v1\n\tv_mov_b32_e32 v0, s26\n\tv_mov_b32_e32 v1, s27\n\tflat_store_b32 v[0:1], v2\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_size@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_size@rel32@hi+12\n\tv_mov_b32_e32 v0, 1\n\tscratch_store_b32 off, v0, off offset:276 ; 4-byte Folded Spill\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:280 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v40, 0\n\tv_readlane_b32 s13, v40, 1\n\tv_readlane_b32 s12, v40, 2\n\tv_readlane_b32 s10, v40, 3\n\tv_readlane_b32 s11, v40, 4\n\tv_readlane_b32 s0, v42, 1\n\tv_readlane_b32 s1, v42, 2\n\tv_readlane_b32 s4, v40, 7\n\tv_readlane_b32 s5, v40, 8\n\tv_readlane_b32 s8, v41, 31\n\tv_readlane_b32 s9, v42, 0\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:276 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:296 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:296 ; 4-byte Folded Reload\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v1, off offset:292 ; 4-byte Folded Spill\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:280 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v40, 0\n\tv_readlane_b32 s13, v40, 1\n\tv_readlane_b32 s12, v40, 2\n\tv_readlane_b32 s10, v40, 3\n\tv_readlane_b32 s11, v40, 4\n\tv_readlane_b32 s8, v41, 31\n\tv_readlane_b32 s9, v42, 0\n\tv_readlane_b32 s4, v40, 7\n\tv_readlane_b32 s5, v40, 8\n\tv_readlane_b32 s2, v40, 25\n\tv_readlane_b32 s3, v40, 26\n\tv_readlane_b32 s0, v42, 1\n\tv_readlane_b32 s1, v42, 2\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:292 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:288 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:288 ; 4-byte Folded Reload\n ; implicit-def: $sgpr6\n ; implicit-def: $sgpr6\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v2, v0, v1\n\tv_mov_b32_e32 v0, s22\n\tv_mov_b32_e32 v1, s23\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tscratch_store_b32 off, v0, off offset:284 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, off offset:268 ; 4-byte Folded Spill\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:280 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v40, 0\n\tv_readlane_b32 s13, v40, 1\n\tv_readlane_b32 s12, v40, 2\n\tv_readlane_b32 s10, v40, 3\n\tv_readlane_b32 s11, v40, 4\n\tv_readlane_b32 s8, v41, 31\n\tv_readlane_b32 s9, v42, 0\n\tv_readlane_b32 s4, v40, 7\n\tv_readlane_b32 s5, v40, 8\n\tv_readlane_b32 s0, v40, 19\n\tv_readlane_b32 s1, v40, 20\n\tv_readlane_b32 s2, v40, 15\n\tv_readlane_b32 s3, v40, 16\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:268 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v4, v1\n\tscratch_load_b32 v1, off, off offset:284 ; 4-byte Folded Reload\n ; implicit-def: $sgpr6\n ; implicit-def: $sgpr6\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v3, v1, v2\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b32 v[1:2], v3\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b64 v[1:2], v[1:2]\n\tv_mov_b32_e32 v4, s1\n\tv_mov_b32_e32 v3, s0\n\tflat_load_b64 v[4:5], v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v6, v4\n\tv_lshrrev_b64 v[7:8], s20, v[1:2]\n\tv_mov_b32_e32 v3, v7\n\tv_mul_lo_u32 v3, v3, v6\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_lshrrev_b64 v[4:5], s20, v[4:5]\n\tv_mov_b32_e32 v2, v4\n\tv_mul_lo_u32 v2, v1, v2\n\tv_mad_u64_u32 v[4:5], s0, v1, v6, 0\n\tv_mov_b32_e32 v1, v5\n\tv_add3_u32 v1, v1, v2, v3\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n\tv_lshlrev_b64 v[2:3], s20, v[1:2]\n\tv_mov_b32_e32 v6, v3\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v42, s0, 3\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v1, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v1\n\tv_mov_b32_e32 v1, v5\n\tv_or_b32_e64 v1, v1, v6\n\tv_mov_b32_e32 v3, v2\n\tv_mov_b32_e32 v2, v4\n\tv_or_b32_e64 v3, v2, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v1, s24\n\tv_mov_b32_e32 v2, s25\n\tflat_store_b64 v[1:2], v[3:4]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_num_groups@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_num_groups@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:280 ; 4-byte Folded Reload\n\tv_readlane_b32 s15, v42, 3\n\tv_readlane_b32 s14, v40, 0\n\tv_readlane_b32 s13, v40, 1\n\tv_readlane_b32 s12, v40, 2\n\tv_readlane_b32 s10, v40, 3\n\tv_readlane_b32 s11, v40, 4\n\tv_readlane_b32 s6, v41, 7\n\tv_readlane_b32 s7, v41, 8\n\tv_readlane_b32 s2, v40, 19\n\tv_readlane_b32 s3, v40, 20\n\tv_readlane_b32 s0, v41, 9\n\tv_readlane_b32 s1, v41, 10\n\tv_readlane_b32 s4, v40, 7\n\tv_readlane_b32 s5, v40, 8\n\tv_readlane_b32 s8, v41, 31\n\tv_readlane_b32 s9, v42, 0\n\tv_readlane_b32 s30, v40, 15\n\tv_readlane_b32 s31, v40, 16\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:276 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:272 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:272 ; 4-byte Folded Reload\n ; implicit-def: $sgpr21\n ; implicit-def: $sgpr21\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n\tv_mov_b32_e32 v3, s30\n\tv_mov_b32_e32 v4, s31\n\tflat_load_b64 v[3:4], v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v6, v3\n\tv_mov_b32_e32 v5, v1\n\tv_mad_u64_u32 v[1:2], s21, v5, v6, 0\n\tv_mov_b32_e32 v7, v2\n ; implicit-def: $sgpr21\n ; implicit-def: $sgpr30\n ; implicit-def: $sgpr30\n\tv_mov_b32_e32 v6, s21\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v6\n\tv_lshrrev_b64 v[3:4], s20, v[3:4]\n\tv_mov_b32_e32 v6, v3\n\tv_mad_u64_u32 v[3:4], s21, v5, v6, v[7:8]\n\tv_mov_b32_e32 v4, v3\n ; implicit-def: $sgpr21\n ; implicit-def: $sgpr30\n ; implicit-def: $sgpr30\n\tv_mov_b32_e32 v3, s21\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v3\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n ; implicit-def: $sgpr21\n\tv_mov_b32_e32 v3, s15\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n\tv_lshlrev_b64 v[2:3], v0, v[1:2]\n\tv_mov_b32_e32 v6, v3\n\ts_mov_b32 s21, 33\n\tv_lshlrev_b64 v[4:5], s21, v[4:5]\n\tv_mov_b32_e32 v1, v5\n\tv_or_b32_e64 v1, v1, v6\n\tv_mov_b32_e32 v3, v2\n\tv_mov_b32_e32 v2, v4\n\tv_or_b32_e64 v3, v2, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v1, s28\n\tv_mov_b32_e32 v2, s29\n\tflat_store_b64 v[1:2], v[3:4]\n\tv_mov_b32_e32 v1, s26\n\tv_mov_b32_e32 v2, s27\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v2, 31, v1\n\tv_mov_b32_e32 v6, v1\n\tv_mov_b32_e32 v7, v2\n\tv_mov_b32_e32 v2, s24\n\tv_mov_b32_e32 v3, s25\n\tflat_load_b64 v[4:5], v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshrrev_b64 v[2:3], s20, v[4:5]\n ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec\n\tv_mul_lo_u32 v2, v1, v2\n\tv_lshrrev_b64 v[6:7], s20, v[6:7]\n\tv_mov_b32_e32 v3, v6\n\tv_mov_b32_e32 v6, v4\n\tv_mul_lo_u32 v3, v3, v6\n\tv_mad_u64_u32 v[4:5], s21, v1, v6, 0\n\tv_mov_b32_e32 v1, v5\n\tv_add3_u32 v1, v1, v2, v3\n ; implicit-def: $sgpr21\n ; implicit-def: $sgpr24\n ; implicit-def: $sgpr24\n\tv_mov_b32_e32 v3, s21\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n\tv_lshlrev_b64 v[2:3], s20, v[1:2]\n\tv_mov_b32_e32 v6, v3\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n ; implicit-def: $sgpr21\n\tv_mov_b32_e32 v1, s15\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v1\n\tv_mov_b32_e32 v1, v5\n\tv_or_b32_e64 v1, v1, v6\n\tv_mov_b32_e32 v3, v2\n\tv_mov_b32_e32 v2, v4\n\tv_or_b32_e64 v2, v2, v3\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v4, s22\n\tv_mov_b32_e32 v5, s23\n\tflat_load_b32 v1, v[4:5]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v4, 31, v1\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v9, v4\n\tv_mov_b32_e32 v5, s3\n\tv_mov_b32_e32 v4, s2\n\tflat_load_b64 v[6:7], v[4:5]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshrrev_b64 v[4:5], s20, v[6:7]\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n\tv_mul_lo_u32 v4, v1, v4\n\tv_lshrrev_b64 v[8:9], s20, v[8:9]\n\tv_mov_b32_e32 v5, v8\n\tv_mov_b32_e32 v8, v6\n\tv_mul_lo_u32 v5, v5, v8\n\tv_mad_u64_u32 v[6:7], s21, v1, v8, 0\n\tv_mov_b32_e32 v1, v7\n\tv_add3_u32 v4, v1, v4, v5\n ; implicit-def: $sgpr21\n ; implicit-def: $sgpr22\n ; implicit-def: $sgpr22\n\tv_mov_b32_e32 v1, s21\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v1\n\tv_lshlrev_b64 v[4:5], s20, v[4:5]\n\tv_mov_b32_e32 v8, v5\n ; kill: def $vgpr6 killed $vgpr6 killed $vgpr6_vgpr7 killed $exec\n ; implicit-def: $sgpr20\n\tv_mov_b32_e32 v1, s15\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v1\n\tv_mov_b32_e32 v1, v7\n\tv_or_b32_e64 v1, v1, v8\n\tv_mov_b32_e32 v5, v4\n\tv_mov_b32_e32 v4, v6\n\tv_or_b32_e64 v5, v4, v5\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v1\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v2, v3\n\tv_mov_b32_e32 v3, v6\n\tv_add_co_u32 v1, s15, v1, v4\n\tv_add_co_ci_u32_e64 v3, s15, v2, v3, s15\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_load_b32 v5, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v3, 31, v5\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v6\n\tv_add_co_u32 v3, s15, v3, v4\n\tv_add_co_ci_u32_e64 v1, s15, v1, v2, s15\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v1, s18\n\tv_mov_b32_e32 v2, s19\n\tflat_store_b64 v[1:2], v[3:4]\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v3, v1, v0\n\tv_mov_b32_e32 v1, s6\n\tv_mov_b32_e32 v2, s7\n\tflat_store_b32 v[1:2], v3\n\tv_mov_b32_e32 v1, s6\n\tv_mov_b32_e32 v2, s7\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v3, 31, v1\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b64 v[3:4], v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_lt_u64_e64 s2, v[1:2], v[3:4]\n\tv_cndmask_b32_e64 v3, 0, 1, s2\n\tv_mov_b32_e32 v2, s1\n\tv_mov_b32_e32 v1, s0\n\tflat_store_b8 v[1:2], v3\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_id@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v2, off, off offset:268 ; 4-byte Folded Reload\n\tv_readlane_b32 s8, v40, 31\n\tv_readlane_b32 s9, v41, 0\n\tv_readlane_b32 s6, v41, 13\n\tv_readlane_b32 s7, v41, 14\n\tv_readlane_b32 s4, v40, 15\n\tv_readlane_b32 s5, v40, 16\n\tv_readlane_b32 s2, v41, 17\n\tv_readlane_b32 s3, v41, 18\n\tv_readlane_b32 s0, v41, 21\n\tv_readlane_b32 s1, v41, 22\n\tv_mov_b32_e32 v3, v1\n ; implicit-def: $sgpr10\n ; implicit-def: $sgpr10\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tv_mov_b32_e32 v3, v0\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tflat_store_b32 v[0:1], v3\n\tv_mov_b32_e32 v0, s8\n\tv_mov_b32_e32 v1, s9\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v3, s6\n\tv_mov_b32_e32 v4, s7\n\tflat_load_b32 v1, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v0, v0, v1\n\tv_ashrrev_i32_e64 v3, 31, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tv_mov_b32_e32 v3, s4\n\tv_mov_b32_e32 v4, s5\n\tflat_load_b64 v[3:4], v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_lt_u64_e64 s4, v[0:1], v[3:4]\n\tv_cndmask_b32_e64 v3, 0, 1, s4\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b8 v[0:1], v3\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v42, s0, 4\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v42, off offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n.LBB17_1: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v40, off, off offset:264 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v41, off, off offset:260 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v42, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(2)\n\tv_readlane_b32 s2, v40, 27\n\tv_readlane_b32 s3, v40, 28\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s4, v41, 23\n\tv_readlane_b32 s5, v41, 24\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v42, 5\n\tv_readlane_b32 s1, v42, 4\n\tv_writelane_b32 v42, s1, 6\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_lt_i32_e64 s1, v0, v1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v42, s0, 7\n\tv_writelane_b32 v42, s0, 8\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v42, s0, 9\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v42, off offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB17_6\n; %bb.2: ; in Loop: Header=BB17_1 Depth=1\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v40, off, off offset:264 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v41, off, off offset:260 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s22, v41, 15\n\tv_readlane_b32 s23, v41, 16\n\tv_readlane_b32 s14, v40, 0\n\tv_readlane_b32 s13, v40, 1\n\tv_readlane_b32 s12, v40, 2\n\tv_readlane_b32 s10, v40, 3\n\tv_readlane_b32 s11, v40, 4\n\tv_readlane_b32 s4, v40, 7\n\tv_readlane_b32 s5, v40, 8\n\tv_readlane_b32 s0, v40, 5\n\tv_readlane_b32 s1, v40, 6\n\tv_readlane_b32 s6, v41, 3\n\tv_readlane_b32 s7, v41, 4\n\tv_readlane_b32 s8, v41, 23\n\tv_readlane_b32 s9, v41, 24\n\tv_readlane_b32 s16, v40, 29\n\tv_readlane_b32 s17, v40, 30\n\tv_readlane_b32 s18, v41, 27\n\tv_readlane_b32 s19, v41, 28\n\tv_readlane_b32 s20, v40, 21\n\tv_readlane_b32 s21, v40, 22\n\tv_readlane_b32 s2, v41, 1\n\tv_readlane_b32 s3, v41, 2\n\tv_readlane_b32 s24, v41, 5\n\tv_readlane_b32 s25, v41, 6\n\tv_readlane_b32 s26, v41, 25\n\tv_readlane_b32 s27, v41, 26\n\tv_readlane_b32 s28, v40, 23\n\tv_readlane_b32 s29, v40, 24\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v42, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\tscratch_load_b32 v31, off, off offset:280 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s8\n\tv_mov_b32_e32 v2, s9\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v0, v0, v1\n\tv_ashrrev_i32_e64 v2, 31, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, s28\n\tv_mov_b32_e32 v3, s29\n\tflat_load_b64 v[2:3], v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_lt_u64_e64 s15, v[0:1], v[2:3]\n\tv_cndmask_b32_e64 v2, 0, 1, s15\n\tv_mov_b32_e32 v0, s26\n\tv_mov_b32_e32 v1, s27\n\tflat_store_b8 v[0:1], v2\n\tv_mov_b32_e32 v0, s24\n\tv_mov_b32_e32 v1, s25\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v3, s8\n\tv_mov_b32_e32 v4, s9\n\tflat_load_b32 v0, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v3, 31, v0\n\tv_mov_b32_e32 v7, v0\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b64 v[5:6], v[3:4]\n\ts_mov_b32 s3, 32\n\tv_writelane_b32 v42, s3, 10\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshrrev_b64 v[3:4], s3, v[5:6]\n ; kill: def $vgpr3 killed $vgpr3 killed $vgpr3_vgpr4 killed $exec\n\tv_mul_lo_u32 v3, v0, v3\n\tv_lshrrev_b64 v[7:8], s3, v[7:8]\n\tv_mov_b32_e32 v4, v7\n\tv_mov_b32_e32 v7, v5\n\tv_mul_lo_u32 v4, v4, v7\n\tv_mad_u64_u32 v[5:6], s2, v0, v7, 0\n\tv_mov_b32_e32 v0, v6\n\tv_add3_u32 v3, v0, v3, v4\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr15\n ; implicit-def: $sgpr15\n\tv_mov_b32_e32 v0, s2\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[3:4], s3, v[3:4]\n\tv_mov_b32_e32 v7, v4\n ; kill: def $vgpr5 killed $vgpr5 killed $vgpr5_vgpr6 killed $exec\n\ts_mov_b32 s2, 0\n\tv_writelane_b32 v42, s2, 11\n ; implicit-def: $sgpr15\n\tv_mov_b32_e32 v0, s2\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v7\n\tv_mov_b32_e32 v4, v3\n\tv_mov_b32_e32 v3, v5\n\tv_or_b32_e64 v4, v3, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s15, v0, v3\n\tv_add_co_ci_u32_e64 v2, s15, v1, v2, s15\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, s22\n\tv_mov_b32_e32 v3, s23\n\tflat_load_b32 v2, v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v3, 31, v2\n\tv_mov_b32_e32 v7, v2\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v3, s20\n\tv_mov_b32_e32 v4, s21\n\tflat_load_b64 v[5:6], v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshrrev_b64 v[3:4], s3, v[5:6]\n ; kill: def $vgpr3 killed $vgpr3 killed $vgpr3_vgpr4 killed $exec\n\tv_mul_lo_u32 v3, v2, v3\n\tv_lshrrev_b64 v[7:8], s3, v[7:8]\n\tv_mov_b32_e32 v4, v7\n\tv_mov_b32_e32 v7, v5\n\tv_mul_lo_u32 v4, v4, v7\n\tv_mad_u64_u32 v[5:6], s15, v2, v7, 0\n\tv_mov_b32_e32 v2, v6\n\tv_add3_u32 v2, v2, v3, v4\n ; implicit-def: $sgpr15\n ; implicit-def: $sgpr20\n ; implicit-def: $sgpr20\n\tv_mov_b32_e32 v4, s15\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tv_lshlrev_b64 v[3:4], s3, v[2:3]\n\tv_mov_b32_e32 v7, v4\n ; kill: def $vgpr5 killed $vgpr5 killed $vgpr5_vgpr6 killed $exec\n ; implicit-def: $sgpr15\n\tv_mov_b32_e32 v2, s2\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v2\n\tv_mov_b32_e32 v2, v6\n\tv_or_b32_e64 v2, v2, v7\n\tv_mov_b32_e32 v4, v3\n\tv_mov_b32_e32 v3, v5\n\tv_or_b32_e64 v4, v3, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v1, v5\n\tv_add_co_u32 v2, s15, v2, v3\n\tv_add_co_ci_u32_e64 v0, s15, v0, v1, s15\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v0\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s8\n\tv_mov_b32_e32 v2, s9\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v0, v0, v1\n\tv_ashrrev_i32_e64 v1, 31, v0\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v6, v1\n\tv_mov_b32_e32 v1, s6\n\tv_mov_b32_e32 v2, s7\n\tflat_load_b64 v[3:4], v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshrrev_b64 v[1:2], s3, v[3:4]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_mul_lo_u32 v1, v0, v1\n\tv_lshrrev_b64 v[5:6], s3, v[5:6]\n\tv_mov_b32_e32 v2, v5\n\tv_mov_b32_e32 v5, v3\n\tv_mul_lo_u32 v4, v2, v5\n\tv_mad_u64_u32 v[2:3], s6, v0, v5, 0\n\tv_mov_b32_e32 v0, v3\n\tv_add3_u32 v0, v0, v1, v4\n ; implicit-def: $sgpr6\n ; implicit-def: $sgpr7\n ; implicit-def: $sgpr7\n\tv_mov_b32_e32 v4, s6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_lshlrev_b64 v[0:1], s3, v[0:1]\n\tv_mov_b32_e32 v5, v1\n\tv_mov_b32_e32 v3, v2\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v2, s2\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v2, v4\n\tv_or_b32_e64 v2, v2, v5\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v3\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], off offset:328 ; 8-byte Folded Spill\n\ts_mov_b64 s[8:9], 0x48\n\ts_mov_b32 s3, s0\n\ts_mov_b32 s0, s1\n\ts_mov_b32 s6, s8\n\ts_mov_b32 s1, s9\n\ts_add_u32 s8, s3, s6\n\ts_addc_u32 s0, s0, s1\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s0\n\tv_writelane_b32 v42, s8, 12\n\tv_writelane_b32 v42, s9, 13\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_group_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_group_id@rel32@hi+12\n\tv_writelane_b32 v42, s0, 14\n\tv_writelane_b32 v42, s1, 15\n\tv_mov_b32_e32 v0, 0\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:280 ; 4-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, off offset:328 ; 8-byte Folded Reload\n\tv_readlane_b32 s14, v40, 0\n\tv_readlane_b32 s13, v40, 1\n\tv_readlane_b32 s12, v40, 2\n\tv_readlane_b32 s10, v40, 3\n\tv_readlane_b32 s11, v40, 4\n\tv_readlane_b32 s8, v42, 12\n\tv_readlane_b32 s9, v42, 13\n\tv_readlane_b32 s6, v40, 17\n\tv_readlane_b32 s7, v40, 18\n\tv_readlane_b32 s4, v40, 7\n\tv_readlane_b32 s5, v40, 8\n\tv_readlane_b32 s3, v42, 10\n\tv_readlane_b32 s0, v42, 14\n\tv_readlane_b32 s1, v42, 15\n\tv_mov_b32_e32 v4, v1\n ; implicit-def: $sgpr15\n ; implicit-def: $sgpr15\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, 1\n\tscratch_store_b32 off, v0, off offset:324 ; 4-byte Folded Spill\n\tv_lshlrev_b32_e64 v1, v0, v1\n\tv_mov_b32_e32 v4, s6\n\tv_mov_b32_e32 v5, s7\n\tflat_load_b64 v[4:5], v[4:5]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v8, v4\n\tv_mad_u64_u32 v[6:7], s6, v1, v8, 0\n\tv_mov_b32_e32 v9, v7\n ; implicit-def: $sgpr6\n ; implicit-def: $sgpr7\n ; implicit-def: $sgpr7\n\tv_mov_b32_e32 v8, s6\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v8\n\tv_lshrrev_b64 v[4:5], s3, v[4:5]\n\tv_mov_b32_e32 v8, v4\n\tv_mad_u64_u32 v[4:5], s6, v1, v8, v[9:10]\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n ; implicit-def: $sgpr6\n ; implicit-def: $sgpr7\n ; implicit-def: $sgpr7\n\tv_mov_b32_e32 v1, s6\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v1\n\tv_lshlrev_b64 v[4:5], s3, v[4:5]\n\tv_mov_b32_e32 v8, v5\n ; kill: def $vgpr6 killed $vgpr6 killed $vgpr6_vgpr7 killed $exec\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v1, s2\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v1\n\tv_mov_b32_e32 v1, v7\n\tv_or_b32_e64 v1, v1, v8\n\tv_mov_b32_e32 v5, v4\n\tv_mov_b32_e32 v4, v6\n\tv_or_b32_e64 v5, v4, v5\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v1\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v2, v3\n\tv_mov_b32_e32 v3, v6\n\tv_add_co_u32 v1, s2, v1, v4\n\tv_add_co_ci_u32_e64 v3, s2, v2, v3, s2\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n\tscratch_store_b64 off, v[1:2], off offset:308 ; 8-byte Folded Spill\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:280 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v40, 0\n\tv_readlane_b32 s13, v40, 1\n\tv_readlane_b32 s12, v40, 2\n\tv_readlane_b32 s10, v40, 3\n\tv_readlane_b32 s11, v40, 4\n\tv_readlane_b32 s8, v42, 12\n\tv_readlane_b32 s9, v42, 13\n\tv_readlane_b32 s4, v40, 7\n\tv_readlane_b32 s5, v40, 8\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:324 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:320 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:320 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v1, off offset:316 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_size@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_size@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s6, v42, 11\n\tv_readlane_b32 s4, v41, 15\n\tv_readlane_b32 s5, v41, 16\n\tv_readlane_b32 s2, v41, 29\n\tv_readlane_b32 s3, v41, 30\n\tv_readlane_b32 s0, v41, 19\n\tv_readlane_b32 s1, v41, 20\n\tv_mov_b32_e32 v3, v0\n\tscratch_load_b32 v0, off, off offset:316 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v5, v1\n\tscratch_load_b64 v[1:2], off, off offset:308 ; 8-byte Folded Reload\n ; implicit-def: $sgpr7\n ; implicit-def: $sgpr7\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n ; kill: def $vgpr3 killed $vgpr3 killed $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mul_lo_u32 v4, v0, v3\n ; implicit-def: $sgpr7\n\tv_mov_b32_e32 v0, s6\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s6, v0, v3\n\tv_add_co_ci_u32_e64 v2, s6, v1, v2, s6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tflat_load_b32 v4, v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v2, 31, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v1, v5\n\tv_add_co_u32 v2, s4, v2, v3\n\tv_add_co_ci_u32_e64 v0, s4, v0, v1, s4\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v0\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_u8 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, 1, v0\n\tv_cmp_eq_u32_e64 s1, v0, 1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v42, s0, 16\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v42, off offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB17_7\n; %bb.3: ; in Loop: Header=BB17_1 Depth=1\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v41, off, off offset:260 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v41, 25\n\tv_readlane_b32 s1, v41, 26\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v42, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_u8 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, 1, v0\n\tv_cmp_eq_u32_e64 s1, v0, 1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v42, s0, 17\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v42, off offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB17_5\n; %bb.4: ; in Loop: Header=BB17_1 Depth=1\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v41, off, off offset:260 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v42, off, off offset:264 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s2, v41, 29\n\tv_readlane_b32 s3, v41, 30\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s4, v42, 13\n\tv_readlane_b32 s5, v42, 14\n\tv_readlane_b32 s0, v41, 27\n\tv_readlane_b32 s1, v41, 28\n\tv_readlane_b32 s6, v42, 11\n\tv_readlane_b32 s7, v42, 12\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s1\n\tv_mov_b32_e32 v3, s0\n\tflat_load_b64 v[3:4], v[3:4]\n\ts_mov_b32 s0, 3\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[6:7], s0, v[0:1]\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v1, v9\n\tv_mov_b32_e32 v4, v7\n\tv_add_co_u32 v0, s0, v0, v5\n\tv_add_co_ci_u32_e64 v4, s0, v1, v4, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_store_b64 v[0:1], v[2:3]\n.LBB17_5: ; in Loop: Header=BB17_1 Depth=1\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v42, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v42, 17\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_branch .LBB17_7\n.LBB17_6: ; in Loop: Header=BB17_1 Depth=1\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v42, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v42, 9\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v42, 6\n\tv_readlane_b32 s1, v42, 8\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v42, s1, 5\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v42, s1, 4\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v42, s1, 18\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v42, off offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB17_1\n\ts_branch .LBB17_15\n.LBB17_7: ; in Loop: Header=BB17_1 Depth=1\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v41, off, off offset:260 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v42, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v42, 16\n\ts_or_b32 exec_lo, exec_lo, s2\n\tv_readlane_b32 s0, v41, 19\n\tv_readlane_b32 s1, v41, 20\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_u8 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, 1, v0\n\tv_cmp_eq_u32_e64 s1, v0, 1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v42, s0, 19\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v42, off offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB17_13\n; %bb.8: ; in Loop: Header=BB17_1 Depth=1\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v41, off, off offset:260 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v41, 25\n\tv_readlane_b32 s1, v41, 26\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v42, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_u8 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, 1, v0\n\tv_cmp_eq_u32_e64 s1, v0, 1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v42, s0, 20\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v42, off offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB17_12\n; %bb.9: ; in Loop: Header=BB17_1 Depth=1\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v41, off, off offset:260 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v41, 11\n\tv_readlane_b32 s1, v41, 12\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v42, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_u8 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, 1, v0\n\tv_cmp_eq_u32_e64 s1, v0, 1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v42, s0, 21\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v42, off offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB17_11\n; %bb.10: ; in Loop: Header=BB17_1 Depth=1\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v41, off, off offset:260 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v42, off, off offset:264 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v42, 17\n\tv_readlane_b32 s3, v42, 18\n\tv_readlane_b32 s4, v41, 29\n\tv_readlane_b32 s5, v41, 30\n\tv_readlane_b32 s6, v42, 13\n\tv_readlane_b32 s7, v42, 14\n\tv_readlane_b32 s0, v41, 27\n\tv_readlane_b32 s1, v41, 28\n\tv_readlane_b32 s8, v42, 11\n\tv_readlane_b32 s9, v42, 12\n\tv_mov_b32_e32 v0, s8\n\tv_mov_b32_e32 v1, s9\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b32 s0, 3\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[1:2], s0, v[0:1]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1] offset:8\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b64 v[10:11], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\ts_waitcnt vmcnt(1) lgkmcnt(1)\n\tv_mov_b32_e32 v0, v10\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v1, v11\n\tv_mov_b32_e32 v4, v7\n\tv_add_co_u32 v0, s1, v0, v5\n\tv_add_co_ci_u32_e64 v4, s1, v1, v4, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_lshlrev_b64 v[6:7], s0, v[0:1]\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v1, v9\n\tv_mov_b32_e32 v4, v7\n\tv_add_co_u32 v0, s0, v0, v5\n\tv_add_co_ci_u32_e64 v4, s0, v1, v4, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_store_b64 v[0:1], v[2:3]\n.LBB17_11: ; in Loop: Header=BB17_1 Depth=1\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v42, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v42, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB17_12: ; in Loop: Header=BB17_1 Depth=1\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v42, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v42, 20\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB17_13: ; in Loop: Header=BB17_1 Depth=1\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v41, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v42, off, off offset:264 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s2, v41, 19\n\ts_or_b32 exec_lo, exec_lo, s2\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s14, v42, 0\n\tv_readlane_b32 s13, v42, 1\n\tv_readlane_b32 s12, v42, 2\n\tv_readlane_b32 s10, v42, 3\n\tv_readlane_b32 s11, v42, 4\n\tv_readlane_b32 s4, v42, 7\n\tv_readlane_b32 s5, v42, 8\n\tv_readlane_b32 s0, v42, 5\n\tv_readlane_b32 s1, v42, 6\n\tscratch_load_b32 v31, off, off offset:280 ; 4-byte Folded Reload\n\ts_mov_b64 s[6:7], 0x48\n\ts_mov_b32 s2, s0\n\ts_mov_b32 s0, s1\n\ts_mov_b32 s3, s6\n\ts_mov_b32 s1, s7\n\ts_add_u32 s8, s2, s3\n\ts_addc_u32 s0, s0, s1\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, _Z13__syncthreadsv@rel32@lo+4\n\ts_addc_u32 s1, s1, _Z13__syncthreadsv@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n; %bb.14: ; in Loop: Header=BB17_1 Depth=1\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v41, off, off offset:260 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v42, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v42, 7\n\tv_readlane_b32 s2, v41, 23\n\tv_readlane_b32 s3, v41, 24\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\ts_mov_b32 s1, 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v2, v0, s1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b32 v[0:1], v2\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v42, s0, 8\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v42, off offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_branch .LBB17_6\n.LBB17_15:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v42, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v42, 18\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.16:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v42, off, off offset:264 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s14, v42, 0\n\tv_readlane_b32 s13, v42, 1\n\tv_readlane_b32 s12, v42, 2\n\tv_readlane_b32 s10, v42, 3\n\tv_readlane_b32 s11, v42, 4\n\tv_readlane_b32 s4, v42, 7\n\tv_readlane_b32 s5, v42, 8\n\tv_readlane_b32 s0, v42, 5\n\tv_readlane_b32 s1, v42, 6\n\tscratch_load_b32 v31, off, off offset:280 ; 4-byte Folded Reload\n\ts_mov_b64 s[6:7], 0x48\n\ts_mov_b32 s2, s0\n\ts_mov_b32 s0, s1\n\ts_mov_b32 s3, s6\n\ts_mov_b32 s1, s7\n\ts_add_u32 s8, s2, s3\n\ts_addc_u32 s0, s0, s1\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, _Z13__syncthreadsv@rel32@lo+4\n\ts_addc_u32 s1, s1, _Z13__syncthreadsv@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 448\n\t\t.amdhsa_kernarg_size 328\n\t\t.amdhsa_user_sgpr_count 13\n\t\t.amdhsa_user_sgpr_dispatch_ptr 1\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 1\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 1\n\t\t.amdhsa_enable_private_segment 1\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 1\n\t\t.amdhsa_system_sgpr_workgroup_id_z 1\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 2\n\t\t.amdhsa_next_free_vgpr 43\n\t\t.amdhsa_next_free_sgpr 68\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end17:\n\t.size\t_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii, .Lfunc_end17-_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 7856\n; NumSgprs: 70\n; NumVgprs: 43\n; ScratchSize: 448\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 8\n; VGPRBlocks: 5\n; NumSGPRsForWavesPerEU: 70\n; NumVGPRsForWavesPerEU: 43\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1\n; COMPUTE_PGM_RSRC2:USER_SGPR: 13\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__const.__assert_fail.fmt,@object ; @__const.__assert_fail.fmt\n\t.section\t.rodata.str1.16,\"aMS\",@progbits,1\n\t.p2align\t4, 0x0\n__const.__assert_fail.fmt:\n\t.asciz\t\"%s:%u: %s: Device-side assertion `%s' failed.\\n\"\n\t.size\t__const.__assert_fail.fmt, 47\n\n\t.protected\tblockIdx\n\t.protected\tblockDim\n\t.protected\tgridDim\n\t.protected\tthreadIdx\n\t.type\t.str,@object ; @.str\n\t.section\t.rodata.str1.1,\"aMS\",@progbits,1\n.str:\n\t.asciz\t\"workgroup\"\n\t.size\t.str, 10\n\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.hidden\t__oclc_ABI_version ; @__oclc_ABI_version\n\t.type\t__oclc_ABI_version,@object\n\t.section\t.rodata,\"a\",@progbits\n\t.weak\t__oclc_ABI_version\n\t.p2align\t2, 0x0\n__oclc_ABI_version:\n\t.long\t500 ; 0x1f4\n\t.size\t__oclc_ABI_version, 4\n\n\t.weak\tblockIdx\n\t.weak\tblockDim\n\t.weak\tgridDim\n\t.weak\tthreadIdx\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 16\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 24\n .size: 8\n .value_kind: global_buffer\n - .offset: 32\n .size: 8\n .value_kind: by_value\n - .offset: 40\n .size: 8\n .value_kind: by_value\n - .offset: 48\n .size: 8\n .value_kind: by_value\n - .offset: 56\n .size: 4\n .value_kind: by_value\n - .offset: 60\n .size: 4\n .value_kind: by_value\n - .offset: 64\n .size: 4\n .value_kind: by_value\n - .offset: 72\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 76\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 80\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 84\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 86\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 88\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 90\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 92\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 94\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 112\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 120\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 128\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 136\n .size: 2\n .value_kind: hidden_grid_dims\n - .offset: 152\n .size: 8\n .value_kind: hidden_hostcall_buffer\n - .offset: 160\n .size: 8\n .value_kind: hidden_multigrid_sync_arg\n - .offset: 168\n .size: 8\n .value_kind: hidden_heap_v1\n - .offset: 176\n .size: 8\n .value_kind: hidden_default_queue\n - .offset: 272\n .size: 8\n .value_kind: hidden_queue_ptr\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 328\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii\n .private_segment_fixed_size: 448\n .sgpr_count: 70\n .sgpr_spill_count: 88\n .symbol: _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: true\n .vgpr_count: 43\n .vgpr_spill_count: 28\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162583,"cells":{"id":{"kind":"string","value":"82a2aab1107aa5357c543759d50bc39a7697cc42_O1"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z8sumOnGpuPiS_S_i --------------------------\n .section .text._Z8sumOnGpuPiS_S_i,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=12\"\n .align 128\n\n\n\n\n .global _Z8sumOnGpuPiS_S_i\n .type _Z8sumOnGpuPiS_S_i,@function\n .size _Z8sumOnGpuPiS_S_i,(.L_x_1 - _Z8sumOnGpuPiS_S_i)\n .other _Z8sumOnGpuPiS_S_i,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z8sumOnGpuPiS_S_i:\n.text._Z8sumOnGpuPiS_S_i:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ S2R R6, SR_TID.X ;\n /*0020*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*0030*/ S2R R3, SR_CTAID.X ;\n /*0040*/ IMAD R6, R3, c[0x0][0x0], R6 ;\n /*0050*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ;\n /*0060*/ @P0 EXIT ;\n /*0070*/ MOV R7, 0x4 ;\n /*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ;\n /*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ;\n /*00a0*/ LDG.E R4, [R4.64] ;\n /*00b0*/ LDG.E R3, [R2.64] ;\n /*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ;\n /*00d0*/ IADD3 R9, R4, R3, RZ ;\n /*00e0*/ STG.E [R6.64], R9 ;\n /*00f0*/ EXIT ;\n.L_x_0:\n /*0100*/ BRA `(.L_x_0);\n /*0110*/ NOP;\n /*0120*/ NOP;\n /*0130*/ NOP;\n /*0140*/ NOP;\n /*0150*/ NOP;\n /*0160*/ NOP;\n /*0170*/ NOP;\n /*0180*/ NOP;\n /*0190*/ NOP;\n /*01a0*/ NOP;\n /*01b0*/ NOP;\n /*01c0*/ NOP;\n /*01d0*/ NOP;\n /*01e0*/ NOP;\n /*01f0*/ NOP;\n.L_x_1:\n"},"hip":{"kind":"string","value":"\t.text\n\t.file\t\"VectSumClassExample.hip\"\n\t.globl\t_Z23__device_stub__sumOnGpuPiS_S_i # -- Begin function _Z23__device_stub__sumOnGpuPiS_S_i\n\t.p2align\t4, 0x90\n\t.type\t_Z23__device_stub__sumOnGpuPiS_S_i,@function\n_Z23__device_stub__sumOnGpuPiS_S_i: # @_Z23__device_stub__sumOnGpuPiS_S_i\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$120, %rsp\n\t.cfi_def_cfa_offset 128\n\tmovq\t%rdi, 72(%rsp)\n\tmovq\t%rsi, 64(%rsp)\n\tmovq\t%rdx, 56(%rsp)\n\tmovl\t%ecx, 4(%rsp)\n\tleaq\t72(%rsp), %rax\n\tmovq\t%rax, 80(%rsp)\n\tleaq\t64(%rsp), %rax\n\tmovq\t%rax, 88(%rsp)\n\tleaq\t56(%rsp), %rax\n\tmovq\t%rax, 96(%rsp)\n\tleaq\t4(%rsp), %rax\n\tmovq\t%rax, 104(%rsp)\n\tleaq\t40(%rsp), %rdi\n\tleaq\t24(%rsp), %rsi\n\tleaq\t16(%rsp), %rdx\n\tleaq\t8(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t40(%rsp), %rsi\n\tmovl\t48(%rsp), %edx\n\tmovq\t24(%rsp), %rcx\n\tmovl\t32(%rsp), %r8d\n\tleaq\t80(%rsp), %r9\n\tmovl\t$_Z8sumOnGpuPiS_S_i, %edi\n\tpushq\t8(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t24(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$136, %rsp\n\t.cfi_adjust_cfa_offset -136\n\tretq\n.Lfunc_end0:\n\t.size\t_Z23__device_stub__sumOnGpuPiS_S_i, .Lfunc_end0-_Z23__device_stub__sumOnGpuPiS_S_i\n\t.cfi_endproc\n # -- End function\n\t.globl\t_Z8sumOnCpuPiS_S_i # -- Begin function _Z8sumOnCpuPiS_S_i\n\t.p2align\t4, 0x90\n\t.type\t_Z8sumOnCpuPiS_S_i,@function\n_Z8sumOnCpuPiS_S_i: # @_Z8sumOnCpuPiS_S_i\n\t.cfi_startproc\n# %bb.0:\n\ttestl\t%ecx, %ecx\n\tjle\t.LBB1_6\n# %bb.1:\n\tmovl\t%ecx, %r8d\n\tmovl\t%r8d, %eax\n\tandl\t$3, %eax\n\tcmpl\t$4, %ecx\n\tjae\t.LBB1_7\n# %bb.2:\n\txorl\t%ecx, %ecx\n\tjmp\t.LBB1_3\n.LBB1_7:\n\tandl\t$2147483644, %r8d # imm = 0x7FFFFFFC\n\txorl\t%ecx, %ecx\n\t.p2align\t4, 0x90\n.LBB1_8: # =>This Inner Loop Header: Depth=1\n\tmovl\t(%rsi,%rcx,4), %r9d\n\taddl\t(%rdi,%rcx,4), %r9d\n\tmovl\t%r9d, (%rdx,%rcx,4)\n\tmovl\t4(%rsi,%rcx,4), %r9d\n\taddl\t4(%rdi,%rcx,4), %r9d\n\tmovl\t%r9d, 4(%rdx,%rcx,4)\n\tmovl\t8(%rsi,%rcx,4), %r9d\n\taddl\t8(%rdi,%rcx,4), %r9d\n\tmovl\t%r9d, 8(%rdx,%rcx,4)\n\tmovl\t12(%rsi,%rcx,4), %r9d\n\taddl\t12(%rdi,%rcx,4), %r9d\n\tmovl\t%r9d, 12(%rdx,%rcx,4)\n\taddq\t$4, %rcx\n\tcmpq\t%rcx, %r8\n\tjne\t.LBB1_8\n.LBB1_3:\n\ttestq\t%rax, %rax\n\tje\t.LBB1_6\n# %bb.4:\n\tleaq\t(%rdx,%rcx,4), %rdx\n\tleaq\t(%rsi,%rcx,4), %rsi\n\tleaq\t(%rdi,%rcx,4), %rcx\n\txorl\t%edi, %edi\n\t.p2align\t4, 0x90\n.LBB1_5: # =>This Inner Loop Header: Depth=1\n\tmovl\t(%rsi,%rdi,4), %r8d\n\taddl\t(%rcx,%rdi,4), %r8d\n\tmovl\t%r8d, (%rdx,%rdi,4)\n\tincq\t%rdi\n\tcmpq\t%rdi, %rax\n\tjne\t.LBB1_5\n.LBB1_6:\n\tretq\n.Lfunc_end1:\n\t.size\t_Z8sumOnCpuPiS_S_i, .Lfunc_end1-_Z8sumOnCpuPiS_S_i\n\t.cfi_endproc\n # -- End function\n\t.globl\t_Z13randomNumbersPii # -- Begin function _Z13randomNumbersPii\n\t.p2align\t4, 0x90\n\t.type\t_Z13randomNumbersPii,@function\n_Z13randomNumbersPii: # @_Z13randomNumbersPii\n\t.cfi_startproc\n# %bb.0:\n\ttestl\t%esi, %esi\n\tjle\t.LBB2_4\n# %bb.1:\n\tpushq\t%r15\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 32\n\t.cfi_offset %rbx, -32\n\t.cfi_offset %r14, -24\n\t.cfi_offset %r15, -16\n\tmovq\t%rdi, %rbx\n\tmovl\t%esi, %r14d\n\txorl\t%r15d, %r15d\n\t.p2align\t4, 0x90\n.LBB2_2: # =>This Inner Loop Header: Depth=1\n\tcallq\trand\n\tcltq\n\timulq\t$351843721, %rax, %rcx # imm = 0x14F8B589\n\tmovq\t%rcx, %rdx\n\tshrq\t$63, %rdx\n\tsarq\t$45, %rcx\n\taddl\t%edx, %ecx\n\timull\t$100000, %ecx, %ecx # imm = 0x186A0\n\tsubl\t%ecx, %eax\n\tmovl\t%eax, (%rbx,%r15,4)\n\tincq\t%r15\n\tcmpq\t%r15, %r14\n\tjne\t.LBB2_2\n# %bb.3:\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 16\n\tpopq\t%r15\n\t.cfi_def_cfa_offset 8\n\t.cfi_restore %rbx\n\t.cfi_restore %r14\n\t.cfi_restore %r15\n.LBB2_4:\n\tretq\n.Lfunc_end2:\n\t.size\t_Z13randomNumbersPii, .Lfunc_end2-_Z13randomNumbersPii\n\t.cfi_endproc\n # -- End function\n\t.globl\t_Z7comparePiS_i # -- Begin function _Z7comparePiS_i\n\t.p2align\t4, 0x90\n\t.type\t_Z7comparePiS_i,@function\n_Z7comparePiS_i: # @_Z7comparePiS_i\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%r15\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpushq\t%r13\n\t.cfi_def_cfa_offset 32\n\tpushq\t%r12\n\t.cfi_def_cfa_offset 40\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 48\n\t.cfi_offset %rbx, -48\n\t.cfi_offset %r12, -40\n\t.cfi_offset %r13, -32\n\t.cfi_offset %r14, -24\n\t.cfi_offset %r15, -16\n\ttestl\t%edx, %edx\n\tjle\t.LBB3_1\n# %bb.2:\n\tmovq\t%rsi, %r14\n\tmovq\t%rdi, %r15\n\tmovl\t%edx, %r13d\n\tmovl\t$1, %ebx\n\txorl\t%r12d, %r12d\n\tjmp\t.LBB3_3\n\t.p2align\t4, 0x90\n.LBB3_5: # in Loop: Header=BB3_3 Depth=1\n\tincq\t%r12\n\tcmpq\t%r12, %r13\n\tje\t.LBB3_6\n.LBB3_3: # =>This Inner Loop Header: Depth=1\n\tmovl\t(%r15,%r12,4), %edx\n\tmovl\t(%r14,%r12,4), %r8d\n\tcmpl\t%r8d, %edx\n\tje\t.LBB3_5\n# %bb.4: # in Loop: Header=BB3_3 Depth=1\n\txorl\t%ebx, %ebx\n\tmovl\t$.L.str, %edi\n\tmovl\t%r12d, %esi\n\tmovl\t%r12d, %ecx\n\txorl\t%eax, %eax\n\tcallq\tprintf\n\tjmp\t.LBB3_5\n.LBB3_6:\n\ttestl\t%ebx, %ebx\n\tmovl\t$.Lstr, %eax\n\tmovl\t$.Lstr.5, %edi\n\tcmoveq\t%rax, %rdi\n\tjmp\t.LBB3_7\n.LBB3_1:\n\tmovl\t$1, %ebx\n\tmovl\t$.Lstr.5, %edi\n.LBB3_7:\n\tcallq\tputs@PLT\n\tmovl\t%ebx, %eax\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 40\n\tpopq\t%r12\n\t.cfi_def_cfa_offset 32\n\tpopq\t%r13\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 16\n\tpopq\t%r15\n\t.cfi_def_cfa_offset 8\n\tretq\n.Lfunc_end3:\n\t.size\t_Z7comparePiS_i, .Lfunc_end3-_Z7comparePiS_i\n\t.cfi_endproc\n # -- End function\n\t.section\t.rodata.cst8,\"aM\",@progbits,8\n\t.p2align\t3, 0x0 # -- Begin function main\n.LCPI4_0:\n\t.quad\t0x412e848000000000 # double 1.0E+6\n\t.text\n\t.globl\tmain\n\t.p2align\t4, 0x90\n\t.type\tmain,@function\nmain: # @main\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rbp\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r15\n\t.cfi_def_cfa_offset 24\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 32\n\tpushq\t%r13\n\t.cfi_def_cfa_offset 40\n\tpushq\t%r12\n\t.cfi_def_cfa_offset 48\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 56\n\tsubq\t$152, %rsp\n\t.cfi_def_cfa_offset 208\n\t.cfi_offset %rbx, -56\n\t.cfi_offset %r12, -48\n\t.cfi_offset %r13, -40\n\t.cfi_offset %r14, -32\n\t.cfi_offset %r15, -24\n\t.cfi_offset %rbp, -16\n\tmovl\t$67108864, %edi # imm = 0x4000000\n\tcallq\tmalloc\n\tmovq\t%rax, %rbx\n\tmovl\t$67108864, %edi # imm = 0x4000000\n\tcallq\tmalloc\n\tmovq\t%rax, %r14\n\tmovl\t$67108864, %edi # imm = 0x4000000\n\tcallq\tmalloc\n\tmovq\t%rax, %r15\n\tleaq\t24(%rsp), %rdi\n\tmovl\t$67108864, %esi # imm = 0x4000000\n\tcallq\thipMalloc\n\tleaq\t16(%rsp), %rdi\n\tmovl\t$67108864, %esi # imm = 0x4000000\n\tcallq\thipMalloc\n\tleaq\t8(%rsp), %rdi\n\tmovl\t$67108864, %esi # imm = 0x4000000\n\tcallq\thipMalloc\n\txorl\t%r12d, %r12d\n\t.p2align\t4, 0x90\n.LBB4_1: # =>This Inner Loop Header: Depth=1\n\tcallq\trand\n\tcltq\n\timulq\t$351843721, %rax, %rcx # imm = 0x14F8B589\n\tmovq\t%rcx, %rdx\n\tshrq\t$63, %rdx\n\tsarq\t$45, %rcx\n\taddl\t%edx, %ecx\n\timull\t$100000, %ecx, %ecx # imm = 0x186A0\n\tsubl\t%ecx, %eax\n\tmovl\t%eax, (%rbx,%r12,4)\n\tincq\t%r12\n\tcmpq\t$16777216, %r12 # imm = 0x1000000\n\tjne\t.LBB4_1\n# %bb.2:\n\txorl\t%r12d, %r12d\n\t.p2align\t4, 0x90\n.LBB4_3: # =>This Inner Loop Header: Depth=1\n\tcallq\trand\n\tcltq\n\timulq\t$351843721, %rax, %rcx # imm = 0x14F8B589\n\tmovq\t%rcx, %rdx\n\tshrq\t$63, %rdx\n\tsarq\t$45, %rcx\n\taddl\t%edx, %ecx\n\timull\t$100000, %ecx, %ecx # imm = 0x186A0\n\tsubl\t%ecx, %eax\n\tmovl\t%eax, (%r14,%r12,4)\n\tincq\t%r12\n\tcmpq\t$16777216, %r12 # imm = 0x1000000\n\tjne\t.LBB4_3\n# %bb.4:\n\tmovq\t24(%rsp), %rdi\n\tmovl\t$67108864, %edx # imm = 0x4000000\n\tmovq\t%rbx, %rsi\n\tmovl\t$1, %ecx\n\tcallq\thipMemcpy\n\tmovq\t16(%rsp), %rdi\n\tmovl\t$67108864, %edx # imm = 0x4000000\n\tmovq\t%r14, %rsi\n\tmovl\t$1, %ecx\n\tcallq\thipMemcpy\n\tcallq\tclock\n\tmovq\t%rax, %r12\n\tmovabsq\t$4294967808, %rdx # imm = 0x100000200\n\tleaq\t32256(%rdx), %rdi\n\tmovl\t$1, %esi\n\tmovl\t$1, %ecx\n\txorl\t%r8d, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipPushCallConfiguration\n\ttestl\t%eax, %eax\n\tjne\t.LBB4_6\n# %bb.5:\n\tmovq\t24(%rsp), %rax\n\tmovq\t16(%rsp), %rcx\n\tmovq\t8(%rsp), %rdx\n\tmovq\t%rax, 104(%rsp)\n\tmovq\t%rcx, 96(%rsp)\n\tmovq\t%rdx, 88(%rsp)\n\tmovl\t$16777216, 36(%rsp) # imm = 0x1000000\n\tleaq\t104(%rsp), %rax\n\tmovq\t%rax, 112(%rsp)\n\tleaq\t96(%rsp), %rax\n\tmovq\t%rax, 120(%rsp)\n\tleaq\t88(%rsp), %rax\n\tmovq\t%rax, 128(%rsp)\n\tleaq\t36(%rsp), %rax\n\tmovq\t%rax, 136(%rsp)\n\tleaq\t72(%rsp), %rdi\n\tleaq\t56(%rsp), %rsi\n\tleaq\t48(%rsp), %rdx\n\tleaq\t40(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t72(%rsp), %rsi\n\tmovl\t80(%rsp), %edx\n\tmovq\t56(%rsp), %rcx\n\tmovl\t64(%rsp), %r8d\n\tleaq\t112(%rsp), %r9\n\tmovl\t$_Z8sumOnGpuPiS_S_i, %edi\n\tpushq\t40(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t56(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$16, %rsp\n\t.cfi_adjust_cfa_offset -16\n.LBB4_6:\n\tcallq\tclock\n\tcvtsi2sd\t%rax, %xmm0\n\tcvtsi2sd\t%r12, %xmm1\n\tsubsd\t%xmm1, %xmm0\n\tdivsd\t.LCPI4_0(%rip), %xmm0\n\tmovl\t$.L.str.3, %edi\n\tmovb\t$1, %al\n\tcallq\tprintf\n\tmovq\t8(%rsp), %rsi\n\tmovl\t$67108864, %edx # imm = 0x4000000\n\tmovq\t%r15, %rdi\n\tmovl\t$2, %ecx\n\tcallq\thipMemcpy\n\tmovl\t$67108864, %edi # imm = 0x4000000\n\tcallq\tmalloc\n\tmovq\t%rax, %r12\n\tmovl\t$3, %ebp\n\tcallq\tclock\n\tmovq\t%rax, %r13\n\t.p2align\t4, 0x90\n.LBB4_7: # =>This Inner Loop Header: Depth=1\n\tmovl\t-12(%r14,%rbp,4), %eax\n\taddl\t-12(%rbx,%rbp,4), %eax\n\tmovl\t-8(%r14,%rbp,4), %ecx\n\taddl\t-8(%rbx,%rbp,4), %ecx\n\tmovl\t%eax, -12(%r12,%rbp,4)\n\tmovl\t-4(%r14,%rbp,4), %eax\n\taddl\t-4(%rbx,%rbp,4), %eax\n\tmovl\t%ecx, -8(%r12,%rbp,4)\n\tmovl\t(%r14,%rbp,4), %ecx\n\taddl\t(%rbx,%rbp,4), %ecx\n\tmovl\t%eax, -4(%r12,%rbp,4)\n\tmovl\t%ecx, (%r12,%rbp,4)\n\taddq\t$4, %rbp\n\tcmpq\t$16777219, %rbp # imm = 0x1000003\n\tjne\t.LBB4_7\n# %bb.8:\n\tcallq\tclock\n\txorps\t%xmm0, %xmm0\n\tcvtsi2sd\t%rax, %xmm0\n\txorps\t%xmm1, %xmm1\n\tcvtsi2sd\t%r13, %xmm1\n\tsubsd\t%xmm1, %xmm0\n\tdivsd\t.LCPI4_0(%rip), %xmm0\n\tmovl\t$.L.str.4, %edi\n\tmovb\t$1, %al\n\tcallq\tprintf\n\tmovl\t$1, %ebp\n\txorl\t%r13d, %r13d\n\tjmp\t.LBB4_9\n\t.p2align\t4, 0x90\n.LBB4_11: # in Loop: Header=BB4_9 Depth=1\n\tincq\t%r13\n\tcmpq\t$16777216, %r13 # imm = 0x1000000\n\tje\t.LBB4_12\n.LBB4_9: # =>This Inner Loop Header: Depth=1\n\tmovl\t(%r15,%r13,4), %edx\n\tmovl\t(%r12,%r13,4), %r8d\n\tcmpl\t%r8d, %edx\n\tje\t.LBB4_11\n# %bb.10: # in Loop: Header=BB4_9 Depth=1\n\txorl\t%ebp, %ebp\n\tmovl\t$.L.str, %edi\n\tmovl\t%r13d, %esi\n\tmovl\t%r13d, %ecx\n\txorl\t%eax, %eax\n\tcallq\tprintf\n\tjmp\t.LBB4_11\n.LBB4_12:\n\ttestl\t%ebp, %ebp\n\tmovl\t$.Lstr, %eax\n\tmovl\t$.Lstr.5, %edi\n\tcmoveq\t%rax, %rdi\n\tcallq\tputs@PLT\n\tmovq\t%rbx, %rdi\n\tcallq\tfree\n\tmovq\t%r14, %rdi\n\tcallq\tfree\n\tmovq\t%r15, %rdi\n\tcallq\tfree\n\tmovq\t%r12, %rdi\n\tcallq\tfree\n\tmovq\t24(%rsp), %rdi\n\tcallq\thipFree\n\tmovq\t16(%rsp), %rdi\n\tcallq\thipFree\n\tmovq\t8(%rsp), %rdi\n\tcallq\thipFree\n\txorl\t%eax, %eax\n\taddq\t$152, %rsp\n\t.cfi_def_cfa_offset 56\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 48\n\tpopq\t%r12\n\t.cfi_def_cfa_offset 40\n\tpopq\t%r13\n\t.cfi_def_cfa_offset 32\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r15\n\t.cfi_def_cfa_offset 16\n\tpopq\t%rbp\n\t.cfi_def_cfa_offset 8\n\tretq\n.Lfunc_end4:\n\t.size\tmain, .Lfunc_end4-main\n\t.cfi_endproc\n # -- End function\n\t.p2align\t4, 0x90 # -- Begin function __hip_module_ctor\n\t.type\t__hip_module_ctor,@function\n__hip_module_ctor: # @__hip_module_ctor\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$40, %rsp\n\t.cfi_def_cfa_offset 48\n\tmovq\t__hip_gpubin_handle(%rip), %rdi\n\ttestq\t%rdi, %rdi\n\tjne\t.LBB5_2\n# %bb.1:\n\tmovl\t$__hip_fatbin_wrapper, %edi\n\tcallq\t__hipRegisterFatBinary\n\tmovq\t%rax, %rdi\n\tmovq\t%rax, __hip_gpubin_handle(%rip)\n.LBB5_2:\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, 16(%rsp)\n\tmovups\t%xmm0, (%rsp)\n\tmovl\t$_Z8sumOnGpuPiS_S_i, %esi\n\tmovl\t$.L__unnamed_1, %edx\n\tmovl\t$.L__unnamed_1, %ecx\n\tmovl\t$-1, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipRegisterFunction\n\tmovl\t$__hip_module_dtor, %edi\n\taddq\t$40, %rsp\n\t.cfi_def_cfa_offset 8\n\tjmp\tatexit # TAILCALL\n.Lfunc_end5:\n\t.size\t__hip_module_ctor, .Lfunc_end5-__hip_module_ctor\n\t.cfi_endproc\n # -- End function\n\t.p2align\t4, 0x90 # -- Begin function __hip_module_dtor\n\t.type\t__hip_module_dtor,@function\n__hip_module_dtor: # @__hip_module_dtor\n\t.cfi_startproc\n# %bb.0:\n\tmovq\t__hip_gpubin_handle(%rip), %rdi\n\ttestq\t%rdi, %rdi\n\tje\t.LBB6_2\n# %bb.1:\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 16\n\tcallq\t__hipUnregisterFatBinary\n\tmovq\t$0, __hip_gpubin_handle(%rip)\n\taddq\t$8, %rsp\n\t.cfi_def_cfa_offset 8\n.LBB6_2:\n\tretq\n.Lfunc_end6:\n\t.size\t__hip_module_dtor, .Lfunc_end6-__hip_module_dtor\n\t.cfi_endproc\n # -- End function\n\t.type\t_Z8sumOnGpuPiS_S_i,@object # @_Z8sumOnGpuPiS_S_i\n\t.section\t.rodata,\"a\",@progbits\n\t.globl\t_Z8sumOnGpuPiS_S_i\n\t.p2align\t3, 0x0\n_Z8sumOnGpuPiS_S_i:\n\t.quad\t_Z23__device_stub__sumOnGpuPiS_S_i\n\t.size\t_Z8sumOnGpuPiS_S_i, 8\n\n\t.type\t.L.str,@object # @.str\n\t.section\t.rodata.str1.1,\"aMS\",@progbits,1\n.L.str:\n\t.asciz\t\"Different values at a[%i] = %i and b[%i] = %i \\n\"\n\t.size\t.L.str, 48\n\n\t.type\t.L.str.3,@object # @.str.3\n.L.str.3:\n\t.asciz\t\"time on GPU %f \\n\"\n\t.size\t.L.str.3, 17\n\n\t.type\t.L.str.4,@object # @.str.4\n.L.str.4:\n\t.asciz\t\"time on CPU %f \\n\"\n\t.size\t.L.str.4, 17\n\n\t.type\t.L__unnamed_1,@object # @0\n.L__unnamed_1:\n\t.asciz\t\"_Z8sumOnGpuPiS_S_i\"\n\t.size\t.L__unnamed_1, 19\n\n\t.type\t__hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper\n\t.section\t.hipFatBinSegment,\"a\",@progbits\n\t.p2align\t3, 0x0\n__hip_fatbin_wrapper:\n\t.long\t1212764230 # 0x48495046\n\t.long\t1 # 0x1\n\t.quad\t__hip_fatbin\n\t.quad\t0\n\t.size\t__hip_fatbin_wrapper, 24\n\n\t.type\t__hip_gpubin_handle,@object # @__hip_gpubin_handle\n\t.local\t__hip_gpubin_handle\n\t.comm\t__hip_gpubin_handle,8,8\n\t.section\t.init_array,\"aw\",@init_array\n\t.p2align\t3, 0x0\n\t.quad\t__hip_module_ctor\n\t.type\t__hip_cuid_,@object # @__hip_cuid_\n\t.bss\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 # 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.type\t.Lstr,@object # @str\n\t.section\t.rodata.str1.1,\"aMS\",@progbits,1\n.Lstr:\n\t.asciz\t\"args are different \"\n\t.size\t.Lstr, 20\n\n\t.type\t.Lstr.5,@object # @str.5\n.Lstr.5:\n\t.asciz\t\"args are the same \"\n\t.size\t.Lstr.5, 19\n\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n"}}},{"rowIdx":162584,"cells":{"id":{"kind":"string","value":"521ce922ea6ff1060451708dd55f62b582430a27_O0"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z25fluidStructureInteractionP15BoundaryElementi --------------------------\n .section .text._Z25fluidStructureInteractionP15BoundaryElementi,\"ax\",@progbits\n .sectionflags @\"SHF_BARRIERS=1\"\n .sectioninfo @\"SHI_REGISTERS=18\"\n .align 128\n\n\n\n\n .global _Z25fluidStructureInteractionP15BoundaryElementi\n .type _Z25fluidStructureInteractionP15BoundaryElementi,@function\n .size _Z25fluidStructureInteractionP15BoundaryElementi,(.L_x_10 - _Z25fluidStructureInteractionP15BoundaryElementi)\n .other _Z25fluidStructureInteractionP15BoundaryElementi,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z25fluidStructureInteractionP15BoundaryElementi:\n.text._Z25fluidStructureInteractionP15BoundaryElementi:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ MOV R12, c[0x0][0x118] ;\n /*0020*/ MOV R13, c[0x0][0x11c] ;\n /*0030*/ MOV R2, RZ ;\n /*0040*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0050*/ MOV R6, R2 ;\n /*0060*/ MOV R7, R3 ;\n /*0070*/ MOV R6, R6 ;\n /*0080*/ MOV R7, R7 ;\n /*0090*/ MOV R0, 0x8 ;\n /*00a0*/ LDC R0, c[0x0][R0+0x160] ;\n /*00b0*/ MOV R0, R0 ;\n /*00c0*/ MOV R6, R6 ;\n /*00d0*/ MOV R7, R7 ;\n /*00e0*/ S2R R4, SR_TID.X ;\n /*00f0*/ MOV R4, R4 ;\n /*0100*/ ISETP.GE.AND P0, PT, R4, R0, PT ;\n /*0110*/ IMAD.WIDE R2, R4, 0x24, RZ ;\n /*0120*/ MOV R0, R2 ;\n /*0130*/ MOV R5, R3 ;\n /*0140*/ IADD3 R2, P1, R6, R0, RZ ;\n /*0150*/ IADD3.X R5, R7, R5, RZ, P1, !PT ;\n /*0160*/ MOV R0, RZ ;\n /*0170*/ IMAD R3, R4, 0x24, R0 ;\n /*0180*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x80, 0x0 ;\n /*0190*/ MOV R0, R2 ;\n /*01a0*/ MOV R2, R5 ;\n /*01b0*/ MOV R3, R3 ;\n /*01c0*/ BSSY B0, `(.L_x_0) ;\n /*01d0*/ @P0 BRA `(.L_x_1) ;\n /*01e0*/ MOV R4, R0 ;\n /*01f0*/ MOV R5, R2 ;\n /*0200*/ MOV R4, R4 ;\n /*0210*/ MOV R5, R5 ;\n /*0220*/ R2UR UR4, R12 ;\n /*0230*/ R2UR UR5, R13 ;\n /*0240*/ LDG.E R4, [R4.64] ;\n /*0250*/ IADD3 R6, P1, R0, 0x4, RZ ;\n /*0260*/ IADD3.X R7, R2, RZ, RZ, P1, !PT ;\n /*0270*/ MOV R6, R6 ;\n /*0280*/ MOV R7, R7 ;\n /*0290*/ MOV R6, R6 ;\n /*02a0*/ MOV R7, R7 ;\n /*02b0*/ R2UR UR4, R12 ;\n /*02c0*/ R2UR UR5, R13 ;\n /*02d0*/ LDG.E R5, [R6.64] ;\n /*02e0*/ IADD3 R10, P1, R0, 0x8, RZ ;\n /*02f0*/ IADD3.X R11, R2, RZ, RZ, P1, !PT ;\n /*0300*/ MOV R10, R10 ;\n /*0310*/ MOV R11, R11 ;\n /*0320*/ MOV R10, R10 ;\n /*0330*/ MOV R11, R11 ;\n /*0340*/ R2UR UR4, R12 ;\n /*0350*/ R2UR UR5, R13 ;\n /*0360*/ LDG.E R10, [R10.64] ;\n /*0370*/ IADD3 R6, P1, R0, 0xc, RZ ;\n /*0380*/ IADD3.X R7, R2, RZ, RZ, P1, !PT ;\n /*0390*/ MOV R6, R6 ;\n /*03a0*/ MOV R7, R7 ;\n /*03b0*/ MOV R6, R6 ;\n /*03c0*/ MOV R7, R7 ;\n /*03d0*/ R2UR UR4, R12 ;\n /*03e0*/ R2UR UR5, R13 ;\n /*03f0*/ LDG.E R9, [R6.64] ;\n /*0400*/ IADD3 R6, P1, R0, 0x10, RZ ;\n /*0410*/ IADD3.X R7, R2, RZ, RZ, P1, !PT ;\n /*0420*/ MOV R6, R6 ;\n /*0430*/ MOV R7, R7 ;\n /*0440*/ MOV R6, R6 ;\n /*0450*/ MOV R7, R7 ;\n /*0460*/ R2UR UR4, R12 ;\n /*0470*/ R2UR UR5, R13 ;\n /*0480*/ LDG.E R8, [R6.64] ;\n /*0490*/ IADD3 R6, P1, R0, 0x14, RZ ;\n /*04a0*/ IADD3.X R7, R2, RZ, RZ, P1, !PT ;\n /*04b0*/ MOV R6, R6 ;\n /*04c0*/ MOV R7, R7 ;\n /*04d0*/ MOV R6, R6 ;\n /*04e0*/ MOV R7, R7 ;\n /*04f0*/ R2UR UR4, R12 ;\n /*0500*/ R2UR UR5, R13 ;\n /*0510*/ LDG.E R7, [R6.64] ;\n /*0520*/ IADD3 R14, P1, R0, 0x18, RZ ;\n /*0530*/ IADD3.X R15, R2, RZ, RZ, P1, !PT ;\n /*0540*/ MOV R14, R14 ;\n /*0550*/ MOV R15, R15 ;\n /*0560*/ MOV R14, R14 ;\n /*0570*/ MOV R15, R15 ;\n /*0580*/ R2UR UR4, R12 ;\n /*0590*/ R2UR UR5, R13 ;\n /*05a0*/ LDG.E R6, [R14.64] ;\n /*05b0*/ IADD3 R14, P1, R0, 0x1c, RZ ;\n /*05c0*/ IADD3.X R15, R2, RZ, RZ, P1, !PT ;\n /*05d0*/ MOV R14, R14 ;\n /*05e0*/ MOV R15, R15 ;\n /*05f0*/ MOV R14, R14 ;\n /*0600*/ MOV R15, R15 ;\n /*0610*/ R2UR UR4, R12 ;\n /*0620*/ R2UR UR5, R13 ;\n /*0630*/ LDG.E R11, [R14.64] ;\n /*0640*/ IADD3 R14, P1, R0, 0x20, RZ ;\n /*0650*/ IADD3.X R15, R2, RZ, RZ, P1, !PT ;\n /*0660*/ MOV R14, R14 ;\n /*0670*/ MOV R15, R15 ;\n /*0680*/ MOV R14, R14 ;\n /*0690*/ MOV R15, R15 ;\n /*06a0*/ R2UR UR4, R12 ;\n /*06b0*/ R2UR UR5, R13 ;\n /*06c0*/ LDG.E R14, [R14.64] ;\n /*06d0*/ MOV R3, R3 ;\n /*06e0*/ STS [R3], R4 ;\n /*06f0*/ IADD3 R4, R3, 0x4, RZ ;\n /*0700*/ MOV R4, R4 ;\n /*0710*/ STS [R4], R5 ;\n /*0720*/ IADD3 R4, R3, 0x8, RZ ;\n /*0730*/ MOV R4, R4 ;\n /*0740*/ STS [R4], R10 ;\n /*0750*/ IADD3 R4, R3, 0xc, RZ ;\n /*0760*/ MOV R4, R4 ;\n /*0770*/ STS [R4], R9 ;\n /*0780*/ IADD3 R4, R3, 0x10, RZ ;\n /*0790*/ MOV R4, R4 ;\n /*07a0*/ STS [R4], R8 ;\n /*07b0*/ IADD3 R4, R3, 0x14, RZ ;\n /*07c0*/ MOV R4, R4 ;\n /*07d0*/ STS [R4], R7 ;\n /*07e0*/ IADD3 R4, R3, 0x18, RZ ;\n /*07f0*/ MOV R4, R4 ;\n /*0800*/ STS [R4], R6 ;\n /*0810*/ IADD3 R4, R3, 0x1c, RZ ;\n /*0820*/ MOV R4, R4 ;\n /*0830*/ STS [R4], R11 ;\n /*0840*/ IADD3 R4, R3, 0x20, RZ ;\n /*0850*/ MOV R4, R4 ;\n /*0860*/ STS [R4], R14 ;\n.L_x_1:\n /*0870*/ BSYNC B0 ;\n.L_x_0:\n /*0880*/ BRA.CONV ~URZ, `(.L_x_2) ;\n /*0890*/ MOV R5, 0x8b0 ;\n /*08a0*/ CALL.REL.NOINC `($__internal_0_$__cuda_sm70_barrier_sync_0) ;\n /*08b0*/ BRA `(.L_x_3) ;\n.L_x_2:\n /*08c0*/ BAR.SYNC 0x0 ;\n.L_x_3:\n /*08d0*/ BSSY B0, `(.L_x_4) ;\n /*08e0*/ @P0 BRA `(.L_x_5) ;\n /*08f0*/ IADD3 R4, R3, 0xc, RZ ;\n /*0900*/ MOV R4, R4 ;\n /*0910*/ LDS R4, [R4] ;\n /*0920*/ FMUL R4, R4, 0.10000000149011611938 ;\n /*0930*/ IADD3 R5, R3, 0x18, RZ ;\n /*0940*/ MOV R5, R5 ;\n /*0950*/ STS [R5], R4 ;\n /*0960*/ IADD3 R4, R3, 0x10, RZ ;\n /*0970*/ MOV R4, R4 ;\n /*0980*/ LDS R4, [R4] ;\n /*0990*/ FMUL R4, R4, 0.10000000149011611938 ;\n /*09a0*/ IADD3 R5, R3, 0x1c, RZ ;\n /*09b0*/ MOV R5, R5 ;\n /*09c0*/ STS [R5], R4 ;\n /*09d0*/ IADD3 R4, R3, 0x14, RZ ;\n /*09e0*/ MOV R4, R4 ;\n /*09f0*/ LDS R4, [R4] ;\n /*0a00*/ FMUL R4, R4, 0.10000000149011611938 ;\n /*0a10*/ IADD3 R5, R3, 0x20, RZ ;\n /*0a20*/ MOV R5, R5 ;\n /*0a30*/ STS [R5], R4 ;\n.L_x_5:\n /*0a40*/ BSYNC B0 ;\n.L_x_4:\n /*0a50*/ BRA.CONV ~URZ, `(.L_x_6) ;\n /*0a60*/ MOV R5, 0xa80 ;\n /*0a70*/ CALL.REL.NOINC `($__internal_0_$__cuda_sm70_barrier_sync_0) ;\n /*0a80*/ BRA `(.L_x_7) ;\n.L_x_6:\n /*0a90*/ BAR.SYNC 0x0 ;\n.L_x_7:\n /*0aa0*/ @P0 BRA `(.L_x_8) ;\n /*0ab0*/ MOV R3, R3 ;\n /*0ac0*/ LDS R11, [R3] ;\n /*0ad0*/ IADD3 R4, R3, 0x4, RZ ;\n /*0ae0*/ MOV R4, R4 ;\n /*0af0*/ LDS R10, [R4] ;\n /*0b00*/ IADD3 R4, R3, 0x8, RZ ;\n /*0b10*/ MOV R4, R4 ;\n /*0b20*/ LDS R9, [R4] ;\n /*0b30*/ IADD3 R4, R3, 0xc, RZ ;\n /*0b40*/ MOV R4, R4 ;\n /*0b50*/ LDS R8, [R4] ;\n /*0b60*/ IADD3 R4, R3, 0x10, RZ ;\n /*0b70*/ MOV R4, R4 ;\n /*0b80*/ LDS R7, [R4] ;\n /*0b90*/ IADD3 R4, R3, 0x14, RZ ;\n /*0ba0*/ MOV R4, R4 ;\n /*0bb0*/ LDS R6, [R4] ;\n /*0bc0*/ IADD3 R4, R3, 0x18, RZ ;\n /*0bd0*/ MOV R4, R4 ;\n /*0be0*/ LDS R5, [R4] ;\n /*0bf0*/ IADD3 R4, R3, 0x1c, RZ ;\n /*0c00*/ MOV R4, R4 ;\n /*0c10*/ LDS R4, [R4] ;\n /*0c20*/ IADD3 R3, R3, 0x20, RZ ;\n /*0c30*/ MOV R3, R3 ;\n /*0c40*/ LDS R3, [R3] ;\n /*0c50*/ MOV R14, R0 ;\n /*0c60*/ MOV R15, R2 ;\n /*0c70*/ MOV R14, R14 ;\n /*0c80*/ MOV R15, R15 ;\n /*0c90*/ R2UR UR4, R12 ;\n /*0ca0*/ R2UR UR5, R13 ;\n /*0cb0*/ STG.E [R14.64], R11 ;\n /*0cc0*/ IADD3 R14, P0, R0, 0x4, RZ ;\n /*0cd0*/ IADD3.X R15, R2, RZ, RZ, P0, !PT ;\n /*0ce0*/ MOV R14, R14 ;\n /*0cf0*/ MOV R15, R15 ;\n /*0d00*/ MOV R14, R14 ;\n /*0d10*/ MOV R15, R15 ;\n /*0d20*/ R2UR UR4, R12 ;\n /*0d30*/ R2UR UR5, R13 ;\n /*0d40*/ STG.E [R14.64], R10 ;\n /*0d50*/ IADD3 R10, P0, R0, 0x8, RZ ;\n /*0d60*/ IADD3.X R11, R2, RZ, RZ, P0, !PT ;\n /*0d70*/ MOV R10, R10 ;\n /*0d80*/ MOV R11, R11 ;\n /*0d90*/ MOV R10, R10 ;\n /*0da0*/ MOV R11, R11 ;\n /*0db0*/ R2UR UR4, R12 ;\n /*0dc0*/ R2UR UR5, R13 ;\n /*0dd0*/ STG.E [R10.64], R9 ;\n /*0de0*/ IADD3 R10, P0, R0, 0xc, RZ ;\n /*0df0*/ IADD3.X R11, R2, RZ, RZ, P0, !PT ;\n /*0e00*/ MOV R10, R10 ;\n /*0e10*/ MOV R11, R11 ;\n /*0e20*/ MOV R10, R10 ;\n /*0e30*/ MOV R11, R11 ;\n /*0e40*/ R2UR UR4, R12 ;\n /*0e50*/ R2UR UR5, R13 ;\n /*0e60*/ STG.E [R10.64], R8 ;\n /*0e70*/ IADD3 R8, P0, R0, 0x10, RZ ;\n /*0e80*/ IADD3.X R9, R2, RZ, RZ, P0, !PT ;\n /*0e90*/ MOV R8, R8 ;\n /*0ea0*/ MOV R9, R9 ;\n /*0eb0*/ MOV R8, R8 ;\n /*0ec0*/ MOV R9, R9 ;\n /*0ed0*/ R2UR UR4, R12 ;\n /*0ee0*/ R2UR UR5, R13 ;\n /*0ef0*/ STG.E [R8.64], R7 ;\n /*0f00*/ IADD3 R8, P0, R0, 0x14, RZ ;\n /*0f10*/ IADD3.X R9, R2, RZ, RZ, P0, !PT ;\n /*0f20*/ MOV R8, R8 ;\n /*0f30*/ MOV R9, R9 ;\n /*0f40*/ MOV R8, R8 ;\n /*0f50*/ MOV R9, R9 ;\n /*0f60*/ R2UR UR4, R12 ;\n /*0f70*/ R2UR UR5, R13 ;\n /*0f80*/ STG.E [R8.64], R6 ;\n /*0f90*/ IADD3 R6, P0, R0, 0x18, RZ ;\n /*0fa0*/ IADD3.X R7, R2, RZ, RZ, P0, !PT ;\n /*0fb0*/ MOV R6, R6 ;\n /*0fc0*/ MOV R7, R7 ;\n /*0fd0*/ MOV R6, R6 ;\n /*0fe0*/ MOV R7, R7 ;\n /*0ff0*/ R2UR UR4, R12 ;\n /*1000*/ R2UR UR5, R13 ;\n /*1010*/ STG.E [R6.64], R5 ;\n /*1020*/ IADD3 R6, P0, R0, 0x1c, RZ ;\n /*1030*/ IADD3.X R7, R2, RZ, RZ, P0, !PT ;\n /*1040*/ MOV R6, R6 ;\n /*1050*/ MOV R7, R7 ;\n /*1060*/ MOV R6, R6 ;\n /*1070*/ MOV R7, R7 ;\n /*1080*/ R2UR UR4, R12 ;\n /*1090*/ R2UR UR5, R13 ;\n /*10a0*/ STG.E [R6.64], R4 ;\n /*10b0*/ IADD3 R4, P0, R0, 0x20, RZ ;\n /*10c0*/ IADD3.X R5, R2, RZ, RZ, P0, !PT ;\n /*10d0*/ MOV R4, R4 ;\n /*10e0*/ MOV R5, R5 ;\n /*10f0*/ MOV R4, R4 ;\n /*1100*/ MOV R5, R5 ;\n /*1110*/ R2UR UR4, R12 ;\n /*1120*/ R2UR UR5, R13 ;\n /*1130*/ STG.E [R4.64], R3 ;\n.L_x_8:\n /*1140*/ EXIT ;\n\n\n\n\n .weak $__internal_0_$__cuda_sm70_barrier_sync_0\n .type $__internal_0_$__cuda_sm70_barrier_sync_0,@function\n .size $__internal_0_$__cuda_sm70_barrier_sync_0,(.L_x_10 - $__internal_0_$__cuda_sm70_barrier_sync_0)\n$__internal_0_$__cuda_sm70_barrier_sync_0:\n /*1150*/ WARPSYNC 0xffffffff ;\n /*1160*/ BAR.SYNC 0x0 ;\n /*1170*/ MOV R4, RZ ;\n /*1180*/ MOV R4, R4 ;\n /*1190*/ MOV R4, R5 ;\n /*11a0*/ MOV R5, 0x0 ;\n /*11b0*/ RET.REL.NODEC R4 `(_Z25fluidStructureInteractionP15BoundaryElementi) ;\n.L_x_9:\n /*11c0*/ BRA `(.L_x_9);\n /*11d0*/ NOP;\n /*11e0*/ NOP;\n /*11f0*/ NOP;\n /*1200*/ NOP;\n /*1210*/ NOP;\n /*1220*/ NOP;\n /*1230*/ NOP;\n /*1240*/ NOP;\n /*1250*/ NOP;\n /*1260*/ NOP;\n /*1270*/ NOP;\n.L_x_10:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.protected\t_Z25fluidStructureInteractionP15BoundaryElementi ; -- Begin function _Z25fluidStructureInteractionP15BoundaryElementi\n\t.globl\t_Z25fluidStructureInteractionP15BoundaryElementi\n\t.p2align\t8\n\t.type\t_Z25fluidStructureInteractionP15BoundaryElementi,@function\n_Z25fluidStructureInteractionP15BoundaryElementi: ; @_Z25fluidStructureInteractionP15BoundaryElementi\n; %bb.0:\n\ts_clause 0x1\n\ts_load_b32 s2, s[0:1], 0x8\n\ts_load_b64 s[0:1], s[0:1], 0x0\n\tv_mad_u32_u24 v1, v0, 36, 0\n\ts_waitcnt lgkmcnt(0)\n\tv_cmp_gt_i32_e32 vcc_lo, s2, v0\n\ts_and_saveexec_b32 s2, vcc_lo\n\ts_cbranch_execz .LBB0_2\n; %bb.1:\n\tv_mad_u64_u32 v[10:11], null, v0, 36, s[0:1]\n\ts_clause 0x2\n\tglobal_load_b128 v[2:5], v[10:11], off offset:16\n\tglobal_load_b128 v[6:9], v[10:11], off\n\tglobal_load_b32 v10, v[10:11], off offset:32\n\ts_waitcnt vmcnt(2)\n\tds_store_2addr_b32 v1, v4, v5 offset0:6 offset1:7\n\tds_store_2addr_b32 v1, v2, v3 offset0:4 offset1:5\n\ts_waitcnt vmcnt(1)\n\tds_store_2addr_b32 v1, v8, v9 offset0:2 offset1:3\n\tds_store_2addr_b32 v1, v6, v7 offset1:1\n\ts_waitcnt vmcnt(0)\n\tds_store_b32 v1, v10 offset:32\n.LBB0_2:\n\ts_or_b32 exec_lo, exec_lo, s2\n\ts_waitcnt lgkmcnt(0)\n\ts_barrier\n\tbuffer_gl0_inv\n\ts_and_saveexec_b32 s2, vcc_lo\n\ts_cbranch_execz .LBB0_4\n; %bb.3:\n\tds_load_2addr_b32 v[2:3], v1 offset0:3 offset1:4\n\tds_load_b32 v4, v1 offset:20\n\ts_waitcnt lgkmcnt(1)\n\tv_dual_mul_f32 v2, 0x3dcccccd, v2 :: v_dual_mul_f32 v3, 0x3dcccccd, v3\n\ts_waitcnt lgkmcnt(0)\n\tv_mul_f32_e32 v4, 0x3dcccccd, v4\n\tds_store_2addr_b32 v1, v2, v3 offset0:6 offset1:7\n\tds_store_b32 v1, v4 offset:32\n.LBB0_4:\n\ts_or_b32 exec_lo, exec_lo, s2\n\ts_waitcnt lgkmcnt(0)\n\ts_barrier\n\tbuffer_gl0_inv\n\ts_and_saveexec_b32 s2, vcc_lo\n\ts_cbranch_execz .LBB0_6\n; %bb.5:\n\tds_load_b32 v12, v1 offset:32\n\tds_load_2addr_b32 v[4:5], v1 offset0:6 offset1:7\n\tds_load_2addr_b32 v[2:3], v1 offset0:4 offset1:5\n\tds_load_2addr_b32 v[8:9], v1 offset0:2 offset1:3\n\tds_load_2addr_b32 v[6:7], v1 offset1:1\n\tv_mad_u64_u32 v[10:11], null, v0, 36, s[0:1]\n\ts_waitcnt lgkmcnt(4)\n\tglobal_store_b32 v[10:11], v12, off offset:32\n\ts_waitcnt lgkmcnt(2)\n\tglobal_store_b128 v[10:11], v[2:5], off offset:16\n\ts_waitcnt lgkmcnt(0)\n\tglobal_store_b128 v[10:11], v[6:9], off\n.LBB0_6:\n\ts_nop 0\n\ts_sendmsg sendmsg(MSG_DEALLOC_VGPRS)\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z25fluidStructureInteractionP15BoundaryElementi\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 12\n\t\t.amdhsa_user_sgpr_count 15\n\t\t.amdhsa_user_sgpr_dispatch_ptr 0\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 0\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 0\n\t\t.amdhsa_next_free_vgpr 13\n\t\t.amdhsa_next_free_sgpr 3\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end0:\n\t.size\t_Z25fluidStructureInteractionP15BoundaryElementi, .Lfunc_end0-_Z25fluidStructureInteractionP15BoundaryElementi\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 344\n; NumSgprs: 5\n; NumVgprs: 13\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 0\n; VGPRBlocks: 1\n; NumSGPRsForWavesPerEU: 5\n; NumVGPRsForWavesPerEU: 13\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 15\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .offset: 8\n .size: 4\n .value_kind: by_value\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 12\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z25fluidStructureInteractionP15BoundaryElementi\n .private_segment_fixed_size: 0\n .sgpr_count: 5\n .sgpr_spill_count: 0\n .symbol: _Z25fluidStructureInteractionP15BoundaryElementi.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 13\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162585,"cells":{"id":{"kind":"string","value":"6606fa6029ba083d280bbdc3f1753b3b7b64018d_O2"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z11gradientGPUPdS_S_iidd --------------------------\n .section .text._Z11gradientGPUPdS_S_iidd,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=29\"\n .align 128\n\n\n\n\n .global _Z11gradientGPUPdS_S_iidd\n .type _Z11gradientGPUPdS_S_iidd,@function\n .size _Z11gradientGPUPdS_S_iidd,(.L_x_26 - _Z11gradientGPUPdS_S_iidd)\n .other _Z11gradientGPUPdS_S_iidd,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z11gradientGPUPdS_S_iidd:\n.text._Z11gradientGPUPdS_S_iidd:\n /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;\n /*0010*/ IABS R7, c[0x0][0x17c] ;\n /*0020*/ S2R R0, SR_CTAID.X ;\n /*0030*/ UMOV UR5, 0x1 ;\n /*0040*/ I2F.RP R4, R7 ;\n /*0050*/ S2R R5, SR_TID.X ;\n /*0060*/ ULDC.64 UR6, c[0x0][0x178] ;\n /*0070*/ UIADD3 UR4, -UR5, UR7, URZ ;\n /*0080*/ MUFU.RCP R4, R4 ;\n /*0090*/ IMAD R0, R0, c[0x0][0x0], R5 ;\n /*00a0*/ IADD3 R2, R4, 0xffffffe, RZ ;\n /*00b0*/ IABS R4, R0 ;\n /*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ;\n /*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ;\n /*00e0*/ IMAD.MOV R6, RZ, RZ, -R3 ;\n /*00f0*/ IMAD R5, R6, R7, RZ ;\n /*0100*/ IMAD.HI.U32 R3, R3, R5, R2 ;\n /*0110*/ IMAD.HI.U32 R3, R3, R4, RZ ;\n /*0120*/ IMAD.MOV R5, RZ, RZ, -R3 ;\n /*0130*/ IMAD R2, R7, R5, R4 ;\n /*0140*/ ISETP.GT.U32.AND P1, PT, R7, R2, PT ;\n /*0150*/ @!P1 IMAD.IADD R2, R2, 0x1, -R7 ;\n /*0160*/ @!P1 IADD3 R3, R3, 0x1, RZ ;\n /*0170*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x17c], PT ;\n /*0180*/ ISETP.GE.U32.AND P0, PT, R2, R7, PT ;\n /*0190*/ LOP3.LUT R2, R0, c[0x0][0x17c], RZ, 0x3c, !PT ;\n /*01a0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ;\n /*01b0*/ @P0 IADD3 R3, R3, 0x1, RZ ;\n /*01c0*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ;\n /*01d0*/ @!P1 LOP3.LUT R3, RZ, c[0x0][0x17c], RZ, 0x33, !PT ;\n /*01e0*/ IMAD.MOV R5, RZ, RZ, -R3 ;\n /*01f0*/ IMAD R2, R5, c[0x0][0x17c], R0 ;\n /*0200*/ ISETP.GE.AND P0, PT, R2, UR4, PT ;\n /*0210*/ UIADD3 UR4, -UR5, UR6, URZ ;\n /*0220*/ ISETP.LT.OR P0, PT, R2, 0x1, P0 ;\n /*0230*/ ISETP.LT.OR P0, PT, R3, 0x1, P0 ;\n /*0240*/ ISETP.GE.OR P0, PT, R3, UR4, P0 ;\n /*0250*/ @P0 EXIT ;\n /*0260*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ;\n /*0270*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*0280*/ IMAD.WIDE R2, R0, R9, c[0x0][0x170] ;\n /*0290*/ LDG.E.64 R4, [R2.64] ;\n /*02a0*/ LDG.E.64 R12, [R2.64+-0x8] ;\n /*02b0*/ LDG.E.64 R10, [R2.64+0x8] ;\n /*02c0*/ IADD3 R6, R0.reuse, c[0x0][0x17c], RZ ;\n /*02d0*/ IADD3 R8, R0, -c[0x0][0x17c], RZ ;\n /*02e0*/ IMAD.WIDE R6, R6, R9, c[0x0][0x170] ;\n /*02f0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ;\n /*0300*/ LDG.E.64 R6, [R6.64] ;\n /*0310*/ LDG.E.64 R8, [R8.64] ;\n /*0320*/ MUFU.RCP64H R15, c[0x0][0x184] ;\n /*0330*/ IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x180] ;\n /*0340*/ BSSY B0, `(.L_x_0) ;\n /*0350*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x184] ;\n /*0360*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ;\n /*0370*/ DFMA R16, R14, -R18, 1 ;\n /*0380*/ DFMA R16, R16, R16, R16 ;\n /*0390*/ DFMA R16, R14, R16, R14 ;\n /*03a0*/ DFMA R2, R16, -R18, 1 ;\n /*03b0*/ DFMA R2, R16, R2, R16 ;\n /*03c0*/ DADD R12, R4, R12 ;\n /*03d0*/ DADD R10, R4, R10 ;\n /*03e0*/ DMUL R12, R12, 0.5 ;\n /*03f0*/ DFMA R10, R10, 0.5, -R12 ;\n /*0400*/ DADD R6, R4, R6 ;\n /*0410*/ DMUL R12, R10, R2 ;\n /*0420*/ FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ;\n /*0430*/ DADD R8, R4, R8 ;\n /*0440*/ DFMA R14, R12, -c[0x0][0x180], R10 ;\n /*0450*/ DMUL R4, R6, 0.5 ;\n /*0460*/ DFMA R2, R2, R14, R12 ;\n /*0470*/ FFMA R12, RZ, c[0x0][0x184], R3 ;\n /*0480*/ FSETP.GT.AND P0, PT, |R12|, 1.469367938527859385e-39, PT ;\n /*0490*/ @P0 BRA P1, `(.L_x_1) ;\n /*04a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ;\n /*04b0*/ MOV R14, 0x4e0 ;\n /*04c0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x184] ;\n /*04d0*/ CALL.REL.NOINC `($__internal_0_$__cuda_sm20_div_rn_f64_full) ;\n.L_x_1:\n /*04e0*/ BSYNC B0 ;\n.L_x_0:\n /*04f0*/ MUFU.RCP64H R7, c[0x0][0x18c] ;\n /*0500*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x188] ;\n /*0510*/ DFMA R8, R8, 0.5, -R4 ;\n /*0520*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x18c] ;\n /*0530*/ BSSY B0, `(.L_x_2) ;\n /*0540*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ;\n /*0550*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ;\n /*0560*/ DFMA R10, R6, -R12, 1 ;\n /*0570*/ DFMA R10, R10, R10, R10 ;\n /*0580*/ DFMA R10, R6, R10, R6 ;\n /*0590*/ DFMA R6, R10, -R12, 1 ;\n /*05a0*/ DFMA R4, R10, R6, R10 ;\n /*05b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ;\n /*05c0*/ DMUL R10, R8, R4 ;\n /*05d0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ;\n /*05e0*/ DFMA R12, R10, -c[0x0][0x188], R8 ;\n /*05f0*/ STG.E.64 [R6.64], R2 ;\n /*0600*/ DFMA R4, R4, R12, R10 ;\n /*0610*/ FFMA R10, RZ, c[0x0][0x18c], R5 ;\n /*0620*/ FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ;\n /*0630*/ @P0 BRA P1, `(.L_x_3) ;\n /*0640*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ;\n /*0650*/ MOV R14, 0x6a0 ;\n /*0660*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ;\n /*0670*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x188] ;\n /*0680*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x18c] ;\n /*0690*/ CALL.REL.NOINC `($__internal_0_$__cuda_sm20_div_rn_f64_full) ;\n /*06a0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ;\n /*06b0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ;\n.L_x_3:\n /*06c0*/ BSYNC B0 ;\n.L_x_2:\n /*06d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ;\n /*06e0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ;\n /*06f0*/ STG.E.64 [R2.64], R4 ;\n /*0700*/ EXIT ;\n\n\n\n\n .weak $__internal_0_$__cuda_sm20_div_rn_f64_full\n .type $__internal_0_$__cuda_sm20_div_rn_f64_full,@function\n .size $__internal_0_$__cuda_sm20_div_rn_f64_full,(.L_x_26 - $__internal_0_$__cuda_sm20_div_rn_f64_full)\n$__internal_0_$__cuda_sm20_div_rn_f64_full:\n /*0710*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ;\n /*0720*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1ca00000 ;\n /*0730*/ LOP3.LUT R2, R7, 0x800fffff, RZ, 0xc0, !PT ;\n /*0740*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ;\n /*0750*/ FSETP.GEU.AND P2, PT, |R11|.reuse, 1.469367938527859385e-39, PT ;\n /*0760*/ BSSY B1, `(.L_x_4) ;\n /*0770*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ;\n /*0780*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ;\n /*0790*/ LOP3.LUT R15, R11, 0x7ff00000, RZ, 0xc0, !PT ;\n /*07a0*/ LOP3.LUT R24, R7, 0x7ff00000, RZ, 0xc0, !PT ;\n /*07b0*/ @!P0 DMUL R2, R6, 8.98846567431157953865e+307 ;\n /*07c0*/ ISETP.GE.U32.AND P1, PT, R15, R24, PT ;\n /*07d0*/ IMAD.MOV.U32 R25, RZ, RZ, R15 ;\n /*07e0*/ @!P2 LOP3.LUT R12, R7, 0x7ff00000, RZ, 0xc0, !PT ;\n /*07f0*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ;\n /*0800*/ MUFU.RCP64H R19, R3 ;\n /*0810*/ SEL R17, R16, 0x63400000, !P1 ;\n /*0820*/ @!P2 ISETP.GE.U32.AND P3, PT, R15, R12, PT ;\n /*0830*/ @!P0 LOP3.LUT R24, R3, 0x7ff00000, RZ, 0xc0, !PT ;\n /*0840*/ @!P2 SEL R21, R16, 0x63400000, !P3 ;\n /*0850*/ IADD3 R26, R24, -0x1, RZ ;\n /*0860*/ @!P2 LOP3.LUT R21, R21, 0x80000000, R11, 0xf8, !PT ;\n /*0870*/ @!P2 LOP3.LUT R21, R21, 0x100000, RZ, 0xfc, !PT ;\n /*0880*/ DFMA R12, R18, -R2, 1 ;\n /*0890*/ DFMA R22, R12, R12, R12 ;\n /*08a0*/ LOP3.LUT R13, R17, 0x800fffff, R11, 0xf8, !PT ;\n /*08b0*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ;\n /*08c0*/ DFMA R22, R18, R22, R18 ;\n /*08d0*/ @!P2 DFMA R12, R12, 2, -R20 ;\n /*08e0*/ DFMA R18, R22, -R2, 1 ;\n /*08f0*/ @!P2 LOP3.LUT R25, R13, 0x7ff00000, RZ, 0xc0, !PT ;\n /*0900*/ DFMA R18, R22, R18, R22 ;\n /*0910*/ IADD3 R17, R25, -0x1, RZ ;\n /*0920*/ DMUL R20, R18, R12 ;\n /*0930*/ ISETP.GT.U32.AND P0, PT, R17, 0x7feffffe, PT ;\n /*0940*/ ISETP.GT.U32.OR P0, PT, R26, 0x7feffffe, P0 ;\n /*0950*/ DFMA R22, R20, -R2, R12 ;\n /*0960*/ DFMA R18, R18, R22, R20 ;\n /*0970*/ @P0 BRA `(.L_x_5) ;\n /*0980*/ LOP3.LUT R20, R7, 0x7ff00000, RZ, 0xc0, !PT ;\n /*0990*/ ISETP.GE.U32.AND P0, PT, R15.reuse, R20, PT ;\n /*09a0*/ IMAD.IADD R10, R15, 0x1, -R20 ;\n /*09b0*/ SEL R15, R16, 0x63400000, !P0 ;\n /*09c0*/ IMNMX R10, R10, -0x46a00000, !PT ;\n /*09d0*/ IMNMX R10, R10, 0x46a00000, PT ;\n /*09e0*/ IMAD.IADD R15, R10, 0x1, -R15 ;\n /*09f0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ;\n /*0a00*/ IADD3 R11, R15, 0x7fe00000, RZ ;\n /*0a10*/ DMUL R16, R18, R10 ;\n /*0a20*/ FSETP.GTU.AND P0, PT, |R17|, 1.469367938527859385e-39, PT ;\n /*0a30*/ @P0 BRA `(.L_x_6) ;\n /*0a40*/ DFMA R2, R18, -R2, R12 ;\n /*0a50*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ;\n /*0a60*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ;\n /*0a70*/ LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ;\n /*0a80*/ LOP3.LUT R11, R7, R11, RZ, 0xfc, !PT ;\n /*0a90*/ @!P0 BRA `(.L_x_6) ;\n /*0aa0*/ IMAD.MOV R3, RZ, RZ, -R15 ;\n /*0ab0*/ DMUL.RP R10, R18, R10 ;\n /*0ac0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ;\n /*0ad0*/ DFMA R2, R16, -R2, R18 ;\n /*0ae0*/ LOP3.LUT R7, R11, R7, RZ, 0x3c, !PT ;\n /*0af0*/ IADD3 R2, -R15, -0x43300000, RZ ;\n /*0b00*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ;\n /*0b10*/ FSEL R16, R10, R16, !P0 ;\n /*0b20*/ FSEL R17, R7, R17, !P0 ;\n /*0b30*/ BRA `(.L_x_6) ;\n.L_x_5:\n /*0b40*/ DSETP.NAN.AND P0, PT, R10, R10, PT ;\n /*0b50*/ @P0 BRA `(.L_x_7) ;\n /*0b60*/ DSETP.NAN.AND P0, PT, R6, R6, PT ;\n /*0b70*/ @P0 BRA `(.L_x_8) ;\n /*0b80*/ ISETP.NE.AND P0, PT, R25, R24, PT ;\n /*0b90*/ IMAD.MOV.U32 R16, RZ, RZ, 0x0 ;\n /*0ba0*/ IMAD.MOV.U32 R17, RZ, RZ, -0x80000 ;\n /*0bb0*/ @!P0 BRA `(.L_x_6) ;\n /*0bc0*/ ISETP.NE.AND P0, PT, R25, 0x7ff00000, PT ;\n /*0bd0*/ LOP3.LUT R17, R11, 0x80000000, R7, 0x48, !PT ;\n /*0be0*/ ISETP.EQ.OR P0, PT, R24, RZ, !P0 ;\n /*0bf0*/ @P0 LOP3.LUT R2, R17, 0x7ff00000, RZ, 0xfc, !PT ;\n /*0c00*/ @!P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ;\n /*0c10*/ @P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ;\n /*0c20*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, R2 ;\n /*0c30*/ BRA `(.L_x_6) ;\n.L_x_8:\n /*0c40*/ LOP3.LUT R17, R7, 0x80000, RZ, 0xfc, !PT ;\n /*0c50*/ IMAD.MOV.U32 R16, RZ, RZ, R6 ;\n /*0c60*/ BRA `(.L_x_6) ;\n.L_x_7:\n /*0c70*/ LOP3.LUT R17, R11, 0x80000, RZ, 0xfc, !PT ;\n /*0c80*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ;\n.L_x_6:\n /*0c90*/ BSYNC B1 ;\n.L_x_4:\n /*0ca0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x0 ;\n /*0cb0*/ IMAD.MOV.U32 R2, RZ, RZ, R16 ;\n /*0cc0*/ IMAD.MOV.U32 R3, RZ, RZ, R17 ;\n /*0cd0*/ RET.REL.NODEC R14 `(_Z11gradientGPUPdS_S_iidd) ;\n.L_x_9:\n /*0ce0*/ BRA `(.L_x_9);\n /*0cf0*/ NOP;\n /*0d00*/ NOP;\n /*0d10*/ NOP;\n /*0d20*/ NOP;\n /*0d30*/ NOP;\n /*0d40*/ NOP;\n /*0d50*/ NOP;\n /*0d60*/ NOP;\n /*0d70*/ NOP;\n.L_x_26:\n\n\n//--------------------- .text._Z12LaplacianGPUPdS_iidd --------------------------\n .section .text._Z12LaplacianGPUPdS_iidd,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=34\"\n .align 128\n\n\n\n\n .global _Z12LaplacianGPUPdS_iidd\n .type _Z12LaplacianGPUPdS_iidd,@function\n .size _Z12LaplacianGPUPdS_iidd,(.L_x_27 - _Z12LaplacianGPUPdS_iidd)\n .other _Z12LaplacianGPUPdS_iidd,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z12LaplacianGPUPdS_iidd:\n.text._Z12LaplacianGPUPdS_iidd:\n /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;\n /*0010*/ IABS R5, c[0x0][0x174] ;\n /*0020*/ S2R R27, SR_CTAID.X ;\n /*0030*/ UMOV UR5, 0x1 ;\n /*0040*/ I2F.RP R0, R5 ;\n /*0050*/ S2R R4, SR_TID.X ;\n /*0060*/ ULDC.64 UR6, c[0x0][0x170] ;\n /*0070*/ UIADD3 UR4, -UR5, UR7, URZ ;\n /*0080*/ MUFU.RCP R0, R0 ;\n /*0090*/ IMAD R27, R27, c[0x0][0x0], R4 ;\n /*00a0*/ IADD3 R2, R0, 0xffffffe, RZ ;\n /*00b0*/ IABS R0, R27 ;\n /*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ;\n /*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ;\n /*00e0*/ IMAD.MOV R6, RZ, RZ, -R3 ;\n /*00f0*/ IMAD R7, R6, R5, RZ ;\n /*0100*/ IMAD.HI.U32 R3, R3, R7, R2 ;\n /*0110*/ IMAD.HI.U32 R3, R3, R0, RZ ;\n /*0120*/ IMAD.MOV R4, RZ, RZ, -R3 ;\n /*0130*/ IMAD R0, R5, R4, R0 ;\n /*0140*/ ISETP.GT.U32.AND P1, PT, R5, R0, PT ;\n /*0150*/ @!P1 IMAD.IADD R0, R0, 0x1, -R5 ;\n /*0160*/ @!P1 IADD3 R3, R3, 0x1, RZ ;\n /*0170*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x174], PT ;\n /*0180*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ;\n /*0190*/ LOP3.LUT R0, R27, c[0x0][0x174], RZ, 0x3c, !PT ;\n /*01a0*/ ISETP.GE.AND P2, PT, R0, RZ, PT ;\n /*01b0*/ @P0 IADD3 R3, R3, 0x1, RZ ;\n /*01c0*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ;\n /*01d0*/ @!P1 LOP3.LUT R3, RZ, c[0x0][0x174], RZ, 0x33, !PT ;\n /*01e0*/ IMAD.MOV R0, RZ, RZ, -R3 ;\n /*01f0*/ IMAD R0, R0, c[0x0][0x174], R27 ;\n /*0200*/ ISETP.GE.AND P0, PT, R0, UR4, PT ;\n /*0210*/ UIADD3 UR4, -UR5, UR6, URZ ;\n /*0220*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ;\n /*0230*/ ISETP.LT.OR P0, PT, R3, 0x1, P0 ;\n /*0240*/ ISETP.GE.OR P0, PT, R3, UR4, P0 ;\n /*0250*/ @P0 EXIT ;\n /*0260*/ IMAD.MOV.U32 R15, RZ, RZ, 0x8 ;\n /*0270*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*0280*/ IMAD.WIDE R4, R27, R15, c[0x0][0x168] ;\n /*0290*/ LDG.E.64 R2, [R4.64+0x8] ;\n /*02a0*/ LDG.E.64 R16, [R4.64] ;\n /*02b0*/ MUFU.RCP64H R7, c[0x0][0x17c] ;\n /*02c0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x178] ;\n /*02d0*/ BSSY B0, `(.L_x_10) ;\n /*02e0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x17c] ;\n /*02f0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ;\n /*0300*/ DFMA R8, R6, -R10, 1 ;\n /*0310*/ DFMA R8, R8, R8, R8 ;\n /*0320*/ DFMA R6, R6, R8, R6 ;\n /*0330*/ DFMA R10, R6, -R10, 1 ;\n /*0340*/ DFMA R10, R6, R10, R6 ;\n /*0350*/ DADD R8, R2, -R16 ;\n /*0360*/ DMUL R2, R8, R10 ;\n /*0370*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ;\n /*0380*/ DFMA R6, R2, -c[0x0][0x178], R8 ;\n /*0390*/ DFMA R2, R10, R6, R2 ;\n /*03a0*/ IADD3 R6, R27, -c[0x0][0x174], RZ ;\n /*03b0*/ IMAD.WIDE R6, R6, R15, c[0x0][0x168] ;\n /*03c0*/ FFMA R0, RZ, c[0x0][0x17c], R3 ;\n /*03d0*/ IMAD.WIDE R14, R15, c[0x0][0x174], R4 ;\n /*03e0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ;\n /*03f0*/ @P0 BRA P1, `(.L_x_11) ;\n /*0400*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x178] ;\n /*0410*/ MOV R28, 0x440 ;\n /*0420*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x17c] ;\n /*0430*/ CALL.REL.NOINC `($__internal_1_$__cuda_sm20_div_rn_f64_full) ;\n /*0440*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ;\n /*0450*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ;\n.L_x_11:\n /*0460*/ BSYNC B0 ;\n.L_x_10:\n /*0470*/ LDG.E.64 R4, [R4.64+-0x8] ;\n /*0480*/ MUFU.RCP64H R9, c[0x0][0x17c] ;\n /*0490*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x178] ;\n /*04a0*/ BSSY B0, `(.L_x_12) ;\n /*04b0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x17c] ;\n /*04c0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ;\n /*04d0*/ DFMA R12, R8, -R10, 1 ;\n /*04e0*/ DFMA R12, R12, R12, R12 ;\n /*04f0*/ DFMA R12, R8, R12, R8 ;\n /*0500*/ DFMA R10, R12, -R10, 1 ;\n /*0510*/ DFMA R12, R12, R10, R12 ;\n /*0520*/ DADD R8, R16, -R4 ;\n /*0530*/ DMUL R10, R12, R8 ;\n /*0540*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ;\n /*0550*/ DFMA R4, R10, -c[0x0][0x178], R8 ;\n /*0560*/ DFMA R4, R12, R4, R10 ;\n /*0570*/ FFMA R0, RZ, c[0x0][0x17c], R5 ;\n /*0580*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ;\n /*0590*/ @P0 BRA P1, `(.L_x_13) ;\n /*05a0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x178] ;\n /*05b0*/ MOV R28, 0x5e0 ;\n /*05c0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x17c] ;\n /*05d0*/ CALL.REL.NOINC `($__internal_1_$__cuda_sm20_div_rn_f64_full) ;\n /*05e0*/ MOV R4, R8 ;\n /*05f0*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ;\n.L_x_13:\n /*0600*/ BSYNC B0 ;\n.L_x_12:\n /*0610*/ LDG.E.64 R6, [R6.64] ;\n /*0620*/ MUFU.RCP64H R9, c[0x0][0x184] ;\n /*0630*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x180] ;\n /*0640*/ BSSY B0, `(.L_x_14) ;\n /*0650*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x184] ;\n /*0660*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ;\n /*0670*/ DFMA R10, R8, -R12, 1 ;\n /*0680*/ DFMA R10, R10, R10, R10 ;\n /*0690*/ DFMA R10, R8, R10, R8 ;\n /*06a0*/ DFMA R12, R10, -R12, 1 ;\n /*06b0*/ DFMA R12, R10, R12, R10 ;\n /*06c0*/ DADD R8, -R16, R6 ;\n /*06d0*/ DMUL R10, R8, R12 ;\n /*06e0*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ;\n /*06f0*/ DFMA R6, R10, -c[0x0][0x180], R8 ;\n /*0700*/ DFMA R6, R12, R6, R10 ;\n /*0710*/ FFMA R0, RZ, c[0x0][0x184], R7 ;\n /*0720*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ;\n /*0730*/ @P0 BRA P1, `(.L_x_15) ;\n /*0740*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x180] ;\n /*0750*/ MOV R28, 0x780 ;\n /*0760*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x184] ;\n /*0770*/ CALL.REL.NOINC `($__internal_1_$__cuda_sm20_div_rn_f64_full) ;\n /*0780*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ;\n /*0790*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ;\n.L_x_15:\n /*07a0*/ BSYNC B0 ;\n.L_x_14:\n /*07b0*/ LDG.E.64 R14, [R14.64] ;\n /*07c0*/ MUFU.RCP64H R9, c[0x0][0x184] ;\n /*07d0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x180] ;\n /*07e0*/ BSSY B0, `(.L_x_16) ;\n /*07f0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x184] ;\n /*0800*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ;\n /*0810*/ DFMA R12, R8, -R10, 1 ;\n /*0820*/ DFMA R12, R12, R12, R12 ;\n /*0830*/ DFMA R12, R8, R12, R8 ;\n /*0840*/ DFMA R10, R12, -R10, 1 ;\n /*0850*/ DFMA R12, R12, R10, R12 ;\n /*0860*/ DADD R16, R16, -R14 ;\n /*0870*/ DMUL R8, R12, R16 ;\n /*0880*/ FSETP.GEU.AND P1, PT, |R17|, 6.5827683646048100446e-37, PT ;\n /*0890*/ DFMA R10, R8, -c[0x0][0x180], R16 ;\n /*08a0*/ DFMA R8, R12, R10, R8 ;\n /*08b0*/ FFMA R0, RZ, c[0x0][0x184], R9 ;\n /*08c0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ;\n /*08d0*/ @P0 BRA P1, `(.L_x_17) ;\n /*08e0*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ;\n /*08f0*/ MOV R10, c[0x0][0x180] ;\n /*0900*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ;\n /*0910*/ MOV R28, 0x940 ;\n /*0920*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x184] ;\n /*0930*/ CALL.REL.NOINC `($__internal_1_$__cuda_sm20_div_rn_f64_full) ;\n.L_x_17:\n /*0940*/ BSYNC B0 ;\n.L_x_16:\n /*0950*/ DADD R6, -R8, R6 ;\n /*0960*/ DADD R2, -R4, R2 ;\n /*0970*/ IMAD.MOV.U32 R4, RZ, RZ, 0x8 ;\n /*0980*/ DMUL R6, R6, c[0x0][0x178] ;\n /*0990*/ IMAD.WIDE R4, R27, R4, c[0x0][0x160] ;\n /*09a0*/ DFMA R2, R2, c[0x0][0x180], R6 ;\n /*09b0*/ STG.E.64 [R4.64], R2 ;\n /*09c0*/ EXIT ;\n\n\n\n\n .weak $__internal_1_$__cuda_sm20_div_rn_f64_full\n .type $__internal_1_$__cuda_sm20_div_rn_f64_full,@function\n .size $__internal_1_$__cuda_sm20_div_rn_f64_full,(.L_x_27 - $__internal_1_$__cuda_sm20_div_rn_f64_full)\n$__internal_1_$__cuda_sm20_div_rn_f64_full:\n /*09d0*/ FSETP.GEU.AND P0, PT, |R11|.reuse, 1.469367938527859385e-39, PT ;\n /*09e0*/ IMAD.MOV.U32 R26, RZ, RZ, 0x1ca00000 ;\n /*09f0*/ LOP3.LUT R12, R11, 0x800fffff, RZ, 0xc0, !PT ;\n /*0a00*/ IMAD.MOV.U32 R30, RZ, RZ, 0x1 ;\n /*0a10*/ FSETP.GEU.AND P2, PT, |R9|.reuse, 1.469367938527859385e-39, PT ;\n /*0a20*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ;\n /*0a30*/ LOP3.LUT R13, R12, 0x3ff00000, RZ, 0xfc, !PT ;\n /*0a40*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ;\n /*0a50*/ LOP3.LUT R29, R9, 0x7ff00000, RZ, 0xc0, !PT ;\n /*0a60*/ BSSY B1, `(.L_x_18) ;\n /*0a70*/ LOP3.LUT R24, R11, 0x7ff00000, RZ, 0xc0, !PT ;\n /*0a80*/ @!P0 DMUL R12, R10, 8.98846567431157953865e+307 ;\n /*0a90*/ ISETP.GE.U32.AND P1, PT, R29, R24, PT ;\n /*0aa0*/ @!P2 LOP3.LUT R0, R11, 0x7ff00000, RZ, 0xc0, !PT ;\n /*0ab0*/ @!P2 IMAD.MOV.U32 R22, RZ, RZ, RZ ;\n /*0ac0*/ MUFU.RCP64H R31, R13 ;\n /*0ad0*/ SEL R19, R26.reuse, 0x63400000, !P1 ;\n /*0ae0*/ @!P2 ISETP.GE.U32.AND P3, PT, R29, R0, PT ;\n /*0af0*/ IMAD.MOV.U32 R0, RZ, RZ, R29 ;\n /*0b00*/ LOP3.LUT R19, R19, 0x800fffff, R9, 0xf8, !PT ;\n /*0b10*/ @!P2 SEL R23, R26, 0x63400000, !P3 ;\n /*0b20*/ @!P2 LOP3.LUT R23, R23, 0x80000000, R9, 0xf8, !PT ;\n /*0b30*/ @!P2 LOP3.LUT R23, R23, 0x100000, RZ, 0xfc, !PT ;\n /*0b40*/ DFMA R20, R30, -R12, 1 ;\n /*0b50*/ @!P2 DFMA R18, R18, 2, -R22 ;\n /*0b60*/ DFMA R20, R20, R20, R20 ;\n /*0b70*/ DFMA R20, R30, R20, R30 ;\n /*0b80*/ @!P2 LOP3.LUT R0, R19, 0x7ff00000, RZ, 0xc0, !PT ;\n /*0b90*/ IMAD.MOV.U32 R31, RZ, RZ, R24 ;\n /*0ba0*/ @!P0 LOP3.LUT R31, R13, 0x7ff00000, RZ, 0xc0, !PT ;\n /*0bb0*/ IADD3 R24, R0, -0x1, RZ ;\n /*0bc0*/ DFMA R22, R20, -R12, 1 ;\n /*0bd0*/ IADD3 R30, R31, -0x1, RZ ;\n /*0be0*/ ISETP.GT.U32.AND P0, PT, R24, 0x7feffffe, PT ;\n /*0bf0*/ DFMA R20, R20, R22, R20 ;\n /*0c00*/ ISETP.GT.U32.OR P0, PT, R30, 0x7feffffe, P0 ;\n /*0c10*/ DMUL R22, R20, R18 ;\n /*0c20*/ DFMA R24, R22, -R12, R18 ;\n /*0c30*/ DFMA R24, R20, R24, R22 ;\n /*0c40*/ @P0 BRA `(.L_x_19) ;\n /*0c50*/ LOP3.LUT R8, R11, 0x7ff00000, RZ, 0xc0, !PT ;\n /*0c60*/ ISETP.GE.U32.AND P0, PT, R29.reuse, R8, PT ;\n /*0c70*/ IMAD.IADD R0, R29, 0x1, -R8 ;\n /*0c80*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ;\n /*0c90*/ SEL R9, R26, 0x63400000, !P0 ;\n /*0ca0*/ IMNMX R0, R0, -0x46a00000, !PT ;\n /*0cb0*/ IMNMX R0, R0, 0x46a00000, PT ;\n /*0cc0*/ IMAD.IADD R0, R0, 0x1, -R9 ;\n /*0cd0*/ IADD3 R9, R0, 0x7fe00000, RZ ;\n /*0ce0*/ DMUL R20, R24, R8 ;\n /*0cf0*/ FSETP.GTU.AND P0, PT, |R21|, 1.469367938527859385e-39, PT ;\n /*0d00*/ @P0 BRA `(.L_x_20) ;\n /*0d10*/ DFMA R12, R24, -R12, R18 ;\n /*0d20*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ;\n /*0d30*/ FSETP.NEU.AND P0, PT, R13.reuse, RZ, PT ;\n /*0d40*/ LOP3.LUT R19, R13, 0x80000000, R11, 0x48, !PT ;\n /*0d50*/ LOP3.LUT R9, R19, R9, RZ, 0xfc, !PT ;\n /*0d60*/ @!P0 BRA `(.L_x_20) ;\n /*0d70*/ IADD3 R11, -R0, RZ, RZ ;\n /*0d80*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ;\n /*0d90*/ DMUL.RP R8, R24, R8 ;\n /*0da0*/ DFMA R10, R20, -R10, R24 ;\n /*0db0*/ LOP3.LUT R19, R9, R19, RZ, 0x3c, !PT ;\n /*0dc0*/ IADD3 R10, -R0, -0x43300000, RZ ;\n /*0dd0*/ FSETP.NEU.AND P0, PT, |R11|, R10, PT ;\n /*0de0*/ FSEL R20, R8, R20, !P0 ;\n /*0df0*/ FSEL R21, R19, R21, !P0 ;\n /*0e00*/ BRA `(.L_x_20) ;\n.L_x_19:\n /*0e10*/ DSETP.NAN.AND P0, PT, R8, R8, PT ;\n /*0e20*/ @P0 BRA `(.L_x_21) ;\n /*0e30*/ DSETP.NAN.AND P0, PT, R10, R10, PT ;\n /*0e40*/ @P0 BRA `(.L_x_22) ;\n /*0e50*/ ISETP.NE.AND P0, PT, R0, R31, PT ;\n /*0e60*/ IMAD.MOV.U32 R20, RZ, RZ, 0x0 ;\n /*0e70*/ IMAD.MOV.U32 R21, RZ, RZ, -0x80000 ;\n /*0e80*/ @!P0 BRA `(.L_x_20) ;\n /*0e90*/ ISETP.NE.AND P0, PT, R0, 0x7ff00000, PT ;\n /*0ea0*/ LOP3.LUT R21, R9, 0x80000000, R11, 0x48, !PT ;\n /*0eb0*/ ISETP.EQ.OR P0, PT, R31, RZ, !P0 ;\n /*0ec0*/ @P0 LOP3.LUT R0, R21, 0x7ff00000, RZ, 0xfc, !PT ;\n /*0ed0*/ @!P0 IMAD.MOV.U32 R20, RZ, RZ, RZ ;\n /*0ee0*/ @P0 IMAD.MOV.U32 R20, RZ, RZ, RZ ;\n /*0ef0*/ @P0 IMAD.MOV.U32 R21, RZ, RZ, R0 ;\n /*0f00*/ BRA `(.L_x_20) ;\n.L_x_22:\n /*0f10*/ LOP3.LUT R21, R11, 0x80000, RZ, 0xfc, !PT ;\n /*0f20*/ IMAD.MOV.U32 R20, RZ, RZ, R10 ;\n /*0f30*/ BRA `(.L_x_20) ;\n.L_x_21:\n /*0f40*/ LOP3.LUT R21, R9, 0x80000, RZ, 0xfc, !PT ;\n /*0f50*/ IMAD.MOV.U32 R20, RZ, RZ, R8 ;\n.L_x_20:\n /*0f60*/ BSYNC B1 ;\n.L_x_18:\n /*0f70*/ IMAD.MOV.U32 R29, RZ, RZ, 0x0 ;\n /*0f80*/ IMAD.MOV.U32 R8, RZ, RZ, R20 ;\n /*0f90*/ IMAD.MOV.U32 R9, RZ, RZ, R21 ;\n /*0fa0*/ RET.REL.NODEC R28 `(_Z12LaplacianGPUPdS_iidd) ;\n.L_x_23:\n /*0fb0*/ BRA `(.L_x_23);\n /*0fc0*/ NOP;\n /*0fd0*/ NOP;\n /*0fe0*/ NOP;\n /*0ff0*/ NOP;\n /*1000*/ NOP;\n /*1010*/ NOP;\n /*1020*/ NOP;\n /*1030*/ NOP;\n /*1040*/ NOP;\n /*1050*/ NOP;\n /*1060*/ NOP;\n /*1070*/ NOP;\n.L_x_27:\n\n\n//--------------------- .text._Z13DivergenceGPUPdS_S_iidd --------------------------\n .section .text._Z13DivergenceGPUPdS_S_iidd,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=24\"\n .align 128\n\n\n\n\n .global _Z13DivergenceGPUPdS_S_iidd\n .type _Z13DivergenceGPUPdS_S_iidd,@function\n .size _Z13DivergenceGPUPdS_S_iidd,(.L_x_30 - _Z13DivergenceGPUPdS_S_iidd)\n .other _Z13DivergenceGPUPdS_S_iidd,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z13DivergenceGPUPdS_S_iidd:\n.text._Z13DivergenceGPUPdS_S_iidd:\n /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;\n /*0010*/ IABS R7, c[0x0][0x17c] ;\n /*0020*/ S2R R3, SR_CTAID.X ;\n /*0030*/ UMOV UR5, 0x1 ;\n /*0040*/ I2F.RP R0, R7 ;\n /*0050*/ S2R R2, SR_TID.X ;\n /*0060*/ ULDC.64 UR6, c[0x0][0x178] ;\n /*0070*/ UIADD3 UR4, -UR5, UR7, URZ ;\n /*0080*/ MUFU.RCP R0, R0 ;\n /*0090*/ IMAD R3, R3, c[0x0][0x0], R2 ;\n /*00a0*/ IADD3 R4, R0, 0xffffffe, RZ ;\n /*00b0*/ IABS R0, R3 ;\n /*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ;\n /*00d0*/ MOV R4, RZ ;\n /*00e0*/ IMAD.MOV R6, RZ, RZ, -R5 ;\n /*00f0*/ IMAD R9, R6, R7, RZ ;\n /*0100*/ IMAD.HI.U32 R5, R5, R9, R4 ;\n /*0110*/ IMAD.HI.U32 R5, R5, R0, RZ ;\n /*0120*/ IMAD.MOV R2, RZ, RZ, -R5 ;\n /*0130*/ IMAD R0, R7, R2, R0 ;\n /*0140*/ ISETP.GT.U32.AND P2, PT, R7, R0, PT ;\n /*0150*/ @!P2 IMAD.IADD R0, R0, 0x1, -R7 ;\n /*0160*/ @!P2 IADD3 R5, R5, 0x1, RZ ;\n /*0170*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x17c], PT ;\n /*0180*/ ISETP.GE.U32.AND P0, PT, R0, R7, PT ;\n /*0190*/ LOP3.LUT R0, R3, c[0x0][0x17c], RZ, 0x3c, !PT ;\n /*01a0*/ ISETP.GE.AND P1, PT, R0, RZ, PT ;\n /*01b0*/ @P0 IADD3 R5, R5, 0x1, RZ ;\n /*01c0*/ @!P1 IADD3 R5, -R5, RZ, RZ ;\n /*01d0*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x17c], RZ, 0x33, !PT ;\n /*01e0*/ IMAD.MOV R0, RZ, RZ, -R5 ;\n /*01f0*/ IMAD R0, R0, c[0x0][0x17c], R3 ;\n /*0200*/ ISETP.GE.AND P0, PT, R0, UR4, PT ;\n /*0210*/ UIADD3 UR4, -UR5, UR6, URZ ;\n /*0220*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ;\n /*0230*/ ISETP.LT.OR P0, PT, R5, 0x1, P0 ;\n /*0240*/ ISETP.GE.OR P0, PT, R5, UR4, P0 ;\n /*0250*/ @P0 EXIT ;\n /*0260*/ MOV R0, 0x8 ;\n /*0270*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*0280*/ IADD3 R9, R3, -c[0x0][0x17c], RZ ;\n /*0290*/ IMAD.WIDE R6, R3, R0, c[0x0][0x170] ;\n /*02a0*/ IMAD.WIDE R8, R9, R0, c[0x0][0x170] ;\n /*02b0*/ IMAD.WIDE R10, R0, c[0x0][0x17c], R6 ;\n /*02c0*/ LDG.E.64 R6, [R6.64] ;\n /*02d0*/ IMAD.WIDE R4, R3.reuse, R0.reuse, c[0x0][0x168] ;\n /*02e0*/ LDG.E.64 R10, [R10.64] ;\n /*02f0*/ LDG.E.64 R8, [R8.64] ;\n /*0300*/ LDG.E.64 R14, [R4.64] ;\n /*0310*/ LDG.E.64 R16, [R4.64+-0x8] ;\n /*0320*/ LDG.E.64 R12, [R4.64+0x8] ;\n /*0330*/ IMAD.WIDE R2, R3, R0, c[0x0][0x160] ;\n /*0340*/ DADD R20, R6, R10 ;\n /*0350*/ DADD R18, R8, R6 ;\n /*0360*/ DMUL R20, R20, 0.5 ;\n /*0370*/ DADD R16, R14, R16 ;\n /*0380*/ DADD R12, R12, R14 ;\n /*0390*/ DMUL R16, R16, 0.5 ;\n /*03a0*/ DFMA R18, R18, 0.5, -R20 ;\n /*03b0*/ DFMA R12, R12, 0.5, -R16 ;\n /*03c0*/ DMUL R18, R18, c[0x0][0x180] ;\n /*03d0*/ DFMA R12, R12, c[0x0][0x188], R18 ;\n /*03e0*/ STG.E.64 [R2.64], R12 ;\n /*03f0*/ EXIT ;\n.L_x_24:\n /*0400*/ BRA `(.L_x_24);\n /*0410*/ NOP;\n /*0420*/ NOP;\n /*0430*/ NOP;\n /*0440*/ NOP;\n /*0450*/ NOP;\n /*0460*/ NOP;\n /*0470*/ NOP;\n /*0480*/ NOP;\n /*0490*/ NOP;\n /*04a0*/ NOP;\n /*04b0*/ NOP;\n /*04c0*/ NOP;\n /*04d0*/ NOP;\n /*04e0*/ NOP;\n /*04f0*/ NOP;\n.L_x_30:\n\n\n//--------------------- .text._Z6DivGPUPdS_S_S_iidd --------------------------\n .section .text._Z6DivGPUPdS_S_S_iidd,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=32\"\n .align 128\n\n\n\n\n .global _Z6DivGPUPdS_S_S_iidd\n .type _Z6DivGPUPdS_S_S_iidd,@function\n .size _Z6DivGPUPdS_S_S_iidd,(.L_x_31 - _Z6DivGPUPdS_S_S_iidd)\n .other _Z6DivGPUPdS_S_S_iidd,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z6DivGPUPdS_S_S_iidd:\n.text._Z6DivGPUPdS_S_S_iidd:\n /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;\n /*0010*/ IABS R5, c[0x0][0x184] ;\n /*0020*/ S2R R7, SR_CTAID.X ;\n /*0030*/ UMOV UR5, 0x1 ;\n /*0040*/ I2F.RP R0, R5 ;\n /*0050*/ S2R R4, SR_TID.X ;\n /*0060*/ ULDC.64 UR6, c[0x0][0x180] ;\n /*0070*/ UIADD3 UR4, -UR5, UR7, URZ ;\n /*0080*/ MUFU.RCP R0, R0 ;\n /*0090*/ IMAD R7, R7, c[0x0][0x0], R4 ;\n /*00a0*/ IADD3 R2, R0, 0xffffffe, RZ ;\n /*00b0*/ IABS R0, R7 ;\n /*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ;\n /*00d0*/ MOV R2, RZ ;\n /*00e0*/ IMAD.MOV R6, RZ, RZ, -R3 ;\n /*00f0*/ IMAD R9, R6, R5, RZ ;\n /*0100*/ IMAD.HI.U32 R3, R3, R9, R2 ;\n /*0110*/ IMAD.HI.U32 R3, R3, R0, RZ ;\n /*0120*/ IMAD.MOV R4, RZ, RZ, -R3 ;\n /*0130*/ IMAD R0, R5, R4, R0 ;\n /*0140*/ ISETP.GT.U32.AND P2, PT, R5, R0, PT ;\n /*0150*/ @!P2 IADD3 R0, R0, -R5.reuse, RZ ;\n /*0160*/ @!P2 IADD3 R3, R3, 0x1, RZ ;\n /*0170*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ;\n /*0180*/ LOP3.LUT R0, R7, c[0x0][0x184], RZ, 0x3c, !PT ;\n /*0190*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x184], PT ;\n /*01a0*/ ISETP.GE.AND P1, PT, R0, RZ, PT ;\n /*01b0*/ @P0 IADD3 R3, R3, 0x1, RZ ;\n /*01c0*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ;\n /*01d0*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x184], RZ, 0x33, !PT ;\n /*01e0*/ IADD3 R0, -R3, RZ, RZ ;\n /*01f0*/ IMAD R0, R0, c[0x0][0x184], R7 ;\n /*0200*/ ISETP.GE.AND P0, PT, R0, UR4, PT ;\n /*0210*/ UIADD3 UR4, -UR5, UR6, URZ ;\n /*0220*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ;\n /*0230*/ ISETP.LT.OR P0, PT, R3, 0x1, P0 ;\n /*0240*/ ISETP.GE.OR P0, PT, R3, UR4, P0 ;\n /*0250*/ @P0 EXIT ;\n /*0260*/ IMAD.MOV.U32 R0, RZ, RZ, 0x8 ;\n /*0270*/ IADD3 R25, R7.reuse, -c[0x0][0x184], RZ ;\n /*0280*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*0290*/ IMAD.WIDE R28, R7, R0, c[0x0][0x168] ;\n /*02a0*/ IMAD.WIDE R26, R7.reuse, R0.reuse, c[0x0][0x178] ;\n /*02b0*/ LDG.E.64 R10, [R28.64+0x8] ;\n /*02c0*/ IMAD.WIDE R16, R7, R0.reuse, c[0x0][0x170] ;\n /*02d0*/ LDG.E.64 R4, [R28.64+-0x8] ;\n /*02e0*/ IMAD.WIDE R12, R0.reuse, c[0x0][0x184], R28 ;\n /*02f0*/ LDG.E.64 R8, [R16.64+0x8] ;\n /*0300*/ IMAD.WIDE R14, R0, c[0x0][0x184], R26 ;\n /*0310*/ LDG.E.64 R2, [R16.64+-0x8] ;\n /*0320*/ IMAD.WIDE R18, R25.reuse, R0.reuse, c[0x0][0x168] ;\n /*0330*/ LDG.E.64 R12, [R12.64] ;\n /*0340*/ IMAD.WIDE R24, R25, R0, c[0x0][0x178] ;\n /*0350*/ LDG.E.64 R14, [R14.64] ;\n /*0360*/ LDG.E.64 R18, [R18.64] ;\n /*0370*/ LDG.E.64 R24, [R24.64] ;\n /*0380*/ LDG.E.64 R20, [R28.64] ;\n /*0390*/ LDG.E.64 R26, [R26.64] ;\n /*03a0*/ LDG.E.64 R22, [R16.64] ;\n /*03b0*/ DMUL R8, R8, R10 ;\n /*03c0*/ DMUL R2, R2, R4 ;\n /*03d0*/ DMUL R10, R14, R12 ;\n /*03e0*/ DMUL R4, R24, R18 ;\n /*03f0*/ DFMA R10, R20, R26, R10 ;\n /*0400*/ DFMA R4, R20, R26, R4 ;\n /*0410*/ DFMA R2, R22, R20, R2 ;\n /*0420*/ DMUL R10, R10, 0.5 ;\n /*0430*/ DFMA R8, R22, R20, R8 ;\n /*0440*/ DMUL R2, R2, 0.5 ;\n /*0450*/ DFMA R4, R4, 0.5, -R10 ;\n /*0460*/ DFMA R2, R8, 0.5, -R2 ;\n /*0470*/ DMUL R4, R4, c[0x0][0x188] ;\n /*0480*/ DFMA R2, R2, c[0x0][0x190], R4 ;\n /*0490*/ IMAD.WIDE R4, R7, R0, c[0x0][0x160] ;\n /*04a0*/ STG.E.64 [R4.64], R2 ;\n /*04b0*/ EXIT ;\n.L_x_25:\n /*04c0*/ BRA `(.L_x_25);\n /*04d0*/ NOP;\n /*04e0*/ NOP;\n /*04f0*/ NOP;\n /*0500*/ NOP;\n /*0510*/ NOP;\n /*0520*/ NOP;\n /*0530*/ NOP;\n /*0540*/ NOP;\n /*0550*/ NOP;\n /*0560*/ NOP;\n /*0570*/ NOP;\n.L_x_31:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.weak\t__cxa_pure_virtual ; -- Begin function __cxa_pure_virtual\n\t.p2align\t2\n\t.type\t__cxa_pure_virtual,@function\n__cxa_pure_virtual: ; @__cxa_pure_virtual\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB0_1: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB0_1\n.Lfunc_end0:\n\t.size\t__cxa_pure_virtual, .Lfunc_end0-__cxa_pure_virtual\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 56\n; NumSgprs: 1\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.weak\t__cxa_deleted_virtual ; -- Begin function __cxa_deleted_virtual\n\t.p2align\t2\n\t.type\t__cxa_deleted_virtual,@function\n__cxa_deleted_virtual: ; @__cxa_deleted_virtual\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB1_1: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB1_1\n.Lfunc_end1:\n\t.size\t__cxa_deleted_virtual, .Lfunc_end1-__cxa_deleted_virtual\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 56\n; NumSgprs: 1\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hsa_signal_add\n\t.type\t__ockl_hsa_signal_add,@function\n__ockl_hsa_signal_add: ; @__ockl_hsa_signal_add\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v6, s32 offset:48 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v4, s32 offset:36 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v3, s32 offset:32 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v2\n\tscratch_load_b32 v2, off, s32 offset:32 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v1, s32 offset:28 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v1, v0\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[3:4], s32 offset:20 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v3, v1\n\tscratch_store_b64 off, v[3:4], s32 offset:12 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v0, v1\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v1, v2\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v0, s1, v0, s1\n\tv_add_co_ci_u32_e64 v2, s0, v1, s0, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s32 offset:4 ; 8-byte Folded Spill\n; %bb.1:\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 3\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, 0\n ; implicit-def: $vgpr6 : SGPR spill to VGPR lane\n\tv_writelane_b32 v6, s1, 0\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 1\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_3\n; %bb.2:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 4\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s1, 2\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 3\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_17\n\ts_branch .LBB2_4\n.LBB2_3:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 1\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s2, v6, 0\n\tv_writelane_b32 v6, s2, 4\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s2, 5\n\tv_writelane_b32 v6, s1, 6\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 7\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_13\n\ts_branch .LBB2_6\n.LBB2_4:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 5\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, -1\n\tv_writelane_b32 v6, s0, 8\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 9\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_15\n\ts_branch .LBB2_18\n.LBB2_5:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 10\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_readlane_b32 s0, v6, 11\n\ts_and_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 0\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_3\n.LBB2_6:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 12\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_7\n\ts_branch .LBB2_14\n.LBB2_7:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 12\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s2, v6, 4\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s2, 13\n\tv_writelane_b32 v6, s1, 14\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 15\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_9\n; %bb.8:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 4\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_lt_i32_e64 s2, v0, s0\n\ts_mov_b32 s0, -1\n\ts_mov_b32 s0, exec_lo\n\ts_and_not1_b32 s1, s1, exec_lo\n\ts_and_b32 s2, s2, exec_lo\n\ts_or_b32 s1, s1, s2\n\tv_writelane_b32 v6, s1, 13\n\tv_writelane_b32 v6, s0, 14\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n.LBB2_9:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s3, v6, 15\n\ts_or_b32 exec_lo, exec_lo, s3\n\tv_readlane_b32 s1, v6, 4\n\tv_readlane_b32 s2, v6, 13\n\tv_readlane_b32 s0, v6, 14\n\ts_and_b32 s0, s0, exec_lo\n\ts_and_not1_b32 s1, s1, exec_lo\n\ts_and_b32 s2, s2, exec_lo\n\ts_or_b32 s1, s1, s2\n\tv_writelane_b32 v6, s1, 5\n\tv_writelane_b32 v6, s0, 6\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_13\n.LBB2_10:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 16\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 17\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n.LBB2_11:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 18\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v6, 17\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 19\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_19\n; %bb.12:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_branch .LBB2_19\n.LBB2_13:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v6, 7\n\ts_or_b32 exec_lo, exec_lo, s2\n\tv_readlane_b32 s0, v6, 5\n\tv_readlane_b32 s1, v6, 6\n\tv_writelane_b32 v6, s1, 16\n\tv_writelane_b32 v6, s1, 17\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 18\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_11\n\ts_branch .LBB2_10\n.LBB2_14:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_branch .LBB2_7\n.LBB2_15:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 9\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_readlane_b32 s0, v6, 8\n\ts_and_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 2\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_17\n.LBB2_16:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_branch .LBB2_5\n.LBB2_17:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 3\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v6, 2\n\tv_writelane_b32 v6, s1, 11\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 10\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_5\n\ts_branch .LBB2_16\n.LBB2_18:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b32 s0, 0\n\ts_xor_b32 s0, exec_lo, -1\n\tv_writelane_b32 v6, s0, 8\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_15\n.LBB2_19:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 19\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:12 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[0:1], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:40 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_ne_u64_e64 s1, v[0:1], s[0:1]\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 20\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_21\n; %bb.20:\n\tscratch_load_b64 v[1:2], off, s32 offset:40 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s32 offset:12 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b32 v0, v[3:4], off offset:24\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v5, 0\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\tv_mov_b32_e32 v4, v5\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[1:2], v[3:4], off\n\tv_readfirstlane_b32 s0, v0\n\ts_mov_b32 s1, 0xff\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB2_21:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 20\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v6, off, s32 offset:48 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end2:\n\t.size\t__ockl_hsa_signal_add, .Lfunc_end2-__ockl_hsa_signal_add\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 1952\n; NumSgprs: 33\n; NumVgprs: 7\n; ScratchSize: 56\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hostcall_internal\n\t.type\t__ockl_hostcall_internal,@function\n__ockl_hostcall_internal: ; @__ockl_hostcall_internal\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s18, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v24, s33 offset:308 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v25, s33 offset:312 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v26, s33 offset:316 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0x150\n\tv_writelane_b32 v24, s30, 0\n\tv_writelane_b32 v24, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:132 ; 4-byte Folded Spill\n ; implicit-def: $vgpr26 : SGPR spill to VGPR lane\n\tv_writelane_b32 v26, s6, 0\n\tv_writelane_b32 v26, s7, 1\n\tscratch_store_b32 off, v18, s33 offset:128 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v16\n\tscratch_load_b32 v16, off, s33 offset:128 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:124 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v14\n\tscratch_load_b32 v14, off, s33 offset:124 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:120 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v12\n\tscratch_load_b32 v12, off, s33 offset:120 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:116 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v10\n\tscratch_load_b32 v10, off, s33 offset:116 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:112 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v8\n\tscratch_load_b32 v8, off, s33 offset:112 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:108 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v6\n\tscratch_load_b32 v6, off, s33 offset:108 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:104 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v4\n\tscratch_load_b32 v4, off, s33 offset:104 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:100 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v2\n\tscratch_load_b32 v2, off, s33 offset:100 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:96 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v1, s33 offset:92 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v1, v0\n\tscratch_load_b32 v0, off, s33 offset:92 ; 4-byte Folded Reload\n\tv_writelane_b32 v26, s15, 2\n\tv_writelane_b32 v26, s14, 3\n\tv_writelane_b32 v26, s13, 4\n\tv_writelane_b32 v26, s12, 5\n\tv_writelane_b32 v26, s10, 6\n\tv_writelane_b32 v26, s11, 7\n\tv_writelane_b32 v26, s8, 8\n\tv_writelane_b32 v26, s9, 9\n\tv_writelane_b32 v26, s4, 10\n\tv_writelane_b32 v26, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\ts_waitcnt vmcnt(8)\n\tv_mov_b32_e32 v18, v16\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr15 killed $vgpr15 def $vgpr15_vgpr16 killed $exec\n\ts_waitcnt vmcnt(7)\n\tv_mov_b32_e32 v16, v14\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec\n\ts_waitcnt vmcnt(6)\n\tv_mov_b32_e32 v14, v12\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\ts_waitcnt vmcnt(5)\n\tv_mov_b32_e32 v12, v10\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\ts_waitcnt vmcnt(4)\n\tv_mov_b32_e32 v10, v8\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\ts_waitcnt vmcnt(3)\n\tv_mov_b32_e32 v8, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v6, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[17:18], s33 offset:84 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[15:16], s33 offset:76 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[13:14], s33 offset:68 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[11:12], s33 offset:60 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[9:10], s33 offset:52 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[7:8], s33 offset:44 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[5:6], s33 offset:36 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[3:4], s33 offset:28 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s0, -1\n\tv_mbcnt_lo_u32_b32 v0, s0, s1\n\tv_mbcnt_hi_u32_b32 v0, s0, v0\n\t;;#ASMSTART\n\t;;#ASMEND\n\tv_mov_b32_e32 v3, v0\n\tscratch_store_b32 off, v3, s33 offset:24 ; 4-byte Folded Spill\n\tv_readfirstlane_b32 s0, v0\n\tscratch_store_b64 off, v[1:2], s33 offset:16 ; 8-byte Folded Spill\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, s1\n\tv_writelane_b32 v26, s0, 12\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v0, 0\n\tv_mov_b32_e32 v1, 0\n\tscratch_store_b64 off, v[0:1], s33 offset:8 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 13\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_6\n; %bb.1:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_mov_b64 s[2:3], 24\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:160 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b64 s[2:3], 40\n\tv_mov_b32_e32 v4, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v5, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v4, s1, v4, s1\n\tv_add_co_ci_u32_e64 v6, s0, v5, s0, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tscratch_store_b64 off, v[4:5], s33 offset:152 ; 8-byte Folded Spill\n\tglobal_load_b64 v[5:6], v[0:1], off\n\tglobal_load_b64 v[10:11], v[0:1], off offset:40\n\tv_mov_b32_e32 v8, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v11\n\tv_and_b32_e64 v4, v4, v8\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v7, v10\n\tv_and_b32_e64 v12, v7, v9\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_mov_b32_e32 v4, v12\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[10:11], s0, v4, s1, 0\n\tv_mov_b32_e32 v14, v11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec\n\tv_mov_b32_e32 v15, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[12:13], s0, v[12:13]\n\tv_mov_b32_e32 v4, v12\n\tv_mad_u64_u32 v[12:13], s1, v4, s1, v[14:15]\n ; kill: def $vgpr12 killed $vgpr12 killed $vgpr12_vgpr13 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s1\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_lshlrev_b64 v[13:14], s0, v[12:13]\n\tv_mov_b32_e32 v7, v14\n\tv_mov_b32_e32 v11, v10\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\tv_mov_b32_e32 v4, v12\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v10, v13\n\tv_mov_b32_e32 v7, v11\n\tv_or_b32_e64 v10, v7, v10\n ; kill: def $vgpr10 killed $vgpr10 def $vgpr10_vgpr11 killed $exec\n\tv_mov_b32_e32 v11, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v11\n\tv_add_co_u32 v4, s0, v4, v7\n\tv_add_co_ci_u32_e64 v6, s0, v5, v6, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tglobal_load_b64 v[4:5], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v10, v5\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s0, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:144 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:136 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 15\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_5\n.LBB3_2: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 14\n\tscratch_load_b64 v[2:3], off, s33 offset:144 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:160 ; 8-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:152 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[5:6], v[4:5], off\n\tglobal_load_b64 v[10:11], v[7:8], off\n\tv_mov_b32_e32 v8, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v11\n\tv_and_b32_e64 v4, v4, v8\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v7, v10\n\tv_and_b32_e64 v12, v7, v9\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_mov_b32_e32 v4, v12\n\ts_mov_b32 s2, 24\n\tv_mad_u64_u32 v[10:11], s0, v4, s2, 0\n\tv_mov_b32_e32 v14, v11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec\n\tv_mov_b32_e32 v15, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[12:13], s0, v[12:13]\n\tv_mov_b32_e32 v4, v12\n\tv_mad_u64_u32 v[12:13], s2, v4, s2, v[14:15]\n ; kill: def $vgpr12 killed $vgpr12 killed $vgpr12_vgpr13 killed $exec\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s2\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_lshlrev_b64 v[13:14], s0, v[12:13]\n\tv_mov_b32_e32 v7, v14\n\tv_mov_b32_e32 v11, v10\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\tv_mov_b32_e32 v4, v12\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v10, v13\n\tv_mov_b32_e32 v7, v11\n\tv_or_b32_e64 v10, v7, v10\n ; kill: def $vgpr10 killed $vgpr10 def $vgpr10_vgpr11 killed $exec\n\tv_mov_b32_e32 v11, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v11\n\tv_add_co_u32 v4, s0, v4, v7\n\tv_add_co_ci_u32_e64 v6, s0, v5, v6, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tglobal_load_b64 v[4:5], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v10, v5\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e64 s0, v[0:1], v[2:3]\n\ts_or_b32 s0, s0, s1\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:144 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:168 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 16\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_2\n; %bb.3:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 16\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.4:\n\tscratch_load_b64 v[0:1], off, s33 offset:168 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:136 ; 8-byte Folded Spill\n.LBB3_5:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:136 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:8 ; 8-byte Folded Spill\n.LBB3_6:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 13\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:8 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[4:5], s0, v[4:5]\n\tv_mov_b32_e32 v2, v4\n\tv_readfirstlane_b32 s4, v3\n\tv_readfirstlane_b32 s2, v2\n ; implicit-def: $sgpr5\n ; implicit-def: $sgpr3\n ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3\n\ts_mov_b32 s3, s5\n\ts_lshl_b64 s[2:3], s[2:3], s0\n\ts_mov_b32 s0, 0\n ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5\n\ts_mov_b32 s5, s0\n\ts_or_b64 s[2:3], s[2:3], s[4:5]\n\tv_writelane_b32 v26, s2, 17\n\tv_writelane_b32 v26, s3, 18\n\tglobal_load_b64 v[2:3], v[0:1], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:200 ; 8-byte Folded Spill\n\ts_mov_b64 s[6:7], 40\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s7\n\tv_add_co_u32 v2, s4, v2, s4\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s4\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tglobal_load_b64 v[3:4], v[0:1], off offset:40\n\ts_mov_b32 s0, s3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v4\n\tv_and_b32_e64 v2, s0, v2\n\ts_mov_b32 s0, s2\n ; kill: def $vgpr3 killed $vgpr3 killed $vgpr3_vgpr4 killed $exec\n\tv_and_b32_e64 v3, s0, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v5, v3\n\tscratch_store_b64 off, v[5:6], s33 offset:184 ; 8-byte Folded Spill\n\tglobal_load_b64 v[1:2], v[0:1], off offset:8\n\ts_mov_b32 s0, 12\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s0, v0, v3\n\tv_add_co_ci_u32_e64 v2, s0, v1, v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:176 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], exec\n\tv_writelane_b32 v26, s2, 19\n\tv_writelane_b32 v26, s3, 20\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 21\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_8\n; %bb.7:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 19\n\tv_readlane_b32 s1, v26, 20\n\tscratch_load_b32 v2, off, s33 offset:96 ; 4-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v5, v0\n\ts_mov_b32 s3, 24\n\tv_mad_u64_u32 v[3:4], s2, v5, s3, 0\n\tv_mov_b32_e32 v9, v4\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v5, s2\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v5\n\ts_mov_b32 s2, 32\n\tv_lshrrev_b64 v[0:1], s2, v[0:1]\n\tv_mov_b32_e32 v5, v0\n\tv_mad_u64_u32 v[0:1], s3, v5, s3, v[9:10]\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v5, s3\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v5\n\tv_lshlrev_b64 v[9:10], s2, v[0:1]\n\tv_mov_b32_e32 v1, v10\n\tv_mov_b32_e32 v4, v3\n\ts_mov_b32 s2, 0\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v0, v5\n\tv_or_b32_e64 v0, v0, v1\n\tv_mov_b32_e32 v3, v9\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v5, v1, v3\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v0\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v3, v6\n\tv_add_co_u32 v0, s2, v0, v4\n\tv_add_co_ci_u32_e64 v3, s2, v1, v3, s2\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tglobal_store_b32 v[0:1], v2, off offset:16\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tglobal_store_b64 v[0:1], v[2:3], off offset:8\n\tv_mov_b32_e32 v2, 1\n\tglobal_store_b32 v[0:1], v2, off offset:20\n.LBB3_8:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[2:3], off, s33 offset:84 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:76 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:68 ; 8-byte Folded Reload\n\tscratch_load_b64 v[8:9], off, s33 offset:60 ; 8-byte Folded Reload\n\tscratch_load_b64 v[10:11], off, s33 offset:52 ; 8-byte Folded Reload\n\tscratch_load_b64 v[12:13], off, s33 offset:44 ; 8-byte Folded Reload\n\tscratch_load_b64 v[14:15], off, s33 offset:36 ; 8-byte Folded Reload\n\tscratch_load_b64 v[16:17], off, s33 offset:28 ; 8-byte Folded Reload\n\tscratch_load_b64 v[22:23], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:24 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v18, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v18\n\ts_mov_b32 s0, 6\n\ts_waitcnt vmcnt(0)\n\tv_lshlrev_b64 v[20:21], s0, v[0:1]\n\tv_mov_b32_e32 v0, v22\n\tv_mov_b32_e32 v19, v20\n\tv_mov_b32_e32 v1, v23\n\tv_mov_b32_e32 v18, v21\n\tv_add_co_u32 v0, s0, v0, v19\n\tv_add_co_ci_u32_e64 v18, s0, v1, v18, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v18\n\tscratch_store_b64 off, v[0:1], s33 offset:216 ; 8-byte Folded Spill\n\tglobal_store_b64 v[0:1], v[16:17], off\n\ts_mov_b64 s[4:5], 8\n\tv_mov_b32_e32 v16, v0\n\ts_mov_b32 s2, s4\n\tv_mov_b32_e32 v17, v1\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v16, s2, v16, s2\n\tv_add_co_ci_u32_e64 v18, s0, v17, s0, s2\n ; kill: def $vgpr16 killed $vgpr16 def $vgpr16_vgpr17 killed $exec\n\tv_mov_b32_e32 v17, v18\n\tscratch_store_b64 off, v[16:17], s33 offset:208 ; 8-byte Folded Spill\n\tglobal_store_b64 v[0:1], v[14:15], off offset:8\n\tglobal_store_b64 v[0:1], v[12:13], off offset:16\n\tglobal_store_b64 v[0:1], v[10:11], off offset:24\n\tglobal_store_b64 v[0:1], v[8:9], off offset:32\n\tglobal_store_b64 v[0:1], v[6:7], off offset:40\n\tglobal_store_b64 v[0:1], v[4:5], off offset:48\n\tglobal_store_b64 v[0:1], v[2:3], off offset:56\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 22\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_13\n; %bb.9:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[5:6], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:192 ; 8-byte Folded Reload\n\ts_mov_b64 s[4:5], 32\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s4\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:240 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:32 glc\n\ts_waitcnt vmcnt(1)\n\tglobal_load_b64 v[7:8], v[7:8], off\n\ts_mov_b32 s0, s3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v8\n\tv_and_b32_e64 v4, v4, s0\n\ts_mov_b32 s1, s2\n ; kill: def $vgpr7 killed $vgpr7 killed $vgpr7_vgpr8 killed $exec\n\tv_and_b32_e64 v7, v7, s1\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v4\n\tv_mov_b32_e32 v4, v7\n\ts_mov_b32 s3, 24\n\tv_mad_u64_u32 v[9:10], s2, v4, s3, 0\n\tv_mov_b32_e32 v11, v10\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v4, s2\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\ts_mov_b32 s2, 32\n\tv_lshrrev_b64 v[7:8], s2, v[7:8]\n\tv_mov_b32_e32 v4, v7\n\tv_mad_u64_u32 v[7:8], s3, v4, s3, v[11:12]\n ; kill: def $vgpr7 killed $vgpr7 killed $vgpr7_vgpr8 killed $exec\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v4, s3\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v4\n\tv_lshlrev_b64 v[7:8], s2, v[7:8]\n\tv_mov_b32_e32 v11, v8\n ; kill: def $vgpr9 killed $vgpr9 killed $vgpr9_vgpr10 killed $exec\n\ts_mov_b32 s2, 0\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v4, v10\n\tv_or_b32_e64 v4, v4, v11\n\tv_mov_b32_e32 v8, v7\n\tv_mov_b32_e32 v7, v9\n\tv_or_b32_e64 v8, v7, v8\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v8\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v9\n\tv_add_co_u32 v4, s2, v4, v7\n\tv_add_co_ci_u32_e64 v6, s2, v5, v6, s2\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tscratch_store_b64 off, v[4:5], s33 offset:232 ; 8-byte Folded Spill\n\tglobal_store_b64 v[4:5], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s1\n\tv_mov_b32_e32 v10, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s2, v[0:1], v[2:3]\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s2, 23\n\tv_writelane_b32 v26, s0, 24\n\tscratch_store_b64 off, v[0:1], s33 offset:224 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 25\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_14\n.LBB3_10: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 24\n\tv_readlane_b32 s1, v26, 23\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[2:3], off, s33 offset:224 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:240 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:232 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_store_b64 v[4:5], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n\ts_mov_b32 s1, s3\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v10, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s1, v[0:1], v[2:3]\n\ts_or_b32 s0, s1, s0\n\tv_writelane_b32 v26, s1, 23\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 24\n\tscratch_store_b64 off, v[0:1], s33 offset:224 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 26\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_10\n; %bb.11:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 26\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.12:\n\ts_branch .LBB3_14\n.LBB3_13:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_branch .LBB3_15\n.LBB3_14:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 25\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s15, v26, 2\n\tv_readlane_b32 s14, v26, 3\n\tv_readlane_b32 s13, v26, 4\n\tv_readlane_b32 s12, v26, 5\n\tv_readlane_b32 s10, v26, 6\n\tv_readlane_b32 s11, v26, 7\n\tv_readlane_b32 s8, v26, 8\n\tv_readlane_b32 s9, v26, 9\n\tv_readlane_b32 s6, v26, 0\n\tv_readlane_b32 s7, v26, 1\n\tv_readlane_b32 s4, v26, 10\n\tv_readlane_b32 s5, v26, 11\n\tscratch_load_b32 v31, off, s33 offset:132 ; 4-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_mov_b32 s0, 32\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[0:1], s0, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v2\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hsa_signal_add@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hsa_signal_add@rel32@hi+12\n\tv_mov_b32_e32 v2, 1\n\tv_mov_b32_e32 v3, 0\n\tv_mov_b32_e32 v4, 3\n\ts_swappc_b64 s[30:31], s[0:1]\n\ts_branch .LBB3_13\n.LBB3_15:\n\tscratch_load_b64 v[6:7], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[3:4], s0, v2, s1, 0\n\tv_mov_b32_e32 v8, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v2\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[0:1]\n\tv_mov_b32_e32 v2, v0\n\tv_mad_u64_u32 v[0:1], s1, v2, s1, v[8:9]\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_lshlrev_b64 v[1:2], s0, v[0:1]\n\tv_mov_b32_e32 v5, v2\n ; kill: def $vgpr3 killed $vgpr3 killed $vgpr3_vgpr4 killed $exec\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_mov_b32_e32 v0, v4\n\tv_or_b32_e64 v0, v0, v5\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v1, v3\n\tv_or_b32_e64 v4, v1, v2\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v1, v6\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v1, s0, v1, v3\n\tv_add_co_ci_u32_e64 v0, s0, v0, v2, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b64 s[2:3], 20\n\tv_mov_b32_e32 v0, v1\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v1, v2\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v0, s1, v0, s1\n\tv_add_co_ci_u32_e64 v2, s0, v1, s0, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:248 ; 8-byte Folded Spill\n.LBB3_16: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 12\n\ts_mov_b32 s0, 1\n\tv_mov_b32_e32 v0, 1\n\tscratch_store_b32 off, v0, s33 offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 27\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_18\n; %bb.17: ; in Loop: Header=BB3_16 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:248 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b32 v0, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b32 s0, 1\n\tv_and_b32_e64 v0, v0, s0\n\tscratch_store_b32 off, v0, s33 offset:256 ; 4-byte Folded Spill\n.LBB3_18: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 27\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s33 offset:256 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s1, v0\n\ts_mov_b32 s0, -1\n\ts_mov_b32 s2, 0\n\ts_cmp_eq_u32 s1, s2\n\tv_writelane_b32 v26, s0, 28\n\ts_mov_b32 s17, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_cbranch_scc1 .LBB3_20\n; %bb.19: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_sleep 1\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v26, s0, 28\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n.LBB3_20: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 28\n\tv_cndmask_b32_e64 v0, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v0, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n\ts_cbranch_vccnz .LBB3_16\n; %bb.21:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[0:1], off, s33 offset:208 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:216 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[2:3], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:268 ; 8-byte Folded Spill\n\tglobal_load_b64 v[0:1], v[0:1], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:260 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 29\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_27\n; %bb.22:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:192 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[11:12], v[2:3], off\n\ts_mov_b64 s[4:5], 1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v11\n\ts_mov_b32 s1, s4\n\tv_mov_b32_e32 v3, v12\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v4, v2\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v5, v3\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v4, s1, v4, s1\n\tv_add_co_ci_u32_e64 v6, s0, v5, s0, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_eq_u64_e64 s0, v[4:5], s[0:1]\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v6, v5\n\tv_cndmask_b32_e64 v10, v6, v7, s0\n\tv_mov_b32_e32 v3, v2\n\tv_mov_b32_e32 v2, v4\n\tv_cndmask_b32_e64 v4, v2, v3, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v8, v4\n\tv_mov_b32_e32 v9, v10\n\tv_mov_b32_e32 v2, v8\n\tv_mov_b32_e32 v3, v9\n\tscratch_store_b64 off, v[2:3], s33 offset:300 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], 24\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v5, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v5\n\tscratch_store_b64 off, v[2:3], s33 offset:292 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:24 glc\n\tglobal_load_b64 v[6:7], v[0:1], off\n\tv_mov_b32_e32 v5, v9\n\tv_mov_b32_e32 v13, v12\n\tv_and_b32_e64 v5, v5, v13\n ; kill: def $vgpr8 killed $vgpr8 killed $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v11\n\tv_and_b32_e64 v8, v8, v9\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v5\n\tv_mov_b32_e32 v5, v8\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[11:12], s0, v5, s1, 0\n\tv_mov_b32_e32 v13, v12\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v5, s0\n ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec\n\tv_mov_b32_e32 v14, v5\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[8:9], s0, v[8:9]\n\tv_mov_b32_e32 v5, v8\n\tv_mad_u64_u32 v[8:9], s1, v5, s1, v[13:14]\n ; kill: def $vgpr8 killed $vgpr8 killed $vgpr8_vgpr9 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v5, s1\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v5\n\tv_lshlrev_b64 v[8:9], s0, v[8:9]\n\tv_mov_b32_e32 v13, v9\n ; kill: def $vgpr11 killed $vgpr11 killed $vgpr11_vgpr12 killed $exec\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v5, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v5\n\tv_mov_b32_e32 v5, v12\n\tv_or_b32_e64 v5, v5, v13\n\tv_mov_b32_e32 v9, v8\n\tv_mov_b32_e32 v8, v11\n\tv_or_b32_e64 v11, v8, v9\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v5\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v8, v11\n\tv_mov_b32_e32 v6, v7\n\tv_mov_b32_e32 v7, v12\n\tv_add_co_u32 v5, s0, v5, v8\n\tv_add_co_ci_u32_e64 v7, s0, v6, v7, s0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v7\n\tscratch_store_b64 off, v[5:6], s33 offset:284 ; 8-byte Folded Spill\n\tglobal_store_b64 v[5:6], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s2, v[0:1], v[2:3]\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s2, 30\n\tv_writelane_b32 v26, s0, 31\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\tscratch_store_b64 off, v[0:1], s33 offset:276 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n ; implicit-def: $vgpr26 : SGPR spill to VGPR lane\n\tv_writelane_b32 v26, s0, 0\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_26\n.LBB3_23: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v25, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v25, 31\n\tv_readlane_b32 s1, v25, 30\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\tscratch_load_b64 v[2:3], off, s33 offset:276 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:292 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:300 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:284 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_store_b64 v[6:7], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v10, v5\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s1, v[0:1], v[2:3]\n\ts_or_b32 s0, s1, s0\n\tv_writelane_b32 v25, s1, 30\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v25, s1, 31\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v25, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\tscratch_store_b64 off, v[0:1], s33 offset:276 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_23\n; %bb.24:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.25:\n.LBB3_26:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 0\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB3_27:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[3:4], off, s33 offset:260 ; 8-byte Folded Reload\n\tscratch_load_b64 v[1:2], off, s33 offset:268 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v3\n\tv_mov_b32_e32 v3, v4\n\tv_readlane_b32 s30, v24, 0\n\tv_readlane_b32 s31, v24, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v24, off, s33 offset:308 ; 4-byte Folded Reload\n\tscratch_load_b32 v25, off, s33 offset:312 ; 4-byte Folded Reload\n\tscratch_load_b32 v26, off, s33 offset:316 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xfffffeb0\n\ts_mov_b32 s33, s18\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end3:\n\t.size\t__ockl_hostcall_internal, .Lfunc_end3-__ockl_hostcall_internal\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 5344\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 392\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hostcall_preview\n\t.type\t__ockl_hostcall_preview,@function\n__ockl_hostcall_preview: ; @__ockl_hostcall_preview\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v27, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tv_writelane_b32 v27, s33, 0\n\tv_writelane_b32 v27, s30, 1\n\tv_writelane_b32 v27, s31, 2\n\tv_mov_b32_e32 v18, v16\n\tv_mov_b32_e32 v17, v15\n\tv_mov_b32_e32 v16, v14\n\tv_mov_b32_e32 v15, v13\n\tv_mov_b32_e32 v14, v12\n\tv_mov_b32_e32 v13, v11\n\tv_mov_b32_e32 v12, v10\n\tv_mov_b32_e32 v11, v9\n\tv_mov_b32_e32 v10, v8\n\tv_mov_b32_e32 v9, v7\n\tv_mov_b32_e32 v8, v6\n\tv_mov_b32_e32 v7, v5\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v5, v3\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s0, s[0:1], 0x0\n\ts_mov_b32 s1, 0x1f4\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_i32 s0, s1\n\ts_mov_b32 s1, 0x50\n\ts_mov_b32 s0, 24\n\ts_cselect_b32 s0, s0, s1\n\ts_load_b64 s[0:1], s[8:9], s0 offset:0x0\n\ts_waitcnt lgkmcnt(0)\n\ts_mov_b32 s3, s0\n\ts_mov_b32 s2, 32\n\ts_lshr_b64 s[0:1], s[0:1], s2\n\ts_mov_b32 s2, s0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_internal@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_internal@rel32@hi+12\n\tv_mov_b32_e32 v0, s3\n\tv_mov_b32_e32 v1, s2\n\tv_readlane_b32 s30, v27, 1\n\tv_readlane_b32 s31, v27, 2\n\tv_readlane_b32 s33, v27, 0\n\ts_xor_saveexec_b32 s2, -1\n\tscratch_load_b32 v27, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s2\n\ts_setpc_b64 s[0:1]\n.Lfunc_end4:\n\t.size\t__ockl_hostcall_preview, .Lfunc_end4-__ockl_hostcall_preview\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 272\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 400\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_stderr_begin\n\t.type\t__ockl_fprintf_stderr_begin,@function\n__ockl_fprintf_stderr_begin: ; @__ockl_fprintf_stderr_begin\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s16, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v28, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 16\n\tv_writelane_b32 v28, s30, 0\n\tv_writelane_b32 v28, s31, 1\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\tv_mov_b32_e32 v1, 33\n\tv_mov_b32_e32 v3, 1\n\tv_mov_b32_e32 v16, 0\n\tv_mov_b32_e32 v2, v16\n\tv_mov_b32_e32 v4, v16\n\tv_mov_b32_e32 v5, v16\n\tv_mov_b32_e32 v6, v16\n\tv_mov_b32_e32 v7, v16\n\tv_mov_b32_e32 v8, v16\n\tv_mov_b32_e32 v9, v16\n\tv_mov_b32_e32 v10, v16\n\tv_mov_b32_e32 v11, v16\n\tv_mov_b32_e32 v12, v16\n\tv_mov_b32_e32 v13, v16\n\tv_mov_b32_e32 v14, v16\n\tv_mov_b32_e32 v15, v16\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_store_b32 off, v1, s33 ; 4-byte Folded Spill\n ; kill: def $vgpr1 killed $vgpr3 killed $exec\n\tscratch_load_b32 v3, off, s33 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v3\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v28, 0\n\tv_readlane_b32 s31, v28, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v28, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, -16\n\ts_mov_b32 s33, s16\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end5:\n\t.size\t__ockl_fprintf_stderr_begin, .Lfunc_end5-__ockl_fprintf_stderr_begin\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 228\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 416\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_append_string_n\n\t.type\t__ockl_fprintf_append_string_n,@function\n__ockl_fprintf_append_string_n: ; @__ockl_fprintf_append_string_n\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s20, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v32, s33 offset:704 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v33, s33 offset:708 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v34, s33 offset:712 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0x2d0\n\tv_writelane_b32 v32, s30, 0\n\tv_writelane_b32 v32, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:68 ; 4-byte Folded Spill\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\tv_writelane_b32 v34, s6, 0\n\tv_writelane_b32 v34, s7, 1\n\tscratch_store_b32 off, v6, s33 offset:60 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v5, s33 offset:56 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v4, s33 offset:64 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v6, v3\n\tscratch_load_b32 v3, off, s33 offset:64 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v4, v2\n\tscratch_load_b32 v2, off, s33 offset:60 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v4, s33 offset:52 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v7, v1\n\tscratch_load_b32 v1, off, s33 offset:56 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v5, v0\n\tscratch_load_b32 v0, off, s33 offset:52 ; 4-byte Folded Reload\n\tv_writelane_b32 v34, s15, 2\n\tv_writelane_b32 v34, s14, 3\n\tv_writelane_b32 v34, s13, 4\n\tv_writelane_b32 v34, s12, 5\n\tv_writelane_b32 v34, s10, 6\n\tv_writelane_b32 v34, s11, 7\n\tv_writelane_b32 v34, s8, 8\n\tv_writelane_b32 v34, s9, 9\n\tv_writelane_b32 v34, s4, 10\n\tv_writelane_b32 v34, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v1\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v7\n\tscratch_store_b64 off, v[3:4], s33 offset:44 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v3, v0\n\tscratch_store_b64 off, v[3:4], s33 offset:36 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s0, 0\n\tv_cmp_eq_u32_e64 s0, v2, s0\n\tv_mov_b32_e32 v4, v6\n\ts_mov_b64 s[2:3], 2\n\ts_mov_b32 s1, s3\n\tv_or_b32_e64 v2, v4, s1\n\tv_mov_b32_e32 v3, v5\n\ts_mov_b32 s1, s2\n\tv_or_b32_e64 v5, v3, s1\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v2\n\tv_mov_b32_e32 v2, v6\n\tv_cndmask_b32_e64 v4, v2, v4, s0\n\tv_mov_b32_e32 v2, v5\n\tv_cndmask_b32_e64 v2, v2, v3, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:28 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_ne_u64_e64 s0, v[0:1], s[0:1]\n ; implicit-def: $sgpr4_sgpr5_sgpr6_sgpr7\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tv_mov_b32_e32 v2, s6\n\tv_mov_b32_e32 v3, s7\n\tscratch_store_b128 off, v[0:3], s33 offset:12 ; 16-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 12\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_3\n\ts_branch .LBB6_2\n.LBB6_1:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v34, 2\n\tv_readlane_b32 s14, v34, 3\n\tv_readlane_b32 s13, v34, 4\n\tv_readlane_b32 s12, v34, 5\n\tv_readlane_b32 s10, v34, 6\n\tv_readlane_b32 s11, v34, 7\n\tv_readlane_b32 s8, v34, 8\n\tv_readlane_b32 s9, v34, 9\n\tv_readlane_b32 s6, v34, 0\n\tv_readlane_b32 s7, v34, 1\n\tv_readlane_b32 s4, v34, 10\n\tv_readlane_b32 s5, v34, 11\n\tscratch_load_b32 v31, off, s33 offset:68 ; 4-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:28 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v3\n\tv_and_b32_e64 v4, v0, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v0, v2\n\tv_and_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_mov_b32_e32 v4, v1\n\ts_mov_b64 s[0:1], 32\n\ts_mov_b32 s2, s1\n\tv_or_b32_e64 v4, v4, s2\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_or_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_mov_b32_e32 v1, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[2:3], s0, v[2:3]\n ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\tv_mov_b32_e32 v16, 0\n\tscratch_store_b32 off, v16, s33 offset:88 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v16\n\tv_mov_b32_e32 v4, v16\n\tv_mov_b32_e32 v5, v16\n\tv_mov_b32_e32 v6, v16\n\tv_mov_b32_e32 v7, v16\n\tv_mov_b32_e32 v8, v16\n\tv_mov_b32_e32 v9, v16\n\tv_mov_b32_e32 v10, v16\n\tv_mov_b32_e32 v11, v16\n\tv_mov_b32_e32 v12, v16\n\tv_mov_b32_e32 v13, v16\n\tv_mov_b32_e32 v14, v16\n\tv_mov_b32_e32 v15, v16\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_mov_b32_e32 v6, v1\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v4, v3\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v6\n\tv_mov_b32_e32 v2, v5\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b128 off, v[0:3], s33 offset:72 ; 16-byte Folded Spill\n\ts_branch .LBB6_63\n.LBB6_2:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b64 v[4:5], off, s33 offset:36 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:44 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:28 ; 8-byte Folded Reload\n\ts_mov_b64 s[0:1], 2\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v1, v3\n\tv_and_b32_e64 v8, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v0, v2\n\tv_and_b32_e64 v2, v0, s0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v8\n\tscratch_store_b64 off, v[2:3], s33 offset:124 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], -3\n\ts_mov_b32 s2, s1\n\tv_and_b32_e64 v2, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_and_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v10, v1\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\ts_mov_b64 s[2:3], 0\n\ts_mov_b32 s0, s3\n\ts_mov_b32 s1, s2\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v9, s1\n\tv_mov_b32_e32 v8, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v10\n\tv_mov_b32_e32 v2, v9\n\tv_mov_b32_e32 v3, v8\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v34, s0, 13\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[6:7], s33 offset:116 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[4:5], s33 offset:108 ; 8-byte Folded Spill\n\tscratch_store_b128 off, v[0:3], s33 offset:92 ; 16-byte Folded Spill\n\ts_branch .LBB6_4\n.LBB6_3:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 12\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b128 v[0:3], off, s33 offset:12 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:72 ; 16-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 14\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_63\n\ts_branch .LBB6_1\n.LBB6_4: ; =>This Loop Header: Depth=1\n ; Child Loop BB6_8 Depth 2\n ; Child Loop BB6_16 Depth 2\n ; Child Loop BB6_24 Depth 2\n ; Child Loop BB6_32 Depth 2\n ; Child Loop BB6_40 Depth 2\n ; Child Loop BB6_48 Depth 2\n ; Child Loop BB6_56 Depth 2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 13\n\tscratch_load_b64 v[6:7], off, s33 offset:124 ; 8-byte Folded Reload\n\tscratch_load_b128 v[8:11], off, s33 offset:92 ; 16-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:116 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:108 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:176 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[3:4], s33 offset:168 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 15\n\ts_mov_b64 s[2:3], 56\n\tv_cmp_gt_u64_e64 s0, v[3:4], s[2:3]\n\tv_mov_b32_e32 v1, v9\n\tv_mov_b32_e32 v2, v8\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v8, v2\n\tv_mov_b32_e32 v9, v1\n\tv_mov_b32_e32 v0, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or_b32_e64 v0, v0, v5\n\tv_mov_b32_e32 v5, v8\n\tv_or_b32_e64 v5, v5, v6\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v0\n\tv_mov_b32_e32 v0, v6\n\tv_cndmask_b32_e64 v0, v0, v1, s0\n\tv_mov_b32_e32 v1, v5\n\tv_cndmask_b32_e64 v1, v1, v2, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_cmp_lt_u64_e64 s1, v[3:4], s[2:3]\n\tv_mov_b32_e32 v0, v4\n\ts_mov_b32 s0, s3\n\tv_cndmask_b32_e64 v5, s0, v0, s1\n\tv_mov_b32_e32 v0, v3\n\ts_mov_b32 s0, s2\n\tv_cndmask_b32_e64 v0, s0, v0, s1\n\tscratch_store_b32 off, v0, s33 offset:164 ; 4-byte Folded Spill\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v3, v0\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:156 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:148 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:140 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:132 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 16\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_6\n; %bb.5: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:164 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 17\n\tv_writelane_b32 v34, s0, 18\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:184 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_11\n\ts_branch .LBB6_8\n.LBB6_6: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 16\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 20\n\tscratch_load_b64 v[0:1], off, s33 offset:140 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:132 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:212 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:208 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:200 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 21\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_12\n; %bb.7: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:212 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:208 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:200 ; 8-byte Folded Spill\n\ts_branch .LBB6_12\n.LBB6_8: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 18\n\tv_readlane_b32 s2, v34, 17\n\tscratch_load_b64 v[4:5], off, s33 offset:192 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:176 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 17\n\tv_writelane_b32 v34, s1, 18\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:220 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 22\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_8\n; %bb.9: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.10: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:220 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:184 ; 8-byte Folded Spill\n.LBB6_11: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 19\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:140 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 20\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:132 ; 8-byte Folded Spill\n\ts_branch .LBB6_6\n.LBB6_12: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:212 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:208 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:200 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:256 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:252 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:244 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:236 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:228 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 23\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_14\n; %bb.13: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:252 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 24\n\tv_writelane_b32 v34, s0, 25\n\tscratch_store_b64 off, v[2:3], s33 offset:272 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:264 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 26\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_19\n\ts_branch .LBB6_16\n.LBB6_14: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 23\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 27\n\tscratch_load_b64 v[0:1], off, s33 offset:236 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:228 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:292 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:288 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:280 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 28\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_20\n; %bb.15: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:244 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:252 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:292 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:288 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:280 ; 8-byte Folded Spill\n\ts_branch .LBB6_20\n.LBB6_16: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 25\n\tv_readlane_b32 s2, v34, 24\n\tscratch_load_b64 v[4:5], off, s33 offset:272 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:252 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:244 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 24\n\tv_writelane_b32 v34, s1, 25\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:272 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:300 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 29\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_16\n; %bb.17: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.18: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:300 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:264 ; 8-byte Folded Spill\n.LBB6_19: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 26\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:244 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:264 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:236 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 27\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:228 ; 8-byte Folded Spill\n\ts_branch .LBB6_14\n.LBB6_20: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 28\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:292 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:288 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:280 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:336 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:332 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:324 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:316 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:308 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 30\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_22\n; %bb.21: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:332 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v33, s2, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tv_writelane_b32 v34, s0, 0\n\tscratch_store_b64 off, v[2:3], s33 offset:352 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:344 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_27\n\ts_branch .LBB6_24\n.LBB6_22: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v33, 30\n\ts_or_saveexec_b32 s0, s0\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v34, 2\n\tscratch_load_b64 v[0:1], off, s33 offset:316 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:308 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:372 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:368 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:360 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 3\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_28\n; %bb.23: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:324 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:332 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:372 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:368 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:360 ; 8-byte Folded Spill\n\ts_branch .LBB6_28\n.LBB6_24: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 0\n\tv_readlane_b32 s2, v33, 31\n\tscratch_load_b64 v[4:5], off, s33 offset:352 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:332 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:324 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v33, s2, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tv_writelane_b32 v34, s1, 0\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:352 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:380 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 4\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_24\n; %bb.25: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.26: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:380 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:344 ; 8-byte Folded Spill\n.LBB6_27: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:324 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:344 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:316 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:308 ; 8-byte Folded Spill\n\ts_branch .LBB6_22\n.LBB6_28: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 3\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:372 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:368 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:360 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:416 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:412 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:404 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:396 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:388 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 5\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_30\n; %bb.29: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:412 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 6\n\tv_writelane_b32 v34, s0, 7\n\tscratch_store_b64 off, v[2:3], s33 offset:432 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:424 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 8\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_35\n\ts_branch .LBB6_32\n.LBB6_30: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 5\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 9\n\tscratch_load_b64 v[0:1], off, s33 offset:396 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:388 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:452 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:448 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:440 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 10\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_36\n; %bb.31: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:404 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:412 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:452 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:448 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:440 ; 8-byte Folded Spill\n\ts_branch .LBB6_36\n.LBB6_32: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 7\n\tv_readlane_b32 s2, v34, 6\n\tscratch_load_b64 v[4:5], off, s33 offset:432 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:412 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:404 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 6\n\tv_writelane_b32 v34, s1, 7\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:432 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:460 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 11\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_32\n; %bb.33: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 11\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.34: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:460 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:424 ; 8-byte Folded Spill\n.LBB6_35: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 8\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:404 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:424 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:396 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 9\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:388 ; 8-byte Folded Spill\n\ts_branch .LBB6_30\n.LBB6_36: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 10\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:452 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:448 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:440 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:496 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:492 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:484 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:476 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:468 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 12\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_38\n; %bb.37: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:492 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 13\n\tv_writelane_b32 v34, s0, 14\n\tscratch_store_b64 off, v[2:3], s33 offset:512 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:504 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 15\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_43\n\ts_branch .LBB6_40\n.LBB6_38: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 12\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 16\n\tscratch_load_b64 v[0:1], off, s33 offset:476 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:468 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:532 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:528 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:520 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 17\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_44\n; %bb.39: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:484 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:492 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:532 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:528 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:520 ; 8-byte Folded Spill\n\ts_branch .LBB6_44\n.LBB6_40: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 14\n\tv_readlane_b32 s2, v34, 13\n\tscratch_load_b64 v[4:5], off, s33 offset:512 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:492 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:484 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 13\n\tv_writelane_b32 v34, s1, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:512 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:540 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 18\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_40\n; %bb.41: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 18\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.42: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:540 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:504 ; 8-byte Folded Spill\n.LBB6_43: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:484 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:504 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:476 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 16\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:468 ; 8-byte Folded Spill\n\ts_branch .LBB6_38\n.LBB6_44: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 17\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:532 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:528 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:520 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:576 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:572 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:564 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:556 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:548 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_46\n; %bb.45: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:572 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 20\n\tv_writelane_b32 v34, s0, 21\n\tscratch_store_b64 off, v[2:3], s33 offset:592 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:584 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 22\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_51\n\ts_branch .LBB6_48\n.LBB6_46: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 19\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 23\n\tscratch_load_b64 v[0:1], off, s33 offset:556 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:548 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:612 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:608 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:600 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 24\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_52\n; %bb.47: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:564 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:572 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:612 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:608 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:600 ; 8-byte Folded Spill\n\ts_branch .LBB6_52\n.LBB6_48: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 21\n\tv_readlane_b32 s2, v34, 20\n\tscratch_load_b64 v[4:5], off, s33 offset:592 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:572 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:564 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 20\n\tv_writelane_b32 v34, s1, 21\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:592 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:620 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 25\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_48\n; %bb.49: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 25\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.50: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:620 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:584 ; 8-byte Folded Spill\n.LBB6_51: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:564 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:584 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:556 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 23\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:548 ; 8-byte Folded Spill\n\ts_branch .LBB6_46\n.LBB6_52: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 24\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:612 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:608 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:600 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:648 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:644 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:636 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s33 offset:628 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 26\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_54\n; %bb.53: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:644 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 27\n\tv_writelane_b32 v34, s0, 28\n\tscratch_store_b64 off, v[2:3], s33 offset:664 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:656 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 29\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_59\n\ts_branch .LBB6_56\n.LBB6_54: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 26\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:628 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:672 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 30\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_60\n; %bb.55: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[2:3], off, s33 offset:636 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tflat_load_u8 v0, v[2:3]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v4, v[2:3] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v5, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v7, v1\n\tv_mov_b32_e32 v4, v6\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v5\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v4\n\tflat_load_u8 v4, v[2:3] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v8, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v4\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v10, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or3_b32 v4, v4, v5, v10\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v5, v8\n\tv_mov_b32_e32 v1, v6\n\tv_or3_b32 v0, v0, v1, v5\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v4, s1, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[6:7], s2, v[4:5]\n\tflat_load_u8 v4, v[2:3] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v4, s1, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[8:9], s0, v[4:5]\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v10, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or3_b32 v4, v4, v5, v10\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v5, v8\n\tv_mov_b32_e32 v1, v6\n\tv_or3_b32 v0, v0, v1, v5\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:6\n\tv_mov_b32_e32 v6, 0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[4:5], s0, v[4:5]\n\tflat_load_u8 v2, v[2:3] offset:7\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v6\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[6:7], s0, v[2:3]\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v8, v7\n\tv_mov_b32_e32 v3, v5\n\tv_or3_b32 v2, v2, v3, v8\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v3, v6\n\tv_mov_b32_e32 v1, v4\n\tv_or3_b32 v0, v0, v1, v3\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:672 ; 8-byte Folded Spill\n\ts_branch .LBB6_60\n.LBB6_56: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 28\n\tv_readlane_b32 s2, v34, 27\n\tscratch_load_b64 v[4:5], off, s33 offset:664 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:644 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:636 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 27\n\tv_writelane_b32 v34, s1, 28\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:664 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:680 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_56\n; %bb.57: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 31\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.58: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:680 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:656 ; 8-byte Folded Spill\n.LBB6_59: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:656 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:628 ; 8-byte Folded Spill\n\ts_branch .LBB6_54\n.LBB6_60: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v34, 30\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v33, 2\n\tv_readlane_b32 s14, v33, 3\n\tv_readlane_b32 s13, v33, 4\n\tv_readlane_b32 s12, v33, 5\n\tv_readlane_b32 s10, v33, 6\n\tv_readlane_b32 s11, v33, 7\n\tv_readlane_b32 s8, v33, 8\n\tv_readlane_b32 s9, v33, 9\n\tv_readlane_b32 s6, v33, 0\n\tv_readlane_b32 s7, v33, 1\n\tv_readlane_b32 s4, v33, 10\n\tv_readlane_b32 s5, v33, 11\n\tscratch_load_b64 v[0:1], off, s33 offset:156 ; 8-byte Folded Reload\n\tscratch_load_b32 v31, off, s33 offset:68 ; 4-byte Folded Reload\n\tscratch_load_b64 v[19:20], off, s33 offset:648 ; 8-byte Folded Reload\n\tscratch_load_b64 v[21:22], off, s33 offset:576 ; 8-byte Folded Reload\n\tscratch_load_b64 v[23:24], off, s33 offset:496 ; 8-byte Folded Reload\n\tscratch_load_b64 v[25:26], off, s33 offset:416 ; 8-byte Folded Reload\n\tscratch_load_b64 v[27:28], off, s33 offset:336 ; 8-byte Folded Reload\n\tscratch_load_b64 v[29:30], off, s33 offset:256 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:148 ; 8-byte Folded Reload\n\tscratch_load_b64 v[17:18], off, s33 offset:672 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(9)\n\tv_mov_b32_e32 v1, v0\n\ts_mov_b32 s0, 28\n\tv_mov_b32_e32 v0, 2\n\tv_lshl_add_u32 v1, v1, v0, s0\n\ts_mov_b32 s0, 0x1e0\n\tv_and_b32_e64 v5, v1, s0\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v1, 0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v1\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v1, v3\n\tv_and_b32_e64 v1, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v4, v2\n\tv_and_b32_e64 v7, v4, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v4, v6\n\tv_or_b32_e64 v1, v1, v4\n\tv_mov_b32_e32 v4, v7\n ; kill: def $vgpr5 killed $vgpr5 killed $vgpr5_vgpr6 killed $exec\n\tv_or_b32_e64 v4, v4, v5\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v1\n\tv_mov_b32_e32 v1, v4\n\ts_mov_b32 s0, 32\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\tv_writelane_b32 v34, s0, 0\n\tv_lshrrev_b64 v[2:3], s0, v[2:3]\n ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec\n\tv_lshrrev_b64 v[3:4], s0, v[29:30]\n\tv_mov_b32_e32 v4, v3\n\tv_lshrrev_b64 v[5:6], s0, v[27:28]\n\tv_mov_b32_e32 v6, v5\n\tv_lshrrev_b64 v[7:8], s0, v[25:26]\n\tv_mov_b32_e32 v8, v7\n\tv_lshrrev_b64 v[9:10], s0, v[23:24]\n\tv_mov_b32_e32 v10, v9\n\tv_lshrrev_b64 v[11:12], s0, v[21:22]\n\tv_mov_b32_e32 v12, v11\n\tv_lshrrev_b64 v[13:14], s0, v[19:20]\n\tv_mov_b32_e32 v14, v13\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[15:16], s0, v[17:18]\n\tv_mov_b32_e32 v16, v15\n\tv_mov_b32_e32 v3, v29\n\tv_mov_b32_e32 v5, v27\n\tv_mov_b32_e32 v7, v25\n\tv_mov_b32_e32 v9, v23\n\tv_mov_b32_e32 v11, v21\n\tv_mov_b32_e32 v13, v19\n\tv_mov_b32_e32 v15, v17\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b64 v[4:5], off, s33 offset:168 ; 8-byte Folded Reload\n\tscratch_load_b64 v[12:13], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b64 v[10:11], off, s33 offset:156 ; 8-byte Folded Reload\n\tv_readlane_b32 s1, v33, 15\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v7, v2\n\tv_mov_b32_e32 v6, v3\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v2, v7\n\tv_mov_b32_e32 v3, v6\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v6, v4\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v5, v11\n\tv_sub_co_u32 v6, s0, v6, v7\n\tv_sub_co_ci_u32_e64 v4, s0, v4, v5, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v4\n\tv_mov_b32_e32 v4, v12\n\tv_mov_b32_e32 v9, v10\n\tv_mov_b32_e32 v5, v13\n\tv_mov_b32_e32 v8, v11\n\tv_add_co_u32 v4, s0, v4, v9\n\tv_add_co_ci_u32_e64 v8, s0, v5, v8, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v8\n\ts_mov_b64 s[2:3], 0\n\tv_cmp_eq_u64_e64 s0, v[6:7], s[2:3]\n\ts_or_b32 s0, s0, s1\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v33, s1, 13\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[6:7], s33 offset:116 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[4:5], s33 offset:108 ; 8-byte Folded Spill\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v6, v2\n\tv_mov_b32_e32 v5, v1\n\tv_mov_b32_e32 v4, v0\n\tscratch_store_b128 off, v[4:7], s33 offset:92 ; 16-byte Folded Spill\n\tscratch_store_b128 off, v[0:3], s33 offset:688 ; 16-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:8 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_4\n; %bb.61:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:8 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.62:\n\tscratch_load_b128 v[0:3], off, s33 offset:688 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:12 ; 16-byte Folded Spill\n\ts_branch .LBB6_3\n.LBB6_63:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 14\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b128 v[3:6], off, s33 offset:72 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v0, v3\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v32, 0\n\tv_readlane_b32 s31, v32, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v32, off, s33 offset:704 ; 4-byte Folded Reload\n\tscratch_load_b32 v33, off, s33 offset:708 ; 4-byte Folded Reload\n\tscratch_load_b32 v34, off, s33 offset:712 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xfffffd30\n\ts_mov_b32 s33, s20\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end6:\n\t.size\t__ockl_fprintf_append_string_n, .Lfunc_end6-__ockl_fprintf_append_string_n\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 11984\n; NumSgprs: 36\n; NumVgprs: 35\n; ScratchSize: 1120\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_append_args\n\t.type\t__ockl_fprintf_append_args,@function\n__ockl_fprintf_append_args: ; @__ockl_fprintf_append_args\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s19, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v28, s33 offset:8 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v29, s33 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 32\n\tv_writelane_b32 v28, s30, 0\n\tv_writelane_b32 v28, s31, 1\n\tscratch_store_b32 off, v17, s33 offset:4 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v17, v2\n\tv_mov_b32_e32 v18, v0\n\tscratch_load_b32 v0, off, s33 offset:4 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v15\n ; kill: def $vgpr20 killed $vgpr16 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v13\n ; kill: def $vgpr20 killed $vgpr14 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v11\n ; kill: def $vgpr20 killed $vgpr12 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v9\n ; kill: def $vgpr20 killed $vgpr10 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v7\n ; kill: def $vgpr20 killed $vgpr8 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v5\n ; kill: def $vgpr20 killed $vgpr6 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v3\n ; kill: def $vgpr20 killed $vgpr4 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr18 killed $vgpr18 def $vgpr18_vgpr19 killed $exec\n\tv_mov_b32_e32 v19, v1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s0, v0, s0\n\tv_mov_b32_e32 v1, v19\n\ts_mov_b64 s[2:3], 2\n\ts_mov_b32 s1, s3\n\tv_or_b32_e64 v0, v1, s1\n\tv_mov_b32_e32 v2, v18\n\ts_mov_b32 s1, s2\n\tv_or_b32_e64 v18, v2, s1\n ; kill: def $vgpr18 killed $vgpr18 def $vgpr18_vgpr19 killed $exec\n\tv_mov_b32_e32 v19, v0\n\tv_mov_b32_e32 v0, v19\n\tv_cndmask_b32_e64 v0, v0, v1, s0\n\tv_mov_b32_e32 v1, v18\n\tv_cndmask_b32_e64 v1, v1, v2, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v0, v2\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\tv_and_b32_e64 v0, v0, s2\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_and_b32_e64 v1, v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\tv_mov_b32_e32 v18, v0\n\ts_mov_b32 s0, 5\n\tv_lshlrev_b64 v[17:18], s0, v[17:18]\n\tv_mov_b32_e32 v0, v2\n\tv_mov_b32_e32 v19, v18\n\tv_or_b32_e64 v0, v0, v19\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v17\n\tv_or_b32_e64 v17, v1, v2\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\tv_mov_b32_e32 v18, v0\n\tv_mov_b32_e32 v1, v17\n\ts_mov_b32 s0, 32\n ; implicit-def: $vgpr29 : SGPR spill to VGPR lane\n\tv_writelane_b32 v29, s0, 0\n\tv_lshrrev_b64 v[17:18], s0, v[17:18]\n\tv_mov_b32_e32 v2, v17\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v29, 0\n\tscratch_store_b32 off, v1, s33 ; 4-byte Folded Spill\n ; kill: def $vgpr1 killed $vgpr3 killed $exec\n\tscratch_load_b32 v3, off, s33 ; 4-byte Folded Reload\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v1, s1\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v3\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v28, 0\n\tv_readlane_b32 s31, v28, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v28, off, s33 offset:8 ; 4-byte Folded Reload\n\tscratch_load_b32 v29, off, s33 offset:12 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xffffffe0\n\ts_mov_b32 s33, s19\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end7:\n\t.size\t__ockl_fprintf_append_args, .Lfunc_end7-__ockl_fprintf_append_args\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 452\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 432\n; MemoryBound: 0\n\t.text\n\t.hidden\t__assert_fail ; -- Begin function __assert_fail\n\t.weak\t__assert_fail\n\t.p2align\t2\n\t.type\t__assert_fail,@function\n__assert_fail: ; @__assert_fail\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s27, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v35, s33 offset:176 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v36, s33 offset:180 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v37, s33 offset:184 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xc0\n\tv_writelane_b32 v35, s30, 0\n\tv_writelane_b32 v35, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:168 ; 4-byte Folded Spill\n ; implicit-def: $vgpr37 : SGPR spill to VGPR lane\n\tv_writelane_b32 v37, s6, 0\n\tv_writelane_b32 v37, s7, 1\n\tscratch_store_b32 off, v5, s33 offset:164 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v3, s33 offset:160 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v5, v2\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v7, v0\n\tscratch_load_b32 v0, off, s33 offset:160 ; 4-byte Folded Reload\n\tv_writelane_b32 v37, s15, 2\n\tv_writelane_b32 v37, s14, 3\n\tv_writelane_b32 v37, s13, 4\n\tv_writelane_b32 v37, s12, 5\n\tv_writelane_b32 v37, s10, 6\n\tv_writelane_b32 v37, s11, 7\n\tv_writelane_b32 v37, s8, 8\n\tv_writelane_b32 v37, s9, 9\n\tv_writelane_b32 v37, s4, 10\n\tv_writelane_b32 v37, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v6, v0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b64 s[0:1], src_private_base\n\ts_mov_b32 s2, 32\n\ts_lshr_b64 s[0:1], s[0:1], s2\n\ts_mov_b32 s24, s0\n\tv_writelane_b32 v37, s24, 12\n\ts_mov_b32 s20, s33\n ; kill: def $sgpr20 killed $sgpr20 def $sgpr20_sgpr21\n\ts_mov_b32 s21, s24\n\ts_mov_b64 s[0:1], s[20:21]\n\tv_writelane_b32 v37, s0, 13\n\tv_writelane_b32 v37, s1, 14\n\ts_add_i32 s0, s33, 8\n\ts_mov_b32 s18, s0\n ; kill: def $sgpr18 killed $sgpr18 def $sgpr18_sgpr19\n\ts_mov_b32 s19, s24\n\ts_mov_b64 s[0:1], s[18:19]\n\tv_writelane_b32 v37, s0, 15\n\tv_writelane_b32 v37, s1, 16\n\ts_add_i32 s0, s33, 16\n\ts_mov_b32 s2, s0\n ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3\n\ts_mov_b32 s3, s24\n\ts_mov_b64 s[0:1], s[2:3]\n\tv_writelane_b32 v37, s0, 17\n\tv_writelane_b32 v37, s1, 18\n\ts_add_i32 s1, s33, 24\n\ts_mov_b32 s0, s1\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s24\n\ts_mov_b64 s[16:17], s[0:1]\n\tv_writelane_b32 v37, s16, 19\n\tv_writelane_b32 v37, s17, 20\n\ts_add_i32 s17, s33, 32\n\ts_mov_b32 s16, s17\n ; kill: def $sgpr16 killed $sgpr16 def $sgpr16_sgpr17\n\ts_mov_b32 s17, s24\n\tv_writelane_b32 v37, s16, 21\n\tv_writelane_b32 v37, s17, 22\n\ts_mov_b64 s[22:23], s[16:17]\n\tv_writelane_b32 v37, s22, 23\n\tv_writelane_b32 v37, s23, 24\n\ts_add_i32 s23, s33, 0x50\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v37, s22, 25\n\tv_writelane_b32 v37, s23, 26\n\tv_writelane_b32 v37, s22, 27\n\tv_writelane_b32 v37, s23, 28\n\ts_add_i32 s23, s33, 0x58\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v37, s22, 29\n\tv_writelane_b32 v37, s23, 30\n ; implicit-def: $vgpr36 : SGPR spill to VGPR lane\n\tv_writelane_b32 v37, s22, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:148 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_writelane_b32 v36, s23, 0\n\ts_add_i32 s23, s33, 0x60\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 1\n\tv_writelane_b32 v36, s23, 2\n\ts_add_i32 s23, s33, 0x68\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 3\n\tv_writelane_b32 v36, s23, 4\n\ts_add_i32 s23, s33, 0x70\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 5\n\tv_writelane_b32 v36, s23, 6\n\ts_add_i32 s23, s33, 0x78\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 7\n\tv_writelane_b32 v36, s23, 8\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_mov_b32_e32 v0, s20\n\tv_mov_b32_e32 v1, s21\n\tflat_store_b64 v[0:1], v[7:8]\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tflat_store_b64 v[0:1], v[5:6]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b32 v[0:1], v4\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, s33 offset:156 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+35\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+43\n\tglobal_load_b128 v[0:3], v0, s[0:1]\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:128\n\tscratch_load_b64 v[0:1], off, s33 offset:136\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_d16_hi_b8 v[3:4], v2 offset:45\n\ts_mov_b32 s1, 24\n\tv_lshrrev_b32_e64 v5, s1, v2\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v5 offset:46\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v2 offset:43\n\ts_mov_b32 s0, 8\n\tv_lshrrev_b32_e64 v4, s0, v2\n\tv_mov_b32_e32 v2, s16\n\tv_mov_b32_e32 v3, s17\n\tflat_store_b8 v[2:3], v4 offset:44\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_d16_hi_b8 v[1:2], v0 offset:41\n\tv_lshrrev_b32_e64 v3, s1, v0\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v3 offset:42\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v0 offset:39\n\tv_lshrrev_b32_e64 v2, s0, v0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b8 v[0:1], v2 offset:40\n\tscratch_load_b64 v[0:1], off, s33 offset:128\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_d16_hi_b8 v[3:4], v2 offset:37\n\tv_lshrrev_b32_e64 v5, s1, v2\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v5 offset:38\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v2 offset:35\n\tv_lshrrev_b32_e64 v4, s0, v2\n\tv_mov_b32_e32 v2, s16\n\tv_mov_b32_e32 v3, s17\n\tflat_store_b8 v[2:3], v4 offset:36\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_d16_hi_b8 v[1:2], v0 offset:33\n\tv_lshrrev_b32_e64 v3, s1, v0\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v3 offset:34\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v0 offset:31\n\tv_lshrrev_b32_e64 v2, s0, v0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b8 v[0:1], v2 offset:32\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+20\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+28\n\ts_load_b128 s[0:3], s[0:1], 0x0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v5, s3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b128 v[0:1], v[2:5] offset:16\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+4\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+12\n\ts_load_b128 s[0:3], s[0:1], 0x0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v5, s3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b128 v[0:1], v[2:5]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_stderr_begin@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_stderr_begin@rel32@hi+12\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v2, off, s33 offset:156 ; 4-byte Folded Reload\n\tv_readlane_b32 s2, v37, 25\n\tv_readlane_b32 s3, v37, 26\n\tv_readlane_b32 s0, v37, 29\n\tv_readlane_b32 s1, v37, 30\n\tv_mov_b32_e32 v3, v0\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b64 v[0:1], v[3:4]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0)\n\tflat_store_b32 v[0:1], v2\n; %bb.1:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 23\n\tv_readlane_b32 s1, v36, 24\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s3, v37, 2\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 9\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_2: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s3, v37, 2\n\tv_readlane_b32 s0, v37, 10\n\tv_readlane_b32 s1, v37, 9\n\tv_writelane_b32 v37, s1, 11\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 12\n\tv_writelane_b32 v37, s0, 13\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 14\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_4\n; %bb.3: ; in Loop: Header=BB8_2 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 12\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 13\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_4: ; in Loop: Header=BB8_2 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 14\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 11\n\tv_readlane_b32 s1, v37, 13\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 10\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 9\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 15\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_2\n; %bb.5:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.6:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 23\n\tv_readlane_b32 s3, v36, 24\n\tv_readlane_b32 s4, v37, 1\n\tv_readlane_b32 s5, v37, 2\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, s2\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.7:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 23\n\tv_readlane_b32 s1, v37, 24\n\tv_readlane_b32 s2, v37, 31\n\tv_readlane_b32 s3, v36, 0\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v5, v4\n\tv_mov_b32_e32 v6, v0\n\ts_mov_b32 s3, 32\n\ts_lshr_b64 s[16:17], s[0:1], s3\n\ts_mov_b32 s2, s16\n\tv_lshrrev_b64 v[0:1], s3, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[5:6], s3, v[5:6]\n ; kill: def $vgpr5 killed $vgpr5 killed $vgpr5_vgpr6 killed $exec\n\ts_mov_b32 s3, s0\n\tv_mov_b32_e32 v0, v2\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v2, s3\n\tv_mov_b32_e32 v3, s2\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.8:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 3\n\tv_readlane_b32 s1, v37, 4\n\tv_readlane_b32 s2, v36, 15\n\tv_readlane_b32 s3, v36, 16\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 16\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_9: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 3\n\tv_readlane_b32 s3, v37, 4\n\tv_readlane_b32 s0, v37, 17\n\tv_readlane_b32 s1, v37, 16\n\tv_writelane_b32 v37, s1, 18\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 19\n\tv_writelane_b32 v37, s0, 20\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 21\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_11\n; %bb.10: ; in Loop: Header=BB8_9 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 19\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 20\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_11: ; in Loop: Header=BB8_9 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 18\n\tv_readlane_b32 s1, v37, 20\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 17\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 16\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 22\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_9\n; %bb.12:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.13:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 15\n\tv_readlane_b32 s3, v36, 16\n\tv_readlane_b32 s4, v37, 3\n\tv_readlane_b32 s5, v37, 4\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.14:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 15\n\tv_readlane_b32 s3, v37, 16\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_writelane_b32 v36, s0, 23\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\tscratch_store_b32 off, v6, s33 offset:172 ; 4-byte Folded Spill\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tscratch_load_b32 v17, off, s33 offset:172 ; 4-byte Folded Reload\n\tv_readlane_b32 s2, v37, 17\n\tv_readlane_b32 s3, v37, 18\n\tv_readlane_b32 s0, v36, 23\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v3, v[0:1]\n\ts_waitcnt vmcnt(1) lgkmcnt(1)\n\tv_lshrrev_b64 v[0:1], s0, v[4:5]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v4\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_args@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_args@rel32@hi+12\n\tv_mov_b32_e32 v2, 1\n\tv_mov_b32_e32 v4, v17\n\tv_mov_b32_e32 v5, v17\n\tv_mov_b32_e32 v6, v17\n\tv_mov_b32_e32 v7, v17\n\tv_mov_b32_e32 v8, v17\n\tv_mov_b32_e32 v9, v17\n\tv_mov_b32_e32 v10, v17\n\tv_mov_b32_e32 v11, v17\n\tv_mov_b32_e32 v12, v17\n\tv_mov_b32_e32 v13, v17\n\tv_mov_b32_e32 v14, v17\n\tv_mov_b32_e32 v15, v17\n\tv_mov_b32_e32 v16, v17\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.15:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 5\n\tv_readlane_b32 s1, v37, 6\n\tv_readlane_b32 s2, v36, 19\n\tv_readlane_b32 s3, v36, 20\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 24\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_16: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 5\n\tv_readlane_b32 s3, v37, 6\n\tv_readlane_b32 s0, v37, 25\n\tv_readlane_b32 s1, v37, 24\n\tv_writelane_b32 v37, s1, 26\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 27\n\tv_writelane_b32 v37, s0, 28\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 29\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_18\n; %bb.17: ; in Loop: Header=BB8_16 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 27\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 28\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_18: ; in Loop: Header=BB8_16 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 26\n\tv_readlane_b32 s1, v37, 28\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 25\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 24\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 30\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_16\n; %bb.19:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 30\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.20:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 19\n\tv_readlane_b32 s3, v36, 20\n\tv_readlane_b32 s4, v37, 5\n\tv_readlane_b32 s5, v37, 6\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.21:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 19\n\tv_readlane_b32 s3, v37, 20\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.22:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 7\n\tv_readlane_b32 s1, v37, 8\n\tv_readlane_b32 s2, v36, 13\n\tv_readlane_b32 s3, v36, 14\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_23: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v36, 7\n\tv_readlane_b32 s3, v36, 8\n ; implicit-def: $vgpr37 : SGPR spill to VGPR lane\n\tv_readlane_b32 s0, v37, 0\n\tv_readlane_b32 s1, v36, 31\n\tv_writelane_b32 v37, s1, 1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 2\n\tv_writelane_b32 v37, s0, 3\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 4\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_25\n; %bb.24: ; in Loop: Header=BB8_23 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 2\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 3\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_25: ; in Loop: Header=BB8_23 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s1, v37, 3\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 0\n\ts_mov_b32 s1, s0\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v36, s1, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 5\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_23\n; %bb.26:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 5\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.27:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 13\n\tv_readlane_b32 s3, v36, 14\n\tv_readlane_b32 s4, v37, 7\n\tv_readlane_b32 s5, v37, 8\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.28:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 13\n\tv_readlane_b32 s3, v37, 14\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 1\n\ts_swappc_b64 s[30:31], s[0:1]\n\ts_cbranch_execnz .LBB8_30\n; %bb.29:\n\tv_readlane_b32 s30, v35, 0\n\tv_readlane_b32 s31, v35, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v35, off, s33 offset:176 ; 4-byte Folded Reload\n\tscratch_load_b32 v36, off, s33 offset:180 ; 4-byte Folded Reload\n\tscratch_load_b32 v37, off, s33 offset:184 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xffffff40\n\ts_mov_b32 s33, s27\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.LBB8_30:\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB8_31: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB8_31\n.Lfunc_end8:\n\t.size\t__assert_fail, .Lfunc_end8-__assert_fail\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 6148\n; NumSgprs: 36\n; NumVgprs: 38\n; ScratchSize: 1312\n; MemoryBound: 0\n\t.text\n\t.hidden\t__assertfail ; -- Begin function __assertfail\n\t.weak\t__assertfail\n\t.p2align\t2\n\t.type\t__assertfail,@function\n__assertfail: ; @__assertfail\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_cbranch_execnz .LBB9_2\n; %bb.1:\n\ts_setpc_b64 s[30:31]\n.LBB9_2:\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB9_3: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB9_3\n.Lfunc_end9:\n\t.size\t__assertfail, .Lfunc_end9-__assertfail\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 64\n; NumSgprs: 32\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_get_group_id\n\t.type\t__ockl_get_group_id,@function\n__ockl_get_group_id: ; @__ockl_get_group_id\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v2, s32 offset:32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill\n ; implicit-def: $vgpr2 : SGPR spill to VGPR lane\n\tv_writelane_b32 v2, s14, 0\n\tv_writelane_b32 v2, s13, 1\n\tv_writelane_b32 v2, s12, 2\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n; %bb.1:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v2, s1, 3\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_4\n; %bb.2:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v2, s1, 4\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_7\n; %bb.3:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 5\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_10\n\ts_branch .LBB10_9\n.LBB10_4:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 3\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 6\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB10_13\n; %bb.5:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 7\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_12\n; %bb.6:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 2\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_branch .LBB10_12\n.LBB10_7:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 4\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:12 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 8\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB10_11\n; %bb.8:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 1\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_branch .LBB10_11\n.LBB10_9:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 0\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n.LBB10_10:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 5\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:16 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_branch .LBB10_7\n.LBB10_11:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 8\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill\n\ts_branch .LBB10_4\n.LBB10_12:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 7\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:24 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n.LBB10_13:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 6\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:20 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v1, 0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v2, off, s32 offset:32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end10:\n\t.size\t__ockl_get_group_id, .Lfunc_end10-__ockl_get_group_id\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 988\n; NumSgprs: 33\n; NumVgprs: 3\n; ScratchSize: 40\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_get_local_size\n\t.type\t__ockl_get_local_size,@function\n__ockl_get_local_size: ; @__ockl_get_local_size\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v4, s32 offset:104 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill\n ; implicit-def: $vgpr4 : SGPR spill to VGPR lane\n\tv_writelane_b32 v4, s14, 0\n\tv_writelane_b32 v4, s13, 1\n\tv_writelane_b32 v4, s12, 2\n\tv_writelane_b32 v4, s8, 3\n\tv_writelane_b32 v4, s9, 4\n\tv_writelane_b32 v4, s4, 5\n\tv_writelane_b32 v4, s5, 6\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n; %bb.1:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:8 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v4, s1, 7\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_4\n; %bb.2:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:16 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v4, s1, 8\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_10\n; %bb.3:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 1\n\tv_mov_b32_e32 v0, 1\n\tv_mov_b32_e32 v1, 0\n\tscratch_store_b64 off, v[0:1], s32 offset:24 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v4, s0, 9\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_20\n\ts_branch .LBB11_15\n.LBB11_4:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 7\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:8 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:32 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v4, s0, 10\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB11_25\n; %bb.5:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 1\n\tv_mov_b32_e32 v0, 1\n\tv_mov_b32_e32 v1, 0\n\tscratch_store_b64 off, v[0:1], s32 offset:40 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v4, s0, 11\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_24\n; %bb.6:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n ; implicit-def: $sgpr2_sgpr3\n\ts_mov_b32 s4, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s4\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:48 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v4, s0, 12\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB11_9\n.LBB11_7:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 12\n\tscratch_load_b64 v[0:1], off, s32 offset:48 ; 8-byte Folded Reload\n\tv_cndmask_b32_e64 v2, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v2, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n ; kill: def $vgpr0_vgpr1 killed $vgpr0_vgpr1 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:56 ; 8-byte Folded Spill\n\ts_cbranch_vccnz .LBB11_23\n; %bb.8:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v4, 2\n\tv_readlane_b32 s2, v4, 5\n\tv_readlane_b32 s3, v4, 6\n\tv_mov_b32_e32 v0, 0\n\tglobal_load_u16 v1, v0, s[2:3] offset:4\n\ts_load_b32 s0, s[2:3], 0xc\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v0, s1, v1\n\ts_waitcnt lgkmcnt(0)\n\tv_sub_nc_u32_e64 v0, s0, v0\n ; implicit-def: $sgpr0\n\tv_min_u32_e64 v0, v0, v1\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr0_sgpr1\n\tscratch_store_b64 off, v[0:1], s32 offset:56 ; 8-byte Folded Spill\n\ts_branch .LBB11_23\n.LBB11_9:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 3\n\tv_readlane_b32 s1, v4, 4\n\tv_readlane_b32 s2, v4, 2\n\ts_load_b32 s3, s[0:1], 0x0\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_u32 s2, s3\n\ts_mov_b32 s3, 18\n\ts_mov_b32 s2, 12\n\ts_cselect_b32 s2, s2, s3\n\tv_mov_b32_e32 v0, s2\n\tglobal_load_u16 v0, v0, s[0:1]\n\ts_mov_b32 s0, 0xffff\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n ; implicit-def: $sgpr0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr2_sgpr3\n\tscratch_store_b64 off, v[0:1], s32 offset:48 ; 8-byte Folded Spill\n\tv_writelane_b32 v4, s0, 12\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB11_7\n.LBB11_10:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 8\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:16 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:64 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v4, s0, 13\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB11_22\n; %bb.11:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n ; implicit-def: $sgpr2_sgpr3\n\ts_mov_b32 s4, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s4\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:72 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v4, s0, 14\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB11_14\n.LBB11_12:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 14\n\tscratch_load_b64 v[0:1], off, s32 offset:72 ; 8-byte Folded Reload\n\tv_cndmask_b32_e64 v2, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v2, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n ; kill: def $vgpr0_vgpr1 killed $vgpr0_vgpr1 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:80 ; 8-byte Folded Spill\n\ts_cbranch_vccnz .LBB11_21\n; %bb.13:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v4, 1\n\tv_readlane_b32 s2, v4, 5\n\tv_readlane_b32 s3, v4, 6\n\tv_mov_b32_e32 v0, 0\n\tglobal_load_u16 v1, v0, s[2:3] offset:6\n\ts_load_b32 s0, s[2:3], 0x10\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v0, s1, v1\n\ts_waitcnt lgkmcnt(0)\n\tv_sub_nc_u32_e64 v0, s0, v0\n ; implicit-def: $sgpr0\n\tv_min_u32_e64 v0, v0, v1\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr0_sgpr1\n\tscratch_store_b64 off, v[0:1], s32 offset:80 ; 8-byte Folded Spill\n\ts_branch .LBB11_21\n.LBB11_14:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 3\n\tv_readlane_b32 s1, v4, 4\n\tv_readlane_b32 s2, v4, 1\n\ts_load_b32 s3, s[0:1], 0x4\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_u32 s2, s3\n\ts_mov_b32 s3, 20\n\ts_mov_b32 s2, 14\n\ts_cselect_b32 s2, s2, s3\n\tv_mov_b32_e32 v0, s2\n\tglobal_load_u16 v0, v0, s[0:1]\n\ts_mov_b32 s0, 0xffff\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n ; implicit-def: $sgpr0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr2_sgpr3\n\tscratch_store_b64 off, v[0:1], s32 offset:72 ; 8-byte Folded Spill\n\tv_writelane_b32 v4, s0, 14\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB11_12\n.LBB11_15:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n ; implicit-def: $sgpr2_sgpr3\n\ts_mov_b32 s4, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s4\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:88 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v4, s0, 15\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB11_18\n.LBB11_16:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 15\n\tscratch_load_b64 v[0:1], off, s32 offset:88 ; 8-byte Folded Reload\n\tv_cndmask_b32_e64 v2, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v2, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n ; kill: def $vgpr0_vgpr1 killed $vgpr0_vgpr1 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:96 ; 8-byte Folded Spill\n\ts_cbranch_vccnz .LBB11_19\n; %bb.17:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v4, 0\n\tv_readlane_b32 s2, v4, 5\n\tv_readlane_b32 s3, v4, 6\n\tv_mov_b32_e32 v0, 0\n\tglobal_load_u16 v1, v0, s[2:3] offset:8\n\ts_load_b32 s0, s[2:3], 0x14\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v0, s1, v1\n\ts_waitcnt lgkmcnt(0)\n\tv_sub_nc_u32_e64 v0, s0, v0\n ; implicit-def: $sgpr0\n\tv_min_u32_e64 v0, v0, v1\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr0_sgpr1\n\tscratch_store_b64 off, v[0:1], s32 offset:96 ; 8-byte Folded Spill\n\ts_branch .LBB11_19\n.LBB11_18:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 3\n\tv_readlane_b32 s1, v4, 4\n\tv_readlane_b32 s2, v4, 0\n\ts_load_b32 s3, s[0:1], 0x8\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_u32 s2, s3\n\ts_mov_b32 s3, 22\n\ts_mov_b32 s2, 16\n\ts_cselect_b32 s2, s2, s3\n\tv_mov_b32_e32 v0, s2\n\tglobal_load_u16 v0, v0, s[0:1]\n\ts_mov_b32 s0, 0xffff\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n ; implicit-def: $sgpr0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr2_sgpr3\n\tscratch_store_b64 off, v[0:1], s32 offset:88 ; 8-byte Folded Spill\n\tv_writelane_b32 v4, s0, 15\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB11_16\n.LBB11_19:\n\tscratch_load_b64 v[0:1], off, s32 offset:96 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:24 ; 8-byte Folded Spill\n.LBB11_20:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 9\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:24 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:16 ; 8-byte Folded Spill\n\ts_branch .LBB11_10\n.LBB11_21:\n\tscratch_load_b64 v[0:1], off, s32 offset:80 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:64 ; 8-byte Folded Spill\n.LBB11_22:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 13\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:64 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:8 ; 8-byte Folded Spill\n\ts_branch .LBB11_4\n.LBB11_23:\n\tscratch_load_b64 v[0:1], off, s32 offset:56 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:40 ; 8-byte Folded Spill\n.LBB11_24:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 11\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:40 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:32 ; 8-byte Folded Spill\n.LBB11_25:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 10\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[2:3], off, s32 offset:32 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 32\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[0:1], s0, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v2\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v4, off, s32 offset:104 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end11:\n\t.size\t__ockl_get_local_size, .Lfunc_end11-__ockl_get_local_size\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 2384\n; NumSgprs: 35\n; NumVgprs: 5\n; ScratchSize: 112\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_get_local_id\n\t.type\t__ockl_get_local_id,@function\n__ockl_get_local_id: ; @__ockl_get_local_id\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v2, s32 offset:36 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v31, s32 offset:8 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill\n; %bb.1:\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n ; implicit-def: $vgpr2 : SGPR spill to VGPR lane\n\tv_writelane_b32 v2, s1, 0\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_4\n; %bb.2:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v2, s1, 1\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_7\n; %bb.3:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 2\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_10\n\ts_branch .LBB12_9\n.LBB12_4:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 0\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:12 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 3\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB12_13\n; %bb.5:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 4\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_12\n; %bb.6:\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0x3ff\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_branch .LBB12_12\n.LBB12_7:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 1\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:16 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:32 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 5\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB12_11\n; %bb.8:\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_bfe_u32 v0, v0, 10, 10\n\tscratch_store_b32 off, v0, s32 offset:32 ; 4-byte Folded Spill\n\ts_branch .LBB12_11\n.LBB12_9:\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_bfe_u32 v0, v0, 20, 10\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n.LBB12_10:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 2\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:20 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_branch .LBB12_7\n.LBB12_11:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 5\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:32 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_branch .LBB12_4\n.LBB12_12:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n.LBB12_13:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 3\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:24 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v1, 0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v2, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end12:\n\t.size\t__ockl_get_local_id, .Lfunc_end12-__ockl_get_local_id\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 912\n; NumSgprs: 33\n; NumVgprs: 32\n; ScratchSize: 44\n; MemoryBound: 0\n\t.text\n\t.protected\t_Z6DivGPUPdS_S_S_iidd ; -- Begin function _Z6DivGPUPdS_S_S_iidd\n\t.globl\t_Z6DivGPUPdS_S_S_iidd\n\t.p2align\t8\n\t.type\t_Z6DivGPUPdS_S_S_iidd,@function\n_Z6DivGPUPdS_S_S_iidd: ; @_Z6DivGPUPdS_S_S_iidd\n; %bb.0:\n\ts_mov_b32 s32, 0x120\n ; implicit-def: $vgpr10 : SGPR spill to VGPR lane\n\tv_writelane_b32 v10, s15, 0\n\ts_mov_b32 s6, s14\n\tv_readlane_b32 s14, v10, 0\n\tv_writelane_b32 v10, s6, 1\n\ts_mov_b32 s12, s13\n\tv_readlane_b32 s13, v10, 1\n\tv_writelane_b32 v10, s12, 2\n\ts_mov_b64 s[10:11], s[4:5]\n\tv_writelane_b32 v10, s10, 3\n\tv_writelane_b32 v10, s11, 4\n\tv_writelane_b32 v10, s2, 5\n\tv_writelane_b32 v10, s3, 6\n\ts_mov_b64 s[4:5], s[0:1]\n\tv_readlane_b32 s0, v10, 5\n\tv_readlane_b32 s1, v10, 6\n\tv_writelane_b32 v10, s4, 7\n\tv_writelane_b32 v10, s5, 8\n\tv_mov_b32_e32 v31, v0\n\tscratch_store_b32 off, v31, off offset:280 ; 4-byte Folded Spill\n\ts_load_b64 s[48:49], s[0:1], 0x0\n\ts_load_b64 s[44:45], s[0:1], 0x8\n\ts_load_b64 s[40:41], s[0:1], 0x10\n\ts_load_b64 s[36:37], s[0:1], 0x18\n\ts_load_b32 s20, s[0:1], 0x20\n\ts_load_b32 s15, s[0:1], 0x24\n\ts_load_b64 s[8:9], s[0:1], 0x28\n\ts_load_b64 s[2:3], s[0:1], 0x30\n\ts_mov_b64 s[6:7], src_private_base\n\ts_mov_b32 s16, 32\n\ts_lshr_b64 s[6:7], s[6:7], s16\n\ts_mov_b32 s21, s6\n\tv_writelane_b32 v10, s21, 9\n\ts_mov_b32 s46, 32\n ; kill: def $sgpr46 killed $sgpr46 def $sgpr46_sgpr47\n\ts_mov_b32 s47, s21\n\ts_mov_b32 s42, 40\n ; kill: def $sgpr42 killed $sgpr42 def $sgpr42_sgpr43\n\ts_mov_b32 s43, s21\n\ts_mov_b32 s38, 48\n ; kill: def $sgpr38 killed $sgpr38 def $sgpr38_sgpr39\n\ts_mov_b32 s39, s21\n\ts_mov_b32 s34, 56\n ; kill: def $sgpr34 killed $sgpr34 def $sgpr34_sgpr35\n\ts_mov_b32 s35, s21\n\ts_mov_b32 s30, 64\n ; kill: def $sgpr30 killed $sgpr30 def $sgpr30_sgpr31\n\ts_mov_b32 s31, s21\n\ts_mov_b64 s[6:7], s[30:31]\n\tv_writelane_b32 v10, s6, 10\n\tv_writelane_b32 v10, s7, 11\n\ts_mov_b32 s28, 0x48\n ; kill: def $sgpr28 killed $sgpr28 def $sgpr28_sgpr29\n\ts_mov_b32 s29, s21\n\ts_mov_b64 s[6:7], s[28:29]\n\tv_writelane_b32 v10, s6, 12\n\tv_writelane_b32 v10, s7, 13\n\ts_mov_b32 s26, 0x50\n ; kill: def $sgpr26 killed $sgpr26 def $sgpr26_sgpr27\n\ts_mov_b32 s27, s21\n\ts_mov_b64 s[6:7], s[26:27]\n\tv_writelane_b32 v10, s6, 14\n\tv_writelane_b32 v10, s7, 15\n\ts_mov_b32 s24, 0x58\n ; kill: def $sgpr24 killed $sgpr24 def $sgpr24_sgpr25\n\ts_mov_b32 s25, s21\n\ts_mov_b64 s[6:7], s[24:25]\n\tv_writelane_b32 v10, s6, 16\n\tv_writelane_b32 v10, s7, 17\n\ts_mov_b32 s22, 0x60\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s21\n\ts_mov_b64 s[6:7], s[22:23]\n\tv_writelane_b32 v10, s6, 18\n\tv_writelane_b32 v10, s7, 19\n\ts_mov_b32 s18, 0x64\n ; kill: def $sgpr18 killed $sgpr18 def $sgpr18_sgpr19\n\ts_mov_b32 s19, s21\n\tv_writelane_b32 v10, s18, 20\n\tv_writelane_b32 v10, s19, 21\n\ts_mov_b64 s[6:7], s[18:19]\n\tv_writelane_b32 v10, s6, 22\n\tv_writelane_b32 v10, s7, 23\n\ts_mov_b32 s16, 0x68\n ; kill: def $sgpr16 killed $sgpr16 def $sgpr16_sgpr17\n\ts_mov_b32 s17, s21\n\ts_mov_b64 s[6:7], s[16:17]\n\tv_writelane_b32 v10, s6, 24\n\tv_writelane_b32 v10, s7, 25\n\ts_mov_b32 s6, 0x70\n ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7\n\ts_mov_b32 s7, s21\n\ts_mov_b64 s[50:51], s[6:7]\n\tv_writelane_b32 v10, s50, 26\n\tv_writelane_b32 v10, s51, 27\n\ts_mov_b32 s50, 0x78\n ; kill: def $sgpr50 killed $sgpr50 def $sgpr50_sgpr51\n\ts_mov_b32 s51, s21\n\tv_writelane_b32 v10, s50, 28\n\tv_writelane_b32 v10, s51, 29\n\tv_writelane_b32 v10, s50, 30\n\tv_writelane_b32 v10, s51, 31\n\ts_or_saveexec_b32 s52, -1\n\tscratch_store_b32 off, v10, off offset:264 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s52\n\ts_mov_b32 s50, 0x7c\n ; kill: def $sgpr50 killed $sgpr50 def $sgpr50_sgpr51\n\ts_mov_b32 s51, s21\n ; implicit-def: $vgpr11 : SGPR spill to VGPR lane\n\tv_writelane_b32 v11, s50, 0\n\tv_writelane_b32 v11, s51, 1\n\tv_writelane_b32 v11, s50, 2\n\tv_writelane_b32 v11, s51, 3\n\ts_mov_b32 s50, 0x80\n ; kill: def $sgpr50 killed $sgpr50 def $sgpr50_sgpr51\n\ts_mov_b32 s51, s21\n\tv_writelane_b32 v11, s50, 4\n\tv_writelane_b32 v11, s51, 5\n\tv_writelane_b32 v11, s50, 6\n\tv_writelane_b32 v11, s51, 7\n\ts_mov_b32 s50, 0x88\n ; kill: def $sgpr50 killed $sgpr50 def $sgpr50_sgpr51\n\ts_mov_b32 s51, s21\n\tv_writelane_b32 v11, s50, 8\n\tv_writelane_b32 v11, s51, 9\n\ts_mov_b32 s50, 0x90\n ; kill: def $sgpr50 killed $sgpr50 def $sgpr50_sgpr51\n\ts_mov_b32 s51, s21\n\tv_writelane_b32 v11, s50, 10\n\tv_writelane_b32 v11, s51, 11\n\ts_mov_b32 s50, 0x98\n ; kill: def $sgpr50 killed $sgpr50 def $sgpr50_sgpr51\n\ts_mov_b32 s51, s21\n\tv_writelane_b32 v11, s50, 12\n\tv_writelane_b32 v11, s51, 13\n\ts_mov_b32 s50, 0xa0\n ; kill: def $sgpr50 killed $sgpr50 def $sgpr50_sgpr51\n\ts_mov_b32 s51, s21\n\tv_writelane_b32 v11, s50, 14\n\tv_writelane_b32 v11, s51, 15\n\ts_mov_b32 s50, 0xa8\n ; kill: def $sgpr50 killed $sgpr50 def $sgpr50_sgpr51\n\ts_mov_b32 s51, s21\n\tv_writelane_b32 v11, s50, 16\n\tv_writelane_b32 v11, s51, 17\n\ts_mov_b32 s50, 0xb0\n ; kill: def $sgpr50 killed $sgpr50 def $sgpr50_sgpr51\n\ts_mov_b32 s51, s21\n\tv_writelane_b32 v11, s50, 18\n\tv_writelane_b32 v11, s51, 19\n\ts_mov_b32 s50, 0xb8\n ; kill: def $sgpr50 killed $sgpr50 def $sgpr50_sgpr51\n\ts_mov_b32 s51, s21\n\tv_writelane_b32 v11, s50, 20\n\tv_writelane_b32 v11, s51, 21\n\ts_mov_b32 s50, 0xc0\n ; kill: def $sgpr50 killed $sgpr50 def $sgpr50_sgpr51\n\ts_mov_b32 s51, s21\n\tv_writelane_b32 v11, s50, 22\n\tv_writelane_b32 v11, s51, 23\n\ts_mov_b32 s50, 0xc8\n ; kill: def $sgpr50 killed $sgpr50 def $sgpr50_sgpr51\n\ts_mov_b32 s51, s21\n\tv_writelane_b32 v11, s50, 24\n\tv_writelane_b32 v11, s51, 25\n\ts_mov_b32 s50, 0xd0\n ; kill: def $sgpr50 killed $sgpr50 def $sgpr50_sgpr51\n\ts_mov_b32 s51, s21\n\tv_writelane_b32 v11, s50, 26\n\tv_writelane_b32 v11, s51, 27\n\ts_mov_b32 s50, 0xd8\n ; kill: def $sgpr50 killed $sgpr50 def $sgpr50_sgpr51\n\ts_mov_b32 s51, s21\n\tv_writelane_b32 v11, s50, 28\n\tv_writelane_b32 v11, s51, 29\n\ts_mov_b32 s50, 0xe0\n ; kill: def $sgpr50 killed $sgpr50 def $sgpr50_sgpr51\n\ts_mov_b32 s51, s21\n\tv_writelane_b32 v11, s50, 30\n\tv_writelane_b32 v11, s51, 31\n\ts_or_saveexec_b32 s52, -1\n\tscratch_store_b32 off, v11, off offset:260 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s52\n\ts_mov_b32 s50, 0xe8\n ; kill: def $sgpr50 killed $sgpr50 def $sgpr50_sgpr51\n\ts_mov_b32 s51, s21\n ; implicit-def: $vgpr12 : SGPR spill to VGPR lane\n\tv_writelane_b32 v12, s50, 0\n\tv_writelane_b32 v12, s51, 1\n\ts_mov_b32 s50, 0xf0\n ; kill: def $sgpr50 killed $sgpr50 def $sgpr50_sgpr51\n\ts_mov_b32 s51, s21\n\tv_writelane_b32 v12, s50, 2\n\tv_writelane_b32 v12, s51, 3\n\ts_mov_b32 s50, 0xf8\n ; kill: def $sgpr50 killed $sgpr50 def $sgpr50_sgpr51\n\ts_mov_b32 s51, s21\n\tv_writelane_b32 v12, s50, 4\n\tv_writelane_b32 v12, s51, 5\n\tv_mov_b32_e32 v0, s46\n\tv_mov_b32_e32 v1, s47\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v2, s48\n\tv_mov_b32_e32 v3, s49\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s46\n\tv_mov_b32_e32 v1, s47\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s42\n\tv_mov_b32_e32 v1, s43\n\tv_mov_b32_e32 v2, s44\n\tv_mov_b32_e32 v3, s45\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s42\n\tv_mov_b32_e32 v1, s43\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s38\n\tv_mov_b32_e32 v1, s39\n\tv_mov_b32_e32 v2, s40\n\tv_mov_b32_e32 v3, s41\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s38\n\tv_mov_b32_e32 v1, s39\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s34\n\tv_mov_b32_e32 v1, s35\n\tv_mov_b32_e32 v2, s36\n\tv_mov_b32_e32 v3, s37\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s34\n\tv_mov_b32_e32 v1, s35\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s30\n\tv_mov_b32_e32 v1, s31\n\ts_waitcnt vmcnt(3) lgkmcnt(6)\n\tflat_store_b64 v[0:1], v[8:9]\n\tv_mov_b32_e32 v0, s28\n\tv_mov_b32_e32 v1, s29\n\ts_waitcnt vmcnt(2) lgkmcnt(5)\n\tflat_store_b64 v[0:1], v[6:7]\n\tv_mov_b32_e32 v0, s26\n\tv_mov_b32_e32 v1, s27\n\ts_waitcnt vmcnt(1) lgkmcnt(4)\n\tflat_store_b64 v[0:1], v[4:5]\n\tv_mov_b32_e32 v0, s24\n\tv_mov_b32_e32 v1, s25\n\ts_waitcnt vmcnt(0) lgkmcnt(3)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s22\n\tv_mov_b32_e32 v1, s23\n\tv_mov_b32_e32 v2, s20\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tv_mov_b32_e32 v2, s15\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tv_mov_b32_e32 v2, s8\n\tv_mov_b32_e32 v3, s9\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b64 s[6:7], 56\n\ts_mov_b32 s2, s0\n\ts_mov_b32 s0, s1\n\ts_mov_b32 s3, s6\n\ts_mov_b32 s1, s7\n\ts_add_u32 s8, s2, s3\n\ts_addc_u32 s0, s0, s1\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s0\n\tv_writelane_b32 v12, s8, 6\n\tv_writelane_b32 v12, s9, 7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_group_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_group_id@rel32@hi+12\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, off offset:268 ; 4-byte Folded Spill\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:280 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v10, 0\n\tv_readlane_b32 s13, v10, 1\n\tv_readlane_b32 s12, v10, 2\n\tv_readlane_b32 s10, v10, 3\n\tv_readlane_b32 s11, v10, 4\n\tv_readlane_b32 s8, v12, 6\n\tv_readlane_b32 s9, v12, 7\n\tv_readlane_b32 s4, v10, 7\n\tv_readlane_b32 s5, v10, 8\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:268 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:284 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:284 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v1, off offset:272 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_size@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_size@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:280 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v10, 0\n\tv_readlane_b32 s13, v10, 1\n\tv_readlane_b32 s12, v10, 2\n\tv_readlane_b32 s10, v10, 3\n\tv_readlane_b32 s11, v10, 4\n\tv_readlane_b32 s4, v10, 7\n\tv_readlane_b32 s5, v10, 8\n\tv_readlane_b32 s8, v12, 6\n\tv_readlane_b32 s9, v12, 7\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:268 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:276 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:276 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v1\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_id@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s8, v10, 28\n\tv_readlane_b32 s9, v10, 29\n\tv_readlane_b32 s6, v10, 20\n\tv_readlane_b32 s7, v10, 21\n\tv_readlane_b32 s2, v11, 4\n\tv_readlane_b32 s3, v11, 5\n\tv_readlane_b32 s0, v11, 0\n\tv_readlane_b32 s1, v11, 1\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:272 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v5, v1\n\tscratch_load_b32 v1, off, off offset:268 ; 4-byte Folded Reload\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v5\n\tv_mov_b32_e32 v5, v2\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr5\n ; implicit-def: $sgpr5\n\tv_mov_b32_e32 v2, s4\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v2\n\ts_waitcnt vmcnt(1)\n\tv_mad_u64_u32 v[2:3], s4, v0, v4, v[5:6]\n\tv_mov_b32_e32 v0, v2\n\tv_mov_b32_e32 v2, s8\n\tv_mov_b32_e32 v3, s9\n\tflat_store_b32 v[2:3], v0\n\tv_mov_b32_e32 v2, s8\n\tv_mov_b32_e32 v3, s9\n\tflat_load_b32 v0, v[2:3]\n\tv_mov_b32_e32 v2, s6\n\tv_mov_b32_e32 v3, s7\n\tflat_load_b32 v2, v[2:3]\n\ts_mov_b32 s4, 31\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v3, s4, v2\n\tv_add_nc_u32_e64 v2, v2, v3\n\tv_xor_b32_e64 v3, v2, v3\n\tv_sub_nc_u32_e64 v4, v1, v3\n\tv_cvt_f32_u32_e32 v2, v3\n\tv_rcp_iflag_f32_e32 v2, v2\n\ts_waitcnt_depctr 0xfff\n\tv_mul_f32_e32 v2, 0x4f7ffffe, v2\n\tv_cvt_u32_f32_e32 v2, v2\n\tv_mul_lo_u32 v4, v4, v2\n\tv_mul_hi_u32 v4, v2, v4\n\tv_add_nc_u32_e64 v4, v2, v4\n\tv_ashrrev_i32_e64 v2, s4, v0\n\tv_add_nc_u32_e64 v0, v0, v2\n\tv_xor_b32_e64 v0, v0, v2\n\tv_mul_hi_u32 v4, v0, v4\n\tv_mul_lo_u32 v4, v4, v3\n\tv_sub_nc_u32_e64 v0, v0, v4\n\tv_cmp_ge_u32_e64 s5, v0, v3\n\tv_sub_nc_u32_e64 v4, v0, v3\n\tv_cndmask_b32_e64 v0, v0, v4, s5\n\tv_cmp_ge_u32_e64 s5, v0, v3\n\tv_sub_nc_u32_e64 v3, v0, v3\n\tv_cndmask_b32_e64 v0, v0, v3, s5\n\tv_xor_b32_e64 v0, v0, v2\n\tv_sub_nc_u32_e64 v0, v0, v2\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b32 v[2:3], v0\n\tv_mov_b32_e32 v2, s8\n\tv_mov_b32_e32 v3, s9\n\tflat_load_b32 v4, v[2:3]\n\tv_mov_b32_e32 v2, s6\n\tv_mov_b32_e32 v3, s7\n\tflat_load_b32 v0, v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v3, s4, v0\n\tv_add_nc_u32_e64 v0, v0, v3\n\tv_xor_b32_e64 v5, v0, v3\n\tv_sub_nc_u32_e64 v2, v1, v5\n\tv_cvt_f32_u32_e32 v0, v5\n\tv_rcp_iflag_f32_e32 v0, v0\n\ts_waitcnt_depctr 0xfff\n\tv_mul_f32_e32 v0, 0x4f7ffffe, v0\n\tv_cvt_u32_f32_e32 v0, v0\n\tv_mul_lo_u32 v2, v2, v0\n\tv_mul_hi_u32 v2, v0, v2\n\tv_add_nc_u32_e64 v0, v0, v2\n\tv_ashrrev_i32_e64 v2, s4, v4\n\tv_add_nc_u32_e64 v4, v4, v2\n\tv_xor_b32_e64 v4, v4, v2\n\tv_mul_hi_u32 v0, v4, v0\n\tv_mul_lo_u32 v6, v0, v5\n\tv_sub_nc_u32_e64 v4, v4, v6\n\tv_cmp_ge_u32_e64 s6, v4, v5\n\tv_sub_nc_u32_e64 v6, v4, v5\n\tv_cndmask_b32_e64 v4, v4, v6, s6\n\tv_cmp_ge_u32_e64 s4, v4, v5\n\ts_mov_b32 s5, 1\n\tv_add_nc_u32_e64 v4, v0, s5\n\tv_cndmask_b32_e64 v0, v0, v4, s6\n\tv_add_nc_u32_e64 v4, v0, s5\n\tv_cndmask_b32_e64 v0, v0, v4, s4\n\tv_xor_b32_e64 v2, v2, v3\n\tv_xor_b32_e64 v0, v0, v2\n\tv_sub_nc_u32_e64 v0, v0, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b32 v[2:3], v0\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_load_b32 v0, v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_gt_i32_e64 s1, v0, v1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v12, s0, 8\n\ts_or_saveexec_b32 s52, -1\n\tscratch_store_b32 off, v12, off offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s52\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB13_8\n; %bb.1:\n\ts_or_saveexec_b32 s52, -1\n\tscratch_load_b32 v10, off, off offset:264 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s52\n\ts_or_saveexec_b32 s52, -1\n\tscratch_load_b32 v11, off, off offset:260 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s52\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v10, 22\n\tv_readlane_b32 s1, v10, 23\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v11, 2\n\tv_readlane_b32 s3, v11, 3\n\ts_or_saveexec_b32 s52, -1\n\tscratch_load_b32 v12, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s52\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v2, s1\n\tv_mov_b32_e32 v1, s0\n\tflat_load_b32 v1, v[1:2]\n\ts_mov_b32 s0, -1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v1, v1, s0\n\tv_cmp_lt_i32_e64 s1, v0, v1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v12, s0, 9\n\ts_or_saveexec_b32 s52, -1\n\tscratch_store_b32 off, v12, off offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s52\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB13_7\n; %bb.2:\n\ts_or_saveexec_b32 s52, -1\n\tscratch_load_b32 v11, off, off offset:260 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s52\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v11, 6\n\tv_readlane_b32 s1, v11, 7\n\ts_or_saveexec_b32 s52, -1\n\tscratch_load_b32 v12, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s52\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v0, v[0:1]\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_gt_i32_e64 s1, v0, s0\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v12, s0, 10\n\ts_or_saveexec_b32 s52, -1\n\tscratch_store_b32 off, v12, off offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s52\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB13_6\n; %bb.3:\n\ts_or_saveexec_b32 s52, -1\n\tscratch_load_b32 v10, off, off offset:264 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s52\n\ts_or_saveexec_b32 s52, -1\n\tscratch_load_b32 v11, off, off offset:260 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s52\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v10, 18\n\tv_readlane_b32 s1, v10, 19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v11, 6\n\tv_readlane_b32 s3, v11, 7\n\ts_or_saveexec_b32 s52, -1\n\tscratch_load_b32 v12, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s52\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v2, s1\n\tv_mov_b32_e32 v1, s0\n\tflat_load_b32 v1, v[1:2]\n\ts_mov_b32 s0, -1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v1, v1, s0\n\tv_cmp_lt_i32_e64 s1, v0, v1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v12, s0, 11\n\ts_or_saveexec_b32 s52, -1\n\tscratch_store_b32 off, v12, off offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s52\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB13_5\n; %bb.4:\n\ts_or_saveexec_b32 s52, -1\n\tscratch_load_b32 v10, off, off offset:260 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s52\n\ts_or_saveexec_b32 s52, -1\n\tscratch_load_b32 v11, off, off offset:264 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s52\n\ts_or_saveexec_b32 s52, -1\n\tscratch_load_b32 v12, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s52\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s2, v11, 30\n\tv_readlane_b32 s3, v11, 31\n\tv_readlane_b32 s4, v11, 10\n\tv_readlane_b32 s5, v11, 11\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s6, v12, 0\n\tv_readlane_b32 s7, v12, 1\n\tv_readlane_b32 s8, v10, 30\n\tv_readlane_b32 s9, v10, 31\n\tv_readlane_b32 s10, v11, 26\n\tv_readlane_b32 s11, v11, 27\n\tv_readlane_b32 s12, v12, 4\n\tv_readlane_b32 s13, v12, 5\n\tv_readlane_b32 s14, v12, 2\n\tv_readlane_b32 s15, v12, 3\n\tv_readlane_b32 s16, v11, 24\n\tv_readlane_b32 s17, v11, 25\n\tv_readlane_b32 s20, v10, 8\n\tv_readlane_b32 s21, v10, 9\n\tv_readlane_b32 s22, v10, 24\n\tv_readlane_b32 s23, v10, 25\n\tv_readlane_b32 s24, v10, 16\n\tv_readlane_b32 s25, v10, 17\n\tv_readlane_b32 s26, v10, 28\n\tv_readlane_b32 s27, v10, 29\n\tv_readlane_b32 s28, v10, 14\n\tv_readlane_b32 s29, v10, 15\n\tv_readlane_b32 s30, v10, 26\n\tv_readlane_b32 s31, v10, 27\n\tv_readlane_b32 s34, v10, 18\n\tv_readlane_b32 s35, v10, 19\n\tv_readlane_b32 s36, v10, 12\n\tv_readlane_b32 s37, v10, 13\n\tv_readlane_b32 s38, v10, 22\n\tv_readlane_b32 s39, v10, 23\n\tv_readlane_b32 s18, v10, 10\n\tv_readlane_b32 s19, v10, 11\n\tv_readlane_b32 s40, v10, 20\n\tv_readlane_b32 s41, v10, 21\n\tv_readlane_b32 s42, v11, 22\n\tv_readlane_b32 s43, v11, 23\n\tv_readlane_b32 s44, v11, 16\n\tv_readlane_b32 s45, v11, 17\n\tv_readlane_b32 s46, v11, 14\n\tv_readlane_b32 s47, v11, 15\n\tv_readlane_b32 s48, v11, 12\n\tv_readlane_b32 s49, v11, 13\n\tv_mov_b32_e32 v0, s48\n\tv_mov_b32_e32 v1, s49\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\ts_mov_b32 s0, 3\n\tv_writelane_b32 v12, s0, 12\n\ts_or_saveexec_b32 s52, -1\n\tscratch_store_b32 off, v12, off offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s52\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s20\n\tv_mov_b32_e32 v1, s21\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s48\n\tv_mov_b32_e32 v1, s49\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v2, 31, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_lshlrev_b64 v[1:2], s0, v[0:1]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1] offset:8\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s48\n\tv_mov_b32_e32 v1, s49\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v0, v[3:4]\n\ts_mov_b32 s1, -1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v3, v0, s1\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s33, v0, v3\n\tv_add_co_ci_u32_e64 v2, s33, v1, v2, s33\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s36\n\tv_mov_b32_e32 v1, s37\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s48\n\tv_mov_b32_e32 v1, s49\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v0, v[3:4]\n\tv_mov_b32_e32 v3, s42\n\tv_mov_b32_e32 v4, s43\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v3, v0, v3\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s33, v0, v3\n\tv_add_co_ci_u32_e64 v2, s33, v1, v2, s33\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s28\n\tv_mov_b32_e32 v1, s29\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s48\n\tv_mov_b32_e32 v1, s49\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v0, v[3:4]\n\tv_mov_b32_e32 v3, s42\n\tv_mov_b32_e32 v4, s43\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v3, v0, v3\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s33, v0, v3\n\tv_add_co_ci_u32_e64 v2, s33, v1, v2, s33\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s24\n\tv_mov_b32_e32 v1, s25\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s46\n\tv_mov_b32_e32 v1, s47\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s33, v0, v3\n\tv_add_co_ci_u32_e64 v2, s33, v1, v2, s33\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s34\n\tv_mov_b32_e32 v1, s35\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s46\n\tv_mov_b32_e32 v1, s47\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v2, 31, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_lshlrev_b64 v[1:2], s0, v[0:1]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s33, v0, v3\n\tv_add_co_ci_u32_e64 v2, s33, v1, v2, s33\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1] offset:8\n\tv_mov_b32_e32 v0, s40\n\tv_mov_b32_e32 v1, s41\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s46\n\tv_mov_b32_e32 v1, s47\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v0, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v3, v0, s1\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s38\n\tv_mov_b32_e32 v1, s39\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s44\n\tv_mov_b32_e32 v1, s45\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s22\n\tv_mov_b32_e32 v1, s23\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s44\n\tv_mov_b32_e32 v1, s45\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v0, v[3:4]\n\tv_mov_b32_e32 v3, s42\n\tv_mov_b32_e32 v4, s43\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v3, v0, v3\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s30\n\tv_mov_b32_e32 v1, s31\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s44\n\tv_mov_b32_e32 v1, s45\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v0, v[3:4]\n\tv_mov_b32_e32 v3, s42\n\tv_mov_b32_e32 v4, s43\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v3, v0, v3\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s26\n\tv_mov_b32_e32 v1, s27\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s40\n\tv_mov_b32_e32 v1, s41\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s18\n\tv_mov_b32_e32 v3, s19\n\tflat_load_b64 v[2:3], v[2:3]\n\tv_mov_b32_e32 v4, s34\n\tv_mov_b32_e32 v5, s35\n\tflat_load_b64 v[4:5], v[4:5]\n\tv_mov_b32_e32 v6, s20\n\tv_mov_b32_e32 v7, s21\n\tflat_load_b64 v[6:7], v[6:7]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mul_f64 v[4:5], v[4:5], v[6:7]\n\tv_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]\n\ts_mov_b64 s[18:19], 0.5\n\tv_mul_f64 v[2:3], v[0:1], s[18:19]\n\tv_mov_b32_e32 v0, s8\n\tv_mov_b32_e32 v1, s9\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s38\n\tv_mov_b32_e32 v1, s39\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s36\n\tv_mov_b32_e32 v3, s37\n\tflat_load_b64 v[2:3], v[2:3]\n\tv_mov_b32_e32 v4, s34\n\tv_mov_b32_e32 v5, s35\n\tflat_load_b64 v[4:5], v[4:5]\n\tv_mov_b32_e32 v6, s20\n\tv_mov_b32_e32 v7, s21\n\tflat_load_b64 v[6:7], v[6:7]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mul_f64 v[4:5], v[4:5], v[6:7]\n\tv_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]\n\tv_mul_f64 v[2:3], v[0:1], s[18:19]\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s30\n\tv_mov_b32_e32 v1, s31\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s28\n\tv_mov_b32_e32 v3, s29\n\tflat_load_b64 v[2:3], v[2:3]\n\tv_mov_b32_e32 v4, s22\n\tv_mov_b32_e32 v5, s23\n\tflat_load_b64 v[4:5], v[4:5]\n\tv_mov_b32_e32 v6, s20\n\tv_mov_b32_e32 v7, s21\n\tflat_load_b64 v[6:7], v[6:7]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mul_f64 v[4:5], v[4:5], v[6:7]\n\tv_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]\n\tv_mul_f64 v[2:3], v[0:1], s[18:19]\n\tv_mov_b32_e32 v0, s14\n\tv_mov_b32_e32 v1, s15\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s26\n\tv_mov_b32_e32 v1, s27\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s24\n\tv_mov_b32_e32 v3, s25\n\tflat_load_b64 v[2:3], v[2:3]\n\tv_mov_b32_e32 v4, s22\n\tv_mov_b32_e32 v5, s23\n\tflat_load_b64 v[4:5], v[4:5]\n\tv_mov_b32_e32 v6, s20\n\tv_mov_b32_e32 v7, s21\n\tflat_load_b64 v[6:7], v[6:7]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mul_f64 v[4:5], v[4:5], v[6:7]\n\tv_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]\n\tv_mul_f64 v[2:3], v[0:1], s[18:19]\n\tv_mov_b32_e32 v0, s12\n\tv_mov_b32_e32 v1, s13\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s14\n\tv_mov_b32_e32 v3, s15\n\tflat_load_b64 v[2:3], v[2:3]\n\tv_mov_b32_e32 v4, s12\n\tv_mov_b32_e32 v5, s13\n\tflat_load_b64 v[4:5], v[4:5]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[2:3], v[2:3], -v[4:5]\n\tv_mov_b32_e32 v4, s10\n\tv_mov_b32_e32 v5, s11\n\tflat_load_b64 v[4:5], v[4:5]\n\tv_mov_b32_e32 v6, s8\n\tv_mov_b32_e32 v7, s9\n\tflat_load_b64 v[6:7], v[6:7]\n\tv_mov_b32_e32 v9, s7\n\tv_mov_b32_e32 v8, s6\n\tflat_load_b64 v[8:9], v[8:9]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[6:7], v[6:7], -v[8:9]\n\tv_mul_f64 v[4:5], v[4:5], v[6:7]\n\tv_fma_f64 v[2:3], v[0:1], v[2:3], v[4:5]\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v4, 31, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_lshlrev_b64 v[6:7], s0, v[0:1]\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v1, v9\n\tv_mov_b32_e32 v4, v7\n\tv_add_co_u32 v0, s0, v0, v5\n\tv_add_co_ci_u32_e64 v4, s0, v1, v4, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_store_b64 v[0:1], v[2:3]\n.LBB13_5:\n\ts_or_saveexec_b32 s52, -1\n\tscratch_load_b32 v12, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s52\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v12, 11\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB13_6:\n\ts_or_saveexec_b32 s52, -1\n\tscratch_load_b32 v12, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s52\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v12, 10\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB13_7:\n\ts_or_saveexec_b32 s52, -1\n\tscratch_load_b32 v12, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s52\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v12, 9\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB13_8:\n\ts_or_saveexec_b32 s52, -1\n\tscratch_load_b32 v12, off, off offset:256 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s52\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v12, 8\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z6DivGPUPdS_S_S_iidd\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 400\n\t\t.amdhsa_kernarg_size 312\n\t\t.amdhsa_user_sgpr_count 13\n\t\t.amdhsa_user_sgpr_dispatch_ptr 1\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 1\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 1\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 1\n\t\t.amdhsa_system_sgpr_workgroup_id_z 1\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 2\n\t\t.amdhsa_next_free_vgpr 32\n\t\t.amdhsa_next_free_sgpr 53\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end13:\n\t.size\t_Z6DivGPUPdS_S_S_iidd, .Lfunc_end13-_Z6DivGPUPdS_S_S_iidd\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 5736\n; NumSgprs: 55\n; NumVgprs: 32\n; ScratchSize: 400\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 6\n; VGPRBlocks: 3\n; NumSGPRsForWavesPerEU: 55\n; NumVGPRsForWavesPerEU: 32\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1\n; COMPUTE_PGM_RSRC2:USER_SGPR: 13\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2\n\t.text\n\t.protected\t_Z13DivergenceGPUPdS_S_iidd ; -- Begin function _Z13DivergenceGPUPdS_S_iidd\n\t.globl\t_Z13DivergenceGPUPdS_S_iidd\n\t.p2align\t8\n\t.type\t_Z13DivergenceGPUPdS_S_iidd,@function\n_Z13DivergenceGPUPdS_S_iidd: ; @_Z13DivergenceGPUPdS_S_iidd\n; %bb.0:\n\ts_mov_b32 s32, 0xf0\n ; implicit-def: $vgpr10 : SGPR spill to VGPR lane\n\tv_writelane_b32 v10, s15, 0\n\ts_mov_b32 s6, s14\n\tv_readlane_b32 s14, v10, 0\n\tv_writelane_b32 v10, s6, 1\n\ts_mov_b32 s12, s13\n\tv_readlane_b32 s13, v10, 1\n\tv_writelane_b32 v10, s12, 2\n\ts_mov_b64 s[10:11], s[4:5]\n\tv_writelane_b32 v10, s10, 3\n\tv_writelane_b32 v10, s11, 4\n\tv_writelane_b32 v10, s2, 5\n\tv_writelane_b32 v10, s3, 6\n\ts_mov_b64 s[4:5], s[0:1]\n\tv_readlane_b32 s0, v10, 5\n\tv_readlane_b32 s1, v10, 6\n\tv_writelane_b32 v10, s4, 7\n\tv_writelane_b32 v10, s5, 8\n\tv_mov_b32_e32 v31, v0\n\tscratch_store_b32 off, v31, off offset:220 ; 4-byte Folded Spill\n\ts_load_b64 s[42:43], s[0:1], 0x0\n\ts_load_b64 s[38:39], s[0:1], 0x8\n\ts_load_b64 s[34:35], s[0:1], 0x10\n\ts_load_b32 s20, s[0:1], 0x18\n\ts_load_b32 s15, s[0:1], 0x1c\n\ts_load_b64 s[8:9], s[0:1], 0x20\n\ts_load_b64 s[2:3], s[0:1], 0x28\n\ts_mov_b64 s[6:7], src_private_base\n\ts_mov_b32 s16, 32\n\ts_lshr_b64 s[6:7], s[6:7], s16\n\ts_mov_b32 s21, s6\n\tv_writelane_b32 v10, s21, 9\n\ts_mov_b32 s40, 32\n ; kill: def $sgpr40 killed $sgpr40 def $sgpr40_sgpr41\n\ts_mov_b32 s41, s21\n\ts_mov_b32 s36, 40\n ; kill: def $sgpr36 killed $sgpr36 def $sgpr36_sgpr37\n\ts_mov_b32 s37, s21\n\ts_mov_b32 s30, 48\n ; kill: def $sgpr30 killed $sgpr30 def $sgpr30_sgpr31\n\ts_mov_b32 s31, s21\n\ts_mov_b32 s28, 56\n ; kill: def $sgpr28 killed $sgpr28 def $sgpr28_sgpr29\n\ts_mov_b32 s29, s21\n\ts_mov_b64 s[6:7], s[28:29]\n\tv_writelane_b32 v10, s6, 10\n\tv_writelane_b32 v10, s7, 11\n\ts_mov_b32 s26, 64\n ; kill: def $sgpr26 killed $sgpr26 def $sgpr26_sgpr27\n\ts_mov_b32 s27, s21\n\ts_mov_b64 s[6:7], s[26:27]\n\tv_writelane_b32 v10, s6, 12\n\tv_writelane_b32 v10, s7, 13\n\ts_mov_b32 s24, 0x48\n ; kill: def $sgpr24 killed $sgpr24 def $sgpr24_sgpr25\n\ts_mov_b32 s25, s21\n\ts_mov_b64 s[6:7], s[24:25]\n\tv_writelane_b32 v10, s6, 14\n\tv_writelane_b32 v10, s7, 15\n\ts_mov_b32 s22, 0x50\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s21\n\ts_mov_b64 s[6:7], s[22:23]\n\tv_writelane_b32 v10, s6, 16\n\tv_writelane_b32 v10, s7, 17\n\ts_mov_b32 s18, 0x54\n ; kill: def $sgpr18 killed $sgpr18 def $sgpr18_sgpr19\n\ts_mov_b32 s19, s21\n\tv_writelane_b32 v10, s18, 18\n\tv_writelane_b32 v10, s19, 19\n\ts_mov_b64 s[6:7], s[18:19]\n\tv_writelane_b32 v10, s6, 20\n\tv_writelane_b32 v10, s7, 21\n\ts_mov_b32 s16, 0x58\n ; kill: def $sgpr16 killed $sgpr16 def $sgpr16_sgpr17\n\ts_mov_b32 s17, s21\n\ts_mov_b64 s[6:7], s[16:17]\n\tv_writelane_b32 v10, s6, 22\n\tv_writelane_b32 v10, s7, 23\n\ts_mov_b32 s6, 0x60\n ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7\n\ts_mov_b32 s7, s21\n\ts_mov_b64 s[44:45], s[6:7]\n\tv_writelane_b32 v10, s44, 24\n\tv_writelane_b32 v10, s45, 25\n\ts_mov_b32 s44, 0x68\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v10, s44, 26\n\tv_writelane_b32 v10, s45, 27\n\tv_writelane_b32 v10, s44, 28\n\tv_writelane_b32 v10, s45, 29\n\ts_mov_b32 s44, 0x6c\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v10, s44, 30\n\tv_writelane_b32 v10, s45, 31\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v10, off offset:204 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n ; implicit-def: $vgpr11 : SGPR spill to VGPR lane\n\tv_writelane_b32 v11, s44, 0\n\tv_writelane_b32 v11, s45, 1\n\ts_mov_b32 s44, 0x70\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v11, s44, 2\n\tv_writelane_b32 v11, s45, 3\n\tv_writelane_b32 v11, s44, 4\n\tv_writelane_b32 v11, s45, 5\n\ts_mov_b32 s44, 0x78\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v11, s44, 6\n\tv_writelane_b32 v11, s45, 7\n\ts_mov_b32 s44, 0x80\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v11, s44, 8\n\tv_writelane_b32 v11, s45, 9\n\ts_mov_b32 s44, 0x88\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v11, s44, 10\n\tv_writelane_b32 v11, s45, 11\n\ts_mov_b32 s44, 0x90\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v11, s44, 12\n\tv_writelane_b32 v11, s45, 13\n\ts_mov_b32 s44, 0x98\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v11, s44, 14\n\tv_writelane_b32 v11, s45, 15\n\ts_mov_b32 s44, 0xa0\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v11, s44, 16\n\tv_writelane_b32 v11, s45, 17\n\ts_mov_b32 s44, 0xa8\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v11, s44, 18\n\tv_writelane_b32 v11, s45, 19\n\ts_mov_b32 s44, 0xb0\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v11, s44, 20\n\tv_writelane_b32 v11, s45, 21\n\ts_mov_b32 s44, 0xb8\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v11, s44, 22\n\tv_writelane_b32 v11, s45, 23\n\ts_mov_b32 s44, 0xc0\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v11, s44, 24\n\tv_writelane_b32 v11, s45, 25\n\tv_mov_b32_e32 v0, s40\n\tv_mov_b32_e32 v1, s41\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v2, s42\n\tv_mov_b32_e32 v3, s43\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s40\n\tv_mov_b32_e32 v1, s41\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s36\n\tv_mov_b32_e32 v1, s37\n\tv_mov_b32_e32 v2, s38\n\tv_mov_b32_e32 v3, s39\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s36\n\tv_mov_b32_e32 v1, s37\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s30\n\tv_mov_b32_e32 v1, s31\n\tv_mov_b32_e32 v2, s34\n\tv_mov_b32_e32 v3, s35\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s30\n\tv_mov_b32_e32 v1, s31\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s28\n\tv_mov_b32_e32 v1, s29\n\ts_waitcnt vmcnt(2) lgkmcnt(4)\n\tflat_store_b64 v[0:1], v[6:7]\n\tv_mov_b32_e32 v0, s26\n\tv_mov_b32_e32 v1, s27\n\ts_waitcnt vmcnt(1) lgkmcnt(3)\n\tflat_store_b64 v[0:1], v[4:5]\n\tv_mov_b32_e32 v0, s24\n\tv_mov_b32_e32 v1, s25\n\ts_waitcnt vmcnt(0) lgkmcnt(2)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s22\n\tv_mov_b32_e32 v1, s23\n\tv_mov_b32_e32 v2, s20\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tv_mov_b32_e32 v2, s15\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tv_mov_b32_e32 v2, s8\n\tv_mov_b32_e32 v3, s9\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b64 s[6:7], 48\n\ts_mov_b32 s2, s0\n\ts_mov_b32 s0, s1\n\ts_mov_b32 s3, s6\n\ts_mov_b32 s1, s7\n\ts_add_u32 s8, s2, s3\n\ts_addc_u32 s0, s0, s1\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s0\n\tv_writelane_b32 v11, s8, 26\n\tv_writelane_b32 v11, s9, 27\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_group_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_group_id@rel32@hi+12\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, off offset:208 ; 4-byte Folded Spill\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:220 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v10, 0\n\tv_readlane_b32 s13, v10, 1\n\tv_readlane_b32 s12, v10, 2\n\tv_readlane_b32 s10, v10, 3\n\tv_readlane_b32 s11, v10, 4\n\tv_readlane_b32 s8, v11, 26\n\tv_readlane_b32 s9, v11, 27\n\tv_readlane_b32 s4, v10, 7\n\tv_readlane_b32 s5, v10, 8\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:208 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:224 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:224 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v1, off offset:212 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_size@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_size@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:220 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v10, 0\n\tv_readlane_b32 s13, v10, 1\n\tv_readlane_b32 s12, v10, 2\n\tv_readlane_b32 s10, v10, 3\n\tv_readlane_b32 s11, v10, 4\n\tv_readlane_b32 s4, v10, 7\n\tv_readlane_b32 s5, v10, 8\n\tv_readlane_b32 s8, v11, 26\n\tv_readlane_b32 s9, v11, 27\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:208 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:216 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:216 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v1\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_id@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s8, v10, 26\n\tv_readlane_b32 s9, v10, 27\n\tv_readlane_b32 s6, v10, 18\n\tv_readlane_b32 s7, v10, 19\n\tv_readlane_b32 s2, v11, 2\n\tv_readlane_b32 s3, v11, 3\n\tv_readlane_b32 s0, v10, 30\n\tv_readlane_b32 s1, v10, 31\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:212 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v5, v1\n\tscratch_load_b32 v1, off, off offset:208 ; 4-byte Folded Reload\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v5\n\tv_mov_b32_e32 v5, v2\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr5\n ; implicit-def: $sgpr5\n\tv_mov_b32_e32 v2, s4\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v2\n\ts_waitcnt vmcnt(1)\n\tv_mad_u64_u32 v[2:3], s4, v0, v4, v[5:6]\n\tv_mov_b32_e32 v0, v2\n\tv_mov_b32_e32 v2, s8\n\tv_mov_b32_e32 v3, s9\n\tflat_store_b32 v[2:3], v0\n\tv_mov_b32_e32 v2, s8\n\tv_mov_b32_e32 v3, s9\n\tflat_load_b32 v0, v[2:3]\n\tv_mov_b32_e32 v2, s6\n\tv_mov_b32_e32 v3, s7\n\tflat_load_b32 v2, v[2:3]\n\ts_mov_b32 s4, 31\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v3, s4, v2\n\tv_add_nc_u32_e64 v2, v2, v3\n\tv_xor_b32_e64 v3, v2, v3\n\tv_sub_nc_u32_e64 v4, v1, v3\n\tv_cvt_f32_u32_e32 v2, v3\n\tv_rcp_iflag_f32_e32 v2, v2\n\ts_waitcnt_depctr 0xfff\n\tv_mul_f32_e32 v2, 0x4f7ffffe, v2\n\tv_cvt_u32_f32_e32 v2, v2\n\tv_mul_lo_u32 v4, v4, v2\n\tv_mul_hi_u32 v4, v2, v4\n\tv_add_nc_u32_e64 v4, v2, v4\n\tv_ashrrev_i32_e64 v2, s4, v0\n\tv_add_nc_u32_e64 v0, v0, v2\n\tv_xor_b32_e64 v0, v0, v2\n\tv_mul_hi_u32 v4, v0, v4\n\tv_mul_lo_u32 v4, v4, v3\n\tv_sub_nc_u32_e64 v0, v0, v4\n\tv_cmp_ge_u32_e64 s5, v0, v3\n\tv_sub_nc_u32_e64 v4, v0, v3\n\tv_cndmask_b32_e64 v0, v0, v4, s5\n\tv_cmp_ge_u32_e64 s5, v0, v3\n\tv_sub_nc_u32_e64 v3, v0, v3\n\tv_cndmask_b32_e64 v0, v0, v3, s5\n\tv_xor_b32_e64 v0, v0, v2\n\tv_sub_nc_u32_e64 v0, v0, v2\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b32 v[2:3], v0\n\tv_mov_b32_e32 v2, s8\n\tv_mov_b32_e32 v3, s9\n\tflat_load_b32 v4, v[2:3]\n\tv_mov_b32_e32 v2, s6\n\tv_mov_b32_e32 v3, s7\n\tflat_load_b32 v0, v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v3, s4, v0\n\tv_add_nc_u32_e64 v0, v0, v3\n\tv_xor_b32_e64 v5, v0, v3\n\tv_sub_nc_u32_e64 v2, v1, v5\n\tv_cvt_f32_u32_e32 v0, v5\n\tv_rcp_iflag_f32_e32 v0, v0\n\ts_waitcnt_depctr 0xfff\n\tv_mul_f32_e32 v0, 0x4f7ffffe, v0\n\tv_cvt_u32_f32_e32 v0, v0\n\tv_mul_lo_u32 v2, v2, v0\n\tv_mul_hi_u32 v2, v0, v2\n\tv_add_nc_u32_e64 v0, v0, v2\n\tv_ashrrev_i32_e64 v2, s4, v4\n\tv_add_nc_u32_e64 v4, v4, v2\n\tv_xor_b32_e64 v4, v4, v2\n\tv_mul_hi_u32 v0, v4, v0\n\tv_mul_lo_u32 v6, v0, v5\n\tv_sub_nc_u32_e64 v4, v4, v6\n\tv_cmp_ge_u32_e64 s6, v4, v5\n\tv_sub_nc_u32_e64 v6, v4, v5\n\tv_cndmask_b32_e64 v4, v4, v6, s6\n\tv_cmp_ge_u32_e64 s4, v4, v5\n\ts_mov_b32 s5, 1\n\tv_add_nc_u32_e64 v4, v0, s5\n\tv_cndmask_b32_e64 v0, v0, v4, s6\n\tv_add_nc_u32_e64 v4, v0, s5\n\tv_cndmask_b32_e64 v0, v0, v4, s4\n\tv_xor_b32_e64 v2, v2, v3\n\tv_xor_b32_e64 v0, v0, v2\n\tv_sub_nc_u32_e64 v0, v0, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b32 v[2:3], v0\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_load_b32 v0, v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_gt_i32_e64 s1, v0, v1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v11, s0, 28\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v11, off offset:200 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB14_8\n; %bb.1:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v10, off, off offset:204 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v11, off, off offset:200 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v10, 20\n\tv_readlane_b32 s1, v10, 21\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v11, 0\n\tv_readlane_b32 s3, v11, 1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v2, s1\n\tv_mov_b32_e32 v1, s0\n\tflat_load_b32 v1, v[1:2]\n\ts_mov_b32 s0, -1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v1, v1, s0\n\tv_cmp_lt_i32_e64 s1, v0, v1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v11, s0, 29\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v11, off offset:200 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB14_7\n; %bb.2:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v11, off, off offset:200 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v11, 4\n\tv_readlane_b32 s1, v11, 5\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v0, v[0:1]\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_gt_i32_e64 s1, v0, s0\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v11, s0, 30\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v11, off offset:200 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB14_6\n; %bb.3:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v10, off, off offset:204 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v11, off, off offset:200 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v10, 16\n\tv_readlane_b32 s1, v10, 17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v11, 4\n\tv_readlane_b32 s3, v11, 5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v2, s1\n\tv_mov_b32_e32 v1, s0\n\tflat_load_b32 v1, v[1:2]\n\ts_mov_b32 s0, -1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v1, v1, s0\n\tv_cmp_lt_i32_e64 s1, v0, v1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v11, s0, 31\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v11, off offset:200 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB14_5\n; %bb.4:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v10, off, off offset:200 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v11, off, off offset:204 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v11, 28\n\tv_readlane_b32 s3, v11, 29\n\tv_readlane_b32 s4, v11, 10\n\tv_readlane_b32 s5, v11, 11\n\tv_readlane_b32 s6, v11, 22\n\tv_readlane_b32 s7, v11, 23\n\tv_readlane_b32 s8, v10, 24\n\tv_readlane_b32 s9, v10, 25\n\tv_readlane_b32 s10, v10, 22\n\tv_readlane_b32 s11, v10, 23\n\tv_readlane_b32 s12, v11, 24\n\tv_readlane_b32 s13, v11, 25\n\tv_readlane_b32 s14, v10, 20\n\tv_readlane_b32 s15, v10, 21\n\tv_readlane_b32 s16, v10, 18\n\tv_readlane_b32 s17, v10, 19\n\tv_readlane_b32 s20, v10, 12\n\tv_readlane_b32 s21, v10, 13\n\tv_readlane_b32 s22, v10, 16\n\tv_readlane_b32 s23, v10, 17\n\tv_readlane_b32 s24, v10, 14\n\tv_readlane_b32 s25, v10, 15\n\tv_readlane_b32 s26, v10, 6\n\tv_readlane_b32 s27, v10, 7\n\tv_readlane_b32 s28, v10, 10\n\tv_readlane_b32 s29, v10, 11\n\tv_readlane_b32 s18, v10, 8\n\tv_readlane_b32 s19, v10, 9\n\tv_readlane_b32 s30, v11, 20\n\tv_readlane_b32 s31, v11, 21\n\tv_readlane_b32 s34, v11, 14\n\tv_readlane_b32 s35, v11, 15\n\tv_readlane_b32 s36, v11, 12\n\tv_readlane_b32 s37, v11, 13\n\tv_mov_b32_e32 v0, s36\n\tv_mov_b32_e32 v1, s37\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\ts_mov_b32 s0, 3\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s26\n\tv_mov_b32_e32 v1, s27\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s36\n\tv_mov_b32_e32 v1, s37\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v2, 31, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_lshlrev_b64 v[1:2], s0, v[0:1]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1] offset:8\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s36\n\tv_mov_b32_e32 v1, s37\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v0, v[3:4]\n\ts_mov_b32 s1, -1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v3, v0, s1\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s28\n\tv_mov_b32_e32 v1, s29\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s34\n\tv_mov_b32_e32 v1, s35\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s20\n\tv_mov_b32_e32 v1, s21\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s34\n\tv_mov_b32_e32 v1, s35\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v0, v[3:4]\n\tv_mov_b32_e32 v3, s30\n\tv_mov_b32_e32 v4, s31\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v3, v0, v3\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s24\n\tv_mov_b32_e32 v1, s25\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s34\n\tv_mov_b32_e32 v1, s35\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v0, v[3:4]\n\tv_mov_b32_e32 v3, s30\n\tv_mov_b32_e32 v4, s31\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v3, v0, v3\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s22\n\tv_mov_b32_e32 v1, s23\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s26\n\tv_mov_b32_e32 v3, s27\n\tflat_load_b64 v[2:3], v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[0:1], v[0:1], v[2:3]\n\ts_mov_b64 s[18:19], 0.5\n\tv_mul_f64 v[2:3], v[0:1], s[18:19]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s28\n\tv_mov_b32_e32 v1, s29\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s26\n\tv_mov_b32_e32 v3, s27\n\tflat_load_b64 v[2:3], v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[0:1], v[0:1], v[2:3]\n\tv_mul_f64 v[2:3], v[0:1], s[18:19]\n\tv_mov_b32_e32 v0, s14\n\tv_mov_b32_e32 v1, s15\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s24\n\tv_mov_b32_e32 v1, s25\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s20\n\tv_mov_b32_e32 v3, s21\n\tflat_load_b64 v[2:3], v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[0:1], v[0:1], v[2:3]\n\tv_mul_f64 v[2:3], v[0:1], s[18:19]\n\tv_mov_b32_e32 v0, s10\n\tv_mov_b32_e32 v1, s11\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s22\n\tv_mov_b32_e32 v1, s23\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s20\n\tv_mov_b32_e32 v3, s21\n\tflat_load_b64 v[2:3], v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[0:1], v[0:1], v[2:3]\n\tv_mul_f64 v[2:3], v[0:1], s[18:19]\n\tv_mov_b32_e32 v0, s8\n\tv_mov_b32_e32 v1, s9\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s14\n\tv_mov_b32_e32 v3, s15\n\tflat_load_b64 v[2:3], v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[0:1], v[0:1], -v[2:3]\n\tv_mov_b32_e32 v2, s12\n\tv_mov_b32_e32 v3, s13\n\tflat_load_b64 v[2:3], v[2:3]\n\tv_mov_b32_e32 v4, s10\n\tv_mov_b32_e32 v5, s11\n\tflat_load_b64 v[4:5], v[4:5]\n\tv_mov_b32_e32 v6, s8\n\tv_mov_b32_e32 v7, s9\n\tflat_load_b64 v[6:7], v[6:7]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[4:5], v[4:5], -v[6:7]\n\tv_mov_b32_e32 v6, s6\n\tv_mov_b32_e32 v7, s7\n\tflat_load_b64 v[6:7], v[6:7]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mul_f64 v[4:5], v[4:5], v[6:7]\n\tv_fma_f64 v[2:3], v[0:1], v[2:3], v[4:5]\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v4, 31, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_lshlrev_b64 v[6:7], s0, v[0:1]\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v1, v9\n\tv_mov_b32_e32 v4, v7\n\tv_add_co_u32 v0, s0, v0, v5\n\tv_add_co_ci_u32_e64 v4, s0, v1, v4, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_store_b64 v[0:1], v[2:3]\n.LBB14_5:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v11, off, off offset:200 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v11, 31\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB14_6:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v11, off, off offset:200 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v11, 30\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB14_7:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v11, off, off offset:200 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v11, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB14_8:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v11, off, off offset:200 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v11, 28\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z13DivergenceGPUPdS_S_iidd\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 352\n\t\t.amdhsa_kernarg_size 304\n\t\t.amdhsa_user_sgpr_count 13\n\t\t.amdhsa_user_sgpr_dispatch_ptr 1\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 1\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 1\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 1\n\t\t.amdhsa_system_sgpr_workgroup_id_z 1\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 2\n\t\t.amdhsa_next_free_vgpr 32\n\t\t.amdhsa_next_free_sgpr 46\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end14:\n\t.size\t_Z13DivergenceGPUPdS_S_iidd, .Lfunc_end14-_Z13DivergenceGPUPdS_S_iidd\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 4468\n; NumSgprs: 48\n; NumVgprs: 32\n; ScratchSize: 352\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 5\n; VGPRBlocks: 3\n; NumSGPRsForWavesPerEU: 48\n; NumVGPRsForWavesPerEU: 32\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1\n; COMPUTE_PGM_RSRC2:USER_SGPR: 13\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2\n\t.text\n\t.protected\t_Z12LaplacianGPUPdS_iidd ; -- Begin function _Z12LaplacianGPUPdS_iidd\n\t.globl\t_Z12LaplacianGPUPdS_iidd\n\t.p2align\t8\n\t.type\t_Z12LaplacianGPUPdS_iidd,@function\n_Z12LaplacianGPUPdS_iidd: ; @_Z12LaplacianGPUPdS_iidd\n; %bb.0:\n\ts_mov_b32 s32, 0xd0\n ; implicit-def: $vgpr12 : SGPR spill to VGPR lane\n\tv_writelane_b32 v12, s15, 0\n\ts_mov_b32 s6, s14\n\tv_readlane_b32 s14, v12, 0\n\tv_writelane_b32 v12, s6, 1\n\ts_mov_b32 s12, s13\n\tv_readlane_b32 s13, v12, 1\n\tv_writelane_b32 v12, s12, 2\n\ts_mov_b64 s[10:11], s[4:5]\n\tv_writelane_b32 v12, s10, 3\n\tv_writelane_b32 v12, s11, 4\n\tv_writelane_b32 v12, s2, 5\n\tv_writelane_b32 v12, s3, 6\n\ts_mov_b64 s[4:5], s[0:1]\n\tv_readlane_b32 s0, v12, 5\n\tv_readlane_b32 s1, v12, 6\n\tv_writelane_b32 v12, s4, 7\n\tv_writelane_b32 v12, s5, 8\n\tv_mov_b32_e32 v31, v0\n\tscratch_store_b32 off, v31, off offset:196 ; 4-byte Folded Spill\n\ts_load_b64 s[36:37], s[0:1], 0x0\n\ts_load_b64 s[30:31], s[0:1], 0x8\n\ts_load_b32 s20, s[0:1], 0x10\n\ts_load_b32 s15, s[0:1], 0x14\n\ts_load_b64 s[8:9], s[0:1], 0x18\n\ts_load_b64 s[2:3], s[0:1], 0x20\n\ts_mov_b64 s[6:7], src_private_base\n\ts_mov_b32 s16, 32\n\ts_lshr_b64 s[6:7], s[6:7], s16\n\ts_mov_b32 s21, s6\n\tv_writelane_b32 v12, s21, 9\n\ts_mov_b32 s34, 32\n ; kill: def $sgpr34 killed $sgpr34 def $sgpr34_sgpr35\n\ts_mov_b32 s35, s21\n\ts_mov_b32 s28, 40\n ; kill: def $sgpr28 killed $sgpr28 def $sgpr28_sgpr29\n\ts_mov_b32 s29, s21\n\ts_mov_b32 s26, 48\n ; kill: def $sgpr26 killed $sgpr26 def $sgpr26_sgpr27\n\ts_mov_b32 s27, s21\n\ts_mov_b64 s[6:7], s[26:27]\n\tv_writelane_b32 v12, s6, 10\n\tv_writelane_b32 v12, s7, 11\n\ts_mov_b32 s24, 56\n ; kill: def $sgpr24 killed $sgpr24 def $sgpr24_sgpr25\n\ts_mov_b32 s25, s21\n\ts_mov_b64 s[6:7], s[24:25]\n\tv_writelane_b32 v12, s6, 12\n\tv_writelane_b32 v12, s7, 13\n\ts_mov_b32 s22, 64\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s21\n\ts_mov_b64 s[6:7], s[22:23]\n\tv_writelane_b32 v12, s6, 14\n\tv_writelane_b32 v12, s7, 15\n\ts_mov_b32 s18, 0x44\n ; kill: def $sgpr18 killed $sgpr18 def $sgpr18_sgpr19\n\ts_mov_b32 s19, s21\n\tv_writelane_b32 v12, s18, 16\n\tv_writelane_b32 v12, s19, 17\n\ts_mov_b64 s[6:7], s[18:19]\n\tv_writelane_b32 v12, s6, 18\n\tv_writelane_b32 v12, s7, 19\n\ts_mov_b32 s16, 0x48\n ; kill: def $sgpr16 killed $sgpr16 def $sgpr16_sgpr17\n\ts_mov_b32 s17, s21\n\ts_mov_b64 s[6:7], s[16:17]\n\tv_writelane_b32 v12, s6, 20\n\tv_writelane_b32 v12, s7, 21\n\ts_mov_b32 s6, 0x50\n ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7\n\ts_mov_b32 s7, s21\n\ts_mov_b64 s[38:39], s[6:7]\n\tv_writelane_b32 v12, s38, 22\n\tv_writelane_b32 v12, s39, 23\n\ts_mov_b32 s38, 0x58\n ; kill: def $sgpr38 killed $sgpr38 def $sgpr38_sgpr39\n\ts_mov_b32 s39, s21\n\tv_writelane_b32 v12, s38, 24\n\tv_writelane_b32 v12, s39, 25\n\tv_writelane_b32 v12, s38, 26\n\tv_writelane_b32 v12, s39, 27\n\ts_mov_b32 s38, 0x5c\n ; kill: def $sgpr38 killed $sgpr38 def $sgpr38_sgpr39\n\ts_mov_b32 s39, s21\n\tv_writelane_b32 v12, s38, 28\n\tv_writelane_b32 v12, s39, 29\n\tv_writelane_b32 v12, s38, 30\n\tv_writelane_b32 v12, s39, 31\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v12, off offset:180 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_mov_b32 s38, 0x60\n ; kill: def $sgpr38 killed $sgpr38 def $sgpr38_sgpr39\n\ts_mov_b32 s39, s21\n ; implicit-def: $vgpr13 : SGPR spill to VGPR lane\n\tv_writelane_b32 v13, s38, 0\n\tv_writelane_b32 v13, s39, 1\n\tv_writelane_b32 v13, s38, 2\n\tv_writelane_b32 v13, s39, 3\n\ts_mov_b32 s38, 0x68\n ; kill: def $sgpr38 killed $sgpr38 def $sgpr38_sgpr39\n\ts_mov_b32 s39, s21\n\tv_writelane_b32 v13, s38, 4\n\tv_writelane_b32 v13, s39, 5\n\ts_mov_b32 s38, 0x70\n ; kill: def $sgpr38 killed $sgpr38 def $sgpr38_sgpr39\n\ts_mov_b32 s39, s21\n\tv_writelane_b32 v13, s38, 6\n\tv_writelane_b32 v13, s39, 7\n\ts_mov_b32 s38, 0x78\n ; kill: def $sgpr38 killed $sgpr38 def $sgpr38_sgpr39\n\ts_mov_b32 s39, s21\n\tv_writelane_b32 v13, s38, 8\n\tv_writelane_b32 v13, s39, 9\n\ts_mov_b32 s38, 0x80\n ; kill: def $sgpr38 killed $sgpr38 def $sgpr38_sgpr39\n\ts_mov_b32 s39, s21\n\tv_writelane_b32 v13, s38, 10\n\tv_writelane_b32 v13, s39, 11\n\ts_mov_b32 s38, 0x88\n ; kill: def $sgpr38 killed $sgpr38 def $sgpr38_sgpr39\n\ts_mov_b32 s39, s21\n\tv_writelane_b32 v13, s38, 12\n\tv_writelane_b32 v13, s39, 13\n\ts_mov_b32 s38, 0x90\n ; kill: def $sgpr38 killed $sgpr38 def $sgpr38_sgpr39\n\ts_mov_b32 s39, s21\n\tv_writelane_b32 v13, s38, 14\n\tv_writelane_b32 v13, s39, 15\n\ts_mov_b32 s38, 0x98\n ; kill: def $sgpr38 killed $sgpr38 def $sgpr38_sgpr39\n\ts_mov_b32 s39, s21\n\tv_writelane_b32 v13, s38, 16\n\tv_writelane_b32 v13, s39, 17\n\ts_mov_b32 s38, 0xa0\n ; kill: def $sgpr38 killed $sgpr38 def $sgpr38_sgpr39\n\ts_mov_b32 s39, s21\n\tv_writelane_b32 v13, s38, 18\n\tv_writelane_b32 v13, s39, 19\n\ts_mov_b32 s38, 0xa8\n ; kill: def $sgpr38 killed $sgpr38 def $sgpr38_sgpr39\n\ts_mov_b32 s39, s21\n\tv_writelane_b32 v13, s38, 20\n\tv_writelane_b32 v13, s39, 21\n\tv_mov_b32_e32 v0, s34\n\tv_mov_b32_e32 v1, s35\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v2, s36\n\tv_mov_b32_e32 v3, s37\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s34\n\tv_mov_b32_e32 v1, s35\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s28\n\tv_mov_b32_e32 v1, s29\n\tv_mov_b32_e32 v2, s30\n\tv_mov_b32_e32 v3, s31\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s28\n\tv_mov_b32_e32 v1, s29\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s26\n\tv_mov_b32_e32 v1, s27\n\ts_waitcnt vmcnt(1) lgkmcnt(2)\n\tflat_store_b64 v[0:1], v[4:5]\n\tv_mov_b32_e32 v0, s24\n\tv_mov_b32_e32 v1, s25\n\ts_waitcnt vmcnt(0) lgkmcnt(1)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s22\n\tv_mov_b32_e32 v1, s23\n\tv_mov_b32_e32 v2, s20\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tv_mov_b32_e32 v2, s15\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tv_mov_b32_e32 v2, s8\n\tv_mov_b32_e32 v3, s9\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b64 s[6:7], 40\n\ts_mov_b32 s2, s0\n\ts_mov_b32 s0, s1\n\ts_mov_b32 s3, s6\n\ts_mov_b32 s1, s7\n\ts_add_u32 s8, s2, s3\n\ts_addc_u32 s0, s0, s1\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s0\n\tv_writelane_b32 v13, s8, 22\n\tv_writelane_b32 v13, s9, 23\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_group_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_group_id@rel32@hi+12\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, off offset:184 ; 4-byte Folded Spill\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:196 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v12, 0\n\tv_readlane_b32 s13, v12, 1\n\tv_readlane_b32 s12, v12, 2\n\tv_readlane_b32 s10, v12, 3\n\tv_readlane_b32 s11, v12, 4\n\tv_readlane_b32 s8, v13, 22\n\tv_readlane_b32 s9, v13, 23\n\tv_readlane_b32 s4, v12, 7\n\tv_readlane_b32 s5, v12, 8\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:184 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:200 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:200 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v1, off offset:188 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_size@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_size@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:196 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v12, 0\n\tv_readlane_b32 s13, v12, 1\n\tv_readlane_b32 s12, v12, 2\n\tv_readlane_b32 s10, v12, 3\n\tv_readlane_b32 s11, v12, 4\n\tv_readlane_b32 s4, v12, 7\n\tv_readlane_b32 s5, v12, 8\n\tv_readlane_b32 s8, v13, 22\n\tv_readlane_b32 s9, v13, 23\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:184 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:192 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:192 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v1\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_id@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s8, v12, 24\n\tv_readlane_b32 s9, v12, 25\n\tv_readlane_b32 s6, v12, 16\n\tv_readlane_b32 s7, v12, 17\n\tv_readlane_b32 s2, v13, 0\n\tv_readlane_b32 s3, v13, 1\n\tv_readlane_b32 s0, v12, 28\n\tv_readlane_b32 s1, v12, 29\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:188 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v5, v1\n\tscratch_load_b32 v1, off, off offset:184 ; 4-byte Folded Reload\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v5\n\tv_mov_b32_e32 v5, v2\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr5\n ; implicit-def: $sgpr5\n\tv_mov_b32_e32 v2, s4\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v2\n\ts_waitcnt vmcnt(1)\n\tv_mad_u64_u32 v[2:3], s4, v0, v4, v[5:6]\n\tv_mov_b32_e32 v0, v2\n\tv_mov_b32_e32 v2, s8\n\tv_mov_b32_e32 v3, s9\n\tflat_store_b32 v[2:3], v0\n\tv_mov_b32_e32 v2, s8\n\tv_mov_b32_e32 v3, s9\n\tflat_load_b32 v0, v[2:3]\n\tv_mov_b32_e32 v2, s6\n\tv_mov_b32_e32 v3, s7\n\tflat_load_b32 v2, v[2:3]\n\ts_mov_b32 s4, 31\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v3, s4, v2\n\tv_add_nc_u32_e64 v2, v2, v3\n\tv_xor_b32_e64 v3, v2, v3\n\tv_sub_nc_u32_e64 v4, v1, v3\n\tv_cvt_f32_u32_e32 v2, v3\n\tv_rcp_iflag_f32_e32 v2, v2\n\ts_waitcnt_depctr 0xfff\n\tv_mul_f32_e32 v2, 0x4f7ffffe, v2\n\tv_cvt_u32_f32_e32 v2, v2\n\tv_mul_lo_u32 v4, v4, v2\n\tv_mul_hi_u32 v4, v2, v4\n\tv_add_nc_u32_e64 v4, v2, v4\n\tv_ashrrev_i32_e64 v2, s4, v0\n\tv_add_nc_u32_e64 v0, v0, v2\n\tv_xor_b32_e64 v0, v0, v2\n\tv_mul_hi_u32 v4, v0, v4\n\tv_mul_lo_u32 v4, v4, v3\n\tv_sub_nc_u32_e64 v0, v0, v4\n\tv_cmp_ge_u32_e64 s5, v0, v3\n\tv_sub_nc_u32_e64 v4, v0, v3\n\tv_cndmask_b32_e64 v0, v0, v4, s5\n\tv_cmp_ge_u32_e64 s5, v0, v3\n\tv_sub_nc_u32_e64 v3, v0, v3\n\tv_cndmask_b32_e64 v0, v0, v3, s5\n\tv_xor_b32_e64 v0, v0, v2\n\tv_sub_nc_u32_e64 v0, v0, v2\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b32 v[2:3], v0\n\tv_mov_b32_e32 v2, s8\n\tv_mov_b32_e32 v3, s9\n\tflat_load_b32 v4, v[2:3]\n\tv_mov_b32_e32 v2, s6\n\tv_mov_b32_e32 v3, s7\n\tflat_load_b32 v0, v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v3, s4, v0\n\tv_add_nc_u32_e64 v0, v0, v3\n\tv_xor_b32_e64 v5, v0, v3\n\tv_sub_nc_u32_e64 v2, v1, v5\n\tv_cvt_f32_u32_e32 v0, v5\n\tv_rcp_iflag_f32_e32 v0, v0\n\ts_waitcnt_depctr 0xfff\n\tv_mul_f32_e32 v0, 0x4f7ffffe, v0\n\tv_cvt_u32_f32_e32 v0, v0\n\tv_mul_lo_u32 v2, v2, v0\n\tv_mul_hi_u32 v2, v0, v2\n\tv_add_nc_u32_e64 v0, v0, v2\n\tv_ashrrev_i32_e64 v2, s4, v4\n\tv_add_nc_u32_e64 v4, v4, v2\n\tv_xor_b32_e64 v4, v4, v2\n\tv_mul_hi_u32 v0, v4, v0\n\tv_mul_lo_u32 v6, v0, v5\n\tv_sub_nc_u32_e64 v4, v4, v6\n\tv_cmp_ge_u32_e64 s6, v4, v5\n\tv_sub_nc_u32_e64 v6, v4, v5\n\tv_cndmask_b32_e64 v4, v4, v6, s6\n\tv_cmp_ge_u32_e64 s4, v4, v5\n\ts_mov_b32 s5, 1\n\tv_add_nc_u32_e64 v4, v0, s5\n\tv_cndmask_b32_e64 v0, v0, v4, s6\n\tv_add_nc_u32_e64 v4, v0, s5\n\tv_cndmask_b32_e64 v0, v0, v4, s4\n\tv_xor_b32_e64 v2, v2, v3\n\tv_xor_b32_e64 v0, v0, v2\n\tv_sub_nc_u32_e64 v0, v0, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b32 v[2:3], v0\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_load_b32 v0, v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_gt_i32_e64 s1, v0, v1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v13, s0, 24\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v13, off offset:176 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB15_8\n; %bb.1:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v12, off, off offset:180 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v12, 18\n\tv_readlane_b32 s1, v12, 19\n\tv_readlane_b32 s2, v12, 30\n\tv_readlane_b32 s3, v12, 31\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v13, off, off offset:176 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v2, s1\n\tv_mov_b32_e32 v1, s0\n\tflat_load_b32 v1, v[1:2]\n\ts_mov_b32 s0, -1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v1, v1, s0\n\tv_cmp_lt_i32_e64 s1, v0, v1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v13, s0, 25\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v13, off offset:176 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB15_7\n; %bb.2:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v13, off, off offset:176 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v13, 2\n\tv_readlane_b32 s1, v13, 3\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v0, v[0:1]\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_gt_i32_e64 s1, v0, s0\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v13, s0, 26\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v13, off offset:176 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB15_6\n; %bb.3:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v12, off, off offset:180 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v13, off, off offset:176 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v12, 14\n\tv_readlane_b32 s1, v12, 15\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v13, 2\n\tv_readlane_b32 s3, v13, 3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v2, s1\n\tv_mov_b32_e32 v1, s0\n\tflat_load_b32 v1, v[1:2]\n\ts_mov_b32 s0, -1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v1, v1, s0\n\tv_cmp_lt_i32_e64 s1, v0, v1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v13, s0, 27\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v13, off offset:176 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB15_5\n; %bb.4:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v12, off, off offset:180 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v13, off, off offset:176 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s2, v12, 26\n\tv_readlane_b32 s3, v12, 27\n\tv_readlane_b32 s4, v12, 10\n\tv_readlane_b32 s5, v12, 11\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s6, v13, 16\n\tv_readlane_b32 s7, v13, 17\n\tv_readlane_b32 s8, v13, 14\n\tv_readlane_b32 s9, v13, 15\n\tv_readlane_b32 s10, v12, 22\n\tv_readlane_b32 s11, v12, 23\n\tv_readlane_b32 s12, v13, 20\n\tv_readlane_b32 s13, v13, 21\n\tv_readlane_b32 s14, v13, 18\n\tv_readlane_b32 s15, v13, 19\n\tv_readlane_b32 s16, v12, 20\n\tv_readlane_b32 s17, v12, 21\n\tv_readlane_b32 s20, v13, 12\n\tv_readlane_b32 s21, v13, 13\n\tv_readlane_b32 s22, v13, 4\n\tv_readlane_b32 s23, v13, 5\n\tv_readlane_b32 s24, v13, 10\n\tv_readlane_b32 s25, v13, 11\n\tv_readlane_b32 s26, v13, 8\n\tv_readlane_b32 s27, v13, 9\n\tv_readlane_b32 s18, v13, 6\n\tv_readlane_b32 s19, v13, 7\n\tv_readlane_b32 s28, v12, 18\n\tv_readlane_b32 s29, v12, 19\n\tv_readlane_b32 s30, v12, 12\n\tv_readlane_b32 s31, v12, 13\n\tv_mov_b32_e32 v0, s30\n\tv_mov_b32_e32 v1, s31\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\ts_mov_b32 s0, 3\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s22\n\tv_mov_b32_e32 v1, s23\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s30\n\tv_mov_b32_e32 v1, s31\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v2, 31, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_lshlrev_b64 v[1:2], s0, v[0:1]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1] offset:8\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s30\n\tv_mov_b32_e32 v1, s31\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v0, v[3:4]\n\ts_mov_b32 s1, -1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v3, v0, s1\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s26\n\tv_mov_b32_e32 v1, s27\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s30\n\tv_mov_b32_e32 v1, s31\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v0, v[3:4]\n\tv_mov_b32_e32 v3, s28\n\tv_mov_b32_e32 v4, s29\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v3, v0, v3\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s24\n\tv_mov_b32_e32 v1, s25\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s30\n\tv_mov_b32_e32 v1, s31\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v0, v[3:4]\n\tv_mov_b32_e32 v3, s28\n\tv_mov_b32_e32 v4, s29\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v3, v0, v3\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s20\n\tv_mov_b32_e32 v1, s21\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s22\n\tv_mov_b32_e32 v3, s23\n\tflat_load_b64 v[2:3], v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[4:5], v[0:1], -v[2:3]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[2:3], v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_div_scale_f64 v[0:1], s1, v[2:3], v[2:3], v[4:5]\n\tv_rcp_f64_e64 v[6:7], v[0:1]\n\ts_mov_b64 s[18:19], 1.0\n\tv_writelane_b32 v13, s18, 28\n\tv_writelane_b32 v13, s19, 29\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v13, off offset:176 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\tv_fma_f64 v[8:9], -v[0:1], v[6:7], s[18:19]\n\tv_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]\n\tv_fma_f64 v[8:9], -v[0:1], v[6:7], s[18:19]\n\tv_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]\n\tv_div_scale_f64 v[10:11], vcc_lo, v[4:5], v[2:3], v[4:5]\n\tv_mul_f64 v[8:9], v[10:11], v[6:7]\n\tv_fma_f64 v[0:1], -v[0:1], v[8:9], v[10:11]\n\tv_div_fmas_f64 v[0:1], v[0:1], v[6:7], v[8:9]\n\tv_div_fixup_f64 v[2:3], v[0:1], v[2:3], v[4:5]\n\tv_mov_b32_e32 v0, s8\n\tv_mov_b32_e32 v1, s9\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s22\n\tv_mov_b32_e32 v1, s23\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s26\n\tv_mov_b32_e32 v3, s27\n\tflat_load_b64 v[2:3], v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[4:5], v[0:1], -v[2:3]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[2:3], v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_div_scale_f64 v[0:1], s1, v[2:3], v[2:3], v[4:5]\n\tv_rcp_f64_e64 v[6:7], v[0:1]\n\ts_waitcnt_depctr 0xfff\n\tv_fma_f64 v[8:9], -v[0:1], v[6:7], s[18:19]\n\tv_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]\n\tv_fma_f64 v[8:9], -v[0:1], v[6:7], s[18:19]\n\tv_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]\n\tv_div_scale_f64 v[10:11], vcc_lo, v[4:5], v[2:3], v[4:5]\n\tv_mul_f64 v[8:9], v[10:11], v[6:7]\n\tv_fma_f64 v[0:1], -v[0:1], v[8:9], v[10:11]\n\tv_div_fmas_f64 v[0:1], v[0:1], v[6:7], v[8:9]\n\tv_div_fixup_f64 v[2:3], v[0:1], v[2:3], v[4:5]\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s24\n\tv_mov_b32_e32 v1, s25\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s22\n\tv_mov_b32_e32 v3, s23\n\tflat_load_b64 v[2:3], v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[4:5], v[0:1], -v[2:3]\n\tv_mov_b32_e32 v0, s10\n\tv_mov_b32_e32 v1, s11\n\tflat_load_b64 v[2:3], v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_div_scale_f64 v[0:1], s1, v[2:3], v[2:3], v[4:5]\n\tv_rcp_f64_e64 v[6:7], v[0:1]\n\ts_waitcnt_depctr 0xfff\n\tv_fma_f64 v[8:9], -v[0:1], v[6:7], s[18:19]\n\tv_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]\n\tv_fma_f64 v[8:9], -v[0:1], v[6:7], s[18:19]\n\tv_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]\n\tv_div_scale_f64 v[10:11], vcc_lo, v[4:5], v[2:3], v[4:5]\n\tv_mul_f64 v[8:9], v[10:11], v[6:7]\n\tv_fma_f64 v[0:1], -v[0:1], v[8:9], v[10:11]\n\tv_div_fmas_f64 v[0:1], v[0:1], v[6:7], v[8:9]\n\tv_div_fixup_f64 v[2:3], v[0:1], v[2:3], v[4:5]\n\tv_mov_b32_e32 v0, s14\n\tv_mov_b32_e32 v1, s15\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s22\n\tv_mov_b32_e32 v1, s23\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s20\n\tv_mov_b32_e32 v3, s21\n\tflat_load_b64 v[2:3], v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[4:5], v[0:1], -v[2:3]\n\tv_mov_b32_e32 v0, s10\n\tv_mov_b32_e32 v1, s11\n\tflat_load_b64 v[2:3], v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_div_scale_f64 v[0:1], s1, v[2:3], v[2:3], v[4:5]\n\tv_rcp_f64_e64 v[6:7], v[0:1]\n\ts_waitcnt_depctr 0xfff\n\tv_fma_f64 v[8:9], -v[0:1], v[6:7], s[18:19]\n\tv_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]\n\tv_fma_f64 v[8:9], -v[0:1], v[6:7], s[18:19]\n\tv_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]\n\tv_div_scale_f64 v[10:11], vcc_lo, v[4:5], v[2:3], v[4:5]\n\tv_mul_f64 v[8:9], v[10:11], v[6:7]\n\tv_fma_f64 v[0:1], -v[0:1], v[8:9], v[10:11]\n\tv_div_fmas_f64 v[0:1], v[0:1], v[6:7], v[8:9]\n\tv_div_fixup_f64 v[2:3], v[0:1], v[2:3], v[4:5]\n\tv_mov_b32_e32 v0, s12\n\tv_mov_b32_e32 v1, s13\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s14\n\tv_mov_b32_e32 v3, s15\n\tflat_load_b64 v[2:3], v[2:3]\n\tv_mov_b32_e32 v4, s12\n\tv_mov_b32_e32 v5, s13\n\tflat_load_b64 v[4:5], v[4:5]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[2:3], v[2:3], -v[4:5]\n\tv_mov_b32_e32 v4, s10\n\tv_mov_b32_e32 v5, s11\n\tflat_load_b64 v[4:5], v[4:5]\n\tv_mov_b32_e32 v6, s8\n\tv_mov_b32_e32 v7, s9\n\tflat_load_b64 v[6:7], v[6:7]\n\tv_mov_b32_e32 v9, s7\n\tv_mov_b32_e32 v8, s6\n\tflat_load_b64 v[8:9], v[8:9]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[6:7], v[6:7], -v[8:9]\n\tv_mul_f64 v[4:5], v[4:5], v[6:7]\n\tv_fma_f64 v[2:3], v[0:1], v[2:3], v[4:5]\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v4, 31, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_lshlrev_b64 v[6:7], s0, v[0:1]\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v1, v9\n\tv_mov_b32_e32 v4, v7\n\tv_add_co_u32 v0, s0, v0, v5\n\tv_add_co_ci_u32_e64 v4, s0, v1, v4, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_store_b64 v[0:1], v[2:3]\n.LBB15_5:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v13, off, off offset:176 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v13, 27\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB15_6:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v13, off, off offset:176 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v13, 26\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB15_7:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v13, off, off offset:176 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v13, 25\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB15_8:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v13, off, off offset:176 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v13, 24\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z12LaplacianGPUPdS_iidd\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 320\n\t\t.amdhsa_kernarg_size 296\n\t\t.amdhsa_user_sgpr_count 13\n\t\t.amdhsa_user_sgpr_dispatch_ptr 1\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 1\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 1\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 1\n\t\t.amdhsa_system_sgpr_workgroup_id_z 1\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 2\n\t\t.amdhsa_next_free_vgpr 32\n\t\t.amdhsa_next_free_sgpr 40\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end15:\n\t.size\t_Z12LaplacianGPUPdS_iidd, .Lfunc_end15-_Z12LaplacianGPUPdS_iidd\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 4616\n; NumSgprs: 42\n; NumVgprs: 32\n; ScratchSize: 320\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 5\n; VGPRBlocks: 3\n; NumSGPRsForWavesPerEU: 42\n; NumVGPRsForWavesPerEU: 32\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1\n; COMPUTE_PGM_RSRC2:USER_SGPR: 13\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2\n\t.text\n\t.protected\t_Z11gradientGPUPdS_S_iidd ; -- Begin function _Z11gradientGPUPdS_S_iidd\n\t.globl\t_Z11gradientGPUPdS_S_iidd\n\t.p2align\t8\n\t.type\t_Z11gradientGPUPdS_S_iidd,@function\n_Z11gradientGPUPdS_S_iidd: ; @_Z11gradientGPUPdS_S_iidd\n; %bb.0:\n\ts_mov_b32 s32, 0xe0\n ; implicit-def: $vgpr12 : SGPR spill to VGPR lane\n\tv_writelane_b32 v12, s15, 0\n\ts_mov_b32 s6, s14\n\tv_readlane_b32 s14, v12, 0\n\tv_writelane_b32 v12, s6, 1\n\ts_mov_b32 s12, s13\n\tv_readlane_b32 s13, v12, 1\n\tv_writelane_b32 v12, s12, 2\n\ts_mov_b64 s[10:11], s[4:5]\n\tv_writelane_b32 v12, s10, 3\n\tv_writelane_b32 v12, s11, 4\n\tv_writelane_b32 v12, s2, 5\n\tv_writelane_b32 v12, s3, 6\n\ts_mov_b64 s[4:5], s[0:1]\n\tv_readlane_b32 s0, v12, 5\n\tv_readlane_b32 s1, v12, 6\n\tv_writelane_b32 v12, s4, 7\n\tv_writelane_b32 v12, s5, 8\n\tv_mov_b32_e32 v31, v0\n\tscratch_store_b32 off, v31, off offset:212 ; 4-byte Folded Spill\n\ts_load_b64 s[42:43], s[0:1], 0x0\n\ts_load_b64 s[38:39], s[0:1], 0x8\n\ts_load_b64 s[34:35], s[0:1], 0x10\n\ts_load_b32 s20, s[0:1], 0x18\n\ts_load_b32 s15, s[0:1], 0x1c\n\ts_load_b64 s[8:9], s[0:1], 0x20\n\ts_load_b64 s[2:3], s[0:1], 0x28\n\ts_mov_b64 s[6:7], src_private_base\n\ts_mov_b32 s16, 32\n\ts_lshr_b64 s[6:7], s[6:7], s16\n\ts_mov_b32 s21, s6\n\tv_writelane_b32 v12, s21, 9\n\ts_mov_b32 s40, 32\n ; kill: def $sgpr40 killed $sgpr40 def $sgpr40_sgpr41\n\ts_mov_b32 s41, s21\n\ts_mov_b32 s36, 40\n ; kill: def $sgpr36 killed $sgpr36 def $sgpr36_sgpr37\n\ts_mov_b32 s37, s21\n\ts_mov_b32 s30, 48\n ; kill: def $sgpr30 killed $sgpr30 def $sgpr30_sgpr31\n\ts_mov_b32 s31, s21\n\ts_mov_b32 s28, 56\n ; kill: def $sgpr28 killed $sgpr28 def $sgpr28_sgpr29\n\ts_mov_b32 s29, s21\n\ts_mov_b64 s[6:7], s[28:29]\n\tv_writelane_b32 v12, s6, 10\n\tv_writelane_b32 v12, s7, 11\n\ts_mov_b32 s26, 64\n ; kill: def $sgpr26 killed $sgpr26 def $sgpr26_sgpr27\n\ts_mov_b32 s27, s21\n\ts_mov_b64 s[6:7], s[26:27]\n\tv_writelane_b32 v12, s6, 12\n\tv_writelane_b32 v12, s7, 13\n\ts_mov_b32 s24, 0x48\n ; kill: def $sgpr24 killed $sgpr24 def $sgpr24_sgpr25\n\ts_mov_b32 s25, s21\n\ts_mov_b64 s[6:7], s[24:25]\n\tv_writelane_b32 v12, s6, 14\n\tv_writelane_b32 v12, s7, 15\n\ts_mov_b32 s22, 0x50\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s21\n\ts_mov_b64 s[6:7], s[22:23]\n\tv_writelane_b32 v12, s6, 16\n\tv_writelane_b32 v12, s7, 17\n\ts_mov_b32 s18, 0x54\n ; kill: def $sgpr18 killed $sgpr18 def $sgpr18_sgpr19\n\ts_mov_b32 s19, s21\n\tv_writelane_b32 v12, s18, 18\n\tv_writelane_b32 v12, s19, 19\n\ts_mov_b64 s[6:7], s[18:19]\n\tv_writelane_b32 v12, s6, 20\n\tv_writelane_b32 v12, s7, 21\n\ts_mov_b32 s16, 0x58\n ; kill: def $sgpr16 killed $sgpr16 def $sgpr16_sgpr17\n\ts_mov_b32 s17, s21\n\ts_mov_b64 s[6:7], s[16:17]\n\tv_writelane_b32 v12, s6, 22\n\tv_writelane_b32 v12, s7, 23\n\ts_mov_b32 s6, 0x60\n ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7\n\ts_mov_b32 s7, s21\n\ts_mov_b64 s[44:45], s[6:7]\n\tv_writelane_b32 v12, s44, 24\n\tv_writelane_b32 v12, s45, 25\n\ts_mov_b32 s44, 0x68\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v12, s44, 26\n\tv_writelane_b32 v12, s45, 27\n\tv_writelane_b32 v12, s44, 28\n\tv_writelane_b32 v12, s45, 29\n\ts_mov_b32 s44, 0x6c\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v12, s44, 30\n\tv_writelane_b32 v12, s45, 31\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v12, off offset:196 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n ; implicit-def: $vgpr13 : SGPR spill to VGPR lane\n\tv_writelane_b32 v13, s44, 0\n\tv_writelane_b32 v13, s45, 1\n\ts_mov_b32 s44, 0x70\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v13, s44, 2\n\tv_writelane_b32 v13, s45, 3\n\tv_writelane_b32 v13, s44, 4\n\tv_writelane_b32 v13, s45, 5\n\ts_mov_b32 s44, 0x78\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v13, s44, 6\n\tv_writelane_b32 v13, s45, 7\n\ts_mov_b32 s44, 0x80\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v13, s44, 8\n\tv_writelane_b32 v13, s45, 9\n\ts_mov_b32 s44, 0x88\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v13, s44, 10\n\tv_writelane_b32 v13, s45, 11\n\ts_mov_b32 s44, 0x90\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v13, s44, 12\n\tv_writelane_b32 v13, s45, 13\n\ts_mov_b32 s44, 0x98\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v13, s44, 14\n\tv_writelane_b32 v13, s45, 15\n\ts_mov_b32 s44, 0xa0\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v13, s44, 16\n\tv_writelane_b32 v13, s45, 17\n\ts_mov_b32 s44, 0xa8\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v13, s44, 18\n\tv_writelane_b32 v13, s45, 19\n\ts_mov_b32 s44, 0xb0\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v13, s44, 20\n\tv_writelane_b32 v13, s45, 21\n\ts_mov_b32 s44, 0xb8\n ; kill: def $sgpr44 killed $sgpr44 def $sgpr44_sgpr45\n\ts_mov_b32 s45, s21\n\tv_writelane_b32 v13, s44, 22\n\tv_writelane_b32 v13, s45, 23\n\tv_mov_b32_e32 v0, s40\n\tv_mov_b32_e32 v1, s41\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v2, s42\n\tv_mov_b32_e32 v3, s43\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s40\n\tv_mov_b32_e32 v1, s41\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s36\n\tv_mov_b32_e32 v1, s37\n\tv_mov_b32_e32 v2, s38\n\tv_mov_b32_e32 v3, s39\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s36\n\tv_mov_b32_e32 v1, s37\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s30\n\tv_mov_b32_e32 v1, s31\n\tv_mov_b32_e32 v2, s34\n\tv_mov_b32_e32 v3, s35\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s30\n\tv_mov_b32_e32 v1, s31\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s28\n\tv_mov_b32_e32 v1, s29\n\ts_waitcnt vmcnt(2) lgkmcnt(4)\n\tflat_store_b64 v[0:1], v[6:7]\n\tv_mov_b32_e32 v0, s26\n\tv_mov_b32_e32 v1, s27\n\ts_waitcnt vmcnt(1) lgkmcnt(3)\n\tflat_store_b64 v[0:1], v[4:5]\n\tv_mov_b32_e32 v0, s24\n\tv_mov_b32_e32 v1, s25\n\ts_waitcnt vmcnt(0) lgkmcnt(2)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s22\n\tv_mov_b32_e32 v1, s23\n\tv_mov_b32_e32 v2, s20\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tv_mov_b32_e32 v2, s15\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tv_mov_b32_e32 v2, s8\n\tv_mov_b32_e32 v3, s9\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b64 s[6:7], 48\n\ts_mov_b32 s2, s0\n\ts_mov_b32 s0, s1\n\ts_mov_b32 s3, s6\n\ts_mov_b32 s1, s7\n\ts_add_u32 s8, s2, s3\n\ts_addc_u32 s0, s0, s1\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s0\n\tv_writelane_b32 v13, s8, 24\n\tv_writelane_b32 v13, s9, 25\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_group_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_group_id@rel32@hi+12\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, off offset:200 ; 4-byte Folded Spill\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:212 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v12, 0\n\tv_readlane_b32 s13, v12, 1\n\tv_readlane_b32 s12, v12, 2\n\tv_readlane_b32 s10, v12, 3\n\tv_readlane_b32 s11, v12, 4\n\tv_readlane_b32 s8, v13, 24\n\tv_readlane_b32 s9, v13, 25\n\tv_readlane_b32 s4, v12, 7\n\tv_readlane_b32 s5, v12, 8\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:200 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:216 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:216 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v1, off offset:204 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_size@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_size@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:212 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v12, 0\n\tv_readlane_b32 s13, v12, 1\n\tv_readlane_b32 s12, v12, 2\n\tv_readlane_b32 s10, v12, 3\n\tv_readlane_b32 s11, v12, 4\n\tv_readlane_b32 s4, v12, 7\n\tv_readlane_b32 s5, v12, 8\n\tv_readlane_b32 s8, v13, 24\n\tv_readlane_b32 s9, v13, 25\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:200 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:208 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:208 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v1\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_id@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s8, v12, 26\n\tv_readlane_b32 s9, v12, 27\n\tv_readlane_b32 s6, v12, 18\n\tv_readlane_b32 s7, v12, 19\n\tv_readlane_b32 s2, v13, 2\n\tv_readlane_b32 s3, v13, 3\n\tv_readlane_b32 s0, v12, 30\n\tv_readlane_b32 s1, v12, 31\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:204 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v5, v1\n\tscratch_load_b32 v1, off, off offset:200 ; 4-byte Folded Reload\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v5\n\tv_mov_b32_e32 v5, v2\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr5\n ; implicit-def: $sgpr5\n\tv_mov_b32_e32 v2, s4\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v2\n\ts_waitcnt vmcnt(1)\n\tv_mad_u64_u32 v[2:3], s4, v0, v4, v[5:6]\n\tv_mov_b32_e32 v0, v2\n\tv_mov_b32_e32 v2, s8\n\tv_mov_b32_e32 v3, s9\n\tflat_store_b32 v[2:3], v0\n\tv_mov_b32_e32 v2, s8\n\tv_mov_b32_e32 v3, s9\n\tflat_load_b32 v0, v[2:3]\n\tv_mov_b32_e32 v2, s6\n\tv_mov_b32_e32 v3, s7\n\tflat_load_b32 v2, v[2:3]\n\ts_mov_b32 s4, 31\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v3, s4, v2\n\tv_add_nc_u32_e64 v2, v2, v3\n\tv_xor_b32_e64 v3, v2, v3\n\tv_sub_nc_u32_e64 v4, v1, v3\n\tv_cvt_f32_u32_e32 v2, v3\n\tv_rcp_iflag_f32_e32 v2, v2\n\ts_waitcnt_depctr 0xfff\n\tv_mul_f32_e32 v2, 0x4f7ffffe, v2\n\tv_cvt_u32_f32_e32 v2, v2\n\tv_mul_lo_u32 v4, v4, v2\n\tv_mul_hi_u32 v4, v2, v4\n\tv_add_nc_u32_e64 v4, v2, v4\n\tv_ashrrev_i32_e64 v2, s4, v0\n\tv_add_nc_u32_e64 v0, v0, v2\n\tv_xor_b32_e64 v0, v0, v2\n\tv_mul_hi_u32 v4, v0, v4\n\tv_mul_lo_u32 v4, v4, v3\n\tv_sub_nc_u32_e64 v0, v0, v4\n\tv_cmp_ge_u32_e64 s5, v0, v3\n\tv_sub_nc_u32_e64 v4, v0, v3\n\tv_cndmask_b32_e64 v0, v0, v4, s5\n\tv_cmp_ge_u32_e64 s5, v0, v3\n\tv_sub_nc_u32_e64 v3, v0, v3\n\tv_cndmask_b32_e64 v0, v0, v3, s5\n\tv_xor_b32_e64 v0, v0, v2\n\tv_sub_nc_u32_e64 v0, v0, v2\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b32 v[2:3], v0\n\tv_mov_b32_e32 v2, s8\n\tv_mov_b32_e32 v3, s9\n\tflat_load_b32 v4, v[2:3]\n\tv_mov_b32_e32 v2, s6\n\tv_mov_b32_e32 v3, s7\n\tflat_load_b32 v0, v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v3, s4, v0\n\tv_add_nc_u32_e64 v0, v0, v3\n\tv_xor_b32_e64 v5, v0, v3\n\tv_sub_nc_u32_e64 v2, v1, v5\n\tv_cvt_f32_u32_e32 v0, v5\n\tv_rcp_iflag_f32_e32 v0, v0\n\ts_waitcnt_depctr 0xfff\n\tv_mul_f32_e32 v0, 0x4f7ffffe, v0\n\tv_cvt_u32_f32_e32 v0, v0\n\tv_mul_lo_u32 v2, v2, v0\n\tv_mul_hi_u32 v2, v0, v2\n\tv_add_nc_u32_e64 v0, v0, v2\n\tv_ashrrev_i32_e64 v2, s4, v4\n\tv_add_nc_u32_e64 v4, v4, v2\n\tv_xor_b32_e64 v4, v4, v2\n\tv_mul_hi_u32 v0, v4, v0\n\tv_mul_lo_u32 v6, v0, v5\n\tv_sub_nc_u32_e64 v4, v4, v6\n\tv_cmp_ge_u32_e64 s6, v4, v5\n\tv_sub_nc_u32_e64 v6, v4, v5\n\tv_cndmask_b32_e64 v4, v4, v6, s6\n\tv_cmp_ge_u32_e64 s4, v4, v5\n\ts_mov_b32 s5, 1\n\tv_add_nc_u32_e64 v4, v0, s5\n\tv_cndmask_b32_e64 v0, v0, v4, s6\n\tv_add_nc_u32_e64 v4, v0, s5\n\tv_cndmask_b32_e64 v0, v0, v4, s4\n\tv_xor_b32_e64 v2, v2, v3\n\tv_xor_b32_e64 v0, v0, v2\n\tv_sub_nc_u32_e64 v0, v0, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b32 v[2:3], v0\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_load_b32 v0, v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_gt_i32_e64 s1, v0, v1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v13, s0, 26\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v13, off offset:192 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB16_8\n; %bb.1:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v12, off, off offset:196 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v13, off, off offset:192 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v12, 20\n\tv_readlane_b32 s1, v12, 21\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v13, 0\n\tv_readlane_b32 s3, v13, 1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v2, s1\n\tv_mov_b32_e32 v1, s0\n\tflat_load_b32 v1, v[1:2]\n\ts_mov_b32 s0, -1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v1, v1, s0\n\tv_cmp_lt_i32_e64 s1, v0, v1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v13, s0, 27\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v13, off offset:192 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB16_7\n; %bb.2:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v13, off, off offset:192 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v13, 4\n\tv_readlane_b32 s1, v13, 5\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v0, v[0:1]\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_gt_i32_e64 s1, v0, s0\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v13, s0, 28\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v13, off offset:192 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB16_6\n; %bb.3:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v12, off, off offset:196 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v13, off, off offset:192 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v12, 16\n\tv_readlane_b32 s1, v12, 17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v13, 4\n\tv_readlane_b32 s3, v13, 5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v2, s1\n\tv_mov_b32_e32 v1, s0\n\tflat_load_b32 v1, v[1:2]\n\ts_mov_b32 s0, -1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v1, v1, s0\n\tv_cmp_lt_i32_e64 s1, v0, v1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v13, s0, 29\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v13, off offset:192 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB16_5\n; %bb.4:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v12, off, off offset:192 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v13, off, off offset:196 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v13, 28\n\tv_readlane_b32 s3, v13, 29\n\tv_readlane_b32 s4, v13, 12\n\tv_readlane_b32 s5, v13, 13\n\tv_readlane_b32 s8, v13, 24\n\tv_readlane_b32 s9, v13, 25\n\tv_readlane_b32 s10, v12, 22\n\tv_readlane_b32 s11, v12, 23\n\tv_readlane_b32 s12, v12, 20\n\tv_readlane_b32 s13, v12, 21\n\tv_readlane_b32 s14, v13, 10\n\tv_readlane_b32 s15, v13, 11\n\tv_readlane_b32 s6, v13, 22\n\tv_readlane_b32 s7, v13, 23\n\tv_readlane_b32 s16, v12, 18\n\tv_readlane_b32 s17, v12, 19\n\tv_readlane_b32 s18, v12, 16\n\tv_readlane_b32 s19, v12, 17\n\tv_readlane_b32 s22, v12, 14\n\tv_readlane_b32 s23, v12, 15\n\tv_readlane_b32 s24, v12, 12\n\tv_readlane_b32 s25, v12, 13\n\tv_readlane_b32 s26, v12, 10\n\tv_readlane_b32 s27, v12, 11\n\tv_readlane_b32 s28, v12, 8\n\tv_readlane_b32 s29, v12, 9\n\tv_readlane_b32 s20, v12, 6\n\tv_readlane_b32 s21, v12, 7\n\tv_readlane_b32 s30, v13, 14\n\tv_readlane_b32 s31, v13, 15\n\tv_readlane_b32 s34, v13, 20\n\tv_readlane_b32 s35, v13, 21\n\tv_mov_b32_e32 v0, s30\n\tv_mov_b32_e32 v1, s31\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v2, 31, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\ts_mov_b32 s0, 3\n\tv_lshlrev_b64 v[1:2], s0, v[0:1]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1] offset:8\n\tv_mov_b32_e32 v0, s20\n\tv_mov_b32_e32 v1, s21\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s30\n\tv_mov_b32_e32 v1, s31\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v0, v[3:4]\n\ts_mov_b32 s1, -1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v3, v0, s1\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s28\n\tv_mov_b32_e32 v1, s29\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s30\n\tv_mov_b32_e32 v1, s31\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v0, v[3:4]\n\tv_mov_b32_e32 v3, s34\n\tv_mov_b32_e32 v4, s35\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v3, v0, v3\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s26\n\tv_mov_b32_e32 v1, s27\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s30\n\tv_mov_b32_e32 v1, s31\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v0, v[3:4]\n\tv_mov_b32_e32 v3, s34\n\tv_mov_b32_e32 v4, s35\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v3, v0, v3\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s24\n\tv_mov_b32_e32 v1, s25\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s30\n\tv_mov_b32_e32 v1, s31\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s1, v0, v3\n\tv_add_co_ci_u32_e64 v2, s1, v1, v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s22\n\tv_mov_b32_e32 v1, s23\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s20\n\tv_mov_b32_e32 v1, s21\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s22\n\tv_mov_b32_e32 v3, s23\n\tflat_load_b64 v[2:3], v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[0:1], v[0:1], v[2:3]\n\ts_mov_b64 s[20:21], 0.5\n\tv_mul_f64 v[2:3], v[0:1], s[20:21]\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s28\n\tv_mov_b32_e32 v1, s29\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s22\n\tv_mov_b32_e32 v3, s23\n\tflat_load_b64 v[2:3], v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[0:1], v[0:1], v[2:3]\n\tv_mul_f64 v[2:3], v[0:1], s[20:21]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s26\n\tv_mov_b32_e32 v1, s27\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s22\n\tv_mov_b32_e32 v3, s23\n\tflat_load_b64 v[2:3], v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[0:1], v[0:1], v[2:3]\n\tv_mul_f64 v[2:3], v[0:1], s[20:21]\n\tv_mov_b32_e32 v0, s12\n\tv_mov_b32_e32 v1, s13\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s24\n\tv_mov_b32_e32 v1, s25\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s22\n\tv_mov_b32_e32 v3, s23\n\tflat_load_b64 v[2:3], v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[0:1], v[0:1], v[2:3]\n\tv_mul_f64 v[2:3], v[0:1], s[20:21]\n\tv_mov_b32_e32 v0, s10\n\tv_mov_b32_e32 v1, s11\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s16\n\tv_mov_b32_e32 v3, s17\n\tflat_load_b64 v[2:3], v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[4:5], v[0:1], -v[2:3]\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tflat_load_b64 v[2:3], v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_div_scale_f64 v[0:1], s1, v[2:3], v[2:3], v[4:5]\n\tv_rcp_f64_e64 v[6:7], v[0:1]\n\ts_mov_b64 s[6:7], 1.0\n\ts_waitcnt_depctr 0xfff\n\tv_fma_f64 v[8:9], -v[0:1], v[6:7], s[6:7]\n\tv_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]\n\tv_fma_f64 v[8:9], -v[0:1], v[6:7], s[6:7]\n\tv_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]\n\tv_div_scale_f64 v[10:11], vcc_lo, v[4:5], v[2:3], v[4:5]\n\tv_mul_f64 v[8:9], v[10:11], v[6:7]\n\tv_fma_f64 v[0:1], -v[0:1], v[8:9], v[10:11]\n\tv_div_fmas_f64 v[0:1], v[0:1], v[6:7], v[8:9]\n\tv_div_fixup_f64 v[2:3], v[0:1], v[2:3], v[4:5]\n\tv_mov_b32_e32 v0, s14\n\tv_mov_b32_e32 v1, s15\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v4, 31, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_lshlrev_b64 v[6:7], s0, v[0:1]\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v1, v9\n\tv_mov_b32_e32 v4, v7\n\tv_add_co_u32 v0, s1, v0, v5\n\tv_add_co_ci_u32_e64 v4, s1, v1, v4, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s12\n\tv_mov_b32_e32 v1, s13\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s10\n\tv_mov_b32_e32 v3, s11\n\tflat_load_b64 v[2:3], v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f64 v[4:5], v[0:1], -v[2:3]\n\tv_mov_b32_e32 v0, s8\n\tv_mov_b32_e32 v1, s9\n\tflat_load_b64 v[2:3], v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_div_scale_f64 v[0:1], s1, v[2:3], v[2:3], v[4:5]\n\tv_rcp_f64_e64 v[6:7], v[0:1]\n\ts_waitcnt_depctr 0xfff\n\tv_fma_f64 v[8:9], -v[0:1], v[6:7], s[6:7]\n\tv_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]\n\tv_fma_f64 v[8:9], -v[0:1], v[6:7], s[6:7]\n\tv_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]\n\tv_div_scale_f64 v[10:11], vcc_lo, v[4:5], v[2:3], v[4:5]\n\tv_mul_f64 v[8:9], v[10:11], v[6:7]\n\tv_fma_f64 v[0:1], -v[0:1], v[8:9], v[10:11]\n\tv_div_fmas_f64 v[0:1], v[0:1], v[6:7], v[8:9]\n\tv_div_fixup_f64 v[2:3], v[0:1], v[2:3], v[4:5]\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v4, 31, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_lshlrev_b64 v[6:7], s0, v[0:1]\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v1, v9\n\tv_mov_b32_e32 v4, v7\n\tv_add_co_u32 v0, s0, v0, v5\n\tv_add_co_ci_u32_e64 v4, s0, v1, v4, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_store_b64 v[0:1], v[2:3]\n.LBB16_5:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v13, off, off offset:192 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v13, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB16_6:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v13, off, off offset:192 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v13, 28\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB16_7:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v13, off, off offset:192 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v13, 27\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB16_8:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v13, off, off offset:192 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v13, 26\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z11gradientGPUPdS_S_iidd\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 336\n\t\t.amdhsa_kernarg_size 304\n\t\t.amdhsa_user_sgpr_count 13\n\t\t.amdhsa_user_sgpr_dispatch_ptr 1\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 1\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 1\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 1\n\t\t.amdhsa_system_sgpr_workgroup_id_z 1\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 2\n\t\t.amdhsa_next_free_vgpr 32\n\t\t.amdhsa_next_free_sgpr 46\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end16:\n\t.size\t_Z11gradientGPUPdS_S_iidd, .Lfunc_end16-_Z11gradientGPUPdS_S_iidd\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 4580\n; NumSgprs: 48\n; NumVgprs: 32\n; ScratchSize: 336\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 5\n; VGPRBlocks: 3\n; NumSGPRsForWavesPerEU: 48\n; NumVGPRsForWavesPerEU: 32\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1\n; COMPUTE_PGM_RSRC2:USER_SGPR: 13\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__const.__assert_fail.fmt,@object ; @__const.__assert_fail.fmt\n\t.section\t.rodata.str1.16,\"aMS\",@progbits,1\n\t.p2align\t4, 0x0\n__const.__assert_fail.fmt:\n\t.asciz\t\"%s:%u: %s: Device-side assertion `%s' failed.\\n\"\n\t.size\t__const.__assert_fail.fmt, 47\n\n\t.protected\tblockIdx\n\t.protected\tblockDim\n\t.protected\tthreadIdx\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.hidden\t__oclc_ABI_version ; @__oclc_ABI_version\n\t.type\t__oclc_ABI_version,@object\n\t.section\t.rodata,\"a\",@progbits\n\t.weak\t__oclc_ABI_version\n\t.p2align\t2, 0x0\n__oclc_ABI_version:\n\t.long\t500 ; 0x1f4\n\t.size\t__oclc_ABI_version, 4\n\n\t.weak\tblockIdx\n\t.weak\tblockDim\n\t.weak\tthreadIdx\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 16\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 24\n .size: 8\n .value_kind: global_buffer\n - .offset: 32\n .size: 4\n .value_kind: by_value\n - .offset: 36\n .size: 4\n .value_kind: by_value\n - .offset: 40\n .size: 8\n .value_kind: by_value\n - .offset: 48\n .size: 8\n .value_kind: by_value\n - .offset: 56\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 60\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 64\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 68\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 70\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 72\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 74\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 76\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 78\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 96\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 104\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 112\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 120\n .size: 2\n .value_kind: hidden_grid_dims\n - .offset: 136\n .size: 8\n .value_kind: hidden_hostcall_buffer\n - .offset: 144\n .size: 8\n .value_kind: hidden_multigrid_sync_arg\n - .offset: 152\n .size: 8\n .value_kind: hidden_heap_v1\n - .offset: 160\n .size: 8\n .value_kind: hidden_default_queue\n - .offset: 256\n .size: 8\n .value_kind: hidden_queue_ptr\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 312\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z6DivGPUPdS_S_S_iidd\n .private_segment_fixed_size: 400\n .sgpr_count: 55\n .sgpr_spill_count: 77\n .symbol: _Z6DivGPUPdS_S_S_iidd.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 32\n .vgpr_spill_count: 12\n .wavefront_size: 32\n .workgroup_processor_mode: 1\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 16\n .size: 8\n .value_kind: global_buffer\n - .offset: 24\n .size: 4\n .value_kind: by_value\n - .offset: 28\n .size: 4\n .value_kind: by_value\n - .offset: 32\n .size: 8\n .value_kind: by_value\n - .offset: 40\n .size: 8\n .value_kind: by_value\n - .offset: 48\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 52\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 56\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 60\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 62\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 64\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 66\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 68\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 70\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 88\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 96\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 104\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 112\n .size: 2\n .value_kind: hidden_grid_dims\n - .offset: 128\n .size: 8\n .value_kind: hidden_hostcall_buffer\n - .offset: 136\n .size: 8\n .value_kind: hidden_multigrid_sync_arg\n - .offset: 144\n .size: 8\n .value_kind: hidden_heap_v1\n - .offset: 152\n .size: 8\n .value_kind: hidden_default_queue\n - .offset: 248\n .size: 8\n .value_kind: hidden_queue_ptr\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 304\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z13DivergenceGPUPdS_S_iidd\n .private_segment_fixed_size: 352\n .sgpr_count: 48\n .sgpr_spill_count: 64\n .symbol: _Z13DivergenceGPUPdS_S_iidd.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 32\n .vgpr_spill_count: 10\n .wavefront_size: 32\n .workgroup_processor_mode: 1\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .offset: 16\n .size: 4\n .value_kind: by_value\n - .offset: 20\n .size: 4\n .value_kind: by_value\n - .offset: 24\n .size: 8\n .value_kind: by_value\n - .offset: 32\n .size: 8\n .value_kind: by_value\n - .offset: 40\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 44\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 48\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 52\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 54\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 56\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 58\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 60\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 62\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 80\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 88\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 96\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 104\n .size: 2\n .value_kind: hidden_grid_dims\n - .offset: 120\n .size: 8\n .value_kind: hidden_hostcall_buffer\n - .offset: 128\n .size: 8\n .value_kind: hidden_multigrid_sync_arg\n - .offset: 136\n .size: 8\n .value_kind: hidden_heap_v1\n - .offset: 144\n .size: 8\n .value_kind: hidden_default_queue\n - .offset: 240\n .size: 8\n .value_kind: hidden_queue_ptr\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 296\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z12LaplacianGPUPdS_iidd\n .private_segment_fixed_size: 320\n .sgpr_count: 42\n .sgpr_spill_count: 62\n .symbol: _Z12LaplacianGPUPdS_iidd.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 32\n .vgpr_spill_count: 11\n .wavefront_size: 32\n .workgroup_processor_mode: 1\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 16\n .size: 8\n .value_kind: global_buffer\n - .offset: 24\n .size: 4\n .value_kind: by_value\n - .offset: 28\n .size: 4\n .value_kind: by_value\n - .offset: 32\n .size: 8\n .value_kind: by_value\n - .offset: 40\n .size: 8\n .value_kind: by_value\n - .offset: 48\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 52\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 56\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 60\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 62\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 64\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 66\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 68\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 70\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 88\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 96\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 104\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 112\n .size: 2\n .value_kind: hidden_grid_dims\n - .offset: 128\n .size: 8\n .value_kind: hidden_hostcall_buffer\n - .offset: 136\n .size: 8\n .value_kind: hidden_multigrid_sync_arg\n - .offset: 144\n .size: 8\n .value_kind: hidden_heap_v1\n - .offset: 152\n .size: 8\n .value_kind: hidden_default_queue\n - .offset: 248\n .size: 8\n .value_kind: hidden_queue_ptr\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 304\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z11gradientGPUPdS_S_iidd\n .private_segment_fixed_size: 336\n .sgpr_count: 48\n .sgpr_spill_count: 62\n .symbol: _Z11gradientGPUPdS_S_iidd.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 32\n .vgpr_spill_count: 10\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162586,"cells":{"id":{"kind":"string","value":"e4e666b66140ce5824c0f0ad31e7e61cd20c2b16_O0"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z12nbody_kernelP8Particlei --------------------------\n .section .text._Z12nbody_kernelP8Particlei,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=28\"\n .align 128\n\n\n\n\n .global _Z12nbody_kernelP8Particlei\n .type _Z12nbody_kernelP8Particlei,@function\n .size _Z12nbody_kernelP8Particlei,(.L_x_18 - _Z12nbody_kernelP8Particlei)\n .other _Z12nbody_kernelP8Particlei,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z12nbody_kernelP8Particlei:\n.text._Z12nbody_kernelP8Particlei:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ MOV R18, c[0x0][0x118] ;\n /*0020*/ MOV R19, c[0x0][0x11c] ;\n /*0030*/ MOV R2, RZ ;\n /*0040*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0050*/ MOV R12, R2 ;\n /*0060*/ MOV R11, R3 ;\n /*0070*/ MOV R12, R12 ;\n /*0080*/ MOV R11, R11 ;\n /*0090*/ MOV R0, 0x8 ;\n /*00a0*/ LDC R0, c[0x0][R0+0x160] ;\n /*00b0*/ MOV R0, R0 ;\n /*00c0*/ MOV R12, R12 ;\n /*00d0*/ MOV R11, R11 ;\n /*00e0*/ MOV R2, c[0x0][0x0] ;\n /*00f0*/ S2R R3, SR_CTAID.X ;\n /*0100*/ MOV R3, R3 ;\n /*0110*/ S2R R4, SR_TID.X ;\n /*0120*/ MOV R4, R4 ;\n /*0130*/ IMAD R2, R3, R2, R4 ;\n /*0140*/ ISETP.GE.AND P0, PT, R2, R0, PT ;\n /*0150*/ MOV R13, R0 ;\n /*0160*/ MOV R12, R12 ;\n /*0170*/ MOV R11, R11 ;\n /*0180*/ MOV R17, R2 ;\n /*0190*/ @P0 BRA `(.L_x_0) ;\n /*01a0*/ IMAD.WIDE R2, R17, 0x20, RZ ;\n /*01b0*/ MOV R10, R2 ;\n /*01c0*/ MOV R9, R3 ;\n /*01d0*/ IADD3 R10, P0, R12, R10, RZ ;\n /*01e0*/ IADD3.X R9, R11, R9, RZ, P0, !PT ;\n /*01f0*/ MOV R4, R10 ;\n /*0200*/ MOV R5, R9 ;\n /*0210*/ MOV R4, R4 ;\n /*0220*/ MOV R5, R5 ;\n /*0230*/ R2UR UR4, R18 ;\n /*0240*/ R2UR UR5, R19 ;\n /*0250*/ LDG.E.128 R4, [R4.64] ;\n /*0260*/ MOV R4, R4 ;\n /*0270*/ MOV R3, R5 ;\n /*0280*/ MOV R2, R6 ;\n /*0290*/ MOV R0, RZ ;\n /*02a0*/ ISETP.LT.AND P0, PT, R17, 0x1, PT ;\n /*02b0*/ MOV R14, RZ ;\n /*02c0*/ MOV R15, R14 ;\n /*02d0*/ MOV R16, R14 ;\n /*02e0*/ MOV R10, R10 ;\n /*02f0*/ MOV R9, R9 ;\n /*0300*/ MOV R8, R4 ;\n /*0310*/ MOV R3, R3 ;\n /*0320*/ MOV R2, R2 ;\n /*0330*/ MOV R0, R0 ;\n /*0340*/ MOV R14, R14 ;\n /*0350*/ MOV R15, R15 ;\n /*0360*/ MOV R16, R16 ;\n /*0370*/ BSSY B0, `(.L_x_1) ;\n /*0380*/ @P0 BRA `(.L_x_2) ;\n /*0390*/ IADD3 R0, R17, -0x1, RZ ;\n /*03a0*/ LOP3.LUT R20, R17, 0x3, RZ, 0xc0, !PT ;\n /*03b0*/ ISETP.LT.U32.AND P0, PT, R0, 0x3, PT ;\n /*03c0*/ MOV R16, RZ ;\n /*03d0*/ MOV R0, RZ ;\n /*03e0*/ MOV R15, R16 ;\n /*03f0*/ MOV R14, R16 ;\n /*0400*/ MOV R20, R20 ;\n /*0410*/ MOV R16, R16 ;\n /*0420*/ MOV R0, R0 ;\n /*0430*/ MOV R15, R15 ;\n /*0440*/ MOV R14, R14 ;\n /*0450*/ BSSY B1, `(.L_x_3) ;\n /*0460*/ @P0 BRA `(.L_x_4) ;\n /*0470*/ IADD3 R21, R17, -R20, RZ ;\n /*0480*/ MOV R16, RZ ;\n /*0490*/ MOV R0, RZ ;\n /*04a0*/ MOV R21, R21 ;\n /*04b0*/ MOV R16, R16 ;\n /*04c0*/ MOV R0, R0 ;\n.L_x_5:\n /*04d0*/ IMAD.WIDE R4, R0, 0x20, RZ ;\n /*04e0*/ MOV R23, R4 ;\n /*04f0*/ MOV R22, R5 ;\n /*0500*/ IADD3 R23, P0, R12, R23, RZ ;\n /*0510*/ IADD3.X R22, R11, R22, RZ, P0, !PT ;\n /*0520*/ MOV R4, R23 ;\n /*0530*/ MOV R5, R22 ;\n /*0540*/ MOV R4, R4 ;\n /*0550*/ MOV R5, R5 ;\n /*0560*/ R2UR UR4, R18 ;\n /*0570*/ R2UR UR5, R19 ;\n /*0580*/ LDG.E.128 R4, [R4.64] ;\n /*0590*/ MOV R4, R4 ;\n /*05a0*/ MOV R5, R5 ;\n /*05b0*/ MOV R6, R6 ;\n /*05c0*/ FADD R4, R4, -R8 ;\n /*05d0*/ FADD R5, R5, -R3 ;\n /*05e0*/ FADD R7, R6, -R2 ;\n /*05f0*/ FMUL R6, R5, R5 ;\n /*0600*/ FFMA R6, R4, R4, R6 ;\n /*0610*/ FFMA R6, R7, R7, R6 ;\n /*0620*/ FADD R6, R6, 9.9999990510468705907e-09 ;\n /*0630*/ MOV R24, R6 ;\n /*0640*/ MOV R23, R23 ;\n /*0650*/ MOV R22, R22 ;\n /*0660*/ MOV R6, R4 ;\n /*0670*/ MOV R5, R5 ;\n /*0680*/ MOV R4, R7 ;\n /*0690*/ MOV R24, R24 ;\n /*06a0*/ MOV R24, R24 ;\n /*06b0*/ MOV R24, R24 ;\n /*06c0*/ FADD R7, -RZ, |R24| ;\n /*06d0*/ MOV R7, R7 ;\n /*06e0*/ MOV R25, 0x800000 ;\n /*06f0*/ FSETP.LT.AND P0, PT, R7, R25, PT ;\n /*0700*/ MOV R7, 0x4b800000 ;\n /*0710*/ FMUL R7, R24, R7 ;\n /*0720*/ FSEL R7, R7, R24, P0 ;\n /*0730*/ MUFU.RSQ R7, R7 ;\n /*0740*/ MOV R7, R7 ;\n /*0750*/ MOV R24, 0x45800000 ;\n /*0760*/ FMUL R24, R7, R24 ;\n /*0770*/ FSEL R24, R24, R7, P0 ;\n /*0780*/ MOV R24, R24 ;\n /*0790*/ MOV R24, R24 ;\n /*07a0*/ FMUL R7, R24, R24 ;\n /*07b0*/ FMUL R7, R24, R7 ;\n /*07c0*/ FMUL R7, R7, 6.6743000015634379452e-11 ;\n /*07d0*/ FFMA R14, R6, R7, R14 ;\n /*07e0*/ FFMA R15, R5, R7, R15 ;\n /*07f0*/ FFMA R16, R4, R7, R16 ;\n /*0800*/ IADD3 R4, P0, R23, 0x20, RZ ;\n /*0810*/ IADD3.X R5, R22, RZ, RZ, P0, !PT ;\n /*0820*/ MOV R4, R4 ;\n /*0830*/ MOV R5, R5 ;\n /*0840*/ MOV R4, R4 ;\n /*0850*/ MOV R5, R5 ;\n /*0860*/ R2UR UR4, R18 ;\n /*0870*/ R2UR UR5, R19 ;\n /*0880*/ LDG.E.128 R4, [R4.64] ;\n /*0890*/ MOV R4, R4 ;\n /*08a0*/ MOV R5, R5 ;\n /*08b0*/ MOV R6, R6 ;\n /*08c0*/ FADD R4, R4, -R8 ;\n /*08d0*/ FADD R5, R5, -R3 ;\n /*08e0*/ FADD R7, R6, -R2 ;\n /*08f0*/ FMUL R6, R5, R5 ;\n /*0900*/ FFMA R6, R4, R4, R6 ;\n /*0910*/ FFMA R6, R7, R7, R6 ;\n /*0920*/ FADD R6, R6, 9.9999990510468705907e-09 ;\n /*0930*/ MOV R24, R6 ;\n /*0940*/ MOV R14, R14 ;\n /*0950*/ MOV R15, R15 ;\n /*0960*/ MOV R16, R16 ;\n /*0970*/ MOV R6, R4 ;\n /*0980*/ MOV R5, R5 ;\n /*0990*/ MOV R4, R7 ;\n /*09a0*/ MOV R24, R24 ;\n /*09b0*/ MOV R24, R24 ;\n /*09c0*/ MOV R24, R24 ;\n /*09d0*/ FADD R7, -RZ, |R24| ;\n /*09e0*/ MOV R7, R7 ;\n /*09f0*/ MOV R25, 0x800000 ;\n /*0a00*/ FSETP.LT.AND P0, PT, R7, R25, PT ;\n /*0a10*/ MOV R7, 0x4b800000 ;\n /*0a20*/ FMUL R7, R24, R7 ;\n /*0a30*/ FSEL R7, R7, R24, P0 ;\n /*0a40*/ MUFU.RSQ R7, R7 ;\n /*0a50*/ MOV R7, R7 ;\n /*0a60*/ MOV R24, 0x45800000 ;\n /*0a70*/ FMUL R24, R7, R24 ;\n /*0a80*/ FSEL R24, R24, R7, P0 ;\n /*0a90*/ MOV R24, R24 ;\n /*0aa0*/ MOV R24, R24 ;\n /*0ab0*/ FMUL R7, R24, R24 ;\n /*0ac0*/ FMUL R7, R24, R7 ;\n /*0ad0*/ FMUL R7, R7, 6.6743000015634379452e-11 ;\n /*0ae0*/ FFMA R14, R6, R7, R14 ;\n /*0af0*/ FFMA R15, R5, R7, R15 ;\n /*0b00*/ FFMA R16, R4, R7, R16 ;\n /*0b10*/ IADD3 R4, P0, R23, 0x40, RZ ;\n /*0b20*/ IADD3.X R5, R22, RZ, RZ, P0, !PT ;\n /*0b30*/ MOV R4, R4 ;\n /*0b40*/ MOV R5, R5 ;\n /*0b50*/ MOV R4, R4 ;\n /*0b60*/ MOV R5, R5 ;\n /*0b70*/ R2UR UR4, R18 ;\n /*0b80*/ R2UR UR5, R19 ;\n /*0b90*/ LDG.E.128 R4, [R4.64] ;\n /*0ba0*/ MOV R4, R4 ;\n /*0bb0*/ MOV R5, R5 ;\n /*0bc0*/ MOV R6, R6 ;\n /*0bd0*/ FADD R4, R4, -R8 ;\n /*0be0*/ FADD R5, R5, -R3 ;\n /*0bf0*/ FADD R7, R6, -R2 ;\n /*0c00*/ FMUL R6, R5, R5 ;\n /*0c10*/ FFMA R6, R4, R4, R6 ;\n /*0c20*/ FFMA R6, R7, R7, R6 ;\n /*0c30*/ FADD R6, R6, 9.9999990510468705907e-09 ;\n /*0c40*/ MOV R24, R6 ;\n /*0c50*/ MOV R14, R14 ;\n /*0c60*/ MOV R15, R15 ;\n /*0c70*/ MOV R16, R16 ;\n /*0c80*/ MOV R6, R4 ;\n /*0c90*/ MOV R5, R5 ;\n /*0ca0*/ MOV R4, R7 ;\n /*0cb0*/ MOV R24, R24 ;\n /*0cc0*/ MOV R24, R24 ;\n /*0cd0*/ MOV R24, R24 ;\n /*0ce0*/ FADD R7, -RZ, |R24| ;\n /*0cf0*/ MOV R7, R7 ;\n /*0d00*/ MOV R25, 0x800000 ;\n /*0d10*/ FSETP.LT.AND P0, PT, R7, R25, PT ;\n /*0d20*/ MOV R7, 0x4b800000 ;\n /*0d30*/ FMUL R7, R24, R7 ;\n /*0d40*/ FSEL R7, R7, R24, P0 ;\n /*0d50*/ MUFU.RSQ R7, R7 ;\n /*0d60*/ MOV R7, R7 ;\n /*0d70*/ MOV R24, 0x45800000 ;\n /*0d80*/ FMUL R24, R7, R24 ;\n /*0d90*/ FSEL R24, R24, R7, P0 ;\n /*0da0*/ MOV R24, R24 ;\n /*0db0*/ MOV R24, R24 ;\n /*0dc0*/ FMUL R7, R24, R24 ;\n /*0dd0*/ FMUL R7, R24, R7 ;\n /*0de0*/ FMUL R7, R7, 6.6743000015634379452e-11 ;\n /*0df0*/ FFMA R14, R6, R7, R14 ;\n /*0e00*/ FFMA R15, R5, R7, R15 ;\n /*0e10*/ FFMA R16, R4, R7, R16 ;\n /*0e20*/ IADD3 R4, P0, R23, 0x60, RZ ;\n /*0e30*/ IADD3.X R5, R22, RZ, RZ, P0, !PT ;\n /*0e40*/ MOV R4, R4 ;\n /*0e50*/ MOV R5, R5 ;\n /*0e60*/ MOV R4, R4 ;\n /*0e70*/ MOV R5, R5 ;\n /*0e80*/ R2UR UR4, R18 ;\n /*0e90*/ R2UR UR5, R19 ;\n /*0ea0*/ LDG.E.128 R4, [R4.64] ;\n /*0eb0*/ MOV R4, R4 ;\n /*0ec0*/ MOV R5, R5 ;\n /*0ed0*/ MOV R6, R6 ;\n /*0ee0*/ FADD R4, R4, -R8 ;\n /*0ef0*/ FADD R5, R5, -R3 ;\n /*0f00*/ FADD R6, R6, -R2 ;\n /*0f10*/ FMUL R7, R5, R5 ;\n /*0f20*/ FFMA R7, R4, R4, R7 ;\n /*0f30*/ FFMA R7, R6, R6, R7 ;\n /*0f40*/ FADD R7, R7, 9.9999990510468705907e-09 ;\n /*0f50*/ MOV R7, R7 ;\n /*0f60*/ MOV R14, R14 ;\n /*0f70*/ MOV R15, R15 ;\n /*0f80*/ MOV R16, R16 ;\n /*0f90*/ MOV R4, R4 ;\n /*0fa0*/ MOV R5, R5 ;\n /*0fb0*/ MOV R6, R6 ;\n /*0fc0*/ MOV R7, R7 ;\n /*0fd0*/ MOV R7, R7 ;\n /*0fe0*/ MOV R7, R7 ;\n /*0ff0*/ FADD R22, -RZ, |R7| ;\n /*1000*/ MOV R22, R22 ;\n /*1010*/ MOV R23, 0x800000 ;\n /*1020*/ FSETP.LT.AND P0, PT, R22, R23, PT ;\n /*1030*/ MOV R22, 0x4b800000 ;\n /*1040*/ FMUL R22, R7, R22 ;\n /*1050*/ FSEL R22, R22, R7, P0 ;\n /*1060*/ MUFU.RSQ R22, R22 ;\n /*1070*/ MOV R22, R22 ;\n /*1080*/ MOV R7, 0x45800000 ;\n /*1090*/ FMUL R7, R22, R7 ;\n /*10a0*/ FSEL R7, R7, R22, P0 ;\n /*10b0*/ MOV R7, R7 ;\n /*10c0*/ MOV R7, R7 ;\n /*10d0*/ FMUL R22, R7, R7 ;\n /*10e0*/ FMUL R22, R7, R22 ;\n /*10f0*/ FMUL R22, R22, 6.6743000015634379452e-11 ;\n /*1100*/ FFMA R14, R4, R22, R14 ;\n /*1110*/ FFMA R15, R5, R22, R15 ;\n /*1120*/ FFMA R16, R6, R22, R16 ;\n /*1130*/ IADD3 R0, R0, 0x4, RZ ;\n /*1140*/ IADD3 R21, R21, -0x4, RZ ;\n /*1150*/ ISETP.NE.AND P0, PT, R21, RZ, PT ;\n /*1160*/ MOV R14, R14 ;\n /*1170*/ MOV R15, R15 ;\n /*1180*/ MOV R16, R16 ;\n /*1190*/ MOV R0, R0 ;\n /*11a0*/ MOV R21, R21 ;\n /*11b0*/ @P0 BRA `(.L_x_5) ;\n.L_x_4:\n /*11c0*/ BSYNC B1 ;\n.L_x_3:\n /*11d0*/ ISETP.EQ.AND P0, PT, R20, RZ, PT ;\n /*11e0*/ @P0 BRA `(.L_x_2) ;\n /*11f0*/ IMAD.WIDE R4, R0, 0x20, RZ ;\n /*1200*/ MOV R21, R4 ;\n /*1210*/ MOV R22, R5 ;\n /*1220*/ IADD3 R21, P0, R12, R21, RZ ;\n /*1230*/ IADD3.X R22, R11, R22, RZ, P0, !PT ;\n /*1240*/ MOV R21, R21 ;\n /*1250*/ MOV R22, R22 ;\n.L_x_6:\n /*1260*/ MOV R4, R21 ;\n /*1270*/ MOV R5, R22 ;\n /*1280*/ MOV R4, R4 ;\n /*1290*/ MOV R5, R5 ;\n /*12a0*/ R2UR UR4, R18 ;\n /*12b0*/ R2UR UR5, R19 ;\n /*12c0*/ LDG.E.128 R4, [R4.64] ;\n /*12d0*/ MOV R4, R4 ;\n /*12e0*/ MOV R5, R5 ;\n /*12f0*/ MOV R6, R6 ;\n /*1300*/ FADD R4, R4, -R8 ;\n /*1310*/ FADD R5, R5, -R3 ;\n /*1320*/ FADD R6, R6, -R2 ;\n /*1330*/ FMUL R7, R5, R5 ;\n /*1340*/ FFMA R7, R4, R4, R7 ;\n /*1350*/ FFMA R7, R6, R6, R7 ;\n /*1360*/ FADD R7, R7, 9.9999990510468705907e-09 ;\n /*1370*/ MOV R7, R7 ;\n /*1380*/ MOV R4, R4 ;\n /*1390*/ MOV R5, R5 ;\n /*13a0*/ MOV R6, R6 ;\n /*13b0*/ MOV R7, R7 ;\n /*13c0*/ MOV R7, R7 ;\n /*13d0*/ MOV R7, R7 ;\n /*13e0*/ FADD R23, -RZ, |R7| ;\n /*13f0*/ MOV R23, R23 ;\n /*1400*/ MOV R24, 0x800000 ;\n /*1410*/ FSETP.LT.AND P0, PT, R23, R24, PT ;\n /*1420*/ MOV R23, 0x4b800000 ;\n /*1430*/ FMUL R23, R7, R23 ;\n /*1440*/ FSEL R23, R23, R7, P0 ;\n /*1450*/ MUFU.RSQ R23, R23 ;\n /*1460*/ MOV R23, R23 ;\n /*1470*/ MOV R7, 0x45800000 ;\n /*1480*/ FMUL R7, R23, R7 ;\n /*1490*/ FSEL R7, R7, R23, P0 ;\n /*14a0*/ MOV R7, R7 ;\n /*14b0*/ MOV R7, R7 ;\n /*14c0*/ FMUL R23, R7, R7 ;\n /*14d0*/ FMUL R23, R7, R23 ;\n /*14e0*/ FMUL R23, R23, 6.6743000015634379452e-11 ;\n /*14f0*/ FFMA R4, R4, R23, R14 ;\n /*1500*/ FFMA R5, R5, R23, R15 ;\n /*1510*/ FFMA R6, R6, R23, R16 ;\n /*1520*/ IADD3 R0, R0, 0x1, RZ ;\n /*1530*/ IADD3 R21, P0, R21, 0x20, RZ ;\n /*1540*/ IADD3.X R22, R22, RZ, RZ, P0, !PT ;\n /*1550*/ IADD3 R20, R20, -0x1, RZ ;\n /*1560*/ ISETP.NE.AND P0, PT, R20, RZ, PT ;\n /*1570*/ MOV R14, R4 ;\n /*1580*/ MOV R15, R5 ;\n /*1590*/ MOV R16, R6 ;\n /*15a0*/ MOV R0, R0 ;\n /*15b0*/ MOV R21, R21 ;\n /*15c0*/ MOV R22, R22 ;\n /*15d0*/ MOV R20, R20 ;\n /*15e0*/ @P0 BRA `(.L_x_6) ;\n.L_x_2:\n /*15f0*/ BSYNC B0 ;\n.L_x_1:\n /*1600*/ ISETP.GE.AND P0, PT, R0, R13, PT ;\n /*1610*/ BSSY B0, `(.L_x_7) ;\n /*1620*/ @P0 BRA `(.L_x_8) ;\n /*1630*/ ISETP.EQ.AND P0, PT, R17, R0, PT ;\n /*1640*/ BSSY B1, `(.L_x_9) ;\n /*1650*/ @P0 BRA `(.L_x_10) ;\n /*1660*/ IMAD.WIDE R4, R0, 0x20, RZ ;\n /*1670*/ MOV R6, R4 ;\n /*1680*/ MOV R5, R5 ;\n /*1690*/ IADD3 R4, P0, R12, R6, RZ ;\n /*16a0*/ IADD3.X R5, R11, R5, RZ, P0, !PT ;\n /*16b0*/ MOV R4, R4 ;\n /*16c0*/ MOV R5, R5 ;\n /*16d0*/ MOV R4, R4 ;\n /*16e0*/ MOV R5, R5 ;\n /*16f0*/ R2UR UR4, R18 ;\n /*1700*/ R2UR UR5, R19 ;\n /*1710*/ LDG.E.128 R4, [R4.64] ;\n /*1720*/ MOV R4, R4 ;\n /*1730*/ MOV R5, R5 ;\n /*1740*/ MOV R6, R6 ;\n /*1750*/ FADD R4, R4, -R8 ;\n /*1760*/ FADD R5, R5, -R3 ;\n /*1770*/ FADD R7, R6, -R2 ;\n /*1780*/ FMUL R6, R5, R5 ;\n /*1790*/ FFMA R6, R4, R4, R6 ;\n /*17a0*/ FFMA R6, R7, R7, R6 ;\n /*17b0*/ FADD R6, R6, 9.9999990510468705907e-09 ;\n /*17c0*/ MOV R17, R6 ;\n /*17d0*/ MOV R6, R4 ;\n /*17e0*/ MOV R5, R5 ;\n /*17f0*/ MOV R4, R7 ;\n /*1800*/ MOV R17, R17 ;\n /*1810*/ MOV R17, R17 ;\n /*1820*/ MOV R17, R17 ;\n /*1830*/ FADD R7, -RZ, |R17| ;\n /*1840*/ MOV R7, R7 ;\n /*1850*/ MOV R20, 0x800000 ;\n /*1860*/ FSETP.LT.AND P0, PT, R7, R20, PT ;\n /*1870*/ MOV R7, 0x4b800000 ;\n /*1880*/ FMUL R7, R17, R7 ;\n /*1890*/ FSEL R7, R7, R17, P0 ;\n /*18a0*/ MUFU.RSQ R7, R7 ;\n /*18b0*/ MOV R7, R7 ;\n /*18c0*/ MOV R17, 0x45800000 ;\n /*18d0*/ FMUL R17, R7, R17 ;\n /*18e0*/ FSEL R17, R17, R7, P0 ;\n /*18f0*/ MOV R17, R17 ;\n /*1900*/ MOV R17, R17 ;\n /*1910*/ FMUL R7, R17, R17 ;\n /*1920*/ FMUL R7, R17, R7 ;\n /*1930*/ FMUL R7, R7, 6.6743000015634379452e-11 ;\n /*1940*/ FFMA R6, R6, R7, R14 ;\n /*1950*/ FFMA R5, R5, R7, R15 ;\n /*1960*/ FFMA R4, R4, R7, R16 ;\n /*1970*/ MOV R14, R6 ;\n /*1980*/ MOV R15, R5 ;\n /*1990*/ MOV R16, R4 ;\n.L_x_10:\n /*19a0*/ BSYNC B1 ;\n.L_x_9:\n /*19b0*/ IADD3 R0, R0, 0x1, RZ ;\n /*19c0*/ MOV R0, R0 ;\n.L_x_8:\n /*19d0*/ BSYNC B0 ;\n.L_x_7:\n /*19e0*/ ISETP.GE.AND P0, PT, R0, R13, PT ;\n /*19f0*/ BSSY B0, `(.L_x_11) ;\n /*1a00*/ @P0 BRA `(.L_x_12) ;\n /*1a10*/ IADD3 R4, R13, -R0, RZ ;\n /*1a20*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ;\n /*1a30*/ ISETP.EQ.AND P0, PT, R4, RZ, PT ;\n /*1a40*/ MOV R17, R0 ;\n /*1a50*/ MOV R20, R4 ;\n /*1a60*/ MOV R17, R17 ;\n /*1a70*/ BSSY B1, `(.L_x_13) ;\n /*1a80*/ @P0 BRA `(.L_x_14) ;\n /*1a90*/ IMAD.WIDE R4, R0, 0x20, RZ ;\n /*1aa0*/ MOV R21, R4 ;\n /*1ab0*/ MOV R22, R5 ;\n /*1ac0*/ IADD3 R21, P0, R12, R21, RZ ;\n /*1ad0*/ IADD3.X R22, R11, R22, RZ, P0, !PT ;\n /*1ae0*/ MOV R17, R0 ;\n /*1af0*/ MOV R21, R21 ;\n /*1b00*/ MOV R22, R22 ;\n /*1b10*/ MOV R17, R17 ;\n.L_x_15:\n /*1b20*/ MOV R4, R21 ;\n /*1b30*/ MOV R5, R22 ;\n /*1b40*/ MOV R4, R4 ;\n /*1b50*/ MOV R5, R5 ;\n /*1b60*/ R2UR UR4, R18 ;\n /*1b70*/ R2UR UR5, R19 ;\n /*1b80*/ LDG.E.128 R4, [R4.64] ;\n /*1b90*/ MOV R4, R4 ;\n /*1ba0*/ MOV R5, R5 ;\n /*1bb0*/ MOV R6, R6 ;\n /*1bc0*/ FADD R4, R4, -R8 ;\n /*1bd0*/ FADD R5, R5, -R3 ;\n /*1be0*/ FADD R6, R6, -R2 ;\n /*1bf0*/ FMUL R7, R5, R5 ;\n /*1c00*/ FFMA R7, R4, R4, R7 ;\n /*1c10*/ FFMA R7, R6, R6, R7 ;\n /*1c20*/ FADD R7, R7, 9.9999990510468705907e-09 ;\n /*1c30*/ MOV R7, R7 ;\n /*1c40*/ MOV R4, R4 ;\n /*1c50*/ MOV R5, R5 ;\n /*1c60*/ MOV R6, R6 ;\n /*1c70*/ MOV R7, R7 ;\n /*1c80*/ MOV R7, R7 ;\n /*1c90*/ MOV R7, R7 ;\n /*1ca0*/ FADD R23, -RZ, |R7| ;\n /*1cb0*/ MOV R23, R23 ;\n /*1cc0*/ MOV R24, 0x800000 ;\n /*1cd0*/ FSETP.LT.AND P0, PT, R23, R24, PT ;\n /*1ce0*/ MOV R23, 0x4b800000 ;\n /*1cf0*/ FMUL R23, R7, R23 ;\n /*1d00*/ FSEL R23, R23, R7, P0 ;\n /*1d10*/ MUFU.RSQ R23, R23 ;\n /*1d20*/ MOV R23, R23 ;\n /*1d30*/ MOV R7, 0x45800000 ;\n /*1d40*/ FMUL R7, R23, R7 ;\n /*1d50*/ FSEL R7, R7, R23, P0 ;\n /*1d60*/ MOV R7, R7 ;\n /*1d70*/ MOV R7, R7 ;\n /*1d80*/ FMUL R23, R7, R7 ;\n /*1d90*/ FMUL R23, R7, R23 ;\n /*1da0*/ FMUL R23, R23, 6.6743000015634379452e-11 ;\n /*1db0*/ FFMA R4, R4, R23, R14 ;\n /*1dc0*/ FFMA R5, R5, R23, R15 ;\n /*1dd0*/ FFMA R6, R6, R23, R16 ;\n /*1de0*/ IADD3 R17, R17, 0x1, RZ ;\n /*1df0*/ IADD3 R21, P0, R21, 0x20, RZ ;\n /*1e00*/ IADD3.X R22, R22, RZ, RZ, P0, !PT ;\n /*1e10*/ IADD3 R20, R20, -0x1, RZ ;\n /*1e20*/ ISETP.NE.AND P0, PT, R20, RZ, PT ;\n /*1e30*/ MOV R14, R4 ;\n /*1e40*/ MOV R15, R5 ;\n /*1e50*/ MOV R16, R6 ;\n /*1e60*/ MOV R17, R17 ;\n /*1e70*/ MOV R21, R21 ;\n /*1e80*/ MOV R22, R22 ;\n /*1e90*/ MOV R20, R20 ;\n /*1ea0*/ @P0 BRA `(.L_x_15) ;\n.L_x_14:\n /*1eb0*/ BSYNC B1 ;\n.L_x_13:\n /*1ec0*/ LOP3.LUT R0, RZ, R0, RZ, 0x33, !PT ;\n /*1ed0*/ IADD3 R0, R0, R13, RZ ;\n /*1ee0*/ ISETP.LT.U32.AND P0, PT, R0, 0x3, PT ;\n /*1ef0*/ @P0 BRA `(.L_x_12) ;\n /*1f00*/ IMAD.WIDE R4, R17, 0x20, RZ ;\n /*1f10*/ MOV R0, R4 ;\n /*1f20*/ MOV R4, R5 ;\n /*1f30*/ IADD3 R12, P0, R12, R0, RZ ;\n /*1f40*/ IADD3.X R0, R11, R4, RZ, P0, !PT ;\n /*1f50*/ IADD3 R11, P0, R12, 0x40, RZ ;\n /*1f60*/ IADD3.X R0, R0, RZ, RZ, P0, !PT ;\n /*1f70*/ MOV R11, R11 ;\n /*1f80*/ MOV R0, R0 ;\n.L_x_16:\n /*1f90*/ IADD3 R4, P0, R11, -0x40, RZ ;\n /*1fa0*/ IADD3.X R5, R0, -0x1, RZ, P0, !PT ;\n /*1fb0*/ MOV R4, R4 ;\n /*1fc0*/ MOV R5, R5 ;\n /*1fd0*/ MOV R4, R4 ;\n /*1fe0*/ MOV R5, R5 ;\n /*1ff0*/ R2UR UR4, R18 ;\n /*2000*/ R2UR UR5, R19 ;\n /*2010*/ LDG.E.128 R4, [R4.64] ;\n /*2020*/ MOV R4, R4 ;\n /*2030*/ MOV R5, R5 ;\n /*2040*/ MOV R6, R6 ;\n /*2050*/ FADD R4, R4, -R8 ;\n /*2060*/ FADD R5, R5, -R3 ;\n /*2070*/ FADD R7, R6, -R2 ;\n /*2080*/ FMUL R6, R5, R5 ;\n /*2090*/ FFMA R6, R4, R4, R6 ;\n /*20a0*/ FFMA R6, R7, R7, R6 ;\n /*20b0*/ FADD R6, R6, 9.9999990510468705907e-09 ;\n /*20c0*/ MOV R12, R6 ;\n /*20d0*/ MOV R6, R4 ;\n /*20e0*/ MOV R5, R5 ;\n /*20f0*/ MOV R4, R7 ;\n /*2100*/ MOV R12, R12 ;\n /*2110*/ MOV R12, R12 ;\n /*2120*/ MOV R12, R12 ;\n /*2130*/ FADD R7, -RZ, |R12| ;\n /*2140*/ MOV R7, R7 ;\n /*2150*/ MOV R20, 0x800000 ;\n /*2160*/ FSETP.LT.AND P0, PT, R7, R20, PT ;\n /*2170*/ MOV R7, 0x4b800000 ;\n /*2180*/ FMUL R7, R12, R7 ;\n /*2190*/ FSEL R7, R7, R12, P0 ;\n /*21a0*/ MUFU.RSQ R7, R7 ;\n /*21b0*/ MOV R7, R7 ;\n /*21c0*/ MOV R12, 0x45800000 ;\n /*21d0*/ FMUL R12, R7, R12 ;\n /*21e0*/ FSEL R12, R12, R7, P0 ;\n /*21f0*/ MOV R12, R12 ;\n /*2200*/ MOV R12, R12 ;\n /*2210*/ FMUL R7, R12, R12 ;\n /*2220*/ FMUL R7, R12, R7 ;\n /*2230*/ FMUL R7, R7, 6.6743000015634379452e-11 ;\n /*2240*/ FFMA R14, R6, R7, R14 ;\n /*2250*/ FFMA R15, R5, R7, R15 ;\n /*2260*/ FFMA R16, R4, R7, R16 ;\n /*2270*/ IADD3 R4, P0, R11, -0x20, RZ ;\n /*2280*/ IADD3.X R5, R0, -0x1, RZ, P0, !PT ;\n /*2290*/ MOV R4, R4 ;\n /*22a0*/ MOV R5, R5 ;\n /*22b0*/ MOV R4, R4 ;\n /*22c0*/ MOV R5, R5 ;\n /*22d0*/ R2UR UR4, R18 ;\n /*22e0*/ R2UR UR5, R19 ;\n /*22f0*/ LDG.E.128 R4, [R4.64] ;\n /*2300*/ MOV R4, R4 ;\n /*2310*/ MOV R5, R5 ;\n /*2320*/ MOV R6, R6 ;\n /*2330*/ FADD R12, R4, -R8 ;\n /*2340*/ FADD R7, R5, -R3 ;\n /*2350*/ FADD R20, R6, -R2 ;\n /*2360*/ FMUL R4, R7, R7 ;\n /*2370*/ FFMA R4, R12, R12, R4 ;\n /*2380*/ FFMA R4, R20, R20, R4 ;\n /*2390*/ FADD R4, R4, 9.9999990510468705907e-09 ;\n /*23a0*/ MOV R21, R4 ;\n /*23b0*/ MOV R5, R14 ;\n /*23c0*/ MOV R4, R15 ;\n /*23d0*/ MOV R6, R16 ;\n /*23e0*/ MOV R12, R12 ;\n /*23f0*/ MOV R14, R7 ;\n /*2400*/ MOV R7, R20 ;\n /*2410*/ MOV R21, R21 ;\n /*2420*/ MOV R21, R21 ;\n /*2430*/ MOV R21, R21 ;\n /*2440*/ FADD R15, -RZ, |R21| ;\n /*2450*/ MOV R15, R15 ;\n /*2460*/ MOV R16, 0x800000 ;\n /*2470*/ FSETP.LT.AND P0, PT, R15, R16, PT ;\n /*2480*/ MOV R15, 0x4b800000 ;\n /*2490*/ FMUL R15, R21, R15 ;\n /*24a0*/ FSEL R15, R15, R21, P0 ;\n /*24b0*/ MUFU.RSQ R15, R15 ;\n /*24c0*/ MOV R15, R15 ;\n /*24d0*/ MOV R16, 0x45800000 ;\n /*24e0*/ FMUL R16, R15, R16 ;\n /*24f0*/ FSEL R16, R16, R15, P0 ;\n /*2500*/ MOV R16, R16 ;\n /*2510*/ MOV R16, R16 ;\n /*2520*/ FMUL R15, R16, R16 ;\n /*2530*/ FMUL R15, R16, R15 ;\n /*2540*/ FMUL R15, R15, 6.6743000015634379452e-11 ;\n /*2550*/ FFMA R12, R12, R15, R5 ;\n /*2560*/ FFMA R14, R14, R15, R4 ;\n /*2570*/ FFMA R15, R7, R15, R6 ;\n /*2580*/ MOV R4, R11 ;\n /*2590*/ MOV R5, R0 ;\n /*25a0*/ MOV R4, R4 ;\n /*25b0*/ MOV R5, R5 ;\n /*25c0*/ R2UR UR4, R18 ;\n /*25d0*/ R2UR UR5, R19 ;\n /*25e0*/ LDG.E.128 R4, [R4.64] ;\n /*25f0*/ MOV R4, R4 ;\n /*2600*/ MOV R5, R5 ;\n /*2610*/ MOV R6, R6 ;\n /*2620*/ FADD R7, R4, -R8 ;\n /*2630*/ FADD R16, R5, -R3 ;\n /*2640*/ FADD R20, R6, -R2 ;\n /*2650*/ FMUL R4, R16, R16 ;\n /*2660*/ FFMA R4, R7, R7, R4 ;\n /*2670*/ FFMA R4, R20, R20, R4 ;\n /*2680*/ FADD R4, R4, 9.9999990510468705907e-09 ;\n /*2690*/ MOV R21, R4 ;\n /*26a0*/ MOV R6, R12 ;\n /*26b0*/ MOV R5, R14 ;\n /*26c0*/ MOV R4, R15 ;\n /*26d0*/ MOV R12, R7 ;\n /*26e0*/ MOV R14, R16 ;\n /*26f0*/ MOV R7, R20 ;\n /*2700*/ MOV R21, R21 ;\n /*2710*/ MOV R21, R21 ;\n /*2720*/ MOV R21, R21 ;\n /*2730*/ FADD R15, -RZ, |R21| ;\n /*2740*/ MOV R15, R15 ;\n /*2750*/ MOV R16, 0x800000 ;\n /*2760*/ FSETP.LT.AND P0, PT, R15, R16, PT ;\n /*2770*/ MOV R15, 0x4b800000 ;\n /*2780*/ FMUL R15, R21, R15 ;\n /*2790*/ FSEL R15, R15, R21, P0 ;\n /*27a0*/ MUFU.RSQ R15, R15 ;\n /*27b0*/ MOV R15, R15 ;\n /*27c0*/ MOV R16, 0x45800000 ;\n /*27d0*/ FMUL R16, R15, R16 ;\n /*27e0*/ FSEL R16, R16, R15, P0 ;\n /*27f0*/ MOV R16, R16 ;\n /*2800*/ MOV R16, R16 ;\n /*2810*/ FMUL R15, R16, R16 ;\n /*2820*/ FMUL R15, R16, R15 ;\n /*2830*/ FMUL R15, R15, 6.6743000015634379452e-11 ;\n /*2840*/ FFMA R12, R12, R15, R6 ;\n /*2850*/ FFMA R14, R14, R15, R5 ;\n /*2860*/ FFMA R15, R7, R15, R4 ;\n /*2870*/ IADD3 R4, P0, R11, 0x20, RZ ;\n /*2880*/ IADD3.X R5, R0, RZ, RZ, P0, !PT ;\n /*2890*/ MOV R4, R4 ;\n /*28a0*/ MOV R5, R5 ;\n /*28b0*/ MOV R4, R4 ;\n /*28c0*/ MOV R5, R5 ;\n /*28d0*/ R2UR UR4, R18 ;\n /*28e0*/ R2UR UR5, R19 ;\n /*28f0*/ LDG.E.128 R4, [R4.64] ;\n /*2900*/ MOV R4, R4 ;\n /*2910*/ MOV R5, R5 ;\n /*2920*/ MOV R6, R6 ;\n /*2930*/ FADD R7, R4, -R8 ;\n /*2940*/ FADD R16, R5, -R3 ;\n /*2950*/ FADD R20, R6, -R2 ;\n /*2960*/ FMUL R4, R16, R16 ;\n /*2970*/ FFMA R4, R7, R7, R4 ;\n /*2980*/ FFMA R4, R20, R20, R4 ;\n /*2990*/ FADD R4, R4, 9.9999990510468705907e-09 ;\n /*29a0*/ MOV R21, R4 ;\n /*29b0*/ MOV R4, R12 ;\n /*29c0*/ MOV R5, R14 ;\n /*29d0*/ MOV R6, R15 ;\n /*29e0*/ MOV R14, R7 ;\n /*29f0*/ MOV R12, R16 ;\n /*2a00*/ MOV R7, R20 ;\n /*2a10*/ MOV R21, R21 ;\n /*2a20*/ MOV R21, R21 ;\n /*2a30*/ MOV R21, R21 ;\n /*2a40*/ FADD R15, -RZ, |R21| ;\n /*2a50*/ MOV R15, R15 ;\n /*2a60*/ MOV R16, 0x800000 ;\n /*2a70*/ FSETP.LT.AND P0, PT, R15, R16, PT ;\n /*2a80*/ MOV R15, 0x4b800000 ;\n /*2a90*/ FMUL R15, R21, R15 ;\n /*2aa0*/ FSEL R15, R15, R21, P0 ;\n /*2ab0*/ MUFU.RSQ R15, R15 ;\n /*2ac0*/ MOV R15, R15 ;\n /*2ad0*/ MOV R16, 0x45800000 ;\n /*2ae0*/ FMUL R16, R15, R16 ;\n /*2af0*/ FSEL R16, R16, R15, P0 ;\n /*2b00*/ MOV R16, R16 ;\n /*2b10*/ MOV R16, R16 ;\n /*2b20*/ FMUL R15, R16, R16 ;\n /*2b30*/ FMUL R15, R16, R15 ;\n /*2b40*/ FMUL R15, R15, 6.6743000015634379452e-11 ;\n /*2b50*/ FFMA R14, R14, R15, R4 ;\n /*2b60*/ FFMA R5, R12, R15, R5 ;\n /*2b70*/ FFMA R6, R7, R15, R6 ;\n /*2b80*/ IADD3 R11, P0, R11, 0x80, RZ ;\n /*2b90*/ IADD3.X R0, R0, RZ, RZ, P0, !PT ;\n /*2ba0*/ IADD3 R17, R17, 0x4, RZ ;\n /*2bb0*/ ISETP.LT.AND P0, PT, R17, R13, PT ;\n /*2bc0*/ MOV R14, R14 ;\n /*2bd0*/ MOV R15, R5 ;\n /*2be0*/ MOV R16, R6 ;\n /*2bf0*/ MOV R11, R11 ;\n /*2c00*/ MOV R0, R0 ;\n /*2c10*/ MOV R17, R17 ;\n /*2c20*/ @P0 BRA `(.L_x_16) ;\n.L_x_12:\n /*2c30*/ BSYNC B0 ;\n.L_x_11:\n /*2c40*/ IADD3 R4, P0, R10, 0x10, RZ ;\n /*2c50*/ IADD3.X R5, R9, RZ, RZ, P0, !PT ;\n /*2c60*/ MOV R4, R4 ;\n /*2c70*/ MOV R5, R5 ;\n /*2c80*/ MOV R4, R4 ;\n /*2c90*/ MOV R5, R5 ;\n /*2ca0*/ R2UR UR4, R18 ;\n /*2cb0*/ R2UR UR5, R19 ;\n /*2cc0*/ LDG.E.128 R4, [R4.64] ;\n /*2cd0*/ MOV R4, R4 ;\n /*2ce0*/ MOV R5, R5 ;\n /*2cf0*/ MOV R6, R6 ;\n /*2d00*/ FFMA R15, R15, 0.0099999997764825820923, R5 ;\n /*2d10*/ FFMA R14, R14, 0.0099999997764825820923, R4 ;\n /*2d20*/ IADD3 R4, P0, R10, 0x10, RZ ;\n /*2d30*/ IADD3.X R5, R9, RZ, RZ, P0, !PT ;\n /*2d40*/ MOV R4, R4 ;\n /*2d50*/ MOV R5, R5 ;\n /*2d60*/ MOV R4, R4 ;\n /*2d70*/ MOV R5, R5 ;\n /*2d80*/ R2UR UR4, R18 ;\n /*2d90*/ R2UR UR5, R19 ;\n /*2da0*/ STG.E.64 [R4.64], R14 ;\n /*2db0*/ FFMA R6, R16, 0.0099999997764825820923, R6 ;\n /*2dc0*/ IADD3 R4, P0, R10, 0x18, RZ ;\n /*2dd0*/ IADD3.X R5, R9, RZ, RZ, P0, !PT ;\n /*2de0*/ MOV R4, R4 ;\n /*2df0*/ MOV R5, R5 ;\n /*2e00*/ MOV R4, R4 ;\n /*2e10*/ MOV R5, R5 ;\n /*2e20*/ R2UR UR4, R18 ;\n /*2e30*/ R2UR UR5, R19 ;\n /*2e40*/ STG.E [R4.64], R6 ;\n /*2e50*/ FFMA R15, R15, 0.0099999997764825820923, R3 ;\n /*2e60*/ FFMA R14, R14, 0.0099999997764825820923, R8 ;\n /*2e70*/ MOV R4, R10 ;\n /*2e80*/ MOV R5, R9 ;\n /*2e90*/ MOV R4, R4 ;\n /*2ea0*/ MOV R5, R5 ;\n /*2eb0*/ R2UR UR4, R18 ;\n /*2ec0*/ R2UR UR5, R19 ;\n /*2ed0*/ STG.E.64 [R4.64], R14 ;\n /*2ee0*/ FFMA R6, R6, 0.0099999997764825820923, R2 ;\n /*2ef0*/ IADD3 R2, P0, R10, 0x8, RZ ;\n /*2f00*/ IADD3.X R3, R9, RZ, RZ, P0, !PT ;\n /*2f10*/ MOV R2, R2 ;\n /*2f20*/ MOV R3, R3 ;\n /*2f30*/ MOV R2, R2 ;\n /*2f40*/ MOV R3, R3 ;\n /*2f50*/ R2UR UR4, R18 ;\n /*2f60*/ R2UR UR5, R19 ;\n /*2f70*/ STG.E [R2.64], R6 ;\n.L_x_0:\n /*2f80*/ EXIT ;\n.L_x_17:\n /*2f90*/ BRA `(.L_x_17);\n /*2fa0*/ NOP;\n /*2fb0*/ NOP;\n /*2fc0*/ NOP;\n /*2fd0*/ NOP;\n /*2fe0*/ NOP;\n /*2ff0*/ NOP;\n /*3000*/ NOP;\n /*3010*/ NOP;\n /*3020*/ NOP;\n /*3030*/ NOP;\n /*3040*/ NOP;\n /*3050*/ NOP;\n /*3060*/ NOP;\n /*3070*/ NOP;\n.L_x_18:\n"},"hip":{"kind":"string","value":"\t.text\n\t.file\t\"cuda_code_070792.hip\"\n\t.globl\t_Z27__device_stub__nbody_kernelP8Particlei # -- Begin function _Z27__device_stub__nbody_kernelP8Particlei\n\t.p2align\t4, 0x90\n\t.type\t_Z27__device_stub__nbody_kernelP8Particlei,@function\n_Z27__device_stub__nbody_kernelP8Particlei: # @_Z27__device_stub__nbody_kernelP8Particlei\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$88, %rsp\n\t.cfi_def_cfa_offset 96\n\tmovq\t%rdi, 56(%rsp)\n\tmovl\t%esi, 4(%rsp)\n\tleaq\t56(%rsp), %rax\n\tmovq\t%rax, 64(%rsp)\n\tleaq\t4(%rsp), %rax\n\tmovq\t%rax, 72(%rsp)\n\tleaq\t40(%rsp), %rdi\n\tleaq\t24(%rsp), %rsi\n\tleaq\t16(%rsp), %rdx\n\tleaq\t8(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t40(%rsp), %rsi\n\tmovl\t48(%rsp), %edx\n\tmovq\t24(%rsp), %rcx\n\tmovl\t32(%rsp), %r8d\n\tleaq\t64(%rsp), %r9\n\tmovl\t$_Z12nbody_kernelP8Particlei, %edi\n\tpushq\t8(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t24(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$104, %rsp\n\t.cfi_adjust_cfa_offset -104\n\tretq\n.Lfunc_end0:\n\t.size\t_Z27__device_stub__nbody_kernelP8Particlei, .Lfunc_end0-_Z27__device_stub__nbody_kernelP8Particlei\n\t.cfi_endproc\n # -- End function\n\t.globl\tmain # -- Begin function main\n\t.p2align\t4, 0x90\n\t.type\tmain,@function\nmain: # @main\n.Lfunc_begin0:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception0\n# %bb.0:\n\tpushq\t%rbp\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r15\n\t.cfi_def_cfa_offset 24\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 32\n\tpushq\t%r12\n\t.cfi_def_cfa_offset 40\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 48\n\tsubq\t$96, %rsp\n\t.cfi_def_cfa_offset 144\n\t.cfi_offset %rbx, -48\n\t.cfi_offset %r12, -40\n\t.cfi_offset %r14, -32\n\t.cfi_offset %r15, -24\n\t.cfi_offset %rbp, -16\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$2048, %edi # imm = 0x800\n\tcallq\t_Znwm\n\tmovq\t%rax, %rbx\n\txorps\t%xmm0, %xmm0\n\tmovaps\t%xmm0, (%rax)\n\tmovaps\t%xmm0, 16(%rax)\n\tmovl\t$96, %eax\n\t.p2align\t4, 0x90\n.LBB1_1: # =>This Inner Loop Header: Depth=1\n\tmovaps\t(%rbx), %xmm0\n\tmovaps\t16(%rbx), %xmm1\n\tmovaps\t%xmm1, -48(%rbx,%rax)\n\tmovaps\t%xmm0, -64(%rbx,%rax)\n\tmovaps\t(%rbx), %xmm0\n\tmovaps\t16(%rbx), %xmm1\n\tmovaps\t%xmm0, -32(%rbx,%rax)\n\tmovaps\t%xmm1, -16(%rbx,%rax)\n\tmovaps\t(%rbx), %xmm0\n\tmovaps\t16(%rbx), %xmm1\n\tmovaps\t%xmm0, (%rbx,%rax)\n\tmovaps\t%xmm1, 16(%rbx,%rax)\n\taddq\t$96, %rax\n\tcmpq\t$2112, %rax # imm = 0x840\n\tjne\t.LBB1_1\n# %bb.2:\n\tleaq\t16(%rbx), %rax\n\txorl\t%ecx, %ecx\n\txorps\t%xmm0, %xmm0\n\t.p2align\t4, 0x90\n.LBB1_3: # =>This Inner Loop Header: Depth=1\n\txorps\t%xmm1, %xmm1\n\tcvtsi2ss\t%ecx, %xmm1\n\txorps\t%xmm2, %xmm2\n\tmovss\t%xmm1, %xmm2 # xmm2 = xmm1[0],xmm2[1,2,3]\n\tshufps\t$64, %xmm2, %xmm1 # xmm1 = xmm1[0,0],xmm2[0,1]\n\tmovaps\t%xmm1, -16(%rax)\n\tmovaps\t%xmm0, (%rax)\n\tincq\t%rcx\n\taddq\t$32, %rax\n\tcmpq\t$64, %rcx\n\tjne\t.LBB1_3\n# %bb.4:\n.Ltmp0:\n\t.cfi_escape 0x2e, 0x00\n\tleaq\t8(%rsp), %rdi\n\tmovl\t$2048, %esi # imm = 0x800\n\tcallq\thipMalloc\n.Ltmp1:\n# %bb.5:\n\tmovl\t%eax, %ebp\n\ttestl\t%eax, %eax\n\tje\t.LBB1_18\n# %bb.6:\n.Ltmp2:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$34, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp3:\n# %bb.7:\n.Ltmp4:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%ebp, %edi\n\tcallq\thipGetErrorString\n.Ltmp5:\n# %bb.8:\n\ttestq\t%rax, %rax\n\tje\t.LBB1_9\n# %bb.10:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tmovq\t%rax, %r14\n\tcallq\tstrlen\n.Ltmp6:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%r14, %rsi\n\tmovq\t%rax, %rdx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp7:\n\tjmp\t.LBB1_11\n.LBB1_18:\n\tmovq\t8(%rsp), %rdi\n.Ltmp18:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$2048, %edx # imm = 0x800\n\tmovq\t%rbx, %rsi\n\tmovl\t$1, %ecx\n\tcallq\thipMemcpy\n.Ltmp19:\n# %bb.19:\n\tmovl\t%eax, %ebp\n\ttestl\t%eax, %eax\n\tje\t.LBB1_35\n# %bb.20:\n.Ltmp20:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$31, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp21:\n# %bb.21:\n.Ltmp22:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%ebp, %edi\n\tcallq\thipGetErrorString\n.Ltmp23:\n# %bb.22:\n\ttestq\t%rax, %rax\n\tje\t.LBB1_23\n# %bb.24:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tmovq\t%rax, %r14\n\tcallq\tstrlen\n.Ltmp24:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%r14, %rsi\n\tmovq\t%rax, %rdx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp25:\n\tjmp\t.LBB1_25\n.LBB1_9:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tleaq\t_ZSt4cerr(%rax), %rdi\n\tmovl\t_ZSt4cerr+32(%rax), %esi\n\torl\t$1, %esi\n.Ltmp8:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\t_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate\n.Ltmp9:\n.LBB1_11:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tmovq\t_ZSt4cerr+240(%rax), %r14\n\ttestq\t%r14, %r14\n\tje\t.LBB1_26\n# %bb.12:\n\tcmpb\t$0, 56(%r14)\n\tje\t.LBB1_14\n# %bb.13:\n\tmovzbl\t67(%r14), %eax\n\tjmp\t.LBB1_16\n.LBB1_14:\n.Ltmp10:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%r14, %rdi\n\tcallq\t_ZNKSt5ctypeIcE13_M_widen_initEv\n.Ltmp11:\n# %bb.15:\n\tmovq\t(%r14), %rax\n.Ltmp12:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%r14, %rdi\n\tmovl\t$10, %esi\n\tcallq\t*48(%rax)\n.Ltmp13:\n.LBB1_16:\n.Ltmp14:\n\t.cfi_escape 0x2e, 0x00\n\tmovsbl\t%al, %esi\n\tmovl\t$_ZSt4cerr, %edi\n\tcallq\t_ZNSo3putEc\n.Ltmp15:\n# %bb.17:\n\tmovl\t$-1, %ebp\n.Ltmp16:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZNSo5flushEv\n.Ltmp17:\n\tjmp\t.LBB1_69\n.LBB1_35:\n.Ltmp41:\n\t.cfi_escape 0x2e, 0x00\n\tmovabsq\t$4294967297, %rdi # imm = 0x100000001\n\tmovabsq\t$4294967552, %rdx # imm = 0x100000100\n\tmovl\t$1, %esi\n\tmovl\t$1, %ecx\n\txorl\t%r8d, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipPushCallConfiguration\n.Ltmp42:\n# %bb.36:\n\ttestl\t%eax, %eax\n\tjne\t.LBB1_39\n# %bb.37:\n\tmovq\t8(%rsp), %rax\n\tmovq\t%rax, 72(%rsp)\n\tmovl\t$64, 20(%rsp)\n\tleaq\t72(%rsp), %rax\n\tmovq\t%rax, 80(%rsp)\n\tleaq\t20(%rsp), %rax\n\tmovq\t%rax, 88(%rsp)\n.Ltmp43:\n\t.cfi_escape 0x2e, 0x00\n\tleaq\t56(%rsp), %rdi\n\tleaq\t40(%rsp), %rsi\n\tleaq\t32(%rsp), %rdx\n\tleaq\t24(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n.Ltmp44:\n# %bb.38:\n\tmovq\t56(%rsp), %rsi\n\tmovl\t64(%rsp), %edx\n\tmovq\t40(%rsp), %rcx\n\tmovl\t48(%rsp), %r8d\n.Ltmp45:\n\t.cfi_escape 0x2e, 0x10\n\tleaq\t80(%rsp), %r9\n\tmovl\t$_Z12nbody_kernelP8Particlei, %edi\n\tpushq\t24(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t40(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$16, %rsp\n\t.cfi_adjust_cfa_offset -16\n.Ltmp46:\n.LBB1_39:\n\tmovq\t8(%rsp), %rsi\n.Ltmp47:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$2048, %edx # imm = 0x800\n\tmovq\t%rbx, %rdi\n\tmovl\t$2, %ecx\n\tcallq\thipMemcpy\n.Ltmp48:\n# %bb.40:\n\tmovl\t%eax, %ebp\n\ttestl\t%eax, %eax\n\tje\t.LBB1_56\n# %bb.41:\n.Ltmp49:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$33, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp50:\n# %bb.42:\n.Ltmp51:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%ebp, %edi\n\tcallq\thipGetErrorString\n.Ltmp52:\n# %bb.43:\n\ttestq\t%rax, %rax\n\tje\t.LBB1_44\n# %bb.45:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tmovq\t%rax, %r14\n\tcallq\tstrlen\n.Ltmp53:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%r14, %rsi\n\tmovq\t%rax, %rdx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp54:\n\tjmp\t.LBB1_46\n.LBB1_23:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tleaq\t_ZSt4cerr(%rax), %rdi\n\tmovl\t_ZSt4cerr+32(%rax), %esi\n\torl\t$1, %esi\n.Ltmp26:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\t_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate\n.Ltmp27:\n.LBB1_25:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tmovq\t_ZSt4cerr+240(%rax), %r14\n\ttestq\t%r14, %r14\n\tje\t.LBB1_26\n# %bb.28:\n\tcmpb\t$0, 56(%r14)\n\tje\t.LBB1_30\n# %bb.29:\n\tmovzbl\t67(%r14), %eax\n\tjmp\t.LBB1_32\n.LBB1_30:\n.Ltmp28:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%r14, %rdi\n\tcallq\t_ZNKSt5ctypeIcE13_M_widen_initEv\n.Ltmp29:\n# %bb.31:\n\tmovq\t(%r14), %rax\n.Ltmp30:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%r14, %rdi\n\tmovl\t$10, %esi\n\tcallq\t*48(%rax)\n.Ltmp31:\n.LBB1_32:\n.Ltmp32:\n\t.cfi_escape 0x2e, 0x00\n\tmovsbl\t%al, %esi\n\tmovl\t$_ZSt4cerr, %edi\n\tcallq\t_ZNSo3putEc\n.Ltmp33:\n# %bb.33:\n.Ltmp34:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZNSo5flushEv\n.Ltmp35:\n# %bb.34:\n\tmovl\t$-1, %ebp\n\tmovq\t8(%rsp), %rdi\n.Ltmp36:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipFree\n.Ltmp37:\n\tjmp\t.LBB1_69\n.LBB1_56:\n\tmovq\t8(%rsp), %rdi\n.Ltmp69:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipFree\n.Ltmp70:\n# %bb.57:\n\tmovq\t%rbx, %r12\n\taddq\t$8, %r12\n\txorl\t%r14d, %r14d\n\t.p2align\t4, 0x90\n.LBB1_58: # =>This Inner Loop Header: Depth=1\n.Ltmp72:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cout, %edi\n\tmovl\t$.L.str.3, %esi\n\tmovl\t$9, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp73:\n# %bb.59: # in Loop: Header=BB1_58 Depth=1\n.Ltmp74:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cout, %edi\n\tmovl\t%r14d, %esi\n\tcallq\t_ZNSolsEi\n.Ltmp75:\n# %bb.60: # in Loop: Header=BB1_58 Depth=1\n.Ltmp76:\n\tmovq\t%rax, %r15\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.4, %esi\n\tmovl\t$3, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp77:\n# %bb.61: # in Loop: Header=BB1_58 Depth=1\n\tmovss\t-8(%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero\n\tcvtss2sd\t%xmm0, %xmm0\n.Ltmp78:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%r15, %rdi\n\tcallq\t_ZNSo9_M_insertIdEERSoT_\n.Ltmp79:\n# %bb.62: # in Loop: Header=BB1_58 Depth=1\n.Ltmp80:\n\tmovq\t%rax, %r15\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.5, %esi\n\tmovl\t$2, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp81:\n# %bb.63: # in Loop: Header=BB1_58 Depth=1\n\tmovss\t-4(%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero\n\tcvtss2sd\t%xmm0, %xmm0\n.Ltmp82:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%r15, %rdi\n\tcallq\t_ZNSo9_M_insertIdEERSoT_\n.Ltmp83:\n# %bb.64: # in Loop: Header=BB1_58 Depth=1\n.Ltmp84:\n\tmovq\t%rax, %r15\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.5, %esi\n\tmovl\t$2, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp85:\n# %bb.65: # in Loop: Header=BB1_58 Depth=1\n\tmovss\t(%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero\n\tcvtss2sd\t%xmm0, %xmm0\n.Ltmp86:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%r15, %rdi\n\tcallq\t_ZNSo9_M_insertIdEERSoT_\n.Ltmp87:\n# %bb.66: # in Loop: Header=BB1_58 Depth=1\n.Ltmp88:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.6, %esi\n\tmovl\t$2, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp89:\n# %bb.67: # in Loop: Header=BB1_58 Depth=1\n\tincq\t%r14\n\taddq\t$32, %r12\n\tcmpq\t$64, %r14\n\tjne\t.LBB1_58\n# %bb.68:\n\txorl\t%ebp, %ebp\n\tjmp\t.LBB1_69\n.LBB1_44:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tleaq\t_ZSt4cerr(%rax), %rdi\n\tmovl\t_ZSt4cerr+32(%rax), %esi\n\torl\t$1, %esi\n.Ltmp55:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\t_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate\n.Ltmp56:\n.LBB1_46:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tmovq\t_ZSt4cerr+240(%rax), %r14\n\ttestq\t%r14, %r14\n\tje\t.LBB1_47\n# %bb.49:\n\tcmpb\t$0, 56(%r14)\n\tje\t.LBB1_51\n# %bb.50:\n\tmovzbl\t67(%r14), %eax\n\tjmp\t.LBB1_53\n.LBB1_51:\n.Ltmp57:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%r14, %rdi\n\tcallq\t_ZNKSt5ctypeIcE13_M_widen_initEv\n.Ltmp58:\n# %bb.52:\n\tmovq\t(%r14), %rax\n.Ltmp59:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%r14, %rdi\n\tmovl\t$10, %esi\n\tcallq\t*48(%rax)\n.Ltmp60:\n.LBB1_53:\n.Ltmp61:\n\t.cfi_escape 0x2e, 0x00\n\tmovsbl\t%al, %esi\n\tmovl\t$_ZSt4cerr, %edi\n\tcallq\t_ZNSo3putEc\n.Ltmp62:\n# %bb.54:\n.Ltmp63:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZNSo5flushEv\n.Ltmp64:\n# %bb.55:\n\tmovl\t$-1, %ebp\n\tmovq\t8(%rsp), %rdi\n.Ltmp65:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipFree\n.Ltmp66:\n.LBB1_69:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZdlPv\n\tmovl\t%ebp, %eax\n\taddq\t$96, %rsp\n\t.cfi_def_cfa_offset 48\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 40\n\tpopq\t%r12\n\t.cfi_def_cfa_offset 32\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r15\n\t.cfi_def_cfa_offset 16\n\tpopq\t%rbp\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB1_26:\n\t.cfi_def_cfa_offset 144\n.Ltmp38:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\t_ZSt16__throw_bad_castv\n.Ltmp39:\n# %bb.27:\n.LBB1_47:\n.Ltmp67:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\t_ZSt16__throw_bad_castv\n.Ltmp68:\n# %bb.48:\n.LBB1_72:\n.Ltmp71:\n\tjmp\t.LBB1_71\n.LBB1_70:\n.Ltmp40:\n\tjmp\t.LBB1_71\n.LBB1_73:\n.Ltmp90:\n.LBB1_71:\n\tmovq\t%rax, %r14\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZdlPv\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%r14, %rdi\n\tcallq\t_Unwind_Resume@PLT\n.Lfunc_end1:\n\t.size\tmain, .Lfunc_end1-main\n\t.cfi_endproc\n\t.section\t.gcc_except_table,\"a\",@progbits\n\t.p2align\t2, 0x0\nGCC_except_table1:\n.Lexception0:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t255 # @TType Encoding = omit\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end0-.Lcst_begin0\n.Lcst_begin0:\n\t.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<\n\t.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<\n\t.uleb128 .Ltmp17-.Ltmp0 # Call between .Ltmp0 and .Ltmp17\n\t.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp41-.Lfunc_begin0 # >> Call Site 3 <<\n\t.uleb128 .Ltmp54-.Ltmp41 # Call between .Ltmp41 and .Ltmp54\n\t.uleb128 .Ltmp71-.Lfunc_begin0 # jumps to .Ltmp71\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 4 <<\n\t.uleb128 .Ltmp37-.Ltmp26 # Call between .Ltmp26 and .Ltmp37\n\t.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp69-.Lfunc_begin0 # >> Call Site 5 <<\n\t.uleb128 .Ltmp70-.Ltmp69 # Call between .Ltmp69 and .Ltmp70\n\t.uleb128 .Ltmp71-.Lfunc_begin0 # jumps to .Ltmp71\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp72-.Lfunc_begin0 # >> Call Site 6 <<\n\t.uleb128 .Ltmp89-.Ltmp72 # Call between .Ltmp72 and .Ltmp89\n\t.uleb128 .Ltmp90-.Lfunc_begin0 # jumps to .Ltmp90\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp55-.Lfunc_begin0 # >> Call Site 7 <<\n\t.uleb128 .Ltmp66-.Ltmp55 # Call between .Ltmp55 and .Ltmp66\n\t.uleb128 .Ltmp71-.Lfunc_begin0 # jumps to .Ltmp71\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp38-.Lfunc_begin0 # >> Call Site 8 <<\n\t.uleb128 .Ltmp39-.Ltmp38 # Call between .Ltmp38 and .Ltmp39\n\t.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp67-.Lfunc_begin0 # >> Call Site 9 <<\n\t.uleb128 .Ltmp68-.Ltmp67 # Call between .Ltmp67 and .Ltmp68\n\t.uleb128 .Ltmp71-.Lfunc_begin0 # jumps to .Ltmp71\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp68-.Lfunc_begin0 # >> Call Site 10 <<\n\t.uleb128 .Lfunc_end1-.Ltmp68 # Call between .Ltmp68 and .Lfunc_end1\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n.Lcst_end0:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text.startup,\"ax\",@progbits\n\t.p2align\t4, 0x90 # -- Begin function _GLOBAL__sub_I_cuda_code_070792.hip\n\t.type\t_GLOBAL__sub_I_cuda_code_070792.hip,@function\n_GLOBAL__sub_I_cuda_code_070792.hip: # @_GLOBAL__sub_I_cuda_code_070792.hip\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 16\n\tmovl\t$_ZStL8__ioinit, %edi\n\tcallq\t_ZNSt8ios_base4InitC1Ev\n\tmovl\t$_ZNSt8ios_base4InitD1Ev, %edi\n\tmovl\t$_ZStL8__ioinit, %esi\n\tmovl\t$__dso_handle, %edx\n\tpopq\t%rax\n\t.cfi_def_cfa_offset 8\n\tjmp\t__cxa_atexit # TAILCALL\n.Lfunc_end2:\n\t.size\t_GLOBAL__sub_I_cuda_code_070792.hip, .Lfunc_end2-_GLOBAL__sub_I_cuda_code_070792.hip\n\t.cfi_endproc\n # -- End function\n\t.text\n\t.p2align\t4, 0x90 # -- Begin function __hip_module_ctor\n\t.type\t__hip_module_ctor,@function\n__hip_module_ctor: # @__hip_module_ctor\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$40, %rsp\n\t.cfi_def_cfa_offset 48\n\tmovq\t__hip_gpubin_handle(%rip), %rdi\n\ttestq\t%rdi, %rdi\n\tjne\t.LBB3_2\n# %bb.1:\n\tmovl\t$__hip_fatbin_wrapper, %edi\n\tcallq\t__hipRegisterFatBinary\n\tmovq\t%rax, %rdi\n\tmovq\t%rax, __hip_gpubin_handle(%rip)\n.LBB3_2:\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, 16(%rsp)\n\tmovups\t%xmm0, (%rsp)\n\tmovl\t$_Z12nbody_kernelP8Particlei, %esi\n\tmovl\t$.L__unnamed_1, %edx\n\tmovl\t$.L__unnamed_1, %ecx\n\tmovl\t$-1, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipRegisterFunction\n\tmovl\t$__hip_module_dtor, %edi\n\taddq\t$40, %rsp\n\t.cfi_def_cfa_offset 8\n\tjmp\tatexit # TAILCALL\n.Lfunc_end3:\n\t.size\t__hip_module_ctor, .Lfunc_end3-__hip_module_ctor\n\t.cfi_endproc\n # -- End function\n\t.p2align\t4, 0x90 # -- Begin function __hip_module_dtor\n\t.type\t__hip_module_dtor,@function\n__hip_module_dtor: # @__hip_module_dtor\n\t.cfi_startproc\n# %bb.0:\n\tmovq\t__hip_gpubin_handle(%rip), %rdi\n\ttestq\t%rdi, %rdi\n\tje\t.LBB4_2\n# %bb.1:\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 16\n\tcallq\t__hipUnregisterFatBinary\n\tmovq\t$0, __hip_gpubin_handle(%rip)\n\taddq\t$8, %rsp\n\t.cfi_def_cfa_offset 8\n.LBB4_2:\n\tretq\n.Lfunc_end4:\n\t.size\t__hip_module_dtor, .Lfunc_end4-__hip_module_dtor\n\t.cfi_endproc\n # -- End function\n\t.type\t_ZStL8__ioinit,@object # @_ZStL8__ioinit\n\t.local\t_ZStL8__ioinit\n\t.comm\t_ZStL8__ioinit,1,1\n\t.hidden\t__dso_handle\n\t.type\t_Z12nbody_kernelP8Particlei,@object # @_Z12nbody_kernelP8Particlei\n\t.section\t.rodata,\"a\",@progbits\n\t.globl\t_Z12nbody_kernelP8Particlei\n\t.p2align\t3, 0x0\n_Z12nbody_kernelP8Particlei:\n\t.quad\t_Z27__device_stub__nbody_kernelP8Particlei\n\t.size\t_Z12nbody_kernelP8Particlei, 8\n\n\t.type\t.L.str,@object # @.str\n\t.section\t.rodata.str1.1,\"aMS\",@progbits,1\n.L.str:\n\t.asciz\t\"Failed to allocate device memory: \"\n\t.size\t.L.str, 35\n\n\t.type\t.L.str.1,@object # @.str.1\n.L.str.1:\n\t.asciz\t\"Failed to copy data to device: \"\n\t.size\t.L.str.1, 32\n\n\t.type\t.L.str.2,@object # @.str.2\n.L.str.2:\n\t.asciz\t\"Failed to copy data from device: \"\n\t.size\t.L.str.2, 34\n\n\t.type\t.L.str.3,@object # @.str.3\n.L.str.3:\n\t.asciz\t\"Particle \"\n\t.size\t.L.str.3, 10\n\n\t.type\t.L.str.4,@object # @.str.4\n.L.str.4:\n\t.asciz\t\": (\"\n\t.size\t.L.str.4, 4\n\n\t.type\t.L.str.5,@object # @.str.5\n.L.str.5:\n\t.asciz\t\", \"\n\t.size\t.L.str.5, 3\n\n\t.type\t.L.str.6,@object # @.str.6\n.L.str.6:\n\t.asciz\t\")\\n\"\n\t.size\t.L.str.6, 3\n\n\t.type\t.L__unnamed_1,@object # @0\n.L__unnamed_1:\n\t.asciz\t\"_Z12nbody_kernelP8Particlei\"\n\t.size\t.L__unnamed_1, 28\n\n\t.type\t__hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper\n\t.section\t.hipFatBinSegment,\"a\",@progbits\n\t.p2align\t3, 0x0\n__hip_fatbin_wrapper:\n\t.long\t1212764230 # 0x48495046\n\t.long\t1 # 0x1\n\t.quad\t__hip_fatbin\n\t.quad\t0\n\t.size\t__hip_fatbin_wrapper, 24\n\n\t.type\t__hip_gpubin_handle,@object # @__hip_gpubin_handle\n\t.local\t__hip_gpubin_handle\n\t.comm\t__hip_gpubin_handle,8,8\n\t.section\t.init_array,\"aw\",@init_array\n\t.p2align\t3, 0x0\n\t.quad\t_GLOBAL__sub_I_cuda_code_070792.hip\n\t.quad\t__hip_module_ctor\n\t.type\t__hip_cuid_,@object # @__hip_cuid_\n\t.bss\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 # 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n"}}},{"rowIdx":162587,"cells":{"id":{"kind":"string","value":"930a2ecc65b1850e90939755a5c1d88b05e193d0_O0"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z11transposeRCPjPfS0_jj --------------------------\n .section .text._Z11transposeRCPjPfS0_jj,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=17\"\n .align 128\n\n\n\n\n .global _Z11transposeRCPjPfS0_jj\n .type _Z11transposeRCPjPfS0_jj,@function\n .size _Z11transposeRCPjPfS0_jj,(.L_x_2 - _Z11transposeRCPjPfS0_jj)\n .other _Z11transposeRCPjPfS0_jj,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z11transposeRCPjPfS0_jj:\n.text._Z11transposeRCPjPfS0_jj:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ MOV R8, c[0x0][0x118] ;\n /*0020*/ MOV R9, c[0x0][0x11c] ;\n /*0030*/ MOV R2, RZ ;\n /*0040*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0050*/ MOV R12, R2 ;\n /*0060*/ MOV R13, R3 ;\n /*0070*/ MOV R12, R12 ;\n /*0080*/ MOV R13, R13 ;\n /*0090*/ MOV R2, 0x8 ;\n /*00a0*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*00b0*/ MOV R4, R2 ;\n /*00c0*/ MOV R14, R3 ;\n /*00d0*/ MOV R4, R4 ;\n /*00e0*/ MOV R14, R14 ;\n /*00f0*/ MOV R2, 0x10 ;\n /*0100*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0110*/ MOV R10, R2 ;\n /*0120*/ MOV R11, R3 ;\n /*0130*/ MOV R10, R10 ;\n /*0140*/ MOV R11, R11 ;\n /*0150*/ MOV R0, 0x18 ;\n /*0160*/ LDC R0, c[0x0][R0+0x160] ;\n /*0170*/ MOV R0, R0 ;\n /*0180*/ MOV R2, 0x1c ;\n /*0190*/ LDC R2, c[0x0][R2+0x160] ;\n /*01a0*/ MOV R5, R2 ;\n /*01b0*/ MOV R12, R12 ;\n /*01c0*/ MOV R13, R13 ;\n /*01d0*/ S2R R2, SR_TID.X ;\n /*01e0*/ MOV R2, R2 ;\n /*01f0*/ IADD3 R6, R2, 0x1, RZ ;\n /*0200*/ S2R R7, SR_CTAID.X ;\n /*0210*/ MOV R7, R7 ;\n /*0220*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ;\n /*0230*/ MOV R4, R4 ;\n /*0240*/ MOV R3, R14 ;\n /*0250*/ MOV R2, R10 ;\n /*0260*/ MOV R0, R11 ;\n /*0270*/ MOV R5, R5 ;\n /*0280*/ MOV R12, R12 ;\n /*0290*/ MOV R13, R13 ;\n /*02a0*/ MOV R10, R6 ;\n /*02b0*/ MOV R7, R7 ;\n /*02c0*/ @P0 BRA `(.L_x_0) ;\n /*02d0*/ IADD3 R5, R5, 0x1, RZ ;\n /*02e0*/ IMAD R5, R5, R7, RZ ;\n /*02f0*/ IMAD.WIDE.U32 R6, R5, 0x4, RZ ;\n /*0300*/ MOV R11, R6 ;\n /*0310*/ MOV R7, R7 ;\n /*0320*/ IADD3 R6, P0, R12, R11, RZ ;\n /*0330*/ IADD3.X R7, R13, R7, RZ, P0, !PT ;\n /*0340*/ MOV R6, R6 ;\n /*0350*/ MOV R7, R7 ;\n /*0360*/ MOV R6, R6 ;\n /*0370*/ MOV R7, R7 ;\n /*0380*/ R2UR UR4, R8 ;\n /*0390*/ R2UR UR5, R9 ;\n /*03a0*/ LDG.E R6, [R6.64] ;\n /*03b0*/ ISETP.GT.U32.AND P0, PT, R10, R6, PT ;\n /*03c0*/ MOV R5, R5 ;\n /*03d0*/ @P0 BRA `(.L_x_0) ;\n /*03e0*/ IADD3 R5, R5, R10, RZ ;\n /*03f0*/ IMAD.WIDE.U32 R6, R5, 0x4, RZ ;\n /*0400*/ MOV R5, R6 ;\n /*0410*/ MOV R6, R7 ;\n /*0420*/ IADD3 R7, P0, R12, R5, RZ ;\n /*0430*/ IADD3.X R10, R13, R6, RZ, P0, !PT ;\n /*0440*/ MOV R4, R4 ;\n /*0450*/ MOV R3, R3 ;\n /*0460*/ IADD3 R4, P0, R4, R5, RZ ;\n /*0470*/ IADD3.X R5, R3, R6, RZ, P0, !PT ;\n /*0480*/ MOV R4, R4 ;\n /*0490*/ MOV R5, R5 ;\n /*04a0*/ MOV R4, R4 ;\n /*04b0*/ MOV R5, R5 ;\n /*04c0*/ R2UR UR4, R8 ;\n /*04d0*/ R2UR UR5, R9 ;\n /*04e0*/ LDG.E R6, [R4.64] ;\n /*04f0*/ MOV R4, R7 ;\n /*0500*/ MOV R5, R10 ;\n /*0510*/ MOV R4, R4 ;\n /*0520*/ MOV R5, R5 ;\n /*0530*/ R2UR UR4, R8 ;\n /*0540*/ R2UR UR5, R9 ;\n /*0550*/ LDG.E R3, [R4.64] ;\n /*0560*/ MOV R4, R2 ;\n /*0570*/ MOV R5, R0 ;\n /*0580*/ IMAD.WIDE.U32 R2, R3, 0x4, RZ ;\n /*0590*/ MOV R0, R2 ;\n /*05a0*/ MOV R3, R3 ;\n /*05b0*/ IADD3 R2, P0, R4, R0, RZ ;\n /*05c0*/ IADD3.X R3, R5, R3, RZ, P0, !PT ;\n /*05d0*/ MOV R2, R2 ;\n /*05e0*/ MOV R3, R3 ;\n /*05f0*/ MOV R2, R2 ;\n /*0600*/ MOV R3, R3 ;\n /*0610*/ R2UR UR4, R8 ;\n /*0620*/ R2UR UR5, R9 ;\n /*0630*/ STG.E [R2.64], R6 ;\n.L_x_0:\n /*0640*/ EXIT ;\n.L_x_1:\n /*0650*/ BRA `(.L_x_1);\n /*0660*/ NOP;\n /*0670*/ NOP;\n /*0680*/ NOP;\n /*0690*/ NOP;\n /*06a0*/ NOP;\n /*06b0*/ NOP;\n /*06c0*/ NOP;\n /*06d0*/ NOP;\n /*06e0*/ NOP;\n /*06f0*/ NOP;\n.L_x_2:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.protected\t_Z11transposeRCPjPfS0_jj ; -- Begin function _Z11transposeRCPjPfS0_jj\n\t.globl\t_Z11transposeRCPjPfS0_jj\n\t.p2align\t8\n\t.type\t_Z11transposeRCPjPfS0_jj,@function\n_Z11transposeRCPjPfS0_jj: ; @_Z11transposeRCPjPfS0_jj\n; %bb.0:\n\ts_load_b64 s[2:3], s[0:1], 0x18\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_ge_u32 s15, s2\n\ts_cbranch_scc1 .LBB0_3\n; %bb.1:\n\ts_load_b128 s[4:7], s[0:1], 0x0\n\ts_add_i32 s2, s3, 1\n\ts_mov_b32 s3, 0\n\ts_mul_i32 s2, s2, s15\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_lshl_b64 s[8:9], s[2:3], 2\n\ts_waitcnt lgkmcnt(0)\n\ts_add_u32 s8, s4, s8\n\ts_addc_u32 s9, s5, s9\n\ts_load_b32 s3, s[8:9], 0x0\n\ts_waitcnt lgkmcnt(0)\n\tv_cmp_gt_u32_e32 vcc_lo, s3, v0\n\ts_and_saveexec_b32 s3, vcc_lo\n\ts_cbranch_execz .LBB0_3\n; %bb.2:\n\tv_add3_u32 v0, v0, s2, 1\n\tv_mov_b32_e32 v1, 0\n\ts_load_b64 s[0:1], s[0:1], 0x10\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[2:3], 2, v[0:1]\n\tv_add_co_u32 v4, vcc_lo, s4, v2\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo\n\tv_add_co_u32 v2, vcc_lo, s6, v2\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo\n\tglobal_load_b32 v0, v[4:5], off\n\tglobal_load_b32 v2, v[2:3], off\n\ts_waitcnt vmcnt(1)\n\tv_lshlrev_b64 v[0:1], 2, v[0:1]\n\ts_waitcnt lgkmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, s0, v0\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo\n\ts_waitcnt vmcnt(0)\n\tglobal_store_b32 v[0:1], v2, off\n.LBB0_3:\n\ts_nop 0\n\ts_sendmsg sendmsg(MSG_DEALLOC_VGPRS)\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z11transposeRCPjPfS0_jj\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 32\n\t\t.amdhsa_user_sgpr_count 15\n\t\t.amdhsa_user_sgpr_dispatch_ptr 0\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 0\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 0\n\t\t.amdhsa_next_free_vgpr 6\n\t\t.amdhsa_next_free_sgpr 16\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end0:\n\t.size\t_Z11transposeRCPjPfS0_jj, .Lfunc_end0-_Z11transposeRCPjPfS0_jj\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 216\n; NumSgprs: 18\n; NumVgprs: 6\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 2\n; VGPRBlocks: 0\n; NumSGPRsForWavesPerEU: 18\n; NumVGPRsForWavesPerEU: 6\n; Occupancy: 16\n; WaveLimiterHint : 1\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 15\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 16\n .size: 8\n .value_kind: global_buffer\n - .offset: 24\n .size: 4\n .value_kind: by_value\n - .offset: 28\n .size: 4\n .value_kind: by_value\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 32\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z11transposeRCPjPfS0_jj\n .private_segment_fixed_size: 0\n .sgpr_count: 18\n .sgpr_spill_count: 0\n .symbol: _Z11transposeRCPjPfS0_jj.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 6\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162588,"cells":{"id":{"kind":"string","value":"524ec273ddb228581793d4a12b8d42a716f4987a_O2"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv --------------------------\n .section .text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=4\"\n .align 128\n\n\n\n\n .global _ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv\n .type _ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv,@function\n .size _ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv,(.L_x_12 - _ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv)\n .other _ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv:\n.text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ EXIT ;\n.L_x_0:\n /*0020*/ BRA `(.L_x_0);\n /*0030*/ NOP;\n /*0040*/ NOP;\n /*0050*/ NOP;\n /*0060*/ NOP;\n /*0070*/ NOP;\n /*0080*/ NOP;\n /*0090*/ NOP;\n /*00a0*/ NOP;\n /*00b0*/ NOP;\n /*00c0*/ NOP;\n /*00d0*/ NOP;\n /*00e0*/ NOP;\n /*00f0*/ NOP;\n.L_x_12:\n\n\n//--------------------- .text._Z18generateKeysKernelP17curandStateXORWOWPii --------------------------\n .section .text._Z18generateKeysKernelP17curandStateXORWOWPii,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=22\"\n .align 128\n\n\n\n\n .global _Z18generateKeysKernelP17curandStateXORWOWPii\n .type _Z18generateKeysKernelP17curandStateXORWOWPii,@function\n .size _Z18generateKeysKernelP17curandStateXORWOWPii,(.L_x_13 - _Z18generateKeysKernelP17curandStateXORWOWPii)\n .other _Z18generateKeysKernelP17curandStateXORWOWPii,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z18generateKeysKernelP17curandStateXORWOWPii:\n.text._Z18generateKeysKernelP17curandStateXORWOWPii:\n /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;\n /*0010*/ S2R R0, SR_CTAID.X ;\n /*0020*/ S2R R3, SR_TID.X ;\n /*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ;\n /*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ;\n /*0050*/ @P0 EXIT ;\n /*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x30 ;\n /*0070*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ;\n /*0090*/ LDG.E.64 R4, [R2.64] ;\n /*00a0*/ LDG.E.64 R8, [R2.64+0x10] ;\n /*00b0*/ LDG.E.64 R10, [R2.64+0x8] ;\n /*00c0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ;\n /*00d0*/ SHF.R.U32.HI R6, RZ, 0x2, R5 ;\n /*00e0*/ IADD3 R12, R4, 0x587c5, RZ ;\n /*00f0*/ LOP3.LUT R6, R6, R5, RZ, 0x3c, !PT ;\n /*0100*/ IMAD.SHL.U32 R5, R9.reuse, 0x10, RZ ;\n /*0110*/ MOV R17, R8 ;\n /*0120*/ IMAD.MOV.U32 R18, RZ, RZ, R9 ;\n /*0130*/ SHF.L.U32 R7, R6, 0x1, RZ ;\n /*0140*/ IMAD.MOV.U32 R13, RZ, RZ, R10 ;\n /*0150*/ MOV R16, R11 ;\n /*0160*/ LOP3.LUT R6, R9, R7, R6, 0x96, !PT ;\n /*0170*/ STG.E.64 [R2.64], R12 ;\n /*0180*/ LOP3.LUT R19, R6, R5, RZ, 0x3c, !PT ;\n /*0190*/ STG.E.64 [R2.64+0x8], R16 ;\n /*01a0*/ IADD3 R6, R19, R12, RZ ;\n /*01b0*/ STG.E.64 [R2.64+0x10], R18 ;\n /*01c0*/ IMAD.WIDE.U32 R4, R6, -0x2e48e8a7, RZ ;\n /*01d0*/ SHF.R.U32.HI R5, RZ, 0xd, R5 ;\n /*01e0*/ IMAD R7, R5, -0x2710, R6 ;\n /*01f0*/ IMAD.WIDE R4, R0, R15, c[0x0][0x168] ;\n /*0200*/ STG.E [R4.64], R7 ;\n /*0210*/ EXIT ;\n.L_x_1:\n /*0220*/ BRA `(.L_x_1);\n /*0230*/ NOP;\n /*0240*/ NOP;\n /*0250*/ NOP;\n /*0260*/ NOP;\n /*0270*/ NOP;\n /*0280*/ NOP;\n /*0290*/ NOP;\n /*02a0*/ NOP;\n /*02b0*/ NOP;\n /*02c0*/ NOP;\n /*02d0*/ NOP;\n /*02e0*/ NOP;\n /*02f0*/ NOP;\n.L_x_13:\n\n\n//--------------------- .text._Z16initRandomKernelP17curandStateXORWOWm --------------------------\n .section .text._Z16initRandomKernelP17curandStateXORWOWm,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=40\"\n .align 128\n\n\n\n\n .global _Z16initRandomKernelP17curandStateXORWOWm\n .type _Z16initRandomKernelP17curandStateXORWOWm,@function\n .size _Z16initRandomKernelP17curandStateXORWOWm,(.L_x_14 - _Z16initRandomKernelP17curandStateXORWOWm)\n .other _Z16initRandomKernelP17curandStateXORWOWm,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z16initRandomKernelP17curandStateXORWOWm:\n.text._Z16initRandomKernelP17curandStateXORWOWm:\n /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;\n /*0010*/ S2R R0, SR_CTAID.X ;\n /*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ;\n /*0030*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*0040*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ;\n /*0050*/ S2R R5, SR_TID.X ;\n /*0060*/ IMAD.MOV.U32 R7, RZ, RZ, 0x30 ;\n /*0070*/ LOP3.LUT R2, R2, 0xaad26b49, RZ, 0x3c, !PT ;\n /*0080*/ BSSY B0, `(.L_x_2) ;\n /*0090*/ LOP3.LUT R3, R3, 0xf7dcefdd, RZ, 0x3c, !PT ;\n /*00a0*/ IMAD R2, R2, 0x4182bed5, RZ ;\n /*00b0*/ IMAD R3, R3, -0x658354e5, RZ ;\n /*00c0*/ LOP3.LUT R8, R2.reuse, 0x159a55e5, RZ, 0x3c, !PT ;\n /*00d0*/ IADD3 R4, R2.reuse, 0x64f0c9, R3 ;\n /*00e0*/ IADD3 R9, R3.reuse, 0x1f123bb5, RZ ;\n /*00f0*/ LOP3.LUT R10, R3, 0x5491333, RZ, 0x3c, !PT ;\n /*0100*/ IADD3 R11, R2, 0x583f19, RZ ;\n /*0110*/ IMAD R0, R0, c[0x0][0x0], R5 ;\n /*0120*/ IADD3 R5, R2, 0x75bcd15, RZ ;\n /*0130*/ IMAD.WIDE R6, R0.reuse, R7, c[0x0][0x160] ;\n /*0140*/ ISETP.NE.AND P0, PT, R0, RZ, PT ;\n /*0150*/ STG.E.64 [R6.64], R4 ;\n /*0160*/ STG.E.64 [R6.64+0x8], R8 ;\n /*0170*/ STG.E.64 [R6.64+0x10], R10 ;\n /*0180*/ @!P0 BRA `(.L_x_3) ;\n /*0190*/ SHF.R.S32.HI R12, RZ, 0x1f, R0 ;\n /*01a0*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ;\n /*01b0*/ IMAD.MOV.U32 R14, RZ, RZ, R0 ;\n /*01c0*/ IMAD.MOV.U32 R15, RZ, RZ, R12 ;\n.L_x_9:\n /*01d0*/ LOP3.LUT P0, RZ, R14, 0x3, RZ, 0xc0, !PT ;\n /*01e0*/ BSSY B1, `(.L_x_4) ;\n /*01f0*/ @!P0 BRA `(.L_x_5) ;\n /*0200*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ;\n.L_x_8:\n /*0210*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ;\n /*0220*/ CS2R R4, SRZ ;\n /*0230*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ;\n /*0240*/ CS2R R2, SRZ ;\n.L_x_7:\n /*0250*/ IMAD.MOV.U32 R9, RZ, RZ, 0x30 ;\n /*0260*/ IMAD R11, R12, 0x30, RZ ;\n /*0270*/ IMAD.WIDE.U32 R8, R0, R9, c[0x0][0x160] ;\n /*0280*/ IMAD.IADD R9, R9, 0x1, R11 ;\n /*0290*/ IMAD.WIDE R10, R18, 0x4, R8 ;\n /*02a0*/ LDG.E R19, [R10.64+0x4] ;\n /*02b0*/ SHF.R.S32.HI R8, RZ, 0x1f, R13 ;\n /*02c0*/ IMAD.MOV.U32 R20, RZ, RZ, 0xc80 ;\n /*02d0*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ;\n /*02e0*/ IMAD R23, R8, 0xc80, RZ ;\n /*02f0*/ IMAD.WIDE.U32 R8, R13, R20, c[0x4][0x0] ;\n /*0300*/ IMAD.IADD R23, R9, 0x1, R23 ;\n.L_x_6:\n /*0310*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ;\n /*0320*/ IMAD R11, R18, 0x20, R21 ;\n /*0330*/ IMAD.MOV.U32 R22, RZ, RZ, R8 ;\n /*0340*/ SHF.L.U32 R10, R10, R21, RZ ;\n /*0350*/ IMAD R11, R11, 0x5, RZ ;\n /*0360*/ LOP3.LUT P4, RZ, R19, R10, RZ, 0xc0, !PT ;\n /*0370*/ IMAD.WIDE R10, R11, 0x4, R22 ;\n /*0380*/ @P4 LDG.E R20, [R10.64] ;\n /*0390*/ IMAD.MOV.U32 R22, RZ, RZ, 0x2 ;\n /*03a0*/ IMAD.MOV.U32 R26, RZ, RZ, 0x8 ;\n /*03b0*/ @P4 LDG.E R31, [R10.64+0xc] ;\n /*03c0*/ SHF.L.U32 R22, R22, R21.reuse, RZ ;\n /*03d0*/ @P4 LDG.E R30, [R10.64+0x10] ;\n /*03e0*/ LOP3.LUT P5, RZ, R19, R22, RZ, 0xc0, !PT ;\n /*03f0*/ IMAD.MOV.U32 R22, RZ, RZ, 0x4 ;\n /*0400*/ @P4 LDG.E R29, [R10.64+0x4] ;\n /*0410*/ SHF.L.U32 R22, R22, R21, RZ ;\n /*0420*/ LOP3.LUT P0, RZ, R19, R22, RZ, 0xc0, !PT ;\n /*0430*/ @P5 LDG.E R24, [R10.64+0x14] ;\n /*0440*/ SHF.L.U32 R22, R26, R21.reuse, RZ ;\n /*0450*/ IMAD.MOV.U32 R26, RZ, RZ, 0x10 ;\n /*0460*/ @P5 LDG.E R27, [R10.64+0x18] ;\n /*0470*/ LOP3.LUT P1, RZ, R19.reuse, R22, RZ, 0xc0, !PT ;\n /*0480*/ SHF.L.U32 R22, R26, R21, RZ ;\n /*0490*/ IMAD.MOV.U32 R26, RZ, RZ, 0x20 ;\n /*04a0*/ @P5 LDG.E R25, [R10.64+0x20] ;\n /*04b0*/ LOP3.LUT P3, RZ, R19, R22, RZ, 0xc0, !PT ;\n /*04c0*/ @P0 LDG.E R28, [R10.64+0x28] ;\n /*04d0*/ SHF.L.U32 R22, R26, R21, RZ ;\n /*04e0*/ @P4 LDG.E R26, [R10.64+0x8] ;\n /*04f0*/ @P1 LDG.E R32, [R10.64+0x3c] ;\n /*0500*/ LOP3.LUT P2, RZ, R19, R22, RZ, 0xc0, !PT ;\n /*0510*/ @P5 LDG.E R22, [R10.64+0x1c] ;\n /*0520*/ @P0 LDG.E R37, [R10.64+0x2c] ;\n /*0530*/ @P1 LDG.E R33, [R10.64+0x40] ;\n /*0540*/ @P1 LDG.E R35, [R10.64+0x48] ;\n /*0550*/ @P3 LDG.E R34, [R10.64+0x50] ;\n /*0560*/ @P2 LDG.E R36, [R10.64+0x64] ;\n /*0570*/ @P4 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ;\n /*0580*/ @P5 LDG.E R20, [R10.64+0x24] ;\n /*0590*/ @P5 LOP3.LUT R17, R17, R24, RZ, 0x3c, !PT ;\n /*05a0*/ @P4 LOP3.LUT R4, R4, R31, RZ, 0x3c, !PT ;\n /*05b0*/ @P2 LDG.E R24, [R10.64+0x6c] ;\n /*05c0*/ @P4 LOP3.LUT R5, R5, R30, RZ, 0x3c, !PT ;\n /*05d0*/ @P0 LDG.E R31, [R10.64+0x34] ;\n /*05e0*/ @P0 LDG.E R30, [R10.64+0x38] ;\n /*05f0*/ @P0 LOP3.LUT R17, R17, R28, RZ, 0x3c, !PT ;\n /*0600*/ @P0 LDG.E R28, [R10.64+0x30] ;\n /*0610*/ @P4 LOP3.LUT R2, R2, R29, RZ, 0x3c, !PT ;\n /*0620*/ @P4 LOP3.LUT R3, R3, R26, RZ, 0x3c, !PT ;\n /*0630*/ @P3 LDG.E R29, [R10.64+0x54] ;\n /*0640*/ @P1 LDG.E R26, [R10.64+0x4c] ;\n /*0650*/ @P1 LOP3.LUT R17, R17, R32, RZ, 0x3c, !PT ;\n /*0660*/ @P5 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ;\n /*0670*/ @P1 LDG.E R32, [R10.64+0x44] ;\n /*0680*/ @P3 LDG.E R27, [R10.64+0x5c] ;\n /*0690*/ @P5 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ;\n /*06a0*/ @P3 LDG.E R22, [R10.64+0x60] ;\n /*06b0*/ @P5 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ;\n /*06c0*/ @P2 LDG.E R25, [R10.64+0x68] ;\n /*06d0*/ @P5 LOP3.LUT R5, R5, R20, RZ, 0x3c, !PT ;\n /*06e0*/ @P3 LDG.E R20, [R10.64+0x58] ;\n /*06f0*/ @P0 LOP3.LUT R2, R2, R37, RZ, 0x3c, !PT ;\n /*0700*/ @P1 LOP3.LUT R2, R2, R33, RZ, 0x3c, !PT ;\n /*0710*/ @P0 LOP3.LUT R3, R3, R28, RZ, 0x3c, !PT ;\n /*0720*/ IMAD.MOV.U32 R28, RZ, RZ, 0x40 ;\n /*0730*/ SHF.L.U32 R28, R28, R21, RZ ;\n /*0740*/ LOP3.LUT P6, RZ, R19, R28, RZ, 0xc0, !PT ;\n /*0750*/ IMAD.MOV.U32 R28, RZ, RZ, 0x80 ;\n /*0760*/ SHF.L.U32 R28, R28, R21, RZ ;\n /*0770*/ @P0 LOP3.LUT R4, R4, R31, RZ, 0x3c, !PT ;\n /*0780*/ LOP3.LUT P5, RZ, R19, R28, RZ, 0xc0, !PT ;\n /*0790*/ @P2 LDG.E R31, [R10.64+0x70] ;\n /*07a0*/ @P0 LOP3.LUT R5, R5, R30, RZ, 0x3c, !PT ;\n /*07b0*/ @P2 LDG.E R28, [R10.64+0x74] ;\n /*07c0*/ @P1 LOP3.LUT R5, R5, R26, RZ, 0x3c, !PT ;\n /*07d0*/ @P1 LOP3.LUT R4, R4, R35, RZ, 0x3c, !PT ;\n /*07e0*/ @P6 LDG.E R26, [R10.64+0x78] ;\n /*07f0*/ @P1 LOP3.LUT R3, R3, R32, RZ, 0x3c, !PT ;\n /*0800*/ @P3 LOP3.LUT R2, R2, R29, RZ, 0x3c, !PT ;\n /*0810*/ @P6 LDG.E R30, [R10.64+0x80] ;\n /*0820*/ @P3 LOP3.LUT R4, R4, R27, RZ, 0x3c, !PT ;\n /*0830*/ @P6 LDG.E R29, [R10.64+0x7c] ;\n /*0840*/ @P6 LDG.E R27, [R10.64+0x84] ;\n /*0850*/ @P6 LDG.E R32, [R10.64+0x88] ;\n /*0860*/ @P3 LOP3.LUT R5, R5, R22, RZ, 0x3c, !PT ;\n /*0870*/ @P5 LDG.E R22, [R10.64+0x8c] ;\n /*0880*/ @P3 LOP3.LUT R17, R17, R34, RZ, 0x3c, !PT ;\n /*0890*/ @P2 LOP3.LUT R2, R2, R25, RZ, 0x3c, !PT ;\n /*08a0*/ @P5 LDG.E R33, [R10.64+0x90] ;\n /*08b0*/ @P5 LDG.E R34, [R10.64+0x94] ;\n /*08c0*/ @P5 LDG.E R25, [R10.64+0x98] ;\n /*08d0*/ @P3 LOP3.LUT R3, R3, R20, RZ, 0x3c, !PT ;\n /*08e0*/ @P5 LDG.E R20, [R10.64+0x9c] ;\n /*08f0*/ @P2 LOP3.LUT R3, R3, R24, RZ, 0x3c, !PT ;\n /*0900*/ IMAD.MOV.U32 R24, RZ, RZ, 0x100 ;\n /*0910*/ SHF.L.U32 R24, R24, R21, RZ ;\n /*0920*/ LOP3.LUT P0, RZ, R19, R24, RZ, 0xc0, !PT ;\n /*0930*/ IMAD.MOV.U32 R24, RZ, RZ, 0x200 ;\n /*0940*/ SHF.L.U32 R24, R24, R21, RZ ;\n /*0950*/ LOP3.LUT P1, RZ, R19, R24, RZ, 0xc0, !PT ;\n /*0960*/ IMAD.MOV.U32 R24, RZ, RZ, 0x400 ;\n /*0970*/ SHF.L.U32 R24, R24, R21, RZ ;\n /*0980*/ LOP3.LUT P4, RZ, R19, R24, RZ, 0xc0, !PT ;\n /*0990*/ IMAD.MOV.U32 R24, RZ, RZ, 0x800 ;\n /*09a0*/ SHF.L.U32 R24, R24, R21, RZ ;\n /*09b0*/ LOP3.LUT P3, RZ, R19, R24, RZ, 0xc0, !PT ;\n /*09c0*/ IMAD.MOV.U32 R24, RZ, RZ, 0x1000 ;\n /*09d0*/ @P2 LOP3.LUT R17, R17, R36, RZ, 0x3c, !PT ;\n /*09e0*/ SHF.L.U32 R24, R24, R21, RZ ;\n /*09f0*/ @P2 LOP3.LUT R4, R4, R31, RZ, 0x3c, !PT ;\n /*0a00*/ @P3 LDG.E R35, [R10.64+0xe8] ;\n /*0a10*/ @P2 LOP3.LUT R5, R5, R28, RZ, 0x3c, !PT ;\n /*0a20*/ LOP3.LUT P2, RZ, R19, R24, RZ, 0xc0, !PT ;\n /*0a30*/ IMAD.MOV.U32 R24, RZ, RZ, 0x2000 ;\n /*0a40*/ @P6 LOP3.LUT R17, R17, R26, RZ, 0x3c, !PT ;\n /*0a50*/ SHF.L.U32 R26, R24, R21, RZ ;\n /*0a60*/ @P0 LDG.E R24, [R10.64+0xa0] ;\n /*0a70*/ @P6 LOP3.LUT R3, R3, R30, RZ, 0x3c, !PT ;\n /*0a80*/ IMAD.MOV.U32 R28, RZ, RZ, 0x4000 ;\n /*0a90*/ @P6 LOP3.LUT R2, R2, R29, RZ, 0x3c, !PT ;\n /*0aa0*/ @P0 LDG.E R30, [R10.64+0xb0] ;\n /*0ab0*/ @P6 LOP3.LUT R4, R4, R27, RZ, 0x3c, !PT ;\n /*0ac0*/ @P0 LDG.E R27, [R10.64+0xa4] ;\n /*0ad0*/ @P6 LOP3.LUT R5, R5, R32, RZ, 0x3c, !PT ;\n /*0ae0*/ LOP3.LUT P6, RZ, R19, R26, RZ, 0xc0, !PT ;\n /*0af0*/ @P3 LDG.E R32, [R10.64+0xdc] ;\n /*0b00*/ @P5 LOP3.LUT R17, R17, R22, RZ, 0x3c, !PT ;\n /*0b10*/ @P1 LDG.E R26, [R10.64+0xb4] ;\n /*0b20*/ @P5 LOP3.LUT R2, R2, R33, RZ, 0x3c, !PT ;\n /*0b30*/ @P4 LDG.E R22, [R10.64+0xc8] ;\n /*0b40*/ @P5 LOP3.LUT R3, R3, R34, RZ, 0x3c, !PT ;\n /*0b50*/ @P2 LDG.E R34, [R10.64+0xf0] ;\n /*0b60*/ @P5 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ;\n /*0b70*/ @P0 LDG.E R29, [R10.64+0xac] ;\n /*0b80*/ @P6 LDG.E R36, [R10.64+0x104] ;\n /*0b90*/ @P1 LDG.E R25, [R10.64+0xb8] ;\n /*0ba0*/ @P3 LDG.E R33, [R10.64+0xe0] ;\n /*0bb0*/ @P5 LOP3.LUT R5, R5, R20, RZ, 0x3c, !PT ;\n /*0bc0*/ SHF.L.U32 R20, R28, R21, RZ ;\n /*0bd0*/ @P0 LDG.E R28, [R10.64+0xa8] ;\n /*0be0*/ LOP3.LUT P5, RZ, R19, R20, RZ, 0xc0, !PT ;\n /*0bf0*/ @P1 LDG.E R20, [R10.64+0xbc] ;\n /*0c00*/ @P5 LDG.E R31, [R10.64+0x118] ;\n /*0c10*/ @P0 LOP3.LUT R17, R17, R24, RZ, 0x3c, !PT ;\n /*0c20*/ @P4 LDG.E R24, [R10.64+0xd0] ;\n /*0c30*/ @P1 LOP3.LUT R17, R17, R26, RZ, 0x3c, !PT ;\n /*0c40*/ @P0 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ;\n /*0c50*/ @P4 LDG.E R26, [R10.64+0xd8] ;\n /*0c60*/ @P4 LOP3.LUT R17, R17, R22, RZ, 0x3c, !PT ;\n /*0c70*/ IMAD.MOV.U32 R22, RZ, RZ, 0x8000 ;\n /*0c80*/ @P0 LOP3.LUT R5, R5, R30, RZ, 0x3c, !PT ;\n /*0c90*/ @P1 LDG.E R27, [R10.64+0xc0] ;\n /*0ca0*/ @P3 LOP3.LUT R17, R17, R32, RZ, 0x3c, !PT ;\n /*0cb0*/ SHF.L.U32 R22, R22, R21, RZ ;\n /*0cc0*/ @P3 LDG.E R30, [R10.64+0xec] ;\n /*0cd0*/ @P2 LOP3.LUT R17, R17, R34, RZ, 0x3c, !PT ;\n /*0ce0*/ @P0 LOP3.LUT R4, R4, R29, RZ, 0x3c, !PT ;\n /*0cf0*/ @P6 LOP3.LUT R17, R17, R36, RZ, 0x3c, !PT ;\n /*0d00*/ @P4 LDG.E R29, [R10.64+0xcc] ;\n /*0d10*/ @P1 LOP3.LUT R2, R2, R25, RZ, 0x3c, !PT ;\n /*0d20*/ @P2 LDG.E R25, [R10.64+0xf4] ;\n /*0d30*/ @P0 LOP3.LUT R3, R3, R28, RZ, 0x3c, !PT ;\n /*0d40*/ LOP3.LUT P0, RZ, R19, R22, RZ, 0xc0, !PT ;\n /*0d50*/ @P3 LDG.E R28, [R10.64+0xe4] ;\n /*0d60*/ @P1 LDG.E R22, [R10.64+0xc4] ;\n /*0d70*/ @P1 LOP3.LUT R3, R3, R20, RZ, 0x3c, !PT ;\n /*0d80*/ @P2 LDG.E R20, [R10.64+0xf8] ;\n /*0d90*/ @P5 LOP3.LUT R17, R17, R31, RZ, 0x3c, !PT ;\n /*0da0*/ @P0 LDG.E R32, [R10.64+0x12c] ;\n /*0db0*/ @P4 LDG.E R31, [R10.64+0xd4] ;\n /*0dc0*/ @P0 LDG.E R37, [R10.64+0x138] ;\n /*0dd0*/ @P4 LOP3.LUT R3, R3, R24, RZ, 0x3c, !PT ;\n /*0de0*/ @P6 LDG.E R24, [R10.64+0x10c] ;\n /*0df0*/ @P1 LOP3.LUT R4, R4, R27, RZ, 0x3c, !PT ;\n /*0e00*/ @P2 LDG.E R27, [R10.64+0xfc] ;\n /*0e10*/ @P4 LOP3.LUT R2, R2, R29, RZ, 0x3c, !PT ;\n /*0e20*/ @P6 LDG.E R29, [R10.64+0x108] ;\n /*0e30*/ @P3 LOP3.LUT R2, R2, R33, RZ, 0x3c, !PT ;\n /*0e40*/ @P5 LDG.E R33, [R10.64+0x124] ;\n /*0e50*/ @P2 LOP3.LUT R2, R2, R25, RZ, 0x3c, !PT ;\n /*0e60*/ @P5 LDG.E R25, [R10.64+0x11c] ;\n /*0e70*/ @P3 LOP3.LUT R3, R3, R28, RZ, 0x3c, !PT ;\n /*0e80*/ @P5 LDG.E R28, [R10.64+0x120] ;\n /*0e90*/ @P1 LOP3.LUT R5, R5, R22, RZ, 0x3c, !PT ;\n /*0ea0*/ @P2 LDG.E R22, [R10.64+0x100] ;\n /*0eb0*/ @P4 LOP3.LUT R5, R5, R26, RZ, 0x3c, !PT ;\n /*0ec0*/ @P6 LDG.E R26, [R10.64+0x114] ;\n /*0ed0*/ @P2 LOP3.LUT R3, R3, R20, RZ, 0x3c, !PT ;\n /*0ee0*/ @P5 LDG.E R20, [R10.64+0x128] ;\n /*0ef0*/ @P4 LOP3.LUT R4, R4, R31, RZ, 0x3c, !PT ;\n /*0f00*/ @P6 LDG.E R31, [R10.64+0x110] ;\n /*0f10*/ @P0 LOP3.LUT R17, R17, R32, RZ, 0x3c, !PT ;\n /*0f20*/ @P3 LOP3.LUT R4, R4, R35, RZ, 0x3c, !PT ;\n /*0f30*/ @P0 LDG.E R32, [R10.64+0x13c] ;\n /*0f40*/ @P3 LOP3.LUT R5, R5, R30, RZ, 0x3c, !PT ;\n /*0f50*/ @P0 LDG.E R35, [R10.64+0x130] ;\n /*0f60*/ @P0 LDG.E R30, [R10.64+0x134] ;\n /*0f70*/ IADD3 R21, R21, 0x10, RZ ;\n /*0f80*/ ISETP.NE.AND P1, PT, R21, 0x20, PT ;\n /*0f90*/ @P6 LOP3.LUT R3, R3, R24, RZ, 0x3c, !PT ;\n /*0fa0*/ @P2 LOP3.LUT R4, R4, R27, RZ, 0x3c, !PT ;\n /*0fb0*/ @P6 LOP3.LUT R2, R2, R29, RZ, 0x3c, !PT ;\n /*0fc0*/ @P5 LOP3.LUT R2, R2, R25, RZ, 0x3c, !PT ;\n /*0fd0*/ @P2 LOP3.LUT R5, R5, R22, RZ, 0x3c, !PT ;\n /*0fe0*/ @P6 LOP3.LUT R5, R5, R26, RZ, 0x3c, !PT ;\n /*0ff0*/ @P5 LOP3.LUT R3, R3, R28, RZ, 0x3c, !PT ;\n /*1000*/ @P5 LOP3.LUT R5, R5, R20, RZ, 0x3c, !PT ;\n /*1010*/ @P6 LOP3.LUT R4, R4, R31, RZ, 0x3c, !PT ;\n /*1020*/ @P5 LOP3.LUT R4, R4, R33, RZ, 0x3c, !PT ;\n /*1030*/ @P0 LOP3.LUT R5, R5, R32, RZ, 0x3c, !PT ;\n /*1040*/ @P0 LOP3.LUT R2, R2, R35, RZ, 0x3c, !PT ;\n /*1050*/ @P0 LOP3.LUT R4, R4, R37, RZ, 0x3c, !PT ;\n /*1060*/ @P0 LOP3.LUT R3, R3, R30, RZ, 0x3c, !PT ;\n /*1070*/ @P1 BRA `(.L_x_6) ;\n /*1080*/ IADD3 R18, R18, 0x1, RZ ;\n /*1090*/ ISETP.GE.U32.AND P0, PT, R18, 0x5, PT ;\n /*10a0*/ @!P0 BRA `(.L_x_7) ;\n /*10b0*/ IADD3 R16, R16, 0x1, RZ ;\n /*10c0*/ STG.E.64 [R6.64+0x8], R2 ;\n /*10d0*/ LOP3.LUT R9, R14, 0x3, RZ, 0xc0, !PT ;\n /*10e0*/ STG.E.64 [R6.64+0x10], R4 ;\n /*10f0*/ ISETP.GT.U32.AND P0, PT, R9, R16, PT ;\n /*1100*/ STG.E [R6.64+0x4], R17 ;\n /*1110*/ ISETP.GT.U32.AND.EX P0, PT, RZ, RZ, PT, P0 ;\n /*1120*/ @P0 BRA `(.L_x_8) ;\n.L_x_5:\n /*1130*/ BSYNC B1 ;\n.L_x_4:\n /*1140*/ SHF.R.U64 R14, R14, 0x2, R15.reuse ;\n /*1150*/ SHF.R.U32.HI R15, RZ, 0x2, R15 ;\n /*1160*/ ISETP.NE.U32.AND P0, PT, R14, RZ, PT ;\n /*1170*/ IADD3 R13, R13, 0x1, RZ ;\n /*1180*/ ISETP.NE.AND.EX P0, PT, R15, RZ, PT, P0 ;\n /*1190*/ @!P0 CALL.REL.NOINC `(.L_x_3) ;\n /*11a0*/ BRA `(.L_x_9) ;\n.L_x_3:\n /*11b0*/ BSYNC B0 ;\n.L_x_2:\n /*11c0*/ STG.E.64 [R6.64+0x18], RZ ;\n /*11d0*/ STG.E [R6.64+0x20], RZ ;\n /*11e0*/ STG.E.64 [R6.64+0x28], RZ ;\n /*11f0*/ EXIT ;\n.L_x_10:\n /*1200*/ BRA `(.L_x_10);\n /*1210*/ NOP;\n /*1220*/ NOP;\n /*1230*/ NOP;\n /*1240*/ NOP;\n /*1250*/ NOP;\n /*1260*/ NOP;\n /*1270*/ NOP;\n /*1280*/ NOP;\n /*1290*/ NOP;\n /*12a0*/ NOP;\n /*12b0*/ NOP;\n /*12c0*/ NOP;\n /*12d0*/ NOP;\n /*12e0*/ NOP;\n /*12f0*/ NOP;\n.L_x_14:\n\n\n//--------------------- .text._Z12insertKernelPiS_S_i --------------------------\n .section .text._Z12insertKernelPiS_S_i,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=14\"\n .align 128\n\n\n\n\n .global _Z12insertKernelPiS_S_i\n .type _Z12insertKernelPiS_S_i,@function\n .size _Z12insertKernelPiS_S_i,(.L_x_15 - _Z12insertKernelPiS_S_i)\n .other _Z12insertKernelPiS_S_i,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z12insertKernelPiS_S_i:\n.text._Z12insertKernelPiS_S_i:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ S2R R2, SR_CTAID.X ;\n /*0020*/ S2R R3, SR_TID.X ;\n /*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ;\n /*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x178], PT ;\n /*0050*/ @P0 EXIT ;\n /*0060*/ MOV R7, 0x4 ;\n /*0070*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*0080*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ;\n /*0090*/ LDG.E R0, [R2.64] ;\n /*00a0*/ MOV R11, 0x1 ;\n /*00b0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ;\n /*00c0*/ LEA.HI R5, R5, R0, RZ, 0xa ;\n /*00d0*/ LOP3.LUT R5, R5, 0xfffffc00, RZ, 0xc0, !PT ;\n /*00e0*/ IMAD.IADD R0, R0, 0x1, -R5 ;\n /*00f0*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x170] ;\n /*0100*/ ATOMG.E.ADD.STRONG.GPU PT, R5, [R4.64], R11 ;\n /*0110*/ LDG.E R9, [R2.64] ;\n /*0120*/ IMAD R6, R0, 0x100, R5 ;\n /*0130*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x168] ;\n /*0140*/ STG.E [R6.64], R9 ;\n /*0150*/ EXIT ;\n.L_x_11:\n /*0160*/ BRA `(.L_x_11);\n /*0170*/ NOP;\n /*0180*/ NOP;\n /*0190*/ NOP;\n /*01a0*/ NOP;\n /*01b0*/ NOP;\n /*01c0*/ NOP;\n /*01d0*/ NOP;\n /*01e0*/ NOP;\n /*01f0*/ NOP;\n.L_x_15:\n"},"hip":{"kind":"string","value":"\t.text\n\t.file\t\"cuda_code_063793.hip\"\n\t.globl\t_Z27__device_stub__insertKernelPiS_S_i # -- Begin function _Z27__device_stub__insertKernelPiS_S_i\n\t.p2align\t4, 0x90\n\t.type\t_Z27__device_stub__insertKernelPiS_S_i,@function\n_Z27__device_stub__insertKernelPiS_S_i: # @_Z27__device_stub__insertKernelPiS_S_i\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$120, %rsp\n\t.cfi_def_cfa_offset 128\n\tmovq\t%rdi, 72(%rsp)\n\tmovq\t%rsi, 64(%rsp)\n\tmovq\t%rdx, 56(%rsp)\n\tmovl\t%ecx, 4(%rsp)\n\tleaq\t72(%rsp), %rax\n\tmovq\t%rax, 80(%rsp)\n\tleaq\t64(%rsp), %rax\n\tmovq\t%rax, 88(%rsp)\n\tleaq\t56(%rsp), %rax\n\tmovq\t%rax, 96(%rsp)\n\tleaq\t4(%rsp), %rax\n\tmovq\t%rax, 104(%rsp)\n\tleaq\t40(%rsp), %rdi\n\tleaq\t24(%rsp), %rsi\n\tleaq\t16(%rsp), %rdx\n\tleaq\t8(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t40(%rsp), %rsi\n\tmovl\t48(%rsp), %edx\n\tmovq\t24(%rsp), %rcx\n\tmovl\t32(%rsp), %r8d\n\tleaq\t80(%rsp), %r9\n\tmovl\t$_Z12insertKernelPiS_S_i, %edi\n\tpushq\t8(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t24(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$136, %rsp\n\t.cfi_adjust_cfa_offset -136\n\tretq\n.Lfunc_end0:\n\t.size\t_Z27__device_stub__insertKernelPiS_S_i, .Lfunc_end0-_Z27__device_stub__insertKernelPiS_S_i\n\t.cfi_endproc\n # -- End function\n\t.globl\t_Z31__device_stub__initRandomKernelP12hiprandStatem # -- Begin function _Z31__device_stub__initRandomKernelP12hiprandStatem\n\t.p2align\t4, 0x90\n\t.type\t_Z31__device_stub__initRandomKernelP12hiprandStatem,@function\n_Z31__device_stub__initRandomKernelP12hiprandStatem: # @_Z31__device_stub__initRandomKernelP12hiprandStatem\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$88, %rsp\n\t.cfi_def_cfa_offset 96\n\tmovq\t%rdi, 56(%rsp)\n\tmovq\t%rsi, 48(%rsp)\n\tleaq\t56(%rsp), %rax\n\tmovq\t%rax, 64(%rsp)\n\tleaq\t48(%rsp), %rax\n\tmovq\t%rax, 72(%rsp)\n\tleaq\t32(%rsp), %rdi\n\tleaq\t16(%rsp), %rsi\n\tleaq\t8(%rsp), %rdx\n\tmovq\t%rsp, %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t32(%rsp), %rsi\n\tmovl\t40(%rsp), %edx\n\tmovq\t16(%rsp), %rcx\n\tmovl\t24(%rsp), %r8d\n\tleaq\t64(%rsp), %r9\n\tmovl\t$_Z16initRandomKernelP12hiprandStatem, %edi\n\tpushq\t(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t16(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$104, %rsp\n\t.cfi_adjust_cfa_offset -104\n\tretq\n.Lfunc_end1:\n\t.size\t_Z31__device_stub__initRandomKernelP12hiprandStatem, .Lfunc_end1-_Z31__device_stub__initRandomKernelP12hiprandStatem\n\t.cfi_endproc\n # -- End function\n\t.globl\t_Z33__device_stub__generateKeysKernelP12hiprandStatePii # -- Begin function _Z33__device_stub__generateKeysKernelP12hiprandStatePii\n\t.p2align\t4, 0x90\n\t.type\t_Z33__device_stub__generateKeysKernelP12hiprandStatePii,@function\n_Z33__device_stub__generateKeysKernelP12hiprandStatePii: # @_Z33__device_stub__generateKeysKernelP12hiprandStatePii\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$104, %rsp\n\t.cfi_def_cfa_offset 112\n\tmovq\t%rdi, 72(%rsp)\n\tmovq\t%rsi, 64(%rsp)\n\tmovl\t%edx, 12(%rsp)\n\tleaq\t72(%rsp), %rax\n\tmovq\t%rax, 80(%rsp)\n\tleaq\t64(%rsp), %rax\n\tmovq\t%rax, 88(%rsp)\n\tleaq\t12(%rsp), %rax\n\tmovq\t%rax, 96(%rsp)\n\tleaq\t48(%rsp), %rdi\n\tleaq\t32(%rsp), %rsi\n\tleaq\t24(%rsp), %rdx\n\tleaq\t16(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t48(%rsp), %rsi\n\tmovl\t56(%rsp), %edx\n\tmovq\t32(%rsp), %rcx\n\tmovl\t40(%rsp), %r8d\n\tleaq\t80(%rsp), %r9\n\tmovl\t$_Z18generateKeysKernelP12hiprandStatePii, %edi\n\tpushq\t16(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t32(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$120, %rsp\n\t.cfi_adjust_cfa_offset -120\n\tretq\n.Lfunc_end2:\n\t.size\t_Z33__device_stub__generateKeysKernelP12hiprandStatePii, .Lfunc_end2-_Z33__device_stub__generateKeysKernelP12hiprandStatePii\n\t.cfi_endproc\n # -- End function\n\t.globl\tmain # -- Begin function main\n\t.p2align\t4, 0x90\n\t.type\tmain,@function\nmain: # @main\n.Lfunc_begin0:\n\t.cfi_startproc\n\t.cfi_personality 3, __gxx_personality_v0\n\t.cfi_lsda 3, .Lexception0\n# %bb.0:\n\tpushq\t%rbp\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r15\n\t.cfi_def_cfa_offset 24\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 32\n\tpushq\t%r13\n\t.cfi_def_cfa_offset 40\n\tpushq\t%r12\n\t.cfi_def_cfa_offset 48\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 56\n\tsubq\t$200, %rsp\n\t.cfi_def_cfa_offset 256\n\t.cfi_offset %rbx, -56\n\t.cfi_offset %r12, -48\n\t.cfi_offset %r13, -40\n\t.cfi_offset %r14, -32\n\t.cfi_offset %r15, -24\n\t.cfi_offset %rbp, -16\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$8192, %edi # imm = 0x2000\n\tcallq\t_Znwm\n\t.cfi_escape 0x2e, 0x00\n\txorl\t%r12d, %r12d\n\tmovl\t$8192, %edx # imm = 0x2000\n\tmovq\t%rax, 8(%rsp) # 8-byte Spill\n\tmovq\t%rax, %rdi\n\txorl\t%esi, %esi\n\tcallq\tmemset@PLT\n\tmovb\t$1, %r15b\n\t.p2align\t4, 0x90\n.LBB3_1: # =>This Inner Loop Header: Depth=1\n.Ltmp0:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%r12d, %edi\n\tcallq\thipSetDevice\n.Ltmp1:\n# %bb.2: # in Loop: Header=BB3_1 Depth=1\n\tmovl\t%eax, %ebx\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_3\n# %bb.23: # in Loop: Header=BB3_1 Depth=1\n\tleaq\t(%rsp,%r12,8), %r13\n\taddq\t$176, %r13\n.Ltmp20:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1048576, %esi # imm = 0x100000\n\tmovq\t%r13, %rdi\n\tcallq\thipMalloc\n.Ltmp21:\n# %bb.24: # in Loop: Header=BB3_1 Depth=1\n\tmovl\t%eax, %ebx\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_25\n# %bb.36: # in Loop: Header=BB3_1 Depth=1\n\tleaq\t(%rsp,%r12,8), %rbp\n\taddq\t$128, %rbp\n.Ltmp40:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$4096, %esi # imm = 0x1000\n\tmovq\t%rbp, %rdi\n\tcallq\thipMalloc\n.Ltmp41:\n# %bb.37: # in Loop: Header=BB3_1 Depth=1\n\tmovl\t%eax, %ebx\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_38\n# %bb.49: # in Loop: Header=BB3_1 Depth=1\n\tleaq\t(%rsp,%r12,8), %r14\n\taddq\t$160, %r14\n.Ltmp60:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$6291456, %esi # imm = 0x600000\n\tmovq\t%r14, %rdi\n\tcallq\thipMalloc\n.Ltmp61:\n# %bb.50: # in Loop: Header=BB3_1 Depth=1\n\tmovl\t%eax, %ebx\n\tmovl\t%r15d, 88(%rsp) # 4-byte Spill\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_51\n# %bb.62: # in Loop: Header=BB3_1 Depth=1\n\tleaq\t(%rsp,%r12,8), %rbx\n\taddq\t$144, %rbx\n.Ltmp80:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$262144, %esi # imm = 0x40000\n\tmovq\t%rbx, %rdi\n\tcallq\thipMalloc\n.Ltmp81:\n# %bb.63: # in Loop: Header=BB3_1 Depth=1\n\tmovl\t%eax, %r15d\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_64\n# %bb.75: # in Loop: Header=BB3_1 Depth=1\n.Ltmp100:\n\t.cfi_escape 0x2e, 0x00\n\tmovabsq\t$4294967808, %rdi # imm = 0x100000200\n\tmovl\t$1, %esi\n\tmovabsq\t$4294967552, %rdx # imm = 0x100000100\n\tmovl\t$1, %ecx\n\txorl\t%r8d, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipPushCallConfiguration\n.Ltmp101:\n# %bb.76: # in Loop: Header=BB3_1 Depth=1\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_79\n# %bb.77: # in Loop: Header=BB3_1 Depth=1\n\tmovq\t(%r14), %r15\n\t.cfi_escape 0x2e, 0x00\n\txorl\t%edi, %edi\n\tcallq\ttime\n\tmovq\t%r15, 72(%rsp)\n\tmovq\t%rax, 64(%rsp)\n\tleaq\t72(%rsp), %rax\n\tmovq\t%rax, 96(%rsp)\n\tleaq\t64(%rsp), %rax\n\tmovq\t%rax, 104(%rsp)\n.Ltmp102:\n\t.cfi_escape 0x2e, 0x00\n\tleaq\t40(%rsp), %rdi\n\tleaq\t24(%rsp), %rsi\n\tleaq\t56(%rsp), %rdx\n\tleaq\t16(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n.Ltmp103:\n# %bb.78: # in Loop: Header=BB3_1 Depth=1\n\tmovq\t40(%rsp), %rsi\n\tmovl\t48(%rsp), %edx\n\tmovq\t24(%rsp), %rcx\n\tmovl\t32(%rsp), %r8d\n.Ltmp104:\n\t.cfi_escape 0x2e, 0x10\n\tmovl\t$_Z16initRandomKernelP12hiprandStatem, %edi\n\tleaq\t96(%rsp), %r9\n\tpushq\t16(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t64(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$16, %rsp\n\t.cfi_adjust_cfa_offset -16\n.Ltmp105:\n.LBB3_79: # in Loop: Header=BB3_1 Depth=1\n.Ltmp106:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipGetLastError\n.Ltmp107:\n# %bb.80: # in Loop: Header=BB3_1 Depth=1\n\tmovl\t%eax, %r15d\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_81\n# %bb.92: # in Loop: Header=BB3_1 Depth=1\n.Ltmp126:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipDeviceSynchronize\n.Ltmp127:\n# %bb.93: # in Loop: Header=BB3_1 Depth=1\n\tmovl\t%eax, %r15d\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_94\n# %bb.105: # in Loop: Header=BB3_1 Depth=1\n.Ltmp146:\n\t.cfi_escape 0x2e, 0x00\n\tmovabsq\t$4294967552, %rdi # imm = 0x100000100\n\tmovl\t$1, %esi\n\tmovq\t%rdi, %rdx\n\tmovl\t$1, %ecx\n\txorl\t%r8d, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipPushCallConfiguration\n.Ltmp147:\n# %bb.106: # in Loop: Header=BB3_1 Depth=1\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_109\n# %bb.107: # in Loop: Header=BB3_1 Depth=1\n\tmovq\t(%r14), %rax\n\tmovq\t(%rbx), %rcx\n\tmovq\t%rax, 72(%rsp)\n\tmovq\t%rcx, 64(%rsp)\n\tmovl\t$65536, 80(%rsp) # imm = 0x10000\n\tleaq\t72(%rsp), %rax\n\tmovq\t%rax, 96(%rsp)\n\tleaq\t64(%rsp), %rax\n\tmovq\t%rax, 104(%rsp)\n\tleaq\t80(%rsp), %rax\n\tmovq\t%rax, 112(%rsp)\n.Ltmp148:\n\t.cfi_escape 0x2e, 0x00\n\tleaq\t40(%rsp), %rdi\n\tleaq\t24(%rsp), %rsi\n\tleaq\t56(%rsp), %rdx\n\tleaq\t16(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n.Ltmp149:\n# %bb.108: # in Loop: Header=BB3_1 Depth=1\n\tmovq\t40(%rsp), %rsi\n\tmovl\t48(%rsp), %edx\n\tmovq\t24(%rsp), %rcx\n\tmovl\t32(%rsp), %r8d\n.Ltmp150:\n\t.cfi_escape 0x2e, 0x10\n\tmovl\t$_Z18generateKeysKernelP12hiprandStatePii, %edi\n\tleaq\t96(%rsp), %r9\n\tpushq\t16(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t64(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$16, %rsp\n\t.cfi_adjust_cfa_offset -16\n.Ltmp151:\n.LBB3_109: # in Loop: Header=BB3_1 Depth=1\n.Ltmp152:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipGetLastError\n.Ltmp153:\n# %bb.110: # in Loop: Header=BB3_1 Depth=1\n\tmovl\t%eax, %r15d\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_111\n# %bb.122: # in Loop: Header=BB3_1 Depth=1\n.Ltmp172:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipDeviceSynchronize\n.Ltmp173:\n# %bb.123: # in Loop: Header=BB3_1 Depth=1\n\tmovl\t%eax, %r15d\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_124\n# %bb.135: # in Loop: Header=BB3_1 Depth=1\n\tmovq\t128(%rsp,%r12,8), %rdi\n\tshlq\t$12, %r12\n\taddq\t8(%rsp), %r12 # 8-byte Folded Reload\n.Ltmp192:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$4096, %edx # imm = 0x1000\n\tmovq\t%r12, %rsi\n\tmovl\t$1, %ecx\n\tcallq\thipMemcpy\n.Ltmp193:\n# %bb.136: # in Loop: Header=BB3_1 Depth=1\n\tmovl\t%eax, %r15d\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_137\n# %bb.148: # in Loop: Header=BB3_1 Depth=1\n.Ltmp212:\n\t.cfi_escape 0x2e, 0x00\n\tmovabsq\t$4294967552, %rdi # imm = 0x100000100\n\tmovl\t$1, %esi\n\tmovq\t%rdi, %rdx\n\tmovl\t$1, %ecx\n\txorl\t%r8d, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipPushCallConfiguration\n.Ltmp213:\n# %bb.149: # in Loop: Header=BB3_1 Depth=1\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_152\n# %bb.150: # in Loop: Header=BB3_1 Depth=1\n\tmovq\t(%rbx), %rax\n\tmovq\t(%r13), %rcx\n\tmovq\t(%rbp), %rdx\n\tmovq\t%rax, 72(%rsp)\n\tmovq\t%rcx, 64(%rsp)\n\tmovq\t%rdx, 56(%rsp)\n\tmovl\t$65536, 92(%rsp) # imm = 0x10000\n\tleaq\t72(%rsp), %rax\n\tmovq\t%rax, 96(%rsp)\n\tleaq\t64(%rsp), %rax\n\tmovq\t%rax, 104(%rsp)\n\tleaq\t56(%rsp), %rax\n\tmovq\t%rax, 112(%rsp)\n\tleaq\t92(%rsp), %rax\n\tmovq\t%rax, 120(%rsp)\n.Ltmp214:\n\t.cfi_escape 0x2e, 0x00\n\tleaq\t40(%rsp), %rdi\n\tleaq\t24(%rsp), %rsi\n\tleaq\t16(%rsp), %rdx\n\tleaq\t80(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n.Ltmp215:\n# %bb.151: # in Loop: Header=BB3_1 Depth=1\n\tmovq\t40(%rsp), %rsi\n\tmovl\t48(%rsp), %edx\n\tmovq\t24(%rsp), %rcx\n\tmovl\t32(%rsp), %r8d\n.Ltmp216:\n\t.cfi_escape 0x2e, 0x10\n\tmovl\t$_Z12insertKernelPiS_S_i, %edi\n\tleaq\t96(%rsp), %r9\n\tpushq\t80(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t24(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$16, %rsp\n\t.cfi_adjust_cfa_offset -16\n.Ltmp217:\n.LBB3_152: # in Loop: Header=BB3_1 Depth=1\n.Ltmp219:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipGetLastError\n.Ltmp220:\n# %bb.153: # in Loop: Header=BB3_1 Depth=1\n\tmovl\t%eax, %r15d\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_154\n# %bb.165: # in Loop: Header=BB3_1 Depth=1\n.Ltmp239:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipDeviceSynchronize\n.Ltmp240:\n# %bb.166: # in Loop: Header=BB3_1 Depth=1\n\tmovl\t%eax, %r15d\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_167\n# %bb.178: # in Loop: Header=BB3_1 Depth=1\n\tmovq\t(%rbp), %rsi\n.Ltmp259:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$4096, %edx # imm = 0x1000\n\tmovq\t%r12, %rdi\n\tmovl\t$2, %ecx\n\tcallq\thipMemcpy\n.Ltmp260:\n# %bb.179: # in Loop: Header=BB3_1 Depth=1\n\tmovl\t%eax, %r15d\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_180\n# %bb.191: # in Loop: Header=BB3_1 Depth=1\n\tmovq\t(%r13), %rdi\n.Ltmp279:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipFree\n.Ltmp280:\n# %bb.192: # in Loop: Header=BB3_1 Depth=1\n\tmovl\t%eax, %r15d\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_193\n# %bb.204: # in Loop: Header=BB3_1 Depth=1\n\tmovq\t(%rbp), %rdi\n.Ltmp299:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipFree\n.Ltmp300:\n# %bb.205: # in Loop: Header=BB3_1 Depth=1\n\tmovl\t%eax, %ebp\n\ttestl\t%eax, %eax\n\tmovl\t88(%rsp), %r15d # 4-byte Reload\n\tjne\t.LBB3_206\n# %bb.217: # in Loop: Header=BB3_1 Depth=1\n\tmovq\t(%r14), %rdi\n.Ltmp319:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipFree\n.Ltmp320:\n# %bb.218: # in Loop: Header=BB3_1 Depth=1\n\tmovl\t%eax, %ebp\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_219\n# %bb.230: # in Loop: Header=BB3_1 Depth=1\n\tmovq\t(%rbx), %rdi\n.Ltmp339:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\thipFree\n.Ltmp340:\n# %bb.231: # in Loop: Header=BB3_1 Depth=1\n\tmovl\t%eax, %ebx\n\ttestl\t%eax, %eax\n\tjne\t.LBB3_232\n# %bb.12: # in Loop: Header=BB3_1 Depth=1\n\tmovl\t$1, %r12d\n\ttestb\t$1, %r15b\n\tmovl\t$0, %r15d\n\tjne\t.LBB3_1\n# %bb.13:\n\txorl\t%ebx, %ebx\n\tjmp\t.LBB3_14\n\t.p2align\t4, 0x90\n.LBB3_250: # in Loop: Header=BB3_14 Depth=1\n\tincq\t%rbx\n\tcmpq\t$2048, %rbx # imm = 0x800\n\tje\t.LBB3_251\n.LBB3_14: # =>This Inner Loop Header: Depth=1\n\tmovq\t8(%rsp), %rax # 8-byte Reload\n\tcmpl\t$0, (%rax,%rbx,4)\n\tjle\t.LBB3_250\n# %bb.15: # in Loop: Header=BB3_14 Depth=1\n.Ltmp359:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cout, %edi\n\tmovl\t$.L.str.4, %esi\n\tmovl\t$7, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp360:\n# %bb.16: # in Loop: Header=BB3_14 Depth=1\n.Ltmp361:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cout, %edi\n\tmovl\t%ebx, %esi\n\tcallq\t_ZNSolsEi\n.Ltmp362:\n# %bb.17: # in Loop: Header=BB3_14 Depth=1\n.Ltmp363:\n\tmovq\t%rax, %r14\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.5, %esi\n\tmovl\t$5, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp364:\n# %bb.18: # in Loop: Header=BB3_14 Depth=1\n\tmovq\t8(%rsp), %rax # 8-byte Reload\n\tmovl\t(%rax,%rbx,4), %esi\n.Ltmp365:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%r14, %rdi\n\tcallq\t_ZNSolsEi\n.Ltmp366:\n# %bb.19: # in Loop: Header=BB3_14 Depth=1\n.Ltmp367:\n\tmovq\t%rax, %r14\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.6, %esi\n\tmovl\t$10, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp368:\n# %bb.20: # in Loop: Header=BB3_14 Depth=1\n\tmovq\t(%r14), %rax\n\tmovq\t-24(%rax), %rax\n\tmovq\t240(%r14,%rax), %r15\n\ttestq\t%r15, %r15\n\tje\t.LBB3_21\n# %bb.244: # in Loop: Header=BB3_14 Depth=1\n\tcmpb\t$0, 56(%r15)\n\tje\t.LBB3_246\n# %bb.245: # in Loop: Header=BB3_14 Depth=1\n\tmovzbl\t67(%r15), %eax\n\tjmp\t.LBB3_248\n\t.p2align\t4, 0x90\n.LBB3_246: # in Loop: Header=BB3_14 Depth=1\n.Ltmp369:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%r15, %rdi\n\tcallq\t_ZNKSt5ctypeIcE13_M_widen_initEv\n.Ltmp370:\n# %bb.247: # in Loop: Header=BB3_14 Depth=1\n\tmovq\t(%r15), %rax\n.Ltmp371:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%r15, %rdi\n\tmovl\t$10, %esi\n\tcallq\t*48(%rax)\n.Ltmp372:\n.LBB3_248: # in Loop: Header=BB3_14 Depth=1\n.Ltmp373:\n\t.cfi_escape 0x2e, 0x00\n\tmovsbl\t%al, %esi\n\tmovq\t%r14, %rdi\n\tcallq\t_ZNSo3putEc\n.Ltmp374:\n# %bb.249: # in Loop: Header=BB3_14 Depth=1\n.Ltmp375:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZNSo5flushEv\n.Ltmp376:\n\tjmp\t.LBB3_250\n.LBB3_251:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t8(%rsp), %rdi # 8-byte Reload\n\tcallq\t_ZdlPv\n\txorl\t%eax, %eax\n\taddq\t$200, %rsp\n\t.cfi_def_cfa_offset 56\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 48\n\tpopq\t%r12\n\t.cfi_def_cfa_offset 40\n\tpopq\t%r13\n\t.cfi_def_cfa_offset 32\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r15\n\t.cfi_def_cfa_offset 16\n\tpopq\t%rbp\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB3_94:\n\t.cfi_def_cfa_offset 256\n.Ltmp129:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$12, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp130:\n# %bb.95:\n.Ltmp131:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%r15d, %edi\n\tcallq\thipGetErrorString\n.Ltmp132:\n# %bb.96:\n.Ltmp133:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rax, %rsi\n\tcallq\t_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc\n.Ltmp134:\n# %bb.97:\n.Ltmp135:\n\tmovq\t%rax, %rbx\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$4, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp136:\n# %bb.98:\n.Ltmp137:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$41, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp138:\n# %bb.99:\n.Ltmp139:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.3, %esi\n\tmovl\t$9, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp140:\n# %bb.100:\n.Ltmp141:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tmovl\t$77, %esi\n\tcallq\t_ZNSolsEi\n.Ltmp142:\n# %bb.101:\n.Ltmp143:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_\n.Ltmp144:\n# %bb.102:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %edi\n\tcallq\texit\n.LBB3_81:\n.Ltmp109:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$12, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp110:\n# %bb.82:\n.Ltmp111:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%r15d, %edi\n\tcallq\thipGetErrorString\n.Ltmp112:\n# %bb.83:\n.Ltmp113:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rax, %rsi\n\tcallq\t_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc\n.Ltmp114:\n# %bb.84:\n.Ltmp115:\n\tmovq\t%rax, %rbx\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$4, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp116:\n# %bb.85:\n.Ltmp117:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$41, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp118:\n# %bb.86:\n.Ltmp119:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.3, %esi\n\tmovl\t$9, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp120:\n# %bb.87:\n.Ltmp121:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tmovl\t$76, %esi\n\tcallq\t_ZNSolsEi\n.Ltmp122:\n# %bb.88:\n.Ltmp123:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_\n.Ltmp124:\n# %bb.89:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %edi\n\tcallq\texit\n.LBB3_64:\n.Ltmp83:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$12, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp84:\n# %bb.65:\n.Ltmp85:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%r15d, %edi\n\tcallq\thipGetErrorString\n.Ltmp86:\n# %bb.66:\n.Ltmp87:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rax, %rsi\n\tcallq\t_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc\n.Ltmp88:\n# %bb.67:\n.Ltmp89:\n\tmovq\t%rax, %rbx\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$4, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp90:\n# %bb.68:\n.Ltmp91:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$41, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp92:\n# %bb.69:\n.Ltmp93:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.3, %esi\n\tmovl\t$9, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp94:\n# %bb.70:\n.Ltmp95:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tmovl\t$72, %esi\n\tcallq\t_ZNSolsEi\n.Ltmp96:\n# %bb.71:\n.Ltmp97:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_\n.Ltmp98:\n# %bb.72:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %edi\n\tcallq\texit\n.LBB3_51:\n.Ltmp63:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$12, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp64:\n# %bb.52:\n.Ltmp65:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%ebx, %edi\n\tcallq\thipGetErrorString\n.Ltmp66:\n# %bb.53:\n.Ltmp67:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rax, %rsi\n\tcallq\t_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc\n.Ltmp68:\n# %bb.54:\n.Ltmp69:\n\tmovq\t%rax, %rbx\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$4, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp70:\n# %bb.55:\n.Ltmp71:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$41, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp72:\n# %bb.56:\n.Ltmp73:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.3, %esi\n\tmovl\t$9, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp74:\n# %bb.57:\n.Ltmp75:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tmovl\t$71, %esi\n\tcallq\t_ZNSolsEi\n.Ltmp76:\n# %bb.58:\n.Ltmp77:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_\n.Ltmp78:\n# %bb.59:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %edi\n\tcallq\texit\n.LBB3_38:\n.Ltmp43:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$12, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp44:\n# %bb.39:\n.Ltmp45:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%ebx, %edi\n\tcallq\thipGetErrorString\n.Ltmp46:\n# %bb.40:\n.Ltmp47:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rax, %rsi\n\tcallq\t_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc\n.Ltmp48:\n# %bb.41:\n.Ltmp49:\n\tmovq\t%rax, %rbx\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$4, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp50:\n# %bb.42:\n.Ltmp51:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$41, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp52:\n# %bb.43:\n.Ltmp53:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.3, %esi\n\tmovl\t$9, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp54:\n# %bb.44:\n.Ltmp55:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tmovl\t$70, %esi\n\tcallq\t_ZNSolsEi\n.Ltmp56:\n# %bb.45:\n.Ltmp57:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_\n.Ltmp58:\n# %bb.46:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %edi\n\tcallq\texit\n.LBB3_25:\n.Ltmp23:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$12, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp24:\n# %bb.26:\n.Ltmp25:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%ebx, %edi\n\tcallq\thipGetErrorString\n.Ltmp26:\n# %bb.27:\n.Ltmp27:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rax, %rsi\n\tcallq\t_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc\n.Ltmp28:\n# %bb.28:\n.Ltmp29:\n\tmovq\t%rax, %rbx\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$4, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp30:\n# %bb.29:\n.Ltmp31:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$41, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp32:\n# %bb.30:\n.Ltmp33:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.3, %esi\n\tmovl\t$9, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp34:\n# %bb.31:\n.Ltmp35:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tmovl\t$69, %esi\n\tcallq\t_ZNSolsEi\n.Ltmp36:\n# %bb.32:\n.Ltmp37:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_\n.Ltmp38:\n# %bb.33:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %edi\n\tcallq\texit\n.LBB3_3:\n.Ltmp3:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$12, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp4:\n# %bb.4:\n.Ltmp5:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%ebx, %edi\n\tcallq\thipGetErrorString\n.Ltmp6:\n# %bb.5:\n.Ltmp7:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rax, %rsi\n\tcallq\t_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc\n.Ltmp8:\n# %bb.6:\n.Ltmp9:\n\tmovq\t%rax, %rbx\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$4, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp10:\n# %bb.7:\n.Ltmp11:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$41, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp12:\n# %bb.8:\n.Ltmp13:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.3, %esi\n\tmovl\t$9, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp14:\n# %bb.9:\n.Ltmp15:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tmovl\t$68, %esi\n\tcallq\t_ZNSolsEi\n.Ltmp16:\n# %bb.10:\n.Ltmp17:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_\n.Ltmp18:\n# %bb.11:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %edi\n\tcallq\texit\n.LBB3_137:\n.Ltmp195:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$12, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp196:\n# %bb.138:\n.Ltmp197:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%r15d, %edi\n\tcallq\thipGetErrorString\n.Ltmp198:\n# %bb.139:\n.Ltmp199:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rax, %rsi\n\tcallq\t_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc\n.Ltmp200:\n# %bb.140:\n.Ltmp201:\n\tmovq\t%rax, %rbx\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$4, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp202:\n# %bb.141:\n.Ltmp203:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$41, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp204:\n# %bb.142:\n.Ltmp205:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.3, %esi\n\tmovl\t$9, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp206:\n# %bb.143:\n.Ltmp207:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tmovl\t$85, %esi\n\tcallq\t_ZNSolsEi\n.Ltmp208:\n# %bb.144:\n.Ltmp209:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_\n.Ltmp210:\n# %bb.145:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %edi\n\tcallq\texit\n.LBB3_124:\n.Ltmp175:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$12, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp176:\n# %bb.125:\n.Ltmp177:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%r15d, %edi\n\tcallq\thipGetErrorString\n.Ltmp178:\n# %bb.126:\n.Ltmp179:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rax, %rsi\n\tcallq\t_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc\n.Ltmp180:\n# %bb.127:\n.Ltmp181:\n\tmovq\t%rax, %rbx\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$4, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp182:\n# %bb.128:\n.Ltmp183:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$41, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp184:\n# %bb.129:\n.Ltmp185:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.3, %esi\n\tmovl\t$9, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp186:\n# %bb.130:\n.Ltmp187:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tmovl\t$82, %esi\n\tcallq\t_ZNSolsEi\n.Ltmp188:\n# %bb.131:\n.Ltmp189:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_\n.Ltmp190:\n# %bb.132:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %edi\n\tcallq\texit\n.LBB3_111:\n.Ltmp155:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$12, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp156:\n# %bb.112:\n.Ltmp157:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%r15d, %edi\n\tcallq\thipGetErrorString\n.Ltmp158:\n# %bb.113:\n.Ltmp159:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rax, %rsi\n\tcallq\t_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc\n.Ltmp160:\n# %bb.114:\n.Ltmp161:\n\tmovq\t%rax, %rbx\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$4, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp162:\n# %bb.115:\n.Ltmp163:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$41, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp164:\n# %bb.116:\n.Ltmp165:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.3, %esi\n\tmovl\t$9, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp166:\n# %bb.117:\n.Ltmp167:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tmovl\t$81, %esi\n\tcallq\t_ZNSolsEi\n.Ltmp168:\n# %bb.118:\n.Ltmp169:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_\n.Ltmp170:\n# %bb.119:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %edi\n\tcallq\texit\n.LBB3_232:\n.Ltmp342:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$12, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp343:\n# %bb.233:\n.Ltmp344:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%ebx, %edi\n\tcallq\thipGetErrorString\n.Ltmp345:\n# %bb.234:\n.Ltmp346:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rax, %rsi\n\tcallq\t_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc\n.Ltmp347:\n# %bb.235:\n.Ltmp348:\n\tmovq\t%rax, %rbx\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$4, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp349:\n# %bb.236:\n.Ltmp350:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$41, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp351:\n# %bb.237:\n.Ltmp352:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.3, %esi\n\tmovl\t$9, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp353:\n# %bb.238:\n.Ltmp354:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tmovl\t$99, %esi\n\tcallq\t_ZNSolsEi\n.Ltmp355:\n# %bb.239:\n.Ltmp356:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_\n.Ltmp357:\n# %bb.240:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %edi\n\tcallq\texit\n.LBB3_219:\n.Ltmp322:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$12, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp323:\n# %bb.220:\n.Ltmp324:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%ebp, %edi\n\tcallq\thipGetErrorString\n.Ltmp325:\n# %bb.221:\n.Ltmp326:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rax, %rsi\n\tcallq\t_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc\n.Ltmp327:\n# %bb.222:\n.Ltmp328:\n\tmovq\t%rax, %rbx\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$4, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp329:\n# %bb.223:\n.Ltmp330:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$41, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp331:\n# %bb.224:\n.Ltmp332:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.3, %esi\n\tmovl\t$9, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp333:\n# %bb.225:\n.Ltmp334:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tmovl\t$98, %esi\n\tcallq\t_ZNSolsEi\n.Ltmp335:\n# %bb.226:\n.Ltmp336:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_\n.Ltmp337:\n# %bb.227:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %edi\n\tcallq\texit\n.LBB3_206:\n.Ltmp302:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$12, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp303:\n# %bb.207:\n.Ltmp304:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%ebp, %edi\n\tcallq\thipGetErrorString\n.Ltmp305:\n# %bb.208:\n.Ltmp306:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rax, %rsi\n\tcallq\t_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc\n.Ltmp307:\n# %bb.209:\n.Ltmp308:\n\tmovq\t%rax, %rbx\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$4, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp309:\n# %bb.210:\n.Ltmp310:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$41, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp311:\n# %bb.211:\n.Ltmp312:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.3, %esi\n\tmovl\t$9, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp313:\n# %bb.212:\n.Ltmp314:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tmovl\t$97, %esi\n\tcallq\t_ZNSolsEi\n.Ltmp315:\n# %bb.213:\n.Ltmp316:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_\n.Ltmp317:\n# %bb.214:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %edi\n\tcallq\texit\n.LBB3_193:\n.Ltmp282:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$12, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp283:\n# %bb.194:\n.Ltmp284:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%r15d, %edi\n\tcallq\thipGetErrorString\n.Ltmp285:\n# %bb.195:\n.Ltmp286:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rax, %rsi\n\tcallq\t_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc\n.Ltmp287:\n# %bb.196:\n.Ltmp288:\n\tmovq\t%rax, %rbx\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$4, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp289:\n# %bb.197:\n.Ltmp290:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$41, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp291:\n# %bb.198:\n.Ltmp292:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.3, %esi\n\tmovl\t$9, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp293:\n# %bb.199:\n.Ltmp294:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tmovl\t$96, %esi\n\tcallq\t_ZNSolsEi\n.Ltmp295:\n# %bb.200:\n.Ltmp296:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_\n.Ltmp297:\n# %bb.201:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %edi\n\tcallq\texit\n.LBB3_180:\n.Ltmp262:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$12, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp263:\n# %bb.181:\n.Ltmp264:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%r15d, %edi\n\tcallq\thipGetErrorString\n.Ltmp265:\n# %bb.182:\n.Ltmp266:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rax, %rsi\n\tcallq\t_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc\n.Ltmp267:\n# %bb.183:\n.Ltmp268:\n\tmovq\t%rax, %rbx\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$4, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp269:\n# %bb.184:\n.Ltmp270:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$41, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp271:\n# %bb.185:\n.Ltmp272:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.3, %esi\n\tmovl\t$9, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp273:\n# %bb.186:\n.Ltmp274:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tmovl\t$93, %esi\n\tcallq\t_ZNSolsEi\n.Ltmp275:\n# %bb.187:\n.Ltmp276:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_\n.Ltmp277:\n# %bb.188:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %edi\n\tcallq\texit\n.LBB3_167:\n.Ltmp242:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$12, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp243:\n# %bb.168:\n.Ltmp244:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%r15d, %edi\n\tcallq\thipGetErrorString\n.Ltmp245:\n# %bb.169:\n.Ltmp246:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rax, %rsi\n\tcallq\t_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc\n.Ltmp247:\n# %bb.170:\n.Ltmp248:\n\tmovq\t%rax, %rbx\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$4, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp249:\n# %bb.171:\n.Ltmp250:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$41, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp251:\n# %bb.172:\n.Ltmp252:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.3, %esi\n\tmovl\t$9, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp253:\n# %bb.173:\n.Ltmp254:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tmovl\t$90, %esi\n\tcallq\t_ZNSolsEi\n.Ltmp255:\n# %bb.174:\n.Ltmp256:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_\n.Ltmp257:\n# %bb.175:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %edi\n\tcallq\texit\n.LBB3_154:\n.Ltmp222:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$12, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp223:\n# %bb.155:\n.Ltmp224:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t%r15d, %edi\n\tcallq\thipGetErrorString\n.Ltmp225:\n# %bb.156:\n.Ltmp226:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rax, %rsi\n\tcallq\t_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc\n.Ltmp227:\n# %bb.157:\n.Ltmp228:\n\tmovq\t%rax, %rbx\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.1, %esi\n\tmovl\t$4, %edx\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp229:\n# %bb.158:\n.Ltmp230:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.2, %esi\n\tmovl\t$41, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp231:\n# %bb.159:\n.Ltmp232:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$.L.str.3, %esi\n\tmovl\t$9, %edx\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n.Ltmp233:\n# %bb.160:\n.Ltmp234:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tmovl\t$89, %esi\n\tcallq\t_ZNSolsEi\n.Ltmp235:\n# %bb.161:\n.Ltmp236:\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rax, %rdi\n\tcallq\t_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_\n.Ltmp237:\n# %bb.162:\n\t.cfi_escape 0x2e, 0x00\n\tmovl\t$1, %edi\n\tcallq\texit\n.LBB3_21:\n.Ltmp378:\n\t.cfi_escape 0x2e, 0x00\n\tcallq\t_ZSt16__throw_bad_castv\n.Ltmp379:\n# %bb.243:\n.LBB3_253:\n.Ltmp380:\n\tjmp\t.LBB3_255\n.LBB3_164:\n.Ltmp238:\n\tjmp\t.LBB3_255\n.LBB3_177:\n.Ltmp258:\n\tjmp\t.LBB3_255\n.LBB3_190:\n.Ltmp278:\n\tjmp\t.LBB3_255\n.LBB3_203:\n.Ltmp298:\n\tjmp\t.LBB3_255\n.LBB3_216:\n.Ltmp318:\n\tjmp\t.LBB3_255\n.LBB3_229:\n.Ltmp338:\n\tjmp\t.LBB3_255\n.LBB3_242:\n.Ltmp358:\n\tjmp\t.LBB3_255\n.LBB3_121:\n.Ltmp171:\n\tjmp\t.LBB3_255\n.LBB3_134:\n.Ltmp191:\n\tjmp\t.LBB3_255\n.LBB3_147:\n.Ltmp211:\n\tjmp\t.LBB3_255\n.LBB3_22:\n.Ltmp19:\n\tjmp\t.LBB3_255\n.LBB3_35:\n.Ltmp39:\n\tjmp\t.LBB3_255\n.LBB3_48:\n.Ltmp59:\n\tjmp\t.LBB3_255\n.LBB3_61:\n.Ltmp79:\n\tjmp\t.LBB3_255\n.LBB3_74:\n.Ltmp99:\n\tjmp\t.LBB3_255\n.LBB3_91:\n.Ltmp125:\n\tjmp\t.LBB3_255\n.LBB3_104:\n.Ltmp145:\n\tjmp\t.LBB3_255\n.LBB3_163:\n.Ltmp221:\n\tjmp\t.LBB3_255\n.LBB3_176:\n.Ltmp241:\n\tjmp\t.LBB3_255\n.LBB3_189:\n.Ltmp261:\n\tjmp\t.LBB3_255\n.LBB3_202:\n.Ltmp281:\n\tjmp\t.LBB3_255\n.LBB3_215:\n.Ltmp301:\n\tjmp\t.LBB3_255\n.LBB3_228:\n.Ltmp321:\n\tjmp\t.LBB3_255\n.LBB3_241:\n.Ltmp341:\n\tjmp\t.LBB3_255\n.LBB3_120:\n.Ltmp154:\n\tjmp\t.LBB3_255\n.LBB3_133:\n.Ltmp174:\n\tjmp\t.LBB3_255\n.LBB3_146:\n.Ltmp194:\n\tjmp\t.LBB3_255\n.LBB3_254:\n.Ltmp2:\n\tjmp\t.LBB3_255\n.LBB3_34:\n.Ltmp22:\n\tjmp\t.LBB3_255\n.LBB3_47:\n.Ltmp42:\n\tjmp\t.LBB3_255\n.LBB3_60:\n.Ltmp62:\n\tjmp\t.LBB3_255\n.LBB3_73:\n.Ltmp82:\n\tjmp\t.LBB3_255\n.LBB3_90:\n.Ltmp108:\n\tjmp\t.LBB3_255\n.LBB3_103:\n.Ltmp128:\n\tjmp\t.LBB3_255\n.LBB3_252:\n.Ltmp377:\n\tjmp\t.LBB3_255\n.LBB3_256:\n.Ltmp218:\n.LBB3_255:\n\tmovq\t%rax, %rbx\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t8(%rsp), %rdi # 8-byte Reload\n\tcallq\t_ZdlPv\n\t.cfi_escape 0x2e, 0x00\n\tmovq\t%rbx, %rdi\n\tcallq\t_Unwind_Resume@PLT\n.Lfunc_end3:\n\t.size\tmain, .Lfunc_end3-main\n\t.cfi_endproc\n\t.section\t.gcc_except_table,\"a\",@progbits\n\t.p2align\t2, 0x0\nGCC_except_table3:\n.Lexception0:\n\t.byte\t255 # @LPStart Encoding = omit\n\t.byte\t255 # @TType Encoding = omit\n\t.byte\t1 # Call site Encoding = uleb128\n\t.uleb128 .Lcst_end0-.Lcst_begin0\n.Lcst_begin0:\n\t.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<\n\t.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<\n\t.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1\n\t.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 3 <<\n\t.uleb128 .Ltmp21-.Ltmp20 # Call between .Ltmp20 and .Ltmp21\n\t.uleb128 .Ltmp22-.Lfunc_begin0 # jumps to .Ltmp22\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp40-.Lfunc_begin0 # >> Call Site 4 <<\n\t.uleb128 .Ltmp41-.Ltmp40 # Call between .Ltmp40 and .Ltmp41\n\t.uleb128 .Ltmp42-.Lfunc_begin0 # jumps to .Ltmp42\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp60-.Lfunc_begin0 # >> Call Site 5 <<\n\t.uleb128 .Ltmp61-.Ltmp60 # Call between .Ltmp60 and .Ltmp61\n\t.uleb128 .Ltmp62-.Lfunc_begin0 # jumps to .Ltmp62\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp80-.Lfunc_begin0 # >> Call Site 6 <<\n\t.uleb128 .Ltmp81-.Ltmp80 # Call between .Ltmp80 and .Ltmp81\n\t.uleb128 .Ltmp82-.Lfunc_begin0 # jumps to .Ltmp82\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp100-.Lfunc_begin0 # >> Call Site 7 <<\n\t.uleb128 .Ltmp105-.Ltmp100 # Call between .Ltmp100 and .Ltmp105\n\t.uleb128 .Ltmp218-.Lfunc_begin0 # jumps to .Ltmp218\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp106-.Lfunc_begin0 # >> Call Site 8 <<\n\t.uleb128 .Ltmp107-.Ltmp106 # Call between .Ltmp106 and .Ltmp107\n\t.uleb128 .Ltmp108-.Lfunc_begin0 # jumps to .Ltmp108\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp126-.Lfunc_begin0 # >> Call Site 9 <<\n\t.uleb128 .Ltmp127-.Ltmp126 # Call between .Ltmp126 and .Ltmp127\n\t.uleb128 .Ltmp128-.Lfunc_begin0 # jumps to .Ltmp128\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp146-.Lfunc_begin0 # >> Call Site 10 <<\n\t.uleb128 .Ltmp151-.Ltmp146 # Call between .Ltmp146 and .Ltmp151\n\t.uleb128 .Ltmp218-.Lfunc_begin0 # jumps to .Ltmp218\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp152-.Lfunc_begin0 # >> Call Site 11 <<\n\t.uleb128 .Ltmp153-.Ltmp152 # Call between .Ltmp152 and .Ltmp153\n\t.uleb128 .Ltmp154-.Lfunc_begin0 # jumps to .Ltmp154\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp172-.Lfunc_begin0 # >> Call Site 12 <<\n\t.uleb128 .Ltmp173-.Ltmp172 # Call between .Ltmp172 and .Ltmp173\n\t.uleb128 .Ltmp174-.Lfunc_begin0 # jumps to .Ltmp174\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp192-.Lfunc_begin0 # >> Call Site 13 <<\n\t.uleb128 .Ltmp193-.Ltmp192 # Call between .Ltmp192 and .Ltmp193\n\t.uleb128 .Ltmp194-.Lfunc_begin0 # jumps to .Ltmp194\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp212-.Lfunc_begin0 # >> Call Site 14 <<\n\t.uleb128 .Ltmp217-.Ltmp212 # Call between .Ltmp212 and .Ltmp217\n\t.uleb128 .Ltmp218-.Lfunc_begin0 # jumps to .Ltmp218\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp219-.Lfunc_begin0 # >> Call Site 15 <<\n\t.uleb128 .Ltmp220-.Ltmp219 # Call between .Ltmp219 and .Ltmp220\n\t.uleb128 .Ltmp221-.Lfunc_begin0 # jumps to .Ltmp221\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp239-.Lfunc_begin0 # >> Call Site 16 <<\n\t.uleb128 .Ltmp240-.Ltmp239 # Call between .Ltmp239 and .Ltmp240\n\t.uleb128 .Ltmp241-.Lfunc_begin0 # jumps to .Ltmp241\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp259-.Lfunc_begin0 # >> Call Site 17 <<\n\t.uleb128 .Ltmp260-.Ltmp259 # Call between .Ltmp259 and .Ltmp260\n\t.uleb128 .Ltmp261-.Lfunc_begin0 # jumps to .Ltmp261\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp279-.Lfunc_begin0 # >> Call Site 18 <<\n\t.uleb128 .Ltmp280-.Ltmp279 # Call between .Ltmp279 and .Ltmp280\n\t.uleb128 .Ltmp281-.Lfunc_begin0 # jumps to .Ltmp281\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp299-.Lfunc_begin0 # >> Call Site 19 <<\n\t.uleb128 .Ltmp300-.Ltmp299 # Call between .Ltmp299 and .Ltmp300\n\t.uleb128 .Ltmp301-.Lfunc_begin0 # jumps to .Ltmp301\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp319-.Lfunc_begin0 # >> Call Site 20 <<\n\t.uleb128 .Ltmp320-.Ltmp319 # Call between .Ltmp319 and .Ltmp320\n\t.uleb128 .Ltmp321-.Lfunc_begin0 # jumps to .Ltmp321\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp339-.Lfunc_begin0 # >> Call Site 21 <<\n\t.uleb128 .Ltmp340-.Ltmp339 # Call between .Ltmp339 and .Ltmp340\n\t.uleb128 .Ltmp341-.Lfunc_begin0 # jumps to .Ltmp341\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp359-.Lfunc_begin0 # >> Call Site 22 <<\n\t.uleb128 .Ltmp376-.Ltmp359 # Call between .Ltmp359 and .Ltmp376\n\t.uleb128 .Ltmp377-.Lfunc_begin0 # jumps to .Ltmp377\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp129-.Lfunc_begin0 # >> Call Site 23 <<\n\t.uleb128 .Ltmp144-.Ltmp129 # Call between .Ltmp129 and .Ltmp144\n\t.uleb128 .Ltmp145-.Lfunc_begin0 # jumps to .Ltmp145\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp109-.Lfunc_begin0 # >> Call Site 24 <<\n\t.uleb128 .Ltmp124-.Ltmp109 # Call between .Ltmp109 and .Ltmp124\n\t.uleb128 .Ltmp125-.Lfunc_begin0 # jumps to .Ltmp125\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp83-.Lfunc_begin0 # >> Call Site 25 <<\n\t.uleb128 .Ltmp98-.Ltmp83 # Call between .Ltmp83 and .Ltmp98\n\t.uleb128 .Ltmp99-.Lfunc_begin0 # jumps to .Ltmp99\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp63-.Lfunc_begin0 # >> Call Site 26 <<\n\t.uleb128 .Ltmp78-.Ltmp63 # Call between .Ltmp63 and .Ltmp78\n\t.uleb128 .Ltmp79-.Lfunc_begin0 # jumps to .Ltmp79\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 27 <<\n\t.uleb128 .Ltmp58-.Ltmp43 # Call between .Ltmp43 and .Ltmp58\n\t.uleb128 .Ltmp59-.Lfunc_begin0 # jumps to .Ltmp59\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 28 <<\n\t.uleb128 .Ltmp38-.Ltmp23 # Call between .Ltmp23 and .Ltmp38\n\t.uleb128 .Ltmp39-.Lfunc_begin0 # jumps to .Ltmp39\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 29 <<\n\t.uleb128 .Ltmp18-.Ltmp3 # Call between .Ltmp3 and .Ltmp18\n\t.uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp195-.Lfunc_begin0 # >> Call Site 30 <<\n\t.uleb128 .Ltmp210-.Ltmp195 # Call between .Ltmp195 and .Ltmp210\n\t.uleb128 .Ltmp211-.Lfunc_begin0 # jumps to .Ltmp211\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp175-.Lfunc_begin0 # >> Call Site 31 <<\n\t.uleb128 .Ltmp190-.Ltmp175 # Call between .Ltmp175 and .Ltmp190\n\t.uleb128 .Ltmp191-.Lfunc_begin0 # jumps to .Ltmp191\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp155-.Lfunc_begin0 # >> Call Site 32 <<\n\t.uleb128 .Ltmp170-.Ltmp155 # Call between .Ltmp155 and .Ltmp170\n\t.uleb128 .Ltmp171-.Lfunc_begin0 # jumps to .Ltmp171\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp342-.Lfunc_begin0 # >> Call Site 33 <<\n\t.uleb128 .Ltmp357-.Ltmp342 # Call between .Ltmp342 and .Ltmp357\n\t.uleb128 .Ltmp358-.Lfunc_begin0 # jumps to .Ltmp358\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp322-.Lfunc_begin0 # >> Call Site 34 <<\n\t.uleb128 .Ltmp337-.Ltmp322 # Call between .Ltmp322 and .Ltmp337\n\t.uleb128 .Ltmp338-.Lfunc_begin0 # jumps to .Ltmp338\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp302-.Lfunc_begin0 # >> Call Site 35 <<\n\t.uleb128 .Ltmp317-.Ltmp302 # Call between .Ltmp302 and .Ltmp317\n\t.uleb128 .Ltmp318-.Lfunc_begin0 # jumps to .Ltmp318\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp282-.Lfunc_begin0 # >> Call Site 36 <<\n\t.uleb128 .Ltmp297-.Ltmp282 # Call between .Ltmp282 and .Ltmp297\n\t.uleb128 .Ltmp298-.Lfunc_begin0 # jumps to .Ltmp298\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp262-.Lfunc_begin0 # >> Call Site 37 <<\n\t.uleb128 .Ltmp277-.Ltmp262 # Call between .Ltmp262 and .Ltmp277\n\t.uleb128 .Ltmp278-.Lfunc_begin0 # jumps to .Ltmp278\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp242-.Lfunc_begin0 # >> Call Site 38 <<\n\t.uleb128 .Ltmp257-.Ltmp242 # Call between .Ltmp242 and .Ltmp257\n\t.uleb128 .Ltmp258-.Lfunc_begin0 # jumps to .Ltmp258\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp222-.Lfunc_begin0 # >> Call Site 39 <<\n\t.uleb128 .Ltmp237-.Ltmp222 # Call between .Ltmp222 and .Ltmp237\n\t.uleb128 .Ltmp238-.Lfunc_begin0 # jumps to .Ltmp238\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp378-.Lfunc_begin0 # >> Call Site 40 <<\n\t.uleb128 .Ltmp379-.Ltmp378 # Call between .Ltmp378 and .Ltmp379\n\t.uleb128 .Ltmp380-.Lfunc_begin0 # jumps to .Ltmp380\n\t.byte\t0 # On action: cleanup\n\t.uleb128 .Ltmp379-.Lfunc_begin0 # >> Call Site 41 <<\n\t.uleb128 .Lfunc_end3-.Ltmp379 # Call between .Ltmp379 and .Lfunc_end3\n\t.byte\t0 # has no landing pad\n\t.byte\t0 # On action: cleanup\n.Lcst_end0:\n\t.p2align\t2, 0x0\n # -- End function\n\t.section\t.text.startup,\"ax\",@progbits\n\t.p2align\t4, 0x90 # -- Begin function _GLOBAL__sub_I_cuda_code_063793.hip\n\t.type\t_GLOBAL__sub_I_cuda_code_063793.hip,@function\n_GLOBAL__sub_I_cuda_code_063793.hip: # @_GLOBAL__sub_I_cuda_code_063793.hip\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 16\n\tmovl\t$_ZStL8__ioinit, %edi\n\tcallq\t_ZNSt8ios_base4InitC1Ev\n\tmovl\t$_ZNSt8ios_base4InitD1Ev, %edi\n\tmovl\t$_ZStL8__ioinit, %esi\n\tmovl\t$__dso_handle, %edx\n\tpopq\t%rax\n\t.cfi_def_cfa_offset 8\n\tjmp\t__cxa_atexit # TAILCALL\n.Lfunc_end4:\n\t.size\t_GLOBAL__sub_I_cuda_code_063793.hip, .Lfunc_end4-_GLOBAL__sub_I_cuda_code_063793.hip\n\t.cfi_endproc\n # -- End function\n\t.text\n\t.p2align\t4, 0x90 # -- Begin function __hip_module_ctor\n\t.type\t__hip_module_ctor,@function\n__hip_module_ctor: # @__hip_module_ctor\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 16\n\tsubq\t$32, %rsp\n\t.cfi_def_cfa_offset 48\n\t.cfi_offset %rbx, -16\n\tmovq\t__hip_gpubin_handle(%rip), %rbx\n\ttestq\t%rbx, %rbx\n\tjne\t.LBB5_2\n# %bb.1:\n\tmovl\t$__hip_fatbin_wrapper, %edi\n\tcallq\t__hipRegisterFatBinary\n\tmovq\t%rax, %rbx\n\tmovq\t%rax, __hip_gpubin_handle(%rip)\n.LBB5_2:\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, 16(%rsp)\n\tmovups\t%xmm0, (%rsp)\n\tmovl\t$_Z12insertKernelPiS_S_i, %esi\n\tmovl\t$.L__unnamed_1, %edx\n\tmovl\t$.L__unnamed_1, %ecx\n\tmovq\t%rbx, %rdi\n\tmovl\t$-1, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipRegisterFunction\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, 16(%rsp)\n\tmovups\t%xmm0, (%rsp)\n\tmovl\t$_Z16initRandomKernelP12hiprandStatem, %esi\n\tmovl\t$.L__unnamed_2, %edx\n\tmovl\t$.L__unnamed_2, %ecx\n\tmovq\t%rbx, %rdi\n\tmovl\t$-1, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipRegisterFunction\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, 16(%rsp)\n\tmovups\t%xmm0, (%rsp)\n\tmovl\t$_Z18generateKeysKernelP12hiprandStatePii, %esi\n\tmovl\t$.L__unnamed_3, %edx\n\tmovl\t$.L__unnamed_3, %ecx\n\tmovq\t%rbx, %rdi\n\tmovl\t$-1, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipRegisterFunction\n\tmovl\t$__hip_module_dtor, %edi\n\taddq\t$32, %rsp\n\t.cfi_def_cfa_offset 16\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 8\n\tjmp\tatexit # TAILCALL\n.Lfunc_end5:\n\t.size\t__hip_module_ctor, .Lfunc_end5-__hip_module_ctor\n\t.cfi_endproc\n # -- End function\n\t.p2align\t4, 0x90 # -- Begin function __hip_module_dtor\n\t.type\t__hip_module_dtor,@function\n__hip_module_dtor: # @__hip_module_dtor\n\t.cfi_startproc\n# %bb.0:\n\tmovq\t__hip_gpubin_handle(%rip), %rdi\n\ttestq\t%rdi, %rdi\n\tje\t.LBB6_2\n# %bb.1:\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 16\n\tcallq\t__hipUnregisterFatBinary\n\tmovq\t$0, __hip_gpubin_handle(%rip)\n\taddq\t$8, %rsp\n\t.cfi_def_cfa_offset 8\n.LBB6_2:\n\tretq\n.Lfunc_end6:\n\t.size\t__hip_module_dtor, .Lfunc_end6-__hip_module_dtor\n\t.cfi_endproc\n # -- End function\n\t.type\t_ZStL8__ioinit,@object # @_ZStL8__ioinit\n\t.local\t_ZStL8__ioinit\n\t.comm\t_ZStL8__ioinit,1,1\n\t.hidden\t__dso_handle\n\t.type\t_Z12insertKernelPiS_S_i,@object # @_Z12insertKernelPiS_S_i\n\t.section\t.rodata,\"a\",@progbits\n\t.globl\t_Z12insertKernelPiS_S_i\n\t.p2align\t3, 0x0\n_Z12insertKernelPiS_S_i:\n\t.quad\t_Z27__device_stub__insertKernelPiS_S_i\n\t.size\t_Z12insertKernelPiS_S_i, 8\n\n\t.type\t_Z16initRandomKernelP12hiprandStatem,@object # @_Z16initRandomKernelP12hiprandStatem\n\t.globl\t_Z16initRandomKernelP12hiprandStatem\n\t.p2align\t3, 0x0\n_Z16initRandomKernelP12hiprandStatem:\n\t.quad\t_Z31__device_stub__initRandomKernelP12hiprandStatem\n\t.size\t_Z16initRandomKernelP12hiprandStatem, 8\n\n\t.type\t_Z18generateKeysKernelP12hiprandStatePii,@object # @_Z18generateKeysKernelP12hiprandStatePii\n\t.globl\t_Z18generateKeysKernelP12hiprandStatePii\n\t.p2align\t3, 0x0\n_Z18generateKeysKernelP12hiprandStatePii:\n\t.quad\t_Z33__device_stub__generateKeysKernelP12hiprandStatePii\n\t.size\t_Z18generateKeysKernelP12hiprandStatePii, 8\n\n\t.type\t.L.str,@object # @.str\n\t.section\t.rodata.str1.1,\"aMS\",@progbits,1\n.L.str:\n\t.asciz\t\"CUDA error: \"\n\t.size\t.L.str, 13\n\n\t.type\t.L.str.1,@object # @.str.1\n.L.str.1:\n\t.asciz\t\" in \"\n\t.size\t.L.str.1, 5\n\n\t.type\t.L.str.2,@object # @.str.2\n.L.str.2:\n\t.asciz\t\"CUDA_repos/synthetic/cuda_code_063793.hip\"\n\t.size\t.L.str.2, 42\n\n\t.type\t.L.str.3,@object # @.str.3\n.L.str.3:\n\t.asciz\t\" at line \"\n\t.size\t.L.str.3, 10\n\n\t.type\t.L.str.4,@object # @.str.4\n.L.str.4:\n\t.asciz\t\"Bucket \"\n\t.size\t.L.str.4, 8\n\n\t.type\t.L.str.5,@object # @.str.5\n.L.str.5:\n\t.asciz\t\" has \"\n\t.size\t.L.str.5, 6\n\n\t.type\t.L.str.6,@object # @.str.6\n.L.str.6:\n\t.asciz\t\" elements.\"\n\t.size\t.L.str.6, 11\n\n\t.type\t.L__unnamed_1,@object # @0\n.L__unnamed_1:\n\t.asciz\t\"_Z12insertKernelPiS_S_i\"\n\t.size\t.L__unnamed_1, 24\n\n\t.type\t.L__unnamed_2,@object # @1\n.L__unnamed_2:\n\t.asciz\t\"_Z16initRandomKernelP12hiprandStatem\"\n\t.size\t.L__unnamed_2, 37\n\n\t.type\t.L__unnamed_3,@object # @2\n.L__unnamed_3:\n\t.asciz\t\"_Z18generateKeysKernelP12hiprandStatePii\"\n\t.size\t.L__unnamed_3, 41\n\n\t.type\t__hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper\n\t.section\t.hipFatBinSegment,\"a\",@progbits\n\t.p2align\t3, 0x0\n__hip_fatbin_wrapper:\n\t.long\t1212764230 # 0x48495046\n\t.long\t1 # 0x1\n\t.quad\t__hip_fatbin\n\t.quad\t0\n\t.size\t__hip_fatbin_wrapper, 24\n\n\t.type\t__hip_gpubin_handle,@object # @__hip_gpubin_handle\n\t.local\t__hip_gpubin_handle\n\t.comm\t__hip_gpubin_handle,8,8\n\t.section\t.init_array,\"aw\",@init_array\n\t.p2align\t3, 0x0\n\t.quad\t_GLOBAL__sub_I_cuda_code_063793.hip\n\t.quad\t__hip_module_ctor\n\t.type\t__hip_cuid_,@object # @__hip_cuid_\n\t.bss\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 # 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n"}}},{"rowIdx":162589,"cells":{"id":{"kind":"string","value":"fa293e3604e07b144decc62ef4938312ab82796f_O2"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z3sumIfEvPT_S1_S1_i --------------------------\n .section .text._Z3sumIfEvPT_S1_S1_i,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=12\"\n .align 128\n\n\n\n\n .global _Z3sumIfEvPT_S1_S1_i\n .type _Z3sumIfEvPT_S1_S1_i,@function\n .size _Z3sumIfEvPT_S1_S1_i,(.L_x_1 - _Z3sumIfEvPT_S1_S1_i)\n .other _Z3sumIfEvPT_S1_S1_i,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z3sumIfEvPT_S1_S1_i:\n.text._Z3sumIfEvPT_S1_S1_i:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ S2R R6, SR_CTAID.X ;\n /*0020*/ S2R R3, SR_TID.X ;\n /*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ;\n /*0040*/ ISETP.GT.AND P0, PT, R6, c[0x0][0x178], PT ;\n /*0050*/ @P0 EXIT ;\n /*0060*/ MOV R7, 0x4 ;\n /*0070*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ;\n /*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ;\n /*00a0*/ LDG.E R4, [R4.64] ;\n /*00b0*/ LDG.E R3, [R2.64] ;\n /*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ;\n /*00d0*/ FADD R9, R4, R3 ;\n /*00e0*/ STG.E [R6.64], R9 ;\n /*00f0*/ EXIT ;\n.L_x_0:\n /*0100*/ BRA `(.L_x_0);\n /*0110*/ NOP;\n /*0120*/ NOP;\n /*0130*/ NOP;\n /*0140*/ NOP;\n /*0150*/ NOP;\n /*0160*/ NOP;\n /*0170*/ NOP;\n /*0180*/ NOP;\n /*0190*/ NOP;\n /*01a0*/ NOP;\n /*01b0*/ NOP;\n /*01c0*/ NOP;\n /*01d0*/ NOP;\n /*01e0*/ NOP;\n /*01f0*/ NOP;\n.L_x_1:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.weak\t__cxa_pure_virtual ; -- Begin function __cxa_pure_virtual\n\t.p2align\t2\n\t.type\t__cxa_pure_virtual,@function\n__cxa_pure_virtual: ; @__cxa_pure_virtual\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB0_1: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB0_1\n.Lfunc_end0:\n\t.size\t__cxa_pure_virtual, .Lfunc_end0-__cxa_pure_virtual\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 56\n; NumSgprs: 1\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.weak\t__cxa_deleted_virtual ; -- Begin function __cxa_deleted_virtual\n\t.p2align\t2\n\t.type\t__cxa_deleted_virtual,@function\n__cxa_deleted_virtual: ; @__cxa_deleted_virtual\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB1_1: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB1_1\n.Lfunc_end1:\n\t.size\t__cxa_deleted_virtual, .Lfunc_end1-__cxa_deleted_virtual\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 56\n; NumSgprs: 1\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hsa_signal_add\n\t.type\t__ockl_hsa_signal_add,@function\n__ockl_hsa_signal_add: ; @__ockl_hsa_signal_add\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v6, s32 offset:48 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v4, s32 offset:36 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v3, s32 offset:32 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v2\n\tscratch_load_b32 v2, off, s32 offset:32 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v1, s32 offset:28 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v1, v0\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[3:4], s32 offset:20 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v3, v1\n\tscratch_store_b64 off, v[3:4], s32 offset:12 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v0, v1\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v1, v2\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v0, s1, v0, s1\n\tv_add_co_ci_u32_e64 v2, s0, v1, s0, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s32 offset:4 ; 8-byte Folded Spill\n; %bb.1:\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 3\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, 0\n ; implicit-def: $vgpr6 : SGPR spill to VGPR lane\n\tv_writelane_b32 v6, s1, 0\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 1\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_3\n; %bb.2:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 4\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s1, 2\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 3\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_17\n\ts_branch .LBB2_4\n.LBB2_3:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 1\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s2, v6, 0\n\tv_writelane_b32 v6, s2, 4\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s2, 5\n\tv_writelane_b32 v6, s1, 6\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 7\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_13\n\ts_branch .LBB2_6\n.LBB2_4:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 5\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, -1\n\tv_writelane_b32 v6, s0, 8\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 9\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_15\n\ts_branch .LBB2_18\n.LBB2_5:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 10\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_readlane_b32 s0, v6, 11\n\ts_and_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 0\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_3\n.LBB2_6:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 12\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_7\n\ts_branch .LBB2_14\n.LBB2_7:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 12\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s2, v6, 4\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s2, 13\n\tv_writelane_b32 v6, s1, 14\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 15\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_9\n; %bb.8:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 4\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_lt_i32_e64 s2, v0, s0\n\ts_mov_b32 s0, -1\n\ts_mov_b32 s0, exec_lo\n\ts_and_not1_b32 s1, s1, exec_lo\n\ts_and_b32 s2, s2, exec_lo\n\ts_or_b32 s1, s1, s2\n\tv_writelane_b32 v6, s1, 13\n\tv_writelane_b32 v6, s0, 14\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n.LBB2_9:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s3, v6, 15\n\ts_or_b32 exec_lo, exec_lo, s3\n\tv_readlane_b32 s1, v6, 4\n\tv_readlane_b32 s2, v6, 13\n\tv_readlane_b32 s0, v6, 14\n\ts_and_b32 s0, s0, exec_lo\n\ts_and_not1_b32 s1, s1, exec_lo\n\ts_and_b32 s2, s2, exec_lo\n\ts_or_b32 s1, s1, s2\n\tv_writelane_b32 v6, s1, 5\n\tv_writelane_b32 v6, s0, 6\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_13\n.LBB2_10:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 16\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 17\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n.LBB2_11:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 18\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v6, 17\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 19\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_19\n; %bb.12:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_branch .LBB2_19\n.LBB2_13:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v6, 7\n\ts_or_b32 exec_lo, exec_lo, s2\n\tv_readlane_b32 s0, v6, 5\n\tv_readlane_b32 s1, v6, 6\n\tv_writelane_b32 v6, s1, 16\n\tv_writelane_b32 v6, s1, 17\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 18\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_11\n\ts_branch .LBB2_10\n.LBB2_14:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_branch .LBB2_7\n.LBB2_15:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 9\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_readlane_b32 s0, v6, 8\n\ts_and_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 2\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_17\n.LBB2_16:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_branch .LBB2_5\n.LBB2_17:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 3\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v6, 2\n\tv_writelane_b32 v6, s1, 11\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 10\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_5\n\ts_branch .LBB2_16\n.LBB2_18:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b32 s0, 0\n\ts_xor_b32 s0, exec_lo, -1\n\tv_writelane_b32 v6, s0, 8\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_15\n.LBB2_19:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 19\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:12 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[0:1], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:40 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_ne_u64_e64 s1, v[0:1], s[0:1]\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 20\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_21\n; %bb.20:\n\tscratch_load_b64 v[1:2], off, s32 offset:40 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s32 offset:12 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b32 v0, v[3:4], off offset:24\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v5, 0\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\tv_mov_b32_e32 v4, v5\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[1:2], v[3:4], off\n\tv_readfirstlane_b32 s0, v0\n\ts_mov_b32 s1, 0xff\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB2_21:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 20\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v6, off, s32 offset:48 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end2:\n\t.size\t__ockl_hsa_signal_add, .Lfunc_end2-__ockl_hsa_signal_add\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 1952\n; NumSgprs: 33\n; NumVgprs: 7\n; ScratchSize: 56\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hostcall_internal\n\t.type\t__ockl_hostcall_internal,@function\n__ockl_hostcall_internal: ; @__ockl_hostcall_internal\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s18, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v24, s33 offset:308 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v25, s33 offset:312 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v26, s33 offset:316 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0x150\n\tv_writelane_b32 v24, s30, 0\n\tv_writelane_b32 v24, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:132 ; 4-byte Folded Spill\n ; implicit-def: $vgpr26 : SGPR spill to VGPR lane\n\tv_writelane_b32 v26, s6, 0\n\tv_writelane_b32 v26, s7, 1\n\tscratch_store_b32 off, v18, s33 offset:128 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v16\n\tscratch_load_b32 v16, off, s33 offset:128 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:124 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v14\n\tscratch_load_b32 v14, off, s33 offset:124 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:120 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v12\n\tscratch_load_b32 v12, off, s33 offset:120 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:116 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v10\n\tscratch_load_b32 v10, off, s33 offset:116 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:112 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v8\n\tscratch_load_b32 v8, off, s33 offset:112 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:108 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v6\n\tscratch_load_b32 v6, off, s33 offset:108 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:104 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v4\n\tscratch_load_b32 v4, off, s33 offset:104 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:100 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v2\n\tscratch_load_b32 v2, off, s33 offset:100 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:96 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v1, s33 offset:92 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v1, v0\n\tscratch_load_b32 v0, off, s33 offset:92 ; 4-byte Folded Reload\n\tv_writelane_b32 v26, s15, 2\n\tv_writelane_b32 v26, s14, 3\n\tv_writelane_b32 v26, s13, 4\n\tv_writelane_b32 v26, s12, 5\n\tv_writelane_b32 v26, s10, 6\n\tv_writelane_b32 v26, s11, 7\n\tv_writelane_b32 v26, s8, 8\n\tv_writelane_b32 v26, s9, 9\n\tv_writelane_b32 v26, s4, 10\n\tv_writelane_b32 v26, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\ts_waitcnt vmcnt(8)\n\tv_mov_b32_e32 v18, v16\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr15 killed $vgpr15 def $vgpr15_vgpr16 killed $exec\n\ts_waitcnt vmcnt(7)\n\tv_mov_b32_e32 v16, v14\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec\n\ts_waitcnt vmcnt(6)\n\tv_mov_b32_e32 v14, v12\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\ts_waitcnt vmcnt(5)\n\tv_mov_b32_e32 v12, v10\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\ts_waitcnt vmcnt(4)\n\tv_mov_b32_e32 v10, v8\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\ts_waitcnt vmcnt(3)\n\tv_mov_b32_e32 v8, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v6, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[17:18], s33 offset:84 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[15:16], s33 offset:76 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[13:14], s33 offset:68 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[11:12], s33 offset:60 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[9:10], s33 offset:52 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[7:8], s33 offset:44 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[5:6], s33 offset:36 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[3:4], s33 offset:28 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s0, -1\n\tv_mbcnt_lo_u32_b32 v0, s0, s1\n\tv_mbcnt_hi_u32_b32 v0, s0, v0\n\t;;#ASMSTART\n\t;;#ASMEND\n\tv_mov_b32_e32 v3, v0\n\tscratch_store_b32 off, v3, s33 offset:24 ; 4-byte Folded Spill\n\tv_readfirstlane_b32 s0, v0\n\tscratch_store_b64 off, v[1:2], s33 offset:16 ; 8-byte Folded Spill\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, s1\n\tv_writelane_b32 v26, s0, 12\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v0, 0\n\tv_mov_b32_e32 v1, 0\n\tscratch_store_b64 off, v[0:1], s33 offset:8 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 13\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_6\n; %bb.1:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_mov_b64 s[2:3], 24\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:160 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b64 s[2:3], 40\n\tv_mov_b32_e32 v4, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v5, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v4, s1, v4, s1\n\tv_add_co_ci_u32_e64 v6, s0, v5, s0, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tscratch_store_b64 off, v[4:5], s33 offset:152 ; 8-byte Folded Spill\n\tglobal_load_b64 v[5:6], v[0:1], off\n\tglobal_load_b64 v[10:11], v[0:1], off offset:40\n\tv_mov_b32_e32 v8, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v11\n\tv_and_b32_e64 v4, v4, v8\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v7, v10\n\tv_and_b32_e64 v12, v7, v9\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_mov_b32_e32 v4, v12\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[10:11], s0, v4, s1, 0\n\tv_mov_b32_e32 v14, v11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec\n\tv_mov_b32_e32 v15, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[12:13], s0, v[12:13]\n\tv_mov_b32_e32 v4, v12\n\tv_mad_u64_u32 v[12:13], s1, v4, s1, v[14:15]\n ; kill: def $vgpr12 killed $vgpr12 killed $vgpr12_vgpr13 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s1\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_lshlrev_b64 v[13:14], s0, v[12:13]\n\tv_mov_b32_e32 v7, v14\n\tv_mov_b32_e32 v11, v10\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\tv_mov_b32_e32 v4, v12\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v10, v13\n\tv_mov_b32_e32 v7, v11\n\tv_or_b32_e64 v10, v7, v10\n ; kill: def $vgpr10 killed $vgpr10 def $vgpr10_vgpr11 killed $exec\n\tv_mov_b32_e32 v11, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v11\n\tv_add_co_u32 v4, s0, v4, v7\n\tv_add_co_ci_u32_e64 v6, s0, v5, v6, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tglobal_load_b64 v[4:5], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v10, v5\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s0, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:144 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:136 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 15\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_5\n.LBB3_2: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 14\n\tscratch_load_b64 v[2:3], off, s33 offset:144 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:160 ; 8-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:152 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[5:6], v[4:5], off\n\tglobal_load_b64 v[10:11], v[7:8], off\n\tv_mov_b32_e32 v8, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v11\n\tv_and_b32_e64 v4, v4, v8\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v7, v10\n\tv_and_b32_e64 v12, v7, v9\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_mov_b32_e32 v4, v12\n\ts_mov_b32 s2, 24\n\tv_mad_u64_u32 v[10:11], s0, v4, s2, 0\n\tv_mov_b32_e32 v14, v11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec\n\tv_mov_b32_e32 v15, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[12:13], s0, v[12:13]\n\tv_mov_b32_e32 v4, v12\n\tv_mad_u64_u32 v[12:13], s2, v4, s2, v[14:15]\n ; kill: def $vgpr12 killed $vgpr12 killed $vgpr12_vgpr13 killed $exec\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s2\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_lshlrev_b64 v[13:14], s0, v[12:13]\n\tv_mov_b32_e32 v7, v14\n\tv_mov_b32_e32 v11, v10\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\tv_mov_b32_e32 v4, v12\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v10, v13\n\tv_mov_b32_e32 v7, v11\n\tv_or_b32_e64 v10, v7, v10\n ; kill: def $vgpr10 killed $vgpr10 def $vgpr10_vgpr11 killed $exec\n\tv_mov_b32_e32 v11, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v11\n\tv_add_co_u32 v4, s0, v4, v7\n\tv_add_co_ci_u32_e64 v6, s0, v5, v6, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tglobal_load_b64 v[4:5], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v10, v5\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e64 s0, v[0:1], v[2:3]\n\ts_or_b32 s0, s0, s1\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:144 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:168 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 16\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_2\n; %bb.3:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 16\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.4:\n\tscratch_load_b64 v[0:1], off, s33 offset:168 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:136 ; 8-byte Folded Spill\n.LBB3_5:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:136 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:8 ; 8-byte Folded Spill\n.LBB3_6:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 13\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:8 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[4:5], s0, v[4:5]\n\tv_mov_b32_e32 v2, v4\n\tv_readfirstlane_b32 s4, v3\n\tv_readfirstlane_b32 s2, v2\n ; implicit-def: $sgpr5\n ; implicit-def: $sgpr3\n ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3\n\ts_mov_b32 s3, s5\n\ts_lshl_b64 s[2:3], s[2:3], s0\n\ts_mov_b32 s0, 0\n ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5\n\ts_mov_b32 s5, s0\n\ts_or_b64 s[2:3], s[2:3], s[4:5]\n\tv_writelane_b32 v26, s2, 17\n\tv_writelane_b32 v26, s3, 18\n\tglobal_load_b64 v[2:3], v[0:1], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:200 ; 8-byte Folded Spill\n\ts_mov_b64 s[6:7], 40\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s7\n\tv_add_co_u32 v2, s4, v2, s4\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s4\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tglobal_load_b64 v[3:4], v[0:1], off offset:40\n\ts_mov_b32 s0, s3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v4\n\tv_and_b32_e64 v2, s0, v2\n\ts_mov_b32 s0, s2\n ; kill: def $vgpr3 killed $vgpr3 killed $vgpr3_vgpr4 killed $exec\n\tv_and_b32_e64 v3, s0, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v5, v3\n\tscratch_store_b64 off, v[5:6], s33 offset:184 ; 8-byte Folded Spill\n\tglobal_load_b64 v[1:2], v[0:1], off offset:8\n\ts_mov_b32 s0, 12\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s0, v0, v3\n\tv_add_co_ci_u32_e64 v2, s0, v1, v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:176 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], exec\n\tv_writelane_b32 v26, s2, 19\n\tv_writelane_b32 v26, s3, 20\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 21\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_8\n; %bb.7:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 19\n\tv_readlane_b32 s1, v26, 20\n\tscratch_load_b32 v2, off, s33 offset:96 ; 4-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v5, v0\n\ts_mov_b32 s3, 24\n\tv_mad_u64_u32 v[3:4], s2, v5, s3, 0\n\tv_mov_b32_e32 v9, v4\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v5, s2\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v5\n\ts_mov_b32 s2, 32\n\tv_lshrrev_b64 v[0:1], s2, v[0:1]\n\tv_mov_b32_e32 v5, v0\n\tv_mad_u64_u32 v[0:1], s3, v5, s3, v[9:10]\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v5, s3\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v5\n\tv_lshlrev_b64 v[9:10], s2, v[0:1]\n\tv_mov_b32_e32 v1, v10\n\tv_mov_b32_e32 v4, v3\n\ts_mov_b32 s2, 0\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v0, v5\n\tv_or_b32_e64 v0, v0, v1\n\tv_mov_b32_e32 v3, v9\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v5, v1, v3\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v0\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v3, v6\n\tv_add_co_u32 v0, s2, v0, v4\n\tv_add_co_ci_u32_e64 v3, s2, v1, v3, s2\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tglobal_store_b32 v[0:1], v2, off offset:16\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tglobal_store_b64 v[0:1], v[2:3], off offset:8\n\tv_mov_b32_e32 v2, 1\n\tglobal_store_b32 v[0:1], v2, off offset:20\n.LBB3_8:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[2:3], off, s33 offset:84 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:76 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:68 ; 8-byte Folded Reload\n\tscratch_load_b64 v[8:9], off, s33 offset:60 ; 8-byte Folded Reload\n\tscratch_load_b64 v[10:11], off, s33 offset:52 ; 8-byte Folded Reload\n\tscratch_load_b64 v[12:13], off, s33 offset:44 ; 8-byte Folded Reload\n\tscratch_load_b64 v[14:15], off, s33 offset:36 ; 8-byte Folded Reload\n\tscratch_load_b64 v[16:17], off, s33 offset:28 ; 8-byte Folded Reload\n\tscratch_load_b64 v[22:23], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:24 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v18, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v18\n\ts_mov_b32 s0, 6\n\ts_waitcnt vmcnt(0)\n\tv_lshlrev_b64 v[20:21], s0, v[0:1]\n\tv_mov_b32_e32 v0, v22\n\tv_mov_b32_e32 v19, v20\n\tv_mov_b32_e32 v1, v23\n\tv_mov_b32_e32 v18, v21\n\tv_add_co_u32 v0, s0, v0, v19\n\tv_add_co_ci_u32_e64 v18, s0, v1, v18, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v18\n\tscratch_store_b64 off, v[0:1], s33 offset:216 ; 8-byte Folded Spill\n\tglobal_store_b64 v[0:1], v[16:17], off\n\ts_mov_b64 s[4:5], 8\n\tv_mov_b32_e32 v16, v0\n\ts_mov_b32 s2, s4\n\tv_mov_b32_e32 v17, v1\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v16, s2, v16, s2\n\tv_add_co_ci_u32_e64 v18, s0, v17, s0, s2\n ; kill: def $vgpr16 killed $vgpr16 def $vgpr16_vgpr17 killed $exec\n\tv_mov_b32_e32 v17, v18\n\tscratch_store_b64 off, v[16:17], s33 offset:208 ; 8-byte Folded Spill\n\tglobal_store_b64 v[0:1], v[14:15], off offset:8\n\tglobal_store_b64 v[0:1], v[12:13], off offset:16\n\tglobal_store_b64 v[0:1], v[10:11], off offset:24\n\tglobal_store_b64 v[0:1], v[8:9], off offset:32\n\tglobal_store_b64 v[0:1], v[6:7], off offset:40\n\tglobal_store_b64 v[0:1], v[4:5], off offset:48\n\tglobal_store_b64 v[0:1], v[2:3], off offset:56\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 22\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_13\n; %bb.9:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[5:6], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:192 ; 8-byte Folded Reload\n\ts_mov_b64 s[4:5], 32\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s4\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:240 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:32 glc\n\ts_waitcnt vmcnt(1)\n\tglobal_load_b64 v[7:8], v[7:8], off\n\ts_mov_b32 s0, s3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v8\n\tv_and_b32_e64 v4, v4, s0\n\ts_mov_b32 s1, s2\n ; kill: def $vgpr7 killed $vgpr7 killed $vgpr7_vgpr8 killed $exec\n\tv_and_b32_e64 v7, v7, s1\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v4\n\tv_mov_b32_e32 v4, v7\n\ts_mov_b32 s3, 24\n\tv_mad_u64_u32 v[9:10], s2, v4, s3, 0\n\tv_mov_b32_e32 v11, v10\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v4, s2\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\ts_mov_b32 s2, 32\n\tv_lshrrev_b64 v[7:8], s2, v[7:8]\n\tv_mov_b32_e32 v4, v7\n\tv_mad_u64_u32 v[7:8], s3, v4, s3, v[11:12]\n ; kill: def $vgpr7 killed $vgpr7 killed $vgpr7_vgpr8 killed $exec\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v4, s3\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v4\n\tv_lshlrev_b64 v[7:8], s2, v[7:8]\n\tv_mov_b32_e32 v11, v8\n ; kill: def $vgpr9 killed $vgpr9 killed $vgpr9_vgpr10 killed $exec\n\ts_mov_b32 s2, 0\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v4, v10\n\tv_or_b32_e64 v4, v4, v11\n\tv_mov_b32_e32 v8, v7\n\tv_mov_b32_e32 v7, v9\n\tv_or_b32_e64 v8, v7, v8\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v8\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v9\n\tv_add_co_u32 v4, s2, v4, v7\n\tv_add_co_ci_u32_e64 v6, s2, v5, v6, s2\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tscratch_store_b64 off, v[4:5], s33 offset:232 ; 8-byte Folded Spill\n\tglobal_store_b64 v[4:5], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s1\n\tv_mov_b32_e32 v10, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s2, v[0:1], v[2:3]\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s2, 23\n\tv_writelane_b32 v26, s0, 24\n\tscratch_store_b64 off, v[0:1], s33 offset:224 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 25\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_14\n.LBB3_10: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 24\n\tv_readlane_b32 s1, v26, 23\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[2:3], off, s33 offset:224 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:240 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:232 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_store_b64 v[4:5], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n\ts_mov_b32 s1, s3\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v10, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s1, v[0:1], v[2:3]\n\ts_or_b32 s0, s1, s0\n\tv_writelane_b32 v26, s1, 23\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 24\n\tscratch_store_b64 off, v[0:1], s33 offset:224 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 26\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_10\n; %bb.11:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 26\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.12:\n\ts_branch .LBB3_14\n.LBB3_13:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_branch .LBB3_15\n.LBB3_14:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 25\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s15, v26, 2\n\tv_readlane_b32 s14, v26, 3\n\tv_readlane_b32 s13, v26, 4\n\tv_readlane_b32 s12, v26, 5\n\tv_readlane_b32 s10, v26, 6\n\tv_readlane_b32 s11, v26, 7\n\tv_readlane_b32 s8, v26, 8\n\tv_readlane_b32 s9, v26, 9\n\tv_readlane_b32 s6, v26, 0\n\tv_readlane_b32 s7, v26, 1\n\tv_readlane_b32 s4, v26, 10\n\tv_readlane_b32 s5, v26, 11\n\tscratch_load_b32 v31, off, s33 offset:132 ; 4-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_mov_b32 s0, 32\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[0:1], s0, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v2\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hsa_signal_add@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hsa_signal_add@rel32@hi+12\n\tv_mov_b32_e32 v2, 1\n\tv_mov_b32_e32 v3, 0\n\tv_mov_b32_e32 v4, 3\n\ts_swappc_b64 s[30:31], s[0:1]\n\ts_branch .LBB3_13\n.LBB3_15:\n\tscratch_load_b64 v[6:7], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[3:4], s0, v2, s1, 0\n\tv_mov_b32_e32 v8, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v2\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[0:1]\n\tv_mov_b32_e32 v2, v0\n\tv_mad_u64_u32 v[0:1], s1, v2, s1, v[8:9]\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_lshlrev_b64 v[1:2], s0, v[0:1]\n\tv_mov_b32_e32 v5, v2\n ; kill: def $vgpr3 killed $vgpr3 killed $vgpr3_vgpr4 killed $exec\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_mov_b32_e32 v0, v4\n\tv_or_b32_e64 v0, v0, v5\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v1, v3\n\tv_or_b32_e64 v4, v1, v2\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v1, v6\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v1, s0, v1, v3\n\tv_add_co_ci_u32_e64 v0, s0, v0, v2, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b64 s[2:3], 20\n\tv_mov_b32_e32 v0, v1\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v1, v2\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v0, s1, v0, s1\n\tv_add_co_ci_u32_e64 v2, s0, v1, s0, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:248 ; 8-byte Folded Spill\n.LBB3_16: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 12\n\ts_mov_b32 s0, 1\n\tv_mov_b32_e32 v0, 1\n\tscratch_store_b32 off, v0, s33 offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 27\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_18\n; %bb.17: ; in Loop: Header=BB3_16 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:248 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b32 v0, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b32 s0, 1\n\tv_and_b32_e64 v0, v0, s0\n\tscratch_store_b32 off, v0, s33 offset:256 ; 4-byte Folded Spill\n.LBB3_18: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 27\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s33 offset:256 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s1, v0\n\ts_mov_b32 s0, -1\n\ts_mov_b32 s2, 0\n\ts_cmp_eq_u32 s1, s2\n\tv_writelane_b32 v26, s0, 28\n\ts_mov_b32 s17, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_cbranch_scc1 .LBB3_20\n; %bb.19: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_sleep 1\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v26, s0, 28\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n.LBB3_20: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 28\n\tv_cndmask_b32_e64 v0, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v0, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n\ts_cbranch_vccnz .LBB3_16\n; %bb.21:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[0:1], off, s33 offset:208 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:216 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[2:3], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:268 ; 8-byte Folded Spill\n\tglobal_load_b64 v[0:1], v[0:1], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:260 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 29\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_27\n; %bb.22:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:192 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[11:12], v[2:3], off\n\ts_mov_b64 s[4:5], 1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v11\n\ts_mov_b32 s1, s4\n\tv_mov_b32_e32 v3, v12\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v4, v2\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v5, v3\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v4, s1, v4, s1\n\tv_add_co_ci_u32_e64 v6, s0, v5, s0, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_eq_u64_e64 s0, v[4:5], s[0:1]\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v6, v5\n\tv_cndmask_b32_e64 v10, v6, v7, s0\n\tv_mov_b32_e32 v3, v2\n\tv_mov_b32_e32 v2, v4\n\tv_cndmask_b32_e64 v4, v2, v3, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v8, v4\n\tv_mov_b32_e32 v9, v10\n\tv_mov_b32_e32 v2, v8\n\tv_mov_b32_e32 v3, v9\n\tscratch_store_b64 off, v[2:3], s33 offset:300 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], 24\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v5, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v5\n\tscratch_store_b64 off, v[2:3], s33 offset:292 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:24 glc\n\tglobal_load_b64 v[6:7], v[0:1], off\n\tv_mov_b32_e32 v5, v9\n\tv_mov_b32_e32 v13, v12\n\tv_and_b32_e64 v5, v5, v13\n ; kill: def $vgpr8 killed $vgpr8 killed $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v11\n\tv_and_b32_e64 v8, v8, v9\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v5\n\tv_mov_b32_e32 v5, v8\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[11:12], s0, v5, s1, 0\n\tv_mov_b32_e32 v13, v12\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v5, s0\n ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec\n\tv_mov_b32_e32 v14, v5\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[8:9], s0, v[8:9]\n\tv_mov_b32_e32 v5, v8\n\tv_mad_u64_u32 v[8:9], s1, v5, s1, v[13:14]\n ; kill: def $vgpr8 killed $vgpr8 killed $vgpr8_vgpr9 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v5, s1\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v5\n\tv_lshlrev_b64 v[8:9], s0, v[8:9]\n\tv_mov_b32_e32 v13, v9\n ; kill: def $vgpr11 killed $vgpr11 killed $vgpr11_vgpr12 killed $exec\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v5, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v5\n\tv_mov_b32_e32 v5, v12\n\tv_or_b32_e64 v5, v5, v13\n\tv_mov_b32_e32 v9, v8\n\tv_mov_b32_e32 v8, v11\n\tv_or_b32_e64 v11, v8, v9\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v5\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v8, v11\n\tv_mov_b32_e32 v6, v7\n\tv_mov_b32_e32 v7, v12\n\tv_add_co_u32 v5, s0, v5, v8\n\tv_add_co_ci_u32_e64 v7, s0, v6, v7, s0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v7\n\tscratch_store_b64 off, v[5:6], s33 offset:284 ; 8-byte Folded Spill\n\tglobal_store_b64 v[5:6], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s2, v[0:1], v[2:3]\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s2, 30\n\tv_writelane_b32 v26, s0, 31\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\tscratch_store_b64 off, v[0:1], s33 offset:276 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n ; implicit-def: $vgpr26 : SGPR spill to VGPR lane\n\tv_writelane_b32 v26, s0, 0\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_26\n.LBB3_23: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v25, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v25, 31\n\tv_readlane_b32 s1, v25, 30\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\tscratch_load_b64 v[2:3], off, s33 offset:276 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:292 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:300 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:284 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_store_b64 v[6:7], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v10, v5\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s1, v[0:1], v[2:3]\n\ts_or_b32 s0, s1, s0\n\tv_writelane_b32 v25, s1, 30\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v25, s1, 31\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v25, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\tscratch_store_b64 off, v[0:1], s33 offset:276 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_23\n; %bb.24:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.25:\n.LBB3_26:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 0\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB3_27:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[3:4], off, s33 offset:260 ; 8-byte Folded Reload\n\tscratch_load_b64 v[1:2], off, s33 offset:268 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v3\n\tv_mov_b32_e32 v3, v4\n\tv_readlane_b32 s30, v24, 0\n\tv_readlane_b32 s31, v24, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v24, off, s33 offset:308 ; 4-byte Folded Reload\n\tscratch_load_b32 v25, off, s33 offset:312 ; 4-byte Folded Reload\n\tscratch_load_b32 v26, off, s33 offset:316 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xfffffeb0\n\ts_mov_b32 s33, s18\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end3:\n\t.size\t__ockl_hostcall_internal, .Lfunc_end3-__ockl_hostcall_internal\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 5344\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 392\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hostcall_preview\n\t.type\t__ockl_hostcall_preview,@function\n__ockl_hostcall_preview: ; @__ockl_hostcall_preview\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v27, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tv_writelane_b32 v27, s33, 0\n\tv_writelane_b32 v27, s30, 1\n\tv_writelane_b32 v27, s31, 2\n\tv_mov_b32_e32 v18, v16\n\tv_mov_b32_e32 v17, v15\n\tv_mov_b32_e32 v16, v14\n\tv_mov_b32_e32 v15, v13\n\tv_mov_b32_e32 v14, v12\n\tv_mov_b32_e32 v13, v11\n\tv_mov_b32_e32 v12, v10\n\tv_mov_b32_e32 v11, v9\n\tv_mov_b32_e32 v10, v8\n\tv_mov_b32_e32 v9, v7\n\tv_mov_b32_e32 v8, v6\n\tv_mov_b32_e32 v7, v5\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v5, v3\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s0, s[0:1], 0x0\n\ts_mov_b32 s1, 0x1f4\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_i32 s0, s1\n\ts_mov_b32 s1, 0x50\n\ts_mov_b32 s0, 24\n\ts_cselect_b32 s0, s0, s1\n\ts_load_b64 s[0:1], s[8:9], s0 offset:0x0\n\ts_waitcnt lgkmcnt(0)\n\ts_mov_b32 s3, s0\n\ts_mov_b32 s2, 32\n\ts_lshr_b64 s[0:1], s[0:1], s2\n\ts_mov_b32 s2, s0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_internal@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_internal@rel32@hi+12\n\tv_mov_b32_e32 v0, s3\n\tv_mov_b32_e32 v1, s2\n\tv_readlane_b32 s30, v27, 1\n\tv_readlane_b32 s31, v27, 2\n\tv_readlane_b32 s33, v27, 0\n\ts_xor_saveexec_b32 s2, -1\n\tscratch_load_b32 v27, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s2\n\ts_setpc_b64 s[0:1]\n.Lfunc_end4:\n\t.size\t__ockl_hostcall_preview, .Lfunc_end4-__ockl_hostcall_preview\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 272\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 400\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_stderr_begin\n\t.type\t__ockl_fprintf_stderr_begin,@function\n__ockl_fprintf_stderr_begin: ; @__ockl_fprintf_stderr_begin\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s16, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v28, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 16\n\tv_writelane_b32 v28, s30, 0\n\tv_writelane_b32 v28, s31, 1\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\tv_mov_b32_e32 v1, 33\n\tv_mov_b32_e32 v3, 1\n\tv_mov_b32_e32 v16, 0\n\tv_mov_b32_e32 v2, v16\n\tv_mov_b32_e32 v4, v16\n\tv_mov_b32_e32 v5, v16\n\tv_mov_b32_e32 v6, v16\n\tv_mov_b32_e32 v7, v16\n\tv_mov_b32_e32 v8, v16\n\tv_mov_b32_e32 v9, v16\n\tv_mov_b32_e32 v10, v16\n\tv_mov_b32_e32 v11, v16\n\tv_mov_b32_e32 v12, v16\n\tv_mov_b32_e32 v13, v16\n\tv_mov_b32_e32 v14, v16\n\tv_mov_b32_e32 v15, v16\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_store_b32 off, v1, s33 ; 4-byte Folded Spill\n ; kill: def $vgpr1 killed $vgpr3 killed $exec\n\tscratch_load_b32 v3, off, s33 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v3\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v28, 0\n\tv_readlane_b32 s31, v28, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v28, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, -16\n\ts_mov_b32 s33, s16\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end5:\n\t.size\t__ockl_fprintf_stderr_begin, .Lfunc_end5-__ockl_fprintf_stderr_begin\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 228\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 416\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_append_string_n\n\t.type\t__ockl_fprintf_append_string_n,@function\n__ockl_fprintf_append_string_n: ; @__ockl_fprintf_append_string_n\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s20, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v32, s33 offset:704 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v33, s33 offset:708 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v34, s33 offset:712 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0x2d0\n\tv_writelane_b32 v32, s30, 0\n\tv_writelane_b32 v32, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:68 ; 4-byte Folded Spill\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\tv_writelane_b32 v34, s6, 0\n\tv_writelane_b32 v34, s7, 1\n\tscratch_store_b32 off, v6, s33 offset:60 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v5, s33 offset:56 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v4, s33 offset:64 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v6, v3\n\tscratch_load_b32 v3, off, s33 offset:64 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v4, v2\n\tscratch_load_b32 v2, off, s33 offset:60 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v4, s33 offset:52 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v7, v1\n\tscratch_load_b32 v1, off, s33 offset:56 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v5, v0\n\tscratch_load_b32 v0, off, s33 offset:52 ; 4-byte Folded Reload\n\tv_writelane_b32 v34, s15, 2\n\tv_writelane_b32 v34, s14, 3\n\tv_writelane_b32 v34, s13, 4\n\tv_writelane_b32 v34, s12, 5\n\tv_writelane_b32 v34, s10, 6\n\tv_writelane_b32 v34, s11, 7\n\tv_writelane_b32 v34, s8, 8\n\tv_writelane_b32 v34, s9, 9\n\tv_writelane_b32 v34, s4, 10\n\tv_writelane_b32 v34, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v1\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v7\n\tscratch_store_b64 off, v[3:4], s33 offset:44 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v3, v0\n\tscratch_store_b64 off, v[3:4], s33 offset:36 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s0, 0\n\tv_cmp_eq_u32_e64 s0, v2, s0\n\tv_mov_b32_e32 v4, v6\n\ts_mov_b64 s[2:3], 2\n\ts_mov_b32 s1, s3\n\tv_or_b32_e64 v2, v4, s1\n\tv_mov_b32_e32 v3, v5\n\ts_mov_b32 s1, s2\n\tv_or_b32_e64 v5, v3, s1\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v2\n\tv_mov_b32_e32 v2, v6\n\tv_cndmask_b32_e64 v4, v2, v4, s0\n\tv_mov_b32_e32 v2, v5\n\tv_cndmask_b32_e64 v2, v2, v3, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:28 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_ne_u64_e64 s0, v[0:1], s[0:1]\n ; implicit-def: $sgpr4_sgpr5_sgpr6_sgpr7\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tv_mov_b32_e32 v2, s6\n\tv_mov_b32_e32 v3, s7\n\tscratch_store_b128 off, v[0:3], s33 offset:12 ; 16-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 12\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_3\n\ts_branch .LBB6_2\n.LBB6_1:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v34, 2\n\tv_readlane_b32 s14, v34, 3\n\tv_readlane_b32 s13, v34, 4\n\tv_readlane_b32 s12, v34, 5\n\tv_readlane_b32 s10, v34, 6\n\tv_readlane_b32 s11, v34, 7\n\tv_readlane_b32 s8, v34, 8\n\tv_readlane_b32 s9, v34, 9\n\tv_readlane_b32 s6, v34, 0\n\tv_readlane_b32 s7, v34, 1\n\tv_readlane_b32 s4, v34, 10\n\tv_readlane_b32 s5, v34, 11\n\tscratch_load_b32 v31, off, s33 offset:68 ; 4-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:28 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v3\n\tv_and_b32_e64 v4, v0, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v0, v2\n\tv_and_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_mov_b32_e32 v4, v1\n\ts_mov_b64 s[0:1], 32\n\ts_mov_b32 s2, s1\n\tv_or_b32_e64 v4, v4, s2\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_or_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_mov_b32_e32 v1, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[2:3], s0, v[2:3]\n ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\tv_mov_b32_e32 v16, 0\n\tscratch_store_b32 off, v16, s33 offset:88 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v16\n\tv_mov_b32_e32 v4, v16\n\tv_mov_b32_e32 v5, v16\n\tv_mov_b32_e32 v6, v16\n\tv_mov_b32_e32 v7, v16\n\tv_mov_b32_e32 v8, v16\n\tv_mov_b32_e32 v9, v16\n\tv_mov_b32_e32 v10, v16\n\tv_mov_b32_e32 v11, v16\n\tv_mov_b32_e32 v12, v16\n\tv_mov_b32_e32 v13, v16\n\tv_mov_b32_e32 v14, v16\n\tv_mov_b32_e32 v15, v16\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_mov_b32_e32 v6, v1\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v4, v3\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v6\n\tv_mov_b32_e32 v2, v5\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b128 off, v[0:3], s33 offset:72 ; 16-byte Folded Spill\n\ts_branch .LBB6_63\n.LBB6_2:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b64 v[4:5], off, s33 offset:36 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:44 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:28 ; 8-byte Folded Reload\n\ts_mov_b64 s[0:1], 2\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v1, v3\n\tv_and_b32_e64 v8, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v0, v2\n\tv_and_b32_e64 v2, v0, s0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v8\n\tscratch_store_b64 off, v[2:3], s33 offset:124 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], -3\n\ts_mov_b32 s2, s1\n\tv_and_b32_e64 v2, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_and_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v10, v1\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\ts_mov_b64 s[2:3], 0\n\ts_mov_b32 s0, s3\n\ts_mov_b32 s1, s2\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v9, s1\n\tv_mov_b32_e32 v8, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v10\n\tv_mov_b32_e32 v2, v9\n\tv_mov_b32_e32 v3, v8\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v34, s0, 13\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[6:7], s33 offset:116 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[4:5], s33 offset:108 ; 8-byte Folded Spill\n\tscratch_store_b128 off, v[0:3], s33 offset:92 ; 16-byte Folded Spill\n\ts_branch .LBB6_4\n.LBB6_3:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 12\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b128 v[0:3], off, s33 offset:12 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:72 ; 16-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 14\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_63\n\ts_branch .LBB6_1\n.LBB6_4: ; =>This Loop Header: Depth=1\n ; Child Loop BB6_8 Depth 2\n ; Child Loop BB6_16 Depth 2\n ; Child Loop BB6_24 Depth 2\n ; Child Loop BB6_32 Depth 2\n ; Child Loop BB6_40 Depth 2\n ; Child Loop BB6_48 Depth 2\n ; Child Loop BB6_56 Depth 2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 13\n\tscratch_load_b64 v[6:7], off, s33 offset:124 ; 8-byte Folded Reload\n\tscratch_load_b128 v[8:11], off, s33 offset:92 ; 16-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:116 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:108 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:176 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[3:4], s33 offset:168 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 15\n\ts_mov_b64 s[2:3], 56\n\tv_cmp_gt_u64_e64 s0, v[3:4], s[2:3]\n\tv_mov_b32_e32 v1, v9\n\tv_mov_b32_e32 v2, v8\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v8, v2\n\tv_mov_b32_e32 v9, v1\n\tv_mov_b32_e32 v0, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or_b32_e64 v0, v0, v5\n\tv_mov_b32_e32 v5, v8\n\tv_or_b32_e64 v5, v5, v6\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v0\n\tv_mov_b32_e32 v0, v6\n\tv_cndmask_b32_e64 v0, v0, v1, s0\n\tv_mov_b32_e32 v1, v5\n\tv_cndmask_b32_e64 v1, v1, v2, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_cmp_lt_u64_e64 s1, v[3:4], s[2:3]\n\tv_mov_b32_e32 v0, v4\n\ts_mov_b32 s0, s3\n\tv_cndmask_b32_e64 v5, s0, v0, s1\n\tv_mov_b32_e32 v0, v3\n\ts_mov_b32 s0, s2\n\tv_cndmask_b32_e64 v0, s0, v0, s1\n\tscratch_store_b32 off, v0, s33 offset:164 ; 4-byte Folded Spill\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v3, v0\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:156 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:148 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:140 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:132 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 16\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_6\n; %bb.5: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:164 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 17\n\tv_writelane_b32 v34, s0, 18\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:184 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_11\n\ts_branch .LBB6_8\n.LBB6_6: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 16\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 20\n\tscratch_load_b64 v[0:1], off, s33 offset:140 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:132 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:212 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:208 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:200 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 21\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_12\n; %bb.7: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:212 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:208 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:200 ; 8-byte Folded Spill\n\ts_branch .LBB6_12\n.LBB6_8: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 18\n\tv_readlane_b32 s2, v34, 17\n\tscratch_load_b64 v[4:5], off, s33 offset:192 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:176 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 17\n\tv_writelane_b32 v34, s1, 18\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:220 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 22\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_8\n; %bb.9: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.10: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:220 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:184 ; 8-byte Folded Spill\n.LBB6_11: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 19\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:140 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 20\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:132 ; 8-byte Folded Spill\n\ts_branch .LBB6_6\n.LBB6_12: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:212 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:208 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:200 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:256 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:252 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:244 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:236 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:228 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 23\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_14\n; %bb.13: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:252 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 24\n\tv_writelane_b32 v34, s0, 25\n\tscratch_store_b64 off, v[2:3], s33 offset:272 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:264 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 26\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_19\n\ts_branch .LBB6_16\n.LBB6_14: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 23\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 27\n\tscratch_load_b64 v[0:1], off, s33 offset:236 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:228 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:292 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:288 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:280 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 28\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_20\n; %bb.15: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:244 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:252 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:292 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:288 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:280 ; 8-byte Folded Spill\n\ts_branch .LBB6_20\n.LBB6_16: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 25\n\tv_readlane_b32 s2, v34, 24\n\tscratch_load_b64 v[4:5], off, s33 offset:272 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:252 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:244 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 24\n\tv_writelane_b32 v34, s1, 25\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:272 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:300 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 29\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_16\n; %bb.17: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.18: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:300 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:264 ; 8-byte Folded Spill\n.LBB6_19: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 26\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:244 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:264 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:236 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 27\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:228 ; 8-byte Folded Spill\n\ts_branch .LBB6_14\n.LBB6_20: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 28\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:292 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:288 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:280 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:336 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:332 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:324 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:316 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:308 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 30\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_22\n; %bb.21: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:332 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v33, s2, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tv_writelane_b32 v34, s0, 0\n\tscratch_store_b64 off, v[2:3], s33 offset:352 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:344 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_27\n\ts_branch .LBB6_24\n.LBB6_22: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v33, 30\n\ts_or_saveexec_b32 s0, s0\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v34, 2\n\tscratch_load_b64 v[0:1], off, s33 offset:316 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:308 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:372 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:368 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:360 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 3\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_28\n; %bb.23: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:324 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:332 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:372 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:368 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:360 ; 8-byte Folded Spill\n\ts_branch .LBB6_28\n.LBB6_24: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 0\n\tv_readlane_b32 s2, v33, 31\n\tscratch_load_b64 v[4:5], off, s33 offset:352 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:332 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:324 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v33, s2, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tv_writelane_b32 v34, s1, 0\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:352 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:380 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 4\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_24\n; %bb.25: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.26: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:380 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:344 ; 8-byte Folded Spill\n.LBB6_27: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:324 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:344 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:316 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:308 ; 8-byte Folded Spill\n\ts_branch .LBB6_22\n.LBB6_28: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 3\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:372 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:368 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:360 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:416 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:412 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:404 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:396 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:388 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 5\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_30\n; %bb.29: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:412 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 6\n\tv_writelane_b32 v34, s0, 7\n\tscratch_store_b64 off, v[2:3], s33 offset:432 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:424 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 8\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_35\n\ts_branch .LBB6_32\n.LBB6_30: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 5\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 9\n\tscratch_load_b64 v[0:1], off, s33 offset:396 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:388 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:452 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:448 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:440 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 10\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_36\n; %bb.31: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:404 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:412 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:452 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:448 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:440 ; 8-byte Folded Spill\n\ts_branch .LBB6_36\n.LBB6_32: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 7\n\tv_readlane_b32 s2, v34, 6\n\tscratch_load_b64 v[4:5], off, s33 offset:432 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:412 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:404 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 6\n\tv_writelane_b32 v34, s1, 7\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:432 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:460 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 11\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_32\n; %bb.33: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 11\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.34: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:460 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:424 ; 8-byte Folded Spill\n.LBB6_35: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 8\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:404 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:424 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:396 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 9\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:388 ; 8-byte Folded Spill\n\ts_branch .LBB6_30\n.LBB6_36: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 10\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:452 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:448 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:440 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:496 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:492 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:484 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:476 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:468 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 12\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_38\n; %bb.37: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:492 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 13\n\tv_writelane_b32 v34, s0, 14\n\tscratch_store_b64 off, v[2:3], s33 offset:512 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:504 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 15\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_43\n\ts_branch .LBB6_40\n.LBB6_38: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 12\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 16\n\tscratch_load_b64 v[0:1], off, s33 offset:476 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:468 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:532 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:528 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:520 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 17\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_44\n; %bb.39: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:484 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:492 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:532 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:528 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:520 ; 8-byte Folded Spill\n\ts_branch .LBB6_44\n.LBB6_40: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 14\n\tv_readlane_b32 s2, v34, 13\n\tscratch_load_b64 v[4:5], off, s33 offset:512 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:492 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:484 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 13\n\tv_writelane_b32 v34, s1, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:512 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:540 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 18\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_40\n; %bb.41: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 18\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.42: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:540 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:504 ; 8-byte Folded Spill\n.LBB6_43: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:484 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:504 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:476 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 16\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:468 ; 8-byte Folded Spill\n\ts_branch .LBB6_38\n.LBB6_44: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 17\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:532 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:528 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:520 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:576 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:572 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:564 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:556 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:548 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_46\n; %bb.45: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:572 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 20\n\tv_writelane_b32 v34, s0, 21\n\tscratch_store_b64 off, v[2:3], s33 offset:592 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:584 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 22\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_51\n\ts_branch .LBB6_48\n.LBB6_46: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 19\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 23\n\tscratch_load_b64 v[0:1], off, s33 offset:556 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:548 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:612 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:608 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:600 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 24\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_52\n; %bb.47: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:564 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:572 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:612 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:608 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:600 ; 8-byte Folded Spill\n\ts_branch .LBB6_52\n.LBB6_48: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 21\n\tv_readlane_b32 s2, v34, 20\n\tscratch_load_b64 v[4:5], off, s33 offset:592 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:572 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:564 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 20\n\tv_writelane_b32 v34, s1, 21\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:592 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:620 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 25\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_48\n; %bb.49: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 25\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.50: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:620 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:584 ; 8-byte Folded Spill\n.LBB6_51: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:564 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:584 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:556 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 23\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:548 ; 8-byte Folded Spill\n\ts_branch .LBB6_46\n.LBB6_52: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 24\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:612 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:608 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:600 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:648 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:644 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:636 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s33 offset:628 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 26\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_54\n; %bb.53: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:644 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 27\n\tv_writelane_b32 v34, s0, 28\n\tscratch_store_b64 off, v[2:3], s33 offset:664 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:656 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 29\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_59\n\ts_branch .LBB6_56\n.LBB6_54: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 26\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:628 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:672 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 30\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_60\n; %bb.55: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[2:3], off, s33 offset:636 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tflat_load_u8 v0, v[2:3]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v4, v[2:3] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v5, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v7, v1\n\tv_mov_b32_e32 v4, v6\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v5\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v4\n\tflat_load_u8 v4, v[2:3] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v8, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v4\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v10, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or3_b32 v4, v4, v5, v10\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v5, v8\n\tv_mov_b32_e32 v1, v6\n\tv_or3_b32 v0, v0, v1, v5\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v4, s1, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[6:7], s2, v[4:5]\n\tflat_load_u8 v4, v[2:3] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v4, s1, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[8:9], s0, v[4:5]\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v10, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or3_b32 v4, v4, v5, v10\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v5, v8\n\tv_mov_b32_e32 v1, v6\n\tv_or3_b32 v0, v0, v1, v5\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:6\n\tv_mov_b32_e32 v6, 0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[4:5], s0, v[4:5]\n\tflat_load_u8 v2, v[2:3] offset:7\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v6\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[6:7], s0, v[2:3]\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v8, v7\n\tv_mov_b32_e32 v3, v5\n\tv_or3_b32 v2, v2, v3, v8\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v3, v6\n\tv_mov_b32_e32 v1, v4\n\tv_or3_b32 v0, v0, v1, v3\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:672 ; 8-byte Folded Spill\n\ts_branch .LBB6_60\n.LBB6_56: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 28\n\tv_readlane_b32 s2, v34, 27\n\tscratch_load_b64 v[4:5], off, s33 offset:664 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:644 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:636 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 27\n\tv_writelane_b32 v34, s1, 28\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:664 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:680 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_56\n; %bb.57: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 31\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.58: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:680 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:656 ; 8-byte Folded Spill\n.LBB6_59: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:656 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:628 ; 8-byte Folded Spill\n\ts_branch .LBB6_54\n.LBB6_60: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v34, 30\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v33, 2\n\tv_readlane_b32 s14, v33, 3\n\tv_readlane_b32 s13, v33, 4\n\tv_readlane_b32 s12, v33, 5\n\tv_readlane_b32 s10, v33, 6\n\tv_readlane_b32 s11, v33, 7\n\tv_readlane_b32 s8, v33, 8\n\tv_readlane_b32 s9, v33, 9\n\tv_readlane_b32 s6, v33, 0\n\tv_readlane_b32 s7, v33, 1\n\tv_readlane_b32 s4, v33, 10\n\tv_readlane_b32 s5, v33, 11\n\tscratch_load_b64 v[0:1], off, s33 offset:156 ; 8-byte Folded Reload\n\tscratch_load_b32 v31, off, s33 offset:68 ; 4-byte Folded Reload\n\tscratch_load_b64 v[19:20], off, s33 offset:648 ; 8-byte Folded Reload\n\tscratch_load_b64 v[21:22], off, s33 offset:576 ; 8-byte Folded Reload\n\tscratch_load_b64 v[23:24], off, s33 offset:496 ; 8-byte Folded Reload\n\tscratch_load_b64 v[25:26], off, s33 offset:416 ; 8-byte Folded Reload\n\tscratch_load_b64 v[27:28], off, s33 offset:336 ; 8-byte Folded Reload\n\tscratch_load_b64 v[29:30], off, s33 offset:256 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:148 ; 8-byte Folded Reload\n\tscratch_load_b64 v[17:18], off, s33 offset:672 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(9)\n\tv_mov_b32_e32 v1, v0\n\ts_mov_b32 s0, 28\n\tv_mov_b32_e32 v0, 2\n\tv_lshl_add_u32 v1, v1, v0, s0\n\ts_mov_b32 s0, 0x1e0\n\tv_and_b32_e64 v5, v1, s0\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v1, 0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v1\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v1, v3\n\tv_and_b32_e64 v1, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v4, v2\n\tv_and_b32_e64 v7, v4, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v4, v6\n\tv_or_b32_e64 v1, v1, v4\n\tv_mov_b32_e32 v4, v7\n ; kill: def $vgpr5 killed $vgpr5 killed $vgpr5_vgpr6 killed $exec\n\tv_or_b32_e64 v4, v4, v5\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v1\n\tv_mov_b32_e32 v1, v4\n\ts_mov_b32 s0, 32\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\tv_writelane_b32 v34, s0, 0\n\tv_lshrrev_b64 v[2:3], s0, v[2:3]\n ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec\n\tv_lshrrev_b64 v[3:4], s0, v[29:30]\n\tv_mov_b32_e32 v4, v3\n\tv_lshrrev_b64 v[5:6], s0, v[27:28]\n\tv_mov_b32_e32 v6, v5\n\tv_lshrrev_b64 v[7:8], s0, v[25:26]\n\tv_mov_b32_e32 v8, v7\n\tv_lshrrev_b64 v[9:10], s0, v[23:24]\n\tv_mov_b32_e32 v10, v9\n\tv_lshrrev_b64 v[11:12], s0, v[21:22]\n\tv_mov_b32_e32 v12, v11\n\tv_lshrrev_b64 v[13:14], s0, v[19:20]\n\tv_mov_b32_e32 v14, v13\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[15:16], s0, v[17:18]\n\tv_mov_b32_e32 v16, v15\n\tv_mov_b32_e32 v3, v29\n\tv_mov_b32_e32 v5, v27\n\tv_mov_b32_e32 v7, v25\n\tv_mov_b32_e32 v9, v23\n\tv_mov_b32_e32 v11, v21\n\tv_mov_b32_e32 v13, v19\n\tv_mov_b32_e32 v15, v17\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b64 v[4:5], off, s33 offset:168 ; 8-byte Folded Reload\n\tscratch_load_b64 v[12:13], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b64 v[10:11], off, s33 offset:156 ; 8-byte Folded Reload\n\tv_readlane_b32 s1, v33, 15\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v7, v2\n\tv_mov_b32_e32 v6, v3\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v2, v7\n\tv_mov_b32_e32 v3, v6\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v6, v4\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v5, v11\n\tv_sub_co_u32 v6, s0, v6, v7\n\tv_sub_co_ci_u32_e64 v4, s0, v4, v5, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v4\n\tv_mov_b32_e32 v4, v12\n\tv_mov_b32_e32 v9, v10\n\tv_mov_b32_e32 v5, v13\n\tv_mov_b32_e32 v8, v11\n\tv_add_co_u32 v4, s0, v4, v9\n\tv_add_co_ci_u32_e64 v8, s0, v5, v8, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v8\n\ts_mov_b64 s[2:3], 0\n\tv_cmp_eq_u64_e64 s0, v[6:7], s[2:3]\n\ts_or_b32 s0, s0, s1\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v33, s1, 13\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[6:7], s33 offset:116 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[4:5], s33 offset:108 ; 8-byte Folded Spill\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v6, v2\n\tv_mov_b32_e32 v5, v1\n\tv_mov_b32_e32 v4, v0\n\tscratch_store_b128 off, v[4:7], s33 offset:92 ; 16-byte Folded Spill\n\tscratch_store_b128 off, v[0:3], s33 offset:688 ; 16-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:8 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_4\n; %bb.61:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:8 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.62:\n\tscratch_load_b128 v[0:3], off, s33 offset:688 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:12 ; 16-byte Folded Spill\n\ts_branch .LBB6_3\n.LBB6_63:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 14\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b128 v[3:6], off, s33 offset:72 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v0, v3\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v32, 0\n\tv_readlane_b32 s31, v32, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v32, off, s33 offset:704 ; 4-byte Folded Reload\n\tscratch_load_b32 v33, off, s33 offset:708 ; 4-byte Folded Reload\n\tscratch_load_b32 v34, off, s33 offset:712 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xfffffd30\n\ts_mov_b32 s33, s20\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end6:\n\t.size\t__ockl_fprintf_append_string_n, .Lfunc_end6-__ockl_fprintf_append_string_n\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 11984\n; NumSgprs: 36\n; NumVgprs: 35\n; ScratchSize: 1120\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_append_args\n\t.type\t__ockl_fprintf_append_args,@function\n__ockl_fprintf_append_args: ; @__ockl_fprintf_append_args\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s19, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v28, s33 offset:8 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v29, s33 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 32\n\tv_writelane_b32 v28, s30, 0\n\tv_writelane_b32 v28, s31, 1\n\tscratch_store_b32 off, v17, s33 offset:4 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v17, v2\n\tv_mov_b32_e32 v18, v0\n\tscratch_load_b32 v0, off, s33 offset:4 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v15\n ; kill: def $vgpr20 killed $vgpr16 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v13\n ; kill: def $vgpr20 killed $vgpr14 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v11\n ; kill: def $vgpr20 killed $vgpr12 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v9\n ; kill: def $vgpr20 killed $vgpr10 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v7\n ; kill: def $vgpr20 killed $vgpr8 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v5\n ; kill: def $vgpr20 killed $vgpr6 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v3\n ; kill: def $vgpr20 killed $vgpr4 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr18 killed $vgpr18 def $vgpr18_vgpr19 killed $exec\n\tv_mov_b32_e32 v19, v1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s0, v0, s0\n\tv_mov_b32_e32 v1, v19\n\ts_mov_b64 s[2:3], 2\n\ts_mov_b32 s1, s3\n\tv_or_b32_e64 v0, v1, s1\n\tv_mov_b32_e32 v2, v18\n\ts_mov_b32 s1, s2\n\tv_or_b32_e64 v18, v2, s1\n ; kill: def $vgpr18 killed $vgpr18 def $vgpr18_vgpr19 killed $exec\n\tv_mov_b32_e32 v19, v0\n\tv_mov_b32_e32 v0, v19\n\tv_cndmask_b32_e64 v0, v0, v1, s0\n\tv_mov_b32_e32 v1, v18\n\tv_cndmask_b32_e64 v1, v1, v2, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v0, v2\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\tv_and_b32_e64 v0, v0, s2\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_and_b32_e64 v1, v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\tv_mov_b32_e32 v18, v0\n\ts_mov_b32 s0, 5\n\tv_lshlrev_b64 v[17:18], s0, v[17:18]\n\tv_mov_b32_e32 v0, v2\n\tv_mov_b32_e32 v19, v18\n\tv_or_b32_e64 v0, v0, v19\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v17\n\tv_or_b32_e64 v17, v1, v2\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\tv_mov_b32_e32 v18, v0\n\tv_mov_b32_e32 v1, v17\n\ts_mov_b32 s0, 32\n ; implicit-def: $vgpr29 : SGPR spill to VGPR lane\n\tv_writelane_b32 v29, s0, 0\n\tv_lshrrev_b64 v[17:18], s0, v[17:18]\n\tv_mov_b32_e32 v2, v17\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v29, 0\n\tscratch_store_b32 off, v1, s33 ; 4-byte Folded Spill\n ; kill: def $vgpr1 killed $vgpr3 killed $exec\n\tscratch_load_b32 v3, off, s33 ; 4-byte Folded Reload\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v1, s1\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v3\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v28, 0\n\tv_readlane_b32 s31, v28, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v28, off, s33 offset:8 ; 4-byte Folded Reload\n\tscratch_load_b32 v29, off, s33 offset:12 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xffffffe0\n\ts_mov_b32 s33, s19\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end7:\n\t.size\t__ockl_fprintf_append_args, .Lfunc_end7-__ockl_fprintf_append_args\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 452\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 432\n; MemoryBound: 0\n\t.text\n\t.hidden\t__assert_fail ; -- Begin function __assert_fail\n\t.weak\t__assert_fail\n\t.p2align\t2\n\t.type\t__assert_fail,@function\n__assert_fail: ; @__assert_fail\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s27, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v35, s33 offset:176 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v36, s33 offset:180 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v37, s33 offset:184 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xc0\n\tv_writelane_b32 v35, s30, 0\n\tv_writelane_b32 v35, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:168 ; 4-byte Folded Spill\n ; implicit-def: $vgpr37 : SGPR spill to VGPR lane\n\tv_writelane_b32 v37, s6, 0\n\tv_writelane_b32 v37, s7, 1\n\tscratch_store_b32 off, v5, s33 offset:164 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v3, s33 offset:160 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v5, v2\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v7, v0\n\tscratch_load_b32 v0, off, s33 offset:160 ; 4-byte Folded Reload\n\tv_writelane_b32 v37, s15, 2\n\tv_writelane_b32 v37, s14, 3\n\tv_writelane_b32 v37, s13, 4\n\tv_writelane_b32 v37, s12, 5\n\tv_writelane_b32 v37, s10, 6\n\tv_writelane_b32 v37, s11, 7\n\tv_writelane_b32 v37, s8, 8\n\tv_writelane_b32 v37, s9, 9\n\tv_writelane_b32 v37, s4, 10\n\tv_writelane_b32 v37, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v6, v0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b64 s[0:1], src_private_base\n\ts_mov_b32 s2, 32\n\ts_lshr_b64 s[0:1], s[0:1], s2\n\ts_mov_b32 s24, s0\n\tv_writelane_b32 v37, s24, 12\n\ts_mov_b32 s20, s33\n ; kill: def $sgpr20 killed $sgpr20 def $sgpr20_sgpr21\n\ts_mov_b32 s21, s24\n\ts_mov_b64 s[0:1], s[20:21]\n\tv_writelane_b32 v37, s0, 13\n\tv_writelane_b32 v37, s1, 14\n\ts_add_i32 s0, s33, 8\n\ts_mov_b32 s18, s0\n ; kill: def $sgpr18 killed $sgpr18 def $sgpr18_sgpr19\n\ts_mov_b32 s19, s24\n\ts_mov_b64 s[0:1], s[18:19]\n\tv_writelane_b32 v37, s0, 15\n\tv_writelane_b32 v37, s1, 16\n\ts_add_i32 s0, s33, 16\n\ts_mov_b32 s2, s0\n ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3\n\ts_mov_b32 s3, s24\n\ts_mov_b64 s[0:1], s[2:3]\n\tv_writelane_b32 v37, s0, 17\n\tv_writelane_b32 v37, s1, 18\n\ts_add_i32 s1, s33, 24\n\ts_mov_b32 s0, s1\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s24\n\ts_mov_b64 s[16:17], s[0:1]\n\tv_writelane_b32 v37, s16, 19\n\tv_writelane_b32 v37, s17, 20\n\ts_add_i32 s17, s33, 32\n\ts_mov_b32 s16, s17\n ; kill: def $sgpr16 killed $sgpr16 def $sgpr16_sgpr17\n\ts_mov_b32 s17, s24\n\tv_writelane_b32 v37, s16, 21\n\tv_writelane_b32 v37, s17, 22\n\ts_mov_b64 s[22:23], s[16:17]\n\tv_writelane_b32 v37, s22, 23\n\tv_writelane_b32 v37, s23, 24\n\ts_add_i32 s23, s33, 0x50\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v37, s22, 25\n\tv_writelane_b32 v37, s23, 26\n\tv_writelane_b32 v37, s22, 27\n\tv_writelane_b32 v37, s23, 28\n\ts_add_i32 s23, s33, 0x58\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v37, s22, 29\n\tv_writelane_b32 v37, s23, 30\n ; implicit-def: $vgpr36 : SGPR spill to VGPR lane\n\tv_writelane_b32 v37, s22, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:148 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_writelane_b32 v36, s23, 0\n\ts_add_i32 s23, s33, 0x60\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 1\n\tv_writelane_b32 v36, s23, 2\n\ts_add_i32 s23, s33, 0x68\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 3\n\tv_writelane_b32 v36, s23, 4\n\ts_add_i32 s23, s33, 0x70\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 5\n\tv_writelane_b32 v36, s23, 6\n\ts_add_i32 s23, s33, 0x78\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 7\n\tv_writelane_b32 v36, s23, 8\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_mov_b32_e32 v0, s20\n\tv_mov_b32_e32 v1, s21\n\tflat_store_b64 v[0:1], v[7:8]\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tflat_store_b64 v[0:1], v[5:6]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b32 v[0:1], v4\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, s33 offset:156 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+35\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+43\n\tglobal_load_b128 v[0:3], v0, s[0:1]\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:128\n\tscratch_load_b64 v[0:1], off, s33 offset:136\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_d16_hi_b8 v[3:4], v2 offset:45\n\ts_mov_b32 s1, 24\n\tv_lshrrev_b32_e64 v5, s1, v2\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v5 offset:46\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v2 offset:43\n\ts_mov_b32 s0, 8\n\tv_lshrrev_b32_e64 v4, s0, v2\n\tv_mov_b32_e32 v2, s16\n\tv_mov_b32_e32 v3, s17\n\tflat_store_b8 v[2:3], v4 offset:44\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_d16_hi_b8 v[1:2], v0 offset:41\n\tv_lshrrev_b32_e64 v3, s1, v0\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v3 offset:42\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v0 offset:39\n\tv_lshrrev_b32_e64 v2, s0, v0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b8 v[0:1], v2 offset:40\n\tscratch_load_b64 v[0:1], off, s33 offset:128\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_d16_hi_b8 v[3:4], v2 offset:37\n\tv_lshrrev_b32_e64 v5, s1, v2\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v5 offset:38\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v2 offset:35\n\tv_lshrrev_b32_e64 v4, s0, v2\n\tv_mov_b32_e32 v2, s16\n\tv_mov_b32_e32 v3, s17\n\tflat_store_b8 v[2:3], v4 offset:36\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_d16_hi_b8 v[1:2], v0 offset:33\n\tv_lshrrev_b32_e64 v3, s1, v0\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v3 offset:34\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v0 offset:31\n\tv_lshrrev_b32_e64 v2, s0, v0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b8 v[0:1], v2 offset:32\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+20\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+28\n\ts_load_b128 s[0:3], s[0:1], 0x0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v5, s3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b128 v[0:1], v[2:5] offset:16\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+4\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+12\n\ts_load_b128 s[0:3], s[0:1], 0x0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v5, s3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b128 v[0:1], v[2:5]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_stderr_begin@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_stderr_begin@rel32@hi+12\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v2, off, s33 offset:156 ; 4-byte Folded Reload\n\tv_readlane_b32 s2, v37, 25\n\tv_readlane_b32 s3, v37, 26\n\tv_readlane_b32 s0, v37, 29\n\tv_readlane_b32 s1, v37, 30\n\tv_mov_b32_e32 v3, v0\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b64 v[0:1], v[3:4]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0)\n\tflat_store_b32 v[0:1], v2\n; %bb.1:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 23\n\tv_readlane_b32 s1, v36, 24\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s3, v37, 2\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 9\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_2: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s3, v37, 2\n\tv_readlane_b32 s0, v37, 10\n\tv_readlane_b32 s1, v37, 9\n\tv_writelane_b32 v37, s1, 11\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 12\n\tv_writelane_b32 v37, s0, 13\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 14\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_4\n; %bb.3: ; in Loop: Header=BB8_2 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 12\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 13\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_4: ; in Loop: Header=BB8_2 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 14\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 11\n\tv_readlane_b32 s1, v37, 13\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 10\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 9\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 15\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_2\n; %bb.5:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.6:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 23\n\tv_readlane_b32 s3, v36, 24\n\tv_readlane_b32 s4, v37, 1\n\tv_readlane_b32 s5, v37, 2\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, s2\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.7:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 23\n\tv_readlane_b32 s1, v37, 24\n\tv_readlane_b32 s2, v37, 31\n\tv_readlane_b32 s3, v36, 0\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v5, v4\n\tv_mov_b32_e32 v6, v0\n\ts_mov_b32 s3, 32\n\ts_lshr_b64 s[16:17], s[0:1], s3\n\ts_mov_b32 s2, s16\n\tv_lshrrev_b64 v[0:1], s3, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[5:6], s3, v[5:6]\n ; kill: def $vgpr5 killed $vgpr5 killed $vgpr5_vgpr6 killed $exec\n\ts_mov_b32 s3, s0\n\tv_mov_b32_e32 v0, v2\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v2, s3\n\tv_mov_b32_e32 v3, s2\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.8:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 3\n\tv_readlane_b32 s1, v37, 4\n\tv_readlane_b32 s2, v36, 15\n\tv_readlane_b32 s3, v36, 16\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 16\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_9: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 3\n\tv_readlane_b32 s3, v37, 4\n\tv_readlane_b32 s0, v37, 17\n\tv_readlane_b32 s1, v37, 16\n\tv_writelane_b32 v37, s1, 18\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 19\n\tv_writelane_b32 v37, s0, 20\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 21\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_11\n; %bb.10: ; in Loop: Header=BB8_9 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 19\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 20\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_11: ; in Loop: Header=BB8_9 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 18\n\tv_readlane_b32 s1, v37, 20\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 17\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 16\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 22\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_9\n; %bb.12:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.13:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 15\n\tv_readlane_b32 s3, v36, 16\n\tv_readlane_b32 s4, v37, 3\n\tv_readlane_b32 s5, v37, 4\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.14:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 15\n\tv_readlane_b32 s3, v37, 16\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_writelane_b32 v36, s0, 23\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\tscratch_store_b32 off, v6, s33 offset:172 ; 4-byte Folded Spill\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tscratch_load_b32 v17, off, s33 offset:172 ; 4-byte Folded Reload\n\tv_readlane_b32 s2, v37, 17\n\tv_readlane_b32 s3, v37, 18\n\tv_readlane_b32 s0, v36, 23\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v3, v[0:1]\n\ts_waitcnt vmcnt(1) lgkmcnt(1)\n\tv_lshrrev_b64 v[0:1], s0, v[4:5]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v4\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_args@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_args@rel32@hi+12\n\tv_mov_b32_e32 v2, 1\n\tv_mov_b32_e32 v4, v17\n\tv_mov_b32_e32 v5, v17\n\tv_mov_b32_e32 v6, v17\n\tv_mov_b32_e32 v7, v17\n\tv_mov_b32_e32 v8, v17\n\tv_mov_b32_e32 v9, v17\n\tv_mov_b32_e32 v10, v17\n\tv_mov_b32_e32 v11, v17\n\tv_mov_b32_e32 v12, v17\n\tv_mov_b32_e32 v13, v17\n\tv_mov_b32_e32 v14, v17\n\tv_mov_b32_e32 v15, v17\n\tv_mov_b32_e32 v16, v17\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.15:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 5\n\tv_readlane_b32 s1, v37, 6\n\tv_readlane_b32 s2, v36, 19\n\tv_readlane_b32 s3, v36, 20\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 24\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_16: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 5\n\tv_readlane_b32 s3, v37, 6\n\tv_readlane_b32 s0, v37, 25\n\tv_readlane_b32 s1, v37, 24\n\tv_writelane_b32 v37, s1, 26\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 27\n\tv_writelane_b32 v37, s0, 28\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 29\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_18\n; %bb.17: ; in Loop: Header=BB8_16 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 27\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 28\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_18: ; in Loop: Header=BB8_16 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 26\n\tv_readlane_b32 s1, v37, 28\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 25\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 24\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 30\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_16\n; %bb.19:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 30\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.20:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 19\n\tv_readlane_b32 s3, v36, 20\n\tv_readlane_b32 s4, v37, 5\n\tv_readlane_b32 s5, v37, 6\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.21:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 19\n\tv_readlane_b32 s3, v37, 20\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.22:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 7\n\tv_readlane_b32 s1, v37, 8\n\tv_readlane_b32 s2, v36, 13\n\tv_readlane_b32 s3, v36, 14\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_23: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v36, 7\n\tv_readlane_b32 s3, v36, 8\n ; implicit-def: $vgpr37 : SGPR spill to VGPR lane\n\tv_readlane_b32 s0, v37, 0\n\tv_readlane_b32 s1, v36, 31\n\tv_writelane_b32 v37, s1, 1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 2\n\tv_writelane_b32 v37, s0, 3\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 4\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_25\n; %bb.24: ; in Loop: Header=BB8_23 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 2\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 3\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_25: ; in Loop: Header=BB8_23 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s1, v37, 3\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 0\n\ts_mov_b32 s1, s0\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v36, s1, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 5\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_23\n; %bb.26:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 5\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.27:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 13\n\tv_readlane_b32 s3, v36, 14\n\tv_readlane_b32 s4, v37, 7\n\tv_readlane_b32 s5, v37, 8\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.28:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 13\n\tv_readlane_b32 s3, v37, 14\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 1\n\ts_swappc_b64 s[30:31], s[0:1]\n\ts_cbranch_execnz .LBB8_30\n; %bb.29:\n\tv_readlane_b32 s30, v35, 0\n\tv_readlane_b32 s31, v35, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v35, off, s33 offset:176 ; 4-byte Folded Reload\n\tscratch_load_b32 v36, off, s33 offset:180 ; 4-byte Folded Reload\n\tscratch_load_b32 v37, off, s33 offset:184 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xffffff40\n\ts_mov_b32 s33, s27\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.LBB8_30:\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB8_31: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB8_31\n.Lfunc_end8:\n\t.size\t__assert_fail, .Lfunc_end8-__assert_fail\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 6148\n; NumSgprs: 36\n; NumVgprs: 38\n; ScratchSize: 1312\n; MemoryBound: 0\n\t.text\n\t.hidden\t__assertfail ; -- Begin function __assertfail\n\t.weak\t__assertfail\n\t.p2align\t2\n\t.type\t__assertfail,@function\n__assertfail: ; @__assertfail\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_cbranch_execnz .LBB9_2\n; %bb.1:\n\ts_setpc_b64 s[30:31]\n.LBB9_2:\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB9_3: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB9_3\n.Lfunc_end9:\n\t.size\t__assertfail, .Lfunc_end9-__assertfail\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 64\n; NumSgprs: 32\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_get_group_id\n\t.type\t__ockl_get_group_id,@function\n__ockl_get_group_id: ; @__ockl_get_group_id\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v2, s32 offset:32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill\n ; implicit-def: $vgpr2 : SGPR spill to VGPR lane\n\tv_writelane_b32 v2, s14, 0\n\tv_writelane_b32 v2, s13, 1\n\tv_writelane_b32 v2, s12, 2\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n; %bb.1:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v2, s1, 3\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_4\n; %bb.2:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v2, s1, 4\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_7\n; %bb.3:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 5\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_10\n\ts_branch .LBB10_9\n.LBB10_4:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 3\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 6\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB10_13\n; %bb.5:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 7\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_12\n; %bb.6:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 2\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_branch .LBB10_12\n.LBB10_7:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 4\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:12 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 8\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB10_11\n; %bb.8:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 1\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_branch .LBB10_11\n.LBB10_9:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 0\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n.LBB10_10:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 5\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:16 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_branch .LBB10_7\n.LBB10_11:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 8\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill\n\ts_branch .LBB10_4\n.LBB10_12:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 7\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:24 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n.LBB10_13:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 6\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:20 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v1, 0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v2, off, s32 offset:32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end10:\n\t.size\t__ockl_get_group_id, .Lfunc_end10-__ockl_get_group_id\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 988\n; NumSgprs: 33\n; NumVgprs: 3\n; ScratchSize: 40\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_get_local_size\n\t.type\t__ockl_get_local_size,@function\n__ockl_get_local_size: ; @__ockl_get_local_size\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v4, s32 offset:104 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill\n ; implicit-def: $vgpr4 : SGPR spill to VGPR lane\n\tv_writelane_b32 v4, s14, 0\n\tv_writelane_b32 v4, s13, 1\n\tv_writelane_b32 v4, s12, 2\n\tv_writelane_b32 v4, s8, 3\n\tv_writelane_b32 v4, s9, 4\n\tv_writelane_b32 v4, s4, 5\n\tv_writelane_b32 v4, s5, 6\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n; %bb.1:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:8 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v4, s1, 7\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_4\n; %bb.2:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:16 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v4, s1, 8\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_10\n; %bb.3:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 1\n\tv_mov_b32_e32 v0, 1\n\tv_mov_b32_e32 v1, 0\n\tscratch_store_b64 off, v[0:1], s32 offset:24 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v4, s0, 9\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_20\n\ts_branch .LBB11_15\n.LBB11_4:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 7\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:8 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:32 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v4, s0, 10\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB11_25\n; %bb.5:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 1\n\tv_mov_b32_e32 v0, 1\n\tv_mov_b32_e32 v1, 0\n\tscratch_store_b64 off, v[0:1], s32 offset:40 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v4, s0, 11\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_24\n; %bb.6:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n ; implicit-def: $sgpr2_sgpr3\n\ts_mov_b32 s4, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s4\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:48 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v4, s0, 12\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB11_9\n.LBB11_7:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 12\n\tscratch_load_b64 v[0:1], off, s32 offset:48 ; 8-byte Folded Reload\n\tv_cndmask_b32_e64 v2, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v2, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n ; kill: def $vgpr0_vgpr1 killed $vgpr0_vgpr1 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:56 ; 8-byte Folded Spill\n\ts_cbranch_vccnz .LBB11_23\n; %bb.8:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v4, 2\n\tv_readlane_b32 s2, v4, 5\n\tv_readlane_b32 s3, v4, 6\n\tv_mov_b32_e32 v0, 0\n\tglobal_load_u16 v1, v0, s[2:3] offset:4\n\ts_load_b32 s0, s[2:3], 0xc\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v0, s1, v1\n\ts_waitcnt lgkmcnt(0)\n\tv_sub_nc_u32_e64 v0, s0, v0\n ; implicit-def: $sgpr0\n\tv_min_u32_e64 v0, v0, v1\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr0_sgpr1\n\tscratch_store_b64 off, v[0:1], s32 offset:56 ; 8-byte Folded Spill\n\ts_branch .LBB11_23\n.LBB11_9:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 3\n\tv_readlane_b32 s1, v4, 4\n\tv_readlane_b32 s2, v4, 2\n\ts_load_b32 s3, s[0:1], 0x0\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_u32 s2, s3\n\ts_mov_b32 s3, 18\n\ts_mov_b32 s2, 12\n\ts_cselect_b32 s2, s2, s3\n\tv_mov_b32_e32 v0, s2\n\tglobal_load_u16 v0, v0, s[0:1]\n\ts_mov_b32 s0, 0xffff\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n ; implicit-def: $sgpr0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr2_sgpr3\n\tscratch_store_b64 off, v[0:1], s32 offset:48 ; 8-byte Folded Spill\n\tv_writelane_b32 v4, s0, 12\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB11_7\n.LBB11_10:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 8\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:16 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:64 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v4, s0, 13\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB11_22\n; %bb.11:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n ; implicit-def: $sgpr2_sgpr3\n\ts_mov_b32 s4, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s4\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:72 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v4, s0, 14\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB11_14\n.LBB11_12:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 14\n\tscratch_load_b64 v[0:1], off, s32 offset:72 ; 8-byte Folded Reload\n\tv_cndmask_b32_e64 v2, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v2, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n ; kill: def $vgpr0_vgpr1 killed $vgpr0_vgpr1 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:80 ; 8-byte Folded Spill\n\ts_cbranch_vccnz .LBB11_21\n; %bb.13:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v4, 1\n\tv_readlane_b32 s2, v4, 5\n\tv_readlane_b32 s3, v4, 6\n\tv_mov_b32_e32 v0, 0\n\tglobal_load_u16 v1, v0, s[2:3] offset:6\n\ts_load_b32 s0, s[2:3], 0x10\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v0, s1, v1\n\ts_waitcnt lgkmcnt(0)\n\tv_sub_nc_u32_e64 v0, s0, v0\n ; implicit-def: $sgpr0\n\tv_min_u32_e64 v0, v0, v1\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr0_sgpr1\n\tscratch_store_b64 off, v[0:1], s32 offset:80 ; 8-byte Folded Spill\n\ts_branch .LBB11_21\n.LBB11_14:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 3\n\tv_readlane_b32 s1, v4, 4\n\tv_readlane_b32 s2, v4, 1\n\ts_load_b32 s3, s[0:1], 0x4\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_u32 s2, s3\n\ts_mov_b32 s3, 20\n\ts_mov_b32 s2, 14\n\ts_cselect_b32 s2, s2, s3\n\tv_mov_b32_e32 v0, s2\n\tglobal_load_u16 v0, v0, s[0:1]\n\ts_mov_b32 s0, 0xffff\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n ; implicit-def: $sgpr0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr2_sgpr3\n\tscratch_store_b64 off, v[0:1], s32 offset:72 ; 8-byte Folded Spill\n\tv_writelane_b32 v4, s0, 14\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB11_12\n.LBB11_15:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n ; implicit-def: $sgpr2_sgpr3\n\ts_mov_b32 s4, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s4\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:88 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v4, s0, 15\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB11_18\n.LBB11_16:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 15\n\tscratch_load_b64 v[0:1], off, s32 offset:88 ; 8-byte Folded Reload\n\tv_cndmask_b32_e64 v2, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v2, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n ; kill: def $vgpr0_vgpr1 killed $vgpr0_vgpr1 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:96 ; 8-byte Folded Spill\n\ts_cbranch_vccnz .LBB11_19\n; %bb.17:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v4, 0\n\tv_readlane_b32 s2, v4, 5\n\tv_readlane_b32 s3, v4, 6\n\tv_mov_b32_e32 v0, 0\n\tglobal_load_u16 v1, v0, s[2:3] offset:8\n\ts_load_b32 s0, s[2:3], 0x14\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v0, s1, v1\n\ts_waitcnt lgkmcnt(0)\n\tv_sub_nc_u32_e64 v0, s0, v0\n ; implicit-def: $sgpr0\n\tv_min_u32_e64 v0, v0, v1\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr0_sgpr1\n\tscratch_store_b64 off, v[0:1], s32 offset:96 ; 8-byte Folded Spill\n\ts_branch .LBB11_19\n.LBB11_18:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 3\n\tv_readlane_b32 s1, v4, 4\n\tv_readlane_b32 s2, v4, 0\n\ts_load_b32 s3, s[0:1], 0x8\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_u32 s2, s3\n\ts_mov_b32 s3, 22\n\ts_mov_b32 s2, 16\n\ts_cselect_b32 s2, s2, s3\n\tv_mov_b32_e32 v0, s2\n\tglobal_load_u16 v0, v0, s[0:1]\n\ts_mov_b32 s0, 0xffff\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n ; implicit-def: $sgpr0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr2_sgpr3\n\tscratch_store_b64 off, v[0:1], s32 offset:88 ; 8-byte Folded Spill\n\tv_writelane_b32 v4, s0, 15\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB11_16\n.LBB11_19:\n\tscratch_load_b64 v[0:1], off, s32 offset:96 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:24 ; 8-byte Folded Spill\n.LBB11_20:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 9\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:24 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:16 ; 8-byte Folded Spill\n\ts_branch .LBB11_10\n.LBB11_21:\n\tscratch_load_b64 v[0:1], off, s32 offset:80 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:64 ; 8-byte Folded Spill\n.LBB11_22:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 13\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:64 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:8 ; 8-byte Folded Spill\n\ts_branch .LBB11_4\n.LBB11_23:\n\tscratch_load_b64 v[0:1], off, s32 offset:56 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:40 ; 8-byte Folded Spill\n.LBB11_24:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 11\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:40 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:32 ; 8-byte Folded Spill\n.LBB11_25:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 10\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[2:3], off, s32 offset:32 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 32\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[0:1], s0, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v2\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v4, off, s32 offset:104 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end11:\n\t.size\t__ockl_get_local_size, .Lfunc_end11-__ockl_get_local_size\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 2384\n; NumSgprs: 35\n; NumVgprs: 5\n; ScratchSize: 112\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_get_local_id\n\t.type\t__ockl_get_local_id,@function\n__ockl_get_local_id: ; @__ockl_get_local_id\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v2, s32 offset:36 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v31, s32 offset:8 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill\n; %bb.1:\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n ; implicit-def: $vgpr2 : SGPR spill to VGPR lane\n\tv_writelane_b32 v2, s1, 0\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_4\n; %bb.2:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v2, s1, 1\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_7\n; %bb.3:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 2\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_10\n\ts_branch .LBB12_9\n.LBB12_4:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 0\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:12 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 3\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB12_13\n; %bb.5:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 4\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_12\n; %bb.6:\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0x3ff\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_branch .LBB12_12\n.LBB12_7:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 1\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:16 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:32 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 5\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB12_11\n; %bb.8:\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_bfe_u32 v0, v0, 10, 10\n\tscratch_store_b32 off, v0, s32 offset:32 ; 4-byte Folded Spill\n\ts_branch .LBB12_11\n.LBB12_9:\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_bfe_u32 v0, v0, 20, 10\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n.LBB12_10:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 2\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:20 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_branch .LBB12_7\n.LBB12_11:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 5\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:32 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_branch .LBB12_4\n.LBB12_12:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n.LBB12_13:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 3\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:24 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v1, 0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v2, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end12:\n\t.size\t__ockl_get_local_id, .Lfunc_end12-__ockl_get_local_id\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 912\n; NumSgprs: 33\n; NumVgprs: 32\n; ScratchSize: 44\n; MemoryBound: 0\n\t.section\t.text._Z3sumIfEvPT_S1_S1_i,\"axG\",@progbits,_Z3sumIfEvPT_S1_S1_i,comdat\n\t.protected\t_Z3sumIfEvPT_S1_S1_i ; -- Begin function _Z3sumIfEvPT_S1_S1_i\n\t.globl\t_Z3sumIfEvPT_S1_S1_i\n\t.p2align\t8\n\t.type\t_Z3sumIfEvPT_S1_S1_i,@function\n_Z3sumIfEvPT_S1_S1_i: ; @_Z3sumIfEvPT_S1_S1_i\n; %bb.0:\n\ts_mov_b32 s32, 0x70\n ; implicit-def: $vgpr9 : SGPR spill to VGPR lane\n\tv_writelane_b32 v9, s15, 0\n\ts_mov_b32 s6, s14\n\tv_readlane_b32 s14, v9, 0\n\tv_writelane_b32 v9, s6, 1\n\ts_mov_b32 s12, s13\n\tv_readlane_b32 s13, v9, 1\n\tv_writelane_b32 v9, s12, 2\n\ts_mov_b64 s[10:11], s[4:5]\n\tv_writelane_b32 v9, s10, 3\n\tv_writelane_b32 v9, s11, 4\n\tv_writelane_b32 v9, s2, 5\n\tv_writelane_b32 v9, s3, 6\n\ts_mov_b64 s[4:5], s[0:1]\n\tv_readlane_b32 s0, v9, 5\n\tv_readlane_b32 s1, v9, 6\n\tv_writelane_b32 v9, s4, 7\n\tv_writelane_b32 v9, s5, 8\n\tv_mov_b32_e32 v31, v0\n\tscratch_store_b32 off, v31, off offset:104 ; 4-byte Folded Spill\n\ts_load_b64 s[30:31], s[0:1], 0x0\n\ts_load_b64 s[26:27], s[0:1], 0x8\n\ts_load_b64 s[22:23], s[0:1], 0x10\n\ts_load_b32 s2, s[0:1], 0x18\n\ts_mov_b64 s[6:7], src_private_base\n\ts_mov_b32 s3, 32\n\ts_lshr_b64 s[6:7], s[6:7], s3\n\ts_mov_b32 s3, s6\n\tv_writelane_b32 v9, s3, 9\n\ts_mov_b32 s28, 32\n ; kill: def $sgpr28 killed $sgpr28 def $sgpr28_sgpr29\n\ts_mov_b32 s29, s3\n\ts_mov_b32 s24, 40\n ; kill: def $sgpr24 killed $sgpr24 def $sgpr24_sgpr25\n\ts_mov_b32 s25, s3\n\ts_mov_b32 s20, 48\n ; kill: def $sgpr20 killed $sgpr20 def $sgpr20_sgpr21\n\ts_mov_b32 s21, s3\n\ts_mov_b32 s18, 56\n ; kill: def $sgpr18 killed $sgpr18 def $sgpr18_sgpr19\n\ts_mov_b32 s19, s3\n\ts_mov_b64 s[6:7], s[18:19]\n\tv_writelane_b32 v9, s6, 10\n\tv_writelane_b32 v9, s7, 11\n\ts_mov_b32 s16, 64\n ; kill: def $sgpr16 killed $sgpr16 def $sgpr16_sgpr17\n\ts_mov_b32 s17, s3\n\ts_mov_b64 s[6:7], s[16:17]\n\tv_writelane_b32 v9, s6, 12\n\tv_writelane_b32 v9, s7, 13\n\ts_mov_b32 s8, 0x48\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s3\n\ts_mov_b64 s[6:7], s[8:9]\n\tv_writelane_b32 v9, s6, 14\n\tv_writelane_b32 v9, s7, 15\n\ts_mov_b32 s6, 0x50\n ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7\n\ts_mov_b32 s7, s3\n\tv_writelane_b32 v9, s6, 16\n\tv_writelane_b32 v9, s7, 17\n\ts_mov_b32 s34, 0x54\n ; kill: def $sgpr34 killed $sgpr34 def $sgpr34_sgpr35\n\ts_mov_b32 s35, s3\n\tv_writelane_b32 v9, s34, 18\n\tv_writelane_b32 v9, s35, 19\n\tv_writelane_b32 v9, s34, 20\n\tv_writelane_b32 v9, s35, 21\n\tv_mov_b32_e32 v0, s28\n\tv_mov_b32_e32 v1, s29\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v2, s30\n\tv_mov_b32_e32 v3, s31\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s28\n\tv_mov_b32_e32 v1, s29\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s24\n\tv_mov_b32_e32 v1, s25\n\tv_mov_b32_e32 v2, s26\n\tv_mov_b32_e32 v3, s27\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s24\n\tv_mov_b32_e32 v1, s25\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s20\n\tv_mov_b32_e32 v1, s21\n\tv_mov_b32_e32 v2, s22\n\tv_mov_b32_e32 v3, s23\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s20\n\tv_mov_b32_e32 v1, s21\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\ts_waitcnt vmcnt(2) lgkmcnt(4)\n\tflat_store_b64 v[0:1], v[6:7]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\ts_waitcnt vmcnt(1) lgkmcnt(3)\n\tflat_store_b64 v[0:1], v[4:5]\n\tv_mov_b32_e32 v0, s8\n\tv_mov_b32_e32 v1, s9\n\ts_waitcnt vmcnt(0) lgkmcnt(2)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tv_mov_b32_e32 v2, s2\n\tflat_store_b32 v[0:1], v2\n\ts_mov_b64 s[6:7], 32\n\ts_mov_b32 s2, s0\n\ts_mov_b32 s0, s1\n\ts_mov_b32 s3, s6\n\ts_mov_b32 s1, s7\n\ts_add_u32 s8, s2, s3\n\ts_addc_u32 s0, s0, s1\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s0\n\tv_writelane_b32 v9, s8, 22\n\tv_writelane_b32 v9, s9, 23\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_group_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_group_id@rel32@hi+12\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, off offset:100 ; 4-byte Folded Spill\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:104 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v9, 0\n\tv_readlane_b32 s13, v9, 1\n\tv_readlane_b32 s12, v9, 2\n\tv_readlane_b32 s10, v9, 3\n\tv_readlane_b32 s11, v9, 4\n\tv_readlane_b32 s8, v9, 22\n\tv_readlane_b32 s9, v9, 23\n\tv_readlane_b32 s4, v9, 7\n\tv_readlane_b32 s5, v9, 8\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:100 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:108 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:108 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v1, off offset:92 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_size@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_size@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:104 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v9, 0\n\tv_readlane_b32 s13, v9, 1\n\tv_readlane_b32 s12, v9, 2\n\tv_readlane_b32 s10, v9, 3\n\tv_readlane_b32 s11, v9, 4\n\tv_readlane_b32 s4, v9, 7\n\tv_readlane_b32 s5, v9, 8\n\tv_readlane_b32 s8, v9, 22\n\tv_readlane_b32 s9, v9, 23\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:100 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:96 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:96 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v3, v1\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_id@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v2, off, off offset:92 ; 4-byte Folded Reload\n\tv_readlane_b32 s2, v9, 18\n\tv_readlane_b32 s3, v9, 19\n\tv_readlane_b32 s0, v9, 16\n\tv_readlane_b32 s1, v9, 17\n\tv_mov_b32_e32 v4, v1\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_mov_b32_e32 v4, v0\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr5\n ; implicit-def: $sgpr5\n\tv_mov_b32_e32 v0, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[0:1], s4, v2, v3, v[4:5]\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v2, s1\n\tv_mov_b32_e32 v1, s0\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_le_i32_e64 s1, v0, v1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v9, s0, 24\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v9, off offset:88 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB13_2\n; %bb.1:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v9, off, off offset:88 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v9, 14\n\tv_readlane_b32 s1, v9, 15\n\tv_readlane_b32 s2, v9, 12\n\tv_readlane_b32 s3, v9, 13\n\tv_readlane_b32 s4, v9, 20\n\tv_readlane_b32 s5, v9, 21\n\tv_readlane_b32 s6, v9, 10\n\tv_readlane_b32 s7, v9, 11\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v3, s4\n\tv_mov_b32_e32 v4, s5\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\ts_mov_b32 s4, 2\n\tv_lshlrev_b64 v[5:6], s4, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v5\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v6\n\tv_add_co_u32 v0, s4, v0, v3\n\tv_add_co_ci_u32_e64 v2, s4, v1, v2, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b64 v[2:3], v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v2, v3\n\tv_mov_b32_e32 v3, v6\n\tv_add_co_u32 v1, s2, v1, v4\n\tv_add_co_ci_u32_e64 v3, s2, v2, v3, s2\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_f32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b64 v[7:8], v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v3, v6\n\tv_add_co_u32 v0, s0, v0, v4\n\tv_add_co_ci_u32_e64 v3, s0, v1, v3, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_store_b32 v[0:1], v2\n.LBB13_2:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v9, off, off offset:88 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v9, 24\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z3sumIfEvPT_S1_S1_i\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 224\n\t\t.amdhsa_kernarg_size 288\n\t\t.amdhsa_user_sgpr_count 13\n\t\t.amdhsa_user_sgpr_dispatch_ptr 1\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 1\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 1\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 1\n\t\t.amdhsa_system_sgpr_workgroup_id_z 1\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 2\n\t\t.amdhsa_next_free_vgpr 32\n\t\t.amdhsa_next_free_sgpr 36\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.section\t.text._Z3sumIfEvPT_S1_S1_i,\"axG\",@progbits,_Z3sumIfEvPT_S1_S1_i,comdat\n.Lfunc_end13:\n\t.size\t_Z3sumIfEvPT_S1_S1_i, .Lfunc_end13-_Z3sumIfEvPT_S1_S1_i\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 1508\n; NumSgprs: 38\n; NumVgprs: 32\n; ScratchSize: 224\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 4\n; VGPRBlocks: 3\n; NumSGPRsForWavesPerEU: 38\n; NumVGPRsForWavesPerEU: 32\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1\n; COMPUTE_PGM_RSRC2:USER_SGPR: 13\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__const.__assert_fail.fmt,@object ; @__const.__assert_fail.fmt\n\t.section\t.rodata.str1.16,\"aMS\",@progbits,1\n\t.p2align\t4, 0x0\n__const.__assert_fail.fmt:\n\t.asciz\t\"%s:%u: %s: Device-side assertion `%s' failed.\\n\"\n\t.size\t__const.__assert_fail.fmt, 47\n\n\t.protected\tblockIdx\n\t.protected\tblockDim\n\t.protected\tthreadIdx\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.hidden\t__oclc_ABI_version ; @__oclc_ABI_version\n\t.type\t__oclc_ABI_version,@object\n\t.section\t.rodata,\"a\",@progbits\n\t.weak\t__oclc_ABI_version\n\t.p2align\t2, 0x0\n__oclc_ABI_version:\n\t.long\t500 ; 0x1f4\n\t.size\t__oclc_ABI_version, 4\n\n\t.weak\tblockIdx\n\t.weak\tblockDim\n\t.weak\tthreadIdx\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 16\n .size: 8\n .value_kind: global_buffer\n - .offset: 24\n .size: 4\n .value_kind: by_value\n - .offset: 32\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 36\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 40\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 44\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 46\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 48\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 50\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 52\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 54\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 72\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 80\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 88\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 96\n .size: 2\n .value_kind: hidden_grid_dims\n - .offset: 112\n .size: 8\n .value_kind: hidden_hostcall_buffer\n - .offset: 120\n .size: 8\n .value_kind: hidden_multigrid_sync_arg\n - .offset: 128\n .size: 8\n .value_kind: hidden_heap_v1\n - .offset: 136\n .size: 8\n .value_kind: hidden_default_queue\n - .offset: 232\n .size: 8\n .value_kind: hidden_queue_ptr\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 288\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z3sumIfEvPT_S1_S1_i\n .private_segment_fixed_size: 224\n .sgpr_count: 38\n .sgpr_spill_count: 25\n .symbol: _Z3sumIfEvPT_S1_S1_i.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 32\n .vgpr_spill_count: 6\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162590,"cells":{"id":{"kind":"string","value":"4e612d498e2ec06b69d5fad0904615218f27a03e_O0"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z9rsaKernelPyi --------------------------\n .section .text._Z9rsaKernelPyi,\"ax\",@progbits\n .sectionflags @\"SHF_BARRIERS=1\"\n .sectioninfo @\"SHI_REGISTERS=30\"\n .align 128\n\n\n\n\n .global _Z9rsaKernelPyi\n .type _Z9rsaKernelPyi,@function\n .size _Z9rsaKernelPyi,(.L_x_14 - _Z9rsaKernelPyi)\n .other _Z9rsaKernelPyi,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z9rsaKernelPyi:\n.text._Z9rsaKernelPyi:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ MOV R20, c[0x0][0x118] ;\n /*0020*/ MOV R21, c[0x0][0x11c] ;\n /*0030*/ MOV R2, RZ ;\n /*0040*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0050*/ MOV R5, R2 ;\n /*0060*/ MOV R6, R3 ;\n /*0070*/ MOV R5, R5 ;\n /*0080*/ MOV R6, R6 ;\n /*0090*/ MOV R0, 0x8 ;\n /*00a0*/ LDC R0, c[0x0][R0+0x160] ;\n /*00b0*/ MOV R0, R0 ;\n /*00c0*/ S2R R2, SR_CTAID.X ;\n /*00d0*/ MOV R2, R2 ;\n /*00e0*/ MOV R3, c[0x0][0x0] ;\n /*00f0*/ S2R R4, SR_TID.X ;\n /*0100*/ MOV R4, R4 ;\n /*0110*/ IMAD R2, R2, R3, R4 ;\n /*0120*/ ISETP.GE.AND P0, PT, R2, R0, PT ;\n /*0130*/ MOV R0, R5 ;\n /*0140*/ MOV R5, R6 ;\n /*0150*/ MOV R4, R4 ;\n /*0160*/ MOV R2, R2 ;\n /*0170*/ @P0 BRA `(.L_x_0) ;\n /*0180*/ MOV R0, R0 ;\n /*0190*/ MOV R5, R5 ;\n /*01a0*/ IMAD.WIDE R2, R2, 0x8, RZ ;\n /*01b0*/ MOV R6, R2 ;\n /*01c0*/ MOV R7, R3 ;\n /*01d0*/ IADD3 R6, P0, R0, R6, RZ ;\n /*01e0*/ IADD3.X R7, R5, R7, RZ, P0, !PT ;\n /*01f0*/ MOV R2, R6 ;\n /*0200*/ MOV R3, R7 ;\n /*0210*/ MOV R2, R2 ;\n /*0220*/ MOV R3, R3 ;\n /*0230*/ R2UR UR4, R20 ;\n /*0240*/ R2UR UR5, R21 ;\n /*0250*/ LDG.E.64 R2, [R2.64] ;\n /*0260*/ SHF.L.U32 R4, R4, 0x3, RZ ;\n /*0270*/ MOV R0, RZ ;\n /*0280*/ IADD3 R5, R0, R4, RZ ;\n /*0290*/ MOV R0, R5 ;\n /*02a0*/ STS.64 [R0], R2 ;\n /*02b0*/ MOV R0, R6 ;\n /*02c0*/ MOV R4, R7 ;\n /*02d0*/ MOV R7, R5 ;\n /*02e0*/ WARPSYNC 0xffffffff ;\n /*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ;\n /*0300*/ BRA.CONV ~URZ, `(.L_x_1) ;\n /*0310*/ MOV R3, 0x330 ;\n /*0320*/ CALL.REL.NOINC `($__internal_1_$__cuda_sm70_barrier_sync_0) ;\n /*0330*/ BRA `(.L_x_2) ;\n.L_x_1:\n /*0340*/ BAR.SYNC 0x0 ;\n.L_x_2:\n /*0350*/ MOV R2, RZ ;\n /*0360*/ LDC.64 R2, c[0x3][R2] ;\n /*0370*/ MOV R5, R2 ;\n /*0380*/ MOV R6, R3 ;\n /*0390*/ MOV R5, R5 ;\n /*03a0*/ MOV R6, R6 ;\n /*03b0*/ ISETP.EQ.U32.AND P0, PT, R5, RZ, PT ;\n /*03c0*/ ISETP.EQ.AND.EX P0, PT, R6, RZ, PT, P0 ;\n /*03d0*/ MOV R2, 0x1 ;\n /*03e0*/ MOV R3, RZ ;\n /*03f0*/ MOV R5, R5 ;\n /*0400*/ MOV R6, R6 ;\n /*0410*/ MOV R2, R2 ;\n /*0420*/ MOV R3, R3 ;\n /*0430*/ MOV R2, R2 ;\n /*0440*/ MOV R3, R3 ;\n /*0450*/ BSSY B0, `(.L_x_3) ;\n /*0460*/ @P0 BRA `(.L_x_4) ;\n /*0470*/ MOV R2, R7 ;\n /*0480*/ LDS.64 R2, [R2] ;\n /*0490*/ MOV R12, 0x1 ;\n /*04a0*/ MOV R13, RZ ;\n /*04b0*/ MOV R8, 0x8 ;\n /*04c0*/ LDC.64 R8, c[0x3][R8] ;\n /*04d0*/ MOV R10, R8 ;\n /*04e0*/ MOV R11, R9 ;\n /*04f0*/ MOV R10, R10 ;\n /*0500*/ MOV R11, R11 ;\n /*0510*/ MOV R7, R10 ;\n /*0520*/ MOV R8, R2 ;\n /*0530*/ MOV R2, R3 ;\n /*0540*/ MOV R8, R8 ;\n /*0550*/ MOV R9, R2 ;\n /*0560*/ MOV R2, R12 ;\n /*0570*/ MOV R3, R13 ;\n /*0580*/ MOV R2, R2 ;\n /*0590*/ MOV R3, R3 ;\n /*05a0*/ MOV R10, R10 ;\n /*05b0*/ MOV R11, R11 ;\n /*05c0*/ MOV R7, R7 ;\n.L_x_11:\n /*05d0*/ LOP3.LUT R12, R5, 0x1, RZ, 0xc0, !PT ;\n /*05e0*/ LOP3.LUT R13, R6, RZ, RZ, 0xc0, !PT ;\n /*05f0*/ ISETP.EQ.U32.AND P0, PT, R12, 0x1, PT ;\n /*0600*/ ISETP.EQ.U32.AND.EX P0, PT, R13, RZ, PT, P0 ;\n /*0610*/ PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x0 ;\n /*0620*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x28, 0x0 ;\n /*0630*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ;\n /*0640*/ BSSY B1, `(.L_x_5) ;\n /*0650*/ @P0 BRA `(.L_x_6) ;\n /*0660*/ MOV R14, R2 ;\n /*0670*/ MOV R3, R3 ;\n /*0680*/ MOV R12, RZ ;\n /*0690*/ MOV R13, RZ ;\n /*06a0*/ MOV R12, R12 ;\n /*06b0*/ MOV R13, R13 ;\n /*06c0*/ IMAD.WIDE.U32 R12, R8, R14, R12 ;\n /*06d0*/ MOV R2, R12 ;\n /*06e0*/ MOV R15, R13 ;\n /*06f0*/ MOV R2, R2 ;\n /*0700*/ IMAD.WIDE.U32 R12, R9, R14, RZ ;\n /*0710*/ MOV R14, R12 ;\n /*0720*/ MOV R12, R13 ;\n /*0730*/ MOV R13, R12 ;\n /*0740*/ MOV R12, R14 ;\n /*0750*/ IMAD.WIDE.U32 R12, P0, R8, R3, R12 ;\n /*0760*/ MOV R14, R12 ;\n /*0770*/ MOV R12, R13 ;\n /*0780*/ IADD3 R15, P1, R14, R15, RZ ;\n /*0790*/ IADD3 R12, RZ, R12, RZ ;\n /*07a0*/ IADD3.X R13, RZ, RZ, RZ, P0, !PT ;\n /*07b0*/ MOV R12, R12 ;\n /*07c0*/ MOV R13, R13 ;\n /*07d0*/ MOV R12, R12 ;\n /*07e0*/ MOV R13, R13 ;\n /*07f0*/ IMAD.WIDE.U32.X R12, R9, R3, R12, P1 ;\n /*0800*/ MOV R3, R12 ;\n /*0810*/ MOV R12, R13 ;\n /*0820*/ LOP3.LUT R3, R2, R10, RZ, 0xfc, !PT ;\n /*0830*/ LOP3.LUT R12, R15, R11, RZ, 0xfc, !PT ;\n /*0840*/ LOP3.LUT R3, R3, RZ, RZ, 0xc0, !PT ;\n /*0850*/ LOP3.LUT R12, R12, 0xffffffff, RZ, 0xc0, !PT ;\n /*0860*/ ISETP.EQ.U32.AND P0, PT, R3, RZ, PT ;\n /*0870*/ ISETP.EQ.AND.EX P0, PT, R12, RZ, PT, P0 ;\n /*0880*/ MOV R2, R2 ;\n /*0890*/ MOV R15, R15 ;\n /*08a0*/ @P0 BRA `(.L_x_7) ;\n /*08b0*/ MOV R14, R2 ;\n /*08c0*/ MOV R15, R15 ;\n /*08d0*/ MOV R16, R10 ;\n /*08e0*/ MOV R17, R11 ;\n /*08f0*/ MOV R12, 0x910 ;\n /*0900*/ CALL.REL.NOINC `($__internal_0_$__cuda_sm20_rem_u64) ;\n /*0910*/ MOV R2, R14 ;\n /*0920*/ MOV R3, R15 ;\n /*0930*/ MOV R2, R2 ;\n /*0940*/ MOV R3, R3 ;\n /*0950*/ BRA `(.L_x_6) ;\n.L_x_7:\n /*0960*/ MOV R2, R2 ;\n /*0970*/ MOV R2, R2 ;\n /*0980*/ MOV R3, R7 ;\n /*0990*/ MOV R2, R2 ;\n /*09a0*/ MOV R3, R3 ;\n /*09b0*/ MOV R2, R2 ;\n /*09c0*/ MOV R3, R3 ;\n /*09d0*/ MOV R2, R2 ;\n /*09e0*/ MOV R3, R3 ;\n /*09f0*/ I2F.U32.RP R12, R3 ;\n /*0a00*/ MUFU.RCP R12, R12 ;\n /*0a10*/ MOV R12, R12 ;\n /*0a20*/ IADD3 R12, R12, 0xffffffe, RZ ;\n /*0a30*/ MOV R12, R12 ;\n /*0a40*/ F2I.FTZ.U32.TRUNC.NTZ R12, R12 ;\n /*0a50*/ IMAD.U32 R13, R12, R3, RZ ;\n /*0a60*/ IADD3 R13, RZ, -R13, RZ ;\n /*0a70*/ MOV R13, R13 ;\n /*0a80*/ MOV R13, R13 ;\n /*0a90*/ IMAD.HI.U32 R13, R12, R13, RZ ;\n /*0aa0*/ IADD3 R13, R12, R13, RZ ;\n /*0ab0*/ IMAD.HI.U32 R13, R13, R2, RZ ;\n /*0ac0*/ IMAD.U32 R13, R13, R3, RZ ;\n /*0ad0*/ IADD3 R13, R2, -R13, RZ ;\n /*0ae0*/ ISETP.GE.U32.AND P0, PT, R13, R3, PT ;\n /*0af0*/ IADD3 R2, R13, -R3, RZ ;\n /*0b00*/ SEL R2, R2, R13, P0 ;\n /*0b10*/ IADD3 R12, R2, -R3, RZ ;\n /*0b20*/ ISETP.GE.U32.AND P0, PT, R2, R3, PT ;\n /*0b30*/ SEL R12, R12, R2, P0 ;\n /*0b40*/ MOV R2, RZ ;\n /*0b50*/ ISETP.NE.U32.AND P0, PT, R3, R2, PT ;\n /*0b60*/ LOP3.LUT R3, RZ, R3, RZ, 0x33, !PT ;\n /*0b70*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ;\n /*0b80*/ SEL R3, R3, R12, P0 ;\n /*0b90*/ MOV R3, R3 ;\n /*0ba0*/ MOV R3, R3 ;\n /*0bb0*/ MOV R3, R3 ;\n /*0bc0*/ MOV R3, R3 ;\n /*0bd0*/ MOV R2, R3 ;\n /*0be0*/ MOV R3, RZ ;\n /*0bf0*/ MOV R2, R2 ;\n /*0c00*/ MOV R3, R3 ;\n /*0c10*/ BRA `(.L_x_6) ;\n.L_x_6:\n /*0c20*/ BSYNC B1 ;\n.L_x_5:\n /*0c30*/ MOV R12, RZ ;\n /*0c40*/ MOV R13, RZ ;\n /*0c50*/ MOV R12, R12 ;\n /*0c60*/ MOV R13, R13 ;\n /*0c70*/ IMAD.WIDE.U32 R12, R8, R8, R12 ;\n /*0c80*/ MOV R14, R12 ;\n /*0c90*/ MOV R13, R13 ;\n /*0ca0*/ MOV R12, R14 ;\n /*0cb0*/ IMAD.WIDE.U32 R14, R9, R8, RZ ;\n /*0cc0*/ MOV R16, R14 ;\n /*0cd0*/ MOV R14, R15 ;\n /*0ce0*/ MOV R15, R14 ;\n /*0cf0*/ MOV R14, R16 ;\n /*0d00*/ IMAD.WIDE.U32 R14, P0, R8, R9, R14 ;\n /*0d10*/ MOV R8, R14 ;\n /*0d20*/ MOV R14, R15 ;\n /*0d30*/ IADD3 R13, P1, R8, R13, RZ ;\n /*0d40*/ IADD3 R14, RZ, R14, RZ ;\n /*0d50*/ IADD3.X R8, RZ, RZ, RZ, P0, !PT ;\n /*0d60*/ MOV R14, R14 ;\n /*0d70*/ MOV R8, R8 ;\n /*0d80*/ MOV R14, R14 ;\n /*0d90*/ MOV R15, R8 ;\n /*0da0*/ IMAD.WIDE.U32.X R8, R9, R9, R14, P1 ;\n /*0db0*/ MOV R14, R8 ;\n /*0dc0*/ MOV R8, R9 ;\n /*0dd0*/ LOP3.LUT R8, R12, R10, RZ, 0xfc, !PT ;\n /*0de0*/ LOP3.LUT R9, R13, R11, RZ, 0xfc, !PT ;\n /*0df0*/ LOP3.LUT R8, R8, RZ, RZ, 0xc0, !PT ;\n /*0e00*/ LOP3.LUT R9, R9, 0xffffffff, RZ, 0xc0, !PT ;\n /*0e10*/ ISETP.EQ.U32.AND P0, PT, R8, RZ, PT ;\n /*0e20*/ ISETP.EQ.AND.EX P0, PT, R9, RZ, PT, P0 ;\n /*0e30*/ MOV R8, R12 ;\n /*0e40*/ MOV R15, R13 ;\n /*0e50*/ BSSY B1, `(.L_x_8) ;\n /*0e60*/ @P0 BRA `(.L_x_9) ;\n /*0e70*/ MOV R14, R8 ;\n /*0e80*/ MOV R15, R15 ;\n /*0e90*/ MOV R16, R10 ;\n /*0ea0*/ MOV R17, R11 ;\n /*0eb0*/ MOV R12, 0xed0 ;\n /*0ec0*/ CALL.REL.NOINC `($__internal_0_$__cuda_sm20_rem_u64) ;\n /*0ed0*/ MOV R8, R14 ;\n /*0ee0*/ MOV R9, R15 ;\n /*0ef0*/ MOV R12, R8 ;\n /*0f00*/ MOV R9, R9 ;\n /*0f10*/ MOV R8, R12 ;\n /*0f20*/ MOV R9, R9 ;\n /*0f30*/ BRA `(.L_x_10) ;\n.L_x_9:\n /*0f40*/ MOV R8, R8 ;\n /*0f50*/ MOV R8, R8 ;\n /*0f60*/ MOV R7, R7 ;\n /*0f70*/ MOV R8, R8 ;\n /*0f80*/ MOV R9, R7 ;\n /*0f90*/ MOV R8, R8 ;\n /*0fa0*/ MOV R9, R9 ;\n /*0fb0*/ MOV R8, R8 ;\n /*0fc0*/ MOV R9, R9 ;\n /*0fd0*/ I2F.U32.RP R12, R9 ;\n /*0fe0*/ MUFU.RCP R12, R12 ;\n /*0ff0*/ MOV R12, R12 ;\n /*1000*/ IADD3 R12, R12, 0xffffffe, RZ ;\n /*1010*/ MOV R12, R12 ;\n /*1020*/ F2I.FTZ.U32.TRUNC.NTZ R12, R12 ;\n /*1030*/ IMAD.U32 R13, R12, R9, RZ ;\n /*1040*/ IADD3 R13, RZ, -R13, RZ ;\n /*1050*/ MOV R13, R13 ;\n /*1060*/ MOV R13, R13 ;\n /*1070*/ IMAD.HI.U32 R13, R12, R13, RZ ;\n /*1080*/ IADD3 R13, R12, R13, RZ ;\n /*1090*/ IMAD.HI.U32 R13, R13, R8, RZ ;\n /*10a0*/ IMAD.U32 R13, R13, R9, RZ ;\n /*10b0*/ IADD3 R13, R8, -R13, RZ ;\n /*10c0*/ ISETP.GE.U32.AND P0, PT, R13, R9, PT ;\n /*10d0*/ IADD3 R8, R13, -R9, RZ ;\n /*10e0*/ SEL R8, R8, R13, P0 ;\n /*10f0*/ IADD3 R12, R8, -R9, RZ ;\n /*1100*/ ISETP.GE.U32.AND P0, PT, R8, R9, PT ;\n /*1110*/ SEL R12, R12, R8, P0 ;\n /*1120*/ MOV R8, RZ ;\n /*1130*/ ISETP.NE.U32.AND P0, PT, R9, R8, PT ;\n /*1140*/ LOP3.LUT R9, RZ, R9, RZ, 0x33, !PT ;\n /*1150*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ;\n /*1160*/ SEL R9, R9, R12, P0 ;\n /*1170*/ MOV R9, R9 ;\n /*1180*/ MOV R9, R9 ;\n /*1190*/ MOV R9, R9 ;\n /*11a0*/ MOV R9, R9 ;\n /*11b0*/ MOV R8, R9 ;\n /*11c0*/ MOV R9, RZ ;\n /*11d0*/ MOV R12, R8 ;\n /*11e0*/ MOV R9, R9 ;\n /*11f0*/ MOV R8, R12 ;\n /*1200*/ MOV R9, R9 ;\n.L_x_10:\n /*1210*/ BSYNC B1 ;\n.L_x_8:\n /*1220*/ SHF.R.U64 R5, R5, 0x1, R6 ;\n /*1230*/ SHF.R.U32.HI R6, RZ, 0x1, R6 ;\n /*1240*/ ISETP.NE.U32.AND P0, PT, R5, RZ, PT ;\n /*1250*/ ISETP.NE.AND.EX P0, PT, R6, RZ, PT, P0 ;\n /*1260*/ MOV R5, R5 ;\n /*1270*/ MOV R6, R6 ;\n /*1280*/ @P0 BRA `(.L_x_11) ;\n.L_x_4:\n /*1290*/ BSYNC B0 ;\n.L_x_3:\n /*12a0*/ MOV R0, R0 ;\n /*12b0*/ MOV R4, R4 ;\n /*12c0*/ MOV R5, R4 ;\n /*12d0*/ MOV R4, R0 ;\n /*12e0*/ R2UR UR4, R20 ;\n /*12f0*/ R2UR UR5, R21 ;\n /*1300*/ STG.E.64 [R4.64], R2 ;\n.L_x_0:\n /*1310*/ EXIT ;\n\n\n\n\n .weak $__internal_0_$__cuda_sm20_rem_u64\n .type $__internal_0_$__cuda_sm20_rem_u64,@function\n .size $__internal_0_$__cuda_sm20_rem_u64,($__internal_1_$__cuda_sm70_barrier_sync_0 - $__internal_0_$__cuda_sm20_rem_u64)\n$__internal_0_$__cuda_sm20_rem_u64:\n /*1320*/ MOV R14, R14 ;\n /*1330*/ MOV R15, R15 ;\n /*1340*/ MOV R16, R16 ;\n /*1350*/ MOV R17, R17 ;\n /*1360*/ MOV R13, R14 ;\n /*1370*/ MOV R14, R15 ;\n /*1380*/ MOV R13, R13 ;\n /*1390*/ MOV R14, R14 ;\n /*13a0*/ MOV R15, R16 ;\n /*13b0*/ MOV R16, R17 ;\n /*13c0*/ MOV R15, R15 ;\n /*13d0*/ MOV R16, R16 ;\n /*13e0*/ MOV R18, R15 ;\n /*13f0*/ MOV R19, R16 ;\n /*1400*/ I2F.U64.RP R18, R18 ;\n /*1410*/ MUFU.RCP R18, R18 ;\n /*1420*/ MOV R18, R18 ;\n /*1430*/ IADD3 R18, R18, 0x1ffffffe, RZ ;\n /*1440*/ MOV R18, R18 ;\n /*1450*/ MOV R18, R18 ;\n /*1460*/ MOV R18, R18 ;\n /*1470*/ F2I.U64.TRUNC R18, R18 ;\n /*1480*/ MOV R17, R18 ;\n /*1490*/ MOV R18, R19 ;\n /*14a0*/ MOV R17, R17 ;\n /*14b0*/ MOV R18, R18 ;\n /*14c0*/ MOV R17, R17 ;\n /*14d0*/ MOV R18, R18 ;\n /*14e0*/ MOV R19, R17 ;\n /*14f0*/ MOV R22, R18 ;\n /*1500*/ MOV R15, R15 ;\n /*1510*/ MOV R16, R16 ;\n /*1520*/ MOV R23, R15 ;\n /*1530*/ MOV R24, R16 ;\n /*1540*/ IMAD.U32 R25, R19, R23, RZ ;\n /*1550*/ IMAD.HI.U32 R26, R19, R23, RZ ;\n /*1560*/ IMAD.U32 R24, R19, R24, R26 ;\n /*1570*/ IMAD.U32 R22, R22, R23, R24 ;\n /*1580*/ MOV R25, R25 ;\n /*1590*/ MOV R22, R22 ;\n /*15a0*/ IADD3 R23, P0, -R25, RZ, RZ ;\n /*15b0*/ IADD3.X R22, ~R22, RZ, RZ, P0, !PT ;\n /*15c0*/ MOV R23, R23 ;\n /*15d0*/ MOV R22, R22 ;\n /*15e0*/ MOV R24, R17 ;\n /*15f0*/ MOV R19, R18 ;\n /*1600*/ MOV R24, R24 ;\n /*1610*/ MOV R19, R19 ;\n /*1620*/ MOV R23, R23 ;\n /*1630*/ MOV R22, R22 ;\n /*1640*/ MOV R23, R23 ;\n /*1650*/ MOV R22, R22 ;\n /*1660*/ MOV R17, R17 ;\n /*1670*/ MOV R18, R18 ;\n /*1680*/ MOV R17, R17 ;\n /*1690*/ MOV R18, R18 ;\n /*16a0*/ IMAD.HI.U32 R25, R24, R23, RZ ;\n /*16b0*/ IMAD.U32 R26, R24, R22, R25 ;\n /*16c0*/ IMAD R27, R24, R22, RZ ;\n /*16d0*/ IADD3 RZ, P0, R27, R25, RZ ;\n /*16e0*/ IMAD.HI.U32 R25, R24, R22, RZ ;\n /*16f0*/ IADD3.X R25, R25, R17, RZ, P0, !PT ;\n /*1700*/ IMAD.HI.U32 R24, R24, R22, RZ ;\n /*1710*/ IADD3.X RZ, P0, R24, R17, RZ, P0, !PT ;\n /*1720*/ IMAD.HI.U32 R17, R19, R22, RZ ;\n /*1730*/ IADD3.X R18, R17, R18, RZ, P0, !PT ;\n /*1740*/ IMAD R17, R19, R23, RZ ;\n /*1750*/ IADD3 RZ, P0, R17, R26, RZ ;\n /*1760*/ IMAD.HI.U32 R17, R19, R23, RZ ;\n /*1770*/ IADD3.X R17, R17, R25, RZ, P0, !PT ;\n /*1780*/ IMAD.HI.U32 R23, R19, R23, RZ ;\n /*1790*/ IADD3.X RZ, P0, R23, R25, RZ, P0, !PT ;\n /*17a0*/ IADD3.X R18, R18, RZ, RZ, P0, !PT ;\n /*17b0*/ IMAD.U32 R23, R19, R22, R17 ;\n /*17c0*/ IMAD R19, R19, R22, RZ ;\n /*17d0*/ IADD3 RZ, P0, R19, R17, RZ ;\n /*17e0*/ IADD3.X R18, R18, RZ, RZ, P0, !PT ;\n /*17f0*/ MOV R17, R23 ;\n /*1800*/ MOV R18, R18 ;\n /*1810*/ MOV R17, R17 ;\n /*1820*/ MOV R18, R18 ;\n /*1830*/ MOV R19, R17 ;\n /*1840*/ MOV R22, R18 ;\n /*1850*/ MOV R15, R15 ;\n /*1860*/ MOV R16, R16 ;\n /*1870*/ MOV R23, R15 ;\n /*1880*/ MOV R24, R16 ;\n /*1890*/ IMAD.U32 R25, R19, R23, RZ ;\n /*18a0*/ IMAD.HI.U32 R26, R19, R23, RZ ;\n /*18b0*/ IMAD.U32 R24, R19, R24, R26 ;\n /*18c0*/ IMAD.U32 R22, R22, R23, R24 ;\n /*18d0*/ MOV R25, R25 ;\n /*18e0*/ MOV R22, R22 ;\n /*18f0*/ IADD3 R23, P0, -R25, RZ, RZ ;\n /*1900*/ IADD3.X R22, ~R22, RZ, RZ, P0, !PT ;\n /*1910*/ MOV R23, R23 ;\n /*1920*/ MOV R22, R22 ;\n /*1930*/ MOV R24, R17 ;\n /*1940*/ MOV R19, R18 ;\n /*1950*/ MOV R24, R24 ;\n /*1960*/ MOV R19, R19 ;\n /*1970*/ MOV R23, R23 ;\n /*1980*/ MOV R22, R22 ;\n /*1990*/ MOV R23, R23 ;\n /*19a0*/ MOV R22, R22 ;\n /*19b0*/ MOV R17, R17 ;\n /*19c0*/ MOV R18, R18 ;\n /*19d0*/ MOV R17, R17 ;\n /*19e0*/ MOV R18, R18 ;\n /*19f0*/ IMAD.HI.U32 R25, R24, R23, RZ ;\n /*1a00*/ IMAD.U32 R26, R24, R22, R25 ;\n /*1a10*/ IMAD R27, R24, R22, RZ ;\n /*1a20*/ IADD3 RZ, P0, R27, R25, RZ ;\n /*1a30*/ IMAD.HI.U32 R25, R24, R22, RZ ;\n /*1a40*/ IADD3.X R25, R25, R17, RZ, P0, !PT ;\n /*1a50*/ IMAD.HI.U32 R24, R24, R22, RZ ;\n /*1a60*/ IADD3.X RZ, P0, R24, R17, RZ, P0, !PT ;\n /*1a70*/ IMAD.HI.U32 R17, R19, R22, RZ ;\n /*1a80*/ IADD3.X R18, R17, R18, RZ, P0, !PT ;\n /*1a90*/ IMAD R17, R19, R23, RZ ;\n /*1aa0*/ IADD3 RZ, P0, R17, R26, RZ ;\n /*1ab0*/ IMAD.HI.U32 R17, R19, R23, RZ ;\n /*1ac0*/ IADD3.X R17, R17, R25, RZ, P0, !PT ;\n /*1ad0*/ IMAD.HI.U32 R23, R19, R23, RZ ;\n /*1ae0*/ IADD3.X RZ, P0, R23, R25, RZ, P0, !PT ;\n /*1af0*/ IADD3.X R18, R18, RZ, RZ, P0, !PT ;\n /*1b00*/ IMAD.U32 R23, R19, R22, R17 ;\n /*1b10*/ IMAD R19, R19, R22, RZ ;\n /*1b20*/ IADD3 RZ, P0, R19, R17, RZ ;\n /*1b30*/ IADD3.X R18, R18, RZ, RZ, P0, !PT ;\n /*1b40*/ MOV R17, R23 ;\n /*1b50*/ MOV R18, R18 ;\n /*1b60*/ MOV R17, R17 ;\n /*1b70*/ MOV R18, R18 ;\n /*1b80*/ MOV R17, R17 ;\n /*1b90*/ MOV R18, R18 ;\n /*1ba0*/ MOV R13, R13 ;\n /*1bb0*/ MOV R14, R14 ;\n /*1bc0*/ MOV R19, R13 ;\n /*1bd0*/ MOV R22, R14 ;\n /*1be0*/ IMAD.HI.U32 R23, R17, R19, RZ ;\n /*1bf0*/ IMAD.U32 R24, R17, R22, R23 ;\n /*1c00*/ IMAD R25, R17, R22, RZ ;\n /*1c10*/ IADD3 RZ, P0, R25, R23, RZ ;\n /*1c20*/ IMAD.HI.U32 R17, R17, R22, RZ ;\n /*1c30*/ IADD3.X R17, R17, RZ, RZ, P0, !PT ;\n /*1c40*/ IMAD R23, R18, R19, RZ ;\n /*1c50*/ IADD3 RZ, P0, R23, R24, RZ ;\n /*1c60*/ IMAD.HI.U32 R23, R18, R19, RZ ;\n /*1c70*/ IADD3.X R23, R23, R17, RZ, P0, !PT ;\n /*1c80*/ IMAD.HI.U32 R19, R18, R19, RZ ;\n /*1c90*/ IADD3.X RZ, P0, R19, R17, RZ, P0, !PT ;\n /*1ca0*/ IMAD.HI.U32 R17, R18, R22, RZ ;\n /*1cb0*/ IADD3.X R17, R17, RZ, RZ, P0, !PT ;\n /*1cc0*/ IMAD.U32 R19, R18, R22, R23 ;\n /*1cd0*/ IMAD R18, R18, R22, RZ ;\n /*1ce0*/ IADD3 RZ, P0, R18, R23, RZ ;\n /*1cf0*/ IADD3.X R17, R17, RZ, RZ, P0, !PT ;\n /*1d00*/ MOV R19, R19 ;\n /*1d10*/ MOV R18, R17 ;\n /*1d20*/ MOV R17, R19 ;\n /*1d30*/ MOV R18, R18 ;\n /*1d40*/ MOV R17, R17 ;\n /*1d50*/ MOV R18, R18 ;\n /*1d60*/ MOV R15, R15 ;\n /*1d70*/ MOV R16, R16 ;\n /*1d80*/ MOV R19, R15 ;\n /*1d90*/ MOV R22, R16 ;\n /*1da0*/ IMAD.U32 R23, R17, R19, RZ ;\n /*1db0*/ IMAD.HI.U32 R24, R17, R19, RZ ;\n /*1dc0*/ IMAD.U32 R22, R17, R22, R24 ;\n /*1dd0*/ IMAD.U32 R18, R18, R19, R22 ;\n /*1de0*/ MOV R23, R23 ;\n /*1df0*/ MOV R18, R18 ;\n /*1e00*/ IADD3 R13, P0, R13, -R23, RZ ;\n /*1e10*/ IADD3.X R14, R14, ~R18, RZ, P0, !PT ;\n /*1e20*/ MOV R13, R13 ;\n /*1e30*/ MOV R14, R14 ;\n /*1e40*/ ISETP.GE.U32.AND P0, PT, R13, R15, PT ;\n /*1e50*/ ISETP.GE.U32.AND.EX P0, PT, R14, R16, PT, P0 ;\n /*1e60*/ IADD3 R17, P1, R13, -R15, RZ ;\n /*1e70*/ IADD3.X R18, R14, ~R16, RZ, P1, !PT ;\n /*1e80*/ SEL R17, R17, R13, P0 ;\n /*1e90*/ SEL R18, R18, R14, P0 ;\n /*1ea0*/ ISETP.GE.U32.AND P0, PT, R17, R15, PT ;\n /*1eb0*/ ISETP.GE.U32.AND.EX P0, PT, R18, R16, PT, P0 ;\n /*1ec0*/ IADD3 R14, P1, R17, -R15, RZ ;\n /*1ed0*/ IADD3.X R13, R18, ~R16, RZ, P1, !PT ;\n /*1ee0*/ SEL R14, R14, R17, P0 ;\n /*1ef0*/ SEL R13, R13, R18, P0 ;\n /*1f00*/ ISETP.EQ.U32.AND P0, PT, R15, RZ, PT ;\n /*1f10*/ ISETP.EQ.AND.EX P0, PT, R16, RZ, PT, P0 ;\n /*1f20*/ SEL R14, R14, 0xffffffff, !P0 ;\n /*1f30*/ SEL R15, R13, 0xffffffff, !P0 ;\n /*1f40*/ MOV R14, R14 ;\n /*1f50*/ MOV R15, R15 ;\n /*1f60*/ MOV R14, R14 ;\n /*1f70*/ MOV R15, R15 ;\n /*1f80*/ MOV R12, R12 ;\n /*1f90*/ MOV R13, 0x0 ;\n /*1fa0*/ RET.REL.NODEC R12 `(_Z9rsaKernelPyi) ;\n\n\n\n\n .weak $__internal_1_$__cuda_sm70_barrier_sync_0\n .type $__internal_1_$__cuda_sm70_barrier_sync_0,@function\n .size $__internal_1_$__cuda_sm70_barrier_sync_0,(.L_x_14 - $__internal_1_$__cuda_sm70_barrier_sync_0)\n$__internal_1_$__cuda_sm70_barrier_sync_0:\n /*1fb0*/ WARPSYNC 0xffffffff ;\n /*1fc0*/ BAR.SYNC 0x0 ;\n /*1fd0*/ MOV R2, RZ ;\n /*1fe0*/ MOV R2, R2 ;\n /*1ff0*/ MOV R2, R3 ;\n /*2000*/ MOV R3, 0x0 ;\n /*2010*/ RET.REL.NODEC R2 `(_Z9rsaKernelPyi) ;\n.L_x_12:\n /*2020*/ BRA `(.L_x_12);\n /*2030*/ NOP;\n /*2040*/ NOP;\n /*2050*/ NOP;\n /*2060*/ NOP;\n /*2070*/ NOP;\n /*2080*/ NOP;\n /*2090*/ NOP;\n /*20a0*/ NOP;\n /*20b0*/ NOP;\n /*20c0*/ NOP;\n /*20d0*/ NOP;\n /*20e0*/ NOP;\n /*20f0*/ NOP;\n.L_x_14:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.protected\t_Z9rsaKernelPyi ; -- Begin function _Z9rsaKernelPyi\n\t.globl\t_Z9rsaKernelPyi\n\t.p2align\t8\n\t.type\t_Z9rsaKernelPyi,@function\n_Z9rsaKernelPyi: ; @_Z9rsaKernelPyi\n; %bb.0:\n\ts_clause 0x1\n\ts_load_b32 s2, s[0:1], 0x1c\n\ts_load_b32 s3, s[0:1], 0x8\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s2, s2, 0xffff\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]\n\ts_mov_b32 s2, exec_lo\n\tv_cmpx_gt_i32_e64 s3, v1\n\ts_cbranch_execz .LBB0_16\n; %bb.1:\n\ts_load_b64 s[0:1], s[0:1], 0x0\n\tv_ashrrev_i32_e32 v2, 31, v1\n\tv_lshl_add_u32 v0, v0, 3, 0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[1:2], 3, v[1:2]\n\ts_waitcnt lgkmcnt(0)\n\tv_add_co_u32 v1, vcc_lo, s0, v1\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, d@rel32@lo+4\n\ts_addc_u32 s1, s1, d@rel32@hi+12\n\ts_load_b64 s[2:3], s[0:1], 0x0\n\tglobal_load_b64 v[3:4], v[1:2], off\n\ts_mov_b32 s1, 0\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_eq_u64 s[2:3], 0\n\ts_waitcnt vmcnt(0)\n\tds_store_b64 v0, v[3:4]\n\ts_waitcnt lgkmcnt(0)\n\ts_barrier\n\tbuffer_gl0_inv\n\ts_barrier\n\tbuffer_gl0_inv\n\ts_cbranch_scc1 .LBB0_14\n; %bb.2:\n\ts_getpc_b64 s[4:5]\n\ts_add_u32 s4, s4, n@rel32@lo+4\n\ts_addc_u32 s5, s5, n@rel32@hi+12\n\tds_load_b64 v[7:8], v0\n\ts_load_b64 s[4:5], s[4:5], 0x0\n\tv_mov_b32_e32 v5, 1\n\tv_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, 0\n\ts_waitcnt lgkmcnt(0)\n\ts_sub_i32 s6, 0, s4\n\ts_branch .LBB0_4\n.LBB0_3: ; in Loop: Header=BB0_4 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_cmp_gt_u64_e64 s0, s[2:3], 1\n\ts_lshr_b64 s[2:3], s[2:3], 1\n\ts_delay_alu instid0(VALU_DEP_1)\n\ts_and_b32 vcc_lo, exec_lo, s0\n\ts_cbranch_vccz .LBB0_15\n.LBB0_4: ; =>This Inner Loop Header: Depth=1\n\ts_and_b32 s0, s2, 1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_cmp_eq_u64 s[0:1], 0\n\ts_cbranch_scc1 .LBB0_10\n; %bb.5: ; in Loop: Header=BB0_4 Depth=1\n\tv_mul_lo_u32 v0, v8, v5\n\tv_mul_lo_u32 v4, v7, v6\n\tv_mad_u64_u32 v[9:10], null, v7, v5, 0\n ; implicit-def: $vgpr5_vgpr6\n\ts_mov_b32 s0, exec_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_add3_u32 v10, v10, v4, v0\n\tv_or_b32_e32 v4, s5, v10\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_ne_u64_e32 0, v[3:4]\n\ts_xor_b32 s7, exec_lo, s0\n\ts_cbranch_execz .LBB0_7\n; %bb.6: ; in Loop: Header=BB0_4 Depth=1\n\tv_cvt_f32_u32_e32 v0, s4\n\tv_cvt_f32_u32_e32 v4, s5\n\ts_sub_u32 s0, 0, s4\n\ts_subb_u32 s8, 0, s5\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmac_f32_e32 v0, 0x4f800000, v4\n\tv_rcp_f32_e32 v0, v0\n\ts_waitcnt_depctr 0xfff\n\tv_mul_f32_e32 v0, 0x5f7ffffc, v0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mul_f32_e32 v4, 0x2f800000, v0\n\tv_trunc_f32_e32 v4, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_fmac_f32_e32 v0, 0xcf800000, v4\n\tv_cvt_u32_f32_e32 v4, v4\n\tv_cvt_u32_f32_e32 v0, v0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v5, s0, v4\n\tv_mul_hi_u32 v6, s0, v0\n\tv_mul_lo_u32 v11, s8, v0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v5, v6, v5\n\tv_mul_lo_u32 v6, s0, v0\n\tv_add_nc_u32_e32 v5, v5, v11\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v11, v0, v6\n\tv_mul_lo_u32 v12, v0, v5\n\tv_mul_hi_u32 v13, v0, v5\n\tv_mul_hi_u32 v14, v4, v6\n\tv_mul_lo_u32 v6, v4, v6\n\tv_mul_hi_u32 v15, v4, v5\n\tv_mul_lo_u32 v5, v4, v5\n\tv_add_co_u32 v11, vcc_lo, v11, v12\n\tv_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v6, vcc_lo, v11, v6\n\tv_add_co_ci_u32_e32 v6, vcc_lo, v12, v14, vcc_lo\n\tv_add_co_ci_u32_e32 v11, vcc_lo, 0, v15, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v5, vcc_lo, v6, v5\n\tv_add_co_ci_u32_e32 v6, vcc_lo, 0, v11, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, v5\n\tv_add_co_ci_u32_e32 v4, vcc_lo, v4, v6, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_mul_hi_u32 v5, s0, v0\n\tv_mul_lo_u32 v11, s8, v0\n\tv_mul_lo_u32 v6, s0, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v5, v5, v6\n\tv_mul_lo_u32 v6, s0, v0\n\tv_add_nc_u32_e32 v5, v5, v11\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v11, v0, v6\n\tv_mul_lo_u32 v12, v0, v5\n\tv_mul_hi_u32 v13, v0, v5\n\tv_mul_hi_u32 v14, v4, v6\n\tv_mul_lo_u32 v6, v4, v6\n\tv_mul_hi_u32 v15, v4, v5\n\tv_mul_lo_u32 v5, v4, v5\n\tv_add_co_u32 v11, vcc_lo, v11, v12\n\tv_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v6, vcc_lo, v11, v6\n\tv_add_co_ci_u32_e32 v6, vcc_lo, v12, v14, vcc_lo\n\tv_add_co_ci_u32_e32 v11, vcc_lo, 0, v15, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v5, vcc_lo, v6, v5\n\tv_add_co_ci_u32_e32 v6, vcc_lo, 0, v11, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, v5\n\tv_add_co_ci_u32_e32 v6, vcc_lo, v4, v6, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_mul_hi_u32 v15, v9, v0\n\tv_mad_u64_u32 v[11:12], null, v10, v0, 0\n\tv_mad_u64_u32 v[4:5], null, v9, v6, 0\n\tv_mad_u64_u32 v[13:14], null, v10, v6, 0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v0, vcc_lo, v15, v4\n\tv_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, v11\n\tv_add_co_ci_u32_e32 v0, vcc_lo, v4, v12, vcc_lo\n\tv_add_co_ci_u32_e32 v4, vcc_lo, 0, v14, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, v13\n\tv_add_co_ci_u32_e32 v6, vcc_lo, 0, v4, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_mul_lo_u32 v11, s5, v0\n\tv_mad_u64_u32 v[4:5], null, s4, v0, 0\n\tv_mul_lo_u32 v0, s4, v6\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_sub_co_u32 v4, vcc_lo, v9, v4\n\tv_add3_u32 v0, v5, v0, v11\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_sub_nc_u32_e32 v5, v10, v0\n\tv_subrev_co_ci_u32_e64 v5, s0, s5, v5, vcc_lo\n\tv_sub_co_ci_u32_e32 v0, vcc_lo, v10, v0, vcc_lo\n\tv_sub_co_u32 v6, vcc_lo, v4, s4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)\n\tv_subrev_co_ci_u32_e64 v9, s0, 0, v5, vcc_lo\n\tv_cmp_le_u32_e64 s0, s4, v4\n\tv_subrev_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo\n\tv_cmp_le_u32_e32 vcc_lo, s5, v0\n\tv_cndmask_b32_e64 v10, 0, -1, s0\n\tv_cmp_le_u32_e64 s0, s4, v6\n\tv_cndmask_b32_e64 v13, 0, -1, vcc_lo\n\tv_cmp_eq_u32_e32 vcc_lo, s5, v9\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cndmask_b32_e64 v11, 0, -1, s0\n\tv_cmp_le_u32_e64 s0, s5, v9\n\tv_cndmask_b32_e64 v12, 0, -1, s0\n\tv_cmp_eq_u32_e64 s0, s5, v0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)\n\tv_cndmask_b32_e32 v11, v12, v11, vcc_lo\n\tv_sub_co_u32 v12, vcc_lo, v6, s4\n\tv_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo\n\tv_cmp_ne_u32_e32 vcc_lo, 0, v11\n\tv_cndmask_b32_e64 v10, v13, v10, s0\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_cndmask_b32_e32 v5, v9, v5, vcc_lo\n\tv_cndmask_b32_e32 v9, v6, v12, vcc_lo\n\tv_cmp_ne_u32_e32 vcc_lo, 0, v10\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)\n\tv_cndmask_b32_e32 v6, v0, v5, vcc_lo\n\tv_cndmask_b32_e32 v5, v4, v9, vcc_lo\n ; implicit-def: $vgpr9_vgpr10\n.LBB0_7: ; in Loop: Header=BB0_4 Depth=1\n\ts_and_not1_saveexec_b32 s0, s7\n\ts_cbranch_execz .LBB0_9\n; %bb.8: ; in Loop: Header=BB0_4 Depth=1\n\tv_cvt_f32_u32_e32 v0, s4\n\ts_sub_i32 s7, 0, s4\n\tv_mov_b32_e32 v6, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_rcp_iflag_f32_e32 v0, v0\n\ts_waitcnt_depctr 0xfff\n\tv_mul_f32_e32 v0, 0x4f7ffffe, v0\n\tv_cvt_u32_f32_e32 v0, v0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mul_lo_u32 v4, s7, v0\n\tv_mul_hi_u32 v4, v0, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_add_nc_u32_e32 v0, v0, v4\n\tv_mul_hi_u32 v0, v9, v0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mul_lo_u32 v0, v0, s4\n\tv_sub_nc_u32_e32 v0, v9, v0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_subrev_nc_u32_e32 v4, s4, v0\n\tv_cmp_le_u32_e32 vcc_lo, s4, v0\n\tv_cndmask_b32_e32 v0, v0, v4, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_subrev_nc_u32_e32 v4, s4, v0\n\tv_cmp_le_u32_e32 vcc_lo, s4, v0\n\tv_cndmask_b32_e32 v5, v0, v4, vcc_lo\n.LBB0_9: ; in Loop: Header=BB0_4 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB0_10: ; in Loop: Header=BB0_4 Depth=1\n\tv_mul_lo_u32 v0, v7, v8\n\tv_mad_u64_u32 v[9:10], null, v7, v7, 0\n ; implicit-def: $vgpr7_vgpr8\n\ts_mov_b32 s0, exec_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_add3_u32 v10, v10, v0, v0\n\tv_or_b32_e32 v4, s5, v10\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_ne_u64_e32 0, v[3:4]\n\ts_xor_b32 s7, exec_lo, s0\n\ts_cbranch_execz .LBB0_12\n; %bb.11: ; in Loop: Header=BB0_4 Depth=1\n\tv_cvt_f32_u32_e32 v0, s4\n\tv_cvt_f32_u32_e32 v4, s5\n\ts_sub_u32 s0, 0, s4\n\ts_subb_u32 s8, 0, s5\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmac_f32_e32 v0, 0x4f800000, v4\n\tv_rcp_f32_e32 v0, v0\n\ts_waitcnt_depctr 0xfff\n\tv_mul_f32_e32 v0, 0x5f7ffffc, v0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mul_f32_e32 v4, 0x2f800000, v0\n\tv_trunc_f32_e32 v4, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_fmac_f32_e32 v0, 0xcf800000, v4\n\tv_cvt_u32_f32_e32 v4, v4\n\tv_cvt_u32_f32_e32 v0, v0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_lo_u32 v7, s0, v4\n\tv_mul_hi_u32 v8, s0, v0\n\tv_mul_lo_u32 v11, s8, v0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v7, v8, v7\n\tv_mul_lo_u32 v8, s0, v0\n\tv_add_nc_u32_e32 v7, v7, v11\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v11, v0, v8\n\tv_mul_lo_u32 v12, v0, v7\n\tv_mul_hi_u32 v13, v0, v7\n\tv_mul_hi_u32 v14, v4, v8\n\tv_mul_lo_u32 v8, v4, v8\n\tv_mul_hi_u32 v15, v4, v7\n\tv_mul_lo_u32 v7, v4, v7\n\tv_add_co_u32 v11, vcc_lo, v11, v12\n\tv_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v8, vcc_lo, v11, v8\n\tv_add_co_ci_u32_e32 v8, vcc_lo, v12, v14, vcc_lo\n\tv_add_co_ci_u32_e32 v11, vcc_lo, 0, v15, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v7, vcc_lo, v8, v7\n\tv_add_co_ci_u32_e32 v8, vcc_lo, 0, v11, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, v7\n\tv_add_co_ci_u32_e32 v4, vcc_lo, v4, v8, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_mul_hi_u32 v7, s0, v0\n\tv_mul_lo_u32 v11, s8, v0\n\tv_mul_lo_u32 v8, s0, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_add_nc_u32_e32 v7, v7, v8\n\tv_mul_lo_u32 v8, s0, v0\n\tv_add_nc_u32_e32 v7, v7, v11\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_mul_hi_u32 v11, v0, v8\n\tv_mul_lo_u32 v12, v0, v7\n\tv_mul_hi_u32 v13, v0, v7\n\tv_mul_hi_u32 v14, v4, v8\n\tv_mul_lo_u32 v8, v4, v8\n\tv_mul_hi_u32 v15, v4, v7\n\tv_mul_lo_u32 v7, v4, v7\n\tv_add_co_u32 v11, vcc_lo, v11, v12\n\tv_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v8, vcc_lo, v11, v8\n\tv_add_co_ci_u32_e32 v8, vcc_lo, v12, v14, vcc_lo\n\tv_add_co_ci_u32_e32 v11, vcc_lo, 0, v15, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v7, vcc_lo, v8, v7\n\tv_add_co_ci_u32_e32 v8, vcc_lo, 0, v11, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, v7\n\tv_add_co_ci_u32_e32 v4, vcc_lo, v4, v8, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_mul_hi_u32 v15, v9, v0\n\tv_mad_u64_u32 v[11:12], null, v10, v0, 0\n\tv_mad_u64_u32 v[7:8], null, v9, v4, 0\n\tv_mad_u64_u32 v[13:14], null, v10, v4, 0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)\n\tv_add_co_u32 v0, vcc_lo, v15, v7\n\tv_add_co_ci_u32_e32 v4, vcc_lo, 0, v8, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, v11\n\tv_add_co_ci_u32_e32 v0, vcc_lo, v4, v12, vcc_lo\n\tv_add_co_ci_u32_e32 v4, vcc_lo, 0, v14, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v0, vcc_lo, v0, v13\n\tv_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_mul_lo_u32 v11, s5, v0\n\tv_mad_u64_u32 v[7:8], null, s4, v0, 0\n\tv_mul_lo_u32 v0, s4, v4\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_sub_co_u32 v7, vcc_lo, v9, v7\n\tv_add3_u32 v0, v8, v0, v11\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_sub_nc_u32_e32 v4, v10, v0\n\tv_subrev_co_ci_u32_e64 v4, s0, s5, v4, vcc_lo\n\tv_sub_co_ci_u32_e32 v0, vcc_lo, v10, v0, vcc_lo\n\tv_sub_co_u32 v8, vcc_lo, v7, s4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)\n\tv_subrev_co_ci_u32_e64 v9, s0, 0, v4, vcc_lo\n\tv_cmp_le_u32_e64 s0, s4, v7\n\tv_subrev_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo\n\tv_cmp_le_u32_e32 vcc_lo, s5, v0\n\tv_cndmask_b32_e64 v10, 0, -1, s0\n\tv_cmp_le_u32_e64 s0, s4, v8\n\tv_cndmask_b32_e64 v13, 0, -1, vcc_lo\n\tv_cmp_eq_u32_e32 vcc_lo, s5, v9\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cndmask_b32_e64 v11, 0, -1, s0\n\tv_cmp_le_u32_e64 s0, s5, v9\n\tv_cndmask_b32_e64 v12, 0, -1, s0\n\tv_cmp_eq_u32_e64 s0, s5, v0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)\n\tv_cndmask_b32_e32 v11, v12, v11, vcc_lo\n\tv_sub_co_u32 v12, vcc_lo, v8, s4\n\tv_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo\n\tv_cmp_ne_u32_e32 vcc_lo, 0, v11\n\tv_cndmask_b32_e64 v10, v13, v10, s0\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_cndmask_b32_e32 v4, v9, v4, vcc_lo\n\tv_cndmask_b32_e32 v9, v8, v12, vcc_lo\n\tv_cmp_ne_u32_e32 vcc_lo, 0, v10\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v8, v0, v4\n ; implicit-def: $vgpr9_vgpr10\n.LBB0_12: ; in Loop: Header=BB0_4 Depth=1\n\ts_and_not1_saveexec_b32 s0, s7\n\ts_cbranch_execz .LBB0_3\n; %bb.13: ; in Loop: Header=BB0_4 Depth=1\n\tv_cvt_f32_u32_e32 v0, s4\n\tv_mov_b32_e32 v8, v3\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_rcp_iflag_f32_e32 v0, v0\n\ts_waitcnt_depctr 0xfff\n\tv_mul_f32_e32 v0, 0x4f7ffffe, v0\n\tv_cvt_u32_f32_e32 v0, v0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mul_lo_u32 v4, s6, v0\n\tv_mul_hi_u32 v4, v0, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_add_nc_u32_e32 v0, v0, v4\n\tv_mul_hi_u32 v0, v9, v0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mul_lo_u32 v0, v0, s4\n\tv_sub_nc_u32_e32 v0, v9, v0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_subrev_nc_u32_e32 v4, s4, v0\n\tv_cmp_le_u32_e32 vcc_lo, s4, v0\n\tv_cndmask_b32_e32 v0, v0, v4, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_subrev_nc_u32_e32 v4, s4, v0\n\tv_cmp_le_u32_e32 vcc_lo, s4, v0\n\tv_cndmask_b32_e32 v7, v0, v4, vcc_lo\n\ts_branch .LBB0_3\n.LBB0_14:\n\tv_mov_b32_e32 v5, 1\n\tv_mov_b32_e32 v6, 0\n.LBB0_15:\n\tglobal_store_b64 v[1:2], v[5:6], off\n.LBB0_16:\n\ts_nop 0\n\ts_sendmsg sendmsg(MSG_DEALLOC_VGPRS)\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z9rsaKernelPyi\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 272\n\t\t.amdhsa_user_sgpr_count 15\n\t\t.amdhsa_user_sgpr_dispatch_ptr 0\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 0\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 0\n\t\t.amdhsa_next_free_vgpr 16\n\t\t.amdhsa_next_free_sgpr 16\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end0:\n\t.size\t_Z9rsaKernelPyi, .Lfunc_end0-_Z9rsaKernelPyi\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 2188\n; NumSgprs: 18\n; NumVgprs: 16\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 2\n; VGPRBlocks: 1\n; NumSGPRsForWavesPerEU: 18\n; NumVGPRsForWavesPerEU: 16\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 15\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.protected\td ; @d\n\t.type\td,@object\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\td\n\t.p2align\t3, 0x0\nd:\n\t.quad\t0 ; 0x0\n\t.size\td, 8\n\n\t.protected\tn ; @n\n\t.type\tn,@object\n\t.globl\tn\n\t.p2align\t3, 0x0\nn:\n\t.quad\t0 ; 0x0\n\t.size\tn, 8\n\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .offset: 8\n .size: 4\n .value_kind: by_value\n - .offset: 16\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 20\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 24\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 28\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 30\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 32\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 34\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 36\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 38\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 56\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 64\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 72\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 80\n .size: 2\n .value_kind: hidden_grid_dims\n - .offset: 136\n .size: 4\n .value_kind: hidden_dynamic_lds_size\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 272\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z9rsaKernelPyi\n .private_segment_fixed_size: 0\n .sgpr_count: 18\n .sgpr_spill_count: 0\n .symbol: _Z9rsaKernelPyi.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 16\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162591,"cells":{"id":{"kind":"string","value":"726873b3eb87905a2df2c262bbbd65ebfcb2b689_O1"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z9bfsKernelPiS_S_S_S_S_i --------------------------\n .section .text._Z9bfsKernelPiS_S_S_S_S_i,\"ax\",@progbits\n .sectionflags @\"SHF_BARRIERS=1\"\n .sectioninfo @\"SHI_REGISTERS=24\"\n .align 128\n\n\n\n\n .global _Z9bfsKernelPiS_S_S_S_S_i\n .type _Z9bfsKernelPiS_S_S_S_S_i,@function\n .size _Z9bfsKernelPiS_S_S_S_S_i,(.L_x_10 - _Z9bfsKernelPiS_S_S_S_S_i)\n .other _Z9bfsKernelPiS_S_S_S_S_i,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z9bfsKernelPiS_S_S_S_S_i:\n.text._Z9bfsKernelPiS_S_S_S_S_i:\n /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;\n /*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ;\n /*0020*/ MOV R3, c[0x0][0x18c] ;\n /*0030*/ ULDC.64 UR6, c[0x0][0x118] ;\n /*0040*/ LDG.E R9, [R2.64] ;\n /*0050*/ BSSY B0, `(.L_x_0) ;\n /*0060*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ;\n /*0070*/ S2R R0, SR_CTAID.X ;\n /*0080*/ S2R R5, SR_TID.X ;\n /*0090*/ IMAD R0, R0, c[0x0][0x0], R5 ;\n /*00a0*/ ISETP.GE.AND P0, PT, R0, R9, PT ;\n /*00b0*/ @P0 BRA `(.L_x_1) ;\n /*00c0*/ MOV R5, 0x4 ;\n /*00d0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x180] ;\n /*00e0*/ LDG.E R5, [R4.64] ;\n /*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ;\n /*0100*/ STS [R0.X4], R5 ;\n.L_x_1:\n /*0110*/ BSYNC B0 ;\n.L_x_0:\n /*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ;\n /*0130*/ ISETP.NE.AND P0, PT, R0.reuse, RZ, PT ;\n /*0140*/ ISETP.GE.AND P1, PT, R0, R7, PT ;\n /*0150*/ @!P0 STG.E [R2.64], RZ ;\n /*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ;\n /*0170*/ @P1 BRA `(.L_x_2) ;\n /*0180*/ MOV R4, c[0x0][0x0] ;\n /*0190*/ ULDC.64 UR4, c[0x0][0x10] ;\n /*01a0*/ UIMAD UR4, UR4, UR5, URZ ;\n /*01b0*/ IMAD R4, R4, c[0x0][0x4], RZ ;\n /*01c0*/ ULDC UR5, c[0x0][0xc] ;\n /*01d0*/ UIMAD UR4, UR4, UR5, URZ ;\n /*01e0*/ IMAD R4, R4, c[0x0][0x8], RZ ;\n /*01f0*/ IMAD R9, R4, UR4, RZ ;\n.L_x_8:\n /*0200*/ LDS R4, [R0.X4] ;\n /*0210*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ;\n /*0220*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ;\n /*0230*/ LDG.E R15, [R4.64] ;\n /*0240*/ LDG.E R6, [R4.64+0x4] ;\n /*0250*/ BSSY B0, `(.L_x_3) ;\n /*0260*/ ISETP.GE.AND P0, PT, R15, R6, PT ;\n /*0270*/ @P0 BRA `(.L_x_4) ;\n /*0280*/ MOV R10, 0x4 ;\n /*0290*/ IMAD.WIDE R10, R15, R10, c[0x0][0x168] ;\n /*02a0*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ;\n /*02b0*/ MOV R17, R11 ;\n.L_x_7:\n /*02c0*/ IMAD.MOV.U32 R13, RZ, RZ, R17 ;\n /*02d0*/ LDG.E R21, [R12.64] ;\n /*02e0*/ MOV R10, 0x4 ;\n /*02f0*/ IMAD.MOV.U32 R18, RZ, RZ, -0x1 ;\n /*0300*/ MOV R19, c[0x0][0x190] ;\n /*0310*/ YIELD ;\n /*0320*/ IMAD.WIDE R10, R21, R10, c[0x0][0x170] ;\n /*0330*/ ATOMG.E.CAS.STRONG.GPU PT, R10, [R10], R18, R19 ;\n /*0340*/ BSSY B1, `(.L_x_5) ;\n /*0350*/ ISETP.NE.AND P0, PT, R10, -0x1, PT ;\n /*0360*/ @P0 BRA `(.L_x_6) ;\n /*0370*/ S2R R11, SR_LANEID ;\n /*0380*/ VOTEU.ANY UR4, UPT, PT ;\n /*0390*/ FLO.U32 R6, UR4 ;\n /*03a0*/ POPC R13, UR4 ;\n /*03b0*/ ISETP.EQ.U32.AND P0, PT, R6, R11, PT ;\n /*03c0*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R13, [R2.64], R13 ;\n /*03d0*/ S2R R8, SR_LTMASK ;\n /*03e0*/ LOP3.LUT R8, R8, UR4, RZ, 0xc0, !PT ;\n /*03f0*/ POPC R11, R8 ;\n /*0400*/ SHFL.IDX PT, R10, R13, R6, 0x1f ;\n /*0410*/ IMAD.IADD R10, R10, 0x1, R11 ;\n /*0420*/ ISETP.GT.AND P0, PT, R10, 0xfff, PT ;\n /*0430*/ @!P0 MOV R11, 0x4 ;\n /*0440*/ @!P0 IMAD.WIDE R10, R10, R11, c[0x0][0x180] ;\n /*0450*/ @!P0 STG.E [R10.64], R21 ;\n.L_x_6:\n /*0460*/ BSYNC B1 ;\n.L_x_5:\n /*0470*/ LDG.E R6, [R4.64+0x4] ;\n /*0480*/ IADD3 R15, R15, 0x1, RZ ;\n /*0490*/ IADD3 R12, P1, R12, 0x4, RZ ;\n /*04a0*/ IMAD.X R17, RZ, RZ, R17, P1 ;\n /*04b0*/ ISETP.GE.AND P0, PT, R15, R6, PT ;\n /*04c0*/ @!P0 BRA `(.L_x_7) ;\n.L_x_4:\n /*04d0*/ BSYNC B0 ;\n.L_x_3:\n /*04e0*/ IMAD R0, R9, c[0x0][0x0], R0 ;\n /*04f0*/ ISETP.GE.AND P0, PT, R0, R7, PT ;\n /*0500*/ @!P0 BRA `(.L_x_8) ;\n.L_x_2:\n /*0510*/ WARPSYNC 0xffffffff ;\n /*0520*/ BAR.SYNC.DEFER_BLOCKING 0x0 ;\n /*0530*/ EXIT ;\n.L_x_9:\n /*0540*/ BRA `(.L_x_9);\n /*0550*/ NOP;\n /*0560*/ NOP;\n /*0570*/ NOP;\n /*0580*/ NOP;\n /*0590*/ NOP;\n /*05a0*/ NOP;\n /*05b0*/ NOP;\n /*05c0*/ NOP;\n /*05d0*/ NOP;\n /*05e0*/ NOP;\n /*05f0*/ NOP;\n.L_x_10:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.protected\t_Z9bfsKernelPiS_S_S_S_S_i ; -- Begin function _Z9bfsKernelPiS_S_S_S_S_i\n\t.globl\t_Z9bfsKernelPiS_S_S_S_S_i\n\t.p2align\t8\n\t.type\t_Z9bfsKernelPiS_S_S_S_S_i,@function\n_Z9bfsKernelPiS_S_S_S_S_i: ; @_Z9bfsKernelPiS_S_S_S_S_i\n; %bb.0:\n\ts_clause 0x1\n\ts_load_b32 s18, s[0:1], 0x44\n\ts_load_b32 s16, s[0:1], 0x38\n\ts_add_u32 s2, s0, 56\n\ts_addc_u32 s3, s1, 0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s17, s18, 0xffff\n\ts_cmp_lt_u32 s15, s16\n\ts_cselect_b32 s4, 12, 18\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_mov_b32_e32 v1, s4\n\ts_load_b128 s[4:7], s[0:1], 0x20\n\tglobal_load_u16 v3, v1, s[2:3]\n\tv_mad_u64_u32 v[1:2], null, s15, s17, v[0:1]\n\tv_mov_b32_e32 v0, 0\n\ts_mov_b32 s3, exec_lo\n\ts_waitcnt lgkmcnt(0)\n\ts_load_b32 s2, s[6:7], 0x0\n\ts_waitcnt lgkmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_cmpx_gt_i32_e64 s2, v1\n\ts_cbranch_execz .LBB0_2\n; %bb.1:\n\tv_ashrrev_i32_e32 v2, 31, v1\n\tv_mov_b32_e32 v0, s2\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[4:5], 2, v[1:2]\n\tv_add_co_u32 v4, vcc_lo, s4, v4\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo\n\tglobal_load_b32 v2, v[4:5], off\n\tv_lshl_add_u32 v4, v1, 2, 0\n\ts_waitcnt vmcnt(0)\n\tds_store_b32 v4, v2\n.LBB0_2:\n\ts_or_b32 exec_lo, exec_lo, s3\n\ts_clause 0x1\n\ts_load_b64 s[12:13], s[0:1], 0x3c\n\ts_load_b32 s15, s[0:1], 0x48\n\ts_mov_b32 s2, exec_lo\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\ts_barrier\n\tbuffer_gl0_inv\n\tv_cmpx_eq_u32_e32 0, v1\n\ts_cbranch_execz .LBB0_4\n; %bb.3:\n\tv_mov_b32_e32 v2, 0\n\tglobal_store_b32 v2, v2, s[6:7]\n.LBB0_4:\n\ts_or_b32 exec_lo, exec_lo, s2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_mov_b32 s14, exec_lo\n\ts_waitcnt_vscnt null, 0x0\n\ts_barrier\n\tbuffer_gl0_inv\n\tv_cmpx_lt_i32_e64 v1, v0\n\ts_cbranch_execz .LBB0_15\n; %bb.5:\n\ts_clause 0x2\n\ts_load_b128 s[8:11], s[0:1], 0x0\n\ts_load_b64 s[2:3], s[0:1], 0x10\n\ts_load_b32 s1, s[0:1], 0x30\n\ts_mul_i32 s13, s13, s16\n\ts_and_b32 s15, 0xffff, s15\n\ts_mul_i32 s13, s13, s17\n\ts_lshr_b32 s0, s18, 16\n\ts_mul_i32 s13, s13, s15\n\tv_dual_mov_b32 v11, 0 :: v_dual_and_b32 v2, 0xffff, v3\n\ts_and_b32 s0, 0xffff, s0\n\ts_mul_i32 s12, s13, s12\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_mul_i32 s12, s12, s0\n\ts_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)\n\tv_mul_lo_u32 v10, s12, v2\n\ts_mov_b32 s12, 0\n\ts_branch .LBB0_7\n.LBB0_6: ; in Loop: Header=BB0_7 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s13\n\tv_add_nc_u32_e32 v1, v1, v10\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\tv_cmp_ge_i32_e32 vcc_lo, v1, v0\n\ts_or_b32 s12, vcc_lo, s12\n\ts_and_not1_b32 exec_lo, exec_lo, s12\n\ts_cbranch_execz .LBB0_15\n.LBB0_7: ; =>This Loop Header: Depth=1\n ; Child Loop BB0_10 Depth 2\n\tv_lshl_add_u32 v2, v1, 2, 0\n\ts_mov_b32 s13, exec_lo\n\tds_load_b32 v2, v2\n\ts_waitcnt lgkmcnt(0)\n\tv_ashrrev_i32_e32 v3, 31, v2\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[2:3], 2, v[2:3]\n\tv_add_co_u32 v2, vcc_lo, s8, v2\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo\n\tglobal_load_b64 v[4:5], v[2:3], off\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_lt_i32_e64 v4, v5\n\ts_cbranch_execz .LBB0_6\n; %bb.8: ; in Loop: Header=BB0_7 Depth=1\n\tv_ashrrev_i32_e32 v5, 31, v4\n\ts_mov_b32 s15, 0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[5:6], 2, v[4:5]\n\tv_add_co_u32 v5, vcc_lo, s10, v5\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo\n\ts_branch .LBB0_10\n.LBB0_9: ; in Loop: Header=BB0_10 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s0\n\tglobal_load_b32 v7, v[2:3], off offset:4\n\tv_add_nc_u32_e32 v4, 1, v4\n\tv_add_co_u32 v5, s0, v5, 4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_ci_u32_e64 v6, s0, 0, v6, s0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ge_i32_e32 vcc_lo, v4, v7\n\ts_or_b32 s15, vcc_lo, s15\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s15\n\ts_cbranch_execz .LBB0_6\n.LBB0_10: ; Parent Loop BB0_7 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tglobal_load_b32 v7, v[5:6], off\n\tv_dual_mov_b32 v12, s1 :: v_dual_mov_b32 v13, -1\n\ts_mov_b32 s0, exec_lo\n\ts_waitcnt vmcnt(0)\n\tv_ashrrev_i32_e32 v8, 31, v7\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[8:9], 2, v[7:8]\n\tv_add_co_u32 v8, vcc_lo, s2, v8\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo\n\tglobal_atomic_cmpswap_b32 v8, v[8:9], v[12:13], off glc\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_eq_u32_e32 -1, v8\n\ts_cbranch_execz .LBB0_9\n; %bb.11: ; in Loop: Header=BB0_10 Depth=2\n\ts_mov_b32 s17, exec_lo\n\ts_mov_b32 s16, exec_lo\n\tv_mbcnt_lo_u32_b32 v8, s17, 0\n ; implicit-def: $vgpr9\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_eq_u32_e32 0, v8\n\ts_cbranch_execz .LBB0_13\n; %bb.12: ; in Loop: Header=BB0_10 Depth=2\n\ts_bcnt1_i32_b32 s17, s17\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\tv_mov_b32_e32 v9, s17\n\tglobal_atomic_add_u32 v9, v11, v9, s[6:7] glc\n.LBB0_13: ; in Loop: Header=BB0_10 Depth=2\n\ts_or_b32 exec_lo, exec_lo, s16\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s16, v9\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_add_nc_u32_e32 v8, s16, v8\n\tv_cmp_gt_i32_e32 vcc_lo, 0x1000, v8\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB0_9\n; %bb.14: ; in Loop: Header=BB0_10 Depth=2\n\tv_ashrrev_i32_e32 v9, 31, v8\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[8:9], 2, v[8:9]\n\tv_add_co_u32 v8, vcc_lo, s4, v8\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo\n\tglobal_store_b32 v[8:9], v7, off\n\ts_branch .LBB0_9\n.LBB0_15:\n\ts_or_b32 exec_lo, exec_lo, s14\n\ts_waitcnt_vscnt null, 0x0\n\ts_barrier\n\tbuffer_gl0_inv\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z9bfsKernelPiS_S_S_S_S_i\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 312\n\t\t.amdhsa_user_sgpr_count 15\n\t\t.amdhsa_user_sgpr_dispatch_ptr 0\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 0\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 0\n\t\t.amdhsa_next_free_vgpr 14\n\t\t.amdhsa_next_free_sgpr 19\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end0:\n\t.size\t_Z9bfsKernelPiS_S_S_S_S_i, .Lfunc_end0-_Z9bfsKernelPiS_S_S_S_S_i\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 828\n; NumSgprs: 21\n; NumVgprs: 14\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 2\n; VGPRBlocks: 1\n; NumSGPRsForWavesPerEU: 21\n; NumVGPRsForWavesPerEU: 14\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 15\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 16\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 24\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 32\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 40\n .size: 8\n .value_kind: global_buffer\n - .offset: 48\n .size: 4\n .value_kind: by_value\n - .offset: 56\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 60\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 64\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 68\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 70\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 72\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 74\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 76\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 78\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 96\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 104\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 112\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 120\n .size: 2\n .value_kind: hidden_grid_dims\n - .offset: 176\n .size: 4\n .value_kind: hidden_dynamic_lds_size\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 312\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z9bfsKernelPiS_S_S_S_S_i\n .private_segment_fixed_size: 0\n .sgpr_count: 21\n .sgpr_spill_count: 0\n .symbol: _Z9bfsKernelPiS_S_S_S_S_i.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 14\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162592,"cells":{"id":{"kind":"string","value":"900738955836d58a72d6aedd7dff706c7ed0b866_O1"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z22geneticAlgorithmKernelPfS_P17curandStateXORWOW --------------------------\n .section .text._Z22geneticAlgorithmKernelPfS_P17curandStateXORWOW,\"ax\",@progbits\n .sectionflags @\"SHF_BARRIERS=1\"\n .sectioninfo @\"SHI_REGISTERS=38\"\n .align 128\n\n\n\n\n .global _Z22geneticAlgorithmKernelPfS_P17curandStateXORWOW\n .type _Z22geneticAlgorithmKernelPfS_P17curandStateXORWOW,@function\n .size _Z22geneticAlgorithmKernelPfS_P17curandStateXORWOW,(.L_x_17 - _Z22geneticAlgorithmKernelPfS_P17curandStateXORWOW)\n .other _Z22geneticAlgorithmKernelPfS_P17curandStateXORWOW,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z22geneticAlgorithmKernelPfS_P17curandStateXORWOW:\n.text._Z22geneticAlgorithmKernelPfS_P17curandStateXORWOW:\n /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;\n /*0010*/ S2R R2, SR_TID.X ;\n /*0020*/ IMAD.MOV.U32 R12, RZ, RZ, 0x30 ;\n /*0030*/ ULDC.64 UR10, c[0x0][0x118] ;\n /*0040*/ BSSY B0, `(.L_x_0) ;\n /*0050*/ S2R R3, SR_CTAID.X ;\n /*0060*/ ISETP.NE.AND P0, PT, R2, RZ, PT ;\n /*0070*/ IMAD.WIDE.U32 R12, R3, R12, c[0x0][0x170] ;\n /*0080*/ @P0 BRA `(.L_x_1) ;\n /*0090*/ CS2R R4, SR_CLOCKLO ;\n /*00a0*/ LOP3.LUT R0, R4, 0xaad26b49, RZ, 0x3c, !PT ;\n /*00b0*/ LOP3.LUT R4, R5, 0xf7dcefdd, RZ, 0x3c, !PT ;\n /*00c0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ;\n /*00d0*/ IMAD R0, R0, 0x4182bed5, RZ ;\n /*00e0*/ IMAD R5, R4, -0x658354e5, RZ ;\n /*00f0*/ IADD3 R7, R0.reuse, 0x75bcd15, RZ ;\n /*0100*/ IADD3 R6, R0.reuse, 0x64f0c9, R5 ;\n /*0110*/ LOP3.LUT R8, R0.reuse, 0x159a55e5, RZ, 0x3c, !PT ;\n /*0120*/ IADD3 R9, R5.reuse, 0x1f123bb5, RZ ;\n /*0130*/ STG.E.64 [R12.64], R6 ;\n /*0140*/ IADD3 R11, R0, 0x583f19, RZ ;\n /*0150*/ LOP3.LUT R10, R5, 0x5491333, RZ, 0x3c, !PT ;\n /*0160*/ STG.E.64 [R12.64+0x8], R8 ;\n /*0170*/ STG.E.64 [R12.64+0x10], R10 ;\n /*0180*/ @!P0 BRA `(.L_x_2) ;\n /*0190*/ IMAD.MOV.U32 R0, RZ, RZ, R3 ;\n /*01a0*/ UMOV UR4, URZ ;\n /*01b0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ;\n.L_x_7:\n /*01c0*/ LOP3.LUT P0, RZ, R0, 0x3, RZ, 0xc0, !PT ;\n /*01d0*/ @!P0 BRA `(.L_x_3) ;\n /*01e0*/ UMOV UR5, URZ ;\n.L_x_6:\n /*01f0*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ;\n /*0200*/ CS2R R6, SRZ ;\n /*0210*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ;\n /*0220*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ;\n /*0230*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ;\n.L_x_5:\n /*0240*/ IMAD.MOV.U32 R4, RZ, RZ, 0x30 ;\n /*0250*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ;\n /*0260*/ IMAD.WIDE.U32 R4, R3, R4, c[0x0][0x170] ;\n /*0270*/ IMAD.IADD R5, R5, 0x1, R21 ;\n /*0280*/ IMAD.WIDE R4, R6, 0x4, R4 ;\n /*0290*/ LDG.E R8, [R4.64+0x4] ;\n /*02a0*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ;\n.L_x_4:\n /*02b0*/ USHF.R.S32.HI UR8, URZ, 0x1f, UR4 ;\n /*02c0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ;\n /*02d0*/ UMOV UR9, 0xc80 ;\n /*02e0*/ IMAD R10, R6, 0x20, R21 ;\n /*02f0*/ ULDC.64 UR6, c[0x4][0x0] ;\n /*0300*/ UIMAD.WIDE.U32 UR6, UR4, UR9, UR6 ;\n /*0310*/ SHF.L.U32 R5, R4, R21, RZ ;\n /*0320*/ UIMAD UR8, UR8, 0xc80, URZ ;\n /*0330*/ IMAD R23, R10, 0x5, RZ ;\n /*0340*/ LOP3.LUT P0, RZ, R8, R5, RZ, 0xc0, !PT ;\n /*0350*/ UIADD3 UR8, UR7, UR8, URZ ;\n /*0360*/ IMAD.U32 R5, RZ, RZ, UR7 ;\n /*0370*/ IMAD.U32 R4, RZ, RZ, UR6 ;\n /*0380*/ IMAD.U32 R5, RZ, RZ, UR8 ;\n /*0390*/ IMAD.WIDE R4, R23, 0x4, R4 ;\n /*03a0*/ @P0 LDG.E R10, [R4.64] ;\n /*03b0*/ @P0 LDG.E R14, [R4.64+0x4] ;\n /*03c0*/ @P0 LDG.E R16, [R4.64+0x8] ;\n /*03d0*/ @P0 LDG.E R18, [R4.64+0xc] ;\n /*03e0*/ @P0 LDG.E R20, [R4.64+0x10] ;\n /*03f0*/ @P0 LOP3.LUT R9, R9, R10, RZ, 0x3c, !PT ;\n /*0400*/ IMAD.MOV.U32 R10, RZ, RZ, 0x2 ;\n /*0410*/ SHF.L.U32 R23, R10, R21, RZ ;\n /*0420*/ LOP3.LUT P1, RZ, R8, R23, RZ, 0xc0, !PT ;\n /*0430*/ @P1 LDG.E R10, [R4.64+0x14] ;\n /*0440*/ @P0 LOP3.LUT R7, R7, R14, RZ, 0x3c, !PT ;\n /*0450*/ @P0 LOP3.LUT R19, R19, R16, RZ, 0x3c, !PT ;\n /*0460*/ @P1 LDG.E R14, [R4.64+0x18] ;\n /*0470*/ @P0 LOP3.LUT R17, R17, R18, RZ, 0x3c, !PT ;\n /*0480*/ @P0 LOP3.LUT R15, R15, R20, RZ, 0x3c, !PT ;\n /*0490*/ @P1 LDG.E R16, [R4.64+0x1c] ;\n /*04a0*/ @P1 LDG.E R18, [R4.64+0x20] ;\n /*04b0*/ @P1 LDG.E R20, [R4.64+0x24] ;\n /*04c0*/ @P1 LOP3.LUT R9, R9, R10, RZ, 0x3c, !PT ;\n /*04d0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ;\n /*04e0*/ SHF.L.U32 R23, R10, R21, RZ ;\n /*04f0*/ LOP3.LUT P0, RZ, R8, R23, RZ, 0xc0, !PT ;\n /*0500*/ @P0 LDG.E R10, [R4.64+0x28] ;\n /*0510*/ @P1 LOP3.LUT R7, R7, R14, RZ, 0x3c, !PT ;\n /*0520*/ @P1 LOP3.LUT R19, R19, R16, RZ, 0x3c, !PT ;\n /*0530*/ @P0 LDG.E R14, [R4.64+0x2c] ;\n /*0540*/ @P1 LOP3.LUT R17, R17, R18, RZ, 0x3c, !PT ;\n /*0550*/ @P1 LOP3.LUT R15, R15, R20, RZ, 0x3c, !PT ;\n /*0560*/ @P0 LDG.E R16, [R4.64+0x30] ;\n /*0570*/ @P0 LDG.E R18, [R4.64+0x34] ;\n /*0580*/ @P0 LDG.E R20, [R4.64+0x38] ;\n /*0590*/ @P0 LOP3.LUT R9, R9, R10, RZ, 0x3c, !PT ;\n /*05a0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x8 ;\n /*05b0*/ SHF.L.U32 R23, R10, R21, RZ ;\n /*05c0*/ LOP3.LUT P1, RZ, R8, R23, RZ, 0xc0, !PT ;\n /*05d0*/ @P1 LDG.E R10, [R4.64+0x3c] ;\n /*05e0*/ @P0 LOP3.LUT R7, R7, R14, RZ, 0x3c, !PT ;\n /*05f0*/ @P0 LOP3.LUT R19, R19, R16, RZ, 0x3c, !PT ;\n /*0600*/ @P1 LDG.E R14, [R4.64+0x40] ;\n /*0610*/ @P0 LOP3.LUT R17, R17, R18, RZ, 0x3c, !PT ;\n /*0620*/ @P0 LOP3.LUT R15, R15, R20, RZ, 0x3c, !PT ;\n /*0630*/ @P1 LDG.E R16, [R4.64+0x44] ;\n /*0640*/ @P1 LDG.E R18, [R4.64+0x48] ;\n /*0650*/ @P1 LDG.E R20, [R4.64+0x4c] ;\n /*0660*/ @P1 LOP3.LUT R9, R9, R10, RZ, 0x3c, !PT ;\n /*0670*/ IMAD.MOV.U32 R10, RZ, RZ, 0x10 ;\n /*0680*/ SHF.L.U32 R23, R10, R21, RZ ;\n /*0690*/ LOP3.LUT P0, RZ, R8, R23, RZ, 0xc0, !PT ;\n /*06a0*/ @P0 LDG.E R10, [R4.64+0x50] ;\n /*06b0*/ @P1 LOP3.LUT R7, R7, R14, RZ, 0x3c, !PT ;\n /*06c0*/ @P1 LOP3.LUT R19, R19, R16, RZ, 0x3c, !PT ;\n /*06d0*/ @P0 LDG.E R14, [R4.64+0x54] ;\n /*06e0*/ @P1 LOP3.LUT R17, R17, R18, RZ, 0x3c, !PT ;\n /*06f0*/ @P1 LOP3.LUT R15, R15, R20, RZ, 0x3c, !PT ;\n /*0700*/ @P0 LDG.E R16, [R4.64+0x58] ;\n /*0710*/ @P0 LDG.E R18, [R4.64+0x5c] ;\n /*0720*/ @P0 LDG.E R20, [R4.64+0x60] ;\n /*0730*/ @P0 LOP3.LUT R9, R9, R10, RZ, 0x3c, !PT ;\n /*0740*/ IMAD.MOV.U32 R10, RZ, RZ, 0x20 ;\n /*0750*/ SHF.L.U32 R23, R10, R21, RZ ;\n /*0760*/ LOP3.LUT P1, RZ, R8, R23, RZ, 0xc0, !PT ;\n /*0770*/ @P1 LDG.E R10, [R4.64+0x64] ;\n /*0780*/ @P0 LOP3.LUT R7, R7, R14, RZ, 0x3c, !PT ;\n /*0790*/ @P0 LOP3.LUT R19, R19, R16, RZ, 0x3c, !PT ;\n /*07a0*/ @P1 LDG.E R14, [R4.64+0x68] ;\n /*07b0*/ @P0 LOP3.LUT R17, R17, R18, RZ, 0x3c, !PT ;\n /*07c0*/ @P0 LOP3.LUT R15, R15, R20, RZ, 0x3c, !PT ;\n /*07d0*/ @P1 LDG.E R16, [R4.64+0x6c] ;\n /*07e0*/ @P1 LDG.E R18, [R4.64+0x70] ;\n /*07f0*/ @P1 LDG.E R20, [R4.64+0x74] ;\n /*0800*/ @P1 LOP3.LUT R9, R9, R10, RZ, 0x3c, !PT ;\n /*0810*/ IMAD.MOV.U32 R10, RZ, RZ, 0x40 ;\n /*0820*/ SHF.L.U32 R23, R10, R21, RZ ;\n /*0830*/ LOP3.LUT P0, RZ, R8, R23, RZ, 0xc0, !PT ;\n /*0840*/ @P0 LDG.E R10, [R4.64+0x78] ;\n /*0850*/ @P1 LOP3.LUT R7, R7, R14, RZ, 0x3c, !PT ;\n /*0860*/ @P1 LOP3.LUT R19, R19, R16, RZ, 0x3c, !PT ;\n /*0870*/ @P0 LDG.E R14, [R4.64+0x7c] ;\n /*0880*/ @P1 LOP3.LUT R17, R17, R18, RZ, 0x3c, !PT ;\n /*0890*/ @P1 LOP3.LUT R15, R15, R20, RZ, 0x3c, !PT ;\n /*08a0*/ @P0 LDG.E R16, [R4.64+0x80] ;\n /*08b0*/ @P0 LDG.E R18, [R4.64+0x84] ;\n /*08c0*/ @P0 LDG.E R20, [R4.64+0x88] ;\n /*08d0*/ @P0 LOP3.LUT R9, R9, R10, RZ, 0x3c, !PT ;\n /*08e0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x80 ;\n /*08f0*/ SHF.L.U32 R23, R10, R21, RZ ;\n /*0900*/ LOP3.LUT P1, RZ, R8, R23, RZ, 0xc0, !PT ;\n /*0910*/ @P1 LDG.E R10, [R4.64+0x8c] ;\n /*0920*/ @P0 LOP3.LUT R7, R7, R14, RZ, 0x3c, !PT ;\n /*0930*/ @P0 LOP3.LUT R19, R19, R16, RZ, 0x3c, !PT ;\n /*0940*/ @P1 LDG.E R14, [R4.64+0x90] ;\n /*0950*/ @P0 LOP3.LUT R17, R17, R18, RZ, 0x3c, !PT ;\n /*0960*/ @P0 LOP3.LUT R15, R15, R20, RZ, 0x3c, !PT ;\n /*0970*/ @P1 LDG.E R16, [R4.64+0x94] ;\n /*0980*/ @P1 LDG.E R18, [R4.64+0x98] ;\n /*0990*/ @P1 LDG.E R20, [R4.64+0x9c] ;\n /*09a0*/ @P1 LOP3.LUT R9, R9, R10, RZ, 0x3c, !PT ;\n /*09b0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x100 ;\n /*09c0*/ SHF.L.U32 R23, R10, R21, RZ ;\n /*09d0*/ LOP3.LUT P0, RZ, R8, R23, RZ, 0xc0, !PT ;\n /*09e0*/ @P0 LDG.E R10, [R4.64+0xa0] ;\n /*09f0*/ @P1 LOP3.LUT R7, R7, R14, RZ, 0x3c, !PT ;\n /*0a00*/ @P1 LOP3.LUT R19, R19, R16, RZ, 0x3c, !PT ;\n /*0a10*/ @P0 LDG.E R14, [R4.64+0xa4] ;\n /*0a20*/ @P1 LOP3.LUT R17, R17, R18, RZ, 0x3c, !PT ;\n /*0a30*/ @P1 LOP3.LUT R15, R15, R20, RZ, 0x3c, !PT ;\n /*0a40*/ @P0 LDG.E R16, [R4.64+0xa8] ;\n /*0a50*/ @P0 LDG.E R18, [R4.64+0xac] ;\n /*0a60*/ @P0 LDG.E R20, [R4.64+0xb0] ;\n /*0a70*/ @P0 LOP3.LUT R9, R9, R10, RZ, 0x3c, !PT ;\n /*0a80*/ IMAD.MOV.U32 R10, RZ, RZ, 0x200 ;\n /*0a90*/ SHF.L.U32 R23, R10, R21, RZ ;\n /*0aa0*/ LOP3.LUT P1, RZ, R8, R23, RZ, 0xc0, !PT ;\n /*0ab0*/ @P1 LDG.E R10, [R4.64+0xb4] ;\n /*0ac0*/ @P0 LOP3.LUT R7, R7, R14, RZ, 0x3c, !PT ;\n /*0ad0*/ @P0 LOP3.LUT R19, R19, R16, RZ, 0x3c, !PT ;\n /*0ae0*/ @P1 LDG.E R14, [R4.64+0xb8] ;\n /*0af0*/ @P0 LOP3.LUT R17, R17, R18, RZ, 0x3c, !PT ;\n /*0b00*/ @P0 LOP3.LUT R15, R15, R20, RZ, 0x3c, !PT ;\n /*0b10*/ @P1 LDG.E R16, [R4.64+0xbc] ;\n /*0b20*/ @P1 LDG.E R18, [R4.64+0xc0] ;\n /*0b30*/ @P1 LDG.E R20, [R4.64+0xc4] ;\n /*0b40*/ @P1 LOP3.LUT R9, R9, R10, RZ, 0x3c, !PT ;\n /*0b50*/ IMAD.MOV.U32 R10, RZ, RZ, 0x400 ;\n /*0b60*/ SHF.L.U32 R23, R10, R21, RZ ;\n /*0b70*/ LOP3.LUT P0, RZ, R8, R23, RZ, 0xc0, !PT ;\n /*0b80*/ @P0 LDG.E R10, [R4.64+0xc8] ;\n /*0b90*/ @P1 LOP3.LUT R7, R7, R14, RZ, 0x3c, !PT ;\n /*0ba0*/ @P1 LOP3.LUT R19, R19, R16, RZ, 0x3c, !PT ;\n /*0bb0*/ @P0 LDG.E R14, [R4.64+0xcc] ;\n /*0bc0*/ @P1 LOP3.LUT R17, R17, R18, RZ, 0x3c, !PT ;\n /*0bd0*/ @P1 LOP3.LUT R15, R15, R20, RZ, 0x3c, !PT ;\n /*0be0*/ @P0 LDG.E R16, [R4.64+0xd0] ;\n /*0bf0*/ @P0 LDG.E R18, [R4.64+0xd4] ;\n /*0c00*/ @P0 LDG.E R20, [R4.64+0xd8] ;\n /*0c10*/ @P0 LOP3.LUT R9, R9, R10, RZ, 0x3c, !PT ;\n /*0c20*/ IMAD.MOV.U32 R10, RZ, RZ, 0x800 ;\n /*0c30*/ SHF.L.U32 R23, R10, R21, RZ ;\n /*0c40*/ LOP3.LUT P1, RZ, R8, R23, RZ, 0xc0, !PT ;\n /*0c50*/ @P1 LDG.E R10, [R4.64+0xdc] ;\n /*0c60*/ @P0 LOP3.LUT R7, R7, R14, RZ, 0x3c, !PT ;\n /*0c70*/ @P0 LOP3.LUT R19, R19, R16, RZ, 0x3c, !PT ;\n /*0c80*/ @P1 LDG.E R14, [R4.64+0xe0] ;\n /*0c90*/ @P0 LOP3.LUT R17, R17, R18, RZ, 0x3c, !PT ;\n /*0ca0*/ @P0 LOP3.LUT R15, R15, R20, RZ, 0x3c, !PT ;\n /*0cb0*/ @P1 LDG.E R16, [R4.64+0xe4] ;\n /*0cc0*/ @P1 LDG.E R18, [R4.64+0xe8] ;\n /*0cd0*/ @P1 LDG.E R20, [R4.64+0xec] ;\n /*0ce0*/ @P1 LOP3.LUT R9, R9, R10, RZ, 0x3c, !PT ;\n /*0cf0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1000 ;\n /*0d00*/ SHF.L.U32 R23, R10, R21, RZ ;\n /*0d10*/ LOP3.LUT P0, RZ, R8, R23, RZ, 0xc0, !PT ;\n /*0d20*/ @P0 LDG.E R10, [R4.64+0xf0] ;\n /*0d30*/ @P1 LOP3.LUT R7, R7, R14, RZ, 0x3c, !PT ;\n /*0d40*/ @P1 LOP3.LUT R19, R19, R16, RZ, 0x3c, !PT ;\n /*0d50*/ @P0 LDG.E R14, [R4.64+0xf4] ;\n /*0d60*/ @P1 LOP3.LUT R17, R17, R18, RZ, 0x3c, !PT ;\n /*0d70*/ @P1 LOP3.LUT R15, R15, R20, RZ, 0x3c, !PT ;\n /*0d80*/ @P0 LDG.E R16, [R4.64+0xf8] ;\n /*0d90*/ @P0 LDG.E R18, [R4.64+0xfc] ;\n /*0da0*/ @P0 LDG.E R20, [R4.64+0x100] ;\n /*0db0*/ @P0 LOP3.LUT R9, R9, R10, RZ, 0x3c, !PT ;\n /*0dc0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x2000 ;\n /*0dd0*/ SHF.L.U32 R23, R10, R21, RZ ;\n /*0de0*/ LOP3.LUT P1, RZ, R8, R23, RZ, 0xc0, !PT ;\n /*0df0*/ @P1 LDG.E R10, [R4.64+0x104] ;\n /*0e00*/ @P0 LOP3.LUT R7, R7, R14, RZ, 0x3c, !PT ;\n /*0e10*/ @P0 LOP3.LUT R19, R19, R16, RZ, 0x3c, !PT ;\n /*0e20*/ @P1 LDG.E R14, [R4.64+0x108] ;\n /*0e30*/ @P0 LOP3.LUT R17, R17, R18, RZ, 0x3c, !PT ;\n /*0e40*/ @P0 LOP3.LUT R15, R15, R20, RZ, 0x3c, !PT ;\n /*0e50*/ @P1 LDG.E R16, [R4.64+0x10c] ;\n /*0e60*/ @P1 LDG.E R18, [R4.64+0x110] ;\n /*0e70*/ @P1 LDG.E R20, [R4.64+0x114] ;\n /*0e80*/ @P1 LOP3.LUT R9, R9, R10, RZ, 0x3c, !PT ;\n /*0e90*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4000 ;\n /*0ea0*/ SHF.L.U32 R23, R10, R21, RZ ;\n /*0eb0*/ LOP3.LUT P0, RZ, R8, R23, RZ, 0xc0, !PT ;\n /*0ec0*/ @P0 LDG.E R10, [R4.64+0x118] ;\n /*0ed0*/ @P1 LOP3.LUT R7, R7, R14, RZ, 0x3c, !PT ;\n /*0ee0*/ @P1 LOP3.LUT R19, R19, R16, RZ, 0x3c, !PT ;\n /*0ef0*/ @P0 LDG.E R14, [R4.64+0x11c] ;\n /*0f00*/ @P1 LOP3.LUT R17, R17, R18, RZ, 0x3c, !PT ;\n /*0f10*/ @P1 LOP3.LUT R15, R15, R20, RZ, 0x3c, !PT ;\n /*0f20*/ @P0 LDG.E R16, [R4.64+0x120] ;\n /*0f30*/ @P0 LDG.E R18, [R4.64+0x124] ;\n /*0f40*/ @P0 LDG.E R20, [R4.64+0x128] ;\n /*0f50*/ @P0 LOP3.LUT R9, R9, R10, RZ, 0x3c, !PT ;\n /*0f60*/ IMAD.MOV.U32 R10, RZ, RZ, 0x8000 ;\n /*0f70*/ SHF.L.U32 R23, R10, R21, RZ ;\n /*0f80*/ LOP3.LUT P1, RZ, R8, R23, RZ, 0xc0, !PT ;\n /*0f90*/ @P0 LOP3.LUT R7, R7, R14, RZ, 0x3c, !PT ;\n /*0fa0*/ @P0 LOP3.LUT R19, R19, R16, RZ, 0x3c, !PT ;\n /*0fb0*/ @P0 LOP3.LUT R17, R17, R18, RZ, 0x3c, !PT ;\n /*0fc0*/ @P0 LOP3.LUT R15, R15, R20, RZ, 0x3c, !PT ;\n /*0fd0*/ @P1 LDG.E R10, [R4.64+0x12c] ;\n /*0fe0*/ @P1 LDG.E R14, [R4.64+0x130] ;\n /*0ff0*/ @P1 LDG.E R16, [R4.64+0x134] ;\n /*1000*/ @P1 LDG.E R18, [R4.64+0x138] ;\n /*1010*/ @P1 LDG.E R20, [R4.64+0x13c] ;\n /*1020*/ IADD3 R21, R21, 0x10, RZ ;\n /*1030*/ ISETP.NE.AND P0, PT, R21, 0x20, PT ;\n /*1040*/ @P1 LOP3.LUT R9, R9, R10, RZ, 0x3c, !PT ;\n /*1050*/ @P1 LOP3.LUT R7, R7, R14, RZ, 0x3c, !PT ;\n /*1060*/ @P1 LOP3.LUT R19, R19, R16, RZ, 0x3c, !PT ;\n /*1070*/ @P1 LOP3.LUT R17, R17, R18, RZ, 0x3c, !PT ;\n /*1080*/ @P1 LOP3.LUT R15, R15, R20, RZ, 0x3c, !PT ;\n /*1090*/ @P0 BRA `(.L_x_4) ;\n /*10a0*/ IADD3 R6, R6, 0x1, RZ ;\n /*10b0*/ ISETP.GE.U32.AND P0, PT, R6, 0x5, PT ;\n /*10c0*/ @!P0 BRA `(.L_x_5) ;\n /*10d0*/ UIADD3 UR5, UR5, 0x1, URZ ;\n /*10e0*/ LOP3.LUT R4, R0, 0x3, RZ, 0xc0, !PT ;\n /*10f0*/ STG.E [R12.64+0x4], R9 ;\n /*1100*/ STG.E [R12.64+0x8], R7 ;\n /*1110*/ ISETP.GT.U32.AND P0, PT, R4, UR5, PT ;\n /*1120*/ STG.E [R12.64+0xc], R19 ;\n /*1130*/ ISETP.GT.U32.AND.EX P0, PT, RZ, RZ, PT, P0 ;\n /*1140*/ STG.E [R12.64+0x10], R17 ;\n /*1150*/ STG.E [R12.64+0x14], R15 ;\n /*1160*/ @!P0 CALL.REL.NOINC `(.L_x_3) ;\n /*1170*/ BRA `(.L_x_6) ;\n.L_x_3:\n /*1180*/ SHF.R.U64 R0, R0, 0x2, R11.reuse ;\n /*1190*/ UIADD3 UR4, UR4, 0x1, URZ ;\n /*11a0*/ SHF.R.U32.HI R11, RZ, 0x2, R11 ;\n /*11b0*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ;\n /*11c0*/ ISETP.NE.AND.EX P0, PT, R11, RZ, PT, P0 ;\n /*11d0*/ @!P0 CALL.REL.NOINC `(.L_x_2) ;\n /*11e0*/ BRA `(.L_x_7) ;\n.L_x_2:\n /*11f0*/ STG.E.64 [R12.64+0x18], RZ ;\n /*1200*/ STG.E [R12.64+0x20], RZ ;\n /*1210*/ STG.E.64 [R12.64+0x28], RZ ;\n.L_x_1:\n /*1220*/ BSYNC B0 ;\n.L_x_0:\n /*1230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ;\n /*1240*/ IMAD R3, R3, c[0x0][0x0], R2 ;\n /*1250*/ IMAD.MOV.U32 R14, RZ, RZ, 0x4 ;\n /*1260*/ IMAD.SHL.U32 R3, R3, 0x20, RZ ;\n /*1270*/ IMAD.SHL.U32 R0, R2, 0x80, RZ ;\n /*1280*/ IMAD.WIDE R14, R3, R14, c[0x0][0x160] ;\n /*1290*/ LDG.E R7, [R14.64+0xc] ;\n /*12a0*/ LDG.E R6, [R14.64+0x8] ;\n /*12b0*/ LDG.E R5, [R14.64+0x4] ;\n /*12c0*/ LDG.E R4, [R14.64] ;\n /*12d0*/ LDG.E R11, [R14.64+0x1c] ;\n /*12e0*/ LDG.E R10, [R14.64+0x18] ;\n /*12f0*/ LDG.E R9, [R14.64+0x14] ;\n /*1300*/ LDG.E R8, [R14.64+0x10] ;\n /*1310*/ LDG.E R19, [R14.64+0x2c] ;\n /*1320*/ LDG.E R18, [R14.64+0x28] ;\n /*1330*/ LDG.E R17, [R14.64+0x24] ;\n /*1340*/ LDG.E R16, [R14.64+0x20] ;\n /*1350*/ LDG.E R23, [R14.64+0x3c] ;\n /*1360*/ LDG.E R22, [R14.64+0x38] ;\n /*1370*/ LDG.E R21, [R14.64+0x34] ;\n /*1380*/ LDG.E R20, [R14.64+0x30] ;\n /*1390*/ STS.128 [R0], R4 ;\n /*13a0*/ STS.128 [R0+0x10], R8 ;\n /*13b0*/ LDG.E R7, [R14.64+0x4c] ;\n /*13c0*/ LDG.E R6, [R14.64+0x48] ;\n /*13d0*/ LDG.E R5, [R14.64+0x44] ;\n /*13e0*/ STS.128 [R0+0x20], R16 ;\n /*13f0*/ LDG.E R4, [R14.64+0x40] ;\n /*1400*/ LDG.E R11, [R14.64+0x5c] ;\n /*1410*/ LDG.E R10, [R14.64+0x58] ;\n /*1420*/ STS.128 [R0+0x30], R20 ;\n /*1430*/ LDG.E R9, [R14.64+0x54] ;\n /*1440*/ LDG.E R8, [R14.64+0x50] ;\n /*1450*/ LDG.E R19, [R14.64+0x6c] ;\n /*1460*/ LDG.E R18, [R14.64+0x68] ;\n /*1470*/ LDG.E R17, [R14.64+0x64] ;\n /*1480*/ LDG.E R16, [R14.64+0x60] ;\n /*1490*/ LDG.E R23, [R14.64+0x7c] ;\n /*14a0*/ LDG.E R22, [R14.64+0x78] ;\n /*14b0*/ LDG.E R21, [R14.64+0x74] ;\n /*14c0*/ LDG.E R20, [R14.64+0x70] ;\n /*14d0*/ LOP3.LUT P0, RZ, R2, 0x10, RZ, 0xc0, !PT ;\n /*14e0*/ BSSY B0, `(.L_x_8) ;\n /*14f0*/ STS.128 [R0+0x40], R4 ;\n /*1500*/ STS.128 [R0+0x50], R8 ;\n /*1510*/ STS.128 [R0+0x60], R16 ;\n /*1520*/ STS.128 [R0+0x70], R20 ;\n /*1530*/ BAR.SYNC.DEFER_BLOCKING 0x0 ;\n /*1540*/ @P0 BRA `(.L_x_9) ;\n /*1550*/ LDG.E.64 R16, [R12.64] ;\n /*1560*/ LDG.E.64 R22, [R12.64+0x8] ;\n /*1570*/ LDG.E.64 R2, [R12.64+0x10] ;\n /*1580*/ IMAD.MOV.U32 R18, RZ, RZ, R0 ;\n /*1590*/ UMOV UR4, 0x20 ;\n /*15a0*/ IADD3 R19, R16, 0x2c3e28, RZ ;\n /*15b0*/ IMAD.MOV.U32 R20, RZ, RZ, R16 ;\n.L_x_10:\n /*15c0*/ SHF.R.U32.HI R4, RZ, 0x2, R17 ;\n /*15d0*/ IMAD.SHL.U32 R6, R3, 0x10, RZ ;\n /*15e0*/ LDS.128 R8, [R18+0x800] ;\n /*15f0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x2f800000 ;\n /*1600*/ LOP3.LUT R4, R4, R17, RZ, 0x3c, !PT ;\n /*1610*/ UIADD3 UR4, UR4, -0x8, URZ ;\n /*1620*/ SHF.R.U32.HI R17, RZ, 0x2, R2 ;\n /*1630*/ IMAD.SHL.U32 R5, R4, 0x2, RZ ;\n /*1640*/ LOP3.LUT R2, R17, R2, RZ, 0x3c, !PT ;\n /*1650*/ LOP3.LUT R5, R3, R5, R4, 0x96, !PT ;\n /*1660*/ IMAD.SHL.U32 R17, R2, 0x2, RZ ;\n /*1670*/ LOP3.LUT R27, R5, R6, RZ, 0x3c, !PT ;\n /*1680*/ SHF.R.U32.HI R5, RZ, 0x2, R22 ;\n /*1690*/ IADD3 R4, R20, 0x587c5, R27 ;\n /*16a0*/ IMAD.SHL.U32 R29, R27, 0x10, RZ ;\n /*16b0*/ LOP3.LUT R22, R5, R22, RZ, 0x3c, !PT ;\n /*16c0*/ I2FP.F32.U32 R4, R4 ;\n /*16d0*/ FFMA R4, R4, R21, 1.1641532182693481445e-10 ;\n /*16e0*/ FSETP.GEU.AND P0, PT, R4, 0.5, PT ;\n /*16f0*/ IMAD.SHL.U32 R4, R22, 0x2, RZ ;\n /*1700*/ LOP3.LUT R4, R27, R4, R22, 0x96, !PT ;\n /*1710*/ LOP3.LUT R29, R4, R29, RZ, 0x3c, !PT ;\n /*1720*/ IADD3 R4, R20, 0xb0f8a, R29 ;\n /*1730*/ IMAD.SHL.U32 R25, R29, 0x10, RZ ;\n /*1740*/ I2FP.F32.U32 R4, R4 ;\n /*1750*/ FFMA R4, R4, R21, 1.1641532182693481445e-10 ;\n /*1760*/ FSETP.GEU.AND P1, PT, R4, 0.5, PT ;\n /*1770*/ SHF.R.U32.HI R4, RZ, 0x2, R23 ;\n /*1780*/ LOP3.LUT R4, R4, R23, RZ, 0x3c, !PT ;\n /*1790*/ IMAD.SHL.U32 R5, R4, 0x2, RZ ;\n /*17a0*/ LOP3.LUT R4, R29, R5, R4, 0x96, !PT ;\n /*17b0*/ LOP3.LUT R25, R4, R25, RZ, 0x3c, !PT ;\n /*17c0*/ LOP3.LUT R2, R25.reuse, R17, R2, 0x96, !PT ;\n /*17d0*/ IMAD.SHL.U32 R17, R25, 0x10, RZ ;\n /*17e0*/ IADD3 R4, R20, 0x10974f, R25.reuse ;\n /*17f0*/ SHF.R.U32.HI R24, RZ, 0x2, R25 ;\n /*1800*/ LOP3.LUT R17, R2, R17, RZ, 0x3c, !PT ;\n /*1810*/ I2FP.F32.U32 R4, R4 ;\n /*1820*/ IADD3 R2, R20, 0x161f14, R17 ;\n /*1830*/ IMAD.SHL.U32 R22, R17, 0x10, RZ ;\n /*1840*/ LOP3.LUT R25, R24, R25, RZ, 0x3c, !PT ;\n /*1850*/ FFMA R4, R4, R21, 1.1641532182693481445e-10 ;\n /*1860*/ I2FP.F32.U32 R2, R2 ;\n /*1870*/ FSETP.GEU.AND P2, PT, R4, 0.5, PT ;\n /*1880*/ FFMA R2, R2, R21, 1.1641532182693481445e-10 ;\n /*1890*/ LDS.128 R4, [R18] ;\n /*18a0*/ FSETP.GEU.AND P3, PT, R2, 0.5, PT ;\n /*18b0*/ SHF.R.U32.HI R2, RZ, 0x2, R3 ;\n /*18c0*/ LOP3.LUT R2, R2, R3, RZ, 0x3c, !PT ;\n /*18d0*/ IMAD.SHL.U32 R3, R2, 0x2, RZ ;\n /*18e0*/ LOP3.LUT R3, R17, R3, R2, 0x96, !PT ;\n /*18f0*/ LOP3.LUT R22, R3, R22, RZ, 0x3c, !PT ;\n /*1900*/ IADD3 R2, R19, -0x10974f, R22 ;\n /*1910*/ IMAD.SHL.U32 R23, R22, 0x10, RZ ;\n /*1920*/ I2FP.F32.U32 R2, R2 ;\n /*1930*/ FFMA R2, R2, R21, 1.1641532182693481445e-10 ;\n /*1940*/ FSEL R4, R4, R8, !P0 ;\n /*1950*/ FSETP.GEU.AND P0, PT, R2, 0.5, PT ;\n /*1960*/ SHF.R.U32.HI R2, RZ, 0x2, R27 ;\n /*1970*/ FSEL R5, R5, R9, !P1 ;\n /*1980*/ LOP3.LUT R27, R2, R27, RZ, 0x3c, !PT ;\n /*1990*/ FSEL R7, R7, R11, !P3 ;\n /*19a0*/ FSEL R6, R6, R10, !P2 ;\n /*19b0*/ IMAD.SHL.U32 R2, R27, 0x2, RZ ;\n /*19c0*/ LDS.128 R8, [R18+0x810] ;\n /*19d0*/ LOP3.LUT R2, R22, R2, R27, 0x96, !PT ;\n /*19e0*/ STS.128 [R18], R4 ;\n /*19f0*/ LOP3.LUT R23, R2, R23, RZ, 0x3c, !PT ;\n /*1a00*/ IADD3 R2, R19, -0xb0f8a, R23 ;\n /*1a10*/ I2FP.F32.U32 R2, R2 ;\n /*1a20*/ FFMA R2, R2, R21, 1.1641532182693481445e-10 ;\n /*1a30*/ FSETP.GEU.AND P1, PT, R2, 0.5, PT ;\n /*1a40*/ SHF.R.U32.HI R2, RZ, 0x2, R29 ;\n /*1a50*/ LOP3.LUT R2, R2, R29, RZ, 0x3c, !PT ;\n /*1a60*/ IMAD.SHL.U32 R3, R2, 0x2, RZ ;\n /*1a70*/ LOP3.LUT R3, R23.reuse, R3, R2, 0x96, !PT ;\n /*1a80*/ IMAD.SHL.U32 R2, R23, 0x10, RZ ;\n /*1a90*/ LOP3.LUT R2, R3, R2, RZ, 0x3c, !PT ;\n /*1aa0*/ IADD3 R3, R19, -0x587c5, R2 ;\n /*1ab0*/ I2FP.F32.U32 R4, R3 ;\n /*1ac0*/ IMAD.SHL.U32 R3, R25, 0x2, RZ ;\n /*1ad0*/ FFMA R4, R4, R21, 1.1641532182693481445e-10 ;\n /*1ae0*/ LOP3.LUT R24, R2.reuse, R3, R25, 0x96, !PT ;\n /*1af0*/ IMAD.SHL.U32 R3, R2, 0x10, RZ ;\n /*1b00*/ FSETP.GEU.AND P2, PT, R4, 0.5, PT ;\n /*1b10*/ LDS.128 R4, [R18+0x10] ;\n /*1b20*/ LOP3.LUT R3, R24, R3, RZ, 0x3c, !PT ;\n /*1b30*/ IMAD.IADD R19, R3, 0x1, R19 ;\n /*1b40*/ I2FP.F32.U32 R24, R19 ;\n /*1b50*/ IADD3 R19, R20, 0x587c50, RZ ;\n /*1b60*/ FFMA R24, R24, R21, 1.1641532182693481445e-10 ;\n /*1b70*/ FSETP.GEU.AND P3, PT, R24, 0.5, PT ;\n /*1b80*/ FSEL R4, R4, R8, !P0 ;\n /*1b90*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ;\n /*1ba0*/ FSEL R7, R7, R11, !P3 ;\n /*1bb0*/ FSEL R6, R6, R10, !P2 ;\n /*1bc0*/ FSEL R5, R5, R9, !P1 ;\n /*1bd0*/ IADD3 R8, R20, 0x2c3e28, RZ ;\n /*1be0*/ STS.128 [R18+0x10], R4 ;\n /*1bf0*/ IMAD.MOV.U32 R20, RZ, RZ, R8 ;\n /*1c00*/ IADD3 R18, R18, 0x20, RZ ;\n /*1c10*/ @P0 BRA `(.L_x_10) ;\n /*1c20*/ IADD3 R16, R16, 0xb0f8a0, RZ ;\n /*1c30*/ STG.E.64 [R12.64+0x8], R22 ;\n /*1c40*/ STG.E.64 [R12.64+0x10], R2 ;\n /*1c50*/ STG.E.64 [R12.64], R16 ;\n.L_x_9:\n /*1c60*/ BSYNC B0 ;\n.L_x_8:\n /*1c70*/ BAR.SYNC.DEFER_BLOCKING 0x0 ;\n /*1c80*/ LDG.E.64 R2, [R12.64] ;\n /*1c90*/ LDG.E.64 R4, [R12.64+0x8] ;\n /*1ca0*/ LDG.E.64 R6, [R12.64+0x10] ;\n /*1cb0*/ IADD3 R8, R0, 0x8, RZ ;\n /*1cc0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ;\n.L_x_15:\n /*1cd0*/ SHF.R.U32.HI R10, RZ, 0x2, R3 ;\n /*1ce0*/ IMAD.SHL.U32 R11, R7, 0x10, RZ ;\n /*1cf0*/ IADD3 R9, R9, 0x10, RZ ;\n /*1d00*/ IMAD.MOV.U32 R16, RZ, RZ, R6 ;\n /*1d10*/ LOP3.LUT R10, R10, R3, RZ, 0x3c, !PT ;\n /*1d20*/ IMAD.MOV.U32 R17, RZ, RZ, R5 ;\n /*1d30*/ ISETP.NE.AND P0, PT, R9, 0x88, PT ;\n /*1d40*/ IMAD.SHL.U32 R3, R10, 0x2, RZ ;\n /*1d50*/ LOP3.LUT R10, R7, R3, R10, 0x96, !PT ;\n /*1d60*/ IADD3 R3, R2, 0x587c5, RZ ;\n /*1d70*/ LOP3.LUT R18, R10, R11, RZ, 0x3c, !PT ;\n /*1d80*/ IMAD.MOV.U32 R11, RZ, RZ, 0x2f800000 ;\n /*1d90*/ IMAD.IADD R10, R18, 0x1, R3 ;\n /*1da0*/ I2FP.F32.U32 R10, R10 ;\n /*1db0*/ FFMA R10, R10, R11, 1.1641532182693481445e-10 ;\n /*1dc0*/ IMAD.MOV.U32 R11, RZ, RZ, R7 ;\n /*1dd0*/ FSETP.GEU.AND P1, PT, R10, 0.0099999997764825820923, PT ;\n /*1de0*/ IMAD.MOV.U32 R10, RZ, RZ, R18 ;\n /*1df0*/ @P1 BRA `(.L_x_11) ;\n /*1e00*/ SHF.R.U32.HI R3, RZ, 0x2, R4 ;\n /*1e10*/ IMAD.SHL.U32 R11, R18, 0x10, RZ ;\n /*1e20*/ IMAD.MOV.U32 R19, RZ, RZ, 0x2f800000 ;\n /*1e30*/ LOP3.LUT R3, R3, R4, RZ, 0x3c, !PT ;\n /*1e40*/ IMAD.MOV.U32 R16, RZ, RZ, R7 ;\n /*1e50*/ IMAD.MOV.U32 R17, RZ, RZ, R6 ;\n /*1e60*/ IMAD.SHL.U32 R4, R3, 0x2, RZ ;\n /*1e70*/ LOP3.LUT R4, R18, R4, R3, 0x96, !PT ;\n /*1e80*/ IADD3 R3, R2, 0xb0f8a, RZ ;\n /*1e90*/ LOP3.LUT R10, R4, R11, RZ, 0x3c, !PT ;\n /*1ea0*/ IMAD.MOV.U32 R11, RZ, RZ, R18 ;\n /*1eb0*/ IMAD.MOV.U32 R4, RZ, RZ, R5 ;\n /*1ec0*/ IMAD.IADD R2, R10, 0x1, R3 ;\n /*1ed0*/ I2FP.F32.U32 R2, R2 ;\n /*1ee0*/ FFMA R19, R2, R19, 1.1641532182693481445e-10 ;\n /*1ef0*/ STS [R8+-0x8], R19 ;\n.L_x_11:\n /*1f00*/ SHF.R.U32.HI R5, RZ, 0x2, R4 ;\n /*1f10*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ;\n /*1f20*/ IMAD.MOV.U32 R7, RZ, RZ, R16 ;\n /*1f30*/ LOP3.LUT R5, R5, R4, RZ, 0x3c, !PT ;\n /*1f40*/ IMAD.SHL.U32 R4, R10, 0x10, RZ ;\n /*1f50*/ IMAD.SHL.U32 R2, R5, 0x2, RZ ;\n /*1f60*/ LOP3.LUT R5, R10, R2, R5, 0x96, !PT ;\n /*1f70*/ IADD3 R2, R3, 0x587c5, RZ ;\n /*1f80*/ LOP3.LUT R19, R5, R4, RZ, 0x3c, !PT ;\n /*1f90*/ IMAD.MOV.U32 R5, RZ, RZ, 0x2f800000 ;\n /*1fa0*/ IMAD.IADD R4, R19, 0x1, R2 ;\n /*1fb0*/ I2FP.F32.U32 R4, R4 ;\n /*1fc0*/ FFMA R4, R4, R5, 1.1641532182693481445e-10 ;\n /*1fd0*/ IMAD.MOV.U32 R5, RZ, RZ, R19 ;\n /*1fe0*/ FSETP.GEU.AND P1, PT, R4, 0.0099999997764825820923, PT ;\n /*1ff0*/ IMAD.MOV.U32 R4, RZ, RZ, R11 ;\n /*2000*/ @P1 BRA `(.L_x_12) ;\n /*2010*/ SHF.R.U32.HI R2, RZ, 0x2, R17 ;\n /*2020*/ IMAD.SHL.U32 R4, R19, 0x10, RZ ;\n /*2030*/ IMAD.MOV.U32 R6, RZ, RZ, R19 ;\n /*2040*/ LOP3.LUT R2, R2, R17, RZ, 0x3c, !PT ;\n /*2050*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ;\n /*2060*/ IMAD.MOV.U32 R17, RZ, RZ, R16 ;\n /*2070*/ IMAD.SHL.U32 R5, R2, 0x2, RZ ;\n /*2080*/ LOP3.LUT R5, R19, R5, R2, 0x96, !PT ;\n /*2090*/ IADD3 R2, R3, 0xb0f8a, RZ ;\n /*20a0*/ LOP3.LUT R5, R5, R4, RZ, 0x3c, !PT ;\n /*20b0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x2f800000 ;\n /*20c0*/ IMAD.IADD R3, R5, 0x1, R2 ;\n /*20d0*/ I2FP.F32.U32 R3, R3 ;\n /*20e0*/ FFMA R3, R3, R4, 1.1641532182693481445e-10 ;\n /*20f0*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ;\n /*2100*/ STS [R8+-0x4], R3 ;\n.L_x_12:\n /*2110*/ SHF.R.U32.HI R10, RZ, 0x2, R17 ;\n /*2120*/ IMAD.SHL.U32 R16, R5, 0x10, RZ ;\n /*2130*/ LOP3.LUT R10, R10, R17, RZ, 0x3c, !PT ;\n /*2140*/ IMAD.MOV.U32 R17, RZ, RZ, R5 ;\n /*2150*/ IMAD.SHL.U32 R3, R10, 0x2, RZ ;\n /*2160*/ LOP3.LUT R3, R5, R3, R10, 0x96, !PT ;\n /*2170*/ IADD3 R10, R2, 0x587c5, RZ ;\n /*2180*/ LOP3.LUT R21, R3, R16, RZ, 0x3c, !PT ;\n /*2190*/ IMAD.MOV.U32 R16, RZ, RZ, 0x2f800000 ;\n /*21a0*/ IMAD.IADD R3, R21, 0x1, R10 ;\n /*21b0*/ IMAD.MOV.U32 R11, RZ, RZ, R21 ;\n /*21c0*/ I2FP.F32.U32 R3, R3 ;\n /*21d0*/ FFMA R3, R3, R16, 1.1641532182693481445e-10 ;\n /*21e0*/ IMAD.MOV.U32 R16, RZ, RZ, R6 ;\n /*21f0*/ FSETP.GEU.AND P1, PT, R3, 0.0099999997764825820923, PT ;\n /*2200*/ IMAD.MOV.U32 R3, RZ, RZ, R4 ;\n /*2210*/ @P1 BRA `(.L_x_13) ;\n /*2220*/ SHF.R.U32.HI R10, RZ, 0x2, R7 ;\n /*2230*/ IMAD.SHL.U32 R16, R21, 0x10, RZ ;\n /*2240*/ IMAD.MOV.U32 R19, RZ, RZ, 0x2f800000 ;\n /*2250*/ LOP3.LUT R10, R10, R7, RZ, 0x3c, !PT ;\n /*2260*/ IMAD.MOV.U32 R17, RZ, RZ, R21 ;\n /*2270*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ;\n /*2280*/ IMAD.SHL.U32 R3, R10, 0x2, RZ ;\n /*2290*/ LOP3.LUT R3, R21, R3, R10, 0x96, !PT ;\n /*22a0*/ IADD3 R10, R2, 0xb0f8a, RZ ;\n /*22b0*/ LOP3.LUT R11, R3, R16, RZ, 0x3c, !PT ;\n /*22c0*/ IMAD.MOV.U32 R16, RZ, RZ, R5 ;\n /*22d0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ;\n /*22e0*/ IMAD.IADD R2, R11, 0x1, R10 ;\n /*22f0*/ I2FP.F32.U32 R2, R2 ;\n /*2300*/ FFMA R19, R2, R19, 1.1641532182693481445e-10 ;\n /*2310*/ STS [R8], R19 ;\n.L_x_13:\n /*2320*/ SHF.R.U32.HI R2, RZ, 0x2, R7 ;\n /*2330*/ IMAD.SHL.U32 R5, R11, 0x10, RZ ;\n /*2340*/ IMAD.MOV.U32 R6, RZ, RZ, R11 ;\n /*2350*/ LOP3.LUT R2, R2, R7, RZ, 0x3c, !PT ;\n /*2360*/ IMAD.SHL.U32 R4, R2, 0x2, RZ ;\n /*2370*/ LOP3.LUT R4, R11, R4, R2, 0x96, !PT ;\n /*2380*/ IADD3 R2, R10, 0x587c5, RZ ;\n /*2390*/ LOP3.LUT R21, R4, R5, RZ, 0x3c, !PT ;\n /*23a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x2f800000 ;\n /*23b0*/ IMAD.IADD R4, R21, 0x1, R2 ;\n /*23c0*/ IMAD.MOV.U32 R7, RZ, RZ, R21 ;\n /*23d0*/ I2FP.F32.U32 R4, R4 ;\n /*23e0*/ FFMA R4, R4, R5, 1.1641532182693481445e-10 ;\n /*23f0*/ IMAD.MOV.U32 R5, RZ, RZ, R17 ;\n /*2400*/ FSETP.GEU.AND P1, PT, R4, 0.0099999997764825820923, PT ;\n /*2410*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ;\n /*2420*/ @P1 BRA `(.L_x_14) ;\n /*2430*/ SHF.R.U32.HI R2, RZ, 0x2, R3 ;\n /*2440*/ IMAD.SHL.U32 R4, R21, 0x10, RZ ;\n /*2450*/ IMAD.MOV.U32 R6, RZ, RZ, R21 ;\n /*2460*/ LOP3.LUT R2, R2, R3, RZ, 0x3c, !PT ;\n /*2470*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ;\n /*2480*/ IMAD.SHL.U32 R3, R2, 0x2, RZ ;\n /*2490*/ LOP3.LUT R3, R21, R3, R2, 0x96, !PT ;\n /*24a0*/ IADD3 R2, R10, 0xb0f8a, RZ ;\n /*24b0*/ LOP3.LUT R7, R3, R4, RZ, 0x3c, !PT ;\n /*24c0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x2f800000 ;\n /*24d0*/ IMAD.IADD R3, R7, 0x1, R2 ;\n /*24e0*/ I2FP.F32.U32 R3, R3 ;\n /*24f0*/ FFMA R19, R3, R4, 1.1641532182693481445e-10 ;\n /*2500*/ IMAD.MOV.U32 R4, RZ, RZ, R17 ;\n /*2510*/ IMAD.MOV.U32 R3, RZ, RZ, R16 ;\n /*2520*/ STS [R8+0x4], R19 ;\n.L_x_14:\n /*2530*/ IADD3 R8, R8, 0x10, RZ ;\n /*2540*/ @P0 BRA `(.L_x_15) ;\n /*2550*/ STG.E.64 [R12.64+0x8], R4 ;\n /*2560*/ STG.E.64 [R12.64+0x10], R6 ;\n /*2570*/ STG.E.64 [R12.64], R2 ;\n /*2580*/ BAR.SYNC.DEFER_BLOCKING 0x0 ;\n /*2590*/ LDS.128 R8, [R0] ;\n /*25a0*/ LDS.128 R16, [R0+0x10] ;\n /*25b0*/ LDS.128 R20, [R0+0x20] ;\n /*25c0*/ LDS.128 R4, [R0+0x30] ;\n /*25d0*/ LDS.128 R24, [R0+0x40] ;\n /*25e0*/ LDS.128 R28, [R0+0x60] ;\n /*25f0*/ LDS.128 R32, [R0+0x70] ;\n /*2600*/ STG.E [R14.64], R8 ;\n /*2610*/ STG.E [R14.64+0x4], R9 ;\n /*2620*/ STG.E [R14.64+0x8], R10 ;\n /*2630*/ STG.E [R14.64+0xc], R11 ;\n /*2640*/ LDS.128 R8, [R0+0x50] ;\n /*2650*/ STG.E [R14.64+0x10], R16 ;\n /*2660*/ STG.E [R14.64+0x14], R17 ;\n /*2670*/ STG.E [R14.64+0x18], R18 ;\n /*2680*/ STG.E [R14.64+0x1c], R19 ;\n /*2690*/ STG.E [R14.64+0x20], R20 ;\n /*26a0*/ STG.E [R14.64+0x24], R21 ;\n /*26b0*/ STG.E [R14.64+0x28], R22 ;\n /*26c0*/ STG.E [R14.64+0x2c], R23 ;\n /*26d0*/ STG.E [R14.64+0x30], R4 ;\n /*26e0*/ STG.E [R14.64+0x34], R5 ;\n /*26f0*/ STG.E [R14.64+0x38], R6 ;\n /*2700*/ STG.E [R14.64+0x3c], R7 ;\n /*2710*/ STG.E [R14.64+0x40], R24 ;\n /*2720*/ STG.E [R14.64+0x44], R25 ;\n /*2730*/ STG.E [R14.64+0x48], R26 ;\n /*2740*/ STG.E [R14.64+0x4c], R27 ;\n /*2750*/ STG.E [R14.64+0x50], R8 ;\n /*2760*/ STG.E [R14.64+0x54], R9 ;\n /*2770*/ STG.E [R14.64+0x58], R10 ;\n /*2780*/ STG.E [R14.64+0x5c], R11 ;\n /*2790*/ STG.E [R14.64+0x60], R28 ;\n /*27a0*/ STG.E [R14.64+0x64], R29 ;\n /*27b0*/ STG.E [R14.64+0x68], R30 ;\n /*27c0*/ STG.E [R14.64+0x6c], R31 ;\n /*27d0*/ STG.E [R14.64+0x70], R32 ;\n /*27e0*/ STG.E [R14.64+0x74], R33 ;\n /*27f0*/ STG.E [R14.64+0x78], R34 ;\n /*2800*/ STG.E [R14.64+0x7c], R35 ;\n /*2810*/ EXIT ;\n.L_x_16:\n /*2820*/ BRA `(.L_x_16);\n /*2830*/ NOP;\n /*2840*/ NOP;\n /*2850*/ NOP;\n /*2860*/ NOP;\n /*2870*/ NOP;\n /*2880*/ NOP;\n /*2890*/ NOP;\n /*28a0*/ NOP;\n /*28b0*/ NOP;\n /*28c0*/ NOP;\n /*28d0*/ NOP;\n /*28e0*/ NOP;\n /*28f0*/ NOP;\n.L_x_17:\n"},"hip":{"kind":"string","value":"\t.text\n\t.file\t\"cuda_code_081750.hip\"\n\t.globl\t_Z37__device_stub__geneticAlgorithmKernelPfS_P12hiprandState # -- Begin function _Z37__device_stub__geneticAlgorithmKernelPfS_P12hiprandState\n\t.p2align\t4, 0x90\n\t.type\t_Z37__device_stub__geneticAlgorithmKernelPfS_P12hiprandState,@function\n_Z37__device_stub__geneticAlgorithmKernelPfS_P12hiprandState: # @_Z37__device_stub__geneticAlgorithmKernelPfS_P12hiprandState\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$104, %rsp\n\t.cfi_def_cfa_offset 112\n\tmovq\t%rdi, 72(%rsp)\n\tmovq\t%rsi, 64(%rsp)\n\tmovq\t%rdx, 56(%rsp)\n\tleaq\t72(%rsp), %rax\n\tmovq\t%rax, 80(%rsp)\n\tleaq\t64(%rsp), %rax\n\tmovq\t%rax, 88(%rsp)\n\tleaq\t56(%rsp), %rax\n\tmovq\t%rax, 96(%rsp)\n\tleaq\t40(%rsp), %rdi\n\tleaq\t24(%rsp), %rsi\n\tleaq\t16(%rsp), %rdx\n\tleaq\t8(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t40(%rsp), %rsi\n\tmovl\t48(%rsp), %edx\n\tmovq\t24(%rsp), %rcx\n\tmovl\t32(%rsp), %r8d\n\tleaq\t80(%rsp), %r9\n\tmovl\t$_Z22geneticAlgorithmKernelPfS_P12hiprandState, %edi\n\tpushq\t8(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t24(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$120, %rsp\n\t.cfi_adjust_cfa_offset -120\n\tretq\n.Lfunc_end0:\n\t.size\t_Z37__device_stub__geneticAlgorithmKernelPfS_P12hiprandState, .Lfunc_end0-_Z37__device_stub__geneticAlgorithmKernelPfS_P12hiprandState\n\t.cfi_endproc\n # -- End function\n\t.section\t.rodata.cst4,\"aM\",@progbits,4\n\t.p2align\t2, 0x0 # -- Begin function main\n.LCPI1_0:\n\t.long\t0x30000000 # float 4.65661287E-10\n\t.text\n\t.globl\tmain\n\t.p2align\t4, 0x90\n\t.type\tmain,@function\nmain: # @main\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rbp\n\t.cfi_def_cfa_offset 16\n\tpushq\t%r14\n\t.cfi_def_cfa_offset 24\n\tpushq\t%rbx\n\t.cfi_def_cfa_offset 32\n\tsubq\t$128, %rsp\n\t.cfi_def_cfa_offset 160\n\t.cfi_offset %rbx, -32\n\t.cfi_offset %r14, -24\n\t.cfi_offset %rbp, -16\n\tmovl\t$2097152, %edi # imm = 0x200000\n\tcallq\tmalloc\n\tmovq\t%rax, %rbx\n\tmovq\t%rsp, %rdi\n\tmovl\t$2097152, %esi # imm = 0x200000\n\tcallq\thipMalloc\n\tleaq\t16(%rsp), %rdi\n\tmovl\t$65536, %esi # imm = 0x10000\n\tcallq\thipMalloc\n\tleaq\t8(%rsp), %rdi\n\tmovl\t$24576, %esi # imm = 0x6000\n\tcallq\thipMalloc\n\txorl\t%r14d, %r14d\n\t.p2align\t4, 0x90\n.LBB1_1: # =>This Inner Loop Header: Depth=1\n\tcallq\trand\n\txorps\t%xmm0, %xmm0\n\tcvtsi2ss\t%eax, %xmm0\n\tmulss\t.LCPI1_0(%rip), %xmm0\n\tmovss\t%xmm0, (%rbx,%r14,4)\n\tincq\t%r14\n\tcmpq\t$524288, %r14 # imm = 0x80000\n\tjne\t.LBB1_1\n# %bb.2:\n\tmovq\t(%rsp), %rdi\n\tmovl\t$2097152, %edx # imm = 0x200000\n\tmovq\t%rbx, %rsi\n\tmovl\t$1, %ecx\n\tcallq\thipMemcpy\n\tmovabsq\t$4294967328, %rdx # imm = 0x100000020\n\tleaq\t480(%rdx), %rdi\n\tmovl\t$4096, %r8d # imm = 0x1000\n\tmovl\t$1, %esi\n\tmovl\t$1, %ecx\n\txorl\t%r9d, %r9d\n\tcallq\t__hipPushCallConfiguration\n\ttestl\t%eax, %eax\n\tjne\t.LBB1_4\n# %bb.3:\n\tmovq\t(%rsp), %rax\n\tmovq\t16(%rsp), %rcx\n\tmovq\t8(%rsp), %rdx\n\tmovq\t%rax, 88(%rsp)\n\tmovq\t%rcx, 80(%rsp)\n\tmovq\t%rdx, 72(%rsp)\n\tleaq\t88(%rsp), %rax\n\tmovq\t%rax, 96(%rsp)\n\tleaq\t80(%rsp), %rax\n\tmovq\t%rax, 104(%rsp)\n\tleaq\t72(%rsp), %rax\n\tmovq\t%rax, 112(%rsp)\n\tleaq\t56(%rsp), %rdi\n\tleaq\t40(%rsp), %rsi\n\tleaq\t32(%rsp), %rdx\n\tleaq\t24(%rsp), %rcx\n\tcallq\t__hipPopCallConfiguration\n\tmovq\t56(%rsp), %rsi\n\tmovl\t64(%rsp), %edx\n\tmovq\t40(%rsp), %rcx\n\tmovl\t48(%rsp), %r8d\n\tleaq\t96(%rsp), %r9\n\tmovl\t$_Z22geneticAlgorithmKernelPfS_P12hiprandState, %edi\n\tpushq\t24(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tpushq\t40(%rsp)\n\t.cfi_adjust_cfa_offset 8\n\tcallq\thipLaunchKernel\n\taddq\t$16, %rsp\n\t.cfi_adjust_cfa_offset -16\n.LBB1_4:\n\tcallq\thipGetLastError\n\ttestl\t%eax, %eax\n\tje\t.LBB1_13\n# %bb.5:\n\tmovl\t%eax, %ebp\n\tmovl\t$_ZSt4cerr, %edi\n\tmovl\t$.L.str, %esi\n\tmovl\t$12, %edx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n\tmovl\t%ebp, %edi\n\tcallq\thipGetErrorString\n\ttestq\t%rax, %rax\n\tje\t.LBB1_6\n# %bb.7:\n\tmovq\t%rax, %rdi\n\tmovq\t%rax, %rbx\n\tcallq\tstrlen\n\tmovl\t$_ZSt4cerr, %edi\n\tmovq\t%rbx, %rsi\n\tmovq\t%rax, %rdx\n\tcallq\t_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l\n\tjmp\t.LBB1_8\n.LBB1_13:\n\tmovq\t(%rsp), %rsi\n\tmovl\t$2097152, %edx # imm = 0x200000\n\tmovq\t%rbx, %rdi\n\tmovl\t$2, %ecx\n\tcallq\thipMemcpy\n\tmovq\t(%rsp), %rdi\n\tcallq\thipFree\n\tmovq\t16(%rsp), %rdi\n\tcallq\thipFree\n\tmovq\t8(%rsp), %rdi\n\tcallq\thipFree\n\tmovq\t%rbx, %rdi\n\tcallq\tfree\n\txorl\t%eax, %eax\n\tjmp\t.LBB1_14\n.LBB1_6:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tleaq\t_ZSt4cerr(%rax), %rdi\n\tmovl\t_ZSt4cerr+32(%rax), %esi\n\torl\t$1, %esi\n\tcallq\t_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate\n.LBB1_8:\n\tmovq\t_ZSt4cerr(%rip), %rax\n\tmovq\t-24(%rax), %rax\n\tmovq\t_ZSt4cerr+240(%rax), %rbx\n\ttestq\t%rbx, %rbx\n\tje\t.LBB1_15\n# %bb.9:\n\tcmpb\t$0, 56(%rbx)\n\tje\t.LBB1_11\n# %bb.10:\n\tmovzbl\t67(%rbx), %eax\n\tjmp\t.LBB1_12\n.LBB1_11:\n\tmovq\t%rbx, %rdi\n\tcallq\t_ZNKSt5ctypeIcE13_M_widen_initEv\n\tmovq\t(%rbx), %rax\n\tmovq\t%rbx, %rdi\n\tmovl\t$10, %esi\n\tcallq\t*48(%rax)\n.LBB1_12:\n\tmovsbl\t%al, %esi\n\tmovl\t$_ZSt4cerr, %edi\n\tcallq\t_ZNSo3putEc\n\tmovq\t%rax, %rdi\n\tcallq\t_ZNSo5flushEv\n\tmovl\t$-1, %eax\n.LBB1_14:\n\taddq\t$128, %rsp\n\t.cfi_def_cfa_offset 32\n\tpopq\t%rbx\n\t.cfi_def_cfa_offset 24\n\tpopq\t%r14\n\t.cfi_def_cfa_offset 16\n\tpopq\t%rbp\n\t.cfi_def_cfa_offset 8\n\tretq\n.LBB1_15:\n\t.cfi_def_cfa_offset 160\n\tcallq\t_ZSt16__throw_bad_castv\n.Lfunc_end1:\n\t.size\tmain, .Lfunc_end1-main\n\t.cfi_endproc\n # -- End function\n\t.section\t.text.startup,\"ax\",@progbits\n\t.p2align\t4, 0x90 # -- Begin function _GLOBAL__sub_I_cuda_code_081750.hip\n\t.type\t_GLOBAL__sub_I_cuda_code_081750.hip,@function\n_GLOBAL__sub_I_cuda_code_081750.hip: # @_GLOBAL__sub_I_cuda_code_081750.hip\n\t.cfi_startproc\n# %bb.0:\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 16\n\tmovl\t$_ZStL8__ioinit, %edi\n\tcallq\t_ZNSt8ios_base4InitC1Ev\n\tmovl\t$_ZNSt8ios_base4InitD1Ev, %edi\n\tmovl\t$_ZStL8__ioinit, %esi\n\tmovl\t$__dso_handle, %edx\n\tpopq\t%rax\n\t.cfi_def_cfa_offset 8\n\tjmp\t__cxa_atexit # TAILCALL\n.Lfunc_end2:\n\t.size\t_GLOBAL__sub_I_cuda_code_081750.hip, .Lfunc_end2-_GLOBAL__sub_I_cuda_code_081750.hip\n\t.cfi_endproc\n # -- End function\n\t.text\n\t.p2align\t4, 0x90 # -- Begin function __hip_module_ctor\n\t.type\t__hip_module_ctor,@function\n__hip_module_ctor: # @__hip_module_ctor\n\t.cfi_startproc\n# %bb.0:\n\tsubq\t$40, %rsp\n\t.cfi_def_cfa_offset 48\n\tmovq\t__hip_gpubin_handle(%rip), %rdi\n\ttestq\t%rdi, %rdi\n\tjne\t.LBB3_2\n# %bb.1:\n\tmovl\t$__hip_fatbin_wrapper, %edi\n\tcallq\t__hipRegisterFatBinary\n\tmovq\t%rax, %rdi\n\tmovq\t%rax, __hip_gpubin_handle(%rip)\n.LBB3_2:\n\txorps\t%xmm0, %xmm0\n\tmovups\t%xmm0, 16(%rsp)\n\tmovups\t%xmm0, (%rsp)\n\tmovl\t$_Z22geneticAlgorithmKernelPfS_P12hiprandState, %esi\n\tmovl\t$.L__unnamed_1, %edx\n\tmovl\t$.L__unnamed_1, %ecx\n\tmovl\t$-1, %r8d\n\txorl\t%r9d, %r9d\n\tcallq\t__hipRegisterFunction\n\tmovl\t$__hip_module_dtor, %edi\n\taddq\t$40, %rsp\n\t.cfi_def_cfa_offset 8\n\tjmp\tatexit # TAILCALL\n.Lfunc_end3:\n\t.size\t__hip_module_ctor, .Lfunc_end3-__hip_module_ctor\n\t.cfi_endproc\n # -- End function\n\t.p2align\t4, 0x90 # -- Begin function __hip_module_dtor\n\t.type\t__hip_module_dtor,@function\n__hip_module_dtor: # @__hip_module_dtor\n\t.cfi_startproc\n# %bb.0:\n\tmovq\t__hip_gpubin_handle(%rip), %rdi\n\ttestq\t%rdi, %rdi\n\tje\t.LBB4_2\n# %bb.1:\n\tpushq\t%rax\n\t.cfi_def_cfa_offset 16\n\tcallq\t__hipUnregisterFatBinary\n\tmovq\t$0, __hip_gpubin_handle(%rip)\n\taddq\t$8, %rsp\n\t.cfi_def_cfa_offset 8\n.LBB4_2:\n\tretq\n.Lfunc_end4:\n\t.size\t__hip_module_dtor, .Lfunc_end4-__hip_module_dtor\n\t.cfi_endproc\n # -- End function\n\t.type\t_ZStL8__ioinit,@object # @_ZStL8__ioinit\n\t.local\t_ZStL8__ioinit\n\t.comm\t_ZStL8__ioinit,1,1\n\t.hidden\t__dso_handle\n\t.type\t_Z22geneticAlgorithmKernelPfS_P12hiprandState,@object # @_Z22geneticAlgorithmKernelPfS_P12hiprandState\n\t.section\t.rodata,\"a\",@progbits\n\t.globl\t_Z22geneticAlgorithmKernelPfS_P12hiprandState\n\t.p2align\t3, 0x0\n_Z22geneticAlgorithmKernelPfS_P12hiprandState:\n\t.quad\t_Z37__device_stub__geneticAlgorithmKernelPfS_P12hiprandState\n\t.size\t_Z22geneticAlgorithmKernelPfS_P12hiprandState, 8\n\n\t.type\t.L.str,@object # @.str\n\t.section\t.rodata.str1.1,\"aMS\",@progbits,1\n.L.str:\n\t.asciz\t\"CUDA error: \"\n\t.size\t.L.str, 13\n\n\t.type\t.L__unnamed_1,@object # @0\n.L__unnamed_1:\n\t.asciz\t\"_Z22geneticAlgorithmKernelPfS_P12hiprandState\"\n\t.size\t.L__unnamed_1, 46\n\n\t.type\t__hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper\n\t.section\t.hipFatBinSegment,\"a\",@progbits\n\t.p2align\t3, 0x0\n__hip_fatbin_wrapper:\n\t.long\t1212764230 # 0x48495046\n\t.long\t1 # 0x1\n\t.quad\t__hip_fatbin\n\t.quad\t0\n\t.size\t__hip_fatbin_wrapper, 24\n\n\t.type\t__hip_gpubin_handle,@object # @__hip_gpubin_handle\n\t.local\t__hip_gpubin_handle\n\t.comm\t__hip_gpubin_handle,8,8\n\t.section\t.init_array,\"aw\",@init_array\n\t.p2align\t3, 0x0\n\t.quad\t_GLOBAL__sub_I_cuda_code_081750.hip\n\t.quad\t__hip_module_ctor\n\t.type\t__hip_cuid_,@object # @__hip_cuid_\n\t.bss\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 # 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n"}}},{"rowIdx":162593,"cells":{"id":{"kind":"string","value":"d739db9be0c36f471f93c988cc7c4ac24e4bff5d_O0"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z28PossionImageCloningIterationPKfS0_PfS1_iii --------------------------\n .section .text._Z28PossionImageCloningIterationPKfS0_PfS1_iii,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=27\"\n .align 128\n\n\n\n\n .global _Z28PossionImageCloningIterationPKfS0_PfS1_iii\n .type _Z28PossionImageCloningIterationPKfS0_PfS1_iii,@function\n .size _Z28PossionImageCloningIterationPKfS0_PfS1_iii,(.L_x_61 - _Z28PossionImageCloningIterationPKfS0_PfS1_iii)\n .other _Z28PossionImageCloningIterationPKfS0_PfS1_iii,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z28PossionImageCloningIterationPKfS0_PfS1_iii:\n.text._Z28PossionImageCloningIterationPKfS0_PfS1_iii:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ MOV R14, c[0x0][0x118] ;\n /*0020*/ MOV R15, c[0x0][0x11c] ;\n /*0030*/ MOV R2, 0x8 ;\n /*0040*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0050*/ MOV R9, R2 ;\n /*0060*/ MOV R10, R3 ;\n /*0070*/ MOV R9, R9 ;\n /*0080*/ MOV R10, R10 ;\n /*0090*/ MOV R2, 0x10 ;\n /*00a0*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*00b0*/ MOV R11, R2 ;\n /*00c0*/ MOV R12, R3 ;\n /*00d0*/ MOV R11, R11 ;\n /*00e0*/ MOV R12, R12 ;\n /*00f0*/ MOV R0, 0x20 ;\n /*0100*/ LDC R0, c[0x0][R0+0x160] ;\n /*0110*/ MOV R0, R0 ;\n /*0120*/ MOV R2, 0x24 ;\n /*0130*/ LDC R2, c[0x0][R2+0x160] ;\n /*0140*/ MOV R2, R2 ;\n /*0150*/ MOV R11, R11 ;\n /*0160*/ MOV R12, R12 ;\n /*0170*/ MOV R9, R9 ;\n /*0180*/ MOV R10, R10 ;\n /*0190*/ MOV R3, c[0x0][0x4] ;\n /*01a0*/ S2R R4, SR_CTAID.Y ;\n /*01b0*/ MOV R4, R4 ;\n /*01c0*/ S2R R5, SR_TID.Y ;\n /*01d0*/ MOV R5, R5 ;\n /*01e0*/ IMAD R5, R4, R3, R5 ;\n /*01f0*/ MOV R3, c[0x0][0x0] ;\n /*0200*/ S2R R4, SR_CTAID.X ;\n /*0210*/ MOV R4, R4 ;\n /*0220*/ S2R R6, SR_TID.X ;\n /*0230*/ MOV R6, R6 ;\n /*0240*/ IMAD R6, R4, R3, R6 ;\n /*0250*/ IMAD R7, R5, R0, RZ ;\n /*0260*/ IADD3 R8, R7, R6, RZ ;\n /*0270*/ ISETP.GE.AND P0, PT, R5, R2, PT ;\n /*0280*/ ISETP.GE.AND P1, PT, R6, R0, PT ;\n /*0290*/ PLOP3.LUT P0, PT, P1, P0, PT, 0xa8, 0x0 ;\n /*02a0*/ MOV R0, R11 ;\n /*02b0*/ MOV R4, R12 ;\n /*02c0*/ MOV R3, R9 ;\n /*02d0*/ MOV R2, R10 ;\n /*02e0*/ MOV R5, R5 ;\n /*02f0*/ MOV R6, R6 ;\n /*0300*/ MOV R7, R7 ;\n /*0310*/ MOV R8, R8 ;\n /*0320*/ @P0 BRA `(.L_x_0) ;\n /*0330*/ IMAD.WIDE R8, R8, 0x4, RZ ;\n /*0340*/ MOV R10, R8 ;\n /*0350*/ MOV R12, R9 ;\n /*0360*/ IADD3 R10, P0, R3, R10, RZ ;\n /*0370*/ IADD3.X R12, R2, R12, RZ, P0, !PT ;\n /*0380*/ MOV R8, R10 ;\n /*0390*/ MOV R9, R12 ;\n /*03a0*/ MOV R8, R8 ;\n /*03b0*/ MOV R9, R9 ;\n /*03c0*/ R2UR UR4, R14 ;\n /*03d0*/ R2UR UR5, R15 ;\n /*03e0*/ LDG.E R8, [R8.64] ;\n /*03f0*/ FSETP.LEU.AND P0, PT, R8, 127, PT ;\n /*0400*/ MOV R11, RZ ;\n /*0410*/ MOV R21, RZ ;\n /*0420*/ MOV R22, RZ ;\n /*0430*/ MOV R8, R10 ;\n /*0440*/ MOV R9, R12 ;\n /*0450*/ MOV R11, R11 ;\n /*0460*/ MOV R21, R21 ;\n /*0470*/ MOV R22, R22 ;\n /*0480*/ @P0 BRA `(.L_x_0) ;\n /*0490*/ MOV R10, 0x24 ;\n /*04a0*/ LDC R10, c[0x0][R10+0x160] ;\n /*04b0*/ MOV R10, R10 ;\n /*04c0*/ MOV R12, 0x20 ;\n /*04d0*/ LDC R12, c[0x0][R12+0x160] ;\n /*04e0*/ MOV R12, R12 ;\n /*04f0*/ IADD3 R16, R6, -0x2, RZ ;\n /*0500*/ SHF.L.U32 R13, R12, 0x1, RZ ;\n /*0510*/ IADD3 R13, R7, -R13, RZ ;\n /*0520*/ IADD3 R17, R13, R16, RZ ;\n /*0530*/ ISETP.GE.AND P0, PT, R16, R12, PT ;\n /*0540*/ IADD3 R18, R5, -0x2, RZ ;\n /*0550*/ LOP3.LUT R12, R18, R16, RZ, 0xfc, !PT ;\n /*0560*/ ISETP.LT.AND P1, PT, R12, RZ, PT ;\n /*0570*/ PLOP3.LUT P2, PT, P0, P1, PT, 0xa8, 0x0 ;\n /*0580*/ ISETP.GE.AND P1, PT, R18, R10, PT ;\n /*0590*/ IADD3 R19, R13, R6, RZ ;\n /*05a0*/ IMAD.WIDE R12, R19, 0x4, RZ ;\n /*05b0*/ MOV R20, R12 ;\n /*05c0*/ MOV R23, R13 ;\n /*05d0*/ IADD3 R20, P3, R3, R20, RZ ;\n /*05e0*/ IADD3.X R23, R2, R23, RZ, P3, !PT ;\n /*05f0*/ IMAD R2, R17, 0x3, RZ ;\n /*0600*/ IMAD.WIDE R2, R2, 0x4, RZ ;\n /*0610*/ MOV R10, R2 ;\n /*0620*/ MOV R12, R3 ;\n /*0630*/ IADD3 R2, P3, R0, R10, RZ ;\n /*0640*/ IADD3.X R12, R4, R12, RZ, P3, !PT ;\n /*0650*/ PLOP3.LUT P2, PT, P1, P2, PT, 0xa8, 0x0 ;\n /*0660*/ MOV R10, R16 ;\n /*0670*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x80, 0x0 ;\n /*0680*/ MOV R13, R18 ;\n /*0690*/ PLOP3.LUT P1, PT, P1, PT, PT, 0x80, 0x0 ;\n /*06a0*/ MOV R19, R19 ;\n /*06b0*/ MOV R16, R20 ;\n /*06c0*/ MOV R17, R23 ;\n /*06d0*/ MOV R18, R2 ;\n /*06e0*/ MOV R12, R12 ;\n /*06f0*/ BSSY B0, `(.L_x_1) ;\n /*0700*/ @P2 BRA `(.L_x_2) ;\n /*0710*/ MOV R22, RZ ;\n /*0720*/ MOV R21, RZ ;\n /*0730*/ MOV R11, RZ ;\n /*0740*/ IADD3 R2, P2, R16, -0x8, RZ ;\n /*0750*/ IADD3.X R3, R17, -0x1, RZ, P2, !PT ;\n /*0760*/ MOV R2, R2 ;\n /*0770*/ MOV R3, R3 ;\n /*0780*/ MOV R2, R2 ;\n /*0790*/ MOV R3, R3 ;\n /*07a0*/ R2UR UR4, R14 ;\n /*07b0*/ R2UR UR5, R15 ;\n /*07c0*/ LDG.E R2, [R2.64] ;\n /*07d0*/ FSETP.LEU.AND P2, PT, R2, 127, PT ;\n /*07e0*/ MOV R22, R22 ;\n /*07f0*/ MOV R21, R21 ;\n /*0800*/ MOV R11, R11 ;\n /*0810*/ @P2 BRA `(.L_x_2) ;\n /*0820*/ MOV R2, R18 ;\n /*0830*/ MOV R3, R12 ;\n /*0840*/ MOV R2, R2 ;\n /*0850*/ MOV R3, R3 ;\n /*0860*/ R2UR UR4, R14 ;\n /*0870*/ R2UR UR5, R15 ;\n /*0880*/ LDG.E R2, [R2.64] ;\n /*0890*/ FADD R22, R2, RZ ;\n /*08a0*/ IADD3 R2, P2, R18, 0x4, RZ ;\n /*08b0*/ IADD3.X R3, R12, RZ, RZ, P2, !PT ;\n /*08c0*/ MOV R2, R2 ;\n /*08d0*/ MOV R3, R3 ;\n /*08e0*/ MOV R2, R2 ;\n /*08f0*/ MOV R3, R3 ;\n /*0900*/ R2UR UR4, R14 ;\n /*0910*/ R2UR UR5, R15 ;\n /*0920*/ LDG.E R2, [R2.64] ;\n /*0930*/ FADD R21, R2, RZ ;\n /*0940*/ IADD3 R2, P2, R18, 0x8, RZ ;\n /*0950*/ IADD3.X R3, R12, RZ, RZ, P2, !PT ;\n /*0960*/ MOV R2, R2 ;\n /*0970*/ MOV R3, R3 ;\n /*0980*/ MOV R2, R2 ;\n /*0990*/ MOV R3, R3 ;\n /*09a0*/ R2UR UR4, R14 ;\n /*09b0*/ R2UR UR5, R15 ;\n /*09c0*/ LDG.E R2, [R2.64] ;\n /*09d0*/ FADD R2, R2, RZ ;\n /*09e0*/ MOV R22, R22 ;\n /*09f0*/ MOV R21, R21 ;\n /*0a00*/ MOV R11, R2 ;\n.L_x_2:\n /*0a10*/ BSYNC B0 ;\n.L_x_1:\n /*0a20*/ LOP3.LUT R2, R13, R6, RZ, 0xfc, !PT ;\n /*0a30*/ ISETP.LT.AND P2, PT, R2, RZ, PT ;\n /*0a40*/ PLOP3.LUT P2, PT, P1, P2, PT, 0xa8, 0x0 ;\n /*0a50*/ BSSY B0, `(.L_x_3) ;\n /*0a60*/ @P2 BRA `(.L_x_4) ;\n /*0a70*/ MOV R2, R16 ;\n /*0a80*/ MOV R3, R17 ;\n /*0a90*/ MOV R2, R2 ;\n /*0aa0*/ MOV R3, R3 ;\n /*0ab0*/ R2UR UR4, R14 ;\n /*0ac0*/ R2UR UR5, R15 ;\n /*0ad0*/ LDG.E R2, [R2.64] ;\n /*0ae0*/ FSETP.LEU.AND P2, PT, R2, 127, PT ;\n /*0af0*/ @P2 BRA `(.L_x_4) ;\n /*0b00*/ IMAD R2, R19, 0x3, RZ ;\n /*0b10*/ IMAD.WIDE R2, R2, 0x4, RZ ;\n /*0b20*/ MOV R19, R2 ;\n /*0b30*/ MOV R20, R3 ;\n /*0b40*/ IADD3 R19, P2, R0, R19, RZ ;\n /*0b50*/ IADD3.X R20, R4, R20, RZ, P2, !PT ;\n /*0b60*/ MOV R2, R19 ;\n /*0b70*/ MOV R3, R20 ;\n /*0b80*/ MOV R2, R2 ;\n /*0b90*/ MOV R3, R3 ;\n /*0ba0*/ R2UR UR4, R14 ;\n /*0bb0*/ R2UR UR5, R15 ;\n /*0bc0*/ LDG.E R2, [R2.64] ;\n /*0bd0*/ FADD R22, R22, R2 ;\n /*0be0*/ IADD3 R2, P2, R19, 0x4, RZ ;\n /*0bf0*/ IADD3.X R3, R20, RZ, RZ, P2, !PT ;\n /*0c00*/ MOV R2, R2 ;\n /*0c10*/ MOV R3, R3 ;\n /*0c20*/ MOV R2, R2 ;\n /*0c30*/ MOV R3, R3 ;\n /*0c40*/ R2UR UR4, R14 ;\n /*0c50*/ R2UR UR5, R15 ;\n /*0c60*/ LDG.E R2, [R2.64] ;\n /*0c70*/ FADD R21, R21, R2 ;\n /*0c80*/ IADD3 R2, P2, R19, 0x8, RZ ;\n /*0c90*/ IADD3.X R3, R20, RZ, RZ, P2, !PT ;\n /*0ca0*/ MOV R2, R2 ;\n /*0cb0*/ MOV R3, R3 ;\n /*0cc0*/ MOV R2, R2 ;\n /*0cd0*/ MOV R3, R3 ;\n /*0ce0*/ R2UR UR4, R14 ;\n /*0cf0*/ R2UR UR5, R15 ;\n /*0d00*/ LDG.E R2, [R2.64] ;\n /*0d10*/ FADD R2, R11, R2 ;\n /*0d20*/ MOV R22, R22 ;\n /*0d30*/ MOV R21, R21 ;\n /*0d40*/ MOV R11, R2 ;\n.L_x_4:\n /*0d50*/ BSYNC B0 ;\n.L_x_3:\n /*0d60*/ MOV R2, 0x20 ;\n /*0d70*/ LDC R2, c[0x0][R2+0x160] ;\n /*0d80*/ MOV R2, R2 ;\n /*0d90*/ IADD3 R3, R6, 0x2, RZ ;\n /*0da0*/ ISETP.GE.AND P2, PT, R3, R2, PT ;\n /*0db0*/ LOP3.LUT R13, R13, R3, RZ, 0xfc, !PT ;\n /*0dc0*/ ISETP.LT.AND P3, PT, R13, RZ, PT ;\n /*0dd0*/ PLOP3.LUT P3, PT, P2, P3, PT, 0xa8, 0x0 ;\n /*0de0*/ PLOP3.LUT P3, PT, P1, P3, PT, 0xa8, 0x0 ;\n /*0df0*/ MOV R13, R3 ;\n /*0e00*/ PLOP3.LUT P1, PT, P2, PT, PT, 0x80, 0x0 ;\n /*0e10*/ BSSY B0, `(.L_x_5) ;\n /*0e20*/ @P3 BRA `(.L_x_6) ;\n /*0e30*/ IADD3 R2, P2, R16, 0x8, RZ ;\n /*0e40*/ IADD3.X R3, R17, RZ, RZ, P2, !PT ;\n /*0e50*/ MOV R2, R2 ;\n /*0e60*/ MOV R3, R3 ;\n /*0e70*/ MOV R2, R2 ;\n /*0e80*/ MOV R3, R3 ;\n /*0e90*/ R2UR UR4, R14 ;\n /*0ea0*/ R2UR UR5, R15 ;\n /*0eb0*/ LDG.E R2, [R2.64] ;\n /*0ec0*/ FSETP.LEU.AND P2, PT, R2, 127, PT ;\n /*0ed0*/ @P2 BRA `(.L_x_6) ;\n /*0ee0*/ IADD3 R2, P2, R18, 0x30, RZ ;\n /*0ef0*/ IADD3.X R3, R12, RZ, RZ, P2, !PT ;\n /*0f00*/ MOV R2, R2 ;\n /*0f10*/ MOV R3, R3 ;\n /*0f20*/ MOV R2, R2 ;\n /*0f30*/ MOV R3, R3 ;\n /*0f40*/ R2UR UR4, R14 ;\n /*0f50*/ R2UR UR5, R15 ;\n /*0f60*/ LDG.E R2, [R2.64] ;\n /*0f70*/ FADD R22, R22, R2 ;\n /*0f80*/ IADD3 R2, P2, R18, 0x34, RZ ;\n /*0f90*/ IADD3.X R3, R12, RZ, RZ, P2, !PT ;\n /*0fa0*/ MOV R2, R2 ;\n /*0fb0*/ MOV R3, R3 ;\n /*0fc0*/ MOV R2, R2 ;\n /*0fd0*/ MOV R3, R3 ;\n /*0fe0*/ R2UR UR4, R14 ;\n /*0ff0*/ R2UR UR5, R15 ;\n /*1000*/ LDG.E R2, [R2.64] ;\n /*1010*/ FADD R21, R21, R2 ;\n /*1020*/ IADD3 R2, P2, R18, 0x38, RZ ;\n /*1030*/ IADD3.X R3, R12, RZ, RZ, P2, !PT ;\n /*1040*/ MOV R2, R2 ;\n /*1050*/ MOV R3, R3 ;\n /*1060*/ MOV R2, R2 ;\n /*1070*/ MOV R3, R3 ;\n /*1080*/ R2UR UR4, R14 ;\n /*1090*/ R2UR UR5, R15 ;\n /*10a0*/ LDG.E R2, [R2.64] ;\n /*10b0*/ FADD R2, R11, R2 ;\n /*10c0*/ MOV R22, R22 ;\n /*10d0*/ MOV R21, R21 ;\n /*10e0*/ MOV R11, R2 ;\n.L_x_6:\n /*10f0*/ BSYNC B0 ;\n.L_x_5:\n /*1100*/ MOV R2, 0x8 ;\n /*1110*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*1120*/ MOV R20, R2 ;\n /*1130*/ MOV R23, R3 ;\n /*1140*/ MOV R20, R20 ;\n /*1150*/ MOV R23, R23 ;\n /*1160*/ MOV R20, R20 ;\n /*1170*/ MOV R23, R23 ;\n /*1180*/ MOV R2, 0x24 ;\n /*1190*/ LDC R2, c[0x0][R2+0x160] ;\n /*11a0*/ MOV R2, R2 ;\n /*11b0*/ MOV R3, 0x20 ;\n /*11c0*/ LDC R3, c[0x0][R3+0x160] ;\n /*11d0*/ MOV R3, R3 ;\n /*11e0*/ IADD3 R16, R5, -0x1, RZ ;\n /*11f0*/ IMAD R12, R16, R3, RZ ;\n /*1200*/ IADD3 R17, R6, -0x1, RZ ;\n /*1210*/ IADD3 R18, R12, R17, RZ ;\n /*1220*/ LOP3.LUT R19, R16, R17, RZ, 0xfc, !PT ;\n /*1230*/ ISETP.LT.AND P3, PT, R19, RZ, PT ;\n /*1240*/ ISETP.GT.AND P2, PT, R6, R3, PT ;\n /*1250*/ PLOP3.LUT P3, PT, P2, P3, PT, 0xa8, 0x0 ;\n /*1260*/ ISETP.GT.AND P4, PT, R5, R2, PT ;\n /*1270*/ IADD3 R12, R12, R6, RZ ;\n /*1280*/ IMAD.WIDE R2, R12, 0x4, RZ ;\n /*1290*/ MOV R19, R2 ;\n /*12a0*/ MOV R24, R3 ;\n /*12b0*/ IADD3 R19, P5, R20, R19, RZ ;\n /*12c0*/ IADD3.X R24, R23, R24, RZ, P5, !PT ;\n /*12d0*/ IMAD R2, R18, 0x3, RZ ;\n /*12e0*/ IMAD.WIDE R2, R2, 0x4, RZ ;\n /*12f0*/ MOV R20, R2 ;\n /*1300*/ MOV R2, R3 ;\n /*1310*/ IADD3 R20, P5, R0, R20, RZ ;\n /*1320*/ IADD3.X R2, R4, R2, RZ, P5, !PT ;\n /*1330*/ PLOP3.LUT P3, PT, P4, P3, PT, 0xa8, 0x0 ;\n /*1340*/ MOV R16, R16 ;\n /*1350*/ MOV R17, R17 ;\n /*1360*/ PLOP3.LUT P2, PT, P2, PT, PT, 0x80, 0x0 ;\n /*1370*/ PLOP3.LUT P4, PT, P4, PT, PT, 0x80, 0x0 ;\n /*1380*/ MOV R23, R12 ;\n /*1390*/ MOV R18, R19 ;\n /*13a0*/ MOV R19, R24 ;\n /*13b0*/ MOV R20, R20 ;\n /*13c0*/ MOV R12, R2 ;\n /*13d0*/ BSSY B0, `(.L_x_7) ;\n /*13e0*/ @P3 BRA `(.L_x_8) ;\n /*13f0*/ IADD3 R2, P3, R18, -0x4, RZ ;\n /*1400*/ IADD3.X R3, R19, -0x1, RZ, P3, !PT ;\n /*1410*/ MOV R2, R2 ;\n /*1420*/ MOV R3, R3 ;\n /*1430*/ MOV R2, R2 ;\n /*1440*/ MOV R3, R3 ;\n /*1450*/ R2UR UR4, R14 ;\n /*1460*/ R2UR UR5, R15 ;\n /*1470*/ LDG.E R2, [R2.64] ;\n /*1480*/ FSETP.LEU.AND P3, PT, R2, 127, PT ;\n /*1490*/ @P3 BRA `(.L_x_8) ;\n /*14a0*/ MOV R2, R20 ;\n /*14b0*/ MOV R3, R12 ;\n /*14c0*/ MOV R2, R2 ;\n /*14d0*/ MOV R3, R3 ;\n /*14e0*/ R2UR UR4, R14 ;\n /*14f0*/ R2UR UR5, R15 ;\n /*1500*/ LDG.E R2, [R2.64] ;\n /*1510*/ FFMA R22, R2, 2, R22 ;\n /*1520*/ IADD3 R2, P3, R20, 0x4, RZ ;\n /*1530*/ IADD3.X R3, R12, RZ, RZ, P3, !PT ;\n /*1540*/ MOV R2, R2 ;\n /*1550*/ MOV R3, R3 ;\n /*1560*/ MOV R2, R2 ;\n /*1570*/ MOV R3, R3 ;\n /*1580*/ R2UR UR4, R14 ;\n /*1590*/ R2UR UR5, R15 ;\n /*15a0*/ LDG.E R2, [R2.64] ;\n /*15b0*/ FFMA R21, R2, 2, R21 ;\n /*15c0*/ IADD3 R2, P3, R20, 0x8, RZ ;\n /*15d0*/ IADD3.X R3, R12, RZ, RZ, P3, !PT ;\n /*15e0*/ MOV R2, R2 ;\n /*15f0*/ MOV R3, R3 ;\n /*1600*/ MOV R2, R2 ;\n /*1610*/ MOV R3, R3 ;\n /*1620*/ R2UR UR4, R14 ;\n /*1630*/ R2UR UR5, R15 ;\n /*1640*/ LDG.E R2, [R2.64] ;\n /*1650*/ FFMA R2, R2, 2, R11 ;\n /*1660*/ MOV R22, R22 ;\n /*1670*/ MOV R21, R21 ;\n /*1680*/ MOV R11, R2 ;\n.L_x_8:\n /*1690*/ BSYNC B0 ;\n.L_x_7:\n /*16a0*/ LOP3.LUT R2, R16, R6, RZ, 0xfc, !PT ;\n /*16b0*/ ISETP.LT.AND P3, PT, R2, RZ, PT ;\n /*16c0*/ PLOP3.LUT P3, PT, P4, P3, PT, 0xa8, 0x0 ;\n /*16d0*/ BSSY B0, `(.L_x_9) ;\n /*16e0*/ @P3 BRA `(.L_x_10) ;\n /*16f0*/ MOV R2, R18 ;\n /*1700*/ MOV R3, R19 ;\n /*1710*/ MOV R2, R2 ;\n /*1720*/ MOV R3, R3 ;\n /*1730*/ R2UR UR4, R14 ;\n /*1740*/ R2UR UR5, R15 ;\n /*1750*/ LDG.E R2, [R2.64] ;\n /*1760*/ FSETP.LEU.AND P3, PT, R2, 127, PT ;\n /*1770*/ @P3 BRA `(.L_x_10) ;\n /*1780*/ IMAD R2, R23, 0x3, RZ ;\n /*1790*/ IMAD.WIDE R2, R2, 0x4, RZ ;\n /*17a0*/ MOV R23, R2 ;\n /*17b0*/ MOV R24, R3 ;\n /*17c0*/ IADD3 R23, P3, R0, R23, RZ ;\n /*17d0*/ IADD3.X R24, R4, R24, RZ, P3, !PT ;\n /*17e0*/ MOV R2, R23 ;\n /*17f0*/ MOV R3, R24 ;\n /*1800*/ MOV R2, R2 ;\n /*1810*/ MOV R3, R3 ;\n /*1820*/ R2UR UR4, R14 ;\n /*1830*/ R2UR UR5, R15 ;\n /*1840*/ LDG.E R2, [R2.64] ;\n /*1850*/ FFMA R22, R2, 2, R22 ;\n /*1860*/ IADD3 R2, P3, R23, 0x4, RZ ;\n /*1870*/ IADD3.X R3, R24, RZ, RZ, P3, !PT ;\n /*1880*/ MOV R2, R2 ;\n /*1890*/ MOV R3, R3 ;\n /*18a0*/ MOV R2, R2 ;\n /*18b0*/ MOV R3, R3 ;\n /*18c0*/ R2UR UR4, R14 ;\n /*18d0*/ R2UR UR5, R15 ;\n /*18e0*/ LDG.E R2, [R2.64] ;\n /*18f0*/ FFMA R21, R2, 2, R21 ;\n /*1900*/ IADD3 R2, P3, R23, 0x8, RZ ;\n /*1910*/ IADD3.X R3, R24, RZ, RZ, P3, !PT ;\n /*1920*/ MOV R2, R2 ;\n /*1930*/ MOV R3, R3 ;\n /*1940*/ MOV R2, R2 ;\n /*1950*/ MOV R3, R3 ;\n /*1960*/ R2UR UR4, R14 ;\n /*1970*/ R2UR UR5, R15 ;\n /*1980*/ LDG.E R2, [R2.64] ;\n /*1990*/ FFMA R2, R2, 2, R11 ;\n /*19a0*/ MOV R22, R22 ;\n /*19b0*/ MOV R21, R21 ;\n /*19c0*/ MOV R11, R2 ;\n.L_x_10:\n /*19d0*/ BSYNC B0 ;\n.L_x_9:\n /*19e0*/ MOV R2, 0x20 ;\n /*19f0*/ LDC R2, c[0x0][R2+0x160] ;\n /*1a00*/ MOV R2, R2 ;\n /*1a10*/ IADD3 R3, R6, 0x1, RZ ;\n /*1a20*/ ISETP.GE.AND P3, PT, R3, R2, PT ;\n /*1a30*/ LOP3.LUT R16, R16, R3, RZ, 0xfc, !PT ;\n /*1a40*/ ISETP.LT.AND P5, PT, R16, RZ, PT ;\n /*1a50*/ PLOP3.LUT P5, PT, P3, P5, PT, 0xa8, 0x0 ;\n /*1a60*/ PLOP3.LUT P5, PT, P4, P5, PT, 0xa8, 0x0 ;\n /*1a70*/ MOV R2, R3 ;\n /*1a80*/ PLOP3.LUT P3, PT, P3, PT, PT, 0x80, 0x0 ;\n /*1a90*/ BSSY B0, `(.L_x_11) ;\n /*1aa0*/ @P5 BRA `(.L_x_12) ;\n /*1ab0*/ IADD3 R18, P4, R18, 0x4, RZ ;\n /*1ac0*/ IADD3.X R19, R19, RZ, RZ, P4, !PT ;\n /*1ad0*/ MOV R18, R18 ;\n /*1ae0*/ MOV R19, R19 ;\n /*1af0*/ MOV R18, R18 ;\n /*1b00*/ MOV R19, R19 ;\n /*1b10*/ R2UR UR4, R14 ;\n /*1b20*/ R2UR UR5, R15 ;\n /*1b30*/ LDG.E R18, [R18.64] ;\n /*1b40*/ FSETP.LEU.AND P4, PT, R18, 127, PT ;\n /*1b50*/ @P4 BRA `(.L_x_12) ;\n /*1b60*/ IADD3 R18, P4, R20, 0x18, RZ ;\n /*1b70*/ IADD3.X R19, R12, RZ, RZ, P4, !PT ;\n /*1b80*/ MOV R18, R18 ;\n /*1b90*/ MOV R19, R19 ;\n /*1ba0*/ MOV R18, R18 ;\n /*1bb0*/ MOV R19, R19 ;\n /*1bc0*/ R2UR UR4, R14 ;\n /*1bd0*/ R2UR UR5, R15 ;\n /*1be0*/ LDG.E R18, [R18.64] ;\n /*1bf0*/ FFMA R22, R18, 2, R22 ;\n /*1c00*/ IADD3 R18, P4, R20, 0x1c, RZ ;\n /*1c10*/ IADD3.X R19, R12, RZ, RZ, P4, !PT ;\n /*1c20*/ MOV R18, R18 ;\n /*1c30*/ MOV R19, R19 ;\n /*1c40*/ MOV R18, R18 ;\n /*1c50*/ MOV R19, R19 ;\n /*1c60*/ R2UR UR4, R14 ;\n /*1c70*/ R2UR UR5, R15 ;\n /*1c80*/ LDG.E R18, [R18.64] ;\n /*1c90*/ FFMA R21, R18, 2, R21 ;\n /*1ca0*/ IADD3 R18, P4, R20, 0x20, RZ ;\n /*1cb0*/ IADD3.X R19, R12, RZ, RZ, P4, !PT ;\n /*1cc0*/ MOV R18, R18 ;\n /*1cd0*/ MOV R19, R19 ;\n /*1ce0*/ MOV R18, R18 ;\n /*1cf0*/ MOV R19, R19 ;\n /*1d00*/ R2UR UR4, R14 ;\n /*1d10*/ R2UR UR5, R15 ;\n /*1d20*/ LDG.E R18, [R18.64] ;\n /*1d30*/ FFMA R11, R18, 2, R11 ;\n /*1d40*/ MOV R22, R22 ;\n /*1d50*/ MOV R21, R21 ;\n /*1d60*/ MOV R11, R11 ;\n.L_x_12:\n /*1d70*/ BSYNC B0 ;\n.L_x_11:\n /*1d80*/ LOP3.LUT R3, R5, R10, RZ, 0xfc, !PT ;\n /*1d90*/ ISETP.LT.AND P4, PT, R3, RZ, PT ;\n /*1da0*/ IADD3 R7, R7, R10, RZ ;\n /*1db0*/ IMAD R7, R7, 0x3, RZ ;\n /*1dc0*/ IMAD.WIDE R18, R7, 0x4, RZ ;\n /*1dd0*/ MOV R7, R18 ;\n /*1de0*/ MOV R3, R19 ;\n /*1df0*/ IADD3 R7, P5, R0, R7, RZ ;\n /*1e00*/ IADD3.X R3, R4, R3, RZ, P5, !PT ;\n /*1e10*/ PLOP3.LUT P4, PT, P0, P4, PT, 0xa8, 0x0 ;\n /*1e20*/ MOV R7, R7 ;\n /*1e30*/ MOV R3, R3 ;\n /*1e40*/ BSSY B0, `(.L_x_13) ;\n /*1e50*/ @P4 BRA `(.L_x_14) ;\n /*1e60*/ IADD3 R18, P4, R8, -0x8, RZ ;\n /*1e70*/ IADD3.X R19, R9, -0x1, RZ, P4, !PT ;\n /*1e80*/ MOV R18, R18 ;\n /*1e90*/ MOV R19, R19 ;\n /*1ea0*/ MOV R18, R18 ;\n /*1eb0*/ MOV R19, R19 ;\n /*1ec0*/ R2UR UR4, R14 ;\n /*1ed0*/ R2UR UR5, R15 ;\n /*1ee0*/ LDG.E R18, [R18.64] ;\n /*1ef0*/ FSETP.LEU.AND P4, PT, R18, 127, PT ;\n /*1f00*/ @P4 BRA `(.L_x_14) ;\n /*1f10*/ MOV R18, R7 ;\n /*1f20*/ MOV R19, R3 ;\n /*1f30*/ MOV R18, R18 ;\n /*1f40*/ MOV R19, R19 ;\n /*1f50*/ R2UR UR4, R14 ;\n /*1f60*/ R2UR UR5, R15 ;\n /*1f70*/ LDG.E R18, [R18.64] ;\n /*1f80*/ FADD R22, R22, R18 ;\n /*1f90*/ IADD3 R18, P4, R7, 0x4, RZ ;\n /*1fa0*/ IADD3.X R19, R3, RZ, RZ, P4, !PT ;\n /*1fb0*/ MOV R18, R18 ;\n /*1fc0*/ MOV R19, R19 ;\n /*1fd0*/ MOV R18, R18 ;\n /*1fe0*/ MOV R19, R19 ;\n /*1ff0*/ R2UR UR4, R14 ;\n /*2000*/ R2UR UR5, R15 ;\n /*2010*/ LDG.E R18, [R18.64] ;\n /*2020*/ FADD R21, R21, R18 ;\n /*2030*/ IADD3 R18, P4, R7, 0x8, RZ ;\n /*2040*/ IADD3.X R19, R3, RZ, RZ, P4, !PT ;\n /*2050*/ MOV R18, R18 ;\n /*2060*/ MOV R19, R19 ;\n /*2070*/ MOV R18, R18 ;\n /*2080*/ MOV R19, R19 ;\n /*2090*/ R2UR UR4, R14 ;\n /*20a0*/ R2UR UR5, R15 ;\n /*20b0*/ LDG.E R18, [R18.64] ;\n /*20c0*/ FADD R11, R11, R18 ;\n /*20d0*/ MOV R22, R22 ;\n /*20e0*/ MOV R21, R21 ;\n /*20f0*/ MOV R11, R11 ;\n.L_x_14:\n /*2100*/ BSYNC B0 ;\n.L_x_13:\n /*2110*/ LOP3.LUT R12, R5, R17, RZ, 0xfc, !PT ;\n /*2120*/ ISETP.LT.AND P4, PT, R12, RZ, PT ;\n /*2130*/ PLOP3.LUT P4, PT, P2, P4, PT, 0xa8, 0x0 ;\n /*2140*/ BSSY B0, `(.L_x_15) ;\n /*2150*/ @P4 BRA `(.L_x_16) ;\n /*2160*/ IADD3 R18, P4, R8, -0x4, RZ ;\n /*2170*/ IADD3.X R19, R9, -0x1, RZ, P4, !PT ;\n /*2180*/ MOV R18, R18 ;\n /*2190*/ MOV R19, R19 ;\n /*21a0*/ MOV R18, R18 ;\n /*21b0*/ MOV R19, R19 ;\n /*21c0*/ R2UR UR4, R14 ;\n /*21d0*/ R2UR UR5, R15 ;\n /*21e0*/ LDG.E R18, [R18.64] ;\n /*21f0*/ FSETP.LEU.AND P4, PT, R18, 127, PT ;\n /*2200*/ @P4 BRA `(.L_x_16) ;\n /*2210*/ IADD3 R18, P4, R7, 0xc, RZ ;\n /*2220*/ IADD3.X R19, R3, RZ, RZ, P4, !PT ;\n /*2230*/ MOV R18, R18 ;\n /*2240*/ MOV R19, R19 ;\n /*2250*/ MOV R18, R18 ;\n /*2260*/ MOV R19, R19 ;\n /*2270*/ R2UR UR4, R14 ;\n /*2280*/ R2UR UR5, R15 ;\n /*2290*/ LDG.E R18, [R18.64] ;\n /*22a0*/ FFMA R22, R18, 2, R22 ;\n /*22b0*/ IADD3 R18, P4, R7, 0x10, RZ ;\n /*22c0*/ IADD3.X R19, R3, RZ, RZ, P4, !PT ;\n /*22d0*/ MOV R18, R18 ;\n /*22e0*/ MOV R19, R19 ;\n /*22f0*/ MOV R18, R18 ;\n /*2300*/ MOV R19, R19 ;\n /*2310*/ R2UR UR4, R14 ;\n /*2320*/ R2UR UR5, R15 ;\n /*2330*/ LDG.E R18, [R18.64] ;\n /*2340*/ FFMA R21, R18, 2, R21 ;\n /*2350*/ IADD3 R18, P4, R7, 0x14, RZ ;\n /*2360*/ IADD3.X R19, R3, RZ, RZ, P4, !PT ;\n /*2370*/ MOV R18, R18 ;\n /*2380*/ MOV R19, R19 ;\n /*2390*/ MOV R18, R18 ;\n /*23a0*/ MOV R19, R19 ;\n /*23b0*/ R2UR UR4, R14 ;\n /*23c0*/ R2UR UR5, R15 ;\n /*23d0*/ LDG.E R18, [R18.64] ;\n /*23e0*/ FFMA R11, R18, 2, R11 ;\n /*23f0*/ MOV R22, R22 ;\n /*2400*/ MOV R21, R21 ;\n /*2410*/ MOV R11, R11 ;\n.L_x_16:\n /*2420*/ BSYNC B0 ;\n.L_x_15:\n /*2430*/ LOP3.LUT R12, R5, R2, RZ, 0xfc, !PT ;\n /*2440*/ ISETP.LT.AND P4, PT, R12, RZ, PT ;\n /*2450*/ PLOP3.LUT P4, PT, P3, P4, PT, 0xa8, 0x0 ;\n /*2460*/ BSSY B0, `(.L_x_17) ;\n /*2470*/ @P4 BRA `(.L_x_18) ;\n /*2480*/ IADD3 R18, P4, R8, 0x4, RZ ;\n /*2490*/ IADD3.X R19, R9, RZ, RZ, P4, !PT ;\n /*24a0*/ MOV R18, R18 ;\n /*24b0*/ MOV R19, R19 ;\n /*24c0*/ MOV R18, R18 ;\n /*24d0*/ MOV R19, R19 ;\n /*24e0*/ R2UR UR4, R14 ;\n /*24f0*/ R2UR UR5, R15 ;\n /*2500*/ LDG.E R18, [R18.64] ;\n /*2510*/ FSETP.LEU.AND P4, PT, R18, 127, PT ;\n /*2520*/ @P4 BRA `(.L_x_18) ;\n /*2530*/ IADD3 R18, P4, R7, 0x24, RZ ;\n /*2540*/ IADD3.X R19, R3, RZ, RZ, P4, !PT ;\n /*2550*/ MOV R18, R18 ;\n /*2560*/ MOV R19, R19 ;\n /*2570*/ MOV R18, R18 ;\n /*2580*/ MOV R19, R19 ;\n /*2590*/ R2UR UR4, R14 ;\n /*25a0*/ R2UR UR5, R15 ;\n /*25b0*/ LDG.E R18, [R18.64] ;\n /*25c0*/ FFMA R22, R18, 2, R22 ;\n /*25d0*/ IADD3 R18, P4, R7, 0x28, RZ ;\n /*25e0*/ IADD3.X R19, R3, RZ, RZ, P4, !PT ;\n /*25f0*/ MOV R18, R18 ;\n /*2600*/ MOV R19, R19 ;\n /*2610*/ MOV R18, R18 ;\n /*2620*/ MOV R19, R19 ;\n /*2630*/ R2UR UR4, R14 ;\n /*2640*/ R2UR UR5, R15 ;\n /*2650*/ LDG.E R18, [R18.64] ;\n /*2660*/ FFMA R21, R18, 2, R21 ;\n /*2670*/ IADD3 R18, P4, R7, 0x2c, RZ ;\n /*2680*/ IADD3.X R19, R3, RZ, RZ, P4, !PT ;\n /*2690*/ MOV R18, R18 ;\n /*26a0*/ MOV R19, R19 ;\n /*26b0*/ MOV R18, R18 ;\n /*26c0*/ MOV R19, R19 ;\n /*26d0*/ R2UR UR4, R14 ;\n /*26e0*/ R2UR UR5, R15 ;\n /*26f0*/ LDG.E R18, [R18.64] ;\n /*2700*/ FFMA R11, R18, 2, R11 ;\n /*2710*/ MOV R22, R22 ;\n /*2720*/ MOV R21, R21 ;\n /*2730*/ MOV R11, R11 ;\n.L_x_18:\n /*2740*/ BSYNC B0 ;\n.L_x_17:\n /*2750*/ LOP3.LUT R12, R5, R13, RZ, 0xfc, !PT ;\n /*2760*/ ISETP.LT.AND P4, PT, R12, RZ, PT ;\n /*2770*/ PLOP3.LUT P4, PT, P1, P4, PT, 0xa8, 0x0 ;\n /*2780*/ BSSY B0, `(.L_x_19) ;\n /*2790*/ @P4 BRA `(.L_x_20) ;\n /*27a0*/ IADD3 R8, P4, R8, 0x8, RZ ;\n /*27b0*/ IADD3.X R9, R9, RZ, RZ, P4, !PT ;\n /*27c0*/ MOV R8, R8 ;\n /*27d0*/ MOV R9, R9 ;\n /*27e0*/ MOV R8, R8 ;\n /*27f0*/ MOV R9, R9 ;\n /*2800*/ R2UR UR4, R14 ;\n /*2810*/ R2UR UR5, R15 ;\n /*2820*/ LDG.E R8, [R8.64] ;\n /*2830*/ FSETP.LEU.AND P4, PT, R8, 127, PT ;\n /*2840*/ @P4 BRA `(.L_x_20) ;\n /*2850*/ IADD3 R8, P4, R7, 0x30, RZ ;\n /*2860*/ IADD3.X R9, R3, RZ, RZ, P4, !PT ;\n /*2870*/ MOV R8, R8 ;\n /*2880*/ MOV R9, R9 ;\n /*2890*/ MOV R8, R8 ;\n /*28a0*/ MOV R9, R9 ;\n /*28b0*/ R2UR UR4, R14 ;\n /*28c0*/ R2UR UR5, R15 ;\n /*28d0*/ LDG.E R8, [R8.64] ;\n /*28e0*/ FADD R22, R22, R8 ;\n /*28f0*/ IADD3 R8, P4, R7, 0x34, RZ ;\n /*2900*/ IADD3.X R9, R3, RZ, RZ, P4, !PT ;\n /*2910*/ MOV R8, R8 ;\n /*2920*/ MOV R9, R9 ;\n /*2930*/ MOV R8, R8 ;\n /*2940*/ MOV R9, R9 ;\n /*2950*/ R2UR UR4, R14 ;\n /*2960*/ R2UR UR5, R15 ;\n /*2970*/ LDG.E R8, [R8.64] ;\n /*2980*/ FADD R21, R21, R8 ;\n /*2990*/ IADD3 R8, P4, R7, 0x38, RZ ;\n /*29a0*/ IADD3.X R9, R3, RZ, RZ, P4, !PT ;\n /*29b0*/ MOV R8, R8 ;\n /*29c0*/ MOV R9, R9 ;\n /*29d0*/ MOV R8, R8 ;\n /*29e0*/ MOV R9, R9 ;\n /*29f0*/ R2UR UR4, R14 ;\n /*2a00*/ R2UR UR5, R15 ;\n /*2a10*/ LDG.E R8, [R8.64] ;\n /*2a20*/ FADD R8, R11, R8 ;\n /*2a30*/ MOV R22, R22 ;\n /*2a40*/ MOV R21, R21 ;\n /*2a50*/ MOV R11, R8 ;\n.L_x_20:\n /*2a60*/ BSYNC B0 ;\n.L_x_19:\n /*2a70*/ MOV R8, 0x8 ;\n /*2a80*/ LDC.64 R8, c[0x0][R8+0x160] ;\n /*2a90*/ MOV R20, R8 ;\n /*2aa0*/ MOV R23, R9 ;\n /*2ab0*/ MOV R20, R20 ;\n /*2ac0*/ MOV R23, R23 ;\n /*2ad0*/ MOV R20, R20 ;\n /*2ae0*/ MOV R23, R23 ;\n /*2af0*/ MOV R3, 0x24 ;\n /*2b00*/ LDC R3, c[0x0][R3+0x160] ;\n /*2b10*/ MOV R3, R3 ;\n /*2b20*/ MOV R7, 0x20 ;\n /*2b30*/ LDC R7, c[0x0][R7+0x160] ;\n /*2b40*/ MOV R7, R7 ;\n /*2b50*/ IADD3 R12, R5, 0x1, RZ ;\n /*2b60*/ IMAD R7, R12, R7, RZ ;\n /*2b70*/ IADD3 R16, R7, R17, RZ ;\n /*2b80*/ LOP3.LUT R17, R12, R17, RZ, 0xfc, !PT ;\n /*2b90*/ ISETP.LT.AND P4, PT, R17, RZ, PT ;\n /*2ba0*/ PLOP3.LUT P4, PT, P2, P4, PT, 0xa8, 0x0 ;\n /*2bb0*/ ISETP.GE.AND P2, PT, R12, R3, PT ;\n /*2bc0*/ IADD3 R7, R7, R6, RZ ;\n /*2bd0*/ IMAD.WIDE R8, R7, 0x4, RZ ;\n /*2be0*/ MOV R18, R8 ;\n /*2bf0*/ MOV R19, R9 ;\n /*2c00*/ IADD3 R18, P5, R20, R18, RZ ;\n /*2c10*/ IADD3.X R19, R23, R19, RZ, P5, !PT ;\n /*2c20*/ IMAD R8, R16, 0x3, RZ ;\n /*2c30*/ IMAD.WIDE R8, R8, 0x4, RZ ;\n /*2c40*/ MOV R3, R8 ;\n /*2c50*/ MOV R17, R9 ;\n /*2c60*/ IADD3 R3, P5, R0, R3, RZ ;\n /*2c70*/ IADD3.X R17, R4, R17, RZ, P5, !PT ;\n /*2c80*/ PLOP3.LUT P4, PT, P2, P4, PT, 0xa8, 0x0 ;\n /*2c90*/ MOV R8, R12 ;\n /*2ca0*/ PLOP3.LUT P2, PT, P2, PT, PT, 0x80, 0x0 ;\n /*2cb0*/ MOV R16, R7 ;\n /*2cc0*/ MOV R9, R18 ;\n /*2cd0*/ MOV R12, R19 ;\n /*2ce0*/ MOV R3, R3 ;\n /*2cf0*/ MOV R7, R17 ;\n /*2d00*/ BSSY B0, `(.L_x_21) ;\n /*2d10*/ @P4 BRA `(.L_x_22) ;\n /*2d20*/ IADD3 R18, P4, R9, -0x4, RZ ;\n /*2d30*/ IADD3.X R19, R12, -0x1, RZ, P4, !PT ;\n /*2d40*/ MOV R18, R18 ;\n /*2d50*/ MOV R19, R19 ;\n /*2d60*/ MOV R18, R18 ;\n /*2d70*/ MOV R19, R19 ;\n /*2d80*/ R2UR UR4, R14 ;\n /*2d90*/ R2UR UR5, R15 ;\n /*2da0*/ LDG.E R18, [R18.64] ;\n /*2db0*/ FSETP.LEU.AND P4, PT, R18, 127, PT ;\n /*2dc0*/ @P4 BRA `(.L_x_22) ;\n /*2dd0*/ MOV R18, R3 ;\n /*2de0*/ MOV R19, R7 ;\n /*2df0*/ MOV R18, R18 ;\n /*2e00*/ MOV R19, R19 ;\n /*2e10*/ R2UR UR4, R14 ;\n /*2e20*/ R2UR UR5, R15 ;\n /*2e30*/ LDG.E R18, [R18.64] ;\n /*2e40*/ FFMA R22, R18, 2, R22 ;\n /*2e50*/ IADD3 R18, P4, R3, 0x4, RZ ;\n /*2e60*/ IADD3.X R19, R7, RZ, RZ, P4, !PT ;\n /*2e70*/ MOV R18, R18 ;\n /*2e80*/ MOV R19, R19 ;\n /*2e90*/ MOV R18, R18 ;\n /*2ea0*/ MOV R19, R19 ;\n /*2eb0*/ R2UR UR4, R14 ;\n /*2ec0*/ R2UR UR5, R15 ;\n /*2ed0*/ LDG.E R18, [R18.64] ;\n /*2ee0*/ FFMA R21, R18, 2, R21 ;\n /*2ef0*/ IADD3 R18, P4, R3, 0x8, RZ ;\n /*2f00*/ IADD3.X R19, R7, RZ, RZ, P4, !PT ;\n /*2f10*/ MOV R18, R18 ;\n /*2f20*/ MOV R19, R19 ;\n /*2f30*/ MOV R18, R18 ;\n /*2f40*/ MOV R19, R19 ;\n /*2f50*/ R2UR UR4, R14 ;\n /*2f60*/ R2UR UR5, R15 ;\n /*2f70*/ LDG.E R18, [R18.64] ;\n /*2f80*/ FFMA R11, R18, 2, R11 ;\n /*2f90*/ MOV R22, R22 ;\n /*2fa0*/ MOV R21, R21 ;\n /*2fb0*/ MOV R11, R11 ;\n.L_x_22:\n /*2fc0*/ BSYNC B0 ;\n.L_x_21:\n /*2fd0*/ LOP3.LUT R17, R8, R6, RZ, 0xfc, !PT ;\n /*2fe0*/ ISETP.LT.AND P4, PT, R17, RZ, PT ;\n /*2ff0*/ PLOP3.LUT P4, PT, P2, P4, PT, 0xa8, 0x0 ;\n /*3000*/ BSSY B0, `(.L_x_23) ;\n /*3010*/ @P4 BRA `(.L_x_24) ;\n /*3020*/ MOV R18, R9 ;\n /*3030*/ MOV R19, R12 ;\n /*3040*/ MOV R18, R18 ;\n /*3050*/ MOV R19, R19 ;\n /*3060*/ R2UR UR4, R14 ;\n /*3070*/ R2UR UR5, R15 ;\n /*3080*/ LDG.E R18, [R18.64] ;\n /*3090*/ FSETP.LEU.AND P4, PT, R18, 127, PT ;\n /*30a0*/ @P4 BRA `(.L_x_24) ;\n /*30b0*/ IMAD R16, R16, 0x3, RZ ;\n /*30c0*/ IMAD.WIDE R16, R16, 0x4, RZ ;\n /*30d0*/ MOV R18, R16 ;\n /*30e0*/ MOV R19, R17 ;\n /*30f0*/ IADD3 R18, P4, R0, R18, RZ ;\n /*3100*/ IADD3.X R19, R4, R19, RZ, P4, !PT ;\n /*3110*/ MOV R16, R18 ;\n /*3120*/ MOV R17, R19 ;\n /*3130*/ MOV R16, R16 ;\n /*3140*/ MOV R17, R17 ;\n /*3150*/ R2UR UR4, R14 ;\n /*3160*/ R2UR UR5, R15 ;\n /*3170*/ LDG.E R16, [R16.64] ;\n /*3180*/ FFMA R22, R16, 2, R22 ;\n /*3190*/ IADD3 R16, P4, R18, 0x4, RZ ;\n /*31a0*/ IADD3.X R17, R19, RZ, RZ, P4, !PT ;\n /*31b0*/ MOV R16, R16 ;\n /*31c0*/ MOV R17, R17 ;\n /*31d0*/ MOV R16, R16 ;\n /*31e0*/ MOV R17, R17 ;\n /*31f0*/ R2UR UR4, R14 ;\n /*3200*/ R2UR UR5, R15 ;\n /*3210*/ LDG.E R16, [R16.64] ;\n /*3220*/ FFMA R21, R16, 2, R21 ;\n /*3230*/ IADD3 R16, P4, R18, 0x8, RZ ;\n /*3240*/ IADD3.X R17, R19, RZ, RZ, P4, !PT ;\n /*3250*/ MOV R16, R16 ;\n /*3260*/ MOV R17, R17 ;\n /*3270*/ MOV R16, R16 ;\n /*3280*/ MOV R17, R17 ;\n /*3290*/ R2UR UR4, R14 ;\n /*32a0*/ R2UR UR5, R15 ;\n /*32b0*/ LDG.E R16, [R16.64] ;\n /*32c0*/ FFMA R11, R16, 2, R11 ;\n /*32d0*/ MOV R22, R22 ;\n /*32e0*/ MOV R21, R21 ;\n /*32f0*/ MOV R11, R11 ;\n.L_x_24:\n /*3300*/ BSYNC B0 ;\n.L_x_23:\n /*3310*/ LOP3.LUT R2, R8, R2, RZ, 0xfc, !PT ;\n /*3320*/ ISETP.LT.AND P4, PT, R2, RZ, PT ;\n /*3330*/ PLOP3.LUT P4, PT, P3, P4, PT, 0xa8, 0x0 ;\n /*3340*/ PLOP3.LUT P4, PT, P2, P4, PT, 0xa8, 0x0 ;\n /*3350*/ BSSY B0, `(.L_x_25) ;\n /*3360*/ @P4 BRA `(.L_x_26) ;\n /*3370*/ IADD3 R8, P2, R9, 0x4, RZ ;\n /*3380*/ IADD3.X R9, R12, RZ, RZ, P2, !PT ;\n /*3390*/ MOV R8, R8 ;\n /*33a0*/ MOV R9, R9 ;\n /*33b0*/ MOV R8, R8 ;\n /*33c0*/ MOV R9, R9 ;\n /*33d0*/ R2UR UR4, R14 ;\n /*33e0*/ R2UR UR5, R15 ;\n /*33f0*/ LDG.E R8, [R8.64] ;\n /*3400*/ FSETP.LEU.AND P2, PT, R8, 127, PT ;\n /*3410*/ @P2 BRA `(.L_x_26) ;\n /*3420*/ IADD3 R8, P2, R3, 0x18, RZ ;\n /*3430*/ IADD3.X R9, R7, RZ, RZ, P2, !PT ;\n /*3440*/ MOV R8, R8 ;\n /*3450*/ MOV R9, R9 ;\n /*3460*/ MOV R8, R8 ;\n /*3470*/ MOV R9, R9 ;\n /*3480*/ R2UR UR4, R14 ;\n /*3490*/ R2UR UR5, R15 ;\n /*34a0*/ LDG.E R8, [R8.64] ;\n /*34b0*/ FFMA R22, R8, 2, R22 ;\n /*34c0*/ IADD3 R8, P2, R3, 0x1c, RZ ;\n /*34d0*/ IADD3.X R9, R7, RZ, RZ, P2, !PT ;\n /*34e0*/ MOV R8, R8 ;\n /*34f0*/ MOV R9, R9 ;\n /*3500*/ MOV R8, R8 ;\n /*3510*/ MOV R9, R9 ;\n /*3520*/ R2UR UR4, R14 ;\n /*3530*/ R2UR UR5, R15 ;\n /*3540*/ LDG.E R8, [R8.64] ;\n /*3550*/ FFMA R8, R8, 2, R21 ;\n /*3560*/ IADD3 R2, P2, R3, 0x20, RZ ;\n /*3570*/ IADD3.X R3, R7, RZ, RZ, P2, !PT ;\n /*3580*/ MOV R2, R2 ;\n /*3590*/ MOV R3, R3 ;\n /*35a0*/ MOV R2, R2 ;\n /*35b0*/ MOV R3, R3 ;\n /*35c0*/ R2UR UR4, R14 ;\n /*35d0*/ R2UR UR5, R15 ;\n /*35e0*/ LDG.E R2, [R2.64] ;\n /*35f0*/ FFMA R2, R2, 2, R11 ;\n /*3600*/ MOV R22, R22 ;\n /*3610*/ MOV R21, R8 ;\n /*3620*/ MOV R11, R2 ;\n.L_x_26:\n /*3630*/ BSYNC B0 ;\n.L_x_25:\n /*3640*/ MOV R2, 0x8 ;\n /*3650*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*3660*/ MOV R12, R2 ;\n /*3670*/ MOV R16, R3 ;\n /*3680*/ MOV R12, R12 ;\n /*3690*/ MOV R16, R16 ;\n /*36a0*/ MOV R12, R12 ;\n /*36b0*/ MOV R16, R16 ;\n /*36c0*/ MOV R2, 0x24 ;\n /*36d0*/ LDC R2, c[0x0][R2+0x160] ;\n /*36e0*/ MOV R2, R2 ;\n /*36f0*/ MOV R3, 0x20 ;\n /*3700*/ LDC R3, c[0x0][R3+0x160] ;\n /*3710*/ MOV R3, R3 ;\n /*3720*/ IADD3 R5, R5, 0x2, RZ ;\n /*3730*/ IMAD R3, R5, R3, RZ ;\n /*3740*/ IADD3 R7, R3, R10, RZ ;\n /*3750*/ LOP3.LUT R10, R5, R10, RZ, 0xfc, !PT ;\n /*3760*/ ISETP.LT.AND P2, PT, R10, RZ, PT ;\n /*3770*/ PLOP3.LUT P2, PT, P0, P2, PT, 0xa8, 0x0 ;\n /*3780*/ ISETP.GE.AND P0, PT, R5, R2, PT ;\n /*3790*/ IADD3 R9, R3, R6, RZ ;\n /*37a0*/ IMAD.WIDE R2, R9, 0x4, RZ ;\n /*37b0*/ MOV R8, R2 ;\n /*37c0*/ MOV R10, R3 ;\n /*37d0*/ IADD3 R8, P3, R12, R8, RZ ;\n /*37e0*/ IADD3.X R10, R16, R10, RZ, P3, !PT ;\n /*37f0*/ IMAD R2, R7, 0x3, RZ ;\n /*3800*/ IMAD.WIDE R2, R2, 0x4, RZ ;\n /*3810*/ MOV R7, R2 ;\n /*3820*/ MOV R3, R3 ;\n /*3830*/ IADD3 R2, P3, R0, R7, RZ ;\n /*3840*/ IADD3.X R3, R4, R3, RZ, P3, !PT ;\n /*3850*/ PLOP3.LUT P2, PT, P0, P2, PT, 0xa8, 0x0 ;\n /*3860*/ MOV R5, R5 ;\n /*3870*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x80, 0x0 ;\n /*3880*/ MOV R9, R9 ;\n /*3890*/ MOV R7, R8 ;\n /*38a0*/ MOV R8, R10 ;\n /*38b0*/ MOV R2, R2 ;\n /*38c0*/ MOV R3, R3 ;\n /*38d0*/ BSSY B0, `(.L_x_27) ;\n /*38e0*/ @P2 BRA `(.L_x_28) ;\n /*38f0*/ IADD3 R16, P2, R7, -0x8, RZ ;\n /*3900*/ IADD3.X R17, R8, -0x1, RZ, P2, !PT ;\n /*3910*/ MOV R16, R16 ;\n /*3920*/ MOV R17, R17 ;\n /*3930*/ MOV R16, R16 ;\n /*3940*/ MOV R17, R17 ;\n /*3950*/ R2UR UR4, R14 ;\n /*3960*/ R2UR UR5, R15 ;\n /*3970*/ LDG.E R16, [R16.64] ;\n /*3980*/ FSETP.LEU.AND P2, PT, R16, 127, PT ;\n /*3990*/ @P2 BRA `(.L_x_28) ;\n /*39a0*/ MOV R16, R2 ;\n /*39b0*/ MOV R17, R3 ;\n /*39c0*/ MOV R16, R16 ;\n /*39d0*/ MOV R17, R17 ;\n /*39e0*/ R2UR UR4, R14 ;\n /*39f0*/ R2UR UR5, R15 ;\n /*3a00*/ LDG.E R16, [R16.64] ;\n /*3a10*/ FADD R22, R22, R16 ;\n /*3a20*/ IADD3 R16, P2, R2, 0x4, RZ ;\n /*3a30*/ IADD3.X R17, R3, RZ, RZ, P2, !PT ;\n /*3a40*/ MOV R16, R16 ;\n /*3a50*/ MOV R17, R17 ;\n /*3a60*/ MOV R16, R16 ;\n /*3a70*/ MOV R17, R17 ;\n /*3a80*/ R2UR UR4, R14 ;\n /*3a90*/ R2UR UR5, R15 ;\n /*3aa0*/ LDG.E R16, [R16.64] ;\n /*3ab0*/ FADD R21, R21, R16 ;\n /*3ac0*/ IADD3 R16, P2, R2, 0x8, RZ ;\n /*3ad0*/ IADD3.X R17, R3, RZ, RZ, P2, !PT ;\n /*3ae0*/ MOV R16, R16 ;\n /*3af0*/ MOV R17, R17 ;\n /*3b00*/ MOV R16, R16 ;\n /*3b10*/ MOV R17, R17 ;\n /*3b20*/ R2UR UR4, R14 ;\n /*3b30*/ R2UR UR5, R15 ;\n /*3b40*/ LDG.E R16, [R16.64] ;\n /*3b50*/ FADD R11, R11, R16 ;\n /*3b60*/ MOV R22, R22 ;\n /*3b70*/ MOV R21, R21 ;\n /*3b80*/ MOV R11, R11 ;\n.L_x_28:\n /*3b90*/ BSYNC B0 ;\n.L_x_27:\n /*3ba0*/ LOP3.LUT R6, R5, R6, RZ, 0xfc, !PT ;\n /*3bb0*/ ISETP.LT.AND P2, PT, R6, RZ, PT ;\n /*3bc0*/ PLOP3.LUT P2, PT, P0, P2, PT, 0xa8, 0x0 ;\n /*3bd0*/ BSSY B0, `(.L_x_29) ;\n /*3be0*/ @P2 BRA `(.L_x_30) ;\n /*3bf0*/ MOV R16, R7 ;\n /*3c00*/ MOV R17, R8 ;\n /*3c10*/ MOV R16, R16 ;\n /*3c20*/ MOV R17, R17 ;\n /*3c30*/ R2UR UR4, R14 ;\n /*3c40*/ R2UR UR5, R15 ;\n /*3c50*/ LDG.E R16, [R16.64] ;\n /*3c60*/ FSETP.LEU.AND P2, PT, R16, 127, PT ;\n /*3c70*/ @P2 BRA `(.L_x_30) ;\n /*3c80*/ IMAD R9, R9, 0x3, RZ ;\n /*3c90*/ IMAD.WIDE R16, R9, 0x4, RZ ;\n /*3ca0*/ MOV R6, R16 ;\n /*3cb0*/ MOV R16, R17 ;\n /*3cc0*/ IADD3 R0, P2, R0, R6, RZ ;\n /*3cd0*/ IADD3.X R4, R4, R16, RZ, P2, !PT ;\n /*3ce0*/ MOV R16, R0 ;\n /*3cf0*/ MOV R17, R4 ;\n /*3d00*/ MOV R16, R16 ;\n /*3d10*/ MOV R17, R17 ;\n /*3d20*/ R2UR UR4, R14 ;\n /*3d30*/ R2UR UR5, R15 ;\n /*3d40*/ LDG.E R16, [R16.64] ;\n /*3d50*/ FADD R22, R22, R16 ;\n /*3d60*/ IADD3 R16, P2, R0, 0x4, RZ ;\n /*3d70*/ IADD3.X R17, R4, RZ, RZ, P2, !PT ;\n /*3d80*/ MOV R16, R16 ;\n /*3d90*/ MOV R17, R17 ;\n /*3da0*/ MOV R16, R16 ;\n /*3db0*/ MOV R17, R17 ;\n /*3dc0*/ R2UR UR4, R14 ;\n /*3dd0*/ R2UR UR5, R15 ;\n /*3de0*/ LDG.E R16, [R16.64] ;\n /*3df0*/ FADD R21, R21, R16 ;\n /*3e00*/ IADD3 R16, P2, R0, 0x8, RZ ;\n /*3e10*/ IADD3.X R17, R4, RZ, RZ, P2, !PT ;\n /*3e20*/ MOV R16, R16 ;\n /*3e30*/ MOV R17, R17 ;\n /*3e40*/ MOV R16, R16 ;\n /*3e50*/ MOV R17, R17 ;\n /*3e60*/ R2UR UR4, R14 ;\n /*3e70*/ R2UR UR5, R15 ;\n /*3e80*/ LDG.E R16, [R16.64] ;\n /*3e90*/ FADD R11, R11, R16 ;\n /*3ea0*/ MOV R22, R22 ;\n /*3eb0*/ MOV R21, R21 ;\n /*3ec0*/ MOV R11, R11 ;\n.L_x_30:\n /*3ed0*/ BSYNC B0 ;\n.L_x_29:\n /*3ee0*/ LOP3.LUT R5, R5, R13, RZ, 0xfc, !PT ;\n /*3ef0*/ ISETP.LT.AND P2, PT, R5, RZ, PT ;\n /*3f00*/ PLOP3.LUT P2, PT, P1, P2, PT, 0xa8, 0x0 ;\n /*3f10*/ PLOP3.LUT P2, PT, P0, P2, PT, 0xa8, 0x0 ;\n /*3f20*/ BSSY B0, `(.L_x_31) ;\n /*3f30*/ @P2 BRA `(.L_x_32) ;\n /*3f40*/ IADD3 R4, P0, R7, 0x8, RZ ;\n /*3f50*/ IADD3.X R5, R8, RZ, RZ, P0, !PT ;\n /*3f60*/ MOV R4, R4 ;\n /*3f70*/ MOV R5, R5 ;\n /*3f80*/ MOV R4, R4 ;\n /*3f90*/ MOV R5, R5 ;\n /*3fa0*/ R2UR UR4, R14 ;\n /*3fb0*/ R2UR UR5, R15 ;\n /*3fc0*/ LDG.E R4, [R4.64] ;\n /*3fd0*/ FSETP.LEU.AND P0, PT, R4, 127, PT ;\n /*3fe0*/ @P0 BRA `(.L_x_32) ;\n /*3ff0*/ IADD3 R4, P0, R2, 0x30, RZ ;\n /*4000*/ IADD3.X R5, R3, RZ, RZ, P0, !PT ;\n /*4010*/ MOV R4, R4 ;\n /*4020*/ MOV R5, R5 ;\n /*4030*/ MOV R4, R4 ;\n /*4040*/ MOV R5, R5 ;\n /*4050*/ R2UR UR4, R14 ;\n /*4060*/ R2UR UR5, R15 ;\n /*4070*/ LDG.E R4, [R4.64] ;\n /*4080*/ FADD R22, R22, R4 ;\n /*4090*/ IADD3 R4, P0, R2, 0x34, RZ ;\n /*40a0*/ IADD3.X R5, R3, RZ, RZ, P0, !PT ;\n /*40b0*/ MOV R4, R4 ;\n /*40c0*/ MOV R5, R5 ;\n /*40d0*/ MOV R4, R4 ;\n /*40e0*/ MOV R5, R5 ;\n /*40f0*/ R2UR UR4, R14 ;\n /*4100*/ R2UR UR5, R15 ;\n /*4110*/ LDG.E R4, [R4.64] ;\n /*4120*/ FADD R4, R21, R4 ;\n /*4130*/ IADD3 R2, P0, R2, 0x38, RZ ;\n /*4140*/ IADD3.X R3, R3, RZ, RZ, P0, !PT ;\n /*4150*/ MOV R2, R2 ;\n /*4160*/ MOV R3, R3 ;\n /*4170*/ MOV R2, R2 ;\n /*4180*/ MOV R3, R3 ;\n /*4190*/ R2UR UR4, R14 ;\n /*41a0*/ R2UR UR5, R15 ;\n /*41b0*/ LDG.E R2, [R2.64] ;\n /*41c0*/ FADD R2, R11, R2 ;\n /*41d0*/ MOV R22, R22 ;\n /*41e0*/ MOV R21, R4 ;\n /*41f0*/ MOV R11, R2 ;\n.L_x_32:\n /*4200*/ BSYNC B0 ;\n.L_x_31:\n /*4210*/ MOV R2, 0x18 ;\n /*4220*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*4230*/ MOV R0, R2 ;\n /*4240*/ MOV R3, R3 ;\n /*4250*/ MOV R2, R0 ;\n /*4260*/ MOV R0, R3 ;\n /*4270*/ MOV R4, RZ ;\n /*4280*/ LDC.64 R4, c[0x0][R4+0x160] ;\n /*4290*/ MOV R9, R4 ;\n /*42a0*/ MOV R10, R5 ;\n /*42b0*/ MOV R9, R9 ;\n /*42c0*/ MOV R10, R10 ;\n /*42d0*/ S2R R3, SR_TID.Y ;\n /*42e0*/ MOV R3, R3 ;\n /*42f0*/ MOV R4, c[0x0][0x4] ;\n /*4300*/ S2R R5, SR_CTAID.Y ;\n /*4310*/ MOV R5, R5 ;\n /*4320*/ MOV R6, 0x20 ;\n /*4330*/ LDC R6, c[0x0][R6+0x160] ;\n /*4340*/ MOV R6, R6 ;\n /*4350*/ IMAD R3, R5, R4, R3 ;\n /*4360*/ S2R R4, SR_TID.X ;\n /*4370*/ MOV R4, R4 ;\n /*4380*/ MOV R5, c[0x0][0x0] ;\n /*4390*/ S2R R7, SR_CTAID.X ;\n /*43a0*/ MOV R7, R7 ;\n /*43b0*/ IMAD R4, R7, R5, R4 ;\n /*43c0*/ IMAD R3, R3, R6, RZ ;\n /*43d0*/ IADD3 R3, R3, R4, RZ ;\n /*43e0*/ IMAD R3, R3, 0x3, RZ ;\n /*43f0*/ MOV R9, R9 ;\n /*4400*/ MOV R10, R10 ;\n /*4410*/ IMAD.WIDE R4, R3, 0x4, RZ ;\n /*4420*/ MOV R12, R4 ;\n /*4430*/ MOV R13, R5 ;\n /*4440*/ IADD3 R9, P0, R9, R12, RZ ;\n /*4450*/ IADD3.X R10, R10, R13, RZ, P0, !PT ;\n /*4460*/ MOV R22, R22 ;\n /*4470*/ MOV R7, 0x41c00000 ;\n /*4480*/ MOV R6, R22 ;\n /*4490*/ MOV R7, R7 ;\n /*44a0*/ MOV R3, R7 ;\n /*44b0*/ MUFU.RCP R4, R3 ;\n /*44c0*/ FADD R3, -RZ, -R3 ;\n /*44d0*/ MOV R3, R3 ;\n /*44e0*/ MOV R5, 0x3f800000 ;\n /*44f0*/ FFMA R5, R3, R4, R5 ;\n /*4500*/ FCHK P0, R6, R7 ;\n /*4510*/ FFMA R5, R4, R5, R4 ;\n /*4520*/ MOV R4, RZ ;\n /*4530*/ MOV R6, R22 ;\n /*4540*/ FFMA R4, R6, R5, R4 ;\n /*4550*/ FFMA R3, R3, R4, R6 ;\n /*4560*/ FFMA R3, R3, R5, R4 ;\n /*4570*/ MOV R8, R3 ;\n /*4580*/ MOV R3, R2 ;\n /*4590*/ MOV R6, R0 ;\n /*45a0*/ MOV R5, R12 ;\n /*45b0*/ MOV R4, R13 ;\n /*45c0*/ MOV R2, R9 ;\n /*45d0*/ MOV R0, R10 ;\n /*45e0*/ MOV R22, R22 ;\n /*45f0*/ MOV R7, R7 ;\n /*4600*/ MOV R8, R8 ;\n /*4610*/ BSSY B1, `(.L_x_33) ;\n /*4620*/ @P0 BRA `(.L_x_34) ;\n /*4630*/ BRA `(.L_x_35) ;\n.L_x_34:\n /*4640*/ MOV R22, R22 ;\n /*4650*/ MOV R7, R7 ;\n /*4660*/ MOV R9, R22 ;\n /*4670*/ MOV R10, R7 ;\n /*4680*/ MOV R7, 0x46a0 ;\n /*4690*/ CALL.REL.NOINC `($__internal_0_$__cuda_sm3x_div_rn_noftz_f32_slowpath) ;\n /*46a0*/ MOV R7, R10 ;\n /*46b0*/ MOV R7, R7 ;\n /*46c0*/ MOV R8, R7 ;\n.L_x_35:\n /*46d0*/ BSYNC B1 ;\n.L_x_33:\n /*46e0*/ MOV R7, R8 ;\n /*46f0*/ MOV R8, R2 ;\n /*4700*/ MOV R9, R0 ;\n /*4710*/ MOV R8, R8 ;\n /*4720*/ MOV R9, R9 ;\n /*4730*/ R2UR UR4, R14 ;\n /*4740*/ R2UR UR5, R15 ;\n /*4750*/ LDG.E R8, [R8.64] ;\n /*4760*/ FADD R7, R7, R8 ;\n /*4770*/ MOV R3, R3 ;\n /*4780*/ MOV R6, R6 ;\n /*4790*/ IADD3 R8, P0, R3, R5, RZ ;\n /*47a0*/ IADD3.X R9, R6, R4, RZ, P0, !PT ;\n /*47b0*/ MOV R4, R8 ;\n /*47c0*/ MOV R5, R9 ;\n /*47d0*/ MOV R4, R4 ;\n /*47e0*/ MOV R5, R5 ;\n /*47f0*/ R2UR UR4, R14 ;\n /*4800*/ R2UR UR5, R15 ;\n /*4810*/ STG.E [R4.64], R7 ;\n /*4820*/ MOV R21, R21 ;\n /*4830*/ MOV R5, 0x41c00000 ;\n /*4840*/ MOV R7, R21 ;\n /*4850*/ MOV R5, R5 ;\n /*4860*/ MOV R3, R5 ;\n /*4870*/ MUFU.RCP R4, R3 ;\n /*4880*/ FADD R3, -RZ, -R3 ;\n /*4890*/ MOV R3, R3 ;\n /*48a0*/ MOV R6, 0x3f800000 ;\n /*48b0*/ FFMA R6, R3, R4, R6 ;\n /*48c0*/ FCHK P0, R7, R5 ;\n /*48d0*/ FFMA R6, R4, R6, R4 ;\n /*48e0*/ MOV R4, RZ ;\n /*48f0*/ MOV R7, R21 ;\n /*4900*/ FFMA R4, R7, R6, R4 ;\n /*4910*/ FFMA R3, R3, R4, R7 ;\n /*4920*/ FFMA R3, R3, R6, R4 ;\n /*4930*/ MOV R6, R3 ;\n /*4940*/ MOV R3, R8 ;\n /*4950*/ MOV R4, R9 ;\n /*4960*/ MOV R21, R21 ;\n /*4970*/ MOV R5, R5 ;\n /*4980*/ MOV R6, R6 ;\n /*4990*/ BSSY B1, `(.L_x_36) ;\n /*49a0*/ @P0 BRA `(.L_x_37) ;\n /*49b0*/ BRA `(.L_x_38) ;\n.L_x_37:\n /*49c0*/ MOV R21, R21 ;\n /*49d0*/ MOV R5, R5 ;\n /*49e0*/ MOV R9, R21 ;\n /*49f0*/ MOV R10, R5 ;\n /*4a00*/ MOV R7, 0x4a20 ;\n /*4a10*/ CALL.REL.NOINC `($__internal_0_$__cuda_sm3x_div_rn_noftz_f32_slowpath) ;\n /*4a20*/ MOV R5, R10 ;\n /*4a30*/ MOV R5, R5 ;\n /*4a40*/ MOV R6, R5 ;\n.L_x_38:\n /*4a50*/ BSYNC B1 ;\n.L_x_36:\n /*4a60*/ MOV R5, R6 ;\n /*4a70*/ IADD3 R6, P0, R2, 0x4, RZ ;\n /*4a80*/ IADD3.X R7, R0, RZ, RZ, P0, !PT ;\n /*4a90*/ MOV R6, R6 ;\n /*4aa0*/ MOV R7, R7 ;\n /*4ab0*/ MOV R6, R6 ;\n /*4ac0*/ MOV R7, R7 ;\n /*4ad0*/ R2UR UR4, R14 ;\n /*4ae0*/ R2UR UR5, R15 ;\n /*4af0*/ LDG.E R6, [R6.64] ;\n /*4b00*/ FADD R5, R5, R6 ;\n /*4b10*/ IADD3 R6, P0, R3, 0x4, RZ ;\n /*4b20*/ IADD3.X R7, R4, RZ, RZ, P0, !PT ;\n /*4b30*/ MOV R6, R6 ;\n /*4b40*/ MOV R7, R7 ;\n /*4b50*/ MOV R6, R6 ;\n /*4b60*/ MOV R7, R7 ;\n /*4b70*/ R2UR UR4, R14 ;\n /*4b80*/ R2UR UR5, R15 ;\n /*4b90*/ STG.E [R6.64], R5 ;\n /*4ba0*/ MOV R11, R11 ;\n /*4bb0*/ MOV R5, 0x41c00000 ;\n /*4bc0*/ MOV R9, R11 ;\n /*4bd0*/ MOV R10, R5 ;\n /*4be0*/ MOV R5, R5 ;\n /*4bf0*/ MUFU.RCP R6, R5 ;\n /*4c00*/ FADD R7, -RZ, -R5 ;\n /*4c10*/ MOV R7, R7 ;\n /*4c20*/ MOV R8, 0x3f800000 ;\n /*4c30*/ FFMA R8, R7, R6, R8 ;\n /*4c40*/ FCHK P0, R9, R10 ;\n /*4c50*/ FFMA R8, R6, R8, R6 ;\n /*4c60*/ MOV R6, RZ ;\n /*4c70*/ MOV R9, R11 ;\n /*4c80*/ FFMA R6, R9, R8, R6 ;\n /*4c90*/ FFMA R7, R7, R6, R9 ;\n /*4ca0*/ FFMA R7, R7, R8, R6 ;\n /*4cb0*/ MOV R7, R7 ;\n /*4cc0*/ MOV R11, R11 ;\n /*4cd0*/ MOV R5, R5 ;\n /*4ce0*/ MOV R7, R7 ;\n /*4cf0*/ BSSY B1, `(.L_x_39) ;\n /*4d00*/ @P0 BRA `(.L_x_40) ;\n /*4d10*/ BRA `(.L_x_41) ;\n.L_x_40:\n /*4d20*/ MOV R11, R11 ;\n /*4d30*/ MOV R5, R5 ;\n /*4d40*/ MOV R9, R11 ;\n /*4d50*/ MOV R10, R5 ;\n /*4d60*/ MOV R7, 0x4d80 ;\n /*4d70*/ CALL.REL.NOINC `($__internal_0_$__cuda_sm3x_div_rn_noftz_f32_slowpath) ;\n /*4d80*/ MOV R5, R10 ;\n /*4d90*/ MOV R5, R5 ;\n /*4da0*/ MOV R7, R5 ;\n.L_x_41:\n /*4db0*/ BSYNC B1 ;\n.L_x_39:\n /*4dc0*/ MOV R5, R7 ;\n /*4dd0*/ IADD3 R6, P0, R2, 0x8, RZ ;\n /*4de0*/ IADD3.X R7, R0, RZ, RZ, P0, !PT ;\n /*4df0*/ MOV R6, R6 ;\n /*4e00*/ MOV R7, R7 ;\n /*4e10*/ MOV R6, R6 ;\n /*4e20*/ MOV R7, R7 ;\n /*4e30*/ R2UR UR4, R14 ;\n /*4e40*/ R2UR UR5, R15 ;\n /*4e50*/ LDG.E R6, [R6.64] ;\n /*4e60*/ FADD R5, R5, R6 ;\n /*4e70*/ IADD3 R2, P0, R3, 0x8, RZ ;\n /*4e80*/ IADD3.X R3, R4, RZ, RZ, P0, !PT ;\n /*4e90*/ MOV R2, R2 ;\n /*4ea0*/ MOV R3, R3 ;\n /*4eb0*/ MOV R2, R2 ;\n /*4ec0*/ MOV R3, R3 ;\n /*4ed0*/ R2UR UR4, R14 ;\n /*4ee0*/ R2UR UR5, R15 ;\n /*4ef0*/ STG.E [R2.64], R5 ;\n.L_x_0:\n /*4f00*/ EXIT ;\n\n\n\n\n .weak $__internal_0_$__cuda_sm3x_div_rn_noftz_f32_slowpath\n .type $__internal_0_$__cuda_sm3x_div_rn_noftz_f32_slowpath,@function\n .size $__internal_0_$__cuda_sm3x_div_rn_noftz_f32_slowpath,(.L_x_61 - $__internal_0_$__cuda_sm3x_div_rn_noftz_f32_slowpath)\n$__internal_0_$__cuda_sm3x_div_rn_noftz_f32_slowpath:\n /*4f10*/ MOV R9, R9 ;\n /*4f20*/ MOV R10, R10 ;\n /*4f30*/ MOV R8, R9 ;\n /*4f40*/ MOV R10, R10 ;\n /*4f50*/ MOV R8, R8 ;\n /*4f60*/ SHF.R.U32.HI R12, RZ, 0x17, R8 ;\n /*4f70*/ LOP3.LUT R12, R12, 0xff, RZ, 0xc0, !PT ;\n /*4f80*/ IADD3 R13, R12, -0x1, RZ ;\n /*4f90*/ MOV R16, R10 ;\n /*4fa0*/ SHF.R.U32.HI R17, RZ, 0x17, R16 ;\n /*4fb0*/ LOP3.LUT R17, R17, 0xff, RZ, 0xc0, !PT ;\n /*4fc0*/ IADD3 R18, R17, -0x1, RZ ;\n /*4fd0*/ ISETP.GT.U32.AND P0, PT, R13, 0xfd, PT ;\n /*4fe0*/ ISETP.GT.U32.AND P1, PT, R18, 0xfd, PT ;\n /*4ff0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;\n /*5000*/ MOV R9, R9 ;\n /*5010*/ MOV R10, R10 ;\n /*5020*/ MOV R8, R8 ;\n /*5030*/ MOV R12, R12 ;\n /*5040*/ MOV R19, R13 ;\n /*5050*/ MOV R13, R16 ;\n /*5060*/ MOV R16, R17 ;\n /*5070*/ MOV R17, R18 ;\n /*5080*/ BSSY B0, `(.L_x_42) ;\n /*5090*/ @P0 BRA `(.L_x_43) ;\n /*50a0*/ MOV R9, RZ ;\n /*50b0*/ MOV R9, R9 ;\n /*50c0*/ BRA `(.L_x_44) ;\n.L_x_43:\n /*50d0*/ MOV R9, R9 ;\n /*50e0*/ FADD.FTZ R18, -RZ, |R9| ;\n /*50f0*/ MOV R20, 0x7f800000 ;\n /*5100*/ MOV R20, R20 ;\n /*5110*/ FSETP.GTU.FTZ.AND P0, PT, R18, R20, PT ;\n /*5120*/ MOV R18, R18 ;\n /*5130*/ MOV R20, R20 ;\n /*5140*/ @P0 BRA `(.L_x_45) ;\n /*5150*/ MOV R10, R10 ;\n /*5160*/ FADD.FTZ R22, -RZ, |R10| ;\n /*5170*/ FSETP.GTU.FTZ.AND P0, PT, R22, R20, PT ;\n /*5180*/ MOV R22, R22 ;\n /*5190*/ @P0 BRA `(.L_x_45) ;\n /*51a0*/ LOP3.LUT R23, R13, R8, RZ, 0xfc, !PT ;\n /*51b0*/ LOP3.LUT R23, R23, 0x7fffffff, RZ, 0xc0, !PT ;\n /*51c0*/ ISETP.EQ.AND P0, PT, R23, RZ, PT ;\n /*51d0*/ @P0 BRA `(.L_x_46) ;\n /*51e0*/ FSETP.EQ.FTZ.AND P0, PT, R18, R20, PT ;\n /*51f0*/ FSETP.EQ.FTZ.AND P1, PT, R22, R20, PT ;\n /*5200*/ PLOP3.LUT P2, PT, P0, P1, PT, 0x80, 0x0 ;\n /*5210*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x80, 0x0 ;\n /*5220*/ PLOP3.LUT P1, PT, P1, PT, PT, 0x80, 0x0 ;\n /*5230*/ @P2 BRA `(.L_x_46) ;\n /*5240*/ LOP3.LUT R18, R8, 0x7fffffff, RZ, 0xc0, !PT ;\n /*5250*/ ISETP.EQ.AND P2, PT, R18, RZ, PT ;\n /*5260*/ PLOP3.LUT P1, PT, P1, P2, PT, 0xa8, 0x0 ;\n /*5270*/ @P1 BRA `(.L_x_47) ;\n /*5280*/ LOP3.LUT R18, R13, 0x7fffffff, RZ, 0xc0, !PT ;\n /*5290*/ ISETP.EQ.AND P1, PT, R18, RZ, PT ;\n /*52a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;\n /*52b0*/ @P0 BRA `(.L_x_48) ;\n /*52c0*/ ISETP.LT.AND P0, PT, R19, RZ, PT ;\n /*52d0*/ BSSY B2, `(.L_x_49) ;\n /*52e0*/ @P0 BRA `(.L_x_50) ;\n /*52f0*/ MOV R9, RZ ;\n /*5300*/ MOV R9, R9 ;\n /*5310*/ BRA `(.L_x_51) ;\n.L_x_50:\n /*5320*/ MOV R8, RZ ;\n /*5330*/ MOV R18, 0x5f800000 ;\n /*5340*/ MOV R9, R9 ;\n /*5350*/ FFMA R8, R9, R18, R8 ;\n /*5360*/ MOV R8, R8 ;\n /*5370*/ MOV R9, 0xffffffc0 ;\n /*5380*/ MOV R8, R8 ;\n /*5390*/ MOV R9, R9 ;\n.L_x_51:\n /*53a0*/ BSYNC B2 ;\n.L_x_49:\n /*53b0*/ ISETP.LT.AND P0, PT, R17, RZ, PT ;\n /*53c0*/ BSSY B2, `(.L_x_44) ;\n /*53d0*/ @P0 BRA `(.L_x_52) ;\n /*53e0*/ BRA `(.L_x_53) ;\n.L_x_52:\n /*53f0*/ MOV R13, RZ ;\n /*5400*/ MOV R17, 0x5f800000 ;\n /*5410*/ MOV R10, R10 ;\n /*5420*/ FFMA R10, R10, R17, R13 ;\n /*5430*/ MOV R10, R10 ;\n /*5440*/ IADD3 R9, R9, 0x40, RZ ;\n /*5450*/ MOV R13, R10 ;\n /*5460*/ MOV R9, R9 ;\n.L_x_53:\n /*5470*/ BSYNC B2 ;\n.L_x_44:\n /*5480*/ IADD3 R12, R12, -0x7f, RZ ;\n /*5490*/ SHF.L.U32 R10, R12, 0x17, RZ ;\n /*54a0*/ IADD3 R10, R8, -R10, RZ ;\n /*54b0*/ MOV R10, R10 ;\n /*54c0*/ SHF.L.U32 R8, R16, 0x17, RZ ;\n /*54d0*/ IADD3 R8, R8, -0x3f800000, RZ ;\n /*54e0*/ IADD3 R8, R13, -R8, RZ ;\n /*54f0*/ MOV R8, R8 ;\n /*5500*/ MUFU.RCP R13, R8 ;\n /*5510*/ FADD.FTZ R8, -RZ, -R8 ;\n /*5520*/ MOV R17, 0x3f800000 ;\n /*5530*/ FFMA R17, R8, R13, R17 ;\n /*5540*/ FFMA R17, R13, R17, R13 ;\n /*5550*/ MOV R13, RZ ;\n /*5560*/ FFMA R13, R10, R17, R13 ;\n /*5570*/ FFMA R18, R8, R13, R10 ;\n /*5580*/ FFMA R18, R18, R17, R13 ;\n /*5590*/ FFMA R8, R8, R18, R10 ;\n /*55a0*/ FFMA R10, R8, R17, R18 ;\n /*55b0*/ MOV R10, R10 ;\n /*55c0*/ SHF.R.U32.HI R13, RZ, 0x17, R10 ;\n /*55d0*/ LOP3.LUT R13, R13, 0xff, RZ, 0xc0, !PT ;\n /*55e0*/ MOV R19, 0x7f ;\n /*55f0*/ IADD3 R19, R19, -R16, RZ ;\n /*5600*/ IADD3 R19, R19, R12, RZ ;\n /*5610*/ IADD3 R19, R19, R9, RZ ;\n /*5620*/ IADD3 R13, R19, R13, RZ ;\n /*5630*/ IADD3 R9, R13, -0x1, RZ ;\n /*5640*/ ISETP.LT.U32.AND P0, PT, R9, 0xfe, PT ;\n /*5650*/ MOV R17, R17 ;\n /*5660*/ MOV R18, R18 ;\n /*5670*/ MOV R9, R8 ;\n /*5680*/ MOV R8, R10 ;\n /*5690*/ MOV R19, R19 ;\n /*56a0*/ MOV R13, R13 ;\n /*56b0*/ BSSY B2, `(.L_x_54) ;\n /*56c0*/ @P0 BRA `(.L_x_55) ;\n /*56d0*/ ISETP.GT.AND P0, PT, R13, 0xfe, PT ;\n /*56e0*/ @P0 BRA `(.L_x_56) ;\n /*56f0*/ ISETP.LT.AND P0, PT, R13, 0x1, PT ;\n /*5700*/ @P0 BRA `(.L_x_57) ;\n /*5710*/ BRA `(.L_x_58) ;\n.L_x_57:\n /*5720*/ ISETP.LT.AND P0, PT, R13, -0x18, PT ;\n /*5730*/ LOP3.LUT R8, R8, 0x80000000, RZ, 0xc0, !PT ;\n /*5740*/ MOV R8, R8 ;\n /*5750*/ @P0 BRA `(.L_x_58) ;\n /*5760*/ FFMA.RP R10, R9, R17, R18 ;\n /*5770*/ FFMA.RM R12, R9, R17, R18 ;\n /*5780*/ FSETP.NEU.FTZ.AND P0, PT, R10, R12, PT ;\n /*5790*/ FFMA.RZ R9, R9, R17, R18 ;\n /*57a0*/ MOV R9, R9 ;\n /*57b0*/ LOP3.LUT R9, R9, 0x7fffff, RZ, 0xc0, !PT ;\n /*57c0*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ;\n /*57d0*/ IADD3 R10, R13, 0x20, RZ ;\n /*57e0*/ SHF.L.U32 R10, R9, R10, RZ ;\n /*57f0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ;\n /*5800*/ ISETP.EQ.AND P2, PT, R13, RZ, PT ;\n /*5810*/ IADD3 R10, RZ, -R13, RZ ;\n /*5820*/ MOV R10, R10 ;\n /*5830*/ MOV R10, R10 ;\n /*5840*/ SEL R10, RZ, R10, P2 ;\n /*5850*/ SHF.R.U32.HI R10, RZ, R10, R9 ;\n /*5860*/ ISETP.NE.AND P2, PT, R13, RZ, PT ;\n /*5870*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x80, 0x0 ;\n /*5880*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;\n /*5890*/ SEL R9, RZ, 0x1, !P0 ;\n /*58a0*/ SHF.R.U32.HI R12, RZ, 0x1, R10 ;\n /*58b0*/ LOP3.LUT R13, R12, 0x1, RZ, 0xc0, !PT ;\n /*58c0*/ LOP3.LUT R9, R9, R13, RZ, 0xfc, !PT ;\n /*58d0*/ LOP3.LUT R9, R9, R10, RZ, 0xc0, !PT ;\n /*58e0*/ IADD3 R9, R9, R12, RZ ;\n /*58f0*/ LOP3.LUT R8, R9, R8, RZ, 0xfc, !PT ;\n /*5900*/ MOV R8, R8 ;\n /*5910*/ BRA `(.L_x_58) ;\n.L_x_56:\n /*5920*/ LOP3.LUT R8, R8, 0x80000000, RZ, 0xc0, !PT ;\n /*5930*/ LOP3.LUT R8, R8, 0x7f800000, RZ, 0xfc, !PT ;\n /*5940*/ MOV R8, R8 ;\n /*5950*/ BRA `(.L_x_58) ;\n.L_x_55:\n /*5960*/ SHF.L.U32 R19, R19, 0x17, RZ ;\n /*5970*/ IADD3 R8, R19, R8, RZ ;\n /*5980*/ MOV R8, R8 ;\n /*5990*/ BRA `(.L_x_58) ;\n.L_x_58:\n /*59a0*/ BSYNC B2 ;\n.L_x_54:\n /*59b0*/ MOV R8, R8 ;\n /*59c0*/ MOV R8, R8 ;\n /*59d0*/ MOV R8, R8 ;\n /*59e0*/ BRA `(.L_x_59) ;\n.L_x_48:\n /*59f0*/ LOP3.LUT R8, R13, R8, RZ, 0x3c, !PT ;\n /*5a00*/ LOP3.LUT R8, R8, 0x80000000, RZ, 0xc0, !PT ;\n /*5a10*/ LOP3.LUT R8, R8, 0x7f800000, RZ, 0xfc, !PT ;\n /*5a20*/ MOV R8, R8 ;\n /*5a30*/ MOV R8, R8 ;\n /*5a40*/ MOV R8, R8 ;\n /*5a50*/ BRA `(.L_x_59) ;\n.L_x_47:\n /*5a60*/ LOP3.LUT R8, R13, R8, RZ, 0x3c, !PT ;\n /*5a70*/ LOP3.LUT R8, R8, 0x80000000, RZ, 0xc0, !PT ;\n /*5a80*/ MOV R8, R8 ;\n /*5a90*/ MOV R8, R8 ;\n /*5aa0*/ MOV R8, R8 ;\n /*5ab0*/ BRA `(.L_x_59) ;\n.L_x_46:\n /*5ac0*/ MOV R8, 0xffc00000 ;\n /*5ad0*/ MOV R8, R8 ;\n /*5ae0*/ MUFU.RSQ R8, R8 ;\n /*5af0*/ MOV R8, R8 ;\n /*5b00*/ MOV R8, R8 ;\n /*5b10*/ BRA `(.L_x_59) ;\n.L_x_45:\n /*5b20*/ MOV R9, R9 ;\n /*5b30*/ MOV R10, R10 ;\n /*5b40*/ FADD.FTZ R9, R9, R10 ;\n /*5b50*/ MOV R9, R9 ;\n /*5b60*/ MOV R8, R9 ;\n /*5b70*/ BRA `(.L_x_59) ;\n.L_x_59:\n /*5b80*/ BSYNC B0 ;\n.L_x_42:\n /*5b90*/ MOV R10, R8 ;\n /*5ba0*/ MOV R8, R7 ;\n /*5bb0*/ MOV R9, 0x0 ;\n /*5bc0*/ RET.REL.NODEC R8 `(_Z28PossionImageCloningIterationPKfS0_PfS1_iii) ;\n.L_x_60:\n /*5bd0*/ BRA `(.L_x_60);\n /*5be0*/ NOP;\n /*5bf0*/ NOP;\n /*5c00*/ NOP;\n /*5c10*/ NOP;\n /*5c20*/ NOP;\n /*5c30*/ NOP;\n /*5c40*/ NOP;\n /*5c50*/ NOP;\n /*5c60*/ NOP;\n /*5c70*/ NOP;\n.L_x_61:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.protected\t_Z28PossionImageCloningIterationPKfS0_PfS1_iii ; -- Begin function _Z28PossionImageCloningIterationPKfS0_PfS1_iii\n\t.globl\t_Z28PossionImageCloningIterationPKfS0_PfS1_iii\n\t.p2align\t8\n\t.type\t_Z28PossionImageCloningIterationPKfS0_PfS1_iii,@function\n_Z28PossionImageCloningIterationPKfS0_PfS1_iii: ; @_Z28PossionImageCloningIterationPKfS0_PfS1_iii\n; %bb.0:\n\ts_clause 0x1\n\ts_load_b32 s2, s[0:1], 0x3c\n\ts_load_b64 s[4:5], s[0:1], 0x20\n\tv_bfe_u32 v1, v0, 10, 10\n\tv_and_b32_e32 v0, 0x3ff, v0\n\ts_waitcnt lgkmcnt(0)\n\ts_lshr_b32 s3, s2, 16\n\ts_and_b32 s2, s2, 0xffff\n\tv_mad_u64_u32 v[16:17], null, s15, s3, v[1:2]\n\tv_mad_u64_u32 v[17:18], null, s14, s2, v[0:1]\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_cmp_gt_i32_e32 vcc_lo, s5, v16\n\tv_cmp_gt_i32_e64 s2, s4, v17\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b32 s2, vcc_lo, s2\n\ts_and_saveexec_b32 s3, s2\n\ts_cbranch_execz .LBB0_11\n; %bb.1:\n\ts_load_b64 s[6:7], s[0:1], 0x8\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[18:19], null, v16, s4, v[17:18]\n\tv_ashrrev_i32_e32 v19, 31, v18\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[0:1], 2, v[18:19]\n\ts_waitcnt lgkmcnt(0)\n\tv_add_co_u32 v0, vcc_lo, s6, v0\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo\n\tglobal_load_b32 v0, v[0:1], off\n\ts_waitcnt vmcnt(0)\n\tv_cmp_lt_f32_e32 vcc_lo, 0x42fe0000, v0\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB0_11\n; %bb.2:\n\ts_load_b64 s[8:9], s[0:1], 0x10\n\tv_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v20, 0\n\tv_mov_b32_e32 v19, 0\n\ts_mov_b64 s[12:13], 0\n\ts_getpc_b64 s[10:11]\n\ts_add_u32 s10, s10, __const._Z28PossionImageCloningIterationPKfS0_PfS1_iii.dir@rel32@lo+8\n\ts_addc_u32 s11, s11, __const._Z28PossionImageCloningIterationPKfS0_PfS1_iii.dir@rel32@hi+16\n\ts_branch .LBB0_6\n.LBB0_3: ; in Loop: Header=BB0_6 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s3\n.LBB0_4: ; in Loop: Header=BB0_6 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s2\n.LBB0_5: ; in Loop: Header=BB0_6 Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 exec_lo, exec_lo, s14\n\ts_add_u32 s12, s12, 1\n\ts_addc_u32 s13, s13, 0\n\ts_add_u32 s10, s10, 8\n\ts_addc_u32 s11, s11, 0\n\ts_cmp_eq_u32 s12, 16\n\ts_cbranch_scc1 .LBB0_10\n.LBB0_6: ; =>This Inner Loop Header: Depth=1\n\ts_add_u32 s2, s10, -4\n\ts_addc_u32 s3, s11, -1\n\ts_mov_b32 s14, exec_lo\n\ts_load_b32 s2, s[2:3], 0x0\n\ts_waitcnt lgkmcnt(0)\n\tv_add_nc_u32_e32 v0, s2, v17\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_lt_i32_e32 -1, v0\n\ts_cbranch_execz .LBB0_5\n; %bb.7: ; in Loop: Header=BB0_6 Depth=1\n\ts_load_b32 s2, s[10:11], 0x0\n\tv_cmp_gt_i32_e32 vcc_lo, s4, v0\n\ts_waitcnt lgkmcnt(0)\n\tv_add_nc_u32_e32 v3, s2, v16\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)\n\tv_cmp_gt_i32_e64 s2, s5, v3\n\tv_cmp_lt_i32_e64 s3, -1, v3\n\ts_and_b32 s2, vcc_lo, s2\n\ts_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)\n\ts_and_b32 s3, s2, s3\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_saveexec_b32 s2, s3\n\ts_cbranch_execz .LBB0_4\n; %bb.8: ; in Loop: Header=BB0_6 Depth=1\n\tv_mad_u64_u32 v[1:2], null, v3, s4, v[0:1]\n\ts_mov_b32 s3, exec_lo\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_ashrrev_i32_e32 v2, 31, v1\n\tv_lshlrev_b64 v[2:3], 2, v[1:2]\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, s6, v2\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo\n\tglobal_load_b32 v0, v[2:3], off\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_lt_f32_e32 0x42fe0000, v0\n\ts_cbranch_execz .LBB0_3\n; %bb.9: ; in Loop: Header=BB0_6 Depth=1\n\tv_lshl_add_u32 v0, v1, 1, v1\n\ts_mov_b32 m0, s12\n\tv_mov_b32_e32 v3, 2\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_ashrrev_i32_e32 v1, 31, v0\n\tv_mov_b32_e32 v4, v3\n\tv_mov_b32_e32 v5, v3\n\tv_mov_b32_e32 v7, v3\n\ts_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[0:1], 2, v[0:1]\n\tv_add_co_u32 v0, vcc_lo, s8, v0\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo\n\tglobal_load_b96 v[22:24], v[0:1], off\n\tv_mov_b32_e32 v0, 1\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v11, v3\n\ts_delay_alu instid0(VALU_DEP_4)\n\tv_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v15, v0\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v6, v0\n\tv_mov_b32_e32 v9, v0\n\tv_mov_b32_e32 v13, v0\n\tv_mov_b32_e32 v14, v0\n\tv_movrels_b32_e32 v0, v0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_cvt_f32_ubyte0_e32 v0, v0\n\ts_waitcnt vmcnt(0)\n\tv_fmac_f32_e32 v21, v22, v0\n\tv_fmac_f32_e32 v20, v23, v0\n\tv_fmac_f32_e32 v19, v24, v0\n\ts_branch .LBB0_3\n.LBB0_10:\n\ts_load_b64 s[2:3], s[0:1], 0x0\n\tv_lshl_add_u32 v0, v18, 1, v18\n\ts_load_b64 s[0:1], s[0:1], 0x18\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_ashrrev_i32_e32 v1, 31, v0\n\tv_lshlrev_b64 v[0:1], 2, v[0:1]\n\ts_waitcnt lgkmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, s2, v0\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo\n\tv_div_scale_f32 v6, vcc_lo, v21, 0x41c00000, v21\n\tglobal_load_b32 v4, v[2:3], off\n\tv_div_scale_f32 v2, null, 0x41c00000, 0x41c00000, v21\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_rcp_f32_e32 v3, v2\n\ts_waitcnt_depctr 0xfff\n\tv_fma_f32 v5, -v2, v3, 1.0\n\tv_fmac_f32_e32 v3, v5, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_mul_f32_e32 v5, v6, v3\n\tv_fma_f32 v7, -v2, v5, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmac_f32_e32 v5, v7, v3\n\tv_fma_f32 v2, -v2, v5, v6\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)\n\tv_div_fmas_f32 v2, v2, v3, v5\n\tv_add_co_u32 v6, vcc_lo, v0, 4\n\tv_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo\n\tv_div_fixup_f32 v5, v2, 0x41c00000, v21\n\tv_add_co_u32 v2, vcc_lo, s0, v0\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_add_f32_e32 v8, v5, v4\n\tv_add_co_u32 v4, vcc_lo, s2, v6\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s3, v7, vcc_lo\n\tglobal_store_b32 v[2:3], v8, off\n\tv_div_scale_f32 v3, null, 0x41c00000, 0x41c00000, v20\n\tglobal_load_b32 v2, v[4:5], off\n\tv_div_scale_f32 v8, vcc_lo, v20, 0x41c00000, v20\n\tv_rcp_f32_e32 v4, v3\n\ts_waitcnt_depctr 0xfff\n\tv_fma_f32 v5, -v3, v4, 1.0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmac_f32_e32 v4, v5, v4\n\tv_mul_f32_e32 v5, v8, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fma_f32 v9, -v3, v5, v8\n\tv_fmac_f32_e32 v5, v9, v4\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fma_f32 v3, -v3, v5, v8\n\tv_div_fmas_f32 v3, v3, v4, v5\n\tv_add_co_u32 v4, vcc_lo, v0, 8\n\tv_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)\n\tv_div_fixup_f32 v3, v3, 0x41c00000, v20\n\tv_add_co_u32 v0, vcc_lo, s0, v6\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s1, v7, vcc_lo\n\ts_waitcnt vmcnt(0)\n\tv_add_f32_e32 v6, v3, v2\n\tv_add_co_u32 v2, vcc_lo, s2, v4\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s3, v5, vcc_lo\n\tglobal_store_b32 v[0:1], v6, off\n\tv_div_scale_f32 v1, null, 0x41c00000, 0x41c00000, v19\n\tglobal_load_b32 v0, v[2:3], off\n\tv_div_scale_f32 v6, vcc_lo, v19, 0x41c00000, v19\n\tv_rcp_f32_e32 v2, v1\n\ts_waitcnt_depctr 0xfff\n\tv_fma_f32 v3, -v1, v2, 1.0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fmac_f32_e32 v2, v3, v2\n\tv_mul_f32_e32 v3, v6, v2\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fma_f32 v7, -v1, v3, v6\n\tv_fmac_f32_e32 v3, v7, v2\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_fma_f32 v1, -v1, v3, v6\n\tv_div_fmas_f32 v1, v1, v2, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_div_fixup_f32 v1, v1, 0x41c00000, v19\n\ts_waitcnt vmcnt(0)\n\tv_add_f32_e32 v2, v1, v0\n\tv_add_co_u32 v0, vcc_lo, s0, v4\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s1, v5, vcc_lo\n\tglobal_store_b32 v[0:1], v2, off\n.LBB0_11:\n\ts_nop 0\n\ts_sendmsg sendmsg(MSG_DEALLOC_VGPRS)\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z28PossionImageCloningIterationPKfS0_PfS1_iii\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 304\n\t\t.amdhsa_user_sgpr_count 14\n\t\t.amdhsa_user_sgpr_dispatch_ptr 0\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 1\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 1\n\t\t.amdhsa_next_free_vgpr 25\n\t\t.amdhsa_next_free_sgpr 16\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end0:\n\t.size\t_Z28PossionImageCloningIterationPKfS0_PfS1_iii, .Lfunc_end0-_Z28PossionImageCloningIterationPKfS0_PfS1_iii\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 1148\n; NumSgprs: 18\n; NumVgprs: 25\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 2\n; VGPRBlocks: 3\n; NumSGPRsForWavesPerEU: 18\n; NumVGPRsForWavesPerEU: 25\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 14\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__const._Z28PossionImageCloningIterationPKfS0_PfS1_iii.dir,@object ; @__const._Z28PossionImageCloningIterationPKfS0_PfS1_iii.dir\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t4, 0x0\n__const._Z28PossionImageCloningIterationPKfS0_PfS1_iii.dir:\n\t.long\t4294967294 ; 0xfffffffe\n\t.long\t4294967294 ; 0xfffffffe\n\t.long\t0 ; 0x0\n\t.long\t4294967294 ; 0xfffffffe\n\t.long\t2 ; 0x2\n\t.long\t4294967294 ; 0xfffffffe\n\t.zero\t8,255\n\t.long\t0 ; 0x0\n\t.long\t4294967295 ; 0xffffffff\n\t.long\t1 ; 0x1\n\t.long\t4294967295 ; 0xffffffff\n\t.long\t4294967294 ; 0xfffffffe\n\t.long\t0 ; 0x0\n\t.long\t4294967295 ; 0xffffffff\n\t.long\t0 ; 0x0\n\t.long\t1 ; 0x1\n\t.long\t0 ; 0x0\n\t.long\t2 ; 0x2\n\t.long\t0 ; 0x0\n\t.long\t4294967295 ; 0xffffffff\n\t.long\t1 ; 0x1\n\t.long\t0 ; 0x0\n\t.long\t1 ; 0x1\n\t.long\t1 ; 0x1\n\t.long\t1 ; 0x1\n\t.long\t4294967294 ; 0xfffffffe\n\t.long\t2 ; 0x2\n\t.long\t0 ; 0x0\n\t.long\t2 ; 0x2\n\t.long\t2 ; 0x2\n\t.long\t2 ; 0x2\n\t.size\t__const._Z28PossionImageCloningIterationPKfS0_PfS1_iii.dir, 128\n\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 16\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 24\n .size: 8\n .value_kind: global_buffer\n - .offset: 32\n .size: 4\n .value_kind: by_value\n - .offset: 36\n .size: 4\n .value_kind: by_value\n - .offset: 40\n .size: 4\n .value_kind: by_value\n - .offset: 48\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 52\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 56\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 60\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 62\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 64\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 66\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 68\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 70\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 88\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 96\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 104\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 112\n .size: 2\n .value_kind: hidden_grid_dims\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 304\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z28PossionImageCloningIterationPKfS0_PfS1_iii\n .private_segment_fixed_size: 0\n .sgpr_count: 18\n .sgpr_spill_count: 0\n .symbol: _Z28PossionImageCloningIterationPKfS0_PfS1_iii.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 25\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162594,"cells":{"id":{"kind":"string","value":"27762e1723118ad5cec69f4834e7b604552f3eaf_O2"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z25fluidStructureInteractionPfS_S_fi --------------------------\n .section .text._Z25fluidStructureInteractionPfS_S_fi,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=14\"\n .align 128\n\n\n\n\n .global _Z25fluidStructureInteractionPfS_S_fi\n .type _Z25fluidStructureInteractionPfS_S_fi,@function\n .size _Z25fluidStructureInteractionPfS_S_fi,(.L_x_1 - _Z25fluidStructureInteractionPfS_S_fi)\n .other _Z25fluidStructureInteractionPfS_S_fi,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z25fluidStructureInteractionPfS_S_fi:\n.text._Z25fluidStructureInteractionPfS_S_fi:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ S2R R6, SR_CTAID.X ;\n /*0020*/ S2R R3, SR_TID.X ;\n /*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ;\n /*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x17c], PT ;\n /*0050*/ @P0 EXIT ;\n /*0060*/ MOV R11, 0x4 ;\n /*0070*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*0080*/ IMAD.WIDE R2, R6, R11, c[0x0][0x160] ;\n /*0090*/ IMAD.WIDE R4, R6, R11.reuse, c[0x0][0x168] ;\n /*00a0*/ LDG.E R2, [R2.64] ;\n /*00b0*/ LDG.E R7, [R4.64] ;\n /*00c0*/ FFMA R9, R2, c[0x0][0x178], R7 ;\n /*00d0*/ IMAD.WIDE R6, R6, R11, c[0x0][0x170] ;\n /*00e0*/ STG.E [R4.64], R9 ;\n /*00f0*/ LDG.E R0, [R6.64] ;\n /*0100*/ FFMA R11, R9, c[0x0][0x178], R0 ;\n /*0110*/ STG.E [R6.64], R11 ;\n /*0120*/ EXIT ;\n.L_x_0:\n /*0130*/ BRA `(.L_x_0);\n /*0140*/ NOP;\n /*0150*/ NOP;\n /*0160*/ NOP;\n /*0170*/ NOP;\n /*0180*/ NOP;\n /*0190*/ NOP;\n /*01a0*/ NOP;\n /*01b0*/ NOP;\n /*01c0*/ NOP;\n /*01d0*/ NOP;\n /*01e0*/ NOP;\n /*01f0*/ NOP;\n.L_x_1:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.weak\t__cxa_pure_virtual ; -- Begin function __cxa_pure_virtual\n\t.p2align\t2\n\t.type\t__cxa_pure_virtual,@function\n__cxa_pure_virtual: ; @__cxa_pure_virtual\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB0_1: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB0_1\n.Lfunc_end0:\n\t.size\t__cxa_pure_virtual, .Lfunc_end0-__cxa_pure_virtual\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 56\n; NumSgprs: 1\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.weak\t__cxa_deleted_virtual ; -- Begin function __cxa_deleted_virtual\n\t.p2align\t2\n\t.type\t__cxa_deleted_virtual,@function\n__cxa_deleted_virtual: ; @__cxa_deleted_virtual\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB1_1: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB1_1\n.Lfunc_end1:\n\t.size\t__cxa_deleted_virtual, .Lfunc_end1-__cxa_deleted_virtual\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 56\n; NumSgprs: 1\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hsa_signal_add\n\t.type\t__ockl_hsa_signal_add,@function\n__ockl_hsa_signal_add: ; @__ockl_hsa_signal_add\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v6, s32 offset:48 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v4, s32 offset:36 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v3, s32 offset:32 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v2\n\tscratch_load_b32 v2, off, s32 offset:32 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v1, s32 offset:28 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v1, v0\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[3:4], s32 offset:20 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v3, v1\n\tscratch_store_b64 off, v[3:4], s32 offset:12 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v0, v1\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v1, v2\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v0, s1, v0, s1\n\tv_add_co_ci_u32_e64 v2, s0, v1, s0, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s32 offset:4 ; 8-byte Folded Spill\n; %bb.1:\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 3\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, 0\n ; implicit-def: $vgpr6 : SGPR spill to VGPR lane\n\tv_writelane_b32 v6, s1, 0\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 1\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_3\n; %bb.2:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 4\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s1, 2\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 3\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_17\n\ts_branch .LBB2_4\n.LBB2_3:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 1\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s2, v6, 0\n\tv_writelane_b32 v6, s2, 4\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s2, 5\n\tv_writelane_b32 v6, s1, 6\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 7\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_13\n\ts_branch .LBB2_6\n.LBB2_4:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 5\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, -1\n\tv_writelane_b32 v6, s0, 8\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 9\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_15\n\ts_branch .LBB2_18\n.LBB2_5:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 10\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_readlane_b32 s0, v6, 11\n\ts_and_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 0\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_3\n.LBB2_6:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 12\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_7\n\ts_branch .LBB2_14\n.LBB2_7:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 12\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s2, v6, 4\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s2, 13\n\tv_writelane_b32 v6, s1, 14\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 15\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_9\n; %bb.8:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 4\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_lt_i32_e64 s2, v0, s0\n\ts_mov_b32 s0, -1\n\ts_mov_b32 s0, exec_lo\n\ts_and_not1_b32 s1, s1, exec_lo\n\ts_and_b32 s2, s2, exec_lo\n\ts_or_b32 s1, s1, s2\n\tv_writelane_b32 v6, s1, 13\n\tv_writelane_b32 v6, s0, 14\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n.LBB2_9:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s3, v6, 15\n\ts_or_b32 exec_lo, exec_lo, s3\n\tv_readlane_b32 s1, v6, 4\n\tv_readlane_b32 s2, v6, 13\n\tv_readlane_b32 s0, v6, 14\n\ts_and_b32 s0, s0, exec_lo\n\ts_and_not1_b32 s1, s1, exec_lo\n\ts_and_b32 s2, s2, exec_lo\n\ts_or_b32 s1, s1, s2\n\tv_writelane_b32 v6, s1, 5\n\tv_writelane_b32 v6, s0, 6\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_13\n.LBB2_10:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 16\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 17\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n.LBB2_11:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 18\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v6, 17\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 19\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_19\n; %bb.12:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_branch .LBB2_19\n.LBB2_13:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v6, 7\n\ts_or_b32 exec_lo, exec_lo, s2\n\tv_readlane_b32 s0, v6, 5\n\tv_readlane_b32 s1, v6, 6\n\tv_writelane_b32 v6, s1, 16\n\tv_writelane_b32 v6, s1, 17\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 18\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_11\n\ts_branch .LBB2_10\n.LBB2_14:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_branch .LBB2_7\n.LBB2_15:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 9\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_readlane_b32 s0, v6, 8\n\ts_and_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 2\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_17\n.LBB2_16:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_branch .LBB2_5\n.LBB2_17:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 3\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v6, 2\n\tv_writelane_b32 v6, s1, 11\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 10\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_5\n\ts_branch .LBB2_16\n.LBB2_18:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b32 s0, 0\n\ts_xor_b32 s0, exec_lo, -1\n\tv_writelane_b32 v6, s0, 8\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_15\n.LBB2_19:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 19\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:12 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[0:1], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:40 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_ne_u64_e64 s1, v[0:1], s[0:1]\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 20\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_21\n; %bb.20:\n\tscratch_load_b64 v[1:2], off, s32 offset:40 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s32 offset:12 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b32 v0, v[3:4], off offset:24\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v5, 0\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\tv_mov_b32_e32 v4, v5\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[1:2], v[3:4], off\n\tv_readfirstlane_b32 s0, v0\n\ts_mov_b32 s1, 0xff\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB2_21:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 20\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v6, off, s32 offset:48 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end2:\n\t.size\t__ockl_hsa_signal_add, .Lfunc_end2-__ockl_hsa_signal_add\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 1952\n; NumSgprs: 33\n; NumVgprs: 7\n; ScratchSize: 56\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hostcall_internal\n\t.type\t__ockl_hostcall_internal,@function\n__ockl_hostcall_internal: ; @__ockl_hostcall_internal\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s18, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v24, s33 offset:308 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v25, s33 offset:312 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v26, s33 offset:316 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0x150\n\tv_writelane_b32 v24, s30, 0\n\tv_writelane_b32 v24, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:132 ; 4-byte Folded Spill\n ; implicit-def: $vgpr26 : SGPR spill to VGPR lane\n\tv_writelane_b32 v26, s6, 0\n\tv_writelane_b32 v26, s7, 1\n\tscratch_store_b32 off, v18, s33 offset:128 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v16\n\tscratch_load_b32 v16, off, s33 offset:128 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:124 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v14\n\tscratch_load_b32 v14, off, s33 offset:124 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:120 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v12\n\tscratch_load_b32 v12, off, s33 offset:120 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:116 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v10\n\tscratch_load_b32 v10, off, s33 offset:116 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:112 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v8\n\tscratch_load_b32 v8, off, s33 offset:112 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:108 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v6\n\tscratch_load_b32 v6, off, s33 offset:108 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:104 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v4\n\tscratch_load_b32 v4, off, s33 offset:104 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:100 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v2\n\tscratch_load_b32 v2, off, s33 offset:100 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:96 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v1, s33 offset:92 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v1, v0\n\tscratch_load_b32 v0, off, s33 offset:92 ; 4-byte Folded Reload\n\tv_writelane_b32 v26, s15, 2\n\tv_writelane_b32 v26, s14, 3\n\tv_writelane_b32 v26, s13, 4\n\tv_writelane_b32 v26, s12, 5\n\tv_writelane_b32 v26, s10, 6\n\tv_writelane_b32 v26, s11, 7\n\tv_writelane_b32 v26, s8, 8\n\tv_writelane_b32 v26, s9, 9\n\tv_writelane_b32 v26, s4, 10\n\tv_writelane_b32 v26, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\ts_waitcnt vmcnt(8)\n\tv_mov_b32_e32 v18, v16\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr15 killed $vgpr15 def $vgpr15_vgpr16 killed $exec\n\ts_waitcnt vmcnt(7)\n\tv_mov_b32_e32 v16, v14\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec\n\ts_waitcnt vmcnt(6)\n\tv_mov_b32_e32 v14, v12\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\ts_waitcnt vmcnt(5)\n\tv_mov_b32_e32 v12, v10\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\ts_waitcnt vmcnt(4)\n\tv_mov_b32_e32 v10, v8\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\ts_waitcnt vmcnt(3)\n\tv_mov_b32_e32 v8, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v6, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[17:18], s33 offset:84 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[15:16], s33 offset:76 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[13:14], s33 offset:68 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[11:12], s33 offset:60 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[9:10], s33 offset:52 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[7:8], s33 offset:44 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[5:6], s33 offset:36 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[3:4], s33 offset:28 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s0, -1\n\tv_mbcnt_lo_u32_b32 v0, s0, s1\n\tv_mbcnt_hi_u32_b32 v0, s0, v0\n\t;;#ASMSTART\n\t;;#ASMEND\n\tv_mov_b32_e32 v3, v0\n\tscratch_store_b32 off, v3, s33 offset:24 ; 4-byte Folded Spill\n\tv_readfirstlane_b32 s0, v0\n\tscratch_store_b64 off, v[1:2], s33 offset:16 ; 8-byte Folded Spill\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, s1\n\tv_writelane_b32 v26, s0, 12\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v0, 0\n\tv_mov_b32_e32 v1, 0\n\tscratch_store_b64 off, v[0:1], s33 offset:8 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 13\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_6\n; %bb.1:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_mov_b64 s[2:3], 24\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:160 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b64 s[2:3], 40\n\tv_mov_b32_e32 v4, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v5, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v4, s1, v4, s1\n\tv_add_co_ci_u32_e64 v6, s0, v5, s0, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tscratch_store_b64 off, v[4:5], s33 offset:152 ; 8-byte Folded Spill\n\tglobal_load_b64 v[5:6], v[0:1], off\n\tglobal_load_b64 v[10:11], v[0:1], off offset:40\n\tv_mov_b32_e32 v8, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v11\n\tv_and_b32_e64 v4, v4, v8\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v7, v10\n\tv_and_b32_e64 v12, v7, v9\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_mov_b32_e32 v4, v12\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[10:11], s0, v4, s1, 0\n\tv_mov_b32_e32 v14, v11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec\n\tv_mov_b32_e32 v15, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[12:13], s0, v[12:13]\n\tv_mov_b32_e32 v4, v12\n\tv_mad_u64_u32 v[12:13], s1, v4, s1, v[14:15]\n ; kill: def $vgpr12 killed $vgpr12 killed $vgpr12_vgpr13 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s1\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_lshlrev_b64 v[13:14], s0, v[12:13]\n\tv_mov_b32_e32 v7, v14\n\tv_mov_b32_e32 v11, v10\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\tv_mov_b32_e32 v4, v12\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v10, v13\n\tv_mov_b32_e32 v7, v11\n\tv_or_b32_e64 v10, v7, v10\n ; kill: def $vgpr10 killed $vgpr10 def $vgpr10_vgpr11 killed $exec\n\tv_mov_b32_e32 v11, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v11\n\tv_add_co_u32 v4, s0, v4, v7\n\tv_add_co_ci_u32_e64 v6, s0, v5, v6, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tglobal_load_b64 v[4:5], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v10, v5\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s0, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:144 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:136 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 15\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_5\n.LBB3_2: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 14\n\tscratch_load_b64 v[2:3], off, s33 offset:144 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:160 ; 8-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:152 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[5:6], v[4:5], off\n\tglobal_load_b64 v[10:11], v[7:8], off\n\tv_mov_b32_e32 v8, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v11\n\tv_and_b32_e64 v4, v4, v8\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v7, v10\n\tv_and_b32_e64 v12, v7, v9\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_mov_b32_e32 v4, v12\n\ts_mov_b32 s2, 24\n\tv_mad_u64_u32 v[10:11], s0, v4, s2, 0\n\tv_mov_b32_e32 v14, v11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec\n\tv_mov_b32_e32 v15, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[12:13], s0, v[12:13]\n\tv_mov_b32_e32 v4, v12\n\tv_mad_u64_u32 v[12:13], s2, v4, s2, v[14:15]\n ; kill: def $vgpr12 killed $vgpr12 killed $vgpr12_vgpr13 killed $exec\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s2\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_lshlrev_b64 v[13:14], s0, v[12:13]\n\tv_mov_b32_e32 v7, v14\n\tv_mov_b32_e32 v11, v10\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\tv_mov_b32_e32 v4, v12\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v10, v13\n\tv_mov_b32_e32 v7, v11\n\tv_or_b32_e64 v10, v7, v10\n ; kill: def $vgpr10 killed $vgpr10 def $vgpr10_vgpr11 killed $exec\n\tv_mov_b32_e32 v11, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v11\n\tv_add_co_u32 v4, s0, v4, v7\n\tv_add_co_ci_u32_e64 v6, s0, v5, v6, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tglobal_load_b64 v[4:5], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v10, v5\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e64 s0, v[0:1], v[2:3]\n\ts_or_b32 s0, s0, s1\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:144 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:168 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 16\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_2\n; %bb.3:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 16\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.4:\n\tscratch_load_b64 v[0:1], off, s33 offset:168 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:136 ; 8-byte Folded Spill\n.LBB3_5:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:136 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:8 ; 8-byte Folded Spill\n.LBB3_6:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 13\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:8 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[4:5], s0, v[4:5]\n\tv_mov_b32_e32 v2, v4\n\tv_readfirstlane_b32 s4, v3\n\tv_readfirstlane_b32 s2, v2\n ; implicit-def: $sgpr5\n ; implicit-def: $sgpr3\n ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3\n\ts_mov_b32 s3, s5\n\ts_lshl_b64 s[2:3], s[2:3], s0\n\ts_mov_b32 s0, 0\n ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5\n\ts_mov_b32 s5, s0\n\ts_or_b64 s[2:3], s[2:3], s[4:5]\n\tv_writelane_b32 v26, s2, 17\n\tv_writelane_b32 v26, s3, 18\n\tglobal_load_b64 v[2:3], v[0:1], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:200 ; 8-byte Folded Spill\n\ts_mov_b64 s[6:7], 40\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s7\n\tv_add_co_u32 v2, s4, v2, s4\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s4\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tglobal_load_b64 v[3:4], v[0:1], off offset:40\n\ts_mov_b32 s0, s3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v4\n\tv_and_b32_e64 v2, s0, v2\n\ts_mov_b32 s0, s2\n ; kill: def $vgpr3 killed $vgpr3 killed $vgpr3_vgpr4 killed $exec\n\tv_and_b32_e64 v3, s0, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v5, v3\n\tscratch_store_b64 off, v[5:6], s33 offset:184 ; 8-byte Folded Spill\n\tglobal_load_b64 v[1:2], v[0:1], off offset:8\n\ts_mov_b32 s0, 12\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s0, v0, v3\n\tv_add_co_ci_u32_e64 v2, s0, v1, v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:176 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], exec\n\tv_writelane_b32 v26, s2, 19\n\tv_writelane_b32 v26, s3, 20\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 21\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_8\n; %bb.7:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 19\n\tv_readlane_b32 s1, v26, 20\n\tscratch_load_b32 v2, off, s33 offset:96 ; 4-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v5, v0\n\ts_mov_b32 s3, 24\n\tv_mad_u64_u32 v[3:4], s2, v5, s3, 0\n\tv_mov_b32_e32 v9, v4\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v5, s2\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v5\n\ts_mov_b32 s2, 32\n\tv_lshrrev_b64 v[0:1], s2, v[0:1]\n\tv_mov_b32_e32 v5, v0\n\tv_mad_u64_u32 v[0:1], s3, v5, s3, v[9:10]\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v5, s3\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v5\n\tv_lshlrev_b64 v[9:10], s2, v[0:1]\n\tv_mov_b32_e32 v1, v10\n\tv_mov_b32_e32 v4, v3\n\ts_mov_b32 s2, 0\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v0, v5\n\tv_or_b32_e64 v0, v0, v1\n\tv_mov_b32_e32 v3, v9\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v5, v1, v3\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v0\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v3, v6\n\tv_add_co_u32 v0, s2, v0, v4\n\tv_add_co_ci_u32_e64 v3, s2, v1, v3, s2\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tglobal_store_b32 v[0:1], v2, off offset:16\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tglobal_store_b64 v[0:1], v[2:3], off offset:8\n\tv_mov_b32_e32 v2, 1\n\tglobal_store_b32 v[0:1], v2, off offset:20\n.LBB3_8:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[2:3], off, s33 offset:84 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:76 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:68 ; 8-byte Folded Reload\n\tscratch_load_b64 v[8:9], off, s33 offset:60 ; 8-byte Folded Reload\n\tscratch_load_b64 v[10:11], off, s33 offset:52 ; 8-byte Folded Reload\n\tscratch_load_b64 v[12:13], off, s33 offset:44 ; 8-byte Folded Reload\n\tscratch_load_b64 v[14:15], off, s33 offset:36 ; 8-byte Folded Reload\n\tscratch_load_b64 v[16:17], off, s33 offset:28 ; 8-byte Folded Reload\n\tscratch_load_b64 v[22:23], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:24 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v18, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v18\n\ts_mov_b32 s0, 6\n\ts_waitcnt vmcnt(0)\n\tv_lshlrev_b64 v[20:21], s0, v[0:1]\n\tv_mov_b32_e32 v0, v22\n\tv_mov_b32_e32 v19, v20\n\tv_mov_b32_e32 v1, v23\n\tv_mov_b32_e32 v18, v21\n\tv_add_co_u32 v0, s0, v0, v19\n\tv_add_co_ci_u32_e64 v18, s0, v1, v18, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v18\n\tscratch_store_b64 off, v[0:1], s33 offset:216 ; 8-byte Folded Spill\n\tglobal_store_b64 v[0:1], v[16:17], off\n\ts_mov_b64 s[4:5], 8\n\tv_mov_b32_e32 v16, v0\n\ts_mov_b32 s2, s4\n\tv_mov_b32_e32 v17, v1\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v16, s2, v16, s2\n\tv_add_co_ci_u32_e64 v18, s0, v17, s0, s2\n ; kill: def $vgpr16 killed $vgpr16 def $vgpr16_vgpr17 killed $exec\n\tv_mov_b32_e32 v17, v18\n\tscratch_store_b64 off, v[16:17], s33 offset:208 ; 8-byte Folded Spill\n\tglobal_store_b64 v[0:1], v[14:15], off offset:8\n\tglobal_store_b64 v[0:1], v[12:13], off offset:16\n\tglobal_store_b64 v[0:1], v[10:11], off offset:24\n\tglobal_store_b64 v[0:1], v[8:9], off offset:32\n\tglobal_store_b64 v[0:1], v[6:7], off offset:40\n\tglobal_store_b64 v[0:1], v[4:5], off offset:48\n\tglobal_store_b64 v[0:1], v[2:3], off offset:56\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 22\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_13\n; %bb.9:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[5:6], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:192 ; 8-byte Folded Reload\n\ts_mov_b64 s[4:5], 32\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s4\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:240 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:32 glc\n\ts_waitcnt vmcnt(1)\n\tglobal_load_b64 v[7:8], v[7:8], off\n\ts_mov_b32 s0, s3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v8\n\tv_and_b32_e64 v4, v4, s0\n\ts_mov_b32 s1, s2\n ; kill: def $vgpr7 killed $vgpr7 killed $vgpr7_vgpr8 killed $exec\n\tv_and_b32_e64 v7, v7, s1\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v4\n\tv_mov_b32_e32 v4, v7\n\ts_mov_b32 s3, 24\n\tv_mad_u64_u32 v[9:10], s2, v4, s3, 0\n\tv_mov_b32_e32 v11, v10\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v4, s2\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\ts_mov_b32 s2, 32\n\tv_lshrrev_b64 v[7:8], s2, v[7:8]\n\tv_mov_b32_e32 v4, v7\n\tv_mad_u64_u32 v[7:8], s3, v4, s3, v[11:12]\n ; kill: def $vgpr7 killed $vgpr7 killed $vgpr7_vgpr8 killed $exec\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v4, s3\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v4\n\tv_lshlrev_b64 v[7:8], s2, v[7:8]\n\tv_mov_b32_e32 v11, v8\n ; kill: def $vgpr9 killed $vgpr9 killed $vgpr9_vgpr10 killed $exec\n\ts_mov_b32 s2, 0\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v4, v10\n\tv_or_b32_e64 v4, v4, v11\n\tv_mov_b32_e32 v8, v7\n\tv_mov_b32_e32 v7, v9\n\tv_or_b32_e64 v8, v7, v8\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v8\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v9\n\tv_add_co_u32 v4, s2, v4, v7\n\tv_add_co_ci_u32_e64 v6, s2, v5, v6, s2\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tscratch_store_b64 off, v[4:5], s33 offset:232 ; 8-byte Folded Spill\n\tglobal_store_b64 v[4:5], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s1\n\tv_mov_b32_e32 v10, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s2, v[0:1], v[2:3]\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s2, 23\n\tv_writelane_b32 v26, s0, 24\n\tscratch_store_b64 off, v[0:1], s33 offset:224 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 25\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_14\n.LBB3_10: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 24\n\tv_readlane_b32 s1, v26, 23\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[2:3], off, s33 offset:224 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:240 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:232 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_store_b64 v[4:5], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n\ts_mov_b32 s1, s3\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v10, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s1, v[0:1], v[2:3]\n\ts_or_b32 s0, s1, s0\n\tv_writelane_b32 v26, s1, 23\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 24\n\tscratch_store_b64 off, v[0:1], s33 offset:224 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 26\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_10\n; %bb.11:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 26\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.12:\n\ts_branch .LBB3_14\n.LBB3_13:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_branch .LBB3_15\n.LBB3_14:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 25\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s15, v26, 2\n\tv_readlane_b32 s14, v26, 3\n\tv_readlane_b32 s13, v26, 4\n\tv_readlane_b32 s12, v26, 5\n\tv_readlane_b32 s10, v26, 6\n\tv_readlane_b32 s11, v26, 7\n\tv_readlane_b32 s8, v26, 8\n\tv_readlane_b32 s9, v26, 9\n\tv_readlane_b32 s6, v26, 0\n\tv_readlane_b32 s7, v26, 1\n\tv_readlane_b32 s4, v26, 10\n\tv_readlane_b32 s5, v26, 11\n\tscratch_load_b32 v31, off, s33 offset:132 ; 4-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_mov_b32 s0, 32\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[0:1], s0, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v2\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hsa_signal_add@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hsa_signal_add@rel32@hi+12\n\tv_mov_b32_e32 v2, 1\n\tv_mov_b32_e32 v3, 0\n\tv_mov_b32_e32 v4, 3\n\ts_swappc_b64 s[30:31], s[0:1]\n\ts_branch .LBB3_13\n.LBB3_15:\n\tscratch_load_b64 v[6:7], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[3:4], s0, v2, s1, 0\n\tv_mov_b32_e32 v8, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v2\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[0:1]\n\tv_mov_b32_e32 v2, v0\n\tv_mad_u64_u32 v[0:1], s1, v2, s1, v[8:9]\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_lshlrev_b64 v[1:2], s0, v[0:1]\n\tv_mov_b32_e32 v5, v2\n ; kill: def $vgpr3 killed $vgpr3 killed $vgpr3_vgpr4 killed $exec\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_mov_b32_e32 v0, v4\n\tv_or_b32_e64 v0, v0, v5\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v1, v3\n\tv_or_b32_e64 v4, v1, v2\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v1, v6\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v1, s0, v1, v3\n\tv_add_co_ci_u32_e64 v0, s0, v0, v2, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b64 s[2:3], 20\n\tv_mov_b32_e32 v0, v1\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v1, v2\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v0, s1, v0, s1\n\tv_add_co_ci_u32_e64 v2, s0, v1, s0, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:248 ; 8-byte Folded Spill\n.LBB3_16: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 12\n\ts_mov_b32 s0, 1\n\tv_mov_b32_e32 v0, 1\n\tscratch_store_b32 off, v0, s33 offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 27\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_18\n; %bb.17: ; in Loop: Header=BB3_16 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:248 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b32 v0, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b32 s0, 1\n\tv_and_b32_e64 v0, v0, s0\n\tscratch_store_b32 off, v0, s33 offset:256 ; 4-byte Folded Spill\n.LBB3_18: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 27\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s33 offset:256 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s1, v0\n\ts_mov_b32 s0, -1\n\ts_mov_b32 s2, 0\n\ts_cmp_eq_u32 s1, s2\n\tv_writelane_b32 v26, s0, 28\n\ts_mov_b32 s17, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_cbranch_scc1 .LBB3_20\n; %bb.19: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_sleep 1\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v26, s0, 28\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n.LBB3_20: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 28\n\tv_cndmask_b32_e64 v0, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v0, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n\ts_cbranch_vccnz .LBB3_16\n; %bb.21:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[0:1], off, s33 offset:208 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:216 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[2:3], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:268 ; 8-byte Folded Spill\n\tglobal_load_b64 v[0:1], v[0:1], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:260 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 29\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_27\n; %bb.22:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:192 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[11:12], v[2:3], off\n\ts_mov_b64 s[4:5], 1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v11\n\ts_mov_b32 s1, s4\n\tv_mov_b32_e32 v3, v12\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v4, v2\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v5, v3\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v4, s1, v4, s1\n\tv_add_co_ci_u32_e64 v6, s0, v5, s0, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_eq_u64_e64 s0, v[4:5], s[0:1]\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v6, v5\n\tv_cndmask_b32_e64 v10, v6, v7, s0\n\tv_mov_b32_e32 v3, v2\n\tv_mov_b32_e32 v2, v4\n\tv_cndmask_b32_e64 v4, v2, v3, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v8, v4\n\tv_mov_b32_e32 v9, v10\n\tv_mov_b32_e32 v2, v8\n\tv_mov_b32_e32 v3, v9\n\tscratch_store_b64 off, v[2:3], s33 offset:300 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], 24\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v5, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v5\n\tscratch_store_b64 off, v[2:3], s33 offset:292 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:24 glc\n\tglobal_load_b64 v[6:7], v[0:1], off\n\tv_mov_b32_e32 v5, v9\n\tv_mov_b32_e32 v13, v12\n\tv_and_b32_e64 v5, v5, v13\n ; kill: def $vgpr8 killed $vgpr8 killed $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v11\n\tv_and_b32_e64 v8, v8, v9\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v5\n\tv_mov_b32_e32 v5, v8\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[11:12], s0, v5, s1, 0\n\tv_mov_b32_e32 v13, v12\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v5, s0\n ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec\n\tv_mov_b32_e32 v14, v5\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[8:9], s0, v[8:9]\n\tv_mov_b32_e32 v5, v8\n\tv_mad_u64_u32 v[8:9], s1, v5, s1, v[13:14]\n ; kill: def $vgpr8 killed $vgpr8 killed $vgpr8_vgpr9 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v5, s1\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v5\n\tv_lshlrev_b64 v[8:9], s0, v[8:9]\n\tv_mov_b32_e32 v13, v9\n ; kill: def $vgpr11 killed $vgpr11 killed $vgpr11_vgpr12 killed $exec\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v5, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v5\n\tv_mov_b32_e32 v5, v12\n\tv_or_b32_e64 v5, v5, v13\n\tv_mov_b32_e32 v9, v8\n\tv_mov_b32_e32 v8, v11\n\tv_or_b32_e64 v11, v8, v9\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v5\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v8, v11\n\tv_mov_b32_e32 v6, v7\n\tv_mov_b32_e32 v7, v12\n\tv_add_co_u32 v5, s0, v5, v8\n\tv_add_co_ci_u32_e64 v7, s0, v6, v7, s0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v7\n\tscratch_store_b64 off, v[5:6], s33 offset:284 ; 8-byte Folded Spill\n\tglobal_store_b64 v[5:6], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s2, v[0:1], v[2:3]\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s2, 30\n\tv_writelane_b32 v26, s0, 31\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\tscratch_store_b64 off, v[0:1], s33 offset:276 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n ; implicit-def: $vgpr26 : SGPR spill to VGPR lane\n\tv_writelane_b32 v26, s0, 0\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_26\n.LBB3_23: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v25, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v25, 31\n\tv_readlane_b32 s1, v25, 30\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\tscratch_load_b64 v[2:3], off, s33 offset:276 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:292 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:300 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:284 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_store_b64 v[6:7], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v10, v5\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s1, v[0:1], v[2:3]\n\ts_or_b32 s0, s1, s0\n\tv_writelane_b32 v25, s1, 30\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v25, s1, 31\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v25, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\tscratch_store_b64 off, v[0:1], s33 offset:276 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_23\n; %bb.24:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.25:\n.LBB3_26:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 0\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB3_27:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[3:4], off, s33 offset:260 ; 8-byte Folded Reload\n\tscratch_load_b64 v[1:2], off, s33 offset:268 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v3\n\tv_mov_b32_e32 v3, v4\n\tv_readlane_b32 s30, v24, 0\n\tv_readlane_b32 s31, v24, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v24, off, s33 offset:308 ; 4-byte Folded Reload\n\tscratch_load_b32 v25, off, s33 offset:312 ; 4-byte Folded Reload\n\tscratch_load_b32 v26, off, s33 offset:316 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xfffffeb0\n\ts_mov_b32 s33, s18\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end3:\n\t.size\t__ockl_hostcall_internal, .Lfunc_end3-__ockl_hostcall_internal\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 5344\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 392\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hostcall_preview\n\t.type\t__ockl_hostcall_preview,@function\n__ockl_hostcall_preview: ; @__ockl_hostcall_preview\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v27, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tv_writelane_b32 v27, s33, 0\n\tv_writelane_b32 v27, s30, 1\n\tv_writelane_b32 v27, s31, 2\n\tv_mov_b32_e32 v18, v16\n\tv_mov_b32_e32 v17, v15\n\tv_mov_b32_e32 v16, v14\n\tv_mov_b32_e32 v15, v13\n\tv_mov_b32_e32 v14, v12\n\tv_mov_b32_e32 v13, v11\n\tv_mov_b32_e32 v12, v10\n\tv_mov_b32_e32 v11, v9\n\tv_mov_b32_e32 v10, v8\n\tv_mov_b32_e32 v9, v7\n\tv_mov_b32_e32 v8, v6\n\tv_mov_b32_e32 v7, v5\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v5, v3\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s0, s[0:1], 0x0\n\ts_mov_b32 s1, 0x1f4\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_i32 s0, s1\n\ts_mov_b32 s1, 0x50\n\ts_mov_b32 s0, 24\n\ts_cselect_b32 s0, s0, s1\n\ts_load_b64 s[0:1], s[8:9], s0 offset:0x0\n\ts_waitcnt lgkmcnt(0)\n\ts_mov_b32 s3, s0\n\ts_mov_b32 s2, 32\n\ts_lshr_b64 s[0:1], s[0:1], s2\n\ts_mov_b32 s2, s0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_internal@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_internal@rel32@hi+12\n\tv_mov_b32_e32 v0, s3\n\tv_mov_b32_e32 v1, s2\n\tv_readlane_b32 s30, v27, 1\n\tv_readlane_b32 s31, v27, 2\n\tv_readlane_b32 s33, v27, 0\n\ts_xor_saveexec_b32 s2, -1\n\tscratch_load_b32 v27, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s2\n\ts_setpc_b64 s[0:1]\n.Lfunc_end4:\n\t.size\t__ockl_hostcall_preview, .Lfunc_end4-__ockl_hostcall_preview\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 272\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 400\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_stderr_begin\n\t.type\t__ockl_fprintf_stderr_begin,@function\n__ockl_fprintf_stderr_begin: ; @__ockl_fprintf_stderr_begin\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s16, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v28, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 16\n\tv_writelane_b32 v28, s30, 0\n\tv_writelane_b32 v28, s31, 1\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\tv_mov_b32_e32 v1, 33\n\tv_mov_b32_e32 v3, 1\n\tv_mov_b32_e32 v16, 0\n\tv_mov_b32_e32 v2, v16\n\tv_mov_b32_e32 v4, v16\n\tv_mov_b32_e32 v5, v16\n\tv_mov_b32_e32 v6, v16\n\tv_mov_b32_e32 v7, v16\n\tv_mov_b32_e32 v8, v16\n\tv_mov_b32_e32 v9, v16\n\tv_mov_b32_e32 v10, v16\n\tv_mov_b32_e32 v11, v16\n\tv_mov_b32_e32 v12, v16\n\tv_mov_b32_e32 v13, v16\n\tv_mov_b32_e32 v14, v16\n\tv_mov_b32_e32 v15, v16\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_store_b32 off, v1, s33 ; 4-byte Folded Spill\n ; kill: def $vgpr1 killed $vgpr3 killed $exec\n\tscratch_load_b32 v3, off, s33 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v3\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v28, 0\n\tv_readlane_b32 s31, v28, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v28, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, -16\n\ts_mov_b32 s33, s16\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end5:\n\t.size\t__ockl_fprintf_stderr_begin, .Lfunc_end5-__ockl_fprintf_stderr_begin\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 228\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 416\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_append_string_n\n\t.type\t__ockl_fprintf_append_string_n,@function\n__ockl_fprintf_append_string_n: ; @__ockl_fprintf_append_string_n\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s20, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v32, s33 offset:704 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v33, s33 offset:708 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v34, s33 offset:712 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0x2d0\n\tv_writelane_b32 v32, s30, 0\n\tv_writelane_b32 v32, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:68 ; 4-byte Folded Spill\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\tv_writelane_b32 v34, s6, 0\n\tv_writelane_b32 v34, s7, 1\n\tscratch_store_b32 off, v6, s33 offset:60 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v5, s33 offset:56 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v4, s33 offset:64 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v6, v3\n\tscratch_load_b32 v3, off, s33 offset:64 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v4, v2\n\tscratch_load_b32 v2, off, s33 offset:60 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v4, s33 offset:52 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v7, v1\n\tscratch_load_b32 v1, off, s33 offset:56 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v5, v0\n\tscratch_load_b32 v0, off, s33 offset:52 ; 4-byte Folded Reload\n\tv_writelane_b32 v34, s15, 2\n\tv_writelane_b32 v34, s14, 3\n\tv_writelane_b32 v34, s13, 4\n\tv_writelane_b32 v34, s12, 5\n\tv_writelane_b32 v34, s10, 6\n\tv_writelane_b32 v34, s11, 7\n\tv_writelane_b32 v34, s8, 8\n\tv_writelane_b32 v34, s9, 9\n\tv_writelane_b32 v34, s4, 10\n\tv_writelane_b32 v34, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v1\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v7\n\tscratch_store_b64 off, v[3:4], s33 offset:44 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v3, v0\n\tscratch_store_b64 off, v[3:4], s33 offset:36 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s0, 0\n\tv_cmp_eq_u32_e64 s0, v2, s0\n\tv_mov_b32_e32 v4, v6\n\ts_mov_b64 s[2:3], 2\n\ts_mov_b32 s1, s3\n\tv_or_b32_e64 v2, v4, s1\n\tv_mov_b32_e32 v3, v5\n\ts_mov_b32 s1, s2\n\tv_or_b32_e64 v5, v3, s1\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v2\n\tv_mov_b32_e32 v2, v6\n\tv_cndmask_b32_e64 v4, v2, v4, s0\n\tv_mov_b32_e32 v2, v5\n\tv_cndmask_b32_e64 v2, v2, v3, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:28 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_ne_u64_e64 s0, v[0:1], s[0:1]\n ; implicit-def: $sgpr4_sgpr5_sgpr6_sgpr7\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tv_mov_b32_e32 v2, s6\n\tv_mov_b32_e32 v3, s7\n\tscratch_store_b128 off, v[0:3], s33 offset:12 ; 16-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 12\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_3\n\ts_branch .LBB6_2\n.LBB6_1:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v34, 2\n\tv_readlane_b32 s14, v34, 3\n\tv_readlane_b32 s13, v34, 4\n\tv_readlane_b32 s12, v34, 5\n\tv_readlane_b32 s10, v34, 6\n\tv_readlane_b32 s11, v34, 7\n\tv_readlane_b32 s8, v34, 8\n\tv_readlane_b32 s9, v34, 9\n\tv_readlane_b32 s6, v34, 0\n\tv_readlane_b32 s7, v34, 1\n\tv_readlane_b32 s4, v34, 10\n\tv_readlane_b32 s5, v34, 11\n\tscratch_load_b32 v31, off, s33 offset:68 ; 4-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:28 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v3\n\tv_and_b32_e64 v4, v0, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v0, v2\n\tv_and_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_mov_b32_e32 v4, v1\n\ts_mov_b64 s[0:1], 32\n\ts_mov_b32 s2, s1\n\tv_or_b32_e64 v4, v4, s2\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_or_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_mov_b32_e32 v1, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[2:3], s0, v[2:3]\n ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\tv_mov_b32_e32 v16, 0\n\tscratch_store_b32 off, v16, s33 offset:88 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v16\n\tv_mov_b32_e32 v4, v16\n\tv_mov_b32_e32 v5, v16\n\tv_mov_b32_e32 v6, v16\n\tv_mov_b32_e32 v7, v16\n\tv_mov_b32_e32 v8, v16\n\tv_mov_b32_e32 v9, v16\n\tv_mov_b32_e32 v10, v16\n\tv_mov_b32_e32 v11, v16\n\tv_mov_b32_e32 v12, v16\n\tv_mov_b32_e32 v13, v16\n\tv_mov_b32_e32 v14, v16\n\tv_mov_b32_e32 v15, v16\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_mov_b32_e32 v6, v1\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v4, v3\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v6\n\tv_mov_b32_e32 v2, v5\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b128 off, v[0:3], s33 offset:72 ; 16-byte Folded Spill\n\ts_branch .LBB6_63\n.LBB6_2:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b64 v[4:5], off, s33 offset:36 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:44 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:28 ; 8-byte Folded Reload\n\ts_mov_b64 s[0:1], 2\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v1, v3\n\tv_and_b32_e64 v8, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v0, v2\n\tv_and_b32_e64 v2, v0, s0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v8\n\tscratch_store_b64 off, v[2:3], s33 offset:124 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], -3\n\ts_mov_b32 s2, s1\n\tv_and_b32_e64 v2, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_and_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v10, v1\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\ts_mov_b64 s[2:3], 0\n\ts_mov_b32 s0, s3\n\ts_mov_b32 s1, s2\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v9, s1\n\tv_mov_b32_e32 v8, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v10\n\tv_mov_b32_e32 v2, v9\n\tv_mov_b32_e32 v3, v8\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v34, s0, 13\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[6:7], s33 offset:116 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[4:5], s33 offset:108 ; 8-byte Folded Spill\n\tscratch_store_b128 off, v[0:3], s33 offset:92 ; 16-byte Folded Spill\n\ts_branch .LBB6_4\n.LBB6_3:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 12\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b128 v[0:3], off, s33 offset:12 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:72 ; 16-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 14\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_63\n\ts_branch .LBB6_1\n.LBB6_4: ; =>This Loop Header: Depth=1\n ; Child Loop BB6_8 Depth 2\n ; Child Loop BB6_16 Depth 2\n ; Child Loop BB6_24 Depth 2\n ; Child Loop BB6_32 Depth 2\n ; Child Loop BB6_40 Depth 2\n ; Child Loop BB6_48 Depth 2\n ; Child Loop BB6_56 Depth 2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 13\n\tscratch_load_b64 v[6:7], off, s33 offset:124 ; 8-byte Folded Reload\n\tscratch_load_b128 v[8:11], off, s33 offset:92 ; 16-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:116 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:108 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:176 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[3:4], s33 offset:168 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 15\n\ts_mov_b64 s[2:3], 56\n\tv_cmp_gt_u64_e64 s0, v[3:4], s[2:3]\n\tv_mov_b32_e32 v1, v9\n\tv_mov_b32_e32 v2, v8\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v8, v2\n\tv_mov_b32_e32 v9, v1\n\tv_mov_b32_e32 v0, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or_b32_e64 v0, v0, v5\n\tv_mov_b32_e32 v5, v8\n\tv_or_b32_e64 v5, v5, v6\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v0\n\tv_mov_b32_e32 v0, v6\n\tv_cndmask_b32_e64 v0, v0, v1, s0\n\tv_mov_b32_e32 v1, v5\n\tv_cndmask_b32_e64 v1, v1, v2, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_cmp_lt_u64_e64 s1, v[3:4], s[2:3]\n\tv_mov_b32_e32 v0, v4\n\ts_mov_b32 s0, s3\n\tv_cndmask_b32_e64 v5, s0, v0, s1\n\tv_mov_b32_e32 v0, v3\n\ts_mov_b32 s0, s2\n\tv_cndmask_b32_e64 v0, s0, v0, s1\n\tscratch_store_b32 off, v0, s33 offset:164 ; 4-byte Folded Spill\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v3, v0\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:156 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:148 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:140 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:132 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 16\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_6\n; %bb.5: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:164 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 17\n\tv_writelane_b32 v34, s0, 18\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:184 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_11\n\ts_branch .LBB6_8\n.LBB6_6: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 16\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 20\n\tscratch_load_b64 v[0:1], off, s33 offset:140 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:132 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:212 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:208 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:200 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 21\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_12\n; %bb.7: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:212 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:208 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:200 ; 8-byte Folded Spill\n\ts_branch .LBB6_12\n.LBB6_8: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 18\n\tv_readlane_b32 s2, v34, 17\n\tscratch_load_b64 v[4:5], off, s33 offset:192 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:176 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 17\n\tv_writelane_b32 v34, s1, 18\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:220 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 22\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_8\n; %bb.9: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.10: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:220 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:184 ; 8-byte Folded Spill\n.LBB6_11: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 19\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:140 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 20\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:132 ; 8-byte Folded Spill\n\ts_branch .LBB6_6\n.LBB6_12: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:212 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:208 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:200 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:256 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:252 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:244 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:236 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:228 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 23\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_14\n; %bb.13: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:252 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 24\n\tv_writelane_b32 v34, s0, 25\n\tscratch_store_b64 off, v[2:3], s33 offset:272 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:264 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 26\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_19\n\ts_branch .LBB6_16\n.LBB6_14: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 23\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 27\n\tscratch_load_b64 v[0:1], off, s33 offset:236 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:228 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:292 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:288 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:280 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 28\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_20\n; %bb.15: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:244 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:252 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:292 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:288 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:280 ; 8-byte Folded Spill\n\ts_branch .LBB6_20\n.LBB6_16: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 25\n\tv_readlane_b32 s2, v34, 24\n\tscratch_load_b64 v[4:5], off, s33 offset:272 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:252 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:244 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 24\n\tv_writelane_b32 v34, s1, 25\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:272 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:300 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 29\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_16\n; %bb.17: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.18: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:300 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:264 ; 8-byte Folded Spill\n.LBB6_19: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 26\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:244 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:264 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:236 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 27\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:228 ; 8-byte Folded Spill\n\ts_branch .LBB6_14\n.LBB6_20: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 28\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:292 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:288 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:280 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:336 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:332 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:324 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:316 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:308 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 30\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_22\n; %bb.21: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:332 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v33, s2, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tv_writelane_b32 v34, s0, 0\n\tscratch_store_b64 off, v[2:3], s33 offset:352 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:344 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_27\n\ts_branch .LBB6_24\n.LBB6_22: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v33, 30\n\ts_or_saveexec_b32 s0, s0\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v34, 2\n\tscratch_load_b64 v[0:1], off, s33 offset:316 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:308 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:372 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:368 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:360 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 3\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_28\n; %bb.23: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:324 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:332 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:372 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:368 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:360 ; 8-byte Folded Spill\n\ts_branch .LBB6_28\n.LBB6_24: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 0\n\tv_readlane_b32 s2, v33, 31\n\tscratch_load_b64 v[4:5], off, s33 offset:352 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:332 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:324 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v33, s2, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tv_writelane_b32 v34, s1, 0\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:352 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:380 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 4\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_24\n; %bb.25: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.26: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:380 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:344 ; 8-byte Folded Spill\n.LBB6_27: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:324 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:344 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:316 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:308 ; 8-byte Folded Spill\n\ts_branch .LBB6_22\n.LBB6_28: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 3\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:372 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:368 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:360 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:416 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:412 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:404 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:396 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:388 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 5\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_30\n; %bb.29: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:412 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 6\n\tv_writelane_b32 v34, s0, 7\n\tscratch_store_b64 off, v[2:3], s33 offset:432 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:424 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 8\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_35\n\ts_branch .LBB6_32\n.LBB6_30: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 5\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 9\n\tscratch_load_b64 v[0:1], off, s33 offset:396 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:388 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:452 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:448 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:440 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 10\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_36\n; %bb.31: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:404 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:412 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:452 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:448 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:440 ; 8-byte Folded Spill\n\ts_branch .LBB6_36\n.LBB6_32: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 7\n\tv_readlane_b32 s2, v34, 6\n\tscratch_load_b64 v[4:5], off, s33 offset:432 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:412 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:404 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 6\n\tv_writelane_b32 v34, s1, 7\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:432 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:460 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 11\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_32\n; %bb.33: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 11\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.34: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:460 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:424 ; 8-byte Folded Spill\n.LBB6_35: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 8\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:404 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:424 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:396 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 9\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:388 ; 8-byte Folded Spill\n\ts_branch .LBB6_30\n.LBB6_36: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 10\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:452 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:448 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:440 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:496 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:492 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:484 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:476 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:468 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 12\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_38\n; %bb.37: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:492 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 13\n\tv_writelane_b32 v34, s0, 14\n\tscratch_store_b64 off, v[2:3], s33 offset:512 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:504 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 15\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_43\n\ts_branch .LBB6_40\n.LBB6_38: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 12\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 16\n\tscratch_load_b64 v[0:1], off, s33 offset:476 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:468 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:532 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:528 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:520 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 17\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_44\n; %bb.39: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:484 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:492 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:532 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:528 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:520 ; 8-byte Folded Spill\n\ts_branch .LBB6_44\n.LBB6_40: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 14\n\tv_readlane_b32 s2, v34, 13\n\tscratch_load_b64 v[4:5], off, s33 offset:512 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:492 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:484 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 13\n\tv_writelane_b32 v34, s1, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:512 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:540 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 18\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_40\n; %bb.41: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 18\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.42: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:540 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:504 ; 8-byte Folded Spill\n.LBB6_43: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:484 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:504 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:476 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 16\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:468 ; 8-byte Folded Spill\n\ts_branch .LBB6_38\n.LBB6_44: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 17\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:532 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:528 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:520 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:576 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:572 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:564 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:556 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:548 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_46\n; %bb.45: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:572 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 20\n\tv_writelane_b32 v34, s0, 21\n\tscratch_store_b64 off, v[2:3], s33 offset:592 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:584 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 22\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_51\n\ts_branch .LBB6_48\n.LBB6_46: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 19\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 23\n\tscratch_load_b64 v[0:1], off, s33 offset:556 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:548 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:612 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:608 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:600 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 24\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_52\n; %bb.47: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:564 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:572 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:612 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:608 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:600 ; 8-byte Folded Spill\n\ts_branch .LBB6_52\n.LBB6_48: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 21\n\tv_readlane_b32 s2, v34, 20\n\tscratch_load_b64 v[4:5], off, s33 offset:592 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:572 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:564 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 20\n\tv_writelane_b32 v34, s1, 21\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:592 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:620 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 25\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_48\n; %bb.49: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 25\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.50: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:620 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:584 ; 8-byte Folded Spill\n.LBB6_51: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:564 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:584 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:556 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 23\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:548 ; 8-byte Folded Spill\n\ts_branch .LBB6_46\n.LBB6_52: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 24\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:612 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:608 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:600 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:648 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:644 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:636 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s33 offset:628 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 26\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_54\n; %bb.53: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:644 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 27\n\tv_writelane_b32 v34, s0, 28\n\tscratch_store_b64 off, v[2:3], s33 offset:664 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:656 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 29\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_59\n\ts_branch .LBB6_56\n.LBB6_54: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 26\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:628 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:672 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 30\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_60\n; %bb.55: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[2:3], off, s33 offset:636 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tflat_load_u8 v0, v[2:3]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v4, v[2:3] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v5, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v7, v1\n\tv_mov_b32_e32 v4, v6\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v5\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v4\n\tflat_load_u8 v4, v[2:3] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v8, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v4\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v10, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or3_b32 v4, v4, v5, v10\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v5, v8\n\tv_mov_b32_e32 v1, v6\n\tv_or3_b32 v0, v0, v1, v5\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v4, s1, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[6:7], s2, v[4:5]\n\tflat_load_u8 v4, v[2:3] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v4, s1, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[8:9], s0, v[4:5]\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v10, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or3_b32 v4, v4, v5, v10\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v5, v8\n\tv_mov_b32_e32 v1, v6\n\tv_or3_b32 v0, v0, v1, v5\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:6\n\tv_mov_b32_e32 v6, 0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[4:5], s0, v[4:5]\n\tflat_load_u8 v2, v[2:3] offset:7\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v6\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[6:7], s0, v[2:3]\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v8, v7\n\tv_mov_b32_e32 v3, v5\n\tv_or3_b32 v2, v2, v3, v8\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v3, v6\n\tv_mov_b32_e32 v1, v4\n\tv_or3_b32 v0, v0, v1, v3\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:672 ; 8-byte Folded Spill\n\ts_branch .LBB6_60\n.LBB6_56: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 28\n\tv_readlane_b32 s2, v34, 27\n\tscratch_load_b64 v[4:5], off, s33 offset:664 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:644 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:636 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 27\n\tv_writelane_b32 v34, s1, 28\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:664 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:680 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_56\n; %bb.57: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 31\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.58: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:680 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:656 ; 8-byte Folded Spill\n.LBB6_59: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:656 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:628 ; 8-byte Folded Spill\n\ts_branch .LBB6_54\n.LBB6_60: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v34, 30\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v33, 2\n\tv_readlane_b32 s14, v33, 3\n\tv_readlane_b32 s13, v33, 4\n\tv_readlane_b32 s12, v33, 5\n\tv_readlane_b32 s10, v33, 6\n\tv_readlane_b32 s11, v33, 7\n\tv_readlane_b32 s8, v33, 8\n\tv_readlane_b32 s9, v33, 9\n\tv_readlane_b32 s6, v33, 0\n\tv_readlane_b32 s7, v33, 1\n\tv_readlane_b32 s4, v33, 10\n\tv_readlane_b32 s5, v33, 11\n\tscratch_load_b64 v[0:1], off, s33 offset:156 ; 8-byte Folded Reload\n\tscratch_load_b32 v31, off, s33 offset:68 ; 4-byte Folded Reload\n\tscratch_load_b64 v[19:20], off, s33 offset:648 ; 8-byte Folded Reload\n\tscratch_load_b64 v[21:22], off, s33 offset:576 ; 8-byte Folded Reload\n\tscratch_load_b64 v[23:24], off, s33 offset:496 ; 8-byte Folded Reload\n\tscratch_load_b64 v[25:26], off, s33 offset:416 ; 8-byte Folded Reload\n\tscratch_load_b64 v[27:28], off, s33 offset:336 ; 8-byte Folded Reload\n\tscratch_load_b64 v[29:30], off, s33 offset:256 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:148 ; 8-byte Folded Reload\n\tscratch_load_b64 v[17:18], off, s33 offset:672 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(9)\n\tv_mov_b32_e32 v1, v0\n\ts_mov_b32 s0, 28\n\tv_mov_b32_e32 v0, 2\n\tv_lshl_add_u32 v1, v1, v0, s0\n\ts_mov_b32 s0, 0x1e0\n\tv_and_b32_e64 v5, v1, s0\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v1, 0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v1\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v1, v3\n\tv_and_b32_e64 v1, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v4, v2\n\tv_and_b32_e64 v7, v4, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v4, v6\n\tv_or_b32_e64 v1, v1, v4\n\tv_mov_b32_e32 v4, v7\n ; kill: def $vgpr5 killed $vgpr5 killed $vgpr5_vgpr6 killed $exec\n\tv_or_b32_e64 v4, v4, v5\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v1\n\tv_mov_b32_e32 v1, v4\n\ts_mov_b32 s0, 32\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\tv_writelane_b32 v34, s0, 0\n\tv_lshrrev_b64 v[2:3], s0, v[2:3]\n ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec\n\tv_lshrrev_b64 v[3:4], s0, v[29:30]\n\tv_mov_b32_e32 v4, v3\n\tv_lshrrev_b64 v[5:6], s0, v[27:28]\n\tv_mov_b32_e32 v6, v5\n\tv_lshrrev_b64 v[7:8], s0, v[25:26]\n\tv_mov_b32_e32 v8, v7\n\tv_lshrrev_b64 v[9:10], s0, v[23:24]\n\tv_mov_b32_e32 v10, v9\n\tv_lshrrev_b64 v[11:12], s0, v[21:22]\n\tv_mov_b32_e32 v12, v11\n\tv_lshrrev_b64 v[13:14], s0, v[19:20]\n\tv_mov_b32_e32 v14, v13\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[15:16], s0, v[17:18]\n\tv_mov_b32_e32 v16, v15\n\tv_mov_b32_e32 v3, v29\n\tv_mov_b32_e32 v5, v27\n\tv_mov_b32_e32 v7, v25\n\tv_mov_b32_e32 v9, v23\n\tv_mov_b32_e32 v11, v21\n\tv_mov_b32_e32 v13, v19\n\tv_mov_b32_e32 v15, v17\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b64 v[4:5], off, s33 offset:168 ; 8-byte Folded Reload\n\tscratch_load_b64 v[12:13], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b64 v[10:11], off, s33 offset:156 ; 8-byte Folded Reload\n\tv_readlane_b32 s1, v33, 15\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v7, v2\n\tv_mov_b32_e32 v6, v3\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v2, v7\n\tv_mov_b32_e32 v3, v6\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v6, v4\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v5, v11\n\tv_sub_co_u32 v6, s0, v6, v7\n\tv_sub_co_ci_u32_e64 v4, s0, v4, v5, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v4\n\tv_mov_b32_e32 v4, v12\n\tv_mov_b32_e32 v9, v10\n\tv_mov_b32_e32 v5, v13\n\tv_mov_b32_e32 v8, v11\n\tv_add_co_u32 v4, s0, v4, v9\n\tv_add_co_ci_u32_e64 v8, s0, v5, v8, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v8\n\ts_mov_b64 s[2:3], 0\n\tv_cmp_eq_u64_e64 s0, v[6:7], s[2:3]\n\ts_or_b32 s0, s0, s1\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v33, s1, 13\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[6:7], s33 offset:116 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[4:5], s33 offset:108 ; 8-byte Folded Spill\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v6, v2\n\tv_mov_b32_e32 v5, v1\n\tv_mov_b32_e32 v4, v0\n\tscratch_store_b128 off, v[4:7], s33 offset:92 ; 16-byte Folded Spill\n\tscratch_store_b128 off, v[0:3], s33 offset:688 ; 16-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:8 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_4\n; %bb.61:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:8 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.62:\n\tscratch_load_b128 v[0:3], off, s33 offset:688 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:12 ; 16-byte Folded Spill\n\ts_branch .LBB6_3\n.LBB6_63:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 14\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b128 v[3:6], off, s33 offset:72 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v0, v3\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v32, 0\n\tv_readlane_b32 s31, v32, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v32, off, s33 offset:704 ; 4-byte Folded Reload\n\tscratch_load_b32 v33, off, s33 offset:708 ; 4-byte Folded Reload\n\tscratch_load_b32 v34, off, s33 offset:712 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xfffffd30\n\ts_mov_b32 s33, s20\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end6:\n\t.size\t__ockl_fprintf_append_string_n, .Lfunc_end6-__ockl_fprintf_append_string_n\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 11984\n; NumSgprs: 36\n; NumVgprs: 35\n; ScratchSize: 1120\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_append_args\n\t.type\t__ockl_fprintf_append_args,@function\n__ockl_fprintf_append_args: ; @__ockl_fprintf_append_args\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s19, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v28, s33 offset:8 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v29, s33 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 32\n\tv_writelane_b32 v28, s30, 0\n\tv_writelane_b32 v28, s31, 1\n\tscratch_store_b32 off, v17, s33 offset:4 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v17, v2\n\tv_mov_b32_e32 v18, v0\n\tscratch_load_b32 v0, off, s33 offset:4 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v15\n ; kill: def $vgpr20 killed $vgpr16 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v13\n ; kill: def $vgpr20 killed $vgpr14 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v11\n ; kill: def $vgpr20 killed $vgpr12 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v9\n ; kill: def $vgpr20 killed $vgpr10 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v7\n ; kill: def $vgpr20 killed $vgpr8 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v5\n ; kill: def $vgpr20 killed $vgpr6 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v3\n ; kill: def $vgpr20 killed $vgpr4 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr18 killed $vgpr18 def $vgpr18_vgpr19 killed $exec\n\tv_mov_b32_e32 v19, v1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s0, v0, s0\n\tv_mov_b32_e32 v1, v19\n\ts_mov_b64 s[2:3], 2\n\ts_mov_b32 s1, s3\n\tv_or_b32_e64 v0, v1, s1\n\tv_mov_b32_e32 v2, v18\n\ts_mov_b32 s1, s2\n\tv_or_b32_e64 v18, v2, s1\n ; kill: def $vgpr18 killed $vgpr18 def $vgpr18_vgpr19 killed $exec\n\tv_mov_b32_e32 v19, v0\n\tv_mov_b32_e32 v0, v19\n\tv_cndmask_b32_e64 v0, v0, v1, s0\n\tv_mov_b32_e32 v1, v18\n\tv_cndmask_b32_e64 v1, v1, v2, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v0, v2\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\tv_and_b32_e64 v0, v0, s2\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_and_b32_e64 v1, v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\tv_mov_b32_e32 v18, v0\n\ts_mov_b32 s0, 5\n\tv_lshlrev_b64 v[17:18], s0, v[17:18]\n\tv_mov_b32_e32 v0, v2\n\tv_mov_b32_e32 v19, v18\n\tv_or_b32_e64 v0, v0, v19\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v17\n\tv_or_b32_e64 v17, v1, v2\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\tv_mov_b32_e32 v18, v0\n\tv_mov_b32_e32 v1, v17\n\ts_mov_b32 s0, 32\n ; implicit-def: $vgpr29 : SGPR spill to VGPR lane\n\tv_writelane_b32 v29, s0, 0\n\tv_lshrrev_b64 v[17:18], s0, v[17:18]\n\tv_mov_b32_e32 v2, v17\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v29, 0\n\tscratch_store_b32 off, v1, s33 ; 4-byte Folded Spill\n ; kill: def $vgpr1 killed $vgpr3 killed $exec\n\tscratch_load_b32 v3, off, s33 ; 4-byte Folded Reload\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v1, s1\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v3\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v28, 0\n\tv_readlane_b32 s31, v28, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v28, off, s33 offset:8 ; 4-byte Folded Reload\n\tscratch_load_b32 v29, off, s33 offset:12 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xffffffe0\n\ts_mov_b32 s33, s19\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end7:\n\t.size\t__ockl_fprintf_append_args, .Lfunc_end7-__ockl_fprintf_append_args\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 452\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 432\n; MemoryBound: 0\n\t.text\n\t.hidden\t__assert_fail ; -- Begin function __assert_fail\n\t.weak\t__assert_fail\n\t.p2align\t2\n\t.type\t__assert_fail,@function\n__assert_fail: ; @__assert_fail\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s27, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v35, s33 offset:176 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v36, s33 offset:180 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v37, s33 offset:184 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xc0\n\tv_writelane_b32 v35, s30, 0\n\tv_writelane_b32 v35, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:168 ; 4-byte Folded Spill\n ; implicit-def: $vgpr37 : SGPR spill to VGPR lane\n\tv_writelane_b32 v37, s6, 0\n\tv_writelane_b32 v37, s7, 1\n\tscratch_store_b32 off, v5, s33 offset:164 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v3, s33 offset:160 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v5, v2\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v7, v0\n\tscratch_load_b32 v0, off, s33 offset:160 ; 4-byte Folded Reload\n\tv_writelane_b32 v37, s15, 2\n\tv_writelane_b32 v37, s14, 3\n\tv_writelane_b32 v37, s13, 4\n\tv_writelane_b32 v37, s12, 5\n\tv_writelane_b32 v37, s10, 6\n\tv_writelane_b32 v37, s11, 7\n\tv_writelane_b32 v37, s8, 8\n\tv_writelane_b32 v37, s9, 9\n\tv_writelane_b32 v37, s4, 10\n\tv_writelane_b32 v37, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v6, v0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b64 s[0:1], src_private_base\n\ts_mov_b32 s2, 32\n\ts_lshr_b64 s[0:1], s[0:1], s2\n\ts_mov_b32 s24, s0\n\tv_writelane_b32 v37, s24, 12\n\ts_mov_b32 s20, s33\n ; kill: def $sgpr20 killed $sgpr20 def $sgpr20_sgpr21\n\ts_mov_b32 s21, s24\n\ts_mov_b64 s[0:1], s[20:21]\n\tv_writelane_b32 v37, s0, 13\n\tv_writelane_b32 v37, s1, 14\n\ts_add_i32 s0, s33, 8\n\ts_mov_b32 s18, s0\n ; kill: def $sgpr18 killed $sgpr18 def $sgpr18_sgpr19\n\ts_mov_b32 s19, s24\n\ts_mov_b64 s[0:1], s[18:19]\n\tv_writelane_b32 v37, s0, 15\n\tv_writelane_b32 v37, s1, 16\n\ts_add_i32 s0, s33, 16\n\ts_mov_b32 s2, s0\n ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3\n\ts_mov_b32 s3, s24\n\ts_mov_b64 s[0:1], s[2:3]\n\tv_writelane_b32 v37, s0, 17\n\tv_writelane_b32 v37, s1, 18\n\ts_add_i32 s1, s33, 24\n\ts_mov_b32 s0, s1\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s24\n\ts_mov_b64 s[16:17], s[0:1]\n\tv_writelane_b32 v37, s16, 19\n\tv_writelane_b32 v37, s17, 20\n\ts_add_i32 s17, s33, 32\n\ts_mov_b32 s16, s17\n ; kill: def $sgpr16 killed $sgpr16 def $sgpr16_sgpr17\n\ts_mov_b32 s17, s24\n\tv_writelane_b32 v37, s16, 21\n\tv_writelane_b32 v37, s17, 22\n\ts_mov_b64 s[22:23], s[16:17]\n\tv_writelane_b32 v37, s22, 23\n\tv_writelane_b32 v37, s23, 24\n\ts_add_i32 s23, s33, 0x50\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v37, s22, 25\n\tv_writelane_b32 v37, s23, 26\n\tv_writelane_b32 v37, s22, 27\n\tv_writelane_b32 v37, s23, 28\n\ts_add_i32 s23, s33, 0x58\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v37, s22, 29\n\tv_writelane_b32 v37, s23, 30\n ; implicit-def: $vgpr36 : SGPR spill to VGPR lane\n\tv_writelane_b32 v37, s22, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:148 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_writelane_b32 v36, s23, 0\n\ts_add_i32 s23, s33, 0x60\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 1\n\tv_writelane_b32 v36, s23, 2\n\ts_add_i32 s23, s33, 0x68\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 3\n\tv_writelane_b32 v36, s23, 4\n\ts_add_i32 s23, s33, 0x70\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 5\n\tv_writelane_b32 v36, s23, 6\n\ts_add_i32 s23, s33, 0x78\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 7\n\tv_writelane_b32 v36, s23, 8\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_mov_b32_e32 v0, s20\n\tv_mov_b32_e32 v1, s21\n\tflat_store_b64 v[0:1], v[7:8]\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tflat_store_b64 v[0:1], v[5:6]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b32 v[0:1], v4\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, s33 offset:156 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+35\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+43\n\tglobal_load_b128 v[0:3], v0, s[0:1]\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:128\n\tscratch_load_b64 v[0:1], off, s33 offset:136\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_d16_hi_b8 v[3:4], v2 offset:45\n\ts_mov_b32 s1, 24\n\tv_lshrrev_b32_e64 v5, s1, v2\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v5 offset:46\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v2 offset:43\n\ts_mov_b32 s0, 8\n\tv_lshrrev_b32_e64 v4, s0, v2\n\tv_mov_b32_e32 v2, s16\n\tv_mov_b32_e32 v3, s17\n\tflat_store_b8 v[2:3], v4 offset:44\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_d16_hi_b8 v[1:2], v0 offset:41\n\tv_lshrrev_b32_e64 v3, s1, v0\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v3 offset:42\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v0 offset:39\n\tv_lshrrev_b32_e64 v2, s0, v0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b8 v[0:1], v2 offset:40\n\tscratch_load_b64 v[0:1], off, s33 offset:128\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_d16_hi_b8 v[3:4], v2 offset:37\n\tv_lshrrev_b32_e64 v5, s1, v2\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v5 offset:38\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v2 offset:35\n\tv_lshrrev_b32_e64 v4, s0, v2\n\tv_mov_b32_e32 v2, s16\n\tv_mov_b32_e32 v3, s17\n\tflat_store_b8 v[2:3], v4 offset:36\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_d16_hi_b8 v[1:2], v0 offset:33\n\tv_lshrrev_b32_e64 v3, s1, v0\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v3 offset:34\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v0 offset:31\n\tv_lshrrev_b32_e64 v2, s0, v0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b8 v[0:1], v2 offset:32\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+20\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+28\n\ts_load_b128 s[0:3], s[0:1], 0x0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v5, s3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b128 v[0:1], v[2:5] offset:16\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+4\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+12\n\ts_load_b128 s[0:3], s[0:1], 0x0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v5, s3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b128 v[0:1], v[2:5]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_stderr_begin@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_stderr_begin@rel32@hi+12\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v2, off, s33 offset:156 ; 4-byte Folded Reload\n\tv_readlane_b32 s2, v37, 25\n\tv_readlane_b32 s3, v37, 26\n\tv_readlane_b32 s0, v37, 29\n\tv_readlane_b32 s1, v37, 30\n\tv_mov_b32_e32 v3, v0\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b64 v[0:1], v[3:4]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0)\n\tflat_store_b32 v[0:1], v2\n; %bb.1:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 23\n\tv_readlane_b32 s1, v36, 24\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s3, v37, 2\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 9\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_2: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s3, v37, 2\n\tv_readlane_b32 s0, v37, 10\n\tv_readlane_b32 s1, v37, 9\n\tv_writelane_b32 v37, s1, 11\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 12\n\tv_writelane_b32 v37, s0, 13\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 14\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_4\n; %bb.3: ; in Loop: Header=BB8_2 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 12\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 13\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_4: ; in Loop: Header=BB8_2 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 14\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 11\n\tv_readlane_b32 s1, v37, 13\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 10\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 9\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 15\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_2\n; %bb.5:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.6:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 23\n\tv_readlane_b32 s3, v36, 24\n\tv_readlane_b32 s4, v37, 1\n\tv_readlane_b32 s5, v37, 2\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, s2\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.7:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 23\n\tv_readlane_b32 s1, v37, 24\n\tv_readlane_b32 s2, v37, 31\n\tv_readlane_b32 s3, v36, 0\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v5, v4\n\tv_mov_b32_e32 v6, v0\n\ts_mov_b32 s3, 32\n\ts_lshr_b64 s[16:17], s[0:1], s3\n\ts_mov_b32 s2, s16\n\tv_lshrrev_b64 v[0:1], s3, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[5:6], s3, v[5:6]\n ; kill: def $vgpr5 killed $vgpr5 killed $vgpr5_vgpr6 killed $exec\n\ts_mov_b32 s3, s0\n\tv_mov_b32_e32 v0, v2\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v2, s3\n\tv_mov_b32_e32 v3, s2\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.8:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 3\n\tv_readlane_b32 s1, v37, 4\n\tv_readlane_b32 s2, v36, 15\n\tv_readlane_b32 s3, v36, 16\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 16\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_9: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 3\n\tv_readlane_b32 s3, v37, 4\n\tv_readlane_b32 s0, v37, 17\n\tv_readlane_b32 s1, v37, 16\n\tv_writelane_b32 v37, s1, 18\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 19\n\tv_writelane_b32 v37, s0, 20\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 21\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_11\n; %bb.10: ; in Loop: Header=BB8_9 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 19\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 20\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_11: ; in Loop: Header=BB8_9 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 18\n\tv_readlane_b32 s1, v37, 20\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 17\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 16\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 22\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_9\n; %bb.12:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.13:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 15\n\tv_readlane_b32 s3, v36, 16\n\tv_readlane_b32 s4, v37, 3\n\tv_readlane_b32 s5, v37, 4\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.14:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 15\n\tv_readlane_b32 s3, v37, 16\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_writelane_b32 v36, s0, 23\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\tscratch_store_b32 off, v6, s33 offset:172 ; 4-byte Folded Spill\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tscratch_load_b32 v17, off, s33 offset:172 ; 4-byte Folded Reload\n\tv_readlane_b32 s2, v37, 17\n\tv_readlane_b32 s3, v37, 18\n\tv_readlane_b32 s0, v36, 23\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v3, v[0:1]\n\ts_waitcnt vmcnt(1) lgkmcnt(1)\n\tv_lshrrev_b64 v[0:1], s0, v[4:5]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v4\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_args@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_args@rel32@hi+12\n\tv_mov_b32_e32 v2, 1\n\tv_mov_b32_e32 v4, v17\n\tv_mov_b32_e32 v5, v17\n\tv_mov_b32_e32 v6, v17\n\tv_mov_b32_e32 v7, v17\n\tv_mov_b32_e32 v8, v17\n\tv_mov_b32_e32 v9, v17\n\tv_mov_b32_e32 v10, v17\n\tv_mov_b32_e32 v11, v17\n\tv_mov_b32_e32 v12, v17\n\tv_mov_b32_e32 v13, v17\n\tv_mov_b32_e32 v14, v17\n\tv_mov_b32_e32 v15, v17\n\tv_mov_b32_e32 v16, v17\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.15:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 5\n\tv_readlane_b32 s1, v37, 6\n\tv_readlane_b32 s2, v36, 19\n\tv_readlane_b32 s3, v36, 20\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 24\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_16: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 5\n\tv_readlane_b32 s3, v37, 6\n\tv_readlane_b32 s0, v37, 25\n\tv_readlane_b32 s1, v37, 24\n\tv_writelane_b32 v37, s1, 26\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 27\n\tv_writelane_b32 v37, s0, 28\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 29\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_18\n; %bb.17: ; in Loop: Header=BB8_16 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 27\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 28\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_18: ; in Loop: Header=BB8_16 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 26\n\tv_readlane_b32 s1, v37, 28\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 25\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 24\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 30\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_16\n; %bb.19:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 30\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.20:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 19\n\tv_readlane_b32 s3, v36, 20\n\tv_readlane_b32 s4, v37, 5\n\tv_readlane_b32 s5, v37, 6\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.21:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 19\n\tv_readlane_b32 s3, v37, 20\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.22:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 7\n\tv_readlane_b32 s1, v37, 8\n\tv_readlane_b32 s2, v36, 13\n\tv_readlane_b32 s3, v36, 14\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_23: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v36, 7\n\tv_readlane_b32 s3, v36, 8\n ; implicit-def: $vgpr37 : SGPR spill to VGPR lane\n\tv_readlane_b32 s0, v37, 0\n\tv_readlane_b32 s1, v36, 31\n\tv_writelane_b32 v37, s1, 1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 2\n\tv_writelane_b32 v37, s0, 3\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 4\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_25\n; %bb.24: ; in Loop: Header=BB8_23 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 2\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 3\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_25: ; in Loop: Header=BB8_23 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s1, v37, 3\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 0\n\ts_mov_b32 s1, s0\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v36, s1, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 5\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_23\n; %bb.26:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 5\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.27:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 13\n\tv_readlane_b32 s3, v36, 14\n\tv_readlane_b32 s4, v37, 7\n\tv_readlane_b32 s5, v37, 8\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.28:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 13\n\tv_readlane_b32 s3, v37, 14\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 1\n\ts_swappc_b64 s[30:31], s[0:1]\n\ts_cbranch_execnz .LBB8_30\n; %bb.29:\n\tv_readlane_b32 s30, v35, 0\n\tv_readlane_b32 s31, v35, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v35, off, s33 offset:176 ; 4-byte Folded Reload\n\tscratch_load_b32 v36, off, s33 offset:180 ; 4-byte Folded Reload\n\tscratch_load_b32 v37, off, s33 offset:184 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xffffff40\n\ts_mov_b32 s33, s27\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.LBB8_30:\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB8_31: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB8_31\n.Lfunc_end8:\n\t.size\t__assert_fail, .Lfunc_end8-__assert_fail\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 6148\n; NumSgprs: 36\n; NumVgprs: 38\n; ScratchSize: 1312\n; MemoryBound: 0\n\t.text\n\t.hidden\t__assertfail ; -- Begin function __assertfail\n\t.weak\t__assertfail\n\t.p2align\t2\n\t.type\t__assertfail,@function\n__assertfail: ; @__assertfail\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_cbranch_execnz .LBB9_2\n; %bb.1:\n\ts_setpc_b64 s[30:31]\n.LBB9_2:\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB9_3: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB9_3\n.Lfunc_end9:\n\t.size\t__assertfail, .Lfunc_end9-__assertfail\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 64\n; NumSgprs: 32\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_get_group_id\n\t.type\t__ockl_get_group_id,@function\n__ockl_get_group_id: ; @__ockl_get_group_id\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v2, s32 offset:32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill\n ; implicit-def: $vgpr2 : SGPR spill to VGPR lane\n\tv_writelane_b32 v2, s14, 0\n\tv_writelane_b32 v2, s13, 1\n\tv_writelane_b32 v2, s12, 2\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n; %bb.1:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v2, s1, 3\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_4\n; %bb.2:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v2, s1, 4\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_7\n; %bb.3:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 5\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_10\n\ts_branch .LBB10_9\n.LBB10_4:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 3\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 6\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB10_13\n; %bb.5:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 7\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_12\n; %bb.6:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 2\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_branch .LBB10_12\n.LBB10_7:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 4\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:12 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 8\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB10_11\n; %bb.8:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 1\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_branch .LBB10_11\n.LBB10_9:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 0\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n.LBB10_10:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 5\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:16 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_branch .LBB10_7\n.LBB10_11:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 8\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill\n\ts_branch .LBB10_4\n.LBB10_12:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 7\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:24 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n.LBB10_13:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 6\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:20 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v1, 0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v2, off, s32 offset:32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end10:\n\t.size\t__ockl_get_group_id, .Lfunc_end10-__ockl_get_group_id\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 988\n; NumSgprs: 33\n; NumVgprs: 3\n; ScratchSize: 40\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_get_local_size\n\t.type\t__ockl_get_local_size,@function\n__ockl_get_local_size: ; @__ockl_get_local_size\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v4, s32 offset:104 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill\n ; implicit-def: $vgpr4 : SGPR spill to VGPR lane\n\tv_writelane_b32 v4, s14, 0\n\tv_writelane_b32 v4, s13, 1\n\tv_writelane_b32 v4, s12, 2\n\tv_writelane_b32 v4, s8, 3\n\tv_writelane_b32 v4, s9, 4\n\tv_writelane_b32 v4, s4, 5\n\tv_writelane_b32 v4, s5, 6\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n; %bb.1:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:8 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v4, s1, 7\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_4\n; %bb.2:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:16 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v4, s1, 8\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_10\n; %bb.3:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 1\n\tv_mov_b32_e32 v0, 1\n\tv_mov_b32_e32 v1, 0\n\tscratch_store_b64 off, v[0:1], s32 offset:24 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v4, s0, 9\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_20\n\ts_branch .LBB11_15\n.LBB11_4:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 7\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:8 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:32 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v4, s0, 10\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB11_25\n; %bb.5:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 1\n\tv_mov_b32_e32 v0, 1\n\tv_mov_b32_e32 v1, 0\n\tscratch_store_b64 off, v[0:1], s32 offset:40 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v4, s0, 11\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_24\n; %bb.6:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n ; implicit-def: $sgpr2_sgpr3\n\ts_mov_b32 s4, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s4\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:48 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v4, s0, 12\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB11_9\n.LBB11_7:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 12\n\tscratch_load_b64 v[0:1], off, s32 offset:48 ; 8-byte Folded Reload\n\tv_cndmask_b32_e64 v2, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v2, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n ; kill: def $vgpr0_vgpr1 killed $vgpr0_vgpr1 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:56 ; 8-byte Folded Spill\n\ts_cbranch_vccnz .LBB11_23\n; %bb.8:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v4, 2\n\tv_readlane_b32 s2, v4, 5\n\tv_readlane_b32 s3, v4, 6\n\tv_mov_b32_e32 v0, 0\n\tglobal_load_u16 v1, v0, s[2:3] offset:4\n\ts_load_b32 s0, s[2:3], 0xc\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v0, s1, v1\n\ts_waitcnt lgkmcnt(0)\n\tv_sub_nc_u32_e64 v0, s0, v0\n ; implicit-def: $sgpr0\n\tv_min_u32_e64 v0, v0, v1\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr0_sgpr1\n\tscratch_store_b64 off, v[0:1], s32 offset:56 ; 8-byte Folded Spill\n\ts_branch .LBB11_23\n.LBB11_9:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 3\n\tv_readlane_b32 s1, v4, 4\n\tv_readlane_b32 s2, v4, 2\n\ts_load_b32 s3, s[0:1], 0x0\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_u32 s2, s3\n\ts_mov_b32 s3, 18\n\ts_mov_b32 s2, 12\n\ts_cselect_b32 s2, s2, s3\n\tv_mov_b32_e32 v0, s2\n\tglobal_load_u16 v0, v0, s[0:1]\n\ts_mov_b32 s0, 0xffff\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n ; implicit-def: $sgpr0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr2_sgpr3\n\tscratch_store_b64 off, v[0:1], s32 offset:48 ; 8-byte Folded Spill\n\tv_writelane_b32 v4, s0, 12\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB11_7\n.LBB11_10:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 8\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:16 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:64 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v4, s0, 13\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB11_22\n; %bb.11:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n ; implicit-def: $sgpr2_sgpr3\n\ts_mov_b32 s4, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s4\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:72 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v4, s0, 14\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB11_14\n.LBB11_12:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 14\n\tscratch_load_b64 v[0:1], off, s32 offset:72 ; 8-byte Folded Reload\n\tv_cndmask_b32_e64 v2, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v2, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n ; kill: def $vgpr0_vgpr1 killed $vgpr0_vgpr1 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:80 ; 8-byte Folded Spill\n\ts_cbranch_vccnz .LBB11_21\n; %bb.13:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v4, 1\n\tv_readlane_b32 s2, v4, 5\n\tv_readlane_b32 s3, v4, 6\n\tv_mov_b32_e32 v0, 0\n\tglobal_load_u16 v1, v0, s[2:3] offset:6\n\ts_load_b32 s0, s[2:3], 0x10\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v0, s1, v1\n\ts_waitcnt lgkmcnt(0)\n\tv_sub_nc_u32_e64 v0, s0, v0\n ; implicit-def: $sgpr0\n\tv_min_u32_e64 v0, v0, v1\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr0_sgpr1\n\tscratch_store_b64 off, v[0:1], s32 offset:80 ; 8-byte Folded Spill\n\ts_branch .LBB11_21\n.LBB11_14:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 3\n\tv_readlane_b32 s1, v4, 4\n\tv_readlane_b32 s2, v4, 1\n\ts_load_b32 s3, s[0:1], 0x4\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_u32 s2, s3\n\ts_mov_b32 s3, 20\n\ts_mov_b32 s2, 14\n\ts_cselect_b32 s2, s2, s3\n\tv_mov_b32_e32 v0, s2\n\tglobal_load_u16 v0, v0, s[0:1]\n\ts_mov_b32 s0, 0xffff\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n ; implicit-def: $sgpr0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr2_sgpr3\n\tscratch_store_b64 off, v[0:1], s32 offset:72 ; 8-byte Folded Spill\n\tv_writelane_b32 v4, s0, 14\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB11_12\n.LBB11_15:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n ; implicit-def: $sgpr2_sgpr3\n\ts_mov_b32 s4, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s4\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:88 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v4, s0, 15\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB11_18\n.LBB11_16:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 15\n\tscratch_load_b64 v[0:1], off, s32 offset:88 ; 8-byte Folded Reload\n\tv_cndmask_b32_e64 v2, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v2, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n ; kill: def $vgpr0_vgpr1 killed $vgpr0_vgpr1 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:96 ; 8-byte Folded Spill\n\ts_cbranch_vccnz .LBB11_19\n; %bb.17:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v4, 0\n\tv_readlane_b32 s2, v4, 5\n\tv_readlane_b32 s3, v4, 6\n\tv_mov_b32_e32 v0, 0\n\tglobal_load_u16 v1, v0, s[2:3] offset:8\n\ts_load_b32 s0, s[2:3], 0x14\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v0, s1, v1\n\ts_waitcnt lgkmcnt(0)\n\tv_sub_nc_u32_e64 v0, s0, v0\n ; implicit-def: $sgpr0\n\tv_min_u32_e64 v0, v0, v1\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr0_sgpr1\n\tscratch_store_b64 off, v[0:1], s32 offset:96 ; 8-byte Folded Spill\n\ts_branch .LBB11_19\n.LBB11_18:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 3\n\tv_readlane_b32 s1, v4, 4\n\tv_readlane_b32 s2, v4, 0\n\ts_load_b32 s3, s[0:1], 0x8\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_u32 s2, s3\n\ts_mov_b32 s3, 22\n\ts_mov_b32 s2, 16\n\ts_cselect_b32 s2, s2, s3\n\tv_mov_b32_e32 v0, s2\n\tglobal_load_u16 v0, v0, s[0:1]\n\ts_mov_b32 s0, 0xffff\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n ; implicit-def: $sgpr0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr2_sgpr3\n\tscratch_store_b64 off, v[0:1], s32 offset:88 ; 8-byte Folded Spill\n\tv_writelane_b32 v4, s0, 15\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB11_16\n.LBB11_19:\n\tscratch_load_b64 v[0:1], off, s32 offset:96 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:24 ; 8-byte Folded Spill\n.LBB11_20:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 9\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:24 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:16 ; 8-byte Folded Spill\n\ts_branch .LBB11_10\n.LBB11_21:\n\tscratch_load_b64 v[0:1], off, s32 offset:80 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:64 ; 8-byte Folded Spill\n.LBB11_22:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 13\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:64 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:8 ; 8-byte Folded Spill\n\ts_branch .LBB11_4\n.LBB11_23:\n\tscratch_load_b64 v[0:1], off, s32 offset:56 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:40 ; 8-byte Folded Spill\n.LBB11_24:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 11\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:40 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:32 ; 8-byte Folded Spill\n.LBB11_25:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 10\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[2:3], off, s32 offset:32 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 32\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[0:1], s0, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v2\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v4, off, s32 offset:104 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end11:\n\t.size\t__ockl_get_local_size, .Lfunc_end11-__ockl_get_local_size\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 2384\n; NumSgprs: 35\n; NumVgprs: 5\n; ScratchSize: 112\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_get_local_id\n\t.type\t__ockl_get_local_id,@function\n__ockl_get_local_id: ; @__ockl_get_local_id\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v2, s32 offset:36 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v31, s32 offset:8 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill\n; %bb.1:\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n ; implicit-def: $vgpr2 : SGPR spill to VGPR lane\n\tv_writelane_b32 v2, s1, 0\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_4\n; %bb.2:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v2, s1, 1\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_7\n; %bb.3:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 2\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_10\n\ts_branch .LBB12_9\n.LBB12_4:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 0\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:12 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 3\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB12_13\n; %bb.5:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 4\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_12\n; %bb.6:\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0x3ff\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_branch .LBB12_12\n.LBB12_7:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 1\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:16 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:32 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 5\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB12_11\n; %bb.8:\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_bfe_u32 v0, v0, 10, 10\n\tscratch_store_b32 off, v0, s32 offset:32 ; 4-byte Folded Spill\n\ts_branch .LBB12_11\n.LBB12_9:\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_bfe_u32 v0, v0, 20, 10\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n.LBB12_10:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 2\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:20 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_branch .LBB12_7\n.LBB12_11:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 5\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:32 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_branch .LBB12_4\n.LBB12_12:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n.LBB12_13:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 3\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:24 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v1, 0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v2, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end12:\n\t.size\t__ockl_get_local_id, .Lfunc_end12-__ockl_get_local_id\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 912\n; NumSgprs: 33\n; NumVgprs: 32\n; ScratchSize: 44\n; MemoryBound: 0\n\t.text\n\t.protected\t_Z25fluidStructureInteractionPfS_S_fi ; -- Begin function _Z25fluidStructureInteractionPfS_S_fi\n\t.globl\t_Z25fluidStructureInteractionPfS_S_fi\n\t.p2align\t8\n\t.type\t_Z25fluidStructureInteractionPfS_S_fi,@function\n_Z25fluidStructureInteractionPfS_S_fi: ; @_Z25fluidStructureInteractionPfS_S_fi\n; %bb.0:\n\ts_mov_b32 s32, 0x80\n ; implicit-def: $vgpr8 : SGPR spill to VGPR lane\n\tv_writelane_b32 v8, s15, 0\n\ts_mov_b32 s6, s14\n\tv_readlane_b32 s14, v8, 0\n\tv_writelane_b32 v8, s6, 1\n\ts_mov_b32 s12, s13\n\tv_readlane_b32 s13, v8, 1\n\tv_writelane_b32 v8, s12, 2\n\ts_mov_b64 s[10:11], s[4:5]\n\tv_writelane_b32 v8, s10, 3\n\tv_writelane_b32 v8, s11, 4\n\tv_writelane_b32 v8, s2, 5\n\tv_writelane_b32 v8, s3, 6\n\ts_mov_b64 s[4:5], s[0:1]\n\tv_readlane_b32 s0, v8, 5\n\tv_readlane_b32 s1, v8, 6\n\tv_writelane_b32 v8, s4, 7\n\tv_writelane_b32 v8, s5, 8\n\tv_mov_b32_e32 v31, v0\n\tscratch_store_b32 off, v31, off offset:108 ; 4-byte Folded Spill\n\ts_load_b64 s[34:35], s[0:1], 0x0\n\ts_load_b64 s[28:29], s[0:1], 0x8\n\ts_load_b64 s[24:25], s[0:1], 0x10\n\ts_load_b32 s3, s[0:1], 0x18\n\ts_load_b32 s2, s[0:1], 0x1c\n\ts_mov_b64 s[6:7], src_private_base\n\ts_mov_b32 s8, 32\n\ts_lshr_b64 s[6:7], s[6:7], s8\n\ts_mov_b32 s15, s6\n\tv_writelane_b32 v8, s15, 9\n\ts_mov_b32 s30, 32\n ; kill: def $sgpr30 killed $sgpr30 def $sgpr30_sgpr31\n\ts_mov_b32 s31, s15\n\ts_mov_b32 s26, 40\n ; kill: def $sgpr26 killed $sgpr26 def $sgpr26_sgpr27\n\ts_mov_b32 s27, s15\n\ts_mov_b32 s22, 48\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s15\n\ts_mov_b32 s20, 56\n ; kill: def $sgpr20 killed $sgpr20 def $sgpr20_sgpr21\n\ts_mov_b32 s21, s15\n\ts_mov_b64 s[6:7], s[20:21]\n\tv_writelane_b32 v8, s6, 10\n\tv_writelane_b32 v8, s7, 11\n\ts_mov_b32 s18, 64\n ; kill: def $sgpr18 killed $sgpr18 def $sgpr18_sgpr19\n\ts_mov_b32 s19, s15\n\ts_mov_b64 s[6:7], s[18:19]\n\tv_writelane_b32 v8, s6, 12\n\tv_writelane_b32 v8, s7, 13\n\ts_mov_b32 s16, 0x48\n ; kill: def $sgpr16 killed $sgpr16 def $sgpr16_sgpr17\n\ts_mov_b32 s17, s15\n\ts_mov_b64 s[6:7], s[16:17]\n\tv_writelane_b32 v8, s6, 14\n\tv_writelane_b32 v8, s7, 15\n\ts_mov_b32 s8, 0x50\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s15\n\ts_mov_b64 s[6:7], s[8:9]\n\tv_writelane_b32 v8, s6, 16\n\tv_writelane_b32 v8, s7, 17\n\ts_mov_b32 s6, 0x54\n ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7\n\ts_mov_b32 s7, s15\n\tv_writelane_b32 v8, s6, 18\n\tv_writelane_b32 v8, s7, 19\n\ts_mov_b32 s36, 0x58\n ; kill: def $sgpr36 killed $sgpr36 def $sgpr36_sgpr37\n\ts_mov_b32 s37, s15\n\tv_writelane_b32 v8, s36, 20\n\tv_writelane_b32 v8, s37, 21\n\tv_writelane_b32 v8, s36, 22\n\tv_writelane_b32 v8, s37, 23\n\tv_mov_b32_e32 v0, s30\n\tv_mov_b32_e32 v1, s31\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v2, s34\n\tv_mov_b32_e32 v3, s35\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s30\n\tv_mov_b32_e32 v1, s31\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s26\n\tv_mov_b32_e32 v1, s27\n\tv_mov_b32_e32 v2, s28\n\tv_mov_b32_e32 v3, s29\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s26\n\tv_mov_b32_e32 v1, s27\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s22\n\tv_mov_b32_e32 v1, s23\n\tv_mov_b32_e32 v2, s24\n\tv_mov_b32_e32 v3, s25\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s22\n\tv_mov_b32_e32 v1, s23\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s20\n\tv_mov_b32_e32 v1, s21\n\ts_waitcnt vmcnt(2) lgkmcnt(4)\n\tflat_store_b64 v[0:1], v[6:7]\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\ts_waitcnt vmcnt(1) lgkmcnt(3)\n\tflat_store_b64 v[0:1], v[4:5]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\ts_waitcnt vmcnt(0) lgkmcnt(2)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s8\n\tv_mov_b32_e32 v1, s9\n\tv_mov_b32_e32 v2, s3\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tv_mov_b32_e32 v2, s2\n\tflat_store_b32 v[0:1], v2\n\ts_mov_b64 s[6:7], 32\n\ts_mov_b32 s2, s0\n\ts_mov_b32 s0, s1\n\ts_mov_b32 s3, s6\n\ts_mov_b32 s1, s7\n\ts_add_u32 s8, s2, s3\n\ts_addc_u32 s0, s0, s1\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s0\n\tv_writelane_b32 v8, s8, 24\n\tv_writelane_b32 v8, s9, 25\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_group_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_group_id@rel32@hi+12\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, off offset:104 ; 4-byte Folded Spill\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:108 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v8, 0\n\tv_readlane_b32 s13, v8, 1\n\tv_readlane_b32 s12, v8, 2\n\tv_readlane_b32 s10, v8, 3\n\tv_readlane_b32 s11, v8, 4\n\tv_readlane_b32 s8, v8, 24\n\tv_readlane_b32 s9, v8, 25\n\tv_readlane_b32 s4, v8, 7\n\tv_readlane_b32 s5, v8, 8\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:104 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:112 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:112 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v1, off offset:96 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_size@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_size@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:108 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v8, 0\n\tv_readlane_b32 s13, v8, 1\n\tv_readlane_b32 s12, v8, 2\n\tv_readlane_b32 s10, v8, 3\n\tv_readlane_b32 s11, v8, 4\n\tv_readlane_b32 s4, v8, 7\n\tv_readlane_b32 s5, v8, 8\n\tv_readlane_b32 s8, v8, 24\n\tv_readlane_b32 s9, v8, 25\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:104 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:100 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:100 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v3, v1\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_id@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v2, off, off offset:96 ; 4-byte Folded Reload\n\tv_readlane_b32 s2, v8, 20\n\tv_readlane_b32 s3, v8, 21\n\tv_readlane_b32 s0, v8, 18\n\tv_readlane_b32 s1, v8, 19\n\tv_mov_b32_e32 v4, v1\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_mov_b32_e32 v4, v0\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr5\n ; implicit-def: $sgpr5\n\tv_mov_b32_e32 v0, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[0:1], s4, v2, v3, v[4:5]\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v2, s1\n\tv_mov_b32_e32 v1, s0\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_lt_i32_e64 s1, v0, v1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v8, s0, 26\n\ts_or_saveexec_b32 s33, -1\n\tscratch_store_b32 off, v8, off offset:92 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s33\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB13_2\n; %bb.1:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v8, off, off offset:92 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v8, 14\n\tv_readlane_b32 s1, v8, 15\n\tv_readlane_b32 s2, v8, 16\n\tv_readlane_b32 s3, v8, 17\n\tv_readlane_b32 s6, v8, 22\n\tv_readlane_b32 s7, v8, 23\n\tv_readlane_b32 s8, v8, 12\n\tv_readlane_b32 s9, v8, 13\n\tv_readlane_b32 s4, v8, 10\n\tv_readlane_b32 s5, v8, 11\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v3, s6\n\tv_mov_b32_e32 v4, s7\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\ts_mov_b32 s4, 2\n\tv_lshlrev_b64 v[6:7], s4, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v6\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_u32 v0, s5, v0, v3\n\tv_add_co_ci_u32_e64 v2, s5, v1, v2, s5\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b32 v3, v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v4, v[0:1]\n\tv_mov_b32_e32 v0, s8\n\tv_mov_b32_e32 v1, s9\n\tflat_load_b64 v[1:2], v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_u32 v0, s5, v0, v5\n\tv_add_co_ci_u32_e64 v2, s5, v1, v2, s5\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b32 v2, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_fmac_f32_e64 v2, v3, v4\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s8\n\tv_mov_b32_e32 v1, s9\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v3, s6\n\tv_mov_b32_e32 v4, s7\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[6:7], s4, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v6\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_u32 v0, s4, v0, v3\n\tv_add_co_ci_u32_e64 v2, s4, v1, v2, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b32 v3, v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v4, v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b64 v[1:2], v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v7\n\tv_add_co_u32 v0, s0, v0, v5\n\tv_add_co_ci_u32_e64 v2, s0, v1, v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b32 v2, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_fmac_f32_e64 v2, v3, v4\n\tflat_store_b32 v[0:1], v2\n.LBB13_2:\n\ts_or_saveexec_b32 s33, -1\n\tscratch_load_b32 v8, off, off offset:92 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s33\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v8, 26\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z25fluidStructureInteractionPfS_S_fi\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 240\n\t\t.amdhsa_kernarg_size 288\n\t\t.amdhsa_user_sgpr_count 13\n\t\t.amdhsa_user_sgpr_dispatch_ptr 1\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 1\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 1\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 1\n\t\t.amdhsa_system_sgpr_workgroup_id_z 1\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 2\n\t\t.amdhsa_next_free_vgpr 32\n\t\t.amdhsa_next_free_sgpr 38\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end13:\n\t.size\t_Z25fluidStructureInteractionPfS_S_fi, .Lfunc_end13-_Z25fluidStructureInteractionPfS_S_fi\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 1744\n; NumSgprs: 40\n; NumVgprs: 32\n; ScratchSize: 240\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 4\n; VGPRBlocks: 3\n; NumSGPRsForWavesPerEU: 40\n; NumVGPRsForWavesPerEU: 32\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1\n; COMPUTE_PGM_RSRC2:USER_SGPR: 13\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__const.__assert_fail.fmt,@object ; @__const.__assert_fail.fmt\n\t.section\t.rodata.str1.16,\"aMS\",@progbits,1\n\t.p2align\t4, 0x0\n__const.__assert_fail.fmt:\n\t.asciz\t\"%s:%u: %s: Device-side assertion `%s' failed.\\n\"\n\t.size\t__const.__assert_fail.fmt, 47\n\n\t.protected\tblockIdx\n\t.protected\tblockDim\n\t.protected\tthreadIdx\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.hidden\t__oclc_ABI_version ; @__oclc_ABI_version\n\t.type\t__oclc_ABI_version,@object\n\t.section\t.rodata,\"a\",@progbits\n\t.weak\t__oclc_ABI_version\n\t.p2align\t2, 0x0\n__oclc_ABI_version:\n\t.long\t500 ; 0x1f4\n\t.size\t__oclc_ABI_version, 4\n\n\t.weak\tblockIdx\n\t.weak\tblockDim\n\t.weak\tthreadIdx\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 16\n .size: 8\n .value_kind: global_buffer\n - .offset: 24\n .size: 4\n .value_kind: by_value\n - .offset: 28\n .size: 4\n .value_kind: by_value\n - .offset: 32\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 36\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 40\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 44\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 46\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 48\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 50\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 52\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 54\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 72\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 80\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 88\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 96\n .size: 2\n .value_kind: hidden_grid_dims\n - .offset: 112\n .size: 8\n .value_kind: hidden_hostcall_buffer\n - .offset: 120\n .size: 8\n .value_kind: hidden_multigrid_sync_arg\n - .offset: 128\n .size: 8\n .value_kind: hidden_heap_v1\n - .offset: 136\n .size: 8\n .value_kind: hidden_default_queue\n - .offset: 232\n .size: 8\n .value_kind: hidden_queue_ptr\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 288\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z25fluidStructureInteractionPfS_S_fi\n .private_segment_fixed_size: 240\n .sgpr_count: 40\n .sgpr_spill_count: 27\n .symbol: _Z25fluidStructureInteractionPfS_S_fi.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 32\n .vgpr_spill_count: 6\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162595,"cells":{"id":{"kind":"string","value":"a33c54304a0b0cdc78328656a4ae805ac7893b5c_O0"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z21globalMemOffsetKernelv --------------------------\n .section .text._Z21globalMemOffsetKernelv,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=4\"\n .align 128\n\n\n\n\n .global _Z21globalMemOffsetKernelv\n .type _Z21globalMemOffsetKernelv,@function\n .size _Z21globalMemOffsetKernelv,(.L_x_3 - _Z21globalMemOffsetKernelv)\n .other _Z21globalMemOffsetKernelv,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z21globalMemOffsetKernelv:\n.text._Z21globalMemOffsetKernelv:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ EXIT ;\n.L_x_0:\n /*0020*/ BRA `(.L_x_0);\n /*0030*/ NOP;\n /*0040*/ NOP;\n /*0050*/ NOP;\n /*0060*/ NOP;\n /*0070*/ NOP;\n /*0080*/ NOP;\n /*0090*/ NOP;\n /*00a0*/ NOP;\n /*00b0*/ NOP;\n /*00c0*/ NOP;\n /*00d0*/ NOP;\n /*00e0*/ NOP;\n /*00f0*/ NOP;\n.L_x_3:\n\n\n//--------------------- .text._Z21globalMemStrideKernelv --------------------------\n .section .text._Z21globalMemStrideKernelv,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=4\"\n .align 128\n\n\n\n\n .global _Z21globalMemStrideKernelv\n .type _Z21globalMemStrideKernelv,@function\n .size _Z21globalMemStrideKernelv,(.L_x_4 - _Z21globalMemStrideKernelv)\n .other _Z21globalMemStrideKernelv,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z21globalMemStrideKernelv:\n.text._Z21globalMemStrideKernelv:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ EXIT ;\n.L_x_1:\n /*0020*/ BRA `(.L_x_1);\n /*0030*/ NOP;\n /*0040*/ NOP;\n /*0050*/ NOP;\n /*0060*/ NOP;\n /*0070*/ NOP;\n /*0080*/ NOP;\n /*0090*/ NOP;\n /*00a0*/ NOP;\n /*00b0*/ NOP;\n /*00c0*/ NOP;\n /*00d0*/ NOP;\n /*00e0*/ NOP;\n /*00f0*/ NOP;\n.L_x_4:\n\n\n//--------------------- .text._Z24globalMemCoalescedKernelv --------------------------\n .section .text._Z24globalMemCoalescedKernelv,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=4\"\n .align 128\n\n\n\n\n .global _Z24globalMemCoalescedKernelv\n .type _Z24globalMemCoalescedKernelv,@function\n .size _Z24globalMemCoalescedKernelv,(.L_x_5 - _Z24globalMemCoalescedKernelv)\n .other _Z24globalMemCoalescedKernelv,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z24globalMemCoalescedKernelv:\n.text._Z24globalMemCoalescedKernelv:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ EXIT ;\n.L_x_2:\n /*0020*/ BRA `(.L_x_2);\n /*0030*/ NOP;\n /*0040*/ NOP;\n /*0050*/ NOP;\n /*0060*/ NOP;\n /*0070*/ NOP;\n /*0080*/ NOP;\n /*0090*/ NOP;\n /*00a0*/ NOP;\n /*00b0*/ NOP;\n /*00c0*/ NOP;\n /*00d0*/ NOP;\n /*00e0*/ NOP;\n /*00f0*/ NOP;\n.L_x_5:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.weak\t__cxa_pure_virtual ; -- Begin function __cxa_pure_virtual\n\t.p2align\t2\n\t.type\t__cxa_pure_virtual,@function\n__cxa_pure_virtual: ; @__cxa_pure_virtual\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB0_1: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB0_1\n.Lfunc_end0:\n\t.size\t__cxa_pure_virtual, .Lfunc_end0-__cxa_pure_virtual\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 56\n; NumSgprs: 1\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.weak\t__cxa_deleted_virtual ; -- Begin function __cxa_deleted_virtual\n\t.p2align\t2\n\t.type\t__cxa_deleted_virtual,@function\n__cxa_deleted_virtual: ; @__cxa_deleted_virtual\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB1_1: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB1_1\n.Lfunc_end1:\n\t.size\t__cxa_deleted_virtual, .Lfunc_end1-__cxa_deleted_virtual\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 56\n; NumSgprs: 1\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hsa_signal_add\n\t.type\t__ockl_hsa_signal_add,@function\n__ockl_hsa_signal_add: ; @__ockl_hsa_signal_add\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v6, s32 offset:48 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v4, s32 offset:36 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v3, s32 offset:32 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v2\n\tscratch_load_b32 v2, off, s32 offset:32 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v1, s32 offset:28 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v1, v0\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[3:4], s32 offset:20 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v3, v1\n\tscratch_store_b64 off, v[3:4], s32 offset:12 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v0, v1\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v1, v2\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v0, s1, v0, s1\n\tv_add_co_ci_u32_e64 v2, s0, v1, s0, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s32 offset:4 ; 8-byte Folded Spill\n; %bb.1:\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 3\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, 0\n ; implicit-def: $vgpr6 : SGPR spill to VGPR lane\n\tv_writelane_b32 v6, s1, 0\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 1\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_3\n; %bb.2:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 4\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s1, 2\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 3\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_17\n\ts_branch .LBB2_4\n.LBB2_3:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 1\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s2, v6, 0\n\tv_writelane_b32 v6, s2, 4\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s2, 5\n\tv_writelane_b32 v6, s1, 6\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 7\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_13\n\ts_branch .LBB2_6\n.LBB2_4:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 5\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, -1\n\tv_writelane_b32 v6, s0, 8\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 9\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_15\n\ts_branch .LBB2_18\n.LBB2_5:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 10\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_readlane_b32 s0, v6, 11\n\ts_and_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 0\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_3\n.LBB2_6:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 12\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_7\n\ts_branch .LBB2_14\n.LBB2_7:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 12\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s2, v6, 4\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s2, 13\n\tv_writelane_b32 v6, s1, 14\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 15\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_9\n; %bb.8:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 4\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_lt_i32_e64 s2, v0, s0\n\ts_mov_b32 s0, -1\n\ts_mov_b32 s0, exec_lo\n\ts_and_not1_b32 s1, s1, exec_lo\n\ts_and_b32 s2, s2, exec_lo\n\ts_or_b32 s1, s1, s2\n\tv_writelane_b32 v6, s1, 13\n\tv_writelane_b32 v6, s0, 14\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n.LBB2_9:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s3, v6, 15\n\ts_or_b32 exec_lo, exec_lo, s3\n\tv_readlane_b32 s1, v6, 4\n\tv_readlane_b32 s2, v6, 13\n\tv_readlane_b32 s0, v6, 14\n\ts_and_b32 s0, s0, exec_lo\n\ts_and_not1_b32 s1, s1, exec_lo\n\ts_and_b32 s2, s2, exec_lo\n\ts_or_b32 s1, s1, s2\n\tv_writelane_b32 v6, s1, 5\n\tv_writelane_b32 v6, s0, 6\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_13\n.LBB2_10:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 16\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 17\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n.LBB2_11:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 18\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v6, 17\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 19\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_19\n; %bb.12:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_branch .LBB2_19\n.LBB2_13:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v6, 7\n\ts_or_b32 exec_lo, exec_lo, s2\n\tv_readlane_b32 s0, v6, 5\n\tv_readlane_b32 s1, v6, 6\n\tv_writelane_b32 v6, s1, 16\n\tv_writelane_b32 v6, s1, 17\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 18\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_11\n\ts_branch .LBB2_10\n.LBB2_14:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_branch .LBB2_7\n.LBB2_15:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 9\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_readlane_b32 s0, v6, 8\n\ts_and_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 2\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_17\n.LBB2_16:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_branch .LBB2_5\n.LBB2_17:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 3\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v6, 2\n\tv_writelane_b32 v6, s1, 11\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 10\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_5\n\ts_branch .LBB2_16\n.LBB2_18:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b32 s0, 0\n\ts_xor_b32 s0, exec_lo, -1\n\tv_writelane_b32 v6, s0, 8\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_15\n.LBB2_19:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 19\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:12 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[0:1], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:40 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_ne_u64_e64 s1, v[0:1], s[0:1]\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 20\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_21\n; %bb.20:\n\tscratch_load_b64 v[1:2], off, s32 offset:40 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s32 offset:12 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b32 v0, v[3:4], off offset:24\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v5, 0\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\tv_mov_b32_e32 v4, v5\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[1:2], v[3:4], off\n\tv_readfirstlane_b32 s0, v0\n\ts_mov_b32 s1, 0xff\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB2_21:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 20\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v6, off, s32 offset:48 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end2:\n\t.size\t__ockl_hsa_signal_add, .Lfunc_end2-__ockl_hsa_signal_add\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 1952\n; NumSgprs: 33\n; NumVgprs: 7\n; ScratchSize: 56\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hostcall_internal\n\t.type\t__ockl_hostcall_internal,@function\n__ockl_hostcall_internal: ; @__ockl_hostcall_internal\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s18, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v24, s33 offset:308 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v25, s33 offset:312 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v26, s33 offset:316 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0x150\n\tv_writelane_b32 v24, s30, 0\n\tv_writelane_b32 v24, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:132 ; 4-byte Folded Spill\n ; implicit-def: $vgpr26 : SGPR spill to VGPR lane\n\tv_writelane_b32 v26, s6, 0\n\tv_writelane_b32 v26, s7, 1\n\tscratch_store_b32 off, v18, s33 offset:128 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v16\n\tscratch_load_b32 v16, off, s33 offset:128 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:124 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v14\n\tscratch_load_b32 v14, off, s33 offset:124 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:120 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v12\n\tscratch_load_b32 v12, off, s33 offset:120 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:116 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v10\n\tscratch_load_b32 v10, off, s33 offset:116 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:112 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v8\n\tscratch_load_b32 v8, off, s33 offset:112 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:108 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v6\n\tscratch_load_b32 v6, off, s33 offset:108 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:104 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v4\n\tscratch_load_b32 v4, off, s33 offset:104 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:100 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v2\n\tscratch_load_b32 v2, off, s33 offset:100 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:96 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v1, s33 offset:92 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v1, v0\n\tscratch_load_b32 v0, off, s33 offset:92 ; 4-byte Folded Reload\n\tv_writelane_b32 v26, s15, 2\n\tv_writelane_b32 v26, s14, 3\n\tv_writelane_b32 v26, s13, 4\n\tv_writelane_b32 v26, s12, 5\n\tv_writelane_b32 v26, s10, 6\n\tv_writelane_b32 v26, s11, 7\n\tv_writelane_b32 v26, s8, 8\n\tv_writelane_b32 v26, s9, 9\n\tv_writelane_b32 v26, s4, 10\n\tv_writelane_b32 v26, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\ts_waitcnt vmcnt(8)\n\tv_mov_b32_e32 v18, v16\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr15 killed $vgpr15 def $vgpr15_vgpr16 killed $exec\n\ts_waitcnt vmcnt(7)\n\tv_mov_b32_e32 v16, v14\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec\n\ts_waitcnt vmcnt(6)\n\tv_mov_b32_e32 v14, v12\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\ts_waitcnt vmcnt(5)\n\tv_mov_b32_e32 v12, v10\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\ts_waitcnt vmcnt(4)\n\tv_mov_b32_e32 v10, v8\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\ts_waitcnt vmcnt(3)\n\tv_mov_b32_e32 v8, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v6, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[17:18], s33 offset:84 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[15:16], s33 offset:76 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[13:14], s33 offset:68 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[11:12], s33 offset:60 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[9:10], s33 offset:52 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[7:8], s33 offset:44 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[5:6], s33 offset:36 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[3:4], s33 offset:28 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s0, -1\n\tv_mbcnt_lo_u32_b32 v0, s0, s1\n\tv_mbcnt_hi_u32_b32 v0, s0, v0\n\t;;#ASMSTART\n\t;;#ASMEND\n\tv_mov_b32_e32 v3, v0\n\tscratch_store_b32 off, v3, s33 offset:24 ; 4-byte Folded Spill\n\tv_readfirstlane_b32 s0, v0\n\tscratch_store_b64 off, v[1:2], s33 offset:16 ; 8-byte Folded Spill\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, s1\n\tv_writelane_b32 v26, s0, 12\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v0, 0\n\tv_mov_b32_e32 v1, 0\n\tscratch_store_b64 off, v[0:1], s33 offset:8 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 13\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_6\n; %bb.1:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_mov_b64 s[2:3], 24\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:160 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b64 s[2:3], 40\n\tv_mov_b32_e32 v4, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v5, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v4, s1, v4, s1\n\tv_add_co_ci_u32_e64 v6, s0, v5, s0, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tscratch_store_b64 off, v[4:5], s33 offset:152 ; 8-byte Folded Spill\n\tglobal_load_b64 v[5:6], v[0:1], off\n\tglobal_load_b64 v[10:11], v[0:1], off offset:40\n\tv_mov_b32_e32 v8, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v11\n\tv_and_b32_e64 v4, v4, v8\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v7, v10\n\tv_and_b32_e64 v12, v7, v9\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_mov_b32_e32 v4, v12\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[10:11], s0, v4, s1, 0\n\tv_mov_b32_e32 v14, v11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec\n\tv_mov_b32_e32 v15, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[12:13], s0, v[12:13]\n\tv_mov_b32_e32 v4, v12\n\tv_mad_u64_u32 v[12:13], s1, v4, s1, v[14:15]\n ; kill: def $vgpr12 killed $vgpr12 killed $vgpr12_vgpr13 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s1\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_lshlrev_b64 v[13:14], s0, v[12:13]\n\tv_mov_b32_e32 v7, v14\n\tv_mov_b32_e32 v11, v10\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\tv_mov_b32_e32 v4, v12\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v10, v13\n\tv_mov_b32_e32 v7, v11\n\tv_or_b32_e64 v10, v7, v10\n ; kill: def $vgpr10 killed $vgpr10 def $vgpr10_vgpr11 killed $exec\n\tv_mov_b32_e32 v11, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v11\n\tv_add_co_u32 v4, s0, v4, v7\n\tv_add_co_ci_u32_e64 v6, s0, v5, v6, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tglobal_load_b64 v[4:5], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v10, v5\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s0, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:144 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:136 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 15\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_5\n.LBB3_2: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 14\n\tscratch_load_b64 v[2:3], off, s33 offset:144 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:160 ; 8-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:152 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[5:6], v[4:5], off\n\tglobal_load_b64 v[10:11], v[7:8], off\n\tv_mov_b32_e32 v8, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v11\n\tv_and_b32_e64 v4, v4, v8\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v7, v10\n\tv_and_b32_e64 v12, v7, v9\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_mov_b32_e32 v4, v12\n\ts_mov_b32 s2, 24\n\tv_mad_u64_u32 v[10:11], s0, v4, s2, 0\n\tv_mov_b32_e32 v14, v11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec\n\tv_mov_b32_e32 v15, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[12:13], s0, v[12:13]\n\tv_mov_b32_e32 v4, v12\n\tv_mad_u64_u32 v[12:13], s2, v4, s2, v[14:15]\n ; kill: def $vgpr12 killed $vgpr12 killed $vgpr12_vgpr13 killed $exec\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s2\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_lshlrev_b64 v[13:14], s0, v[12:13]\n\tv_mov_b32_e32 v7, v14\n\tv_mov_b32_e32 v11, v10\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\tv_mov_b32_e32 v4, v12\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v10, v13\n\tv_mov_b32_e32 v7, v11\n\tv_or_b32_e64 v10, v7, v10\n ; kill: def $vgpr10 killed $vgpr10 def $vgpr10_vgpr11 killed $exec\n\tv_mov_b32_e32 v11, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v11\n\tv_add_co_u32 v4, s0, v4, v7\n\tv_add_co_ci_u32_e64 v6, s0, v5, v6, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tglobal_load_b64 v[4:5], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v10, v5\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e64 s0, v[0:1], v[2:3]\n\ts_or_b32 s0, s0, s1\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:144 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:168 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 16\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_2\n; %bb.3:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 16\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.4:\n\tscratch_load_b64 v[0:1], off, s33 offset:168 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:136 ; 8-byte Folded Spill\n.LBB3_5:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:136 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:8 ; 8-byte Folded Spill\n.LBB3_6:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 13\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:8 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[4:5], s0, v[4:5]\n\tv_mov_b32_e32 v2, v4\n\tv_readfirstlane_b32 s4, v3\n\tv_readfirstlane_b32 s2, v2\n ; implicit-def: $sgpr5\n ; implicit-def: $sgpr3\n ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3\n\ts_mov_b32 s3, s5\n\ts_lshl_b64 s[2:3], s[2:3], s0\n\ts_mov_b32 s0, 0\n ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5\n\ts_mov_b32 s5, s0\n\ts_or_b64 s[2:3], s[2:3], s[4:5]\n\tv_writelane_b32 v26, s2, 17\n\tv_writelane_b32 v26, s3, 18\n\tglobal_load_b64 v[2:3], v[0:1], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:200 ; 8-byte Folded Spill\n\ts_mov_b64 s[6:7], 40\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s7\n\tv_add_co_u32 v2, s4, v2, s4\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s4\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tglobal_load_b64 v[3:4], v[0:1], off offset:40\n\ts_mov_b32 s0, s3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v4\n\tv_and_b32_e64 v2, s0, v2\n\ts_mov_b32 s0, s2\n ; kill: def $vgpr3 killed $vgpr3 killed $vgpr3_vgpr4 killed $exec\n\tv_and_b32_e64 v3, s0, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v5, v3\n\tscratch_store_b64 off, v[5:6], s33 offset:184 ; 8-byte Folded Spill\n\tglobal_load_b64 v[1:2], v[0:1], off offset:8\n\ts_mov_b32 s0, 12\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s0, v0, v3\n\tv_add_co_ci_u32_e64 v2, s0, v1, v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:176 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], exec\n\tv_writelane_b32 v26, s2, 19\n\tv_writelane_b32 v26, s3, 20\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 21\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_8\n; %bb.7:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 19\n\tv_readlane_b32 s1, v26, 20\n\tscratch_load_b32 v2, off, s33 offset:96 ; 4-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v5, v0\n\ts_mov_b32 s3, 24\n\tv_mad_u64_u32 v[3:4], s2, v5, s3, 0\n\tv_mov_b32_e32 v9, v4\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v5, s2\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v5\n\ts_mov_b32 s2, 32\n\tv_lshrrev_b64 v[0:1], s2, v[0:1]\n\tv_mov_b32_e32 v5, v0\n\tv_mad_u64_u32 v[0:1], s3, v5, s3, v[9:10]\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v5, s3\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v5\n\tv_lshlrev_b64 v[9:10], s2, v[0:1]\n\tv_mov_b32_e32 v1, v10\n\tv_mov_b32_e32 v4, v3\n\ts_mov_b32 s2, 0\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v0, v5\n\tv_or_b32_e64 v0, v0, v1\n\tv_mov_b32_e32 v3, v9\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v5, v1, v3\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v0\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v3, v6\n\tv_add_co_u32 v0, s2, v0, v4\n\tv_add_co_ci_u32_e64 v3, s2, v1, v3, s2\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tglobal_store_b32 v[0:1], v2, off offset:16\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tglobal_store_b64 v[0:1], v[2:3], off offset:8\n\tv_mov_b32_e32 v2, 1\n\tglobal_store_b32 v[0:1], v2, off offset:20\n.LBB3_8:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[2:3], off, s33 offset:84 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:76 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:68 ; 8-byte Folded Reload\n\tscratch_load_b64 v[8:9], off, s33 offset:60 ; 8-byte Folded Reload\n\tscratch_load_b64 v[10:11], off, s33 offset:52 ; 8-byte Folded Reload\n\tscratch_load_b64 v[12:13], off, s33 offset:44 ; 8-byte Folded Reload\n\tscratch_load_b64 v[14:15], off, s33 offset:36 ; 8-byte Folded Reload\n\tscratch_load_b64 v[16:17], off, s33 offset:28 ; 8-byte Folded Reload\n\tscratch_load_b64 v[22:23], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:24 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v18, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v18\n\ts_mov_b32 s0, 6\n\ts_waitcnt vmcnt(0)\n\tv_lshlrev_b64 v[20:21], s0, v[0:1]\n\tv_mov_b32_e32 v0, v22\n\tv_mov_b32_e32 v19, v20\n\tv_mov_b32_e32 v1, v23\n\tv_mov_b32_e32 v18, v21\n\tv_add_co_u32 v0, s0, v0, v19\n\tv_add_co_ci_u32_e64 v18, s0, v1, v18, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v18\n\tscratch_store_b64 off, v[0:1], s33 offset:216 ; 8-byte Folded Spill\n\tglobal_store_b64 v[0:1], v[16:17], off\n\ts_mov_b64 s[4:5], 8\n\tv_mov_b32_e32 v16, v0\n\ts_mov_b32 s2, s4\n\tv_mov_b32_e32 v17, v1\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v16, s2, v16, s2\n\tv_add_co_ci_u32_e64 v18, s0, v17, s0, s2\n ; kill: def $vgpr16 killed $vgpr16 def $vgpr16_vgpr17 killed $exec\n\tv_mov_b32_e32 v17, v18\n\tscratch_store_b64 off, v[16:17], s33 offset:208 ; 8-byte Folded Spill\n\tglobal_store_b64 v[0:1], v[14:15], off offset:8\n\tglobal_store_b64 v[0:1], v[12:13], off offset:16\n\tglobal_store_b64 v[0:1], v[10:11], off offset:24\n\tglobal_store_b64 v[0:1], v[8:9], off offset:32\n\tglobal_store_b64 v[0:1], v[6:7], off offset:40\n\tglobal_store_b64 v[0:1], v[4:5], off offset:48\n\tglobal_store_b64 v[0:1], v[2:3], off offset:56\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 22\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_13\n; %bb.9:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[5:6], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:192 ; 8-byte Folded Reload\n\ts_mov_b64 s[4:5], 32\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s4\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:240 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:32 glc\n\ts_waitcnt vmcnt(1)\n\tglobal_load_b64 v[7:8], v[7:8], off\n\ts_mov_b32 s0, s3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v8\n\tv_and_b32_e64 v4, v4, s0\n\ts_mov_b32 s1, s2\n ; kill: def $vgpr7 killed $vgpr7 killed $vgpr7_vgpr8 killed $exec\n\tv_and_b32_e64 v7, v7, s1\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v4\n\tv_mov_b32_e32 v4, v7\n\ts_mov_b32 s3, 24\n\tv_mad_u64_u32 v[9:10], s2, v4, s3, 0\n\tv_mov_b32_e32 v11, v10\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v4, s2\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\ts_mov_b32 s2, 32\n\tv_lshrrev_b64 v[7:8], s2, v[7:8]\n\tv_mov_b32_e32 v4, v7\n\tv_mad_u64_u32 v[7:8], s3, v4, s3, v[11:12]\n ; kill: def $vgpr7 killed $vgpr7 killed $vgpr7_vgpr8 killed $exec\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v4, s3\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v4\n\tv_lshlrev_b64 v[7:8], s2, v[7:8]\n\tv_mov_b32_e32 v11, v8\n ; kill: def $vgpr9 killed $vgpr9 killed $vgpr9_vgpr10 killed $exec\n\ts_mov_b32 s2, 0\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v4, v10\n\tv_or_b32_e64 v4, v4, v11\n\tv_mov_b32_e32 v8, v7\n\tv_mov_b32_e32 v7, v9\n\tv_or_b32_e64 v8, v7, v8\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v8\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v9\n\tv_add_co_u32 v4, s2, v4, v7\n\tv_add_co_ci_u32_e64 v6, s2, v5, v6, s2\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tscratch_store_b64 off, v[4:5], s33 offset:232 ; 8-byte Folded Spill\n\tglobal_store_b64 v[4:5], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s1\n\tv_mov_b32_e32 v10, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s2, v[0:1], v[2:3]\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s2, 23\n\tv_writelane_b32 v26, s0, 24\n\tscratch_store_b64 off, v[0:1], s33 offset:224 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 25\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_14\n.LBB3_10: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 24\n\tv_readlane_b32 s1, v26, 23\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[2:3], off, s33 offset:224 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:240 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:232 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_store_b64 v[4:5], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n\ts_mov_b32 s1, s3\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v10, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s1, v[0:1], v[2:3]\n\ts_or_b32 s0, s1, s0\n\tv_writelane_b32 v26, s1, 23\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 24\n\tscratch_store_b64 off, v[0:1], s33 offset:224 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 26\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_10\n; %bb.11:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 26\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.12:\n\ts_branch .LBB3_14\n.LBB3_13:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_branch .LBB3_15\n.LBB3_14:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 25\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s15, v26, 2\n\tv_readlane_b32 s14, v26, 3\n\tv_readlane_b32 s13, v26, 4\n\tv_readlane_b32 s12, v26, 5\n\tv_readlane_b32 s10, v26, 6\n\tv_readlane_b32 s11, v26, 7\n\tv_readlane_b32 s8, v26, 8\n\tv_readlane_b32 s9, v26, 9\n\tv_readlane_b32 s6, v26, 0\n\tv_readlane_b32 s7, v26, 1\n\tv_readlane_b32 s4, v26, 10\n\tv_readlane_b32 s5, v26, 11\n\tscratch_load_b32 v31, off, s33 offset:132 ; 4-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_mov_b32 s0, 32\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[0:1], s0, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v2\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hsa_signal_add@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hsa_signal_add@rel32@hi+12\n\tv_mov_b32_e32 v2, 1\n\tv_mov_b32_e32 v3, 0\n\tv_mov_b32_e32 v4, 3\n\ts_swappc_b64 s[30:31], s[0:1]\n\ts_branch .LBB3_13\n.LBB3_15:\n\tscratch_load_b64 v[6:7], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[3:4], s0, v2, s1, 0\n\tv_mov_b32_e32 v8, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v2\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[0:1]\n\tv_mov_b32_e32 v2, v0\n\tv_mad_u64_u32 v[0:1], s1, v2, s1, v[8:9]\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_lshlrev_b64 v[1:2], s0, v[0:1]\n\tv_mov_b32_e32 v5, v2\n ; kill: def $vgpr3 killed $vgpr3 killed $vgpr3_vgpr4 killed $exec\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_mov_b32_e32 v0, v4\n\tv_or_b32_e64 v0, v0, v5\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v1, v3\n\tv_or_b32_e64 v4, v1, v2\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v1, v6\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v1, s0, v1, v3\n\tv_add_co_ci_u32_e64 v0, s0, v0, v2, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b64 s[2:3], 20\n\tv_mov_b32_e32 v0, v1\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v1, v2\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v0, s1, v0, s1\n\tv_add_co_ci_u32_e64 v2, s0, v1, s0, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:248 ; 8-byte Folded Spill\n.LBB3_16: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 12\n\ts_mov_b32 s0, 1\n\tv_mov_b32_e32 v0, 1\n\tscratch_store_b32 off, v0, s33 offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 27\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_18\n; %bb.17: ; in Loop: Header=BB3_16 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:248 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b32 v0, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b32 s0, 1\n\tv_and_b32_e64 v0, v0, s0\n\tscratch_store_b32 off, v0, s33 offset:256 ; 4-byte Folded Spill\n.LBB3_18: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 27\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s33 offset:256 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s1, v0\n\ts_mov_b32 s0, -1\n\ts_mov_b32 s2, 0\n\ts_cmp_eq_u32 s1, s2\n\tv_writelane_b32 v26, s0, 28\n\ts_mov_b32 s17, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_cbranch_scc1 .LBB3_20\n; %bb.19: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_sleep 1\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v26, s0, 28\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n.LBB3_20: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 28\n\tv_cndmask_b32_e64 v0, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v0, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n\ts_cbranch_vccnz .LBB3_16\n; %bb.21:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[0:1], off, s33 offset:208 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:216 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[2:3], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:268 ; 8-byte Folded Spill\n\tglobal_load_b64 v[0:1], v[0:1], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:260 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 29\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_27\n; %bb.22:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:192 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[11:12], v[2:3], off\n\ts_mov_b64 s[4:5], 1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v11\n\ts_mov_b32 s1, s4\n\tv_mov_b32_e32 v3, v12\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v4, v2\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v5, v3\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v4, s1, v4, s1\n\tv_add_co_ci_u32_e64 v6, s0, v5, s0, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_eq_u64_e64 s0, v[4:5], s[0:1]\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v6, v5\n\tv_cndmask_b32_e64 v10, v6, v7, s0\n\tv_mov_b32_e32 v3, v2\n\tv_mov_b32_e32 v2, v4\n\tv_cndmask_b32_e64 v4, v2, v3, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v8, v4\n\tv_mov_b32_e32 v9, v10\n\tv_mov_b32_e32 v2, v8\n\tv_mov_b32_e32 v3, v9\n\tscratch_store_b64 off, v[2:3], s33 offset:300 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], 24\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v5, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v5\n\tscratch_store_b64 off, v[2:3], s33 offset:292 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:24 glc\n\tglobal_load_b64 v[6:7], v[0:1], off\n\tv_mov_b32_e32 v5, v9\n\tv_mov_b32_e32 v13, v12\n\tv_and_b32_e64 v5, v5, v13\n ; kill: def $vgpr8 killed $vgpr8 killed $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v11\n\tv_and_b32_e64 v8, v8, v9\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v5\n\tv_mov_b32_e32 v5, v8\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[11:12], s0, v5, s1, 0\n\tv_mov_b32_e32 v13, v12\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v5, s0\n ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec\n\tv_mov_b32_e32 v14, v5\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[8:9], s0, v[8:9]\n\tv_mov_b32_e32 v5, v8\n\tv_mad_u64_u32 v[8:9], s1, v5, s1, v[13:14]\n ; kill: def $vgpr8 killed $vgpr8 killed $vgpr8_vgpr9 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v5, s1\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v5\n\tv_lshlrev_b64 v[8:9], s0, v[8:9]\n\tv_mov_b32_e32 v13, v9\n ; kill: def $vgpr11 killed $vgpr11 killed $vgpr11_vgpr12 killed $exec\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v5, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v5\n\tv_mov_b32_e32 v5, v12\n\tv_or_b32_e64 v5, v5, v13\n\tv_mov_b32_e32 v9, v8\n\tv_mov_b32_e32 v8, v11\n\tv_or_b32_e64 v11, v8, v9\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v5\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v8, v11\n\tv_mov_b32_e32 v6, v7\n\tv_mov_b32_e32 v7, v12\n\tv_add_co_u32 v5, s0, v5, v8\n\tv_add_co_ci_u32_e64 v7, s0, v6, v7, s0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v7\n\tscratch_store_b64 off, v[5:6], s33 offset:284 ; 8-byte Folded Spill\n\tglobal_store_b64 v[5:6], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s2, v[0:1], v[2:3]\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s2, 30\n\tv_writelane_b32 v26, s0, 31\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\tscratch_store_b64 off, v[0:1], s33 offset:276 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n ; implicit-def: $vgpr26 : SGPR spill to VGPR lane\n\tv_writelane_b32 v26, s0, 0\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_26\n.LBB3_23: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v25, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v25, 31\n\tv_readlane_b32 s1, v25, 30\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\tscratch_load_b64 v[2:3], off, s33 offset:276 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:292 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:300 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:284 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_store_b64 v[6:7], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v10, v5\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s1, v[0:1], v[2:3]\n\ts_or_b32 s0, s1, s0\n\tv_writelane_b32 v25, s1, 30\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v25, s1, 31\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v25, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\tscratch_store_b64 off, v[0:1], s33 offset:276 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_23\n; %bb.24:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.25:\n.LBB3_26:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 0\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB3_27:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[3:4], off, s33 offset:260 ; 8-byte Folded Reload\n\tscratch_load_b64 v[1:2], off, s33 offset:268 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v3\n\tv_mov_b32_e32 v3, v4\n\tv_readlane_b32 s30, v24, 0\n\tv_readlane_b32 s31, v24, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v24, off, s33 offset:308 ; 4-byte Folded Reload\n\tscratch_load_b32 v25, off, s33 offset:312 ; 4-byte Folded Reload\n\tscratch_load_b32 v26, off, s33 offset:316 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xfffffeb0\n\ts_mov_b32 s33, s18\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end3:\n\t.size\t__ockl_hostcall_internal, .Lfunc_end3-__ockl_hostcall_internal\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 5344\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 392\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hostcall_preview\n\t.type\t__ockl_hostcall_preview,@function\n__ockl_hostcall_preview: ; @__ockl_hostcall_preview\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v27, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tv_writelane_b32 v27, s33, 0\n\tv_writelane_b32 v27, s30, 1\n\tv_writelane_b32 v27, s31, 2\n\tv_mov_b32_e32 v18, v16\n\tv_mov_b32_e32 v17, v15\n\tv_mov_b32_e32 v16, v14\n\tv_mov_b32_e32 v15, v13\n\tv_mov_b32_e32 v14, v12\n\tv_mov_b32_e32 v13, v11\n\tv_mov_b32_e32 v12, v10\n\tv_mov_b32_e32 v11, v9\n\tv_mov_b32_e32 v10, v8\n\tv_mov_b32_e32 v9, v7\n\tv_mov_b32_e32 v8, v6\n\tv_mov_b32_e32 v7, v5\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v5, v3\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s0, s[0:1], 0x0\n\ts_mov_b32 s1, 0x1f4\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_i32 s0, s1\n\ts_mov_b32 s1, 0x50\n\ts_mov_b32 s0, 24\n\ts_cselect_b32 s0, s0, s1\n\ts_load_b64 s[0:1], s[8:9], s0 offset:0x0\n\ts_waitcnt lgkmcnt(0)\n\ts_mov_b32 s3, s0\n\ts_mov_b32 s2, 32\n\ts_lshr_b64 s[0:1], s[0:1], s2\n\ts_mov_b32 s2, s0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_internal@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_internal@rel32@hi+12\n\tv_mov_b32_e32 v0, s3\n\tv_mov_b32_e32 v1, s2\n\tv_readlane_b32 s30, v27, 1\n\tv_readlane_b32 s31, v27, 2\n\tv_readlane_b32 s33, v27, 0\n\ts_xor_saveexec_b32 s2, -1\n\tscratch_load_b32 v27, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s2\n\ts_setpc_b64 s[0:1]\n.Lfunc_end4:\n\t.size\t__ockl_hostcall_preview, .Lfunc_end4-__ockl_hostcall_preview\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 272\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 400\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_stderr_begin\n\t.type\t__ockl_fprintf_stderr_begin,@function\n__ockl_fprintf_stderr_begin: ; @__ockl_fprintf_stderr_begin\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s16, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v28, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 16\n\tv_writelane_b32 v28, s30, 0\n\tv_writelane_b32 v28, s31, 1\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\tv_mov_b32_e32 v1, 33\n\tv_mov_b32_e32 v3, 1\n\tv_mov_b32_e32 v16, 0\n\tv_mov_b32_e32 v2, v16\n\tv_mov_b32_e32 v4, v16\n\tv_mov_b32_e32 v5, v16\n\tv_mov_b32_e32 v6, v16\n\tv_mov_b32_e32 v7, v16\n\tv_mov_b32_e32 v8, v16\n\tv_mov_b32_e32 v9, v16\n\tv_mov_b32_e32 v10, v16\n\tv_mov_b32_e32 v11, v16\n\tv_mov_b32_e32 v12, v16\n\tv_mov_b32_e32 v13, v16\n\tv_mov_b32_e32 v14, v16\n\tv_mov_b32_e32 v15, v16\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_store_b32 off, v1, s33 ; 4-byte Folded Spill\n ; kill: def $vgpr1 killed $vgpr3 killed $exec\n\tscratch_load_b32 v3, off, s33 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v3\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v28, 0\n\tv_readlane_b32 s31, v28, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v28, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, -16\n\ts_mov_b32 s33, s16\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end5:\n\t.size\t__ockl_fprintf_stderr_begin, .Lfunc_end5-__ockl_fprintf_stderr_begin\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 228\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 416\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_append_string_n\n\t.type\t__ockl_fprintf_append_string_n,@function\n__ockl_fprintf_append_string_n: ; @__ockl_fprintf_append_string_n\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s20, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v32, s33 offset:704 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v33, s33 offset:708 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v34, s33 offset:712 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0x2d0\n\tv_writelane_b32 v32, s30, 0\n\tv_writelane_b32 v32, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:68 ; 4-byte Folded Spill\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\tv_writelane_b32 v34, s6, 0\n\tv_writelane_b32 v34, s7, 1\n\tscratch_store_b32 off, v6, s33 offset:60 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v5, s33 offset:56 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v4, s33 offset:64 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v6, v3\n\tscratch_load_b32 v3, off, s33 offset:64 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v4, v2\n\tscratch_load_b32 v2, off, s33 offset:60 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v4, s33 offset:52 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v7, v1\n\tscratch_load_b32 v1, off, s33 offset:56 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v5, v0\n\tscratch_load_b32 v0, off, s33 offset:52 ; 4-byte Folded Reload\n\tv_writelane_b32 v34, s15, 2\n\tv_writelane_b32 v34, s14, 3\n\tv_writelane_b32 v34, s13, 4\n\tv_writelane_b32 v34, s12, 5\n\tv_writelane_b32 v34, s10, 6\n\tv_writelane_b32 v34, s11, 7\n\tv_writelane_b32 v34, s8, 8\n\tv_writelane_b32 v34, s9, 9\n\tv_writelane_b32 v34, s4, 10\n\tv_writelane_b32 v34, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v1\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v7\n\tscratch_store_b64 off, v[3:4], s33 offset:44 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v3, v0\n\tscratch_store_b64 off, v[3:4], s33 offset:36 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s0, 0\n\tv_cmp_eq_u32_e64 s0, v2, s0\n\tv_mov_b32_e32 v4, v6\n\ts_mov_b64 s[2:3], 2\n\ts_mov_b32 s1, s3\n\tv_or_b32_e64 v2, v4, s1\n\tv_mov_b32_e32 v3, v5\n\ts_mov_b32 s1, s2\n\tv_or_b32_e64 v5, v3, s1\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v2\n\tv_mov_b32_e32 v2, v6\n\tv_cndmask_b32_e64 v4, v2, v4, s0\n\tv_mov_b32_e32 v2, v5\n\tv_cndmask_b32_e64 v2, v2, v3, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:28 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_ne_u64_e64 s0, v[0:1], s[0:1]\n ; implicit-def: $sgpr4_sgpr5_sgpr6_sgpr7\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tv_mov_b32_e32 v2, s6\n\tv_mov_b32_e32 v3, s7\n\tscratch_store_b128 off, v[0:3], s33 offset:12 ; 16-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 12\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_3\n\ts_branch .LBB6_2\n.LBB6_1:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v34, 2\n\tv_readlane_b32 s14, v34, 3\n\tv_readlane_b32 s13, v34, 4\n\tv_readlane_b32 s12, v34, 5\n\tv_readlane_b32 s10, v34, 6\n\tv_readlane_b32 s11, v34, 7\n\tv_readlane_b32 s8, v34, 8\n\tv_readlane_b32 s9, v34, 9\n\tv_readlane_b32 s6, v34, 0\n\tv_readlane_b32 s7, v34, 1\n\tv_readlane_b32 s4, v34, 10\n\tv_readlane_b32 s5, v34, 11\n\tscratch_load_b32 v31, off, s33 offset:68 ; 4-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:28 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v3\n\tv_and_b32_e64 v4, v0, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v0, v2\n\tv_and_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_mov_b32_e32 v4, v1\n\ts_mov_b64 s[0:1], 32\n\ts_mov_b32 s2, s1\n\tv_or_b32_e64 v4, v4, s2\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_or_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_mov_b32_e32 v1, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[2:3], s0, v[2:3]\n ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\tv_mov_b32_e32 v16, 0\n\tscratch_store_b32 off, v16, s33 offset:88 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v16\n\tv_mov_b32_e32 v4, v16\n\tv_mov_b32_e32 v5, v16\n\tv_mov_b32_e32 v6, v16\n\tv_mov_b32_e32 v7, v16\n\tv_mov_b32_e32 v8, v16\n\tv_mov_b32_e32 v9, v16\n\tv_mov_b32_e32 v10, v16\n\tv_mov_b32_e32 v11, v16\n\tv_mov_b32_e32 v12, v16\n\tv_mov_b32_e32 v13, v16\n\tv_mov_b32_e32 v14, v16\n\tv_mov_b32_e32 v15, v16\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_mov_b32_e32 v6, v1\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v4, v3\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v6\n\tv_mov_b32_e32 v2, v5\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b128 off, v[0:3], s33 offset:72 ; 16-byte Folded Spill\n\ts_branch .LBB6_63\n.LBB6_2:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b64 v[4:5], off, s33 offset:36 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:44 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:28 ; 8-byte Folded Reload\n\ts_mov_b64 s[0:1], 2\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v1, v3\n\tv_and_b32_e64 v8, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v0, v2\n\tv_and_b32_e64 v2, v0, s0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v8\n\tscratch_store_b64 off, v[2:3], s33 offset:124 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], -3\n\ts_mov_b32 s2, s1\n\tv_and_b32_e64 v2, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_and_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v10, v1\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\ts_mov_b64 s[2:3], 0\n\ts_mov_b32 s0, s3\n\ts_mov_b32 s1, s2\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v9, s1\n\tv_mov_b32_e32 v8, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v10\n\tv_mov_b32_e32 v2, v9\n\tv_mov_b32_e32 v3, v8\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v34, s0, 13\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[6:7], s33 offset:116 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[4:5], s33 offset:108 ; 8-byte Folded Spill\n\tscratch_store_b128 off, v[0:3], s33 offset:92 ; 16-byte Folded Spill\n\ts_branch .LBB6_4\n.LBB6_3:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 12\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b128 v[0:3], off, s33 offset:12 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:72 ; 16-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 14\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_63\n\ts_branch .LBB6_1\n.LBB6_4: ; =>This Loop Header: Depth=1\n ; Child Loop BB6_8 Depth 2\n ; Child Loop BB6_16 Depth 2\n ; Child Loop BB6_24 Depth 2\n ; Child Loop BB6_32 Depth 2\n ; Child Loop BB6_40 Depth 2\n ; Child Loop BB6_48 Depth 2\n ; Child Loop BB6_56 Depth 2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 13\n\tscratch_load_b64 v[6:7], off, s33 offset:124 ; 8-byte Folded Reload\n\tscratch_load_b128 v[8:11], off, s33 offset:92 ; 16-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:116 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:108 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:176 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[3:4], s33 offset:168 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 15\n\ts_mov_b64 s[2:3], 56\n\tv_cmp_gt_u64_e64 s0, v[3:4], s[2:3]\n\tv_mov_b32_e32 v1, v9\n\tv_mov_b32_e32 v2, v8\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v8, v2\n\tv_mov_b32_e32 v9, v1\n\tv_mov_b32_e32 v0, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or_b32_e64 v0, v0, v5\n\tv_mov_b32_e32 v5, v8\n\tv_or_b32_e64 v5, v5, v6\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v0\n\tv_mov_b32_e32 v0, v6\n\tv_cndmask_b32_e64 v0, v0, v1, s0\n\tv_mov_b32_e32 v1, v5\n\tv_cndmask_b32_e64 v1, v1, v2, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_cmp_lt_u64_e64 s1, v[3:4], s[2:3]\n\tv_mov_b32_e32 v0, v4\n\ts_mov_b32 s0, s3\n\tv_cndmask_b32_e64 v5, s0, v0, s1\n\tv_mov_b32_e32 v0, v3\n\ts_mov_b32 s0, s2\n\tv_cndmask_b32_e64 v0, s0, v0, s1\n\tscratch_store_b32 off, v0, s33 offset:164 ; 4-byte Folded Spill\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v3, v0\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:156 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:148 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:140 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:132 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 16\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_6\n; %bb.5: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:164 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 17\n\tv_writelane_b32 v34, s0, 18\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:184 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_11\n\ts_branch .LBB6_8\n.LBB6_6: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 16\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 20\n\tscratch_load_b64 v[0:1], off, s33 offset:140 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:132 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:212 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:208 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:200 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 21\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_12\n; %bb.7: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:212 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:208 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:200 ; 8-byte Folded Spill\n\ts_branch .LBB6_12\n.LBB6_8: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 18\n\tv_readlane_b32 s2, v34, 17\n\tscratch_load_b64 v[4:5], off, s33 offset:192 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:176 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 17\n\tv_writelane_b32 v34, s1, 18\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:220 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 22\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_8\n; %bb.9: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.10: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:220 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:184 ; 8-byte Folded Spill\n.LBB6_11: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 19\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:140 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 20\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:132 ; 8-byte Folded Spill\n\ts_branch .LBB6_6\n.LBB6_12: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:212 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:208 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:200 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:256 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:252 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:244 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:236 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:228 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 23\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_14\n; %bb.13: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:252 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 24\n\tv_writelane_b32 v34, s0, 25\n\tscratch_store_b64 off, v[2:3], s33 offset:272 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:264 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 26\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_19\n\ts_branch .LBB6_16\n.LBB6_14: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 23\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 27\n\tscratch_load_b64 v[0:1], off, s33 offset:236 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:228 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:292 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:288 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:280 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 28\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_20\n; %bb.15: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:244 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:252 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:292 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:288 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:280 ; 8-byte Folded Spill\n\ts_branch .LBB6_20\n.LBB6_16: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 25\n\tv_readlane_b32 s2, v34, 24\n\tscratch_load_b64 v[4:5], off, s33 offset:272 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:252 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:244 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 24\n\tv_writelane_b32 v34, s1, 25\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:272 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:300 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 29\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_16\n; %bb.17: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.18: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:300 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:264 ; 8-byte Folded Spill\n.LBB6_19: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 26\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:244 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:264 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:236 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 27\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:228 ; 8-byte Folded Spill\n\ts_branch .LBB6_14\n.LBB6_20: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 28\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:292 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:288 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:280 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:336 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:332 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:324 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:316 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:308 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 30\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_22\n; %bb.21: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:332 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v33, s2, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tv_writelane_b32 v34, s0, 0\n\tscratch_store_b64 off, v[2:3], s33 offset:352 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:344 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_27\n\ts_branch .LBB6_24\n.LBB6_22: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v33, 30\n\ts_or_saveexec_b32 s0, s0\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v34, 2\n\tscratch_load_b64 v[0:1], off, s33 offset:316 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:308 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:372 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:368 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:360 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 3\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_28\n; %bb.23: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:324 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:332 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:372 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:368 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:360 ; 8-byte Folded Spill\n\ts_branch .LBB6_28\n.LBB6_24: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 0\n\tv_readlane_b32 s2, v33, 31\n\tscratch_load_b64 v[4:5], off, s33 offset:352 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:332 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:324 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v33, s2, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tv_writelane_b32 v34, s1, 0\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:352 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:380 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 4\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_24\n; %bb.25: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.26: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:380 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:344 ; 8-byte Folded Spill\n.LBB6_27: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:324 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:344 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:316 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:308 ; 8-byte Folded Spill\n\ts_branch .LBB6_22\n.LBB6_28: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 3\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:372 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:368 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:360 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:416 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:412 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:404 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:396 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:388 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 5\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_30\n; %bb.29: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:412 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 6\n\tv_writelane_b32 v34, s0, 7\n\tscratch_store_b64 off, v[2:3], s33 offset:432 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:424 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 8\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_35\n\ts_branch .LBB6_32\n.LBB6_30: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 5\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 9\n\tscratch_load_b64 v[0:1], off, s33 offset:396 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:388 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:452 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:448 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:440 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 10\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_36\n; %bb.31: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:404 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:412 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:452 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:448 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:440 ; 8-byte Folded Spill\n\ts_branch .LBB6_36\n.LBB6_32: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 7\n\tv_readlane_b32 s2, v34, 6\n\tscratch_load_b64 v[4:5], off, s33 offset:432 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:412 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:404 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 6\n\tv_writelane_b32 v34, s1, 7\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:432 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:460 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 11\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_32\n; %bb.33: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 11\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.34: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:460 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:424 ; 8-byte Folded Spill\n.LBB6_35: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 8\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:404 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:424 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:396 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 9\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:388 ; 8-byte Folded Spill\n\ts_branch .LBB6_30\n.LBB6_36: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 10\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:452 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:448 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:440 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:496 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:492 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:484 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:476 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:468 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 12\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_38\n; %bb.37: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:492 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 13\n\tv_writelane_b32 v34, s0, 14\n\tscratch_store_b64 off, v[2:3], s33 offset:512 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:504 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 15\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_43\n\ts_branch .LBB6_40\n.LBB6_38: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 12\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 16\n\tscratch_load_b64 v[0:1], off, s33 offset:476 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:468 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:532 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:528 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:520 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 17\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_44\n; %bb.39: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:484 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:492 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:532 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:528 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:520 ; 8-byte Folded Spill\n\ts_branch .LBB6_44\n.LBB6_40: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 14\n\tv_readlane_b32 s2, v34, 13\n\tscratch_load_b64 v[4:5], off, s33 offset:512 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:492 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:484 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 13\n\tv_writelane_b32 v34, s1, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:512 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:540 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 18\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_40\n; %bb.41: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 18\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.42: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:540 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:504 ; 8-byte Folded Spill\n.LBB6_43: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:484 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:504 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:476 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 16\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:468 ; 8-byte Folded Spill\n\ts_branch .LBB6_38\n.LBB6_44: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 17\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:532 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:528 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:520 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:576 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:572 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:564 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:556 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:548 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_46\n; %bb.45: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:572 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 20\n\tv_writelane_b32 v34, s0, 21\n\tscratch_store_b64 off, v[2:3], s33 offset:592 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:584 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 22\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_51\n\ts_branch .LBB6_48\n.LBB6_46: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 19\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 23\n\tscratch_load_b64 v[0:1], off, s33 offset:556 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:548 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:612 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:608 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:600 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 24\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_52\n; %bb.47: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:564 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:572 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:612 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:608 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:600 ; 8-byte Folded Spill\n\ts_branch .LBB6_52\n.LBB6_48: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 21\n\tv_readlane_b32 s2, v34, 20\n\tscratch_load_b64 v[4:5], off, s33 offset:592 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:572 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:564 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 20\n\tv_writelane_b32 v34, s1, 21\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:592 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:620 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 25\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_48\n; %bb.49: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 25\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.50: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:620 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:584 ; 8-byte Folded Spill\n.LBB6_51: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:564 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:584 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:556 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 23\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:548 ; 8-byte Folded Spill\n\ts_branch .LBB6_46\n.LBB6_52: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 24\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:612 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:608 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:600 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:648 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:644 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:636 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s33 offset:628 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 26\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_54\n; %bb.53: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:644 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 27\n\tv_writelane_b32 v34, s0, 28\n\tscratch_store_b64 off, v[2:3], s33 offset:664 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:656 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 29\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_59\n\ts_branch .LBB6_56\n.LBB6_54: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 26\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:628 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:672 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 30\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_60\n; %bb.55: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[2:3], off, s33 offset:636 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tflat_load_u8 v0, v[2:3]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v4, v[2:3] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v5, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v7, v1\n\tv_mov_b32_e32 v4, v6\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v5\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v4\n\tflat_load_u8 v4, v[2:3] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v8, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v4\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v10, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or3_b32 v4, v4, v5, v10\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v5, v8\n\tv_mov_b32_e32 v1, v6\n\tv_or3_b32 v0, v0, v1, v5\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v4, s1, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[6:7], s2, v[4:5]\n\tflat_load_u8 v4, v[2:3] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v4, s1, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[8:9], s0, v[4:5]\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v10, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or3_b32 v4, v4, v5, v10\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v5, v8\n\tv_mov_b32_e32 v1, v6\n\tv_or3_b32 v0, v0, v1, v5\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:6\n\tv_mov_b32_e32 v6, 0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[4:5], s0, v[4:5]\n\tflat_load_u8 v2, v[2:3] offset:7\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v6\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[6:7], s0, v[2:3]\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v8, v7\n\tv_mov_b32_e32 v3, v5\n\tv_or3_b32 v2, v2, v3, v8\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v3, v6\n\tv_mov_b32_e32 v1, v4\n\tv_or3_b32 v0, v0, v1, v3\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:672 ; 8-byte Folded Spill\n\ts_branch .LBB6_60\n.LBB6_56: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 28\n\tv_readlane_b32 s2, v34, 27\n\tscratch_load_b64 v[4:5], off, s33 offset:664 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:644 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:636 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 27\n\tv_writelane_b32 v34, s1, 28\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:664 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:680 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_56\n; %bb.57: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 31\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.58: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:680 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:656 ; 8-byte Folded Spill\n.LBB6_59: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:656 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:628 ; 8-byte Folded Spill\n\ts_branch .LBB6_54\n.LBB6_60: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v34, 30\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v33, 2\n\tv_readlane_b32 s14, v33, 3\n\tv_readlane_b32 s13, v33, 4\n\tv_readlane_b32 s12, v33, 5\n\tv_readlane_b32 s10, v33, 6\n\tv_readlane_b32 s11, v33, 7\n\tv_readlane_b32 s8, v33, 8\n\tv_readlane_b32 s9, v33, 9\n\tv_readlane_b32 s6, v33, 0\n\tv_readlane_b32 s7, v33, 1\n\tv_readlane_b32 s4, v33, 10\n\tv_readlane_b32 s5, v33, 11\n\tscratch_load_b64 v[0:1], off, s33 offset:156 ; 8-byte Folded Reload\n\tscratch_load_b32 v31, off, s33 offset:68 ; 4-byte Folded Reload\n\tscratch_load_b64 v[19:20], off, s33 offset:648 ; 8-byte Folded Reload\n\tscratch_load_b64 v[21:22], off, s33 offset:576 ; 8-byte Folded Reload\n\tscratch_load_b64 v[23:24], off, s33 offset:496 ; 8-byte Folded Reload\n\tscratch_load_b64 v[25:26], off, s33 offset:416 ; 8-byte Folded Reload\n\tscratch_load_b64 v[27:28], off, s33 offset:336 ; 8-byte Folded Reload\n\tscratch_load_b64 v[29:30], off, s33 offset:256 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:148 ; 8-byte Folded Reload\n\tscratch_load_b64 v[17:18], off, s33 offset:672 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(9)\n\tv_mov_b32_e32 v1, v0\n\ts_mov_b32 s0, 28\n\tv_mov_b32_e32 v0, 2\n\tv_lshl_add_u32 v1, v1, v0, s0\n\ts_mov_b32 s0, 0x1e0\n\tv_and_b32_e64 v5, v1, s0\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v1, 0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v1\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v1, v3\n\tv_and_b32_e64 v1, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v4, v2\n\tv_and_b32_e64 v7, v4, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v4, v6\n\tv_or_b32_e64 v1, v1, v4\n\tv_mov_b32_e32 v4, v7\n ; kill: def $vgpr5 killed $vgpr5 killed $vgpr5_vgpr6 killed $exec\n\tv_or_b32_e64 v4, v4, v5\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v1\n\tv_mov_b32_e32 v1, v4\n\ts_mov_b32 s0, 32\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\tv_writelane_b32 v34, s0, 0\n\tv_lshrrev_b64 v[2:3], s0, v[2:3]\n ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec\n\tv_lshrrev_b64 v[3:4], s0, v[29:30]\n\tv_mov_b32_e32 v4, v3\n\tv_lshrrev_b64 v[5:6], s0, v[27:28]\n\tv_mov_b32_e32 v6, v5\n\tv_lshrrev_b64 v[7:8], s0, v[25:26]\n\tv_mov_b32_e32 v8, v7\n\tv_lshrrev_b64 v[9:10], s0, v[23:24]\n\tv_mov_b32_e32 v10, v9\n\tv_lshrrev_b64 v[11:12], s0, v[21:22]\n\tv_mov_b32_e32 v12, v11\n\tv_lshrrev_b64 v[13:14], s0, v[19:20]\n\tv_mov_b32_e32 v14, v13\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[15:16], s0, v[17:18]\n\tv_mov_b32_e32 v16, v15\n\tv_mov_b32_e32 v3, v29\n\tv_mov_b32_e32 v5, v27\n\tv_mov_b32_e32 v7, v25\n\tv_mov_b32_e32 v9, v23\n\tv_mov_b32_e32 v11, v21\n\tv_mov_b32_e32 v13, v19\n\tv_mov_b32_e32 v15, v17\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b64 v[4:5], off, s33 offset:168 ; 8-byte Folded Reload\n\tscratch_load_b64 v[12:13], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b64 v[10:11], off, s33 offset:156 ; 8-byte Folded Reload\n\tv_readlane_b32 s1, v33, 15\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v7, v2\n\tv_mov_b32_e32 v6, v3\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v2, v7\n\tv_mov_b32_e32 v3, v6\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v6, v4\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v5, v11\n\tv_sub_co_u32 v6, s0, v6, v7\n\tv_sub_co_ci_u32_e64 v4, s0, v4, v5, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v4\n\tv_mov_b32_e32 v4, v12\n\tv_mov_b32_e32 v9, v10\n\tv_mov_b32_e32 v5, v13\n\tv_mov_b32_e32 v8, v11\n\tv_add_co_u32 v4, s0, v4, v9\n\tv_add_co_ci_u32_e64 v8, s0, v5, v8, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v8\n\ts_mov_b64 s[2:3], 0\n\tv_cmp_eq_u64_e64 s0, v[6:7], s[2:3]\n\ts_or_b32 s0, s0, s1\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v33, s1, 13\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[6:7], s33 offset:116 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[4:5], s33 offset:108 ; 8-byte Folded Spill\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v6, v2\n\tv_mov_b32_e32 v5, v1\n\tv_mov_b32_e32 v4, v0\n\tscratch_store_b128 off, v[4:7], s33 offset:92 ; 16-byte Folded Spill\n\tscratch_store_b128 off, v[0:3], s33 offset:688 ; 16-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:8 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_4\n; %bb.61:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:8 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.62:\n\tscratch_load_b128 v[0:3], off, s33 offset:688 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:12 ; 16-byte Folded Spill\n\ts_branch .LBB6_3\n.LBB6_63:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 14\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b128 v[3:6], off, s33 offset:72 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v0, v3\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v32, 0\n\tv_readlane_b32 s31, v32, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v32, off, s33 offset:704 ; 4-byte Folded Reload\n\tscratch_load_b32 v33, off, s33 offset:708 ; 4-byte Folded Reload\n\tscratch_load_b32 v34, off, s33 offset:712 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xfffffd30\n\ts_mov_b32 s33, s20\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end6:\n\t.size\t__ockl_fprintf_append_string_n, .Lfunc_end6-__ockl_fprintf_append_string_n\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 11984\n; NumSgprs: 36\n; NumVgprs: 35\n; ScratchSize: 1120\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_append_args\n\t.type\t__ockl_fprintf_append_args,@function\n__ockl_fprintf_append_args: ; @__ockl_fprintf_append_args\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s19, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v28, s33 offset:8 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v29, s33 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 32\n\tv_writelane_b32 v28, s30, 0\n\tv_writelane_b32 v28, s31, 1\n\tscratch_store_b32 off, v17, s33 offset:4 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v17, v2\n\tv_mov_b32_e32 v18, v0\n\tscratch_load_b32 v0, off, s33 offset:4 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v15\n ; kill: def $vgpr20 killed $vgpr16 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v13\n ; kill: def $vgpr20 killed $vgpr14 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v11\n ; kill: def $vgpr20 killed $vgpr12 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v9\n ; kill: def $vgpr20 killed $vgpr10 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v7\n ; kill: def $vgpr20 killed $vgpr8 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v5\n ; kill: def $vgpr20 killed $vgpr6 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v3\n ; kill: def $vgpr20 killed $vgpr4 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr18 killed $vgpr18 def $vgpr18_vgpr19 killed $exec\n\tv_mov_b32_e32 v19, v1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s0, v0, s0\n\tv_mov_b32_e32 v1, v19\n\ts_mov_b64 s[2:3], 2\n\ts_mov_b32 s1, s3\n\tv_or_b32_e64 v0, v1, s1\n\tv_mov_b32_e32 v2, v18\n\ts_mov_b32 s1, s2\n\tv_or_b32_e64 v18, v2, s1\n ; kill: def $vgpr18 killed $vgpr18 def $vgpr18_vgpr19 killed $exec\n\tv_mov_b32_e32 v19, v0\n\tv_mov_b32_e32 v0, v19\n\tv_cndmask_b32_e64 v0, v0, v1, s0\n\tv_mov_b32_e32 v1, v18\n\tv_cndmask_b32_e64 v1, v1, v2, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v0, v2\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\tv_and_b32_e64 v0, v0, s2\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_and_b32_e64 v1, v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\tv_mov_b32_e32 v18, v0\n\ts_mov_b32 s0, 5\n\tv_lshlrev_b64 v[17:18], s0, v[17:18]\n\tv_mov_b32_e32 v0, v2\n\tv_mov_b32_e32 v19, v18\n\tv_or_b32_e64 v0, v0, v19\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v17\n\tv_or_b32_e64 v17, v1, v2\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\tv_mov_b32_e32 v18, v0\n\tv_mov_b32_e32 v1, v17\n\ts_mov_b32 s0, 32\n ; implicit-def: $vgpr29 : SGPR spill to VGPR lane\n\tv_writelane_b32 v29, s0, 0\n\tv_lshrrev_b64 v[17:18], s0, v[17:18]\n\tv_mov_b32_e32 v2, v17\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v29, 0\n\tscratch_store_b32 off, v1, s33 ; 4-byte Folded Spill\n ; kill: def $vgpr1 killed $vgpr3 killed $exec\n\tscratch_load_b32 v3, off, s33 ; 4-byte Folded Reload\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v1, s1\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v3\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v28, 0\n\tv_readlane_b32 s31, v28, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v28, off, s33 offset:8 ; 4-byte Folded Reload\n\tscratch_load_b32 v29, off, s33 offset:12 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xffffffe0\n\ts_mov_b32 s33, s19\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end7:\n\t.size\t__ockl_fprintf_append_args, .Lfunc_end7-__ockl_fprintf_append_args\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 452\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 432\n; MemoryBound: 0\n\t.text\n\t.hidden\t__assert_fail ; -- Begin function __assert_fail\n\t.weak\t__assert_fail\n\t.p2align\t2\n\t.type\t__assert_fail,@function\n__assert_fail: ; @__assert_fail\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s27, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v35, s33 offset:176 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v36, s33 offset:180 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v37, s33 offset:184 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xc0\n\tv_writelane_b32 v35, s30, 0\n\tv_writelane_b32 v35, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:168 ; 4-byte Folded Spill\n ; implicit-def: $vgpr37 : SGPR spill to VGPR lane\n\tv_writelane_b32 v37, s6, 0\n\tv_writelane_b32 v37, s7, 1\n\tscratch_store_b32 off, v5, s33 offset:164 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v3, s33 offset:160 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v5, v2\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v7, v0\n\tscratch_load_b32 v0, off, s33 offset:160 ; 4-byte Folded Reload\n\tv_writelane_b32 v37, s15, 2\n\tv_writelane_b32 v37, s14, 3\n\tv_writelane_b32 v37, s13, 4\n\tv_writelane_b32 v37, s12, 5\n\tv_writelane_b32 v37, s10, 6\n\tv_writelane_b32 v37, s11, 7\n\tv_writelane_b32 v37, s8, 8\n\tv_writelane_b32 v37, s9, 9\n\tv_writelane_b32 v37, s4, 10\n\tv_writelane_b32 v37, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v6, v0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b64 s[0:1], src_private_base\n\ts_mov_b32 s2, 32\n\ts_lshr_b64 s[0:1], s[0:1], s2\n\ts_mov_b32 s24, s0\n\tv_writelane_b32 v37, s24, 12\n\ts_mov_b32 s20, s33\n ; kill: def $sgpr20 killed $sgpr20 def $sgpr20_sgpr21\n\ts_mov_b32 s21, s24\n\ts_mov_b64 s[0:1], s[20:21]\n\tv_writelane_b32 v37, s0, 13\n\tv_writelane_b32 v37, s1, 14\n\ts_add_i32 s0, s33, 8\n\ts_mov_b32 s18, s0\n ; kill: def $sgpr18 killed $sgpr18 def $sgpr18_sgpr19\n\ts_mov_b32 s19, s24\n\ts_mov_b64 s[0:1], s[18:19]\n\tv_writelane_b32 v37, s0, 15\n\tv_writelane_b32 v37, s1, 16\n\ts_add_i32 s0, s33, 16\n\ts_mov_b32 s2, s0\n ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3\n\ts_mov_b32 s3, s24\n\ts_mov_b64 s[0:1], s[2:3]\n\tv_writelane_b32 v37, s0, 17\n\tv_writelane_b32 v37, s1, 18\n\ts_add_i32 s1, s33, 24\n\ts_mov_b32 s0, s1\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s24\n\ts_mov_b64 s[16:17], s[0:1]\n\tv_writelane_b32 v37, s16, 19\n\tv_writelane_b32 v37, s17, 20\n\ts_add_i32 s17, s33, 32\n\ts_mov_b32 s16, s17\n ; kill: def $sgpr16 killed $sgpr16 def $sgpr16_sgpr17\n\ts_mov_b32 s17, s24\n\tv_writelane_b32 v37, s16, 21\n\tv_writelane_b32 v37, s17, 22\n\ts_mov_b64 s[22:23], s[16:17]\n\tv_writelane_b32 v37, s22, 23\n\tv_writelane_b32 v37, s23, 24\n\ts_add_i32 s23, s33, 0x50\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v37, s22, 25\n\tv_writelane_b32 v37, s23, 26\n\tv_writelane_b32 v37, s22, 27\n\tv_writelane_b32 v37, s23, 28\n\ts_add_i32 s23, s33, 0x58\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v37, s22, 29\n\tv_writelane_b32 v37, s23, 30\n ; implicit-def: $vgpr36 : SGPR spill to VGPR lane\n\tv_writelane_b32 v37, s22, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:148 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_writelane_b32 v36, s23, 0\n\ts_add_i32 s23, s33, 0x60\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 1\n\tv_writelane_b32 v36, s23, 2\n\ts_add_i32 s23, s33, 0x68\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 3\n\tv_writelane_b32 v36, s23, 4\n\ts_add_i32 s23, s33, 0x70\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 5\n\tv_writelane_b32 v36, s23, 6\n\ts_add_i32 s23, s33, 0x78\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 7\n\tv_writelane_b32 v36, s23, 8\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_mov_b32_e32 v0, s20\n\tv_mov_b32_e32 v1, s21\n\tflat_store_b64 v[0:1], v[7:8]\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tflat_store_b64 v[0:1], v[5:6]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b32 v[0:1], v4\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, s33 offset:156 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+35\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+43\n\tglobal_load_b128 v[0:3], v0, s[0:1]\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:128\n\tscratch_load_b64 v[0:1], off, s33 offset:136\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_d16_hi_b8 v[3:4], v2 offset:45\n\ts_mov_b32 s1, 24\n\tv_lshrrev_b32_e64 v5, s1, v2\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v5 offset:46\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v2 offset:43\n\ts_mov_b32 s0, 8\n\tv_lshrrev_b32_e64 v4, s0, v2\n\tv_mov_b32_e32 v2, s16\n\tv_mov_b32_e32 v3, s17\n\tflat_store_b8 v[2:3], v4 offset:44\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_d16_hi_b8 v[1:2], v0 offset:41\n\tv_lshrrev_b32_e64 v3, s1, v0\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v3 offset:42\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v0 offset:39\n\tv_lshrrev_b32_e64 v2, s0, v0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b8 v[0:1], v2 offset:40\n\tscratch_load_b64 v[0:1], off, s33 offset:128\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_d16_hi_b8 v[3:4], v2 offset:37\n\tv_lshrrev_b32_e64 v5, s1, v2\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v5 offset:38\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v2 offset:35\n\tv_lshrrev_b32_e64 v4, s0, v2\n\tv_mov_b32_e32 v2, s16\n\tv_mov_b32_e32 v3, s17\n\tflat_store_b8 v[2:3], v4 offset:36\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_d16_hi_b8 v[1:2], v0 offset:33\n\tv_lshrrev_b32_e64 v3, s1, v0\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v3 offset:34\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v0 offset:31\n\tv_lshrrev_b32_e64 v2, s0, v0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b8 v[0:1], v2 offset:32\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+20\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+28\n\ts_load_b128 s[0:3], s[0:1], 0x0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v5, s3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b128 v[0:1], v[2:5] offset:16\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+4\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+12\n\ts_load_b128 s[0:3], s[0:1], 0x0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v5, s3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b128 v[0:1], v[2:5]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_stderr_begin@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_stderr_begin@rel32@hi+12\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v2, off, s33 offset:156 ; 4-byte Folded Reload\n\tv_readlane_b32 s2, v37, 25\n\tv_readlane_b32 s3, v37, 26\n\tv_readlane_b32 s0, v37, 29\n\tv_readlane_b32 s1, v37, 30\n\tv_mov_b32_e32 v3, v0\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b64 v[0:1], v[3:4]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0)\n\tflat_store_b32 v[0:1], v2\n; %bb.1:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 23\n\tv_readlane_b32 s1, v36, 24\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s3, v37, 2\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 9\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_2: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s3, v37, 2\n\tv_readlane_b32 s0, v37, 10\n\tv_readlane_b32 s1, v37, 9\n\tv_writelane_b32 v37, s1, 11\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 12\n\tv_writelane_b32 v37, s0, 13\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 14\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_4\n; %bb.3: ; in Loop: Header=BB8_2 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 12\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 13\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_4: ; in Loop: Header=BB8_2 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 14\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 11\n\tv_readlane_b32 s1, v37, 13\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 10\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 9\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 15\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_2\n; %bb.5:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.6:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 23\n\tv_readlane_b32 s3, v36, 24\n\tv_readlane_b32 s4, v37, 1\n\tv_readlane_b32 s5, v37, 2\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, s2\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.7:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 23\n\tv_readlane_b32 s1, v37, 24\n\tv_readlane_b32 s2, v37, 31\n\tv_readlane_b32 s3, v36, 0\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v5, v4\n\tv_mov_b32_e32 v6, v0\n\ts_mov_b32 s3, 32\n\ts_lshr_b64 s[16:17], s[0:1], s3\n\ts_mov_b32 s2, s16\n\tv_lshrrev_b64 v[0:1], s3, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[5:6], s3, v[5:6]\n ; kill: def $vgpr5 killed $vgpr5 killed $vgpr5_vgpr6 killed $exec\n\ts_mov_b32 s3, s0\n\tv_mov_b32_e32 v0, v2\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v2, s3\n\tv_mov_b32_e32 v3, s2\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.8:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 3\n\tv_readlane_b32 s1, v37, 4\n\tv_readlane_b32 s2, v36, 15\n\tv_readlane_b32 s3, v36, 16\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 16\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_9: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 3\n\tv_readlane_b32 s3, v37, 4\n\tv_readlane_b32 s0, v37, 17\n\tv_readlane_b32 s1, v37, 16\n\tv_writelane_b32 v37, s1, 18\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 19\n\tv_writelane_b32 v37, s0, 20\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 21\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_11\n; %bb.10: ; in Loop: Header=BB8_9 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 19\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 20\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_11: ; in Loop: Header=BB8_9 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 18\n\tv_readlane_b32 s1, v37, 20\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 17\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 16\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 22\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_9\n; %bb.12:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.13:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 15\n\tv_readlane_b32 s3, v36, 16\n\tv_readlane_b32 s4, v37, 3\n\tv_readlane_b32 s5, v37, 4\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.14:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 15\n\tv_readlane_b32 s3, v37, 16\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_writelane_b32 v36, s0, 23\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\tscratch_store_b32 off, v6, s33 offset:172 ; 4-byte Folded Spill\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tscratch_load_b32 v17, off, s33 offset:172 ; 4-byte Folded Reload\n\tv_readlane_b32 s2, v37, 17\n\tv_readlane_b32 s3, v37, 18\n\tv_readlane_b32 s0, v36, 23\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v3, v[0:1]\n\ts_waitcnt vmcnt(1) lgkmcnt(1)\n\tv_lshrrev_b64 v[0:1], s0, v[4:5]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v4\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_args@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_args@rel32@hi+12\n\tv_mov_b32_e32 v2, 1\n\tv_mov_b32_e32 v4, v17\n\tv_mov_b32_e32 v5, v17\n\tv_mov_b32_e32 v6, v17\n\tv_mov_b32_e32 v7, v17\n\tv_mov_b32_e32 v8, v17\n\tv_mov_b32_e32 v9, v17\n\tv_mov_b32_e32 v10, v17\n\tv_mov_b32_e32 v11, v17\n\tv_mov_b32_e32 v12, v17\n\tv_mov_b32_e32 v13, v17\n\tv_mov_b32_e32 v14, v17\n\tv_mov_b32_e32 v15, v17\n\tv_mov_b32_e32 v16, v17\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.15:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 5\n\tv_readlane_b32 s1, v37, 6\n\tv_readlane_b32 s2, v36, 19\n\tv_readlane_b32 s3, v36, 20\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 24\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_16: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 5\n\tv_readlane_b32 s3, v37, 6\n\tv_readlane_b32 s0, v37, 25\n\tv_readlane_b32 s1, v37, 24\n\tv_writelane_b32 v37, s1, 26\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 27\n\tv_writelane_b32 v37, s0, 28\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 29\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_18\n; %bb.17: ; in Loop: Header=BB8_16 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 27\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 28\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_18: ; in Loop: Header=BB8_16 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 26\n\tv_readlane_b32 s1, v37, 28\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 25\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 24\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 30\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_16\n; %bb.19:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 30\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.20:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 19\n\tv_readlane_b32 s3, v36, 20\n\tv_readlane_b32 s4, v37, 5\n\tv_readlane_b32 s5, v37, 6\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.21:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 19\n\tv_readlane_b32 s3, v37, 20\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.22:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 7\n\tv_readlane_b32 s1, v37, 8\n\tv_readlane_b32 s2, v36, 13\n\tv_readlane_b32 s3, v36, 14\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_23: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v36, 7\n\tv_readlane_b32 s3, v36, 8\n ; implicit-def: $vgpr37 : SGPR spill to VGPR lane\n\tv_readlane_b32 s0, v37, 0\n\tv_readlane_b32 s1, v36, 31\n\tv_writelane_b32 v37, s1, 1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 2\n\tv_writelane_b32 v37, s0, 3\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 4\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_25\n; %bb.24: ; in Loop: Header=BB8_23 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 2\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 3\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_25: ; in Loop: Header=BB8_23 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s1, v37, 3\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 0\n\ts_mov_b32 s1, s0\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v36, s1, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 5\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_23\n; %bb.26:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 5\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.27:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 13\n\tv_readlane_b32 s3, v36, 14\n\tv_readlane_b32 s4, v37, 7\n\tv_readlane_b32 s5, v37, 8\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.28:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 13\n\tv_readlane_b32 s3, v37, 14\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 1\n\ts_swappc_b64 s[30:31], s[0:1]\n\ts_cbranch_execnz .LBB8_30\n; %bb.29:\n\tv_readlane_b32 s30, v35, 0\n\tv_readlane_b32 s31, v35, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v35, off, s33 offset:176 ; 4-byte Folded Reload\n\tscratch_load_b32 v36, off, s33 offset:180 ; 4-byte Folded Reload\n\tscratch_load_b32 v37, off, s33 offset:184 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xffffff40\n\ts_mov_b32 s33, s27\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.LBB8_30:\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB8_31: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB8_31\n.Lfunc_end8:\n\t.size\t__assert_fail, .Lfunc_end8-__assert_fail\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 6148\n; NumSgprs: 36\n; NumVgprs: 38\n; ScratchSize: 1312\n; MemoryBound: 0\n\t.text\n\t.hidden\t__assertfail ; -- Begin function __assertfail\n\t.weak\t__assertfail\n\t.p2align\t2\n\t.type\t__assertfail,@function\n__assertfail: ; @__assertfail\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_cbranch_execnz .LBB9_2\n; %bb.1:\n\ts_setpc_b64 s[30:31]\n.LBB9_2:\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB9_3: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB9_3\n.Lfunc_end9:\n\t.size\t__assertfail, .Lfunc_end9-__assertfail\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 64\n; NumSgprs: 32\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.protected\t_Z24globalMemCoalescedKernelv ; -- Begin function _Z24globalMemCoalescedKernelv\n\t.globl\t_Z24globalMemCoalescedKernelv\n\t.p2align\t8\n\t.type\t_Z24globalMemCoalescedKernelv,@function\n_Z24globalMemCoalescedKernelv: ; @_Z24globalMemCoalescedKernelv\n; %bb.0:\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z24globalMemCoalescedKernelv\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 256\n\t\t.amdhsa_user_sgpr_count 13\n\t\t.amdhsa_user_sgpr_dispatch_ptr 1\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 1\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 1\n\t\t.amdhsa_system_sgpr_workgroup_id_z 1\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 2\n\t\t.amdhsa_next_free_vgpr 1\n\t\t.amdhsa_next_free_sgpr 1\n\t\t.amdhsa_reserve_vcc 0\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end10:\n\t.size\t_Z24globalMemCoalescedKernelv, .Lfunc_end10-_Z24globalMemCoalescedKernelv\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 4\n; NumSgprs: 0\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 0\n; VGPRBlocks: 0\n; NumSGPRsForWavesPerEU: 1\n; NumVGPRsForWavesPerEU: 1\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 13\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2\n\t.text\n\t.protected\t_Z21globalMemStrideKernelv ; -- Begin function _Z21globalMemStrideKernelv\n\t.globl\t_Z21globalMemStrideKernelv\n\t.p2align\t8\n\t.type\t_Z21globalMemStrideKernelv,@function\n_Z21globalMemStrideKernelv: ; @_Z21globalMemStrideKernelv\n; %bb.0:\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z21globalMemStrideKernelv\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 256\n\t\t.amdhsa_user_sgpr_count 13\n\t\t.amdhsa_user_sgpr_dispatch_ptr 1\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 1\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 1\n\t\t.amdhsa_system_sgpr_workgroup_id_z 1\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 2\n\t\t.amdhsa_next_free_vgpr 1\n\t\t.amdhsa_next_free_sgpr 1\n\t\t.amdhsa_reserve_vcc 0\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end11:\n\t.size\t_Z21globalMemStrideKernelv, .Lfunc_end11-_Z21globalMemStrideKernelv\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 4\n; NumSgprs: 0\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 0\n; VGPRBlocks: 0\n; NumSGPRsForWavesPerEU: 1\n; NumVGPRsForWavesPerEU: 1\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 13\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2\n\t.text\n\t.protected\t_Z21globalMemOffsetKernelv ; -- Begin function _Z21globalMemOffsetKernelv\n\t.globl\t_Z21globalMemOffsetKernelv\n\t.p2align\t8\n\t.type\t_Z21globalMemOffsetKernelv,@function\n_Z21globalMemOffsetKernelv: ; @_Z21globalMemOffsetKernelv\n; %bb.0:\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z21globalMemOffsetKernelv\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 256\n\t\t.amdhsa_user_sgpr_count 13\n\t\t.amdhsa_user_sgpr_dispatch_ptr 1\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 1\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 1\n\t\t.amdhsa_system_sgpr_workgroup_id_z 1\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 2\n\t\t.amdhsa_next_free_vgpr 1\n\t\t.amdhsa_next_free_sgpr 1\n\t\t.amdhsa_reserve_vcc 0\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end12:\n\t.size\t_Z21globalMemOffsetKernelv, .Lfunc_end12-_Z21globalMemOffsetKernelv\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 4\n; NumSgprs: 0\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 0\n; VGPRBlocks: 0\n; NumSGPRsForWavesPerEU: 1\n; NumVGPRsForWavesPerEU: 1\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 13\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__const.__assert_fail.fmt,@object ; @__const.__assert_fail.fmt\n\t.section\t.rodata.str1.16,\"aMS\",@progbits,1\n\t.p2align\t4, 0x0\n__const.__assert_fail.fmt:\n\t.asciz\t\"%s:%u: %s: Device-side assertion `%s' failed.\\n\"\n\t.size\t__const.__assert_fail.fmt, 47\n\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.hidden\t__oclc_ABI_version ; @__oclc_ABI_version\n\t.type\t__oclc_ABI_version,@object\n\t.section\t.rodata,\"a\",@progbits\n\t.weak\t__oclc_ABI_version\n\t.p2align\t2, 0x0\n__oclc_ABI_version:\n\t.long\t500 ; 0x1f4\n\t.size\t__oclc_ABI_version, 4\n\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .offset: 0\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 4\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 8\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 12\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 14\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 16\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 18\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 20\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 22\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 40\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 48\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 56\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 64\n .size: 2\n .value_kind: hidden_grid_dims\n - .offset: 80\n .size: 8\n .value_kind: hidden_hostcall_buffer\n - .offset: 88\n .size: 8\n .value_kind: hidden_multigrid_sync_arg\n - .offset: 96\n .size: 8\n .value_kind: hidden_heap_v1\n - .offset: 104\n .size: 8\n .value_kind: hidden_default_queue\n - .offset: 200\n .size: 8\n .value_kind: hidden_queue_ptr\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 256\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z24globalMemCoalescedKernelv\n .private_segment_fixed_size: 0\n .sgpr_count: 0\n .sgpr_spill_count: 0\n .symbol: _Z24globalMemCoalescedKernelv.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 0\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\n - .args:\n - .offset: 0\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 4\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 8\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 12\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 14\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 16\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 18\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 20\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 22\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 40\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 48\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 56\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 64\n .size: 2\n .value_kind: hidden_grid_dims\n - .offset: 80\n .size: 8\n .value_kind: hidden_hostcall_buffer\n - .offset: 88\n .size: 8\n .value_kind: hidden_multigrid_sync_arg\n - .offset: 96\n .size: 8\n .value_kind: hidden_heap_v1\n - .offset: 104\n .size: 8\n .value_kind: hidden_default_queue\n - .offset: 200\n .size: 8\n .value_kind: hidden_queue_ptr\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 256\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z21globalMemStrideKernelv\n .private_segment_fixed_size: 0\n .sgpr_count: 0\n .sgpr_spill_count: 0\n .symbol: _Z21globalMemStrideKernelv.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 0\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\n - .args:\n - .offset: 0\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 4\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 8\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 12\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 14\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 16\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 18\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 20\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 22\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 40\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 48\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 56\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 64\n .size: 2\n .value_kind: hidden_grid_dims\n - .offset: 80\n .size: 8\n .value_kind: hidden_hostcall_buffer\n - .offset: 88\n .size: 8\n .value_kind: hidden_multigrid_sync_arg\n - .offset: 96\n .size: 8\n .value_kind: hidden_heap_v1\n - .offset: 104\n .size: 8\n .value_kind: hidden_default_queue\n - .offset: 200\n .size: 8\n .value_kind: hidden_queue_ptr\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 256\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z21globalMemOffsetKernelv\n .private_segment_fixed_size: 0\n .sgpr_count: 0\n .sgpr_spill_count: 0\n .symbol: _Z21globalMemOffsetKernelv.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 0\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162596,"cells":{"id":{"kind":"string","value":"d6741a0805ea1a6b43e4af8b63f069332adbe01c_O1"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z13update_labelsiPbS_PiS0_S0_ --------------------------\n .section .text._Z13update_labelsiPbS_PiS0_S0_,\"ax\",@progbits\n .sectionflags @\"SHF_BARRIERS=1\"\n .sectioninfo @\"SHI_REGISTERS=18\"\n .align 128\n\n\n\n\n .global _Z13update_labelsiPbS_PiS0_S0_\n .type _Z13update_labelsiPbS_PiS0_S0_,@function\n .size _Z13update_labelsiPbS_PiS0_S0_,(.L_x_8 - _Z13update_labelsiPbS_PiS0_S0_)\n .other _Z13update_labelsiPbS_PiS0_S0_,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z13update_labelsiPbS_PiS0_S0_:\n.text._Z13update_labelsiPbS_PiS0_S0_:\n /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;\n /*0010*/ S2R R0, SR_CTAID.X ;\n /*0020*/ ULDC.64 UR6, c[0x0][0x118] ;\n /*0030*/ S2R R3, SR_TID.X ;\n /*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ;\n /*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ;\n /*0060*/ @P0 EXIT ;\n /*0070*/ SHF.R.S32.HI R15, RZ, 0x1f, R0 ;\n /*0080*/ IADD3 R4, P0, R0, c[0x0][0x168], RZ ;\n /*0090*/ IADD3.X R5, R15, c[0x0][0x16c], RZ, P0, !PT ;\n /*00a0*/ LDG.E.U8 R2, [R4.64] ;\n /*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x5f5e100 ;\n /*00c0*/ BSSY B0, `(.L_x_0) ;\n /*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;\n /*00e0*/ STS [RZ], R6 ;\n /*00f0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ;\n /*0100*/ IMAD.WIDE R2, R0, R3, c[0x0][0x188] ;\n /*0110*/ @P0 BRA `(.L_x_1) ;\n /*0120*/ LDG.E R6, [R2.64] ;\n /*0130*/ VOTEU.ANY UR4, UPT, PT ;\n /*0140*/ UFLO.U32 UR4, UR4 ;\n /*0150*/ S2R R7, SR_LANEID ;\n /*0160*/ ISETP.EQ.U32.AND P0, PT, R7, UR4, PT ;\n /*0170*/ REDUX.MIN.S32 UR5, R6 ;\n /*0180*/ IMAD.U32 R7, RZ, RZ, UR5 ;\n /*0190*/ @P0 ATOMS.MIN.S32 RZ, [RZ], R7 ;\n.L_x_1:\n /*01a0*/ BSYNC B0 ;\n.L_x_0:\n /*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ;\n /*01c0*/ IADD3 R10, P0, R0, c[0x0][0x170], RZ ;\n /*01d0*/ IADD3.X R11, R15, c[0x0][0x174], RZ, P0, !PT ;\n /*01e0*/ LDG.E.U8 R10, [R10.64] ;\n /*01f0*/ LDS R12, [RZ] ;\n /*0200*/ ISETP.NE.AND P0, PT, R10, RZ, PT ;\n /*0210*/ @P0 LEA R6, P1, R0, c[0x0][0x178], 0x2 ;\n /*0220*/ @P0 LEA.HI.X R7, R0, c[0x0][0x17c], R15, 0x2, P1 ;\n /*0230*/ @P0 LDG.E R9, [R6.64] ;\n /*0240*/ @P0 IMAD.IADD R13, R9, 0x1, -R12 ;\n /*0250*/ @P0 STG.E [R6.64], R13 ;\n /*0260*/ LDG.E.U8 R4, [R4.64] ;\n /*0270*/ ISETP.NE.AND P0, PT, R4, RZ, PT ;\n /*0280*/ @P0 LEA R8, P1, R0, c[0x0][0x180], 0x2 ;\n /*0290*/ @P0 LEA.HI.X R9, R0, c[0x0][0x184], R15, 0x2, P1 ;\n /*02a0*/ @P0 LDG.E R11, [R8.64] ;\n /*02b0*/ @P0 IMAD.IADD R11, R12, 0x1, R11 ;\n /*02c0*/ @P0 STG.E [R8.64], R11 ;\n /*02d0*/ @P0 EXIT ;\n /*02e0*/ LDG.E R5, [R2.64] ;\n /*02f0*/ IMAD.IADD R5, R5, 0x1, -R12 ;\n /*0300*/ STG.E [R2.64], R5 ;\n /*0310*/ EXIT ;\n.L_x_2:\n /*0320*/ BRA `(.L_x_2);\n /*0330*/ NOP;\n /*0340*/ NOP;\n /*0350*/ NOP;\n /*0360*/ NOP;\n /*0370*/ NOP;\n /*0380*/ NOP;\n /*0390*/ NOP;\n /*03a0*/ NOP;\n /*03b0*/ NOP;\n /*03c0*/ NOP;\n /*03d0*/ NOP;\n /*03e0*/ NOP;\n /*03f0*/ NOP;\n.L_x_8:\n\n\n//--------------------- .text._Z11add_to_treeiiiPiS_S_S_S_ --------------------------\n .section .text._Z11add_to_treeiiiPiS_S_S_S_,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=16\"\n .align 128\n\n\n\n\n .global _Z11add_to_treeiiiPiS_S_S_S_\n .type _Z11add_to_treeiiiPiS_S_S_S_,@function\n .size _Z11add_to_treeiiiPiS_S_S_S_,(.L_x_9 - _Z11add_to_treeiiiPiS_S_S_S_)\n .other _Z11add_to_treeiiiPiS_S_S_S_,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z11add_to_treeiiiPiS_S_S_S_:\n.text._Z11add_to_treeiiiPiS_S_S_S_:\n /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;\n /*0010*/ S2R R0, SR_CTAID.X ;\n /*0020*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*0030*/ S2R R3, SR_TID.X ;\n /*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ;\n /*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ;\n /*0060*/ @P0 EXIT ;\n /*0070*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ;\n /*0080*/ MOV R9, 0x4 ;\n /*0090*/ IMAD R6, R2, c[0x0][0x168], R0 ;\n /*00a0*/ IMAD.WIDE R2, R9, R2, c[0x0][0x170] ;\n /*00b0*/ IMAD.WIDE R6, R6, R9.reuse, c[0x0][0x180] ;\n /*00c0*/ LDG.E R3, [R2.64] ;\n /*00d0*/ IMAD.WIDE R4, R0.reuse, R9.reuse, c[0x0][0x178] ;\n /*00e0*/ LDG.E R6, [R6.64] ;\n /*00f0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x188] ;\n /*0100*/ LDG.E R4, [R4.64] ;\n /*0110*/ LDG.E R10, [R8.64] ;\n /*0120*/ SHF.R.S32.HI R13, RZ, 0x1f, R0 ;\n /*0130*/ IADD3 R11, -R6, R4, R3 ;\n /*0140*/ ISETP.GE.AND P0, PT, R11, R10, PT ;\n /*0150*/ @P0 EXIT ;\n /*0160*/ LEA R2, P0, R0.reuse, c[0x0][0x190], 0x2 ;\n /*0170*/ STG.E [R8.64], R11 ;\n /*0180*/ MOV R5, c[0x0][0x160] ;\n /*0190*/ LEA.HI.X R3, R0, c[0x0][0x194], R13, 0x2, P0 ;\n /*01a0*/ STG.E [R2.64], R5 ;\n /*01b0*/ EXIT ;\n.L_x_3:\n /*01c0*/ BRA `(.L_x_3);\n /*01d0*/ NOP;\n /*01e0*/ NOP;\n /*01f0*/ NOP;\n /*0200*/ NOP;\n /*0210*/ NOP;\n /*0220*/ NOP;\n /*0230*/ NOP;\n /*0240*/ NOP;\n /*0250*/ NOP;\n /*0260*/ NOP;\n /*0270*/ NOP;\n.L_x_9:\n\n\n//--------------------- .text._Z11init_labelsiPiS_S_ --------------------------\n .section .text._Z11init_labelsiPiS_S_,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=18\"\n .align 128\n\n\n\n\n .global _Z11init_labelsiPiS_S_\n .type _Z11init_labelsiPiS_S_,@function\n .size _Z11init_labelsiPiS_S_,(.L_x_10 - _Z11init_labelsiPiS_S_)\n .other _Z11init_labelsiPiS_S_,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z11init_labelsiPiS_S_:\n.text._Z11init_labelsiPiS_S_:\n /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;\n /*0010*/ S2R R0, SR_CTAID.X ;\n /*0020*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*0030*/ S2R R3, SR_TID.X ;\n /*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ;\n /*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ;\n /*0060*/ @P0 EXIT ;\n /*0070*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ;\n /*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ;\n /*0090*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ;\n /*00a0*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ;\n /*00b0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ;\n /*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ;\n /*00d0*/ STG.E [R2.64], RZ ;\n /*00e0*/ STG.E [R4.64], RZ ;\n /*00f0*/ @!P0 EXIT ;\n /*0100*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ;\n /*0110*/ IADD3 R4, R6.reuse, -0x1, RZ ;\n /*0120*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ;\n /*0130*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ;\n /*0140*/ @!P0 BRA `(.L_x_4) ;\n /*0150*/ LDG.E R9, [R2.64] ;\n /*0160*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ;\n /*0170*/ IMAD R4, R0, c[0x0][0x160], RZ ;\n /*0180*/ IMAD.WIDE R4, R4, R5, c[0x0][0x178] ;\n /*0190*/ IADD3 R8, -R6, c[0x0][0x160], RZ ;\n /*01a0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ;\n /*01b0*/ MOV R11, R5 ;\n /*01c0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ;\n.L_x_5:\n /*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ;\n /*01e0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ;\n /*01f0*/ LDG.E R10, [R4.64] ;\n /*0200*/ IMNMX R11, R10, R9, !PT ;\n /*0210*/ STG.E [R2.64], R11 ;\n /*0220*/ LDG.E R10, [R4.64+0x4] ;\n /*0230*/ IMNMX R13, R11, R10, !PT ;\n /*0240*/ STG.E [R2.64], R13 ;\n /*0250*/ LDG.E R10, [R4.64+0x8] ;\n /*0260*/ IMNMX R15, R13, R10, !PT ;\n /*0270*/ STG.E [R2.64], R15 ;\n /*0280*/ LDG.E R10, [R4.64+0xc] ;\n /*0290*/ IADD3 R8, R8, -0x4, RZ ;\n /*02a0*/ IADD3 R7, R7, 0x4, RZ ;\n /*02b0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ;\n /*02c0*/ IMNMX R9, R15, R10, !PT ;\n /*02d0*/ IADD3 R10, P1, R4, 0x10, RZ ;\n /*02e0*/ STG.E [R2.64], R9 ;\n /*02f0*/ IADD3.X R11, RZ, R5, RZ, P1, !PT ;\n /*0300*/ @P0 BRA `(.L_x_5) ;\n.L_x_4:\n /*0310*/ ISETP.NE.AND P0, PT, R6, RZ, PT ;\n /*0320*/ @!P0 EXIT ;\n /*0330*/ IMAD R4, R0, c[0x0][0x160], R7 ;\n /*0340*/ LDG.E R7, [R2.64] ;\n /*0350*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ;\n /*0360*/ IMAD.WIDE R4, R4, R5, c[0x0][0x178] ;\n.L_x_6:\n /*0370*/ LDG.E R0, [R4.64] ;\n /*0380*/ IADD3 R6, R6, -0x1, RZ ;\n /*0390*/ ISETP.NE.AND P0, PT, R6, RZ, PT ;\n /*03a0*/ IADD3 R4, P1, R4, 0x4, RZ ;\n /*03b0*/ IMAD.X R5, RZ, RZ, R5, P1 ;\n /*03c0*/ IMNMX R7, R0, R7, !PT ;\n /*03d0*/ STG.E [R2.64], R7 ;\n /*03e0*/ @P0 BRA `(.L_x_6) ;\n /*03f0*/ EXIT ;\n.L_x_7:\n /*0400*/ BRA `(.L_x_7);\n /*0410*/ NOP;\n /*0420*/ NOP;\n /*0430*/ NOP;\n /*0440*/ NOP;\n /*0450*/ NOP;\n /*0460*/ NOP;\n /*0470*/ NOP;\n /*0480*/ NOP;\n /*0490*/ NOP;\n /*04a0*/ NOP;\n /*04b0*/ NOP;\n /*04c0*/ NOP;\n /*04d0*/ NOP;\n /*04e0*/ NOP;\n /*04f0*/ NOP;\n.L_x_10:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.protected\t_Z11init_labelsiPiS_S_ ; -- Begin function _Z11init_labelsiPiS_S_\n\t.globl\t_Z11init_labelsiPiS_S_\n\t.p2align\t8\n\t.type\t_Z11init_labelsiPiS_S_,@function\n_Z11init_labelsiPiS_S_: ; @_Z11init_labelsiPiS_S_\n; %bb.0:\n\ts_clause 0x1\n\ts_load_b32 s3, s[0:1], 0x2c\n\ts_load_b32 s2, s[0:1], 0x0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s3, s3, 0xffff\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]\n\ts_mov_b32 s3, exec_lo\n\tv_cmpx_gt_i32_e64 s2, v2\n\ts_cbranch_execz .LBB0_4\n; %bb.1:\n\ts_load_b128 s[4:7], s[0:1], 0x8\n\tv_ashrrev_i32_e32 v3, 31, v2\n\tv_mov_b32_e32 v5, 0\n\ts_cmp_lt_i32 s2, 1\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[3:4], 2, v[2:3]\n\ts_waitcnt lgkmcnt(0)\n\tv_add_co_u32 v0, vcc_lo, s4, v3\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s5, v4, vcc_lo\n\tv_add_co_u32 v3, vcc_lo, s6, v3\n\tv_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo\n\tglobal_store_b32 v[0:1], v5, off\n\tglobal_store_b32 v[3:4], v5, off\n\ts_cbranch_scc1 .LBB0_4\n; %bb.2:\n\tglobal_load_b32 v4, v[0:1], off\n\ts_load_b64 s[0:1], s[0:1], 0x18\n\tv_mul_lo_u32 v2, v2, s2\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_ashrrev_i32_e32 v3, 31, v2\n\tv_lshlrev_b64 v[2:3], 2, v[2:3]\n\ts_waitcnt lgkmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v2, vcc_lo, s0, v2\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo\n.LBB0_3: ; =>This Inner Loop Header: Depth=1\n\tglobal_load_b32 v5, v[2:3], off\n\tv_add_co_u32 v2, vcc_lo, v2, 4\n\tv_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo\n\ts_add_i32 s2, s2, -1\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_cmp_lg_u32 s2, 0\n\ts_waitcnt vmcnt(0)\n\tv_max_i32_e32 v4, v4, v5\n\tglobal_store_b32 v[0:1], v4, off\n\ts_cbranch_scc1 .LBB0_3\n.LBB0_4:\n\ts_nop 0\n\ts_sendmsg sendmsg(MSG_DEALLOC_VGPRS)\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z11init_labelsiPiS_S_\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 288\n\t\t.amdhsa_user_sgpr_count 15\n\t\t.amdhsa_user_sgpr_dispatch_ptr 0\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 0\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 0\n\t\t.amdhsa_next_free_vgpr 6\n\t\t.amdhsa_next_free_sgpr 16\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end0:\n\t.size\t_Z11init_labelsiPiS_S_, .Lfunc_end0-_Z11init_labelsiPiS_S_\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 268\n; NumSgprs: 18\n; NumVgprs: 6\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 2\n; VGPRBlocks: 0\n; NumSGPRsForWavesPerEU: 18\n; NumVGPRsForWavesPerEU: 6\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 15\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0\n\t.text\n\t.protected\t_Z11add_to_treeiiiPiS_S_S_S_ ; -- Begin function _Z11add_to_treeiiiPiS_S_S_S_\n\t.globl\t_Z11add_to_treeiiiPiS_S_S_S_\n\t.p2align\t8\n\t.type\t_Z11add_to_treeiiiPiS_S_S_S_,@function\n_Z11add_to_treeiiiPiS_S_S_S_: ; @_Z11add_to_treeiiiPiS_S_S_S_\n; %bb.0:\n\ts_clause 0x1\n\ts_load_b32 s2, s[0:1], 0x44\n\ts_load_b32 s3, s[0:1], 0x8\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s2, s2, 0xffff\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]\n\ts_mov_b32 s2, exec_lo\n\tv_cmpx_gt_i32_e64 s3, v1\n\ts_cbranch_execz .LBB1_3\n; %bb.1:\n\ts_clause 0x1\n\ts_load_b32 s2, s[0:1], 0x0\n\ts_load_b256 s[4:11], s[0:1], 0x10\n\tv_ashrrev_i32_e32 v2, 31, v1\n\ts_waitcnt lgkmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)\n\tv_mad_u64_u32 v[3:4], null, s3, s2, v[1:2]\n\tv_lshlrev_b64 v[0:1], 2, v[1:2]\n\ts_ashr_i32 s3, s2, 31\n\tv_ashrrev_i32_e32 v4, 31, v3\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)\n\tv_lshlrev_b64 v[2:3], 2, v[3:4]\n\tv_add_co_u32 v4, vcc_lo, s6, v0\n\ts_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo\n\ts_lshl_b64 s[6:7], s[2:3], 2\n\tv_add_co_u32 v2, vcc_lo, s8, v2\n\ts_delay_alu instid0(VALU_DEP_4)\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo\n\ts_add_u32 s4, s4, s6\n\ts_addc_u32 s5, s5, s7\n\tglobal_load_b32 v4, v[4:5], off\n\tglobal_load_b32 v5, v[2:3], off\n\tv_add_co_u32 v2, vcc_lo, s10, v0\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo\n\ts_load_b32 s3, s[4:5], 0x0\n\tglobal_load_b32 v6, v[2:3], off\n\ts_waitcnt vmcnt(2) lgkmcnt(0)\n\tv_add_nc_u32_e32 v4, s3, v4\n\ts_waitcnt vmcnt(1)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_sub_nc_u32_e32 v4, v4, v5\n\ts_waitcnt vmcnt(0)\n\tv_cmp_lt_i32_e32 vcc_lo, v4, v6\n\ts_and_b32 exec_lo, exec_lo, vcc_lo\n\ts_cbranch_execz .LBB1_3\n; %bb.2:\n\ts_load_b64 s[0:1], s[0:1], 0x30\n\tv_mov_b32_e32 v5, s2\n\ts_waitcnt lgkmcnt(0)\n\tv_add_co_u32 v0, vcc_lo, s0, v0\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo\n\tglobal_store_b32 v[2:3], v4, off\n\tglobal_store_b32 v[0:1], v5, off\n.LBB1_3:\n\ts_nop 0\n\ts_sendmsg sendmsg(MSG_DEALLOC_VGPRS)\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z11add_to_treeiiiPiS_S_S_S_\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 312\n\t\t.amdhsa_user_sgpr_count 15\n\t\t.amdhsa_user_sgpr_dispatch_ptr 0\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 0\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 0\n\t\t.amdhsa_next_free_vgpr 7\n\t\t.amdhsa_next_free_sgpr 16\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end1:\n\t.size\t_Z11add_to_treeiiiPiS_S_S_S_, .Lfunc_end1-_Z11add_to_treeiiiPiS_S_S_S_\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 308\n; NumSgprs: 18\n; NumVgprs: 7\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 2\n; VGPRBlocks: 0\n; NumSGPRsForWavesPerEU: 18\n; NumVGPRsForWavesPerEU: 7\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 15\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0\n\t.text\n\t.protected\t_Z13update_labelsiPbS_PiS0_S0_ ; -- Begin function _Z13update_labelsiPbS_PiS0_S0_\n\t.globl\t_Z13update_labelsiPbS_PiS0_S0_\n\t.p2align\t8\n\t.type\t_Z13update_labelsiPbS_PiS0_S0_,@function\n_Z13update_labelsiPbS_PiS0_S0_: ; @_Z13update_labelsiPbS_PiS0_S0_\n; %bb.0:\n\ts_clause 0x1\n\ts_load_b32 s2, s[0:1], 0x3c\n\ts_load_b32 s3, s[0:1], 0x0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s2, s2, 0xffff\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]\n\ts_mov_b32 s2, exec_lo\n\tv_cmpx_gt_i32_e64 s3, v4\n\ts_cbranch_execz .LBB2_12\n; %bb.1:\n\ts_load_b256 s[4:11], s[0:1], 0x8\n\tv_ashrrev_i32_e32 v5, 31, v4\n\ts_load_b64 s[0:1], s[0:1], 0x28\n\tv_dual_mov_b32 v7, 0x5f5e100 :: v_dual_mov_b32 v8, 0\n\ts_mov_b32 s2, exec_lo\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_lshlrev_b64 v[0:1], 2, v[4:5]\n\tds_store_b32 v8, v7\n\ts_waitcnt lgkmcnt(0)\n\tv_add_co_u32 v2, vcc_lo, s4, v4\n\tv_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo\n\tglobal_load_u8 v6, v[2:3], off\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_eq_u16_e32 0, v6\n\ts_cbranch_execz .LBB2_6\n; %bb.2:\n\tv_add_co_u32 v6, vcc_lo, s0, v0\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo\n\ts_mov_b32 s4, exec_lo\n\ts_brev_b32 s3, -2\n\tglobal_load_b32 v6, v[6:7], off\n.LBB2_3: ; =>This Inner Loop Header: Depth=1\n\ts_ctz_i32_b32 s5, s4\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s12, v6, s5\n\ts_lshl_b32 s5, 1, s5\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\ts_and_not1_b32 s4, s4, s5\n\ts_min_i32 s3, s3, s12\n\ts_cmp_lg_u32 s4, 0\n\ts_cbranch_scc1 .LBB2_3\n; %bb.4:\n\tv_mbcnt_lo_u32_b32 v6, exec_lo, 0\n\ts_mov_b32 s4, exec_lo\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_eq_u32_e32 0, v6\n\ts_xor_b32 s4, exec_lo, s4\n\ts_cbranch_execz .LBB2_6\n; %bb.5:\n\tv_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, s3\n\tds_min_i32 v6, v7\n.LBB2_6:\n\ts_or_b32 exec_lo, exec_lo, s2\n\tv_add_co_u32 v4, vcc_lo, s6, v4\n\tv_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo\n\ts_waitcnt lgkmcnt(0)\n\ts_barrier\n\tbuffer_gl0_inv\n\tglobal_load_u8 v5, v[4:5], off\n\tv_mov_b32_e32 v4, 0\n\ts_mov_b32 s2, exec_lo\n\tds_load_b32 v4, v4\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u16_e32 0, v5\n\ts_cbranch_execz .LBB2_8\n; %bb.7:\n\tv_add_co_u32 v5, vcc_lo, s8, v0\n\tv_add_co_ci_u32_e32 v6, vcc_lo, s9, v1, vcc_lo\n\tglobal_load_b32 v7, v[5:6], off\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e32 v7, v7, v4\n\tglobal_store_b32 v[5:6], v7, off\n.LBB2_8:\n\ts_or_b32 exec_lo, exec_lo, s2\n\tglobal_load_u8 v2, v[2:3], off\n\ts_mov_b32 s2, exec_lo\n\ts_waitcnt vmcnt(0)\n\tv_cmpx_ne_u16_e32 0, v2\n\ts_xor_b32 s2, exec_lo, s2\n\ts_cbranch_execz .LBB2_10\n; %bb.9:\n\tv_add_co_u32 v0, vcc_lo, s10, v0\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo\n\tglobal_load_b32 v2, v[0:1], off\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e32 v2, v2, v4\n ; implicit-def: $vgpr4\n\tglobal_store_b32 v[0:1], v2, off\n ; implicit-def: $vgpr0_vgpr1\n.LBB2_10:\n\ts_and_not1_saveexec_b32 s2, s2\n\ts_cbranch_execz .LBB2_12\n; %bb.11:\n\tv_add_co_u32 v0, vcc_lo, s0, v0\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo\n\tglobal_load_b32 v2, v[0:1], off\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e32 v2, v2, v4\n\tglobal_store_b32 v[0:1], v2, off\n.LBB2_12:\n\ts_nop 0\n\ts_sendmsg sendmsg(MSG_DEALLOC_VGPRS)\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z13update_labelsiPbS_PiS0_S0_\n\t\t.amdhsa_group_segment_fixed_size 4\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 304\n\t\t.amdhsa_user_sgpr_count 15\n\t\t.amdhsa_user_sgpr_dispatch_ptr 0\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 0\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 0\n\t\t.amdhsa_next_free_vgpr 9\n\t\t.amdhsa_next_free_sgpr 16\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end2:\n\t.size\t_Z13update_labelsiPbS_PiS0_S0_, .Lfunc_end2-_Z13update_labelsiPbS_PiS0_S0_\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 492\n; NumSgprs: 18\n; NumVgprs: 9\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 4 bytes/workgroup (compile time only)\n; SGPRBlocks: 2\n; VGPRBlocks: 1\n; NumSGPRsForWavesPerEU: 18\n; NumVGPRsForWavesPerEU: 9\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 15\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .offset: 0\n .size: 4\n .value_kind: by_value\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 16\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 24\n .size: 8\n .value_kind: global_buffer\n - .offset: 32\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 36\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 40\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 44\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 46\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 48\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 50\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 52\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 54\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 72\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 80\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 88\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 96\n .size: 2\n .value_kind: hidden_grid_dims\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 288\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z11init_labelsiPiS_S_\n .private_segment_fixed_size: 0\n .sgpr_count: 18\n .sgpr_spill_count: 0\n .symbol: _Z11init_labelsiPiS_S_.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 6\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\n - .args:\n - .offset: 0\n .size: 4\n .value_kind: by_value\n - .offset: 4\n .size: 4\n .value_kind: by_value\n - .offset: 8\n .size: 4\n .value_kind: by_value\n - .address_space: global\n .offset: 16\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 24\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 32\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 40\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 48\n .size: 8\n .value_kind: global_buffer\n - .offset: 56\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 60\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 64\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 68\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 70\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 72\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 74\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 76\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 78\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 96\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 104\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 112\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 120\n .size: 2\n .value_kind: hidden_grid_dims\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 312\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z11add_to_treeiiiPiS_S_S_S_\n .private_segment_fixed_size: 0\n .sgpr_count: 18\n .sgpr_spill_count: 0\n .symbol: _Z11add_to_treeiiiPiS_S_S_S_.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 7\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\n - .args:\n - .offset: 0\n .size: 4\n .value_kind: by_value\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 16\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 24\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 32\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 40\n .size: 8\n .value_kind: global_buffer\n - .offset: 48\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 52\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 56\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 60\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 62\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 64\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 66\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 68\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 70\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 88\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 96\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 104\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 112\n .size: 2\n .value_kind: hidden_grid_dims\n .group_segment_fixed_size: 4\n .kernarg_segment_align: 8\n .kernarg_segment_size: 304\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z13update_labelsiPbS_PiS0_S0_\n .private_segment_fixed_size: 0\n .sgpr_count: 18\n .sgpr_spill_count: 0\n .symbol: _Z13update_labelsiPbS_PiS0_S0_.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 9\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162597,"cells":{"id":{"kind":"string","value":"6371e4ddfad7246f2580aba7c1a34dec43f1605f_O1"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z9insertKeyP9BTreeNodeii --------------------------\n .section .text._Z9insertKeyP9BTreeNodeii,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=16\"\n .align 128\n\n\n\n\n .global _Z9insertKeyP9BTreeNodeii\n .type _Z9insertKeyP9BTreeNodeii,@function\n .size _Z9insertKeyP9BTreeNodeii,(.L_x_4 - _Z9insertKeyP9BTreeNodeii)\n .other _Z9insertKeyP9BTreeNodeii,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z9insertKeyP9BTreeNodeii:\n.text._Z9insertKeyP9BTreeNodeii:\n /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;\n /*0010*/ S2UR UR4, SR_CTAID.X ;\n /*0020*/ S2R R0, SR_TID.X ;\n /*0030*/ ULDC UR5, c[0x0][0x0] ;\n /*0040*/ UIMAD UR4, UR4, UR5, URZ ;\n /*0050*/ IMAD.MOV R0, RZ, RZ, -R0 ;\n /*0060*/ ISETP.NE.AND P0, PT, R0, UR4, PT ;\n /*0070*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*0080*/ @P0 EXIT ;\n /*0090*/ MOV R2, c[0x0][0x168] ;\n /*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x18 ;\n /*00b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;\n /*00c0*/ LDG.E R9, [R2.64+0x14] ;\n /*00d0*/ ISETP.GT.AND P0, PT, R9, 0x1, PT ;\n /*00e0*/ @P0 EXIT ;\n /*00f0*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ;\n /*0100*/ MOV R0, c[0x0][0x168] ;\n /*0110*/ SHF.R.S32.HI R0, RZ, 0x1f, R0 ;\n /*0120*/ @P0 BRA `(.L_x_0) ;\n /*0130*/ MOV R5, 0x18 ;\n /*0140*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ;\n /*0150*/ MOV R9, 0x1 ;\n /*0160*/ IMAD R7, R0, 0x18, RZ ;\n /*0170*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ;\n /*0180*/ IMAD.IADD R5, R5, 0x1, R7 ;\n.L_x_1:\n /*0190*/ IADD3 R11, R9, -0x1, RZ ;\n /*01a0*/ IMAD.WIDE R6, R11, 0x4, R4 ;\n /*01b0*/ LDG.E R13, [R6.64] ;\n /*01c0*/ ISETP.GT.AND P0, PT, R13, c[0x0][0x16c], PT ;\n /*01d0*/ @!P0 BRA `(.L_x_0) ;\n /*01e0*/ IMAD.WIDE R6, R9.reuse, 0x4, R4 ;\n /*01f0*/ ISETP.GT.AND P0, PT, R9, 0x1, PT ;\n /*0200*/ IMAD.MOV.U32 R9, RZ, RZ, R11 ;\n /*0210*/ STG.E [R6.64], R13 ;\n /*0220*/ @P0 BRA `(.L_x_1) ;\n.L_x_0:\n /*0230*/ MOV R4, c[0x0][0x168] ;\n /*0240*/ IMAD.MOV.U32 R5, RZ, RZ, 0x18 ;\n /*0250*/ IMAD R7, R0, 0x18, RZ ;\n /*0260*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ;\n /*0270*/ IADD3 R5, R5, R7, RZ ;\n /*0280*/ IMAD.WIDE R4, R9, 0x4, R4 ;\n /*0290*/ MOV R9, c[0x0][0x16c] ;\n /*02a0*/ STG.E [R4.64], R9 ;\n /*02b0*/ LDG.E R0, [R2.64+0x14] ;\n /*02c0*/ IADD3 R7, R0, 0x1, RZ ;\n /*02d0*/ STG.E [R2.64+0x14], R7 ;\n /*02e0*/ EXIT ;\n.L_x_2:\n /*02f0*/ BRA `(.L_x_2);\n /*0300*/ NOP;\n /*0310*/ NOP;\n /*0320*/ NOP;\n /*0330*/ NOP;\n /*0340*/ NOP;\n /*0350*/ NOP;\n /*0360*/ NOP;\n /*0370*/ NOP;\n.L_x_4:\n\n\n//--------------------- .text._Z15initializeNodesP9BTreeNode --------------------------\n .section .text._Z15initializeNodesP9BTreeNode,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=8\"\n .align 128\n\n\n\n\n .global _Z15initializeNodesP9BTreeNode\n .type _Z15initializeNodesP9BTreeNode,@function\n .size _Z15initializeNodesP9BTreeNode,(.L_x_5 - _Z15initializeNodesP9BTreeNode)\n .other _Z15initializeNodesP9BTreeNode,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z15initializeNodesP9BTreeNode:\n.text._Z15initializeNodesP9BTreeNode:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ S2R R2, SR_CTAID.X ;\n /*0020*/ ULDC.64 UR4, c[0x0][0x118] ;\n /*0030*/ S2R R3, SR_TID.X ;\n /*0040*/ IMAD R2, R2, c[0x0][0x0], R3 ;\n /*0050*/ ISETP.GT.AND P0, PT, R2, 0x3ff, PT ;\n /*0060*/ @P0 EXIT ;\n /*0070*/ MOV R3, 0x18 ;\n /*0080*/ MOV R5, 0xffffffff ;\n /*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;\n /*00a0*/ STG.E [R2.64+0x14], RZ ;\n /*00b0*/ STG.E [R2.64], RZ ;\n /*00c0*/ STG.E [R2.64+0x8], R5 ;\n /*00d0*/ STG.E [R2.64+0x4], RZ ;\n /*00e0*/ STG.E [R2.64+0xc], R5 ;\n /*00f0*/ STG.E [R2.64+0x10], R5 ;\n /*0100*/ EXIT ;\n.L_x_3:\n /*0110*/ BRA `(.L_x_3);\n /*0120*/ NOP;\n /*0130*/ NOP;\n /*0140*/ NOP;\n /*0150*/ NOP;\n /*0160*/ NOP;\n /*0170*/ NOP;\n /*0180*/ NOP;\n /*0190*/ NOP;\n /*01a0*/ NOP;\n /*01b0*/ NOP;\n /*01c0*/ NOP;\n /*01d0*/ NOP;\n /*01e0*/ NOP;\n /*01f0*/ NOP;\n.L_x_5:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.weak\t__cxa_pure_virtual ; -- Begin function __cxa_pure_virtual\n\t.p2align\t2\n\t.type\t__cxa_pure_virtual,@function\n__cxa_pure_virtual: ; @__cxa_pure_virtual\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB0_1: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB0_1\n.Lfunc_end0:\n\t.size\t__cxa_pure_virtual, .Lfunc_end0-__cxa_pure_virtual\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 56\n; NumSgprs: 1\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.weak\t__cxa_deleted_virtual ; -- Begin function __cxa_deleted_virtual\n\t.p2align\t2\n\t.type\t__cxa_deleted_virtual,@function\n__cxa_deleted_virtual: ; @__cxa_deleted_virtual\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB1_1: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB1_1\n.Lfunc_end1:\n\t.size\t__cxa_deleted_virtual, .Lfunc_end1-__cxa_deleted_virtual\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 56\n; NumSgprs: 1\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hsa_signal_add\n\t.type\t__ockl_hsa_signal_add,@function\n__ockl_hsa_signal_add: ; @__ockl_hsa_signal_add\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v6, s32 offset:48 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v4, s32 offset:36 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v3, s32 offset:32 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v2\n\tscratch_load_b32 v2, off, s32 offset:32 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v1, s32 offset:28 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v1, v0\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[3:4], s32 offset:20 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v3, v1\n\tscratch_store_b64 off, v[3:4], s32 offset:12 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v0, v1\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v1, v2\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v0, s1, v0, s1\n\tv_add_co_ci_u32_e64 v2, s0, v1, s0, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s32 offset:4 ; 8-byte Folded Spill\n; %bb.1:\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 3\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, 0\n ; implicit-def: $vgpr6 : SGPR spill to VGPR lane\n\tv_writelane_b32 v6, s1, 0\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 1\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_3\n; %bb.2:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 4\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s1, 2\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 3\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_17\n\ts_branch .LBB2_4\n.LBB2_3:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 1\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s2, v6, 0\n\tv_writelane_b32 v6, s2, 4\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s2, 5\n\tv_writelane_b32 v6, s1, 6\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 7\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_13\n\ts_branch .LBB2_6\n.LBB2_4:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 5\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, -1\n\tv_writelane_b32 v6, s0, 8\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 9\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_15\n\ts_branch .LBB2_18\n.LBB2_5:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 10\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_readlane_b32 s0, v6, 11\n\ts_and_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 0\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_3\n.LBB2_6:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 12\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_7\n\ts_branch .LBB2_14\n.LBB2_7:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 12\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s2, v6, 4\n\ts_mov_b32 s1, 0\n\tv_writelane_b32 v6, s2, 13\n\tv_writelane_b32 v6, s1, 14\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 15\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_9\n; %bb.8:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 4\n\tscratch_load_b32 v0, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_lt_i32_e64 s2, v0, s0\n\ts_mov_b32 s0, -1\n\ts_mov_b32 s0, exec_lo\n\ts_and_not1_b32 s1, s1, exec_lo\n\ts_and_b32 s2, s2, exec_lo\n\ts_or_b32 s1, s1, s2\n\tv_writelane_b32 v6, s1, 13\n\tv_writelane_b32 v6, s0, 14\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n.LBB2_9:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s3, v6, 15\n\ts_or_b32 exec_lo, exec_lo, s3\n\tv_readlane_b32 s1, v6, 4\n\tv_readlane_b32 s2, v6, 13\n\tv_readlane_b32 s0, v6, 14\n\ts_and_b32 s0, s0, exec_lo\n\ts_and_not1_b32 s1, s1, exec_lo\n\ts_and_b32 s2, s2, exec_lo\n\ts_or_b32 s1, s1, s2\n\tv_writelane_b32 v6, s1, 5\n\tv_writelane_b32 v6, s0, 6\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_13\n.LBB2_10:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 16\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 17\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n.LBB2_11:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 18\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v6, 17\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 19\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_19\n; %bb.12:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_branch .LBB2_19\n.LBB2_13:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v6, 7\n\ts_or_b32 exec_lo, exec_lo, s2\n\tv_readlane_b32 s0, v6, 5\n\tv_readlane_b32 s1, v6, 6\n\tv_writelane_b32 v6, s1, 16\n\tv_writelane_b32 v6, s1, 17\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v6, s1, 18\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_11\n\ts_branch .LBB2_10\n.LBB2_14:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_branch .LBB2_7\n.LBB2_15:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v6, 9\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_readlane_b32 s0, v6, 8\n\ts_and_b32 s0, s0, exec_lo\n\tv_writelane_b32 v6, s0, 2\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_17\n.LBB2_16:\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_branch .LBB2_5\n.LBB2_17:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 3\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v6, 2\n\tv_writelane_b32 v6, s1, 11\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v6, s0, 10\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB2_5\n\ts_branch .LBB2_16\n.LBB2_18:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\tscratch_load_b64 v[0:1], off, s32 offset:4 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s32 offset:20 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_add_u64 v[0:1], v[2:3], off\n\ts_waitcnt_vscnt null, 0x0\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b32 s0, 0\n\ts_xor_b32 s0, exec_lo, -1\n\tv_writelane_b32 v6, s0, 8\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_branch .LBB2_15\n.LBB2_19:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 19\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:12 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[0:1], v[0:1], off offset:16\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:40 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_ne_u64_e64 s1, v[0:1], s[0:1]\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v6, s0, 20\n\ts_or_saveexec_b32 s5, -1\n\tscratch_store_b32 off, v6, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s5\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB2_21\n; %bb.20:\n\tscratch_load_b64 v[1:2], off, s32 offset:40 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s32 offset:12 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b32 v0, v[3:4], off offset:24\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v5, 0\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\tv_mov_b32_e32 v4, v5\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_store_b64 v[1:2], v[3:4], off\n\tv_readfirstlane_b32 s0, v0\n\ts_mov_b32 s1, 0xff\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n.LBB2_21:\n\ts_or_saveexec_b32 s5, -1\n\tscratch_load_b32 v6, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s5\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v6, 20\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v6, off, s32 offset:48 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end2:\n\t.size\t__ockl_hsa_signal_add, .Lfunc_end2-__ockl_hsa_signal_add\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 1952\n; NumSgprs: 33\n; NumVgprs: 7\n; ScratchSize: 56\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hostcall_internal\n\t.type\t__ockl_hostcall_internal,@function\n__ockl_hostcall_internal: ; @__ockl_hostcall_internal\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s18, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v24, s33 offset:308 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v25, s33 offset:312 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v26, s33 offset:316 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0x150\n\tv_writelane_b32 v24, s30, 0\n\tv_writelane_b32 v24, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:132 ; 4-byte Folded Spill\n ; implicit-def: $vgpr26 : SGPR spill to VGPR lane\n\tv_writelane_b32 v26, s6, 0\n\tv_writelane_b32 v26, s7, 1\n\tscratch_store_b32 off, v18, s33 offset:128 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v16\n\tscratch_load_b32 v16, off, s33 offset:128 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:124 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v14\n\tscratch_load_b32 v14, off, s33 offset:124 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:120 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v12\n\tscratch_load_b32 v12, off, s33 offset:120 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:116 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v10\n\tscratch_load_b32 v10, off, s33 offset:116 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:112 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v8\n\tscratch_load_b32 v8, off, s33 offset:112 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:108 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v6\n\tscratch_load_b32 v6, off, s33 offset:108 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:104 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v4\n\tscratch_load_b32 v4, off, s33 offset:104 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:100 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v18, v2\n\tscratch_load_b32 v2, off, s33 offset:100 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v18, s33 offset:96 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v1, s33 offset:92 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v1, v0\n\tscratch_load_b32 v0, off, s33 offset:92 ; 4-byte Folded Reload\n\tv_writelane_b32 v26, s15, 2\n\tv_writelane_b32 v26, s14, 3\n\tv_writelane_b32 v26, s13, 4\n\tv_writelane_b32 v26, s12, 5\n\tv_writelane_b32 v26, s10, 6\n\tv_writelane_b32 v26, s11, 7\n\tv_writelane_b32 v26, s8, 8\n\tv_writelane_b32 v26, s9, 9\n\tv_writelane_b32 v26, s4, 10\n\tv_writelane_b32 v26, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\ts_waitcnt vmcnt(8)\n\tv_mov_b32_e32 v18, v16\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr15 killed $vgpr15 def $vgpr15_vgpr16 killed $exec\n\ts_waitcnt vmcnt(7)\n\tv_mov_b32_e32 v16, v14\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec\n\ts_waitcnt vmcnt(6)\n\tv_mov_b32_e32 v14, v12\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\ts_waitcnt vmcnt(5)\n\tv_mov_b32_e32 v12, v10\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\ts_waitcnt vmcnt(4)\n\tv_mov_b32_e32 v10, v8\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\ts_waitcnt vmcnt(3)\n\tv_mov_b32_e32 v8, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v6, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[17:18], s33 offset:84 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[15:16], s33 offset:76 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[13:14], s33 offset:68 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[11:12], s33 offset:60 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[9:10], s33 offset:52 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[7:8], s33 offset:44 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[5:6], s33 offset:36 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[3:4], s33 offset:28 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s0, -1\n\tv_mbcnt_lo_u32_b32 v0, s0, s1\n\tv_mbcnt_hi_u32_b32 v0, s0, v0\n\t;;#ASMSTART\n\t;;#ASMEND\n\tv_mov_b32_e32 v3, v0\n\tscratch_store_b32 off, v3, s33 offset:24 ; 4-byte Folded Spill\n\tv_readfirstlane_b32 s0, v0\n\tscratch_store_b64 off, v[1:2], s33 offset:16 ; 8-byte Folded Spill\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, s1\n\tv_writelane_b32 v26, s0, 12\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v0, 0\n\tv_mov_b32_e32 v1, 0\n\tscratch_store_b64 off, v[0:1], s33 offset:8 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 13\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_6\n; %bb.1:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_mov_b64 s[2:3], 24\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:160 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b64 s[2:3], 40\n\tv_mov_b32_e32 v4, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v5, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v4, s1, v4, s1\n\tv_add_co_ci_u32_e64 v6, s0, v5, s0, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tscratch_store_b64 off, v[4:5], s33 offset:152 ; 8-byte Folded Spill\n\tglobal_load_b64 v[5:6], v[0:1], off\n\tglobal_load_b64 v[10:11], v[0:1], off offset:40\n\tv_mov_b32_e32 v8, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v11\n\tv_and_b32_e64 v4, v4, v8\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v7, v10\n\tv_and_b32_e64 v12, v7, v9\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_mov_b32_e32 v4, v12\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[10:11], s0, v4, s1, 0\n\tv_mov_b32_e32 v14, v11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec\n\tv_mov_b32_e32 v15, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[12:13], s0, v[12:13]\n\tv_mov_b32_e32 v4, v12\n\tv_mad_u64_u32 v[12:13], s1, v4, s1, v[14:15]\n ; kill: def $vgpr12 killed $vgpr12 killed $vgpr12_vgpr13 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s1\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_lshlrev_b64 v[13:14], s0, v[12:13]\n\tv_mov_b32_e32 v7, v14\n\tv_mov_b32_e32 v11, v10\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\tv_mov_b32_e32 v4, v12\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v10, v13\n\tv_mov_b32_e32 v7, v11\n\tv_or_b32_e64 v10, v7, v10\n ; kill: def $vgpr10 killed $vgpr10 def $vgpr10_vgpr11 killed $exec\n\tv_mov_b32_e32 v11, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v11\n\tv_add_co_u32 v4, s0, v4, v7\n\tv_add_co_ci_u32_e64 v6, s0, v5, v6, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tglobal_load_b64 v[4:5], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v10, v5\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s0, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:144 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:136 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 15\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_5\n.LBB3_2: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 14\n\tscratch_load_b64 v[2:3], off, s33 offset:144 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:160 ; 8-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:152 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[5:6], v[4:5], off\n\tglobal_load_b64 v[10:11], v[7:8], off\n\tv_mov_b32_e32 v8, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v11\n\tv_and_b32_e64 v4, v4, v8\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v7, v10\n\tv_and_b32_e64 v12, v7, v9\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_mov_b32_e32 v4, v12\n\ts_mov_b32 s2, 24\n\tv_mad_u64_u32 v[10:11], s0, v4, s2, 0\n\tv_mov_b32_e32 v14, v11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec\n\tv_mov_b32_e32 v15, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[12:13], s0, v[12:13]\n\tv_mov_b32_e32 v4, v12\n\tv_mad_u64_u32 v[12:13], s2, v4, s2, v[14:15]\n ; kill: def $vgpr12 killed $vgpr12 killed $vgpr12_vgpr13 killed $exec\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s2\n ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec\n\tv_mov_b32_e32 v13, v4\n\tv_lshlrev_b64 v[13:14], s0, v[12:13]\n\tv_mov_b32_e32 v7, v14\n\tv_mov_b32_e32 v11, v10\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\tv_mov_b32_e32 v4, v12\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v10, v13\n\tv_mov_b32_e32 v7, v11\n\tv_or_b32_e64 v10, v7, v10\n ; kill: def $vgpr10 killed $vgpr10 def $vgpr10_vgpr11 killed $exec\n\tv_mov_b32_e32 v11, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v11\n\tv_add_co_u32 v4, s0, v4, v7\n\tv_add_co_ci_u32_e64 v6, s0, v5, v6, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tglobal_load_b64 v[4:5], v[4:5], off glc\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v10, v5\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\tv_cmp_eq_u64_e64 s0, v[0:1], v[2:3]\n\ts_or_b32 s0, s0, s1\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:144 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:168 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 16\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_2\n; %bb.3:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 16\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.4:\n\tscratch_load_b64 v[0:1], off, s33 offset:168 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:136 ; 8-byte Folded Spill\n.LBB3_5:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:136 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:8 ; 8-byte Folded Spill\n.LBB3_6:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 13\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:8 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[4:5], s0, v[4:5]\n\tv_mov_b32_e32 v2, v4\n\tv_readfirstlane_b32 s4, v3\n\tv_readfirstlane_b32 s2, v2\n ; implicit-def: $sgpr5\n ; implicit-def: $sgpr3\n ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3\n\ts_mov_b32 s3, s5\n\ts_lshl_b64 s[2:3], s[2:3], s0\n\ts_mov_b32 s0, 0\n ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5\n\ts_mov_b32 s5, s0\n\ts_or_b64 s[2:3], s[2:3], s[4:5]\n\tv_writelane_b32 v26, s2, 17\n\tv_writelane_b32 v26, s3, 18\n\tglobal_load_b64 v[2:3], v[0:1], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:200 ; 8-byte Folded Spill\n\ts_mov_b64 s[6:7], 40\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s7\n\tv_add_co_u32 v2, s4, v2, s4\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s4\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tglobal_load_b64 v[3:4], v[0:1], off offset:40\n\ts_mov_b32 s0, s3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v4\n\tv_and_b32_e64 v2, s0, v2\n\ts_mov_b32 s0, s2\n ; kill: def $vgpr3 killed $vgpr3 killed $vgpr3_vgpr4 killed $exec\n\tv_and_b32_e64 v3, s0, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v5, v3\n\tscratch_store_b64 off, v[5:6], s33 offset:184 ; 8-byte Folded Spill\n\tglobal_load_b64 v[1:2], v[0:1], off offset:8\n\ts_mov_b32 s0, 12\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s0, v0, v3\n\tv_add_co_ci_u32_e64 v2, s0, v1, v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:176 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], exec\n\tv_writelane_b32 v26, s2, 19\n\tv_writelane_b32 v26, s3, 20\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 21\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_8\n; %bb.7:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 19\n\tv_readlane_b32 s1, v26, 20\n\tscratch_load_b32 v2, off, s33 offset:96 ; 4-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v5, v0\n\ts_mov_b32 s3, 24\n\tv_mad_u64_u32 v[3:4], s2, v5, s3, 0\n\tv_mov_b32_e32 v9, v4\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v5, s2\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v5\n\ts_mov_b32 s2, 32\n\tv_lshrrev_b64 v[0:1], s2, v[0:1]\n\tv_mov_b32_e32 v5, v0\n\tv_mad_u64_u32 v[0:1], s3, v5, s3, v[9:10]\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v5, s3\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v5\n\tv_lshlrev_b64 v[9:10], s2, v[0:1]\n\tv_mov_b32_e32 v1, v10\n\tv_mov_b32_e32 v4, v3\n\ts_mov_b32 s2, 0\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v0, v5\n\tv_or_b32_e64 v0, v0, v1\n\tv_mov_b32_e32 v3, v9\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v5, v1, v3\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v0\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v3, v6\n\tv_add_co_u32 v0, s2, v0, v4\n\tv_add_co_ci_u32_e64 v3, s2, v1, v3, s2\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tglobal_store_b32 v[0:1], v2, off offset:16\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tglobal_store_b64 v[0:1], v[2:3], off offset:8\n\tv_mov_b32_e32 v2, 1\n\tglobal_store_b32 v[0:1], v2, off offset:20\n.LBB3_8:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[2:3], off, s33 offset:84 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:76 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:68 ; 8-byte Folded Reload\n\tscratch_load_b64 v[8:9], off, s33 offset:60 ; 8-byte Folded Reload\n\tscratch_load_b64 v[10:11], off, s33 offset:52 ; 8-byte Folded Reload\n\tscratch_load_b64 v[12:13], off, s33 offset:44 ; 8-byte Folded Reload\n\tscratch_load_b64 v[14:15], off, s33 offset:36 ; 8-byte Folded Reload\n\tscratch_load_b64 v[16:17], off, s33 offset:28 ; 8-byte Folded Reload\n\tscratch_load_b64 v[22:23], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:24 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v18, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v18\n\ts_mov_b32 s0, 6\n\ts_waitcnt vmcnt(0)\n\tv_lshlrev_b64 v[20:21], s0, v[0:1]\n\tv_mov_b32_e32 v0, v22\n\tv_mov_b32_e32 v19, v20\n\tv_mov_b32_e32 v1, v23\n\tv_mov_b32_e32 v18, v21\n\tv_add_co_u32 v0, s0, v0, v19\n\tv_add_co_ci_u32_e64 v18, s0, v1, v18, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v18\n\tscratch_store_b64 off, v[0:1], s33 offset:216 ; 8-byte Folded Spill\n\tglobal_store_b64 v[0:1], v[16:17], off\n\ts_mov_b64 s[4:5], 8\n\tv_mov_b32_e32 v16, v0\n\ts_mov_b32 s2, s4\n\tv_mov_b32_e32 v17, v1\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v16, s2, v16, s2\n\tv_add_co_ci_u32_e64 v18, s0, v17, s0, s2\n ; kill: def $vgpr16 killed $vgpr16 def $vgpr16_vgpr17 killed $exec\n\tv_mov_b32_e32 v17, v18\n\tscratch_store_b64 off, v[16:17], s33 offset:208 ; 8-byte Folded Spill\n\tglobal_store_b64 v[0:1], v[14:15], off offset:8\n\tglobal_store_b64 v[0:1], v[12:13], off offset:16\n\tglobal_store_b64 v[0:1], v[10:11], off offset:24\n\tglobal_store_b64 v[0:1], v[8:9], off offset:32\n\tglobal_store_b64 v[0:1], v[6:7], off offset:40\n\tglobal_store_b64 v[0:1], v[4:5], off offset:48\n\tglobal_store_b64 v[0:1], v[2:3], off offset:56\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 22\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_13\n; %bb.9:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[5:6], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[7:8], off, s33 offset:192 ; 8-byte Folded Reload\n\ts_mov_b64 s[4:5], 32\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s4\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:240 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:32 glc\n\ts_waitcnt vmcnt(1)\n\tglobal_load_b64 v[7:8], v[7:8], off\n\ts_mov_b32 s0, s3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v8\n\tv_and_b32_e64 v4, v4, s0\n\ts_mov_b32 s1, s2\n ; kill: def $vgpr7 killed $vgpr7 killed $vgpr7_vgpr8 killed $exec\n\tv_and_b32_e64 v7, v7, s1\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v4\n\tv_mov_b32_e32 v4, v7\n\ts_mov_b32 s3, 24\n\tv_mad_u64_u32 v[9:10], s2, v4, s3, 0\n\tv_mov_b32_e32 v11, v10\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v4, s2\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v4\n\ts_mov_b32 s2, 32\n\tv_lshrrev_b64 v[7:8], s2, v[7:8]\n\tv_mov_b32_e32 v4, v7\n\tv_mad_u64_u32 v[7:8], s3, v4, s3, v[11:12]\n ; kill: def $vgpr7 killed $vgpr7 killed $vgpr7_vgpr8 killed $exec\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n\tv_mov_b32_e32 v4, s3\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v4\n\tv_lshlrev_b64 v[7:8], s2, v[7:8]\n\tv_mov_b32_e32 v11, v8\n ; kill: def $vgpr9 killed $vgpr9 killed $vgpr9_vgpr10 killed $exec\n\ts_mov_b32 s2, 0\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, 0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v4, v10\n\tv_or_b32_e64 v4, v4, v11\n\tv_mov_b32_e32 v8, v7\n\tv_mov_b32_e32 v7, v9\n\tv_or_b32_e64 v8, v7, v8\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v4\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v7, v8\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v6, v9\n\tv_add_co_u32 v4, s2, v4, v7\n\tv_add_co_ci_u32_e64 v6, s2, v5, v6, s2\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\tscratch_store_b64 off, v[4:5], s33 offset:232 ; 8-byte Folded Spill\n\tglobal_store_b64 v[4:5], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s1\n\tv_mov_b32_e32 v10, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:32 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s2, v[0:1], v[2:3]\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s2, 23\n\tv_writelane_b32 v26, s0, 24\n\tscratch_store_b64 off, v[0:1], s33 offset:224 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 25\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_14\n.LBB3_10: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 24\n\tv_readlane_b32 s1, v26, 23\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[2:3], off, s33 offset:224 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:240 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:232 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_store_b64 v[4:5], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n\ts_mov_b32 s1, s3\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v10, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s1, v[0:1], v[2:3]\n\ts_or_b32 s0, s1, s0\n\tv_writelane_b32 v26, s1, 23\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 24\n\tscratch_store_b64 off, v[0:1], s33 offset:224 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 26\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_10\n; %bb.11:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 26\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.12:\n\ts_branch .LBB3_14\n.LBB3_13:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_branch .LBB3_15\n.LBB3_14:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 25\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s15, v26, 2\n\tv_readlane_b32 s14, v26, 3\n\tv_readlane_b32 s13, v26, 4\n\tv_readlane_b32 s12, v26, 5\n\tv_readlane_b32 s10, v26, 6\n\tv_readlane_b32 s11, v26, 7\n\tv_readlane_b32 s8, v26, 8\n\tv_readlane_b32 s9, v26, 9\n\tv_readlane_b32 s6, v26, 0\n\tv_readlane_b32 s7, v26, 1\n\tv_readlane_b32 s4, v26, 10\n\tv_readlane_b32 s5, v26, 11\n\tscratch_load_b32 v31, off, s33 offset:132 ; 4-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[0:1], off offset:16\n\ts_mov_b32 s0, 32\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[0:1], s0, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v2\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hsa_signal_add@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hsa_signal_add@rel32@hi+12\n\tv_mov_b32_e32 v2, 1\n\tv_mov_b32_e32 v3, 0\n\tv_mov_b32_e32 v4, 3\n\ts_swappc_b64 s[30:31], s[0:1]\n\ts_branch .LBB3_13\n.LBB3_15:\n\tscratch_load_b64 v[6:7], off, s33 offset:200 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[3:4], s0, v2, s1, 0\n\tv_mov_b32_e32 v8, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v2\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[0:1]\n\tv_mov_b32_e32 v2, v0\n\tv_mad_u64_u32 v[0:1], s1, v2, s1, v[8:9]\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v2, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_lshlrev_b64 v[1:2], s0, v[0:1]\n\tv_mov_b32_e32 v5, v2\n ; kill: def $vgpr3 killed $vgpr3 killed $vgpr3_vgpr4 killed $exec\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_mov_b32_e32 v0, v4\n\tv_or_b32_e64 v0, v0, v5\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v1, v3\n\tv_or_b32_e64 v4, v1, v2\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v1, v6\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v1, s0, v1, v3\n\tv_add_co_ci_u32_e64 v0, s0, v0, v2, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b64 s[2:3], 20\n\tv_mov_b32_e32 v0, v1\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v1, v2\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v0, s1, v0, s1\n\tv_add_co_ci_u32_e64 v2, s0, v1, s0, s1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:248 ; 8-byte Folded Spill\n.LBB3_16: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 12\n\ts_mov_b32 s0, 1\n\tv_mov_b32_e32 v0, 1\n\tscratch_store_b32 off, v0, s33 offset:256 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 27\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_18\n; %bb.17: ; in Loop: Header=BB3_16 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:248 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b32 v0, v[0:1], off glc\n\ts_waitcnt vmcnt(0)\n\tbuffer_gl1_inv\n\tbuffer_gl0_inv\n\ts_mov_b32 s0, 1\n\tv_and_b32_e64 v0, v0, s0\n\tscratch_store_b32 off, v0, s33 offset:256 ; 4-byte Folded Spill\n.LBB3_18: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 27\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s33 offset:256 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_readfirstlane_b32 s1, v0\n\ts_mov_b32 s0, -1\n\ts_mov_b32 s2, 0\n\ts_cmp_eq_u32 s1, s2\n\tv_writelane_b32 v26, s0, 28\n\ts_mov_b32 s17, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_cbranch_scc1 .LBB3_20\n; %bb.19: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_sleep 1\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v26, s0, 28\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n.LBB3_20: ; in Loop: Header=BB3_16 Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 28\n\tv_cndmask_b32_e64 v0, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v0, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n\ts_cbranch_vccnz .LBB3_16\n; %bb.21:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v26, 12\n\tscratch_load_b64 v[0:1], off, s33 offset:208 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:216 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[2:3], v[2:3], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:268 ; 8-byte Folded Spill\n\tglobal_load_b64 v[0:1], v[0:1], off\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:260 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v26, s0, 29\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_27\n; %bb.22:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v26, 17\n\tv_readlane_b32 s3, v26, 18\n\tscratch_load_b64 v[0:1], off, s33 offset:16 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:192 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tglobal_load_b64 v[11:12], v[2:3], off\n\ts_mov_b64 s[4:5], 1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v11\n\ts_mov_b32 s1, s4\n\tv_mov_b32_e32 v3, v12\n\ts_mov_b32 s0, s5\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v4, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v4, v2\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v5, v3\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v4, s1, v4, s1\n\tv_add_co_ci_u32_e64 v6, s0, v5, s0, s1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_eq_u64_e64 s0, v[4:5], s[0:1]\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v6, v5\n\tv_cndmask_b32_e64 v10, v6, v7, s0\n\tv_mov_b32_e32 v3, v2\n\tv_mov_b32_e32 v2, v4\n\tv_cndmask_b32_e64 v4, v2, v3, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v8, v4\n\tv_mov_b32_e32 v9, v10\n\tv_mov_b32_e32 v2, v8\n\tv_mov_b32_e32 v3, v9\n\tscratch_store_b64 off, v[2:3], s33 offset:300 ; 8-byte Folded Spill\n\ts_mov_b64 s[2:3], 24\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v3, v1\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v2, s1, v2, s1\n\tv_add_co_ci_u32_e64 v5, s0, v3, s0, s1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v5\n\tscratch_store_b64 off, v[2:3], s33 offset:292 ; 8-byte Folded Spill\n\tglobal_load_b64 v[2:3], v[0:1], off offset:24 glc\n\tglobal_load_b64 v[6:7], v[0:1], off\n\tv_mov_b32_e32 v5, v9\n\tv_mov_b32_e32 v13, v12\n\tv_and_b32_e64 v5, v5, v13\n ; kill: def $vgpr8 killed $vgpr8 killed $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v11\n\tv_and_b32_e64 v8, v8, v9\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v5\n\tv_mov_b32_e32 v5, v8\n\ts_mov_b32 s1, 24\n\tv_mad_u64_u32 v[11:12], s0, v5, s1, 0\n\tv_mov_b32_e32 v13, v12\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v5, s0\n ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec\n\tv_mov_b32_e32 v14, v5\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[8:9], s0, v[8:9]\n\tv_mov_b32_e32 v5, v8\n\tv_mad_u64_u32 v[8:9], s1, v5, s1, v[13:14]\n ; kill: def $vgpr8 killed $vgpr8 killed $vgpr8_vgpr9 killed $exec\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v5, s1\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v5\n\tv_lshlrev_b64 v[8:9], s0, v[8:9]\n\tv_mov_b32_e32 v13, v9\n ; kill: def $vgpr11 killed $vgpr11 killed $vgpr11_vgpr12 killed $exec\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v5, 0\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v5\n\tv_mov_b32_e32 v5, v12\n\tv_or_b32_e64 v5, v5, v13\n\tv_mov_b32_e32 v9, v8\n\tv_mov_b32_e32 v8, v11\n\tv_or_b32_e64 v11, v8, v9\n ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec\n\tv_mov_b32_e32 v12, v5\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v5, v6\n\tv_mov_b32_e32 v8, v11\n\tv_mov_b32_e32 v6, v7\n\tv_mov_b32_e32 v7, v12\n\tv_add_co_u32 v5, s0, v5, v8\n\tv_add_co_ci_u32_e64 v7, s0, v6, v7, s0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v7\n\tscratch_store_b64 off, v[5:6], s33 offset:284 ; 8-byte Folded Spill\n\tglobal_store_b64 v[5:6], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off offset:24 glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s2, v[0:1], v[2:3]\n\tv_cmp_ne_u64_e64 s1, v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v26, s2, 30\n\tv_writelane_b32 v26, s0, 31\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\tscratch_store_b64 off, v[0:1], s33 offset:276 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n ; implicit-def: $vgpr26 : SGPR spill to VGPR lane\n\tv_writelane_b32 v26, s0, 0\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB3_26\n.LBB3_23: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v25, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v25, 31\n\tv_readlane_b32 s1, v25, 30\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\tscratch_load_b64 v[2:3], off, s33 offset:276 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:292 ; 8-byte Folded Reload\n\tscratch_load_b64 v[4:5], off, s33 offset:300 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:284 ; 8-byte Folded Reload\n\ts_sleep 1\n\ts_waitcnt vmcnt(0)\n\tglobal_store_b64 v[6:7], v[2:3], off\n\tv_mov_b32_e32 v8, v3\n\tv_mov_b32_e32 v9, v2\n\tv_mov_b32_e32 v10, v5\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v7, v8\n\ts_waitcnt_vscnt null, 0x0\n\tglobal_atomic_cmpswap_b64 v[0:1], v[0:1], v[4:7], off glc\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u64_e64 s1, v[0:1], v[2:3]\n\ts_or_b32 s0, s1, s0\n\tv_writelane_b32 v25, s1, 30\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v25, s1, 31\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v25, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\tscratch_store_b64 off, v[0:1], s33 offset:276 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v26, s1, 1\n\ts_or_saveexec_b32 s17, -1\n\tscratch_store_b32 off, v26, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s17\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB3_23\n; %bb.24:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.25:\n.LBB3_26:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 0\n\ts_or_b32 exec_lo, exec_lo, s0\n.LBB3_27:\n\ts_or_saveexec_b32 s17, -1\n\tscratch_load_b32 v26, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s17\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v26, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[3:4], off, s33 offset:260 ; 8-byte Folded Reload\n\tscratch_load_b64 v[1:2], off, s33 offset:268 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v3\n\tv_mov_b32_e32 v3, v4\n\tv_readlane_b32 s30, v24, 0\n\tv_readlane_b32 s31, v24, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v24, off, s33 offset:308 ; 4-byte Folded Reload\n\tscratch_load_b32 v25, off, s33 offset:312 ; 4-byte Folded Reload\n\tscratch_load_b32 v26, off, s33 offset:316 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xfffffeb0\n\ts_mov_b32 s33, s18\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end3:\n\t.size\t__ockl_hostcall_internal, .Lfunc_end3-__ockl_hostcall_internal\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 5344\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 392\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_hostcall_preview\n\t.type\t__ockl_hostcall_preview,@function\n__ockl_hostcall_preview: ; @__ockl_hostcall_preview\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v27, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tv_writelane_b32 v27, s33, 0\n\tv_writelane_b32 v27, s30, 1\n\tv_writelane_b32 v27, s31, 2\n\tv_mov_b32_e32 v18, v16\n\tv_mov_b32_e32 v17, v15\n\tv_mov_b32_e32 v16, v14\n\tv_mov_b32_e32 v15, v13\n\tv_mov_b32_e32 v14, v12\n\tv_mov_b32_e32 v13, v11\n\tv_mov_b32_e32 v12, v10\n\tv_mov_b32_e32 v11, v9\n\tv_mov_b32_e32 v10, v8\n\tv_mov_b32_e32 v9, v7\n\tv_mov_b32_e32 v8, v6\n\tv_mov_b32_e32 v7, v5\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v5, v3\n\tv_mov_b32_e32 v4, v2\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s0, s[0:1], 0x0\n\ts_mov_b32 s1, 0x1f4\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_i32 s0, s1\n\ts_mov_b32 s1, 0x50\n\ts_mov_b32 s0, 24\n\ts_cselect_b32 s0, s0, s1\n\ts_load_b64 s[0:1], s[8:9], s0 offset:0x0\n\ts_waitcnt lgkmcnt(0)\n\ts_mov_b32 s3, s0\n\ts_mov_b32 s2, 32\n\ts_lshr_b64 s[0:1], s[0:1], s2\n\ts_mov_b32 s2, s0\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_internal@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_internal@rel32@hi+12\n\tv_mov_b32_e32 v0, s3\n\tv_mov_b32_e32 v1, s2\n\tv_readlane_b32 s30, v27, 1\n\tv_readlane_b32 s31, v27, 2\n\tv_readlane_b32 s33, v27, 0\n\ts_xor_saveexec_b32 s2, -1\n\tscratch_load_b32 v27, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s2\n\ts_setpc_b64 s[0:1]\n.Lfunc_end4:\n\t.size\t__ockl_hostcall_preview, .Lfunc_end4-__ockl_hostcall_preview\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 272\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 400\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_stderr_begin\n\t.type\t__ockl_fprintf_stderr_begin,@function\n__ockl_fprintf_stderr_begin: ; @__ockl_fprintf_stderr_begin\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s16, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v28, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 16\n\tv_writelane_b32 v28, s30, 0\n\tv_writelane_b32 v28, s31, 1\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\tv_mov_b32_e32 v1, 33\n\tv_mov_b32_e32 v3, 1\n\tv_mov_b32_e32 v16, 0\n\tv_mov_b32_e32 v2, v16\n\tv_mov_b32_e32 v4, v16\n\tv_mov_b32_e32 v5, v16\n\tv_mov_b32_e32 v6, v16\n\tv_mov_b32_e32 v7, v16\n\tv_mov_b32_e32 v8, v16\n\tv_mov_b32_e32 v9, v16\n\tv_mov_b32_e32 v10, v16\n\tv_mov_b32_e32 v11, v16\n\tv_mov_b32_e32 v12, v16\n\tv_mov_b32_e32 v13, v16\n\tv_mov_b32_e32 v14, v16\n\tv_mov_b32_e32 v15, v16\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_store_b32 off, v1, s33 ; 4-byte Folded Spill\n ; kill: def $vgpr1 killed $vgpr3 killed $exec\n\tscratch_load_b32 v3, off, s33 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v3\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v28, 0\n\tv_readlane_b32 s31, v28, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v28, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, -16\n\ts_mov_b32 s33, s16\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end5:\n\t.size\t__ockl_fprintf_stderr_begin, .Lfunc_end5-__ockl_fprintf_stderr_begin\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 228\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 416\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_append_string_n\n\t.type\t__ockl_fprintf_append_string_n,@function\n__ockl_fprintf_append_string_n: ; @__ockl_fprintf_append_string_n\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s20, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v32, s33 offset:704 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v33, s33 offset:708 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v34, s33 offset:712 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0x2d0\n\tv_writelane_b32 v32, s30, 0\n\tv_writelane_b32 v32, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:68 ; 4-byte Folded Spill\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\tv_writelane_b32 v34, s6, 0\n\tv_writelane_b32 v34, s7, 1\n\tscratch_store_b32 off, v6, s33 offset:60 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v5, s33 offset:56 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v4, s33 offset:64 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v6, v3\n\tscratch_load_b32 v3, off, s33 offset:64 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v4, v2\n\tscratch_load_b32 v2, off, s33 offset:60 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v4, s33 offset:52 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v7, v1\n\tscratch_load_b32 v1, off, s33 offset:56 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v5, v0\n\tscratch_load_b32 v0, off, s33 offset:52 ; 4-byte Folded Reload\n\tv_writelane_b32 v34, s15, 2\n\tv_writelane_b32 v34, s14, 3\n\tv_writelane_b32 v34, s13, 4\n\tv_writelane_b32 v34, s12, 5\n\tv_writelane_b32 v34, s10, 6\n\tv_writelane_b32 v34, s11, 7\n\tv_writelane_b32 v34, s8, 8\n\tv_writelane_b32 v34, s9, 9\n\tv_writelane_b32 v34, s4, 10\n\tv_writelane_b32 v34, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v4, v1\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v7\n\tscratch_store_b64 off, v[3:4], s33 offset:44 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v3, v0\n\tscratch_store_b64 off, v[3:4], s33 offset:36 ; 8-byte Folded Spill\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s0, 0\n\tv_cmp_eq_u32_e64 s0, v2, s0\n\tv_mov_b32_e32 v4, v6\n\ts_mov_b64 s[2:3], 2\n\ts_mov_b32 s1, s3\n\tv_or_b32_e64 v2, v4, s1\n\tv_mov_b32_e32 v3, v5\n\ts_mov_b32 s1, s2\n\tv_or_b32_e64 v5, v3, s1\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v2\n\tv_mov_b32_e32 v2, v6\n\tv_cndmask_b32_e64 v4, v2, v4, s0\n\tv_mov_b32_e32 v2, v5\n\tv_cndmask_b32_e64 v2, v2, v3, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b64 off, v[2:3], s33 offset:28 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], 0\n\tv_cmp_ne_u64_e64 s0, v[0:1], s[0:1]\n ; implicit-def: $sgpr4_sgpr5_sgpr6_sgpr7\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tv_mov_b32_e32 v2, s6\n\tv_mov_b32_e32 v3, s7\n\tscratch_store_b128 off, v[0:3], s33 offset:12 ; 16-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 12\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_3\n\ts_branch .LBB6_2\n.LBB6_1:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v34, 2\n\tv_readlane_b32 s14, v34, 3\n\tv_readlane_b32 s13, v34, 4\n\tv_readlane_b32 s12, v34, 5\n\tv_readlane_b32 s10, v34, 6\n\tv_readlane_b32 s11, v34, 7\n\tv_readlane_b32 s8, v34, 8\n\tv_readlane_b32 s9, v34, 9\n\tv_readlane_b32 s6, v34, 0\n\tv_readlane_b32 s7, v34, 1\n\tv_readlane_b32 s4, v34, 10\n\tv_readlane_b32 s5, v34, 11\n\tscratch_load_b32 v31, off, s33 offset:68 ; 4-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:28 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v3\n\tv_and_b32_e64 v4, v0, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v0, v2\n\tv_and_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_mov_b32_e32 v4, v1\n\ts_mov_b64 s[0:1], 32\n\ts_mov_b32 s2, s1\n\tv_or_b32_e64 v4, v4, s2\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_or_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_mov_b32_e32 v1, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[2:3], s0, v[2:3]\n ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\tv_mov_b32_e32 v16, 0\n\tscratch_store_b32 off, v16, s33 offset:88 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v16\n\tv_mov_b32_e32 v4, v16\n\tv_mov_b32_e32 v5, v16\n\tv_mov_b32_e32 v6, v16\n\tv_mov_b32_e32 v7, v16\n\tv_mov_b32_e32 v8, v16\n\tv_mov_b32_e32 v9, v16\n\tv_mov_b32_e32 v10, v16\n\tv_mov_b32_e32 v11, v16\n\tv_mov_b32_e32 v12, v16\n\tv_mov_b32_e32 v13, v16\n\tv_mov_b32_e32 v14, v16\n\tv_mov_b32_e32 v15, v16\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_mov_b32_e32 v6, v1\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v4, v3\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v6\n\tv_mov_b32_e32 v2, v5\n\tv_mov_b32_e32 v3, v4\n\tscratch_store_b128 off, v[0:3], s33 offset:72 ; 16-byte Folded Spill\n\ts_branch .LBB6_63\n.LBB6_2:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b64 v[4:5], off, s33 offset:36 ; 8-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:44 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:28 ; 8-byte Folded Reload\n\ts_mov_b64 s[0:1], 2\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v1, v3\n\tv_and_b32_e64 v8, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v0, v2\n\tv_and_b32_e64 v2, v0, s0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v8\n\tscratch_store_b64 off, v[2:3], s33 offset:124 ; 8-byte Folded Spill\n\ts_mov_b64 s[0:1], -3\n\ts_mov_b32 s2, s1\n\tv_and_b32_e64 v2, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_and_b32_e64 v0, v0, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v10, v1\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\ts_mov_b64 s[2:3], 0\n\ts_mov_b32 s0, s3\n\ts_mov_b32 s1, s2\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v9, s1\n\tv_mov_b32_e32 v8, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v10\n\tv_mov_b32_e32 v2, v9\n\tv_mov_b32_e32 v3, v8\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v34, s0, 13\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[6:7], s33 offset:116 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[4:5], s33 offset:108 ; 8-byte Folded Spill\n\tscratch_store_b128 off, v[0:3], s33 offset:92 ; 16-byte Folded Spill\n\ts_branch .LBB6_4\n.LBB6_3:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 12\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b128 v[0:3], off, s33 offset:12 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:72 ; 16-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 14\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_63\n\ts_branch .LBB6_1\n.LBB6_4: ; =>This Loop Header: Depth=1\n ; Child Loop BB6_8 Depth 2\n ; Child Loop BB6_16 Depth 2\n ; Child Loop BB6_24 Depth 2\n ; Child Loop BB6_32 Depth 2\n ; Child Loop BB6_40 Depth 2\n ; Child Loop BB6_48 Depth 2\n ; Child Loop BB6_56 Depth 2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 13\n\tscratch_load_b64 v[6:7], off, s33 offset:124 ; 8-byte Folded Reload\n\tscratch_load_b128 v[8:11], off, s33 offset:92 ; 16-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:116 ; 8-byte Folded Reload\n\tscratch_load_b64 v[0:1], off, s33 offset:108 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:176 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[3:4], s33 offset:168 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 15\n\ts_mov_b64 s[2:3], 56\n\tv_cmp_gt_u64_e64 s0, v[3:4], s[2:3]\n\tv_mov_b32_e32 v1, v9\n\tv_mov_b32_e32 v2, v8\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v8, v2\n\tv_mov_b32_e32 v9, v1\n\tv_mov_b32_e32 v0, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or_b32_e64 v0, v0, v5\n\tv_mov_b32_e32 v5, v8\n\tv_or_b32_e64 v5, v5, v6\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v0\n\tv_mov_b32_e32 v0, v6\n\tv_cndmask_b32_e64 v0, v0, v1, s0\n\tv_mov_b32_e32 v1, v5\n\tv_cndmask_b32_e64 v1, v1, v2, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_cmp_lt_u64_e64 s1, v[3:4], s[2:3]\n\tv_mov_b32_e32 v0, v4\n\ts_mov_b32 s0, s3\n\tv_cndmask_b32_e64 v5, s0, v0, s1\n\tv_mov_b32_e32 v0, v3\n\ts_mov_b32 s0, s2\n\tv_cndmask_b32_e64 v0, s0, v0, s1\n\tscratch_store_b32 off, v0, s33 offset:164 ; 4-byte Folded Spill\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v3, v0\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:156 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:148 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:140 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:132 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 16\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_6\n; %bb.5: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:164 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 17\n\tv_writelane_b32 v34, s0, 18\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:184 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_11\n\ts_branch .LBB6_8\n.LBB6_6: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 16\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 20\n\tscratch_load_b64 v[0:1], off, s33 offset:140 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:132 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:212 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:208 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:200 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 21\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_12\n; %bb.7: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:212 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:208 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:200 ; 8-byte Folded Spill\n\ts_branch .LBB6_12\n.LBB6_8: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 18\n\tv_readlane_b32 s2, v34, 17\n\tscratch_load_b64 v[4:5], off, s33 offset:192 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:176 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 17\n\tv_writelane_b32 v34, s1, 18\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:192 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:220 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 22\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_8\n; %bb.9: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.10: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:220 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:184 ; 8-byte Folded Spill\n.LBB6_11: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 19\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:184 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:140 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 20\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:132 ; 8-byte Folded Spill\n\ts_branch .LBB6_6\n.LBB6_12: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:212 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:208 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:200 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:256 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:252 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:244 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:236 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:228 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 23\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_14\n; %bb.13: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:252 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 24\n\tv_writelane_b32 v34, s0, 25\n\tscratch_store_b64 off, v[2:3], s33 offset:272 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:264 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 26\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_19\n\ts_branch .LBB6_16\n.LBB6_14: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 23\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 27\n\tscratch_load_b64 v[0:1], off, s33 offset:236 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:228 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:292 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:288 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:280 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 28\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_20\n; %bb.15: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:244 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:252 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:292 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:288 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:280 ; 8-byte Folded Spill\n\ts_branch .LBB6_20\n.LBB6_16: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 25\n\tv_readlane_b32 s2, v34, 24\n\tscratch_load_b64 v[4:5], off, s33 offset:272 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:252 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:244 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 24\n\tv_writelane_b32 v34, s1, 25\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:272 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:300 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 29\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_16\n; %bb.17: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.18: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:300 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:264 ; 8-byte Folded Spill\n.LBB6_19: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 26\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:244 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:264 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:236 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 27\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:228 ; 8-byte Folded Spill\n\ts_branch .LBB6_14\n.LBB6_20: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 28\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:292 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:288 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:280 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:336 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:332 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:324 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:316 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:308 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 30\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_22\n; %bb.21: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:332 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v33, s2, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tv_writelane_b32 v34, s0, 0\n\tscratch_store_b64 off, v[2:3], s33 offset:352 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:344 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_27\n\ts_branch .LBB6_24\n.LBB6_22: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v33, 30\n\ts_or_saveexec_b32 s0, s0\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v34, 2\n\tscratch_load_b64 v[0:1], off, s33 offset:316 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:308 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:372 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:368 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:360 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 3\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_28\n; %bb.23: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:324 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:332 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:372 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:368 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:360 ; 8-byte Folded Spill\n\ts_branch .LBB6_28\n.LBB6_24: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 0\n\tv_readlane_b32 s2, v33, 31\n\tscratch_load_b64 v[4:5], off, s33 offset:352 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:332 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:324 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v33, s2, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tv_writelane_b32 v34, s1, 0\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:352 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:380 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 4\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_24\n; %bb.25: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.26: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:380 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:344 ; 8-byte Folded Spill\n.LBB6_27: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:324 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:344 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:316 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:308 ; 8-byte Folded Spill\n\ts_branch .LBB6_22\n.LBB6_28: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 3\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:372 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:368 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:360 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:416 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:412 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:404 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:396 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:388 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 5\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_30\n; %bb.29: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:412 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 6\n\tv_writelane_b32 v34, s0, 7\n\tscratch_store_b64 off, v[2:3], s33 offset:432 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:424 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 8\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_35\n\ts_branch .LBB6_32\n.LBB6_30: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 5\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 9\n\tscratch_load_b64 v[0:1], off, s33 offset:396 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:388 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:452 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:448 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:440 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 10\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_36\n; %bb.31: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:404 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:412 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:452 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:448 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:440 ; 8-byte Folded Spill\n\ts_branch .LBB6_36\n.LBB6_32: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 7\n\tv_readlane_b32 s2, v34, 6\n\tscratch_load_b64 v[4:5], off, s33 offset:432 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:412 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:404 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 6\n\tv_writelane_b32 v34, s1, 7\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:432 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:460 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 11\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_32\n; %bb.33: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 11\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.34: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:460 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:424 ; 8-byte Folded Spill\n.LBB6_35: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 8\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:404 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:424 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:396 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 9\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:388 ; 8-byte Folded Spill\n\ts_branch .LBB6_30\n.LBB6_36: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 10\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:452 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:448 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:440 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:496 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:492 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:484 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:476 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:468 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 12\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_38\n; %bb.37: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:492 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 13\n\tv_writelane_b32 v34, s0, 14\n\tscratch_store_b64 off, v[2:3], s33 offset:512 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:504 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 15\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_43\n\ts_branch .LBB6_40\n.LBB6_38: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 12\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 16\n\tscratch_load_b64 v[0:1], off, s33 offset:476 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:468 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:532 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:528 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:520 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 17\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_44\n; %bb.39: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:484 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:492 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:532 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:528 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:520 ; 8-byte Folded Spill\n\ts_branch .LBB6_44\n.LBB6_40: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 14\n\tv_readlane_b32 s2, v34, 13\n\tscratch_load_b64 v[4:5], off, s33 offset:512 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:492 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:484 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 13\n\tv_writelane_b32 v34, s1, 14\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:512 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:540 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 18\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_40\n; %bb.41: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 18\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.42: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:540 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:504 ; 8-byte Folded Spill\n.LBB6_43: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:484 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:504 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:476 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 16\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:468 ; 8-byte Folded Spill\n\ts_branch .LBB6_38\n.LBB6_44: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 17\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:532 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:528 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:520 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:576 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:572 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:564 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n ; implicit-def: $sgpr4_sgpr5\n\tv_mov_b32_e32 v2, s4\n\tv_mov_b32_e32 v3, s5\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[2:3], s33 offset:556 ; 8-byte Folded Spill\n ; implicit-def: $sgpr1\n\tscratch_store_b64 off, v[0:1], s33 offset:548 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_46\n; %bb.45: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:572 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 20\n\tv_writelane_b32 v34, s0, 21\n\tscratch_store_b64 off, v[2:3], s33 offset:592 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:584 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 22\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_51\n\ts_branch .LBB6_48\n.LBB6_46: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 19\n\ts_or_saveexec_b32 s0, s0\n\tv_readlane_b32 s1, v34, 23\n\tscratch_load_b64 v[0:1], off, s33 offset:556 ; 8-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:548 ; 8-byte Folded Reload\n\tv_mov_b32_e32 v2, s1\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:612 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:608 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:600 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 24\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_52\n; %bb.47: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[4:5], off, s33 offset:564 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:572 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(1)\n\tflat_load_u8 v0, v[4:5]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v3, v[4:5] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v3, v7\n\tv_or_b32_e64 v3, v3, v8\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v6\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v7, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v3\n\tflat_load_u8 v3, v[4:5] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v9, s2, v3\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v3, v[4:5] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v6, s1, v3\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[7:8], s2, v[6:7]\n\tflat_load_u8 v3, v[4:5] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v9, s1, v3\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v6, v[4:5] offset:6\n\tv_mov_b32_e32 v3, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v3\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[7:8], s0, v[6:7]\n\tflat_load_u8 v9, v[4:5] offset:7\n ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec\n\tv_mov_b32_e32 v10, v3\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[9:10], s0, v[9:10]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v11, v10\n\tv_mov_b32_e32 v6, v8\n\tv_or3_b32 v3, v3, v6, v11\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v6, v9\n\tv_mov_b32_e32 v1, v7\n\tv_or3_b32 v0, v0, v1, v6\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s0, -8\n\tv_add_nc_u32_e64 v2, v2, s0\n\ts_mov_b64 s[2:3], 8\n\tv_mov_b32_e32 v3, v4\n\ts_mov_b32 s1, s2\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, s3\n\tv_add_co_u32 v3, s1, v3, s1\n\tv_add_co_ci_u32_e64 v5, s0, v4, s0, s1\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\tscratch_store_b64 off, v[3:4], s33 offset:612 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v2, s33 offset:608 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:600 ; 8-byte Folded Spill\n\ts_branch .LBB6_52\n.LBB6_48: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 21\n\tv_readlane_b32 s2, v34, 20\n\tscratch_load_b64 v[4:5], off, s33 offset:592 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:572 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:564 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 20\n\tv_writelane_b32 v34, s1, 21\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:592 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:620 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 25\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_48\n; %bb.49: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 25\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.50: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:620 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:584 ; 8-byte Folded Spill\n.LBB6_51: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:564 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:584 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[2:3], s33 offset:556 ; 8-byte Folded Spill\n\tv_writelane_b32 v34, s0, 23\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[0:1], s33 offset:548 ; 8-byte Folded Spill\n\ts_branch .LBB6_46\n.LBB6_52: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 24\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[1:2], off, s33 offset:612 ; 8-byte Folded Reload\n\tscratch_load_b32 v0, off, s33 offset:608 ; 4-byte Folded Reload\n\tscratch_load_b64 v[3:4], off, s33 offset:600 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[3:4], s33 offset:648 ; 8-byte Folded Spill\n\tscratch_store_b32 off, v0, s33 offset:644 ; 4-byte Folded Spill\n\tscratch_store_b64 off, v[1:2], s33 offset:636 ; 8-byte Folded Spill\n\ts_mov_b32 s0, 8\n\tv_cmp_lt_u32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s33 offset:628 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v34, s1, 26\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_54\n; %bb.53: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\tscratch_load_b32 v0, off, s33 offset:644 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_ne_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 0\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 27\n\tv_writelane_b32 v34, s0, 28\n\tscratch_store_b64 off, v[2:3], s33 offset:664 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:656 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v34, s0, 29\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB6_59\n\ts_branch .LBB6_56\n.LBB6_54: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 26\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:628 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:672 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v34, s0, 30\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB6_60\n; %bb.55: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[2:3], off, s33 offset:636 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tflat_load_u8 v0, v[2:3]\n\ts_mov_b32 s1, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s1, v0\n\ts_mov_b32 s0, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s0\n\tflat_load_u8 v4, v[2:3] offset:1\n\ts_mov_b32 s2, 8\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v5, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v4\n\tv_mov_b32_e32 v7, v1\n\tv_mov_b32_e32 v4, v6\n\tv_or_b32_e64 v4, v4, v7\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v5\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:2\n\ts_mov_b32 s2, 16\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v6, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v4\n\tflat_load_u8 v4, v[2:3] offset:3\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b32_e64 v8, s2, v4\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v4, s0\n ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec\n\tv_mov_b32_e32 v9, v4\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v10, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or3_b32 v4, v4, v5, v10\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v5, v8\n\tv_mov_b32_e32 v1, v6\n\tv_or3_b32 v0, v0, v1, v5\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:4\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v4, s1, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, s0\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[6:7], s2, v[4:5]\n\tflat_load_u8 v4, v[2:3] offset:5\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v4, s1, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, s0\n\ts_mov_b32 s0, 40\n\tv_lshlrev_b64 v[8:9], s0, v[4:5]\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v10, v9\n\tv_mov_b32_e32 v5, v7\n\tv_or3_b32 v4, v4, v5, v10\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v5, v8\n\tv_mov_b32_e32 v1, v6\n\tv_or3_b32 v0, v0, v1, v5\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tflat_load_u8 v4, v[2:3] offset:6\n\tv_mov_b32_e32 v6, 0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v6\n\ts_mov_b32 s0, 48\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[4:5], s0, v[4:5]\n\tflat_load_u8 v2, v[2:3] offset:7\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v6\n\ts_mov_b32 s0, 56\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_lshlrev_b64 v[6:7], s0, v[2:3]\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v8, v7\n\tv_mov_b32_e32 v3, v5\n\tv_or3_b32 v2, v2, v3, v8\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v3, v6\n\tv_mov_b32_e32 v1, v4\n\tv_or3_b32 v0, v0, v1, v3\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tscratch_store_b64 off, v[0:1], s33 offset:672 ; 8-byte Folded Spill\n\ts_branch .LBB6_60\n.LBB6_56: ; Parent Loop BB6_4 Depth=1\n ; => This Inner Loop Header: Depth=2\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 28\n\tv_readlane_b32 s2, v34, 27\n\tscratch_load_b64 v[4:5], off, s33 offset:664 ; 8-byte Folded Reload\n\tscratch_load_b32 v2, off, s33 offset:644 ; 4-byte Folded Reload\n\tscratch_load_b64 v[6:7], off, s33 offset:636 ; 8-byte Folded Reload\n\ts_mov_b32 s1, 0\n\ts_mov_b32 s6, s0\n\ts_mov_b32 s7, s1\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v6\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v1, v7\n\ts_mov_b32 s3, s7\n\tv_add_co_u32 v0, s4, v0, s4\n\tv_add_co_ci_u32_e64 v3, s3, v1, s3, s4\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s3, 0xffff\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_and_b32_e64 v0, s3, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s1\n\ts_mov_b32 s1, 3\n\ts_lshl_b32 s1, s0, s1\n\tv_lshlrev_b64 v[0:1], s1, v[0:1]\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v6, v5\n\tv_or_b32_e64 v3, v3, v6\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_or_b32_e64 v0, v0, v1\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s1, 1\n\ts_add_i32 s1, s0, s1\n\tv_cmp_eq_u32_e64 s0, s1, v2\n\ts_or_b32 s0, s0, s2\n\ts_mov_b32 s2, s0\n\tv_writelane_b32 v34, s2, 27\n\tv_writelane_b32 v34, s1, 28\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v2, v0\n\tscratch_store_b64 off, v[2:3], s33 offset:664 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[0:1], s33 offset:680 ; 8-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 31\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:4 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_56\n; %bb.57: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 31\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.58: ; in Loop: Header=BB6_4 Depth=1\n\tscratch_load_b64 v[0:1], off, s33 offset:680 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:656 ; 8-byte Folded Spill\n.LBB6_59: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s33 offset:656 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s33 offset:628 ; 8-byte Folded Spill\n\ts_branch .LBB6_54\n.LBB6_60: ; in Loop: Header=BB6_4 Depth=1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v33, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v34, 30\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v33, 2\n\tv_readlane_b32 s14, v33, 3\n\tv_readlane_b32 s13, v33, 4\n\tv_readlane_b32 s12, v33, 5\n\tv_readlane_b32 s10, v33, 6\n\tv_readlane_b32 s11, v33, 7\n\tv_readlane_b32 s8, v33, 8\n\tv_readlane_b32 s9, v33, 9\n\tv_readlane_b32 s6, v33, 0\n\tv_readlane_b32 s7, v33, 1\n\tv_readlane_b32 s4, v33, 10\n\tv_readlane_b32 s5, v33, 11\n\tscratch_load_b64 v[0:1], off, s33 offset:156 ; 8-byte Folded Reload\n\tscratch_load_b32 v31, off, s33 offset:68 ; 4-byte Folded Reload\n\tscratch_load_b64 v[19:20], off, s33 offset:648 ; 8-byte Folded Reload\n\tscratch_load_b64 v[21:22], off, s33 offset:576 ; 8-byte Folded Reload\n\tscratch_load_b64 v[23:24], off, s33 offset:496 ; 8-byte Folded Reload\n\tscratch_load_b64 v[25:26], off, s33 offset:416 ; 8-byte Folded Reload\n\tscratch_load_b64 v[27:28], off, s33 offset:336 ; 8-byte Folded Reload\n\tscratch_load_b64 v[29:30], off, s33 offset:256 ; 8-byte Folded Reload\n\tscratch_load_b64 v[2:3], off, s33 offset:148 ; 8-byte Folded Reload\n\tscratch_load_b64 v[17:18], off, s33 offset:672 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(9)\n\tv_mov_b32_e32 v1, v0\n\ts_mov_b32 s0, 28\n\tv_mov_b32_e32 v0, 2\n\tv_lshl_add_u32 v1, v1, v0, s0\n\ts_mov_b32 s0, 0x1e0\n\tv_and_b32_e64 v5, v1, s0\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v1, 0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v1\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\ts_waitcnt vmcnt(1)\n\tv_mov_b32_e32 v1, v3\n\tv_and_b32_e64 v1, v1, s2\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_mov_b32_e32 v4, v2\n\tv_and_b32_e64 v7, v4, s0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v4, v6\n\tv_or_b32_e64 v1, v1, v4\n\tv_mov_b32_e32 v4, v7\n ; kill: def $vgpr5 killed $vgpr5 killed $vgpr5_vgpr6 killed $exec\n\tv_or_b32_e64 v4, v4, v5\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v1\n\tv_mov_b32_e32 v1, v4\n\ts_mov_b32 s0, 32\n ; implicit-def: $vgpr34 : SGPR spill to VGPR lane\n\tv_writelane_b32 v34, s0, 0\n\tv_lshrrev_b64 v[2:3], s0, v[2:3]\n ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec\n\tv_lshrrev_b64 v[3:4], s0, v[29:30]\n\tv_mov_b32_e32 v4, v3\n\tv_lshrrev_b64 v[5:6], s0, v[27:28]\n\tv_mov_b32_e32 v6, v5\n\tv_lshrrev_b64 v[7:8], s0, v[25:26]\n\tv_mov_b32_e32 v8, v7\n\tv_lshrrev_b64 v[9:10], s0, v[23:24]\n\tv_mov_b32_e32 v10, v9\n\tv_lshrrev_b64 v[11:12], s0, v[21:22]\n\tv_mov_b32_e32 v12, v11\n\tv_lshrrev_b64 v[13:14], s0, v[19:20]\n\tv_mov_b32_e32 v14, v13\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[15:16], s0, v[17:18]\n\tv_mov_b32_e32 v16, v15\n\tv_mov_b32_e32 v3, v29\n\tv_mov_b32_e32 v5, v27\n\tv_mov_b32_e32 v7, v25\n\tv_mov_b32_e32 v9, v23\n\tv_mov_b32_e32 v11, v21\n\tv_mov_b32_e32 v13, v19\n\tv_mov_b32_e32 v15, v17\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b64 v[4:5], off, s33 offset:168 ; 8-byte Folded Reload\n\tscratch_load_b64 v[12:13], off, s33 offset:176 ; 8-byte Folded Reload\n\tscratch_load_b64 v[10:11], off, s33 offset:156 ; 8-byte Folded Reload\n\tv_readlane_b32 s1, v33, 15\n\tv_mov_b32_e32 v8, v1\n\tv_mov_b32_e32 v7, v2\n\tv_mov_b32_e32 v6, v3\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v2, v7\n\tv_mov_b32_e32 v3, v6\n\ts_waitcnt vmcnt(2)\n\tv_mov_b32_e32 v6, v4\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v7, v10\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v5, v11\n\tv_sub_co_u32 v6, s0, v6, v7\n\tv_sub_co_ci_u32_e64 v4, s0, v4, v5, s0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v4\n\tv_mov_b32_e32 v4, v12\n\tv_mov_b32_e32 v9, v10\n\tv_mov_b32_e32 v5, v13\n\tv_mov_b32_e32 v8, v11\n\tv_add_co_u32 v4, s0, v4, v9\n\tv_add_co_ci_u32_e64 v8, s0, v5, v8, s0\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v8\n\ts_mov_b64 s[2:3], 0\n\tv_cmp_eq_u64_e64 s0, v[6:7], s[2:3]\n\ts_or_b32 s0, s0, s1\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v33, s1, 13\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v33, s33 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\tscratch_store_b64 off, v[6:7], s33 offset:116 ; 8-byte Folded Spill\n\tscratch_store_b64 off, v[4:5], s33 offset:108 ; 8-byte Folded Spill\n\tv_mov_b32_e32 v7, v3\n\tv_mov_b32_e32 v6, v2\n\tv_mov_b32_e32 v5, v1\n\tv_mov_b32_e32 v4, v0\n\tscratch_store_b128 off, v[4:7], s33 offset:92 ; 16-byte Folded Spill\n\tscratch_store_b128 off, v[0:3], s33 offset:688 ; 16-byte Folded Spill\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v34, s1, 1\n\ts_or_saveexec_b32 s19, -1\n\tscratch_store_b32 off, v34, s33 offset:8 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s19\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB6_4\n; %bb.61:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 offset:8 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 1\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.62:\n\tscratch_load_b128 v[0:3], off, s33 offset:688 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:12 ; 16-byte Folded Spill\n\ts_branch .LBB6_3\n.LBB6_63:\n\ts_or_saveexec_b32 s19, -1\n\tscratch_load_b32 v34, off, s33 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s19\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v34, 14\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b128 v[3:6], off, s33 offset:72 ; 16-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v0, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v0, v3\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v32, 0\n\tv_readlane_b32 s31, v32, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v32, off, s33 offset:704 ; 4-byte Folded Reload\n\tscratch_load_b32 v33, off, s33 offset:708 ; 4-byte Folded Reload\n\tscratch_load_b32 v34, off, s33 offset:712 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xfffffd30\n\ts_mov_b32 s33, s20\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end6:\n\t.size\t__ockl_fprintf_append_string_n, .Lfunc_end6-__ockl_fprintf_append_string_n\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 11984\n; NumSgprs: 36\n; NumVgprs: 35\n; ScratchSize: 1120\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_fprintf_append_args\n\t.type\t__ockl_fprintf_append_args,@function\n__ockl_fprintf_append_args: ; @__ockl_fprintf_append_args\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s19, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v28, s33 offset:8 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v29, s33 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 32\n\tv_writelane_b32 v28, s30, 0\n\tv_writelane_b32 v28, s31, 1\n\tscratch_store_b32 off, v17, s33 offset:4 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v17, v2\n\tv_mov_b32_e32 v18, v0\n\tscratch_load_b32 v0, off, s33 offset:4 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v15\n ; kill: def $vgpr20 killed $vgpr16 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v13\n ; kill: def $vgpr20 killed $vgpr14 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v11\n ; kill: def $vgpr20 killed $vgpr12 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v9\n ; kill: def $vgpr20 killed $vgpr10 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v7\n ; kill: def $vgpr20 killed $vgpr8 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v5\n ; kill: def $vgpr20 killed $vgpr6 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v19, v3\n ; kill: def $vgpr20 killed $vgpr4 killed $exec\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr18 killed $vgpr18 def $vgpr18_vgpr19 killed $exec\n\tv_mov_b32_e32 v19, v1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s0, v0, s0\n\tv_mov_b32_e32 v1, v19\n\ts_mov_b64 s[2:3], 2\n\ts_mov_b32 s1, s3\n\tv_or_b32_e64 v0, v1, s1\n\tv_mov_b32_e32 v2, v18\n\ts_mov_b32 s1, s2\n\tv_or_b32_e64 v18, v2, s1\n ; kill: def $vgpr18 killed $vgpr18 def $vgpr18_vgpr19 killed $exec\n\tv_mov_b32_e32 v19, v0\n\tv_mov_b32_e32 v0, v19\n\tv_cndmask_b32_e64 v0, v0, v1, s0\n\tv_mov_b32_e32 v1, v18\n\tv_cndmask_b32_e64 v1, v1, v2, s0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v0, v2\n\ts_mov_b32 s0, 0xffffff1f\n\ts_mov_b32 s1, -1\n\ts_mov_b32 s2, s1\n\tv_and_b32_e64 v0, v0, s2\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1\n\tv_and_b32_e64 v1, v1, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\tv_mov_b32_e32 v18, v0\n\ts_mov_b32 s0, 5\n\tv_lshlrev_b64 v[17:18], s0, v[17:18]\n\tv_mov_b32_e32 v0, v2\n\tv_mov_b32_e32 v19, v18\n\tv_or_b32_e64 v0, v0, v19\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v17\n\tv_or_b32_e64 v17, v1, v2\n ; kill: def $vgpr17 killed $vgpr17 def $vgpr17_vgpr18 killed $exec\n\tv_mov_b32_e32 v18, v0\n\tv_mov_b32_e32 v1, v17\n\ts_mov_b32 s0, 32\n ; implicit-def: $vgpr29 : SGPR spill to VGPR lane\n\tv_writelane_b32 v29, s0, 0\n\tv_lshrrev_b64 v[17:18], s0, v[17:18]\n\tv_mov_b32_e32 v2, v17\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_hostcall_preview@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_hostcall_preview@rel32@hi+12\n\tv_mov_b32_e32 v0, 2\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v29, 0\n\tscratch_store_b32 off, v1, s33 ; 4-byte Folded Spill\n ; kill: def $vgpr1 killed $vgpr3 killed $exec\n\tscratch_load_b32 v3, off, s33 ; 4-byte Folded Reload\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v1, s1\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v3\n\tv_lshrrev_b64 v[1:2], s0, v[1:2]\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\tv_readlane_b32 s30, v28, 0\n\tv_readlane_b32 s31, v28, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v28, off, s33 offset:8 ; 4-byte Folded Reload\n\tscratch_load_b32 v29, off, s33 offset:12 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xffffffe0\n\ts_mov_b32 s33, s19\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end7:\n\t.size\t__ockl_fprintf_append_args, .Lfunc_end7-__ockl_fprintf_append_args\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 452\n; NumSgprs: 36\n; NumVgprs: 32\n; ScratchSize: 432\n; MemoryBound: 0\n\t.text\n\t.hidden\t__assert_fail ; -- Begin function __assert_fail\n\t.weak\t__assert_fail\n\t.p2align\t2\n\t.type\t__assert_fail,@function\n__assert_fail: ; @__assert_fail\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_mov_b32 s27, s33\n\ts_mov_b32 s33, s32\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v35, s33 offset:176 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v36, s33 offset:180 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v37, s33 offset:184 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xc0\n\tv_writelane_b32 v35, s30, 0\n\tv_writelane_b32 v35, s31, 1\n\tscratch_store_b32 off, v31, s33 offset:168 ; 4-byte Folded Spill\n ; implicit-def: $vgpr37 : SGPR spill to VGPR lane\n\tv_writelane_b32 v37, s6, 0\n\tv_writelane_b32 v37, s7, 1\n\tscratch_store_b32 off, v5, s33 offset:164 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v3, s33 offset:160 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v5, v2\n\tscratch_load_b32 v2, off, s33 offset:164 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v7, v0\n\tscratch_load_b32 v0, off, s33 offset:160 ; 4-byte Folded Reload\n\tv_writelane_b32 v37, s15, 2\n\tv_writelane_b32 v37, s14, 3\n\tv_writelane_b32 v37, s13, 4\n\tv_writelane_b32 v37, s12, 5\n\tv_writelane_b32 v37, s10, 6\n\tv_writelane_b32 v37, s11, 7\n\tv_writelane_b32 v37, s8, 8\n\tv_writelane_b32 v37, s9, 9\n\tv_writelane_b32 v37, s4, 10\n\tv_writelane_b32 v37, s5, 11\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v6\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v6, v0\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec\n\tv_mov_b32_e32 v8, v1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n ; implicit-def: $sgpr0_sgpr1\n\ts_mov_b64 s[0:1], src_private_base\n\ts_mov_b32 s2, 32\n\ts_lshr_b64 s[0:1], s[0:1], s2\n\ts_mov_b32 s24, s0\n\tv_writelane_b32 v37, s24, 12\n\ts_mov_b32 s20, s33\n ; kill: def $sgpr20 killed $sgpr20 def $sgpr20_sgpr21\n\ts_mov_b32 s21, s24\n\ts_mov_b64 s[0:1], s[20:21]\n\tv_writelane_b32 v37, s0, 13\n\tv_writelane_b32 v37, s1, 14\n\ts_add_i32 s0, s33, 8\n\ts_mov_b32 s18, s0\n ; kill: def $sgpr18 killed $sgpr18 def $sgpr18_sgpr19\n\ts_mov_b32 s19, s24\n\ts_mov_b64 s[0:1], s[18:19]\n\tv_writelane_b32 v37, s0, 15\n\tv_writelane_b32 v37, s1, 16\n\ts_add_i32 s0, s33, 16\n\ts_mov_b32 s2, s0\n ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3\n\ts_mov_b32 s3, s24\n\ts_mov_b64 s[0:1], s[2:3]\n\tv_writelane_b32 v37, s0, 17\n\tv_writelane_b32 v37, s1, 18\n\ts_add_i32 s1, s33, 24\n\ts_mov_b32 s0, s1\n ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1\n\ts_mov_b32 s1, s24\n\ts_mov_b64 s[16:17], s[0:1]\n\tv_writelane_b32 v37, s16, 19\n\tv_writelane_b32 v37, s17, 20\n\ts_add_i32 s17, s33, 32\n\ts_mov_b32 s16, s17\n ; kill: def $sgpr16 killed $sgpr16 def $sgpr16_sgpr17\n\ts_mov_b32 s17, s24\n\tv_writelane_b32 v37, s16, 21\n\tv_writelane_b32 v37, s17, 22\n\ts_mov_b64 s[22:23], s[16:17]\n\tv_writelane_b32 v37, s22, 23\n\tv_writelane_b32 v37, s23, 24\n\ts_add_i32 s23, s33, 0x50\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v37, s22, 25\n\tv_writelane_b32 v37, s23, 26\n\tv_writelane_b32 v37, s22, 27\n\tv_writelane_b32 v37, s23, 28\n\ts_add_i32 s23, s33, 0x58\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v37, s22, 29\n\tv_writelane_b32 v37, s23, 30\n ; implicit-def: $vgpr36 : SGPR spill to VGPR lane\n\tv_writelane_b32 v37, s22, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:148 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_writelane_b32 v36, s23, 0\n\ts_add_i32 s23, s33, 0x60\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 1\n\tv_writelane_b32 v36, s23, 2\n\ts_add_i32 s23, s33, 0x68\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 3\n\tv_writelane_b32 v36, s23, 4\n\ts_add_i32 s23, s33, 0x70\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 5\n\tv_writelane_b32 v36, s23, 6\n\ts_add_i32 s23, s33, 0x78\n\ts_mov_b32 s22, s23\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s24\n\tv_writelane_b32 v36, s22, 7\n\tv_writelane_b32 v36, s23, 8\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_mov_b32_e32 v0, s20\n\tv_mov_b32_e32 v1, s21\n\tflat_store_b64 v[0:1], v[7:8]\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tflat_store_b64 v[0:1], v[5:6]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b32 v[0:1], v4\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, s33 offset:156 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+35\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+43\n\tglobal_load_b128 v[0:3], v0, s[0:1]\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b128 off, v[0:3], s33 offset:128\n\tscratch_load_b64 v[0:1], off, s33 offset:136\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_d16_hi_b8 v[3:4], v2 offset:45\n\ts_mov_b32 s1, 24\n\tv_lshrrev_b32_e64 v5, s1, v2\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v5 offset:46\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v2 offset:43\n\ts_mov_b32 s0, 8\n\tv_lshrrev_b32_e64 v4, s0, v2\n\tv_mov_b32_e32 v2, s16\n\tv_mov_b32_e32 v3, s17\n\tflat_store_b8 v[2:3], v4 offset:44\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_d16_hi_b8 v[1:2], v0 offset:41\n\tv_lshrrev_b32_e64 v3, s1, v0\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v3 offset:42\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v0 offset:39\n\tv_lshrrev_b32_e64 v2, s0, v0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b8 v[0:1], v2 offset:40\n\tscratch_load_b64 v[0:1], off, s33 offset:128\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v2, v1\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_d16_hi_b8 v[3:4], v2 offset:37\n\tv_lshrrev_b32_e64 v5, s1, v2\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v5 offset:38\n\tv_mov_b32_e32 v3, s16\n\tv_mov_b32_e32 v4, s17\n\tflat_store_b8 v[3:4], v2 offset:35\n\tv_lshrrev_b32_e64 v4, s0, v2\n\tv_mov_b32_e32 v2, s16\n\tv_mov_b32_e32 v3, s17\n\tflat_store_b8 v[2:3], v4 offset:36\n ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_d16_hi_b8 v[1:2], v0 offset:33\n\tv_lshrrev_b32_e64 v3, s1, v0\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v3 offset:34\n\tv_mov_b32_e32 v1, s16\n\tv_mov_b32_e32 v2, s17\n\tflat_store_b8 v[1:2], v0 offset:31\n\tv_lshrrev_b32_e64 v2, s0, v0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b8 v[0:1], v2 offset:32\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+20\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+28\n\ts_load_b128 s[0:3], s[0:1], 0x0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v5, s3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b128 v[0:1], v[2:5] offset:16\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __const.__assert_fail.fmt@rel32@lo+4\n\ts_addc_u32 s1, s1, __const.__assert_fail.fmt@rel32@hi+12\n\ts_load_b128 s[0:3], s[0:1], 0x0\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v5, s3\n\tv_mov_b32_e32 v4, s2\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b128 v[0:1], v[2:5]\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_stderr_begin@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_stderr_begin@rel32@hi+12\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v2, off, s33 offset:156 ; 4-byte Folded Reload\n\tv_readlane_b32 s2, v37, 25\n\tv_readlane_b32 s3, v37, 26\n\tv_readlane_b32 s0, v37, 29\n\tv_readlane_b32 s1, v37, 30\n\tv_mov_b32_e32 v3, v0\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr4\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b64 v[0:1], v[3:4]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0)\n\tflat_store_b32 v[0:1], v2\n; %bb.1:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 23\n\tv_readlane_b32 s1, v36, 24\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s3, v37, 2\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 9\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_2: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s3, v37, 2\n\tv_readlane_b32 s0, v37, 10\n\tv_readlane_b32 s1, v37, 9\n\tv_writelane_b32 v37, s1, 11\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 12\n\tv_writelane_b32 v37, s0, 13\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 14\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_4\n; %bb.3: ; in Loop: Header=BB8_2 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 12\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 13\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_4: ; in Loop: Header=BB8_2 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 14\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 11\n\tv_readlane_b32 s1, v37, 13\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 10\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 9\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 15\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_2\n; %bb.5:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 15\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.6:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 23\n\tv_readlane_b32 s3, v36, 24\n\tv_readlane_b32 s4, v37, 1\n\tv_readlane_b32 s5, v37, 2\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, s2\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.7:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 23\n\tv_readlane_b32 s1, v37, 24\n\tv_readlane_b32 s2, v37, 31\n\tv_readlane_b32 s3, v36, 0\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v5, v4\n\tv_mov_b32_e32 v6, v0\n\ts_mov_b32 s3, 32\n\ts_lshr_b64 s[16:17], s[0:1], s3\n\ts_mov_b32 s2, s16\n\tv_lshrrev_b64 v[0:1], s3, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[5:6], s3, v[5:6]\n ; kill: def $vgpr5 killed $vgpr5 killed $vgpr5_vgpr6 killed $exec\n\ts_mov_b32 s3, s0\n\tv_mov_b32_e32 v0, v2\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\tv_mov_b32_e32 v2, s3\n\tv_mov_b32_e32 v3, s2\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.8:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 3\n\tv_readlane_b32 s1, v37, 4\n\tv_readlane_b32 s2, v36, 15\n\tv_readlane_b32 s3, v36, 16\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 16\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_9: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 3\n\tv_readlane_b32 s3, v37, 4\n\tv_readlane_b32 s0, v37, 17\n\tv_readlane_b32 s1, v37, 16\n\tv_writelane_b32 v37, s1, 18\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 19\n\tv_writelane_b32 v37, s0, 20\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 21\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_11\n; %bb.10: ; in Loop: Header=BB8_9 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 19\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 20\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_11: ; in Loop: Header=BB8_9 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 21\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 18\n\tv_readlane_b32 s1, v37, 20\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 17\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 16\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 22\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_9\n; %bb.12:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 22\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.13:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 15\n\tv_readlane_b32 s3, v36, 16\n\tv_readlane_b32 s4, v37, 3\n\tv_readlane_b32 s5, v37, 4\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.14:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 15\n\tv_readlane_b32 s3, v37, 16\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_writelane_b32 v36, s0, 23\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\tscratch_store_b32 off, v6, s33 offset:172 ; 4-byte Folded Spill\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tscratch_load_b32 v17, off, s33 offset:172 ; 4-byte Folded Reload\n\tv_readlane_b32 s2, v37, 17\n\tv_readlane_b32 s3, v37, 18\n\tv_readlane_b32 s0, v36, 23\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[4:5], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v3, v[0:1]\n\ts_waitcnt vmcnt(1) lgkmcnt(1)\n\tv_lshrrev_b64 v[0:1], s0, v[4:5]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v4\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_args@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_args@rel32@hi+12\n\tv_mov_b32_e32 v2, 1\n\tv_mov_b32_e32 v4, v17\n\tv_mov_b32_e32 v5, v17\n\tv_mov_b32_e32 v6, v17\n\tv_mov_b32_e32 v7, v17\n\tv_mov_b32_e32 v8, v17\n\tv_mov_b32_e32 v9, v17\n\tv_mov_b32_e32 v10, v17\n\tv_mov_b32_e32 v11, v17\n\tv_mov_b32_e32 v12, v17\n\tv_mov_b32_e32 v13, v17\n\tv_mov_b32_e32 v14, v17\n\tv_mov_b32_e32 v15, v17\n\tv_mov_b32_e32 v16, v17\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.15:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 5\n\tv_readlane_b32 s1, v37, 6\n\tv_readlane_b32 s2, v36, 19\n\tv_readlane_b32 s3, v36, 20\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 24\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_16: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v37, 5\n\tv_readlane_b32 s3, v37, 6\n\tv_readlane_b32 s0, v37, 25\n\tv_readlane_b32 s1, v37, 24\n\tv_writelane_b32 v37, s1, 26\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 27\n\tv_writelane_b32 v37, s0, 28\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 29\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_18\n; %bb.17: ; in Loop: Header=BB8_16 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 27\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 28\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_18: ; in Loop: Header=BB8_16 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 29\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 26\n\tv_readlane_b32 s1, v37, 28\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 25\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 24\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 30\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_16\n; %bb.19:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 30\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.20:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 19\n\tv_readlane_b32 s3, v36, 20\n\tv_readlane_b32 s4, v37, 5\n\tv_readlane_b32 s5, v37, 6\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.21:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 19\n\tv_readlane_b32 s3, v37, 20\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 0\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v37, 27\n\tv_readlane_b32 s1, v37, 28\n\tv_mov_b32_e32 v2, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n; %bb.22:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 7\n\tv_readlane_b32 s1, v37, 8\n\tv_readlane_b32 s2, v36, 13\n\tv_readlane_b32 s3, v36, 14\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v37, s0, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_23: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v36, 7\n\tv_readlane_b32 s3, v36, 8\n ; implicit-def: $vgpr37 : SGPR spill to VGPR lane\n\tv_readlane_b32 s0, v37, 0\n\tv_readlane_b32 s1, v36, 31\n\tv_writelane_b32 v37, s1, 1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_mov_b64 s[6:7], 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mov_b32_e32 v3, v0\n\ts_mov_b32 s4, s6\n\tv_mov_b32_e32 v2, v1\n\ts_mov_b32 s1, s7\n\tv_add_co_u32 v4, s4, v3, s4\n\tv_add_co_ci_u32_e64 v2, s1, v2, s1, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_store_b64 v[2:3], v[4:5]\n\tflat_load_u8 v0, v[0:1]\n\ts_mov_b32 s1, 0\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 2\n\tv_writelane_b32 v37, s0, 3\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v37, s0, 4\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB8_25\n; %bb.24: ; in Loop: Header=BB8_23 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 2\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v37, s0, 3\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n.LBB8_25: ; in Loop: Header=BB8_23 Depth=1\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v37, 1\n\tv_readlane_b32 s1, v37, 3\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v37, s1, 0\n\ts_mov_b32 s1, s0\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v36, s1, 31\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v36, s33 offset:144 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v37, s1, 5\n\ts_or_saveexec_b32 s26, -1\n\tscratch_store_b32 off, v37, s33 offset:152 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s26\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB8_23\n; %bb.26:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:152 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v37, 5\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.27:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(1)\n\tv_readlane_b32 s0, v36, 31\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v37, 0\n\tv_readlane_b32 s2, v36, 13\n\tv_readlane_b32 s3, v36, 14\n\tv_readlane_b32 s4, v37, 7\n\tv_readlane_b32 s5, v37, 8\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v1, s2\n\tv_mov_b32_e32 v2, s3\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_sub_nc_u32_e64 v2, v0, v1\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n; %bb.28:\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v36, off, s33 offset:144 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_or_saveexec_b32 s26, -1\n\tscratch_load_b32 v37, off, s33 offset:148 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s26\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s15, v37, 2\n\tv_readlane_b32 s14, v37, 3\n\tv_readlane_b32 s13, v37, 4\n\tv_readlane_b32 s12, v37, 5\n\tv_readlane_b32 s10, v37, 6\n\tv_readlane_b32 s11, v37, 7\n\tv_readlane_b32 s8, v37, 8\n\tv_readlane_b32 s9, v37, 9\n\tv_readlane_b32 s6, v37, 0\n\tv_readlane_b32 s7, v37, 1\n\tv_readlane_b32 s4, v37, 10\n\tv_readlane_b32 s5, v37, 11\n\tv_readlane_b32 s0, v37, 31\n\tv_readlane_b32 s1, v36, 0\n\tv_readlane_b32 s2, v37, 13\n\tv_readlane_b32 s3, v37, 14\n\tv_readlane_b32 s16, v37, 27\n\tv_readlane_b32 s17, v37, 28\n\tscratch_load_b32 v31, off, s33 offset:168 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\tflat_load_b64 v[8:9], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v4, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v4\n\tv_mov_b32_e32 v10, v4\n\tv_mov_b32_e32 v11, v0\n\ts_mov_b32 s0, 32\n\tv_lshrrev_b64 v[0:1], s0, v[8:9]\n\tv_mov_b32_e32 v1, v0\n\tv_lshrrev_b64 v[2:3], s0, v[6:7]\n\tv_mov_b32_e32 v3, v2\n\tv_lshrrev_b64 v[10:11], s0, v[10:11]\n\tv_mov_b32_e32 v5, v10\n\tv_mov_b32_e32 v0, v8\n\tv_mov_b32_e32 v2, v6\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_fprintf_append_string_n@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_fprintf_append_string_n@rel32@hi+12\n\tv_mov_b32_e32 v6, 1\n\ts_swappc_b64 s[30:31], s[0:1]\n\ts_cbranch_execnz .LBB8_30\n; %bb.29:\n\tv_readlane_b32 s30, v35, 0\n\tv_readlane_b32 s31, v35, 1\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v35, off, s33 offset:176 ; 4-byte Folded Reload\n\tscratch_load_b32 v36, off, s33 offset:180 ; 4-byte Folded Reload\n\tscratch_load_b32 v37, off, s33 offset:184 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_add_i32 s32, s32, 0xffffff40\n\ts_mov_b32 s33, s27\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.LBB8_30:\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB8_31: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB8_31\n.Lfunc_end8:\n\t.size\t__assert_fail, .Lfunc_end8-__assert_fail\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 6148\n; NumSgprs: 36\n; NumVgprs: 38\n; ScratchSize: 1312\n; MemoryBound: 0\n\t.text\n\t.hidden\t__assertfail ; -- Begin function __assertfail\n\t.weak\t__assertfail\n\t.p2align\t2\n\t.type\t__assertfail,@function\n__assertfail: ; @__assertfail\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_cbranch_execnz .LBB9_2\n; %bb.1:\n\ts_setpc_b64 s[30:31]\n.LBB9_2:\n\ts_trap 2\n\ts_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)\n\ts_mov_b32 ttmp2, m0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s0, s0, 0x3ff\n\ts_or_b32 s0, s0, 0x400\n\ts_mov_b32 m0, s0\n\ts_sendmsg sendmsg(MSG_INTERRUPT)\n\ts_mov_b32 m0, ttmp2\n.LBB9_3: ; =>This Inner Loop Header: Depth=1\n\ts_sethalt 5\n\ts_branch .LBB9_3\n.Lfunc_end9:\n\t.size\t__assertfail, .Lfunc_end9-__assertfail\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 64\n; NumSgprs: 32\n; NumVgprs: 0\n; ScratchSize: 0\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_get_group_id\n\t.type\t__ockl_get_group_id,@function\n__ockl_get_group_id: ; @__ockl_get_group_id\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v2, s32 offset:32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill\n ; implicit-def: $vgpr2 : SGPR spill to VGPR lane\n\tv_writelane_b32 v2, s14, 0\n\tv_writelane_b32 v2, s13, 1\n\tv_writelane_b32 v2, s12, 2\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n; %bb.1:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v2, s1, 3\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_4\n; %bb.2:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v2, s1, 4\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_7\n; %bb.3:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 5\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_10\n\ts_branch .LBB10_9\n.LBB10_4:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 3\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 6\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB10_13\n; %bb.5:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 7\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB10_12\n; %bb.6:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 2\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_branch .LBB10_12\n.LBB10_7:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 4\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:12 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 8\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB10_11\n; %bb.8:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 1\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_branch .LBB10_11\n.LBB10_9:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 0\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n.LBB10_10:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 5\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:16 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_branch .LBB10_7\n.LBB10_11:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 8\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill\n\ts_branch .LBB10_4\n.LBB10_12:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 7\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:24 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n.LBB10_13:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 6\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:20 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v1, 0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v2, off, s32 offset:32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end10:\n\t.size\t__ockl_get_group_id, .Lfunc_end10-__ockl_get_group_id\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 988\n; NumSgprs: 33\n; NumVgprs: 3\n; ScratchSize: 40\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_get_local_size\n\t.type\t__ockl_get_local_size,@function\n__ockl_get_local_size: ; @__ockl_get_local_size\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v4, s32 offset:104 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill\n ; implicit-def: $vgpr4 : SGPR spill to VGPR lane\n\tv_writelane_b32 v4, s14, 0\n\tv_writelane_b32 v4, s13, 1\n\tv_writelane_b32 v4, s12, 2\n\tv_writelane_b32 v4, s8, 3\n\tv_writelane_b32 v4, s9, 4\n\tv_writelane_b32 v4, s4, 5\n\tv_writelane_b32 v4, s5, 6\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n; %bb.1:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:8 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v4, s1, 7\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_4\n; %bb.2:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr2_sgpr3\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:16 ; 8-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v4, s1, 8\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_10\n; %bb.3:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 1\n\tv_mov_b32_e32 v0, 1\n\tv_mov_b32_e32 v1, 0\n\tscratch_store_b64 off, v[0:1], s32 offset:24 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v4, s0, 9\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_20\n\ts_branch .LBB11_15\n.LBB11_4:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 7\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:8 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:32 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v4, s0, 10\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB11_25\n; %bb.5:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b64 s[2:3], 1\n\tv_mov_b32_e32 v0, 1\n\tv_mov_b32_e32 v1, 0\n\tscratch_store_b64 off, v[0:1], s32 offset:40 ; 8-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v4, s0, 11\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB11_24\n; %bb.6:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n ; implicit-def: $sgpr2_sgpr3\n\ts_mov_b32 s4, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s4\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:48 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v4, s0, 12\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB11_9\n.LBB11_7:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 12\n\tscratch_load_b64 v[0:1], off, s32 offset:48 ; 8-byte Folded Reload\n\tv_cndmask_b32_e64 v2, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v2, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n ; kill: def $vgpr0_vgpr1 killed $vgpr0_vgpr1 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:56 ; 8-byte Folded Spill\n\ts_cbranch_vccnz .LBB11_23\n; %bb.8:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v4, 2\n\tv_readlane_b32 s2, v4, 5\n\tv_readlane_b32 s3, v4, 6\n\tv_mov_b32_e32 v0, 0\n\tglobal_load_u16 v1, v0, s[2:3] offset:4\n\ts_load_b32 s0, s[2:3], 0xc\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v0, s1, v1\n\ts_waitcnt lgkmcnt(0)\n\tv_sub_nc_u32_e64 v0, s0, v0\n ; implicit-def: $sgpr0\n\tv_min_u32_e64 v0, v0, v1\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr0_sgpr1\n\tscratch_store_b64 off, v[0:1], s32 offset:56 ; 8-byte Folded Spill\n\ts_branch .LBB11_23\n.LBB11_9:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 3\n\tv_readlane_b32 s1, v4, 4\n\tv_readlane_b32 s2, v4, 2\n\ts_load_b32 s3, s[0:1], 0x0\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_u32 s2, s3\n\ts_mov_b32 s3, 18\n\ts_mov_b32 s2, 12\n\ts_cselect_b32 s2, s2, s3\n\tv_mov_b32_e32 v0, s2\n\tglobal_load_u16 v0, v0, s[0:1]\n\ts_mov_b32 s0, 0xffff\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n ; implicit-def: $sgpr0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr2_sgpr3\n\tscratch_store_b64 off, v[0:1], s32 offset:48 ; 8-byte Folded Spill\n\tv_writelane_b32 v4, s0, 12\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB11_7\n.LBB11_10:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 8\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:16 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:64 ; 8-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v4, s0, 13\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB11_22\n; %bb.11:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n ; implicit-def: $sgpr2_sgpr3\n\ts_mov_b32 s4, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s4\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:72 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v4, s0, 14\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB11_14\n.LBB11_12:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 14\n\tscratch_load_b64 v[0:1], off, s32 offset:72 ; 8-byte Folded Reload\n\tv_cndmask_b32_e64 v2, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v2, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n ; kill: def $vgpr0_vgpr1 killed $vgpr0_vgpr1 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:80 ; 8-byte Folded Spill\n\ts_cbranch_vccnz .LBB11_21\n; %bb.13:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v4, 1\n\tv_readlane_b32 s2, v4, 5\n\tv_readlane_b32 s3, v4, 6\n\tv_mov_b32_e32 v0, 0\n\tglobal_load_u16 v1, v0, s[2:3] offset:6\n\ts_load_b32 s0, s[2:3], 0x10\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v0, s1, v1\n\ts_waitcnt lgkmcnt(0)\n\tv_sub_nc_u32_e64 v0, s0, v0\n ; implicit-def: $sgpr0\n\tv_min_u32_e64 v0, v0, v1\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr0_sgpr1\n\tscratch_store_b64 off, v[0:1], s32 offset:80 ; 8-byte Folded Spill\n\ts_branch .LBB11_21\n.LBB11_14:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 3\n\tv_readlane_b32 s1, v4, 4\n\tv_readlane_b32 s2, v4, 1\n\ts_load_b32 s3, s[0:1], 0x4\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_u32 s2, s3\n\ts_mov_b32 s3, 20\n\ts_mov_b32 s2, 14\n\ts_cselect_b32 s2, s2, s3\n\tv_mov_b32_e32 v0, s2\n\tglobal_load_u16 v0, v0, s[0:1]\n\ts_mov_b32 s0, 0xffff\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n ; implicit-def: $sgpr0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr2_sgpr3\n\tscratch_store_b64 off, v[0:1], s32 offset:72 ; 8-byte Folded Spill\n\tv_writelane_b32 v4, s0, 14\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB11_12\n.LBB11_15:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __oclc_ABI_version@rel32@lo+4\n\ts_addc_u32 s1, s1, __oclc_ABI_version@rel32@hi+12\n\ts_load_b32 s1, s[0:1], 0x0\n\ts_mov_b32 s0, -1\n ; implicit-def: $sgpr2_sgpr3\n\ts_mov_b32 s4, 0x1f3\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_gt_i32 s1, s4\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tscratch_store_b64 off, v[0:1], s32 offset:88 ; 8-byte Folded Spill\n\ts_waitcnt vmcnt(0)\n\tv_writelane_b32 v4, s0, 15\n\ts_mov_b32 s7, exec_lo\n\ts_mov_b32 exec_lo, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_cbranch_scc1 .LBB11_18\n.LBB11_16:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 15\n\tscratch_load_b64 v[0:1], off, s32 offset:88 ; 8-byte Folded Reload\n\tv_cndmask_b32_e64 v2, 0, 1, s0\n\ts_mov_b32 s0, 1\n ; implicit-def: $sgpr1\n\tv_cmp_ne_u32_e64 s0, v2, s0\n\ts_and_b32 vcc_lo, exec_lo, s0\n ; kill: def $vgpr0_vgpr1 killed $vgpr0_vgpr1 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:96 ; 8-byte Folded Spill\n\ts_cbranch_vccnz .LBB11_19\n; %bb.17:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s1, v4, 0\n\tv_readlane_b32 s2, v4, 5\n\tv_readlane_b32 s3, v4, 6\n\tv_mov_b32_e32 v0, 0\n\tglobal_load_u16 v1, v0, s[2:3] offset:8\n\ts_load_b32 s0, s[2:3], 0x14\n ; implicit-def: $sgpr2\n\ts_waitcnt vmcnt(0)\n\tv_mul_lo_u32 v0, s1, v1\n\ts_waitcnt lgkmcnt(0)\n\tv_sub_nc_u32_e64 v0, s0, v0\n ; implicit-def: $sgpr0\n\tv_min_u32_e64 v0, v0, v1\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, 0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr0_sgpr1\n\tscratch_store_b64 off, v[0:1], s32 offset:96 ; 8-byte Folded Spill\n\ts_branch .LBB11_19\n.LBB11_18:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 3\n\tv_readlane_b32 s1, v4, 4\n\tv_readlane_b32 s2, v4, 0\n\ts_load_b32 s3, s[0:1], 0x8\n\ts_waitcnt lgkmcnt(0)\n\ts_cmp_lt_u32 s2, s3\n\ts_mov_b32 s3, 22\n\ts_mov_b32 s2, 16\n\ts_cselect_b32 s2, s2, s3\n\tv_mov_b32_e32 v0, s2\n\tglobal_load_u16 v0, v0, s[0:1]\n\ts_mov_b32 s0, 0xffff\n ; implicit-def: $sgpr1\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n ; implicit-def: $sgpr0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr2_sgpr3\n\tscratch_store_b64 off, v[0:1], s32 offset:88 ; 8-byte Folded Spill\n\tv_writelane_b32 v4, s0, 15\n\ts_or_saveexec_b32 s7, -1\n\tscratch_store_b32 off, v4, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s7\n\ts_branch .LBB11_16\n.LBB11_19:\n\tscratch_load_b64 v[0:1], off, s32 offset:96 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:24 ; 8-byte Folded Spill\n.LBB11_20:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 9\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:24 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:16 ; 8-byte Folded Spill\n\ts_branch .LBB11_10\n.LBB11_21:\n\tscratch_load_b64 v[0:1], off, s32 offset:80 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:64 ; 8-byte Folded Spill\n.LBB11_22:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 13\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:64 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:8 ; 8-byte Folded Spill\n\ts_branch .LBB11_4\n.LBB11_23:\n\tscratch_load_b64 v[0:1], off, s32 offset:56 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:40 ; 8-byte Folded Spill\n.LBB11_24:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 11\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[0:1], off, s32 offset:40 ; 8-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b64 off, v[0:1], s32 offset:32 ; 8-byte Folded Spill\n.LBB11_25:\n\ts_or_saveexec_b32 s7, -1\n\tscratch_load_b32 v4, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s7\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v4, 10\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b64 v[2:3], off, s32 offset:32 ; 8-byte Folded Reload\n\ts_mov_b32 s0, 32\n\ts_waitcnt vmcnt(0)\n\tv_lshrrev_b64 v[0:1], s0, v[2:3]\n\tv_mov_b32_e32 v1, v0\n\tv_mov_b32_e32 v0, v2\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v4, off, s32 offset:104 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end11:\n\t.size\t__ockl_get_local_size, .Lfunc_end11-__ockl_get_local_size\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 2384\n; NumSgprs: 35\n; NumVgprs: 5\n; ScratchSize: 112\n; MemoryBound: 0\n\t.text\n\t.p2align\t2 ; -- Begin function __ockl_get_local_id\n\t.type\t__ockl_get_local_id,@function\n__ockl_get_local_id: ; @__ockl_get_local_id\n; %bb.0:\n\ts_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_store_b32 off, v2, s32 offset:36 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s0\n\tscratch_store_b32 off, v31, s32 offset:8 ; 4-byte Folded Spill\n\tscratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill\n; %bb.1:\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n ; implicit-def: $vgpr2 : SGPR spill to VGPR lane\n\tv_writelane_b32 v2, s1, 0\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_4\n; %bb.2:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, s0\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v0, s1\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_mov_b32 s1, exec_lo\n\ts_and_b32 s0, s1, s0\n\ts_xor_b32 s1, s0, s1\n\tv_writelane_b32 v2, s1, 1\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_7\n; %bb.3:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\ts_mov_b32 s0, 0\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 2\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_10\n\ts_branch .LBB12_9\n.LBB12_4:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 0\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:12 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 3\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB12_13\n; %bb.5:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\tscratch_load_b32 v0, off, s32 offset:4 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0\n\ts_waitcnt vmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, s0\n\tv_mov_b32_e32 v0, s0\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v2, s0, 4\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB12_12\n; %bb.6:\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_mov_b32 s0, 0x3ff\n\ts_waitcnt vmcnt(0)\n\tv_and_b32_e64 v0, v0, s0\n\tscratch_store_b32 off, v0, s32 offset:28 ; 4-byte Folded Spill\n\ts_branch .LBB12_12\n.LBB12_7:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 1\n\ts_or_saveexec_b32 s0, s0\n\tscratch_load_b32 v0, off, s32 offset:16 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:32 ; 4-byte Folded Spill\n\ts_and_b32 s0, exec_lo, s0\n\tv_writelane_b32 v2, s0, 5\n\ts_or_saveexec_b32 s3, -1\n\tscratch_store_b32 off, v2, s32 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s3\n\ts_xor_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execz .LBB12_11\n; %bb.8:\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_bfe_u32 v0, v0, 10, 10\n\tscratch_store_b32 off, v0, s32 offset:32 ; 4-byte Folded Spill\n\ts_branch .LBB12_11\n.LBB12_9:\n\tscratch_load_b32 v0, off, s32 offset:8 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tv_bfe_u32 v0, v0, 20, 10\n\tscratch_store_b32 off, v0, s32 offset:20 ; 4-byte Folded Spill\n.LBB12_10:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 2\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:20 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:16 ; 4-byte Folded Spill\n\ts_branch .LBB12_7\n.LBB12_11:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 5\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:32 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill\n\ts_branch .LBB12_4\n.LBB12_12:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 4\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:28 ; 4-byte Folded Reload\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v0, s32 offset:24 ; 4-byte Folded Spill\n.LBB12_13:\n\ts_or_saveexec_b32 s3, -1\n\tscratch_load_b32 v2, off, s32 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s3\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v2, 3\n\ts_or_b32 exec_lo, exec_lo, s0\n\tscratch_load_b32 v0, off, s32 offset:24 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v1, 0\n\ts_xor_saveexec_b32 s0, -1\n\tscratch_load_b32 v2, off, s32 offset:36 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s0\n\ts_waitcnt vmcnt(0)\n\ts_setpc_b64 s[30:31]\n.Lfunc_end12:\n\t.size\t__ockl_get_local_id, .Lfunc_end12-__ockl_get_local_id\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Function info:\n; codeLenInByte = 912\n; NumSgprs: 33\n; NumVgprs: 32\n; ScratchSize: 44\n; MemoryBound: 0\n\t.text\n\t.protected\t_Z15initializeNodesP9BTreeNode ; -- Begin function _Z15initializeNodesP9BTreeNode\n\t.globl\t_Z15initializeNodesP9BTreeNode\n\t.p2align\t8\n\t.type\t_Z15initializeNodesP9BTreeNode,@function\n_Z15initializeNodesP9BTreeNode: ; @_Z15initializeNodesP9BTreeNode\n; %bb.0:\n\ts_mov_b32 s32, 0x50\n ; implicit-def: $vgpr8 : SGPR spill to VGPR lane\n\tv_writelane_b32 v8, s15, 0\n\ts_mov_b32 s6, s14\n\tv_readlane_b32 s14, v8, 0\n\tv_writelane_b32 v8, s6, 1\n\ts_mov_b32 s12, s13\n\tv_readlane_b32 s13, v8, 1\n\tv_writelane_b32 v8, s12, 2\n\ts_mov_b64 s[10:11], s[4:5]\n\tv_writelane_b32 v8, s10, 3\n\tv_writelane_b32 v8, s11, 4\n\tv_writelane_b32 v8, s2, 5\n\tv_writelane_b32 v8, s3, 6\n\ts_mov_b64 s[4:5], s[0:1]\n\tv_readlane_b32 s0, v8, 5\n\tv_readlane_b32 s1, v8, 6\n\tv_writelane_b32 v8, s4, 7\n\tv_writelane_b32 v8, s5, 8\n\tv_mov_b32_e32 v31, v0\n\tscratch_store_b32 off, v31, off offset:72 ; 4-byte Folded Spill\n\ts_load_b64 s[8:9], s[0:1], 0x0\n\ts_mov_b64 s[2:3], src_private_base\n\ts_mov_b32 s6, 32\n\ts_lshr_b64 s[2:3], s[2:3], s6\n\ts_mov_b32 s15, s2\n\ts_mov_b32 s6, 32\n ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7\n\ts_mov_b32 s7, s15\n\ts_mov_b32 s2, 40\n ; kill: def $sgpr2 killed $sgpr2 def $sgpr2_sgpr3\n\ts_mov_b32 s3, s15\n\ts_mov_b64 s[16:17], s[2:3]\n\tv_writelane_b32 v8, s16, 9\n\tv_writelane_b32 v8, s17, 10\n\ts_mov_b32 s16, 48\n ; kill: def $sgpr16 killed $sgpr16 def $sgpr16_sgpr17\n\ts_mov_b32 s17, s15\n\tv_writelane_b32 v8, s16, 11\n\tv_writelane_b32 v8, s17, 12\n\tv_writelane_b32 v8, s16, 13\n\tv_writelane_b32 v8, s17, 14\n\ts_mov_b32 s16, 52\n ; kill: def $sgpr16 killed $sgpr16 def $sgpr16_sgpr17\n\ts_mov_b32 s17, s15\n\tv_writelane_b32 v8, s16, 15\n\tv_writelane_b32 v8, s17, 16\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v2, s8\n\tv_mov_b32_e32 v3, s9\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\ts_mov_b64 s[6:7], 8\n\ts_mov_b32 s2, s0\n\ts_mov_b32 s0, s1\n\ts_mov_b32 s3, s6\n\ts_mov_b32 s1, s7\n\ts_add_u32 s8, s2, s3\n\ts_addc_u32 s0, s0, s1\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s0\n\tv_writelane_b32 v8, s8, 17\n\tv_writelane_b32 v8, s9, 18\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_group_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_group_id@rel32@hi+12\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, off offset:68 ; 4-byte Folded Spill\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:72 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v8, 0\n\tv_readlane_b32 s13, v8, 1\n\tv_readlane_b32 s12, v8, 2\n\tv_readlane_b32 s10, v8, 3\n\tv_readlane_b32 s11, v8, 4\n\tv_readlane_b32 s8, v8, 17\n\tv_readlane_b32 s9, v8, 18\n\tv_readlane_b32 s4, v8, 7\n\tv_readlane_b32 s5, v8, 8\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:68 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:76 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:76 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v1, off offset:60 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_size@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_size@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:72 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v8, 0\n\tv_readlane_b32 s13, v8, 1\n\tv_readlane_b32 s12, v8, 2\n\tv_readlane_b32 s10, v8, 3\n\tv_readlane_b32 s11, v8, 4\n\tv_readlane_b32 s4, v8, 7\n\tv_readlane_b32 s5, v8, 8\n\tv_readlane_b32 s8, v8, 17\n\tv_readlane_b32 s9, v8, 18\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:68 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:64 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:64 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v3, v1\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_id@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v2, off, off offset:60 ; 4-byte Folded Reload\n\tv_readlane_b32 s0, v8, 11\n\tv_readlane_b32 s1, v8, 12\n\tv_mov_b32_e32 v4, v1\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v4\n\tv_mov_b32_e32 v4, v0\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v0, s2\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[0:1], s2, v2, v3, v[4:5]\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v0, v[0:1]\n\ts_mov_b32 s0, 0x400\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_lt_i32_e64 s1, v0, s0\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v8, s0, 19\n\ts_or_saveexec_b32 s18, -1\n\tscratch_store_b32 off, v8, off offset:56 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s18\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB13_2\n; %bb.1:\n\ts_or_saveexec_b32 s18, -1\n\tscratch_load_b32 v8, off, off offset:56 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s18\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v8, 15\n\tv_readlane_b32 s1, v8, 16\n\tv_readlane_b32 s2, v8, 13\n\tv_readlane_b32 s3, v8, 14\n\tv_readlane_b32 s4, v8, 9\n\tv_readlane_b32 s5, v8, 10\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v0, v[3:4]\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mad_i64_i32 v[3:4], s2, v0, s2, 0\n\tv_mov_b32_e32 v6, v3\n\ts_mov_b32 s2, 0\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v0\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v3, v4\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v5, s2\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[4:5], s2, v[3:4]\n\tv_mov_b32_e32 v3, v5\n\tv_or_b32_e64 v0, v0, v3\n\tv_mov_b32_e32 v3, v6\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n\tv_or_b32_e64 v4, v3, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s2, v0, v3\n\tv_add_co_ci_u32_e64 v2, s2, v1, v2, s2\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, 0\n\tflat_store_b32 v[0:1], v2 offset:20\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr1\n\tv_writelane_b32 v8, s0, 20\n\ts_or_saveexec_b32 s18, -1\n\tscratch_store_b32 off, v8, off offset:56 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s18\n\ts_branch .LBB13_3\n.LBB13_2:\n\ts_or_saveexec_b32 s18, -1\n\tscratch_load_b32 v8, off, off offset:56 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s18\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v8, 19\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_branch .LBB13_9\n.LBB13_3: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s18, -1\n\tscratch_load_b32 v8, off, off offset:56 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s18\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v8, 15\n\tv_readlane_b32 s3, v8, 16\n\tv_readlane_b32 s0, v8, 21\n\tv_readlane_b32 s1, v8, 20\n\tv_writelane_b32 v8, s1, 22\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\ts_mov_b32 s1, 2\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_lt_i32_e64 s1, v0, s1\n\ts_mov_b32 s2, -1\n\ts_or_b32 s0, s0, exec_lo\n\tv_writelane_b32 v8, s0, 23\n\tv_writelane_b32 v8, s0, 24\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v8, s0, 25\n\ts_or_saveexec_b32 s18, -1\n\tscratch_store_b32 off, v8, off offset:56 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s18\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB13_5\n; %bb.4: ; in Loop: Header=BB13_3 Depth=1\n\ts_or_saveexec_b32 s18, -1\n\tscratch_load_b32 v8, off, off offset:56 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s18\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v8, 15\n\tv_readlane_b32 s3, v8, 16\n\tv_readlane_b32 s6, v8, 13\n\tv_readlane_b32 s7, v8, 14\n\tv_readlane_b32 s8, v8, 9\n\tv_readlane_b32 s9, v8, 10\n\tv_mov_b32_e32 v0, s8\n\tv_mov_b32_e32 v1, s9\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tflat_load_b32 v0, v[0:1]\n\ts_mov_b32 s5, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mad_i64_i32 v[1:2], s0, v0, s5, 0\n\tv_mov_b32_e32 v4, v1\n\ts_mov_b32 s4, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v0, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v0, v5\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v3, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n\ts_mov_b32 s1, 32\n\tv_lshlrev_b64 v[2:3], s1, v[1:2]\n\tv_mov_b32_e32 v1, v3\n\tv_or_b32_e64 v0, v0, v1\n\tv_mov_b32_e32 v1, v4\n ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec\n\tv_or_b32_e64 v4, v1, v2\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v1, v6\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v1, s0, v1, v3\n\tv_add_co_ci_u32_e64 v0, s0, v0, v2, s0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\ts_mov_b32 s0, 2\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s10, v0, v3\n\tv_add_co_ci_u32_e64 v2, s10, v1, v2, s10\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, 0\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s8\n\tv_mov_b32_e32 v1, s9\n\tflat_load_b64 v[6:7], v[0:1]\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mad_i64_i32 v[1:2], s5, v0, s5, 0\n\tv_mov_b32_e32 v4, v1\n ; implicit-def: $sgpr5\n\tv_mov_b32_e32 v0, s4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v0, v5\n\tv_mov_b32_e32 v1, v2\n ; implicit-def: $sgpr4\n ; implicit-def: $sgpr5\n ; implicit-def: $sgpr5\n\tv_mov_b32_e32 v3, s4\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n\tv_lshlrev_b64 v[2:3], s1, v[1:2]\n\tv_mov_b32_e32 v1, v3\n\tv_or_b32_e64 v0, v0, v1\n\tv_mov_b32_e32 v1, v4\n ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec\n\tv_or_b32_e64 v4, v1, v2\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v1, v6\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v1, s1, v1, v3\n\tv_add_co_ci_u32_e64 v0, s1, v0, v2, s1\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s0, v0, v3\n\tv_add_co_ci_u32_e64 v2, s0, v1, v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, -1\n\tflat_store_b32 v[0:1], v2 offset:8\n\ts_branch .LBB13_6\n.LBB13_5: ; in Loop: Header=BB13_3 Depth=1\n\ts_or_saveexec_b32 s18, -1\n\tscratch_load_b32 v8, off, off offset:56 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s18\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v8, 25\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s2, v8, 22\n\tv_readlane_b32 s1, v8, 24\n\ts_mov_b32 s0, s1\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s2\n\tv_writelane_b32 v8, s1, 21\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v8, s1, 20\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v8, s1, 26\n\ts_or_saveexec_b32 s18, -1\n\tscratch_store_b32 off, v8, off offset:56 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s18\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB13_3\n\ts_branch .LBB13_7\n.LBB13_6: ; in Loop: Header=BB13_3 Depth=1\n\ts_or_saveexec_b32 s18, -1\n\tscratch_load_b32 v8, off, off offset:56 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s18\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v8, 23\n\tv_readlane_b32 s2, v8, 15\n\tv_readlane_b32 s3, v8, 16\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\ts_mov_b32 s1, 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v2, v0, s1\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_store_b32 v[0:1], v2\n\ts_mov_b32 s1, 0\n\ts_and_not1_b32 s0, s0, exec_lo\n\tv_writelane_b32 v8, s0, 24\n\ts_or_saveexec_b32 s18, -1\n\tscratch_store_b32 off, v8, off offset:56 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s18\n\ts_branch .LBB13_5\n.LBB13_7:\n\ts_or_saveexec_b32 s18, -1\n\tscratch_load_b32 v8, off, off offset:56 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s18\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v8, 26\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.8:\n\ts_or_saveexec_b32 s18, -1\n\tscratch_load_b32 v8, off, off offset:56 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s18\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v8, 13\n\tv_readlane_b32 s1, v8, 14\n\tv_readlane_b32 s2, v8, 9\n\tv_readlane_b32 s3, v8, 10\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s1\n\tv_mov_b32_e32 v3, s0\n\tflat_load_b32 v0, v[3:4]\n\ts_mov_b32 s0, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mad_i64_i32 v[3:4], s0, v0, s0, 0\n\tv_mov_b32_e32 v6, v3\n\ts_mov_b32 s0, 0\n ; implicit-def: $sgpr0\n\tv_mov_b32_e32 v0, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v0\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v3, v4\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr1\n ; implicit-def: $sgpr1\n\tv_mov_b32_e32 v5, s0\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s0, 32\n\tv_lshlrev_b64 v[4:5], s0, v[3:4]\n\tv_mov_b32_e32 v3, v5\n\tv_or_b32_e64 v0, v0, v3\n\tv_mov_b32_e32 v3, v6\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n\tv_or_b32_e64 v4, v3, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v0\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s0, v0, v3\n\tv_add_co_ci_u32_e64 v2, s0, v1, v2, s0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, -1\n\tflat_store_b32 v[0:1], v2 offset:16\n\ts_branch .LBB13_2\n.LBB13_9:\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z15initializeNodesP9BTreeNode\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 192\n\t\t.amdhsa_kernarg_size 264\n\t\t.amdhsa_user_sgpr_count 13\n\t\t.amdhsa_user_sgpr_dispatch_ptr 1\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 1\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 1\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 1\n\t\t.amdhsa_system_sgpr_workgroup_id_z 1\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 2\n\t\t.amdhsa_next_free_vgpr 32\n\t\t.amdhsa_next_free_sgpr 33\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end13:\n\t.size\t_Z15initializeNodesP9BTreeNode, .Lfunc_end13-_Z15initializeNodesP9BTreeNode\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 2400\n; NumSgprs: 35\n; NumVgprs: 32\n; ScratchSize: 192\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 4\n; VGPRBlocks: 3\n; NumSGPRsForWavesPerEU: 35\n; NumVGPRsForWavesPerEU: 32\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1\n; COMPUTE_PGM_RSRC2:USER_SGPR: 13\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2\n\t.text\n\t.protected\t_Z9insertKeyP9BTreeNodeii ; -- Begin function _Z9insertKeyP9BTreeNodeii\n\t.globl\t_Z9insertKeyP9BTreeNodeii\n\t.p2align\t8\n\t.type\t_Z9insertKeyP9BTreeNodeii,@function\n_Z9insertKeyP9BTreeNodeii: ; @_Z9insertKeyP9BTreeNodeii\n; %bb.0:\n\ts_mov_b32 s32, 0x70\n ; implicit-def: $vgpr9 : SGPR spill to VGPR lane\n\tv_writelane_b32 v9, s15, 0\n\ts_mov_b32 s6, s14\n\tv_readlane_b32 s14, v9, 0\n\tv_writelane_b32 v9, s6, 1\n\ts_mov_b32 s12, s13\n\tv_readlane_b32 s13, v9, 1\n\tv_writelane_b32 v9, s12, 2\n\ts_mov_b64 s[10:11], s[4:5]\n\tv_writelane_b32 v9, s10, 3\n\tv_writelane_b32 v9, s11, 4\n\tv_writelane_b32 v9, s2, 5\n\tv_writelane_b32 v9, s3, 6\n\ts_mov_b64 s[4:5], s[0:1]\n\tv_readlane_b32 s0, v9, 5\n\tv_readlane_b32 s1, v9, 6\n\tv_writelane_b32 v9, s4, 7\n\tv_writelane_b32 v9, s5, 8\n\tv_mov_b32_e32 v31, v0\n\tscratch_store_b32 off, v31, off offset:92 ; 4-byte Folded Spill\n\ts_load_b64 s[20:21], s[0:1], 0x0\n\ts_load_b32 s3, s[0:1], 0x8\n\ts_load_b32 s2, s[0:1], 0xc\n\ts_mov_b64 s[6:7], src_private_base\n\ts_mov_b32 s8, 32\n\ts_lshr_b64 s[6:7], s[6:7], s8\n\ts_mov_b32 s15, s6\n\ts_mov_b32 s18, 32\n ; kill: def $sgpr18 killed $sgpr18 def $sgpr18_sgpr19\n\ts_mov_b32 s19, s15\n\ts_mov_b32 s16, 40\n ; kill: def $sgpr16 killed $sgpr16 def $sgpr16_sgpr17\n\ts_mov_b32 s17, s15\n\ts_mov_b64 s[6:7], s[16:17]\n\tv_writelane_b32 v9, s6, 9\n\tv_writelane_b32 v9, s7, 10\n\ts_mov_b32 s8, 48\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s15\n\ts_mov_b64 s[6:7], s[8:9]\n\tv_writelane_b32 v9, s6, 11\n\tv_writelane_b32 v9, s7, 12\n\ts_mov_b32 s6, 52\n ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7\n\ts_mov_b32 s7, s15\n\ts_mov_b64 s[22:23], s[6:7]\n\tv_writelane_b32 v9, s22, 13\n\tv_writelane_b32 v9, s23, 14\n\ts_mov_b32 s22, 56\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s15\n\tv_writelane_b32 v9, s22, 15\n\tv_writelane_b32 v9, s23, 16\n\ts_mov_b32 s22, 64\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s15\n\tv_writelane_b32 v9, s22, 17\n\tv_writelane_b32 v9, s23, 18\n\ts_mov_b32 s22, 0x48\n ; kill: def $sgpr22 killed $sgpr22 def $sgpr22_sgpr23\n\ts_mov_b32 s23, s15\n\tv_writelane_b32 v9, s22, 19\n\tv_writelane_b32 v9, s23, 20\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\ts_waitcnt lgkmcnt(0)\n\tv_mov_b32_e32 v2, s20\n\tv_mov_b32_e32 v3, s21\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s18\n\tv_mov_b32_e32 v1, s19\n\tflat_load_b64 v[2:3], v[0:1]\n\tv_mov_b32_e32 v0, s16\n\tv_mov_b32_e32 v1, s17\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s8\n\tv_mov_b32_e32 v1, s9\n\tv_mov_b32_e32 v2, s3\n\tflat_store_b32 v[0:1], v2\n\tv_mov_b32_e32 v0, s6\n\tv_mov_b32_e32 v1, s7\n\tv_mov_b32_e32 v2, s2\n\tflat_store_b32 v[0:1], v2\n\ts_mov_b64 s[6:7], 16\n\ts_mov_b32 s2, s0\n\ts_mov_b32 s0, s1\n\ts_mov_b32 s3, s6\n\ts_mov_b32 s1, s7\n\ts_add_u32 s8, s2, s3\n\ts_addc_u32 s0, s0, s1\n ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9\n\ts_mov_b32 s9, s0\n\tv_writelane_b32 v9, s8, 21\n\tv_writelane_b32 v9, s9, 22\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_group_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_group_id@rel32@hi+12\n\tv_mov_b32_e32 v0, 0\n\tscratch_store_b32 off, v0, off offset:80 ; 4-byte Folded Spill\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:92 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v9, 0\n\tv_readlane_b32 s13, v9, 1\n\tv_readlane_b32 s12, v9, 2\n\tv_readlane_b32 s10, v9, 3\n\tv_readlane_b32 s11, v9, 4\n\tv_readlane_b32 s8, v9, 21\n\tv_readlane_b32 s9, v9, 22\n\tv_readlane_b32 s4, v9, 7\n\tv_readlane_b32 s5, v9, 8\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:80 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:96 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:96 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec\n\ts_waitcnt vmcnt(0)\n\tscratch_store_b32 off, v1, off offset:84 ; 4-byte Folded Spill\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_size@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_size@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tscratch_load_b32 v31, off, off offset:92 ; 4-byte Folded Reload\n\tv_readlane_b32 s14, v9, 0\n\tv_readlane_b32 s13, v9, 1\n\tv_readlane_b32 s12, v9, 2\n\tv_readlane_b32 s10, v9, 3\n\tv_readlane_b32 s11, v9, 4\n\tv_readlane_b32 s4, v9, 7\n\tv_readlane_b32 s5, v9, 8\n\tv_readlane_b32 s8, v9, 21\n\tv_readlane_b32 s9, v9, 22\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:80 ; 4-byte Folded Reload\n\tscratch_store_b32 off, v2, off offset:88 ; 4-byte Folded Spill\n\tv_mov_b32_e32 v3, v1\n\tscratch_load_b32 v1, off, off offset:88 ; 4-byte Folded Reload\n ; implicit-def: $sgpr0\n ; implicit-def: $sgpr0\n ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec\n\tv_mov_b32_e32 v2, v3\n\ts_waitcnt vmcnt(0)\n\tv_mov_b32_e32 v4, v1\n\ts_getpc_b64 s[0:1]\n\ts_add_u32 s0, s0, __ockl_get_local_id@rel32@lo+4\n\ts_addc_u32 s1, s1, __ockl_get_local_id@rel32@hi+12\n ; implicit-def: $sgpr6_sgpr7\n ; implicit-def: $sgpr15\n\ts_swappc_b64 s[30:31], s[0:1]\n\tv_readlane_b32 s0, v9, 15\n\tv_readlane_b32 s1, v9, 16\n\tv_mov_b32_e32 v2, v0\n\tscratch_load_b32 v0, off, off offset:84 ; 4-byte Folded Reload\n\tv_mov_b32_e32 v5, v1\n\tscratch_load_b32 v1, off, off offset:80 ; 4-byte Folded Reload\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v5\n\tv_mov_b32_e32 v5, v2\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v2, s2\n ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec\n\tv_mov_b32_e32 v6, v2\n\ts_waitcnt vmcnt(1)\n\tv_mad_u64_u32 v[2:3], s2, v0, v4, v[5:6]\n\tv_mov_b32_e32 v0, v2\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_store_b32 v[2:3], v0\n\tv_mov_b32_e32 v3, s1\n\tv_mov_b32_e32 v2, s0\n\tflat_load_b32 v0, v[2:3]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_eq_u32_e64 s1, v0, v1\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v9, s0, 23\n\ts_or_saveexec_b32 s24, -1\n\tscratch_store_b32 off, v9, off offset:76 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s24\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB14_11\n; %bb.1:\n\ts_or_saveexec_b32 s24, -1\n\tscratch_load_b32 v9, off, off offset:76 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s24\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v9, 17\n\tv_readlane_b32 s1, v9, 18\n\tv_readlane_b32 s2, v9, 11\n\tv_readlane_b32 s3, v9, 12\n\tv_readlane_b32 s4, v9, 9\n\tv_readlane_b32 s5, v9, 10\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b64 v[0:1], v[0:1]\n\tv_mov_b32_e32 v2, s2\n\tv_mov_b32_e32 v3, s3\n\tflat_load_b32 v2, v[2:3]\n\ts_mov_b32 s2, 24\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_mad_i64_i32 v[3:4], s2, v2, s2, 0\n\tv_mov_b32_e32 v6, v3\n\ts_mov_b32 s2, 0\n ; implicit-def: $sgpr2\n\tv_mov_b32_e32 v2, 0\n ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec\n\tv_mov_b32_e32 v7, v2\n\tv_mov_b32_e32 v2, v7\n\tv_mov_b32_e32 v3, v4\n ; implicit-def: $sgpr2\n ; implicit-def: $sgpr3\n ; implicit-def: $sgpr3\n\tv_mov_b32_e32 v5, s2\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v5\n\ts_mov_b32 s2, 32\n\tv_lshlrev_b64 v[4:5], s2, v[3:4]\n\tv_mov_b32_e32 v3, v5\n\tv_or_b32_e64 v2, v2, v3\n\tv_mov_b32_e32 v3, v6\n ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec\n\tv_or_b32_e64 v4, v3, v4\n ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec\n\tv_mov_b32_e32 v5, v2\n\tv_mov_b32_e32 v2, v0\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v1, v5\n\tv_add_co_u32 v2, s2, v2, v3\n\tv_add_co_ci_u32_e64 v0, s2, v0, v1, s2\n ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec\n\tv_mov_b32_e32 v3, v0\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b64 v[0:1], v[2:3]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_load_b32 v0, v[0:1] offset:20\n\ts_mov_b32 s0, 2\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_lt_i32_e64 s1, v0, s0\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v9, s0, 24\n\ts_or_saveexec_b32 s24, -1\n\tscratch_store_b32 off, v9, off offset:76 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s24\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB14_3\n; %bb.2:\n\ts_or_saveexec_b32 s24, -1\n\tscratch_load_b32 v9, off, off offset:76 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s24\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v9, 19\n\tv_readlane_b32 s1, v9, 20\n\tv_readlane_b32 s2, v9, 17\n\tv_readlane_b32 s3, v9, 18\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_load_b32 v0, v[0:1] offset:20\n\ts_mov_b32 s2, -1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v2, v0, s2\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v9, s0, 25\n\ts_or_saveexec_b32 s24, -1\n\tscratch_store_b32 off, v9, off offset:76 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s24\n\ts_branch .LBB14_4\n.LBB14_3:\n\ts_or_saveexec_b32 s24, -1\n\tscratch_load_b32 v9, off, off offset:76 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s24\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v9, 24\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_branch .LBB14_12\n.LBB14_4: ; =>This Inner Loop Header: Depth=1\n\ts_or_saveexec_b32 s24, -1\n\tscratch_load_b32 v9, off, off offset:76 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s24\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v9, 19\n\tv_readlane_b32 s1, v9, 20\n\tv_readlane_b32 s2, v9, 25\n\tv_writelane_b32 v9, s2, 26\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v0, v[0:1]\n\ts_mov_b32 s0, -1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_gt_i32_e64 s1, v0, s0\n\ts_mov_b32 s0, 0\n\tv_writelane_b32 v9, s0, 27\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v9, s0, 28\n\ts_or_saveexec_b32 s24, -1\n\tscratch_store_b32 off, v9, off offset:76 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s24\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB14_6\n; %bb.5: ; in Loop: Header=BB14_4 Depth=1\n\ts_or_saveexec_b32 s24, -1\n\tscratch_load_b32 v9, off, off offset:76 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s24\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v9, 13\n\tv_readlane_b32 s1, v9, 14\n\tv_readlane_b32 s2, v9, 19\n\tv_readlane_b32 s3, v9, 20\n\tv_readlane_b32 s4, v9, 17\n\tv_readlane_b32 s5, v9, 18\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s3\n\tv_mov_b32_e32 v3, s2\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\ts_mov_b32 s2, 2\n\tv_lshlrev_b64 v[4:5], s2, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s2, v0, v3\n\tv_add_co_ci_u32_e64 v2, s2, v1, v2, s2\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b32 v0, v[0:1]\n\tv_mov_b32_e32 v2, s1\n\tv_mov_b32_e32 v1, s0\n\tflat_load_b32 v1, v[1:2]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_cmp_gt_i32_e64 s0, v0, v1\n\ts_and_b32 s0, s0, exec_lo\n\tv_writelane_b32 v9, s0, 27\n\ts_or_saveexec_b32 s24, -1\n\tscratch_store_b32 off, v9, off offset:76 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s24\n.LBB14_6: ; in Loop: Header=BB14_4 Depth=1\n\ts_or_saveexec_b32 s24, -1\n\tscratch_load_b32 v9, off, off offset:76 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s24\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v9, 28\n\ts_or_b32 exec_lo, exec_lo, s0\n\tv_readlane_b32 s1, v9, 27\n\ts_mov_b32 s0, -1\n\tv_writelane_b32 v9, s0, 29\n\ts_mov_b32 s0, exec_lo\n\tv_writelane_b32 v9, s0, 30\n\ts_or_saveexec_b32 s24, -1\n\tscratch_store_b32 off, v9, off offset:76 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s24\n\ts_and_b32 s0, s0, s1\n\ts_mov_b32 exec_lo, s0\n\ts_cbranch_execz .LBB14_8\n; %bb.7: ; in Loop: Header=BB14_4 Depth=1\n\ts_or_saveexec_b32 s24, -1\n\tscratch_load_b32 v9, off, off offset:76 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s24\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v9, 19\n\tv_readlane_b32 s1, v9, 20\n\tv_readlane_b32 s2, v9, 17\n\tv_readlane_b32 s3, v9, 18\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b64 v[1:2], v[0:1]\n\tv_mov_b32_e32 v4, s1\n\tv_mov_b32_e32 v3, s0\n\tflat_load_b32 v3, v[3:4]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v0, 31, v3\n ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec\n\tv_mov_b32_e32 v4, v0\n\ts_mov_b32 s2, 2\n\tv_lshlrev_b64 v[4:5], s2, v[3:4]\n\tv_mov_b32_e32 v0, v1\n\tv_mov_b32_e32 v3, v4\n\tv_mov_b32_e32 v1, v2\n\tv_mov_b32_e32 v2, v5\n\tv_add_co_u32 v0, s2, v0, v3\n\tv_add_co_ci_u32_e64 v2, s2, v1, v2, s2\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v2\n\tflat_load_b32 v2, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_store_b32 v[0:1], v2 offset:4\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b32 v0, v[0:1]\n\ts_mov_b32 s2, -1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v2, v0, s2\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_store_b32 v[0:1], v2\n\ts_mov_b32 s0, 0\n\ts_xor_b32 s0, exec_lo, -1\n\tv_writelane_b32 v9, s0, 29\n\ts_or_saveexec_b32 s24, -1\n\tscratch_store_b32 off, v9, off offset:76 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s24\n.LBB14_8: ; in Loop: Header=BB14_4 Depth=1\n\ts_or_saveexec_b32 s24, -1\n\tscratch_load_b32 v9, off, off offset:76 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s24\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s2, v9, 30\n\ts_or_b32 exec_lo, exec_lo, s2\n\tv_readlane_b32 s1, v9, 26\n\tv_readlane_b32 s0, v9, 29\n\ts_and_b32 s0, exec_lo, s0\n\ts_or_b32 s0, s0, s1\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v9, s1, 25\n\ts_mov_b32 s1, s0\n\tv_writelane_b32 v9, s1, 31\n\ts_or_saveexec_b32 s24, -1\n\tscratch_store_b32 off, v9, off offset:76 ; 4-byte Folded Spill\n\ts_mov_b32 exec_lo, s24\n\ts_and_not1_b32 exec_lo, exec_lo, s0\n\ts_cbranch_execnz .LBB14_4\n; %bb.9:\n\ts_or_saveexec_b32 s24, -1\n\tscratch_load_b32 v9, off, off offset:76 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s24\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v9, 31\n\ts_or_b32 exec_lo, exec_lo, s0\n; %bb.10:\n\ts_or_saveexec_b32 s24, -1\n\tscratch_load_b32 v9, off, off offset:76 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s24\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v9, 17\n\tv_readlane_b32 s1, v9, 18\n\tv_readlane_b32 s2, v9, 19\n\tv_readlane_b32 s3, v9, 20\n\tv_readlane_b32 s4, v9, 13\n\tv_readlane_b32 s5, v9, 14\n\tv_mov_b32_e32 v0, s4\n\tv_mov_b32_e32 v1, s5\n\tflat_load_b32 v2, v[0:1]\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b64 v[5:6], v[0:1]\n\tv_mov_b32_e32 v0, s2\n\tv_mov_b32_e32 v1, s3\n\tflat_load_b32 v0, v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_ashrrev_i32_e64 v3, 31, v0\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\ts_mov_b32 s2, 2\n\tv_lshlrev_b64 v[7:8], s2, v[0:1]\n\tv_mov_b32_e32 v0, v7\n\tv_mov_b32_e32 v4, v5\n\tv_mov_b32_e32 v1, v8\n\tv_mov_b32_e32 v3, v6\n\tv_add_co_u32 v0, s2, v0, v4\n\tv_add_co_ci_u32_e64 v3, s2, v1, v3, s2\n ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec\n\tv_mov_b32_e32 v1, v3\n\tflat_store_b32 v[0:1], v2 offset:4\n\tv_mov_b32_e32 v0, s0\n\tv_mov_b32_e32 v1, s1\n\tflat_load_b64 v[0:1], v[0:1]\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tflat_load_b32 v2, v[0:1] offset:20\n\ts_mov_b32 s0, 1\n\ts_waitcnt vmcnt(0) lgkmcnt(0)\n\tv_add_nc_u32_e64 v2, v2, s0\n\tflat_store_b32 v[0:1], v2 offset:20\n\ts_branch .LBB14_3\n.LBB14_11:\n\ts_or_saveexec_b32 s24, -1\n\tscratch_load_b32 v9, off, off offset:76 ; 4-byte Folded Reload\n\ts_mov_b32 exec_lo, s24\n\ts_waitcnt vmcnt(0)\n\tv_readlane_b32 s0, v9, 23\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_branch .LBB14_13\n.LBB14_12:\n\ts_branch .LBB14_11\n.LBB14_13:\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z9insertKeyP9BTreeNodeii\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 224\n\t\t.amdhsa_kernarg_size 272\n\t\t.amdhsa_user_sgpr_count 13\n\t\t.amdhsa_user_sgpr_dispatch_ptr 1\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 1\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 1\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 1\n\t\t.amdhsa_system_sgpr_workgroup_id_z 1\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 2\n\t\t.amdhsa_next_free_vgpr 32\n\t\t.amdhsa_next_free_sgpr 33\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end14:\n\t.size\t_Z9insertKeyP9BTreeNodeii, .Lfunc_end14-_Z9insertKeyP9BTreeNodeii\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 2624\n; NumSgprs: 35\n; NumVgprs: 32\n; ScratchSize: 224\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 4\n; VGPRBlocks: 3\n; NumSGPRsForWavesPerEU: 35\n; NumVGPRsForWavesPerEU: 32\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1\n; COMPUTE_PGM_RSRC2:USER_SGPR: 13\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__const.__assert_fail.fmt,@object ; @__const.__assert_fail.fmt\n\t.section\t.rodata.str1.16,\"aMS\",@progbits,1\n\t.p2align\t4, 0x0\n__const.__assert_fail.fmt:\n\t.asciz\t\"%s:%u: %s: Device-side assertion `%s' failed.\\n\"\n\t.size\t__const.__assert_fail.fmt, 47\n\n\t.protected\tblockIdx\n\t.protected\tblockDim\n\t.protected\tthreadIdx\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.hidden\t__oclc_ABI_version ; @__oclc_ABI_version\n\t.type\t__oclc_ABI_version,@object\n\t.section\t.rodata,\"a\",@progbits\n\t.weak\t__oclc_ABI_version\n\t.p2align\t2, 0x0\n__oclc_ABI_version:\n\t.long\t500 ; 0x1f4\n\t.size\t__oclc_ABI_version, 4\n\n\t.weak\tblockIdx\n\t.weak\tblockDim\n\t.weak\tthreadIdx\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .offset: 8\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 12\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 16\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 20\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 22\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 24\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 26\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 28\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 30\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 48\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 56\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 64\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 72\n .size: 2\n .value_kind: hidden_grid_dims\n - .offset: 88\n .size: 8\n .value_kind: hidden_hostcall_buffer\n - .offset: 96\n .size: 8\n .value_kind: hidden_multigrid_sync_arg\n - .offset: 104\n .size: 8\n .value_kind: hidden_heap_v1\n - .offset: 112\n .size: 8\n .value_kind: hidden_default_queue\n - .offset: 208\n .size: 8\n .value_kind: hidden_queue_ptr\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 264\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z15initializeNodesP9BTreeNode\n .private_segment_fixed_size: 192\n .sgpr_count: 35\n .sgpr_spill_count: 29\n .symbol: _Z15initializeNodesP9BTreeNode.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 32\n .vgpr_spill_count: 10\n .wavefront_size: 32\n .workgroup_processor_mode: 1\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .offset: 8\n .size: 4\n .value_kind: by_value\n - .offset: 12\n .size: 4\n .value_kind: by_value\n - .offset: 16\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 20\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 24\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 28\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 30\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 32\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 34\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 36\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 38\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 56\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 64\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 72\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 80\n .size: 2\n .value_kind: hidden_grid_dims\n - .offset: 96\n .size: 8\n .value_kind: hidden_hostcall_buffer\n - .offset: 104\n .size: 8\n .value_kind: hidden_multigrid_sync_arg\n - .offset: 112\n .size: 8\n .value_kind: hidden_heap_v1\n - .offset: 120\n .size: 8\n .value_kind: hidden_default_queue\n - .offset: 216\n .size: 8\n .value_kind: hidden_queue_ptr\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 272\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z9insertKeyP9BTreeNodeii\n .private_segment_fixed_size: 224\n .sgpr_count: 35\n .sgpr_spill_count: 35\n .symbol: _Z9insertKeyP9BTreeNodeii.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 32\n .vgpr_spill_count: 13\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162598,"cells":{"id":{"kind":"string","value":"d2f09eb45391c5b30bcbe75f94443b9bf51b82fc_O0"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z9mulKernelPKiS0_Pii --------------------------\n .section .text._Z9mulKernelPKiS0_Pii,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=31\"\n .align 128\n\n\n\n\n .global _Z9mulKernelPKiS0_Pii\n .type _Z9mulKernelPKiS0_Pii,@function\n .size _Z9mulKernelPKiS0_Pii,(.L_x_5 - _Z9mulKernelPKiS0_Pii)\n .other _Z9mulKernelPKiS0_Pii,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z9mulKernelPKiS0_Pii:\n.text._Z9mulKernelPKiS0_Pii:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ MOV R12, c[0x0][0x118] ;\n /*0020*/ MOV R13, c[0x0][0x11c] ;\n /*0030*/ MOV R2, RZ ;\n /*0040*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0050*/ MOV R8, R2 ;\n /*0060*/ MOV R9, R3 ;\n /*0070*/ MOV R8, R8 ;\n /*0080*/ MOV R9, R9 ;\n /*0090*/ MOV R2, 0x8 ;\n /*00a0*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*00b0*/ MOV R6, R2 ;\n /*00c0*/ MOV R7, R3 ;\n /*00d0*/ MOV R6, R6 ;\n /*00e0*/ MOV R7, R7 ;\n /*00f0*/ MOV R2, 0x10 ;\n /*0100*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0110*/ MOV R10, R2 ;\n /*0120*/ MOV R14, R3 ;\n /*0130*/ MOV R10, R10 ;\n /*0140*/ MOV R14, R14 ;\n /*0150*/ MOV R0, 0x18 ;\n /*0160*/ LDC R0, c[0x0][R0+0x160] ;\n /*0170*/ MOV R5, R0 ;\n /*0180*/ MOV R6, R6 ;\n /*0190*/ MOV R7, R7 ;\n /*01a0*/ MOV R8, R8 ;\n /*01b0*/ MOV R9, R9 ;\n /*01c0*/ MOV R0, c[0x0][0x0] ;\n /*01d0*/ S2R R2, SR_CTAID.X ;\n /*01e0*/ MOV R2, R2 ;\n /*01f0*/ S2R R3, SR_TID.X ;\n /*0200*/ MOV R3, R3 ;\n /*0210*/ IMAD R2, R2, R0, R3 ;\n /*0220*/ MOV R0, c[0x0][0x4] ;\n /*0230*/ S2R R3, SR_CTAID.Y ;\n /*0240*/ MOV R3, R3 ;\n /*0250*/ S2R R4, SR_TID.Y ;\n /*0260*/ MOV R4, R4 ;\n /*0270*/ IMAD R0, R3, R0, R4 ;\n /*0280*/ IMAD R11, R0, R5, RZ ;\n /*0290*/ ISETP.LT.AND P0, PT, R5, 0x1, PT ;\n /*02a0*/ MOV R25, RZ ;\n /*02b0*/ MOV R0, R10 ;\n /*02c0*/ MOV R4, R14 ;\n /*02d0*/ MOV R5, R5 ;\n /*02e0*/ MOV R6, R6 ;\n /*02f0*/ MOV R7, R7 ;\n /*0300*/ MOV R8, R8 ;\n /*0310*/ MOV R9, R9 ;\n /*0320*/ MOV R10, R2 ;\n /*0330*/ MOV R11, R11 ;\n /*0340*/ MOV R25, R25 ;\n /*0350*/ @P0 BRA `(.L_x_0) ;\n /*0360*/ IADD3 R2, R5, -0x1, RZ ;\n /*0370*/ LOP3.LUT R15, R5, 0x3, RZ, 0xc0, !PT ;\n /*0380*/ ISETP.LT.U32.AND P0, PT, R2, 0x3, PT ;\n /*0390*/ MOV R25, RZ ;\n /*03a0*/ MOV R19, R25 ;\n /*03b0*/ MOV R15, R15 ;\n /*03c0*/ MOV R25, R25 ;\n /*03d0*/ MOV R19, R19 ;\n /*03e0*/ @P0 BRA `(.L_x_1) ;\n /*03f0*/ IADD3 R22, R5, -R15, RZ ;\n /*0400*/ IMAD.WIDE R16, R11, 0x4, RZ ;\n /*0410*/ IMAD.WIDE R2, R10, 0x4, RZ ;\n /*0420*/ MOV R27, R2 ;\n /*0430*/ MOV R26, R3 ;\n /*0440*/ IADD3 R27, P0, R6, R27, RZ ;\n /*0450*/ IADD3.X R26, R7, R26, RZ, P0, !PT ;\n /*0460*/ IMAD.WIDE R2, R5, 0x4, RZ ;\n /*0470*/ MOV R25, RZ ;\n /*0480*/ MOV R14, R8 ;\n /*0490*/ MOV R9, R9 ;\n /*04a0*/ MOV R22, R22 ;\n /*04b0*/ MOV R18, R16 ;\n /*04c0*/ MOV R16, R17 ;\n /*04d0*/ MOV R17, R18 ;\n /*04e0*/ MOV R18, R16 ;\n /*04f0*/ MOV R27, R27 ;\n /*0500*/ MOV R26, R26 ;\n /*0510*/ MOV R20, R2 ;\n /*0520*/ MOV R21, R3 ;\n /*0530*/ MOV R20, R20 ;\n /*0540*/ MOV R21, R21 ;\n /*0550*/ MOV R25, R25 ;\n /*0560*/ MOV R14, R14 ;\n /*0570*/ MOV R16, R9 ;\n.L_x_2:\n /*0580*/ IADD3 R23, P0, R14, R17, RZ ;\n /*0590*/ IADD3.X R24, R16, R18, RZ, P0, !PT ;\n /*05a0*/ MOV R2, R27 ;\n /*05b0*/ MOV R3, R26 ;\n /*05c0*/ MOV R2, R2 ;\n /*05d0*/ MOV R3, R3 ;\n /*05e0*/ R2UR UR4, R12 ;\n /*05f0*/ R2UR UR5, R13 ;\n /*0600*/ LDG.E R28, [R2.64] ;\n /*0610*/ MOV R2, R23 ;\n /*0620*/ MOV R3, R24 ;\n /*0630*/ MOV R2, R2 ;\n /*0640*/ MOV R3, R3 ;\n /*0650*/ R2UR UR4, R12 ;\n /*0660*/ R2UR UR5, R13 ;\n /*0670*/ LDG.E R2, [R2.64] ;\n /*0680*/ IMAD R25, R28, R2, R25 ;\n /*0690*/ IADD3 R27, P0, R27, R20, RZ ;\n /*06a0*/ IADD3.X R26, R26, R21, RZ, P0, !PT ;\n /*06b0*/ MOV R2, R27 ;\n /*06c0*/ MOV R3, R26 ;\n /*06d0*/ MOV R2, R2 ;\n /*06e0*/ MOV R3, R3 ;\n /*06f0*/ R2UR UR4, R12 ;\n /*0700*/ R2UR UR5, R13 ;\n /*0710*/ LDG.E R28, [R2.64] ;\n /*0720*/ IADD3 R2, P0, R23, 0x4, RZ ;\n /*0730*/ IADD3.X R3, R24, RZ, RZ, P0, !PT ;\n /*0740*/ MOV R2, R2 ;\n /*0750*/ MOV R3, R3 ;\n /*0760*/ MOV R2, R2 ;\n /*0770*/ MOV R3, R3 ;\n /*0780*/ R2UR UR4, R12 ;\n /*0790*/ R2UR UR5, R13 ;\n /*07a0*/ LDG.E R2, [R2.64] ;\n /*07b0*/ IMAD R25, R28, R2, R25 ;\n /*07c0*/ IADD3 R27, P0, R27, R20, RZ ;\n /*07d0*/ IADD3.X R26, R26, R21, RZ, P0, !PT ;\n /*07e0*/ MOV R2, R27 ;\n /*07f0*/ MOV R3, R26 ;\n /*0800*/ MOV R2, R2 ;\n /*0810*/ MOV R3, R3 ;\n /*0820*/ R2UR UR4, R12 ;\n /*0830*/ R2UR UR5, R13 ;\n /*0840*/ LDG.E R28, [R2.64] ;\n /*0850*/ IADD3 R2, P0, R23, 0x8, RZ ;\n /*0860*/ IADD3.X R3, R24, RZ, RZ, P0, !PT ;\n /*0870*/ MOV R2, R2 ;\n /*0880*/ MOV R3, R3 ;\n /*0890*/ MOV R2, R2 ;\n /*08a0*/ MOV R3, R3 ;\n /*08b0*/ R2UR UR4, R12 ;\n /*08c0*/ R2UR UR5, R13 ;\n /*08d0*/ LDG.E R2, [R2.64] ;\n /*08e0*/ IMAD R25, R28, R2, R25 ;\n /*08f0*/ IADD3 R2, P0, R27, R20, RZ ;\n /*0900*/ IADD3.X R3, R26, R21, RZ, P0, !PT ;\n /*0910*/ IADD3 R27, P0, R2, R20, RZ ;\n /*0920*/ IADD3.X R26, R3, R21, RZ, P0, !PT ;\n /*0930*/ MOV R2, R2 ;\n /*0940*/ MOV R3, R3 ;\n /*0950*/ MOV R2, R2 ;\n /*0960*/ MOV R3, R3 ;\n /*0970*/ R2UR UR4, R12 ;\n /*0980*/ R2UR UR5, R13 ;\n /*0990*/ LDG.E R28, [R2.64] ;\n /*09a0*/ IADD3 R2, P0, R23, 0xc, RZ ;\n /*09b0*/ IADD3.X R3, R24, RZ, RZ, P0, !PT ;\n /*09c0*/ MOV R2, R2 ;\n /*09d0*/ MOV R3, R3 ;\n /*09e0*/ MOV R2, R2 ;\n /*09f0*/ MOV R3, R3 ;\n /*0a00*/ R2UR UR4, R12 ;\n /*0a10*/ R2UR UR5, R13 ;\n /*0a20*/ LDG.E R2, [R2.64] ;\n /*0a30*/ IMAD R25, R28, R2, R25 ;\n /*0a40*/ IADD3 R19, R19, 0x4, RZ ;\n /*0a50*/ IADD3 R14, P0, R14, 0x10, RZ ;\n /*0a60*/ IADD3.X R16, R16, RZ, RZ, P0, !PT ;\n /*0a70*/ IADD3 R22, R22, -0x4, RZ ;\n /*0a80*/ ISETP.NE.AND P0, PT, R22, RZ, PT ;\n /*0a90*/ MOV R27, R27 ;\n /*0aa0*/ MOV R26, R26 ;\n /*0ab0*/ MOV R25, R25 ;\n /*0ac0*/ MOV R19, R19 ;\n /*0ad0*/ MOV R14, R14 ;\n /*0ae0*/ MOV R16, R16 ;\n /*0af0*/ MOV R22, R22 ;\n /*0b00*/ @P0 BRA `(.L_x_2) ;\n.L_x_1:\n /*0b10*/ ISETP.EQ.AND P0, PT, R15, RZ, PT ;\n /*0b20*/ @P0 BRA `(.L_x_0) ;\n /*0b30*/ IMAD R2, R19, R5, R10 ;\n /*0b40*/ IMAD.WIDE R2, R2, 0x4, RZ ;\n /*0b50*/ MOV R14, R2 ;\n /*0b60*/ MOV R16, R3 ;\n /*0b70*/ IADD3 R14, P0, R6, R14, RZ ;\n /*0b80*/ IADD3.X R16, R7, R16, RZ, P0, !PT ;\n /*0b90*/ IMAD.WIDE R2, R5, 0x4, RZ ;\n /*0ba0*/ IADD3 R6, R19, R11, RZ ;\n /*0bb0*/ IMAD.WIDE R6, R6, 0x4, RZ ;\n /*0bc0*/ MOV R5, R6 ;\n /*0bd0*/ MOV R6, R7 ;\n /*0be0*/ IADD3 R8, P0, R8, R5, RZ ;\n /*0bf0*/ IADD3.X R9, R9, R6, RZ, P0, !PT ;\n /*0c00*/ MOV R6, R14 ;\n /*0c10*/ MOV R7, R16 ;\n /*0c20*/ MOV R14, R2 ;\n /*0c30*/ MOV R16, R3 ;\n /*0c40*/ MOV R14, R14 ;\n /*0c50*/ MOV R16, R16 ;\n /*0c60*/ MOV R8, R8 ;\n /*0c70*/ MOV R9, R9 ;\n.L_x_3:\n /*0c80*/ MOV R2, R6 ;\n /*0c90*/ MOV R3, R7 ;\n /*0ca0*/ MOV R2, R2 ;\n /*0cb0*/ MOV R3, R3 ;\n /*0cc0*/ R2UR UR4, R12 ;\n /*0cd0*/ R2UR UR5, R13 ;\n /*0ce0*/ LDG.E R5, [R2.64] ;\n /*0cf0*/ MOV R2, R8 ;\n /*0d00*/ MOV R3, R9 ;\n /*0d10*/ MOV R2, R2 ;\n /*0d20*/ MOV R3, R3 ;\n /*0d30*/ R2UR UR4, R12 ;\n /*0d40*/ R2UR UR5, R13 ;\n /*0d50*/ LDG.E R2, [R2.64] ;\n /*0d60*/ IMAD R2, R5, R2, R25 ;\n /*0d70*/ IADD3 R6, P0, R6, R14, RZ ;\n /*0d80*/ IADD3.X R7, R7, R16, RZ, P0, !PT ;\n /*0d90*/ IADD3 R3, P0, R8, 0x4, RZ ;\n /*0da0*/ IADD3.X R5, R9, RZ, RZ, P0, !PT ;\n /*0db0*/ IADD3 R15, R15, -0x1, RZ ;\n /*0dc0*/ ISETP.NE.AND P0, PT, R15, RZ, PT ;\n /*0dd0*/ MOV R25, R2 ;\n /*0de0*/ MOV R6, R6 ;\n /*0df0*/ MOV R7, R7 ;\n /*0e00*/ MOV R8, R3 ;\n /*0e10*/ MOV R9, R5 ;\n /*0e20*/ MOV R15, R15 ;\n /*0e30*/ @P0 BRA `(.L_x_3) ;\n.L_x_0:\n /*0e40*/ IADD3 R2, R11, R10, RZ ;\n /*0e50*/ MOV R5, R0 ;\n /*0e60*/ MOV R4, R4 ;\n /*0e70*/ IMAD.WIDE R2, R2, 0x4, RZ ;\n /*0e80*/ MOV R0, R2 ;\n /*0e90*/ MOV R3, R3 ;\n /*0ea0*/ IADD3 R2, P0, R5, R0, RZ ;\n /*0eb0*/ IADD3.X R3, R4, R3, RZ, P0, !PT ;\n /*0ec0*/ MOV R2, R2 ;\n /*0ed0*/ MOV R3, R3 ;\n /*0ee0*/ MOV R2, R2 ;\n /*0ef0*/ MOV R3, R3 ;\n /*0f00*/ R2UR UR4, R12 ;\n /*0f10*/ R2UR UR5, R13 ;\n /*0f20*/ STG.E [R2.64], R25 ;\n /*0f30*/ EXIT ;\n.L_x_4:\n /*0f40*/ BRA `(.L_x_4);\n /*0f50*/ NOP;\n /*0f60*/ NOP;\n /*0f70*/ NOP;\n /*0f80*/ NOP;\n /*0f90*/ NOP;\n /*0fa0*/ NOP;\n /*0fb0*/ NOP;\n /*0fc0*/ NOP;\n /*0fd0*/ NOP;\n /*0fe0*/ NOP;\n /*0ff0*/ NOP;\n.L_x_5:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.protected\t_Z9mulKernelPKiS0_Pii ; -- Begin function _Z9mulKernelPKiS0_Pii\n\t.globl\t_Z9mulKernelPKiS0_Pii\n\t.p2align\t8\n\t.type\t_Z9mulKernelPKiS0_Pii,@function\n_Z9mulKernelPKiS0_Pii: ; @_Z9mulKernelPKiS0_Pii\n; %bb.0:\n\ts_clause 0x1\n\ts_load_b32 s3, s[0:1], 0x2c\n\ts_load_b32 s2, s[0:1], 0x18\n\tv_bfe_u32 v1, v0, 10, 10\n\ts_waitcnt lgkmcnt(0)\n\ts_lshr_b32 s4, s3, 16\n\ts_and_b32 s3, s3, 0xffff\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]\n\tv_and_b32_e32 v3, 0x3ff, v0\n\ts_cmp_lt_i32 s2, 1\n\tv_mad_u64_u32 v[0:1], null, s14, s3, v[3:4]\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_mul_lo_u32 v1, v2, s2\n\ts_cbranch_scc1 .LBB0_3\n; %bb.1:\n\ts_load_b128 s[4:7], s[0:1], 0x0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)\n\tv_ashrrev_i32_e32 v2, 31, v1\n\ts_mov_b32 s3, s2\n\tv_mov_b32_e32 v5, v0\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)\n\tv_lshlrev_b64 v[3:4], 2, v[1:2]\n\tv_mov_b32_e32 v2, 0\n\ts_waitcnt lgkmcnt(0)\n\tv_add_co_u32 v3, vcc_lo, s4, v3\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo\n\t.p2align\t6\n.LBB0_2: ; =>This Inner Loop Header: Depth=1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\tv_ashrrev_i32_e32 v6, 31, v5\n\ts_add_i32 s3, s3, -1\n\ts_cmp_lg_u32 s3, 0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[6:7], 2, v[5:6]\n\tv_add_co_u32 v6, vcc_lo, s6, v6\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo\n\tglobal_load_b32 v8, v[3:4], off\n\tglobal_load_b32 v9, v[6:7], off\n\ts_waitcnt vmcnt(0)\n\tv_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]\n\tv_add_co_u32 v3, vcc_lo, v3, 4\n\tv_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5\n\ts_cbranch_scc1 .LBB0_2\n\ts_branch .LBB0_4\n.LBB0_3:\n\tv_mov_b32_e32 v2, 0\n.LBB0_4:\n\ts_load_b64 s[0:1], s[0:1], 0x10\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)\n\tv_add_nc_u32_e32 v0, v1, v0\n\tv_ashrrev_i32_e32 v1, 31, v0\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[0:1], 2, v[0:1]\n\ts_waitcnt lgkmcnt(0)\n\tv_add_co_u32 v0, vcc_lo, s0, v0\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo\n\tglobal_store_b32 v[0:1], v2, off\n\ts_nop 0\n\ts_sendmsg sendmsg(MSG_DEALLOC_VGPRS)\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z9mulKernelPKiS0_Pii\n\t\t.amdhsa_group_segment_fixed_size 0\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 288\n\t\t.amdhsa_user_sgpr_count 14\n\t\t.amdhsa_user_sgpr_dispatch_ptr 0\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 1\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 1\n\t\t.amdhsa_next_free_vgpr 10\n\t\t.amdhsa_next_free_sgpr 16\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end0:\n\t.size\t_Z9mulKernelPKiS0_Pii, .Lfunc_end0-_Z9mulKernelPKiS0_Pii\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 332\n; NumSgprs: 18\n; NumVgprs: 10\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 0 bytes/workgroup (compile time only)\n; SGPRBlocks: 2\n; VGPRBlocks: 1\n; NumSGPRsForWavesPerEU: 18\n; NumVGPRsForWavesPerEU: 10\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 14\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .address_space: global\n .offset: 0\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 8\n .size: 8\n .value_kind: global_buffer\n - .address_space: global\n .offset: 16\n .size: 8\n .value_kind: global_buffer\n - .offset: 24\n .size: 4\n .value_kind: by_value\n - .offset: 32\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 36\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 40\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 44\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 46\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 48\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 50\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 52\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 54\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 72\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 80\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 88\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 96\n .size: 2\n .value_kind: hidden_grid_dims\n .group_segment_fixed_size: 0\n .kernarg_segment_align: 8\n .kernarg_segment_size: 288\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z9mulKernelPKiS0_Pii\n .private_segment_fixed_size: 0\n .sgpr_count: 18\n .sgpr_spill_count: 0\n .symbol: _Z9mulKernelPKiS0_Pii.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 10\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}},{"rowIdx":162599,"cells":{"id":{"kind":"string","value":"0aae2e3c7ab05292214949b8999461687d7bb33f_O0"},"cuda":{"kind":"string","value":" .headerflags @\"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)\"\n .elftype @\"ET_EXEC\"\n\n\n//--------------------- .text._Z18BP_queens_root_dfsijiPK10queen_rootPyS2_ --------------------------\n .section .text._Z18BP_queens_root_dfsijiPK10queen_rootPyS2_,\"ax\",@progbits\n .sectioninfo @\"SHI_REGISTERS=38\"\n .align 128\n\n\n\n\n .global _Z18BP_queens_root_dfsijiPK10queen_rootPyS2_\n .type _Z18BP_queens_root_dfsijiPK10queen_rootPyS2_,@function\n .size _Z18BP_queens_root_dfsijiPK10queen_rootPyS2_,(.L_x_28 - _Z18BP_queens_root_dfsijiPK10queen_rootPyS2_)\n .other _Z18BP_queens_root_dfsijiPK10queen_rootPyS2_,@\"STO_CUDA_ENTRY STV_DEFAULT\"\n_Z18BP_queens_root_dfsijiPK10queen_rootPyS2_:\n.text._Z18BP_queens_root_dfsijiPK10queen_rootPyS2_:\n /*0000*/ MOV R1, c[0x0][0x28] ;\n /*0010*/ IADD3 R1, R1, -0x18, RZ ;\n /*0020*/ S2R R0, SR_LMEMHIOFF ;\n /*0030*/ ISETP.GE.U32.AND P0, PT, R1, R0, PT ;\n /*0040*/ @P0 BRA `(.L_x_0) ;\n /*0050*/ BPT.TRAP 0x1 ;\n.L_x_0:\n /*0060*/ MOV R18, c[0x0][0x118] ;\n /*0070*/ MOV R19, c[0x0][0x11c] ;\n /*0080*/ IADD3 R0, R1, RZ, RZ ;\n /*0090*/ MOV R0, R0 ;\n /*00a0*/ MOV R2, R0 ;\n /*00b0*/ MOV R3, RZ ;\n /*00c0*/ MOV R7, R2 ;\n /*00d0*/ MOV R6, R3 ;\n /*00e0*/ MOV R7, R7 ;\n /*00f0*/ MOV R6, R6 ;\n /*0100*/ MOV R0, RZ ;\n /*0110*/ LDC R0, c[0x0][R0+0x160] ;\n /*0120*/ MOV R9, R0 ;\n /*0130*/ MOV R0, 0x4 ;\n /*0140*/ LDC R0, c[0x0][R0+0x160] ;\n /*0150*/ MOV R0, R0 ;\n /*0160*/ MOV R2, 0x8 ;\n /*0170*/ LDC R2, c[0x0][R2+0x160] ;\n /*0180*/ MOV R8, R2 ;\n /*0190*/ MOV R2, 0x10 ;\n /*01a0*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*01b0*/ MOV R14, R2 ;\n /*01c0*/ MOV R15, R3 ;\n /*01d0*/ MOV R14, R14 ;\n /*01e0*/ MOV R15, R15 ;\n /*01f0*/ MOV R2, 0x18 ;\n /*0200*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0210*/ MOV R10, R2 ;\n /*0220*/ MOV R11, R3 ;\n /*0230*/ MOV R10, R10 ;\n /*0240*/ MOV R11, R11 ;\n /*0250*/ MOV R2, 0x20 ;\n /*0260*/ LDC.64 R2, c[0x0][R2+0x160] ;\n /*0270*/ MOV R12, R2 ;\n /*0280*/ MOV R13, R3 ;\n /*0290*/ MOV R12, R12 ;\n /*02a0*/ MOV R13, R13 ;\n /*02b0*/ MOV R14, R14 ;\n /*02c0*/ MOV R15, R15 ;\n /*02d0*/ IADD3 R7, P0, R7, RZ, RZ ;\n /*02e0*/ IADD3.X R6, R6, RZ, RZ, P0, !PT ;\n /*02f0*/ MOV R2, c[0x0][0x0] ;\n /*0300*/ S2R R3, SR_CTAID.X ;\n /*0310*/ MOV R3, R3 ;\n /*0320*/ S2R R4, SR_TID.X ;\n /*0330*/ MOV R4, R4 ;\n /*0340*/ IMAD R2, R3, R2, R4 ;\n /*0350*/ ISETP.GE.U32.AND P0, PT, R2, R0, PT ;\n /*0360*/ MOV R9, R9 ;\n /*0370*/ MOV R8, R8 ;\n /*0380*/ MOV R10, R10 ;\n /*0390*/ MOV R11, R11 ;\n /*03a0*/ MOV R12, R12 ;\n /*03b0*/ MOV R13, R13 ;\n /*03c0*/ MOV R14, R14 ;\n /*03d0*/ MOV R15, R15 ;\n /*03e0*/ MOV R7, R7 ;\n /*03f0*/ MOV R6, R6 ;\n /*0400*/ MOV R0, R2 ;\n /*0410*/ @P0 BRA `(.L_x_1) ;\n /*0420*/ ISETP.LT.AND P0, PT, R9, 0x1, PT ;\n /*0430*/ @P0 BRA `(.L_x_2) ;\n /*0440*/ LOP3.LUT R2, R9, 0x1, RZ, 0xc0, !PT ;\n /*0450*/ ISETP.EQ.AND P0, PT, R9, 0x1, PT ;\n /*0460*/ MOV R3, RZ ;\n /*0470*/ MOV R4, RZ ;\n /*0480*/ MOV R2, R2 ;\n /*0490*/ MOV R3, R3 ;\n /*04a0*/ MOV R4, R4 ;\n /*04b0*/ @P0 BRA `(.L_x_3) ;\n /*04c0*/ IADD3 R3, R9, -R2, RZ ;\n /*04d0*/ MOV R4, RZ ;\n /*04e0*/ MOV R3, R3 ;\n /*04f0*/ MOV R16, R4 ;\n.L_x_4:\n /*0500*/ MOV R4, R16 ;\n /*0510*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ;\n /*0520*/ MOV R4, R4 ;\n /*0530*/ MOV R5, R5 ;\n /*0540*/ MOV R17, R4 ;\n /*0550*/ MOV R5, R5 ;\n /*0560*/ MOV R17, R17 ;\n /*0570*/ MOV R5, R5 ;\n /*0580*/ IADD3 R17, P0, R7, R17, RZ ;\n /*0590*/ IADD3.X R5, R6, R5, RZ, P0, !PT ;\n /*05a0*/ MOV R4, 0xff ;\n /*05b0*/ MOV R4, R4 ;\n /*05c0*/ MOV R17, R17 ;\n /*05d0*/ MOV R5, R5 ;\n /*05e0*/ MOV R4, R4 ;\n /*05f0*/ PRMT R5, R4, 0x7610, R5 ;\n /*0600*/ MOV R4, R4 ;\n /*0610*/ SHF.L.U32 R5, R5, 0x8, RZ ;\n /*0620*/ LOP3.LUT R4, R5, 0xff00, R4, 0xe2, !PT ;\n /*0630*/ STL.U16 [R17], R4 ;\n /*0640*/ IADD3 R16, R16, 0x2, RZ ;\n /*0650*/ IADD3 R3, R3, -0x2, RZ ;\n /*0660*/ ISETP.NE.AND P0, PT, R3, RZ, PT ;\n /*0670*/ MOV R16, R16 ;\n /*0680*/ MOV R3, R3 ;\n /*0690*/ @P0 BRA `(.L_x_4) ;\n /*06a0*/ MOV R4, R16 ;\n /*06b0*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ;\n /*06c0*/ MOV R4, R4 ;\n /*06d0*/ MOV R5, R5 ;\n /*06e0*/ MOV R4, R4 ;\n /*06f0*/ MOV R5, R5 ;\n /*0700*/ MOV R3, R4 ;\n /*0710*/ MOV R4, R5 ;\n /*0720*/ MOV R3, R3 ;\n /*0730*/ MOV R4, R4 ;\n.L_x_3:\n /*0740*/ ISETP.EQ.AND P0, PT, R2, RZ, PT ;\n /*0750*/ @P0 BRA `(.L_x_2) ;\n /*0760*/ IADD3 R3, P0, R7, R3, RZ ;\n /*0770*/ IADD3.X R4, R6, R4, RZ, P0, !PT ;\n /*0780*/ MOV R2, 0xff ;\n /*0790*/ MOV R2, R2 ;\n /*07a0*/ MOV R3, R3 ;\n /*07b0*/ MOV R4, R4 ;\n /*07c0*/ MOV R2, R2 ;\n /*07d0*/ STL.U8 [R3], R2 ;\n.L_x_2:\n /*07e0*/ MOV R2, R0 ;\n /*07f0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ;\n /*0800*/ MOV R2, R2 ;\n /*0810*/ MOV R3, R3 ;\n /*0820*/ MOV R2, R2 ;\n /*0830*/ MOV R3, R3 ;\n /*0840*/ IMAD.WIDE R4, R0, 0x10, RZ ;\n /*0850*/ MOV R0, R4 ;\n /*0860*/ MOV R5, R5 ;\n /*0870*/ IADD3 R4, P0, R14, R0, RZ ;\n /*0880*/ IADD3.X R5, R15, R5, RZ, P0, !PT ;\n /*0890*/ MOV R4, R4 ;\n /*08a0*/ MOV R5, R5 ;\n /*08b0*/ MOV R4, R4 ;\n /*08c0*/ MOV R5, R5 ;\n /*08d0*/ R2UR UR4, R18 ;\n /*08e0*/ R2UR UR5, R19 ;\n /*08f0*/ LDG.E.CONSTANT R0, [R4.64] ;\n /*0900*/ ISETP.LT.AND P0, PT, R8, 0x1, PT ;\n /*0910*/ MOV R5, R2 ;\n /*0920*/ MOV R4, R3 ;\n /*0930*/ MOV R5, R5 ;\n /*0940*/ MOV R4, R4 ;\n /*0950*/ MOV R0, R0 ;\n /*0960*/ @P0 BRA `(.L_x_5) ;\n /*0970*/ LOP3.LUT R16, R8, 0x1, RZ, 0xc0, !PT ;\n /*0980*/ ISETP.EQ.AND P0, PT, R8, 0x1, PT ;\n /*0990*/ MOV R17, RZ ;\n /*09a0*/ MOV R20, RZ ;\n /*09b0*/ MOV R16, R16 ;\n /*09c0*/ MOV R17, R17 ;\n /*09d0*/ MOV R20, R20 ;\n /*09e0*/ @P0 BRA `(.L_x_6) ;\n /*09f0*/ IADD3 R20, R8, -R16, RZ ;\n /*0a00*/ MOV R22, RZ ;\n /*0a10*/ SHF.L.U64.HI R17, R5, 0x4, R4 ;\n /*0a20*/ SHF.L.U32 R21, R5, 0x4, RZ ;\n /*0a30*/ IADD3 R21, P0, R14, R21, RZ ;\n /*0a40*/ IADD3.X R17, R15, R17, RZ, P0, !PT ;\n /*0a50*/ MOV R20, R20 ;\n /*0a60*/ MOV R22, R22 ;\n /*0a70*/ MOV R21, R21 ;\n /*0a80*/ MOV R17, R17 ;\n.L_x_7:\n /*0a90*/ MOV R2, R22 ;\n /*0aa0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ;\n /*0ab0*/ MOV R2, R2 ;\n /*0ac0*/ MOV R3, R3 ;\n /*0ad0*/ MOV R24, R2 ;\n /*0ae0*/ MOV R23, R3 ;\n /*0af0*/ MOV R24, R24 ;\n /*0b00*/ MOV R23, R23 ;\n /*0b10*/ IADD3 R26, P0, R21, R24, RZ ;\n /*0b20*/ IADD3.X R27, R17, R23, RZ, P0, !PT ;\n /*0b30*/ IADD3 R24, P0, R7, R24, RZ ;\n /*0b40*/ IADD3.X R23, R6, R23, RZ, P0, !PT ;\n /*0b50*/ IADD3 R2, P0, R26, 0x4, RZ ;\n /*0b60*/ IADD3.X R3, R27, RZ, RZ, P0, !PT ;\n /*0b70*/ MOV R2, R2 ;\n /*0b80*/ MOV R3, R3 ;\n /*0b90*/ MOV R2, R2 ;\n /*0ba0*/ MOV R3, R3 ;\n /*0bb0*/ R2UR UR4, R18 ;\n /*0bc0*/ R2UR UR5, R19 ;\n /*0bd0*/ LDG.E.U8.CONSTANT R2, [R2.64] ;\n /*0be0*/ PRMT R2, R2, 0x7770, RZ ;\n /*0bf0*/ PRMT R25, R2, 0x7710, RZ ;\n /*0c00*/ IADD3 R2, P0, R26, 0x5, RZ ;\n /*0c10*/ IADD3.X R3, R27, RZ, RZ, P0, !PT ;\n /*0c20*/ MOV R2, R2 ;\n /*0c30*/ MOV R3, R3 ;\n /*0c40*/ MOV R2, R2 ;\n /*0c50*/ MOV R3, R3 ;\n /*0c60*/ R2UR UR4, R18 ;\n /*0c70*/ R2UR UR5, R19 ;\n /*0c80*/ LDG.E.U8.CONSTANT R2, [R2.64] ;\n /*0c90*/ PRMT R2, R2, 0x7770, RZ ;\n /*0ca0*/ PRMT R2, R2, 0x7710, RZ ;\n /*0cb0*/ MOV R24, R24 ;\n /*0cc0*/ MOV R23, R23 ;\n /*0cd0*/ MOV R25, R25 ;\n /*0ce0*/ MOV R2, R2 ;\n /*0cf0*/ MOV R25, R25 ;\n /*0d00*/ SHF.L.U32 R2, R2, 0x8, RZ ;\n /*0d10*/ LOP3.LUT R25, R2, 0xff00, R25, 0xe2, !PT ;\n /*0d20*/ STL.U16 [R24], R25 ;\n /*0d30*/ IADD3 R22, R22, 0x2, RZ ;\n /*0d40*/ IADD3 R20, R20, -0x2, RZ ;\n /*0d50*/ ISETP.NE.AND P0, PT, R20, RZ, PT ;\n /*0d60*/ MOV R22, R22 ;\n /*0d70*/ MOV R20, R20 ;\n /*0d80*/ @P0 BRA `(.L_x_7) ;\n /*0d90*/ MOV R2, R22 ;\n /*0da0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ;\n /*0db0*/ MOV R2, R2 ;\n /*0dc0*/ MOV R3, R3 ;\n /*0dd0*/ MOV R2, R2 ;\n /*0de0*/ MOV R3, R3 ;\n /*0df0*/ MOV R17, R2 ;\n /*0e00*/ MOV R2, R3 ;\n /*0e10*/ MOV R17, R17 ;\n /*0e20*/ MOV R20, R2 ;\n.L_x_6:\n /*0e30*/ ISETP.EQ.AND P0, PT, R16, RZ, PT ;\n /*0e40*/ @P0 BRA `(.L_x_5) ;\n /*0e50*/ SHF.L.U64.HI R3, R5, 0x4, R4 ;\n /*0e60*/ SHF.L.U32 R2, R5, 0x4, RZ ;\n /*0e70*/ IADD3 R2, P0, R14, R2, RZ ;\n /*0e80*/ IADD3.X R3, R15, R3, RZ, P0, !PT ;\n /*0e90*/ IADD3 R2, P0, R2, R17, RZ ;\n /*0ea0*/ IADD3.X R3, R3, R20, RZ, P0, !PT ;\n /*0eb0*/ IADD3 R2, P0, R2, 0x4, RZ ;\n /*0ec0*/ IADD3.X R3, R3, RZ, RZ, P0, !PT ;\n /*0ed0*/ MOV R2, R2 ;\n /*0ee0*/ MOV R3, R3 ;\n /*0ef0*/ MOV R2, R2 ;\n /*0f00*/ MOV R3, R3 ;\n /*0f10*/ R2UR UR4, R18 ;\n /*0f20*/ R2UR UR5, R19 ;\n /*0f30*/ LDG.E.U8.CONSTANT R2, [R2.64] ;\n /*0f40*/ PRMT R2, R2, 0x7770, RZ ;\n /*0f50*/ PRMT R2, R2, 0x7710, RZ ;\n /*0f60*/ IADD3 R3, P0, R7, R17, RZ ;\n /*0f70*/ IADD3.X R14, R6, R20, RZ, P0, !PT ;\n /*0f80*/ MOV R3, R3 ;\n /*0f90*/ MOV R14, R14 ;\n /*0fa0*/ MOV R2, R2 ;\n /*0fb0*/ STL.U8 [R3], R2 ;\n.L_x_5:\n /*0fc0*/ MOV R22, R12 ;\n /*0fd0*/ MOV R21, R13 ;\n /*0fe0*/ MOV R10, R10 ;\n /*0ff0*/ MOV R11, R11 ;\n /*1000*/ MOV R16, RZ ;\n /*1010*/ MOV R15, RZ ;\n /*1020*/ MOV R14, R8 ;\n /*1030*/ MOV R13, R16 ;\n /*1040*/ MOV R12, R15 ;\n /*1050*/ MOV R22, R22 ;\n /*1060*/ MOV R21, R21 ;\n /*1070*/ MOV R20, R10 ;\n /*1080*/ MOV R17, R11 ;\n /*1090*/ MOV R16, R16 ;\n /*10a0*/ MOV R15, R15 ;\n /*10b0*/ MOV R14, R14 ;\n /*10c0*/ MOV R13, R13 ;\n /*10d0*/ MOV R12, R12 ;\n /*10e0*/ BSSY B2, `(.L_x_8) ;\n /*10f0*/ BRA `(.L_x_9) ;\n.L_x_26:\n /*1100*/ ISETP.LT.AND P0, PT, R14, 0x1, PT ;\n /*1110*/ MOV R10, 0x1 ;\n /*1120*/ MOV R10, R10 ;\n /*1130*/ PLOP3.LUT P2, PT, P0, PT, PT, 0x80, 0x0 ;\n /*1140*/ MOV R10, R10 ;\n /*1150*/ BSSY B3, `(.L_x_10) ;\n /*1160*/ @P0 BRA `(.L_x_11) ;\n /*1170*/ IADD3 R2, R14, -0x1, RZ ;\n /*1180*/ LOP3.LUT R26, R14, 0x3, RZ, 0xc0, !PT ;\n /*1190*/ ISETP.LT.U32.AND P0, PT, R2, 0x3, PT ;\n /*11a0*/ MOV R10, 0x1 ;\n /*11b0*/ MOV R10, R10 ;\n /*11c0*/ MOV R28, RZ ;\n /*11d0*/ MOV R26, R26 ;\n /*11e0*/ MOV R10, R10 ;\n /*11f0*/ MOV R28, R28 ;\n /*1200*/ BSSY B4, `(.L_x_12) ;\n /*1210*/ @P0 BRA `(.L_x_13) ;\n /*1220*/ IADD3 R29, R14, -R26, RZ ;\n /*1230*/ MOV R10, 0x1 ;\n /*1240*/ MOV R10, R10 ;\n /*1250*/ MOV R28, RZ ;\n /*1260*/ MOV R2, R7 ;\n /*1270*/ MOV R3, R6 ;\n /*1280*/ MOV R29, R29 ;\n /*1290*/ MOV R10, R10 ;\n /*12a0*/ MOV R28, R28 ;\n /*12b0*/ MOV R2, R2 ;\n /*12c0*/ MOV R3, R3 ;\n.L_x_14:\n /*12d0*/ MOV R30, R2 ;\n /*12e0*/ MOV R3, R3 ;\n /*12f0*/ LDL R30, [R30] ;\n /*1300*/ PRMT R32, R30, 0x7770, RZ ;\n /*1310*/ PRMT R33, R30, 0x7771, RZ ;\n /*1320*/ PRMT R31, R30, 0x7772, RZ ;\n /*1330*/ PRMT R30, R30, 0x7773, RZ ;\n /*1340*/ PRMT R32, R32, 0x7770, RZ ;\n /*1350*/ PRMT R32, R32, 0x7710, RZ ;\n /*1360*/ PRMT R33, R33, 0x7770, RZ ;\n /*1370*/ PRMT R33, R33, 0x7710, RZ ;\n /*1380*/ PRMT R31, R31, 0x7770, RZ ;\n /*1390*/ PRMT R34, R31, 0x7710, RZ ;\n /*13a0*/ PRMT R30, R30, 0x7770, RZ ;\n /*13b0*/ PRMT R35, R30, 0x7710, RZ ;\n /*13c0*/ PRMT R30, R32, 0x7610, R30 ;\n /*13d0*/ PRMT R31, R33, 0x7610, R31 ;\n /*13e0*/ PRMT R32, R34, 0x7610, R32 ;\n /*13f0*/ PRMT R33, R35, 0x7610, R33 ;\n /*1400*/ LOP3.LUT R34, R27, 0xff, RZ, 0xc0, !PT ;\n /*1410*/ PRMT R35, R34, 0x9910, RZ ;\n /*1420*/ MOV R35, R35 ;\n /*1430*/ PRMT R30, R30, 0x9910, RZ ;\n /*1440*/ MOV R30, R30 ;\n /*1450*/ ISETP.EQ.AND P0, PT, R30, R35, PT ;\n /*1460*/ PRMT R30, R34, 0x9910, RZ ;\n /*1470*/ MOV R30, R30 ;\n /*1480*/ PRMT R31, R31, 0x9910, RZ ;\n /*1490*/ MOV R31, R31 ;\n /*14a0*/ ISETP.EQ.AND P1, PT, R31, R30, PT ;\n /*14b0*/ PLOP3.LUT P0, PT, P1, P0, PT, 0xa8, 0x0 ;\n /*14c0*/ PRMT R30, R34, 0x9910, RZ ;\n /*14d0*/ MOV R30, R30 ;\n /*14e0*/ PRMT R31, R32, 0x9910, RZ ;\n /*14f0*/ MOV R31, R31 ;\n /*1500*/ ISETP.EQ.AND P1, PT, R31, R30, PT ;\n /*1510*/ PLOP3.LUT P0, PT, P1, P0, PT, 0xa8, 0x0 ;\n /*1520*/ PRMT R30, R34, 0x9910, RZ ;\n /*1530*/ MOV R30, R30 ;\n /*1540*/ PRMT R31, R33, 0x9910, RZ ;\n /*1550*/ MOV R31, R31 ;\n /*1560*/ ISETP.EQ.AND P1, PT, R31, R30, PT ;\n /*1570*/ PLOP3.LUT P0, PT, P1, P0, PT, 0xa8, 0x0 ;\n /*1580*/ SEL R10, RZ, R10, P0 ;\n /*1590*/ IADD3 R28, R28, 0x4, RZ ;\n /*15a0*/ IADD3 R2, P0, R2, 0x4, RZ ;\n /*15b0*/ IADD3.X R3, R3, RZ, RZ, P0, !PT ;\n /*15c0*/ IADD3 R29, R29, -0x4, RZ ;\n /*15d0*/ ISETP.NE.AND P0, PT, R29, RZ, PT ;\n /*15e0*/ MOV R10, R10 ;\n /*15f0*/ MOV R28, R28 ;\n /*1600*/ MOV R2, R2 ;\n /*1610*/ MOV R3, R3 ;\n /*1620*/ MOV R29, R29 ;\n /*1630*/ @P0 BRA `(.L_x_14) ;\n.L_x_13:\n /*1640*/ BSYNC B4 ;\n.L_x_12:\n /*1650*/ ISETP.EQ.AND P0, PT, R26, RZ, PT ;\n /*1660*/ @P0 BRA `(.L_x_11) ;\n /*1670*/ MOV R2, R28 ;\n /*1680*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ;\n /*1690*/ MOV R2, R2 ;\n /*16a0*/ MOV R3, R3 ;\n /*16b0*/ MOV R28, R2 ;\n /*16c0*/ MOV R2, R3 ;\n /*16d0*/ MOV R3, R28 ;\n /*16e0*/ MOV R2, R2 ;\n /*16f0*/ IADD3 R3, P0, R7, R3, RZ ;\n /*1700*/ IADD3.X R2, R6, R2, RZ, P0, !PT ;\n /*1710*/ MOV R28, R3 ;\n /*1720*/ MOV R2, R2 ;\n /*1730*/ LDL.U8 R28, [R28] ;\n /*1740*/ PRMT R28, R28, 0x7770, RZ ;\n /*1750*/ PRMT R28, R28, 0x7710, RZ ;\n /*1760*/ LOP3.LUT R29, R27, 0xff, RZ, 0xc0, !PT ;\n /*1770*/ PRMT R27, R29, 0x9910, RZ ;\n /*1780*/ MOV R27, R27 ;\n /*1790*/ PRMT R28, R28, 0x9910, RZ ;\n /*17a0*/ MOV R28, R28 ;\n /*17b0*/ ISETP.EQ.AND P0, PT, R28, R27, PT ;\n /*17c0*/ SEL R10, RZ, R10, P0 ;\n /*17d0*/ ISETP.EQ.AND P0, PT, R26, 0x1, PT ;\n /*17e0*/ MOV R3, R3 ;\n /*17f0*/ MOV R27, R2 ;\n /*1800*/ PRMT R2, R29, 0x7610, R2 ;\n /*1810*/ MOV R10, R10 ;\n /*1820*/ @P0 BRA `(.L_x_11) ;\n /*1830*/ IADD3 R28, P0, R3, 0x1, RZ ;\n /*1840*/ IADD3.X R29, R27, RZ, RZ, P0, !PT ;\n /*1850*/ MOV R28, R28 ;\n /*1860*/ MOV R29, R29 ;\n /*1870*/ LDL.U8 R28, [R28] ;\n /*1880*/ PRMT R28, R28, 0x7770, RZ ;\n /*1890*/ PRMT R28, R28, 0x7710, RZ ;\n /*18a0*/ PRMT R29, R2, 0x9910, RZ ;\n /*18b0*/ MOV R29, R29 ;\n /*18c0*/ PRMT R28, R28, 0x9910, RZ ;\n /*18d0*/ MOV R28, R28 ;\n /*18e0*/ ISETP.EQ.AND P0, PT, R28, R29, PT ;\n /*18f0*/ SEL R10, RZ, R10, P0 ;\n /*1900*/ ISETP.EQ.AND P0, PT, R26, 0x2, PT ;\n /*1910*/ MOV R10, R10 ;\n /*1920*/ @P0 BRA `(.L_x_11) ;\n /*1930*/ IADD3 R3, P0, R3, 0x2, RZ ;\n /*1940*/ IADD3.X R26, R27, RZ, RZ, P0, !PT ;\n /*1950*/ MOV R3, R3 ;\n /*1960*/ MOV R26, R26 ;\n /*1970*/ LDL.U8 R3, [R3] ;\n /*1980*/ PRMT R3, R3, 0x7770, RZ ;\n /*1990*/ PRMT R3, R3, 0x7710, RZ ;\n /*19a0*/ PRMT R2, R2, 0x9910, RZ ;\n /*19b0*/ MOV R2, R2 ;\n /*19c0*/ PRMT R3, R3, 0x9910, RZ ;\n /*19d0*/ MOV R3, R3 ;\n /*19e0*/ ISETP.EQ.AND P0, PT, R3, R2, PT ;\n /*19f0*/ SEL R10, RZ, R10, P0 ;\n /*1a00*/ MOV R10, R10 ;\n.L_x_11:\n /*1a10*/ BSYNC B3 ;\n.L_x_10:\n /*1a20*/ BSSY B3, `(.L_x_15) ;\n /*1a30*/ @P2 BRA `(.L_x_16) ;\n /*1a40*/ LOP3.LUT R2, RZ, R14, RZ, 0x33, !PT ;\n /*1a50*/ IMNMX R2, R2, -0x2, !PT ;\n /*1a60*/ IADD3 R2, R14, R2, RZ ;\n /*1a70*/ IADD3 R3, R2, 0x2, RZ ;\n /*1a80*/ LOP3.LUT R3, R3, 0x3, RZ, 0xc0, !PT ;\n /*1a90*/ ISETP.EQ.AND P0, PT, R3, RZ, PT ;\n /*1aa0*/ MOV R26, R14 ;\n /*1ab0*/ MOV R28, R25 ;\n /*1ac0*/ MOV R27, R25 ;\n /*1ad0*/ MOV R2, R2 ;\n /*1ae0*/ MOV R3, R3 ;\n /*1af0*/ MOV R26, R26 ;\n /*1b00*/ MOV R28, R28 ;\n /*1b10*/ MOV R27, R27 ;\n /*1b20*/ BSSY B4, `(.L_x_17) ;\n /*1b30*/ @P0 BRA `(.L_x_18) ;\n /*1b40*/ IADD3 R26, R14, -0x1, RZ ;\n /*1b50*/ IADD3 R27, P0, R23, -0x1, RZ ;\n /*1b60*/ IADD3.X R28, R24, -0x1, RZ, P0, !PT ;\n /*1b70*/ MOV R27, R27 ;\n /*1b80*/ MOV R28, R28 ;\n /*1b90*/ LDL.S8 R27, [R27] ;\n /*1ba0*/ PRMT R27, R27, 0x8880, RZ ;\n /*1bb0*/ MOV R27, R27 ;\n /*1bc0*/ IADD3 R28, R25, -0x1, RZ ;\n /*1bd0*/ ISETP.EQ.AND P0, PT, R28, R27, PT ;\n /*1be0*/ IADD3 R29, R25, 0x1, RZ ;\n /*1bf0*/ ISETP.EQ.AND P1, PT, R29, R27, PT ;\n /*1c00*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;\n /*1c10*/ SEL R10, RZ, R10, P0 ;\n /*1c20*/ ISETP.EQ.AND P0, PT, R3, 0x1, PT ;\n /*1c30*/ MOV R26, R26 ;\n /*1c40*/ MOV R27, R28 ;\n /*1c50*/ MOV R28, R29 ;\n /*1c60*/ MOV R10, R10 ;\n /*1c70*/ @P0 BRA `(.L_x_18) ;\n /*1c80*/ IADD3 R26, R14, -0x2, RZ ;\n /*1c90*/ IADD3 R27, P0, R23, -0x2, RZ ;\n /*1ca0*/ IADD3.X R28, R24, -0x1, RZ, P0, !PT ;\n /*1cb0*/ MOV R27, R27 ;\n /*1cc0*/ MOV R28, R28 ;\n /*1cd0*/ LDL.S8 R27, [R27] ;\n /*1ce0*/ PRMT R27, R27, 0x8880, RZ ;\n /*1cf0*/ MOV R27, R27 ;\n /*1d00*/ IADD3 R28, R25, -0x2, RZ ;\n /*1d10*/ ISETP.EQ.AND P0, PT, R28, R27, PT ;\n /*1d20*/ IADD3 R29, R25, 0x2, RZ ;\n /*1d30*/ ISETP.EQ.AND P1, PT, R29, R27, PT ;\n /*1d40*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;\n /*1d50*/ SEL R10, RZ, R10, P0 ;\n /*1d60*/ ISETP.EQ.AND P0, PT, R3, 0x2, PT ;\n /*1d70*/ MOV R26, R26 ;\n /*1d80*/ MOV R27, R28 ;\n /*1d90*/ MOV R28, R29 ;\n /*1da0*/ MOV R10, R10 ;\n /*1db0*/ @P0 BRA `(.L_x_18) ;\n /*1dc0*/ IADD3 R26, R14, -0x3, RZ ;\n /*1dd0*/ IADD3 R3, P0, R23, -0x3, RZ ;\n /*1de0*/ IADD3.X R23, R24, -0x1, RZ, P0, !PT ;\n /*1df0*/ MOV R3, R3 ;\n /*1e00*/ MOV R23, R23 ;\n /*1e10*/ LDL.S8 R3, [R3] ;\n /*1e20*/ PRMT R3, R3, 0x8880, RZ ;\n /*1e30*/ MOV R3, R3 ;\n /*1e40*/ IADD3 R27, R25, -0x3, RZ ;\n /*1e50*/ ISETP.EQ.AND P0, PT, R27, R3, PT ;\n /*1e60*/ IADD3 R25, R25, 0x3, RZ ;\n /*1e70*/ ISETP.EQ.AND P1, PT, R25, R3, PT ;\n /*1e80*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;\n /*1e90*/ SEL R10, RZ, R10, P0 ;\n /*1ea0*/ MOV R26, R26 ;\n /*1eb0*/ MOV R27, R27 ;\n /*1ec0*/ MOV R28, R25 ;\n /*1ed0*/ MOV R10, R10 ;\n.L_x_18:\n /*1ee0*/ BSYNC B4 ;\n.L_x_17:\n /*1ef0*/ IADD3 R2, R2, 0x1, RZ ;\n /*1f00*/ ISETP.LT.U32.AND P0, PT, R2, 0x3, PT ;\n /*1f10*/ @P0 BRA `(.L_x_16) ;\n.L_x_19:\n /*1f20*/ MOV R2, R26 ;\n /*1f30*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ;\n /*1f40*/ MOV R2, R2 ;\n /*1f50*/ MOV R3, R3 ;\n /*1f60*/ MOV R23, R2 ;\n /*1f70*/ MOV R2, R3 ;\n /*1f80*/ MOV R3, R23 ;\n /*1f90*/ MOV R2, R2 ;\n /*1fa0*/ IADD3 R3, P0, R7, R3, RZ ;\n /*1fb0*/ IADD3.X R2, R6, R2, RZ, P0, !PT ;\n /*1fc0*/ IADD3 R23, P0, R3, -0x1, RZ ;\n /*1fd0*/ IADD3.X R24, R2, -0x1, RZ, P0, !PT ;\n /*1fe0*/ MOV R23, R23 ;\n /*1ff0*/ MOV R24, R24 ;\n /*2000*/ LDL.S8 R23, [R23] ;\n /*2010*/ PRMT R23, R23, 0x8880, RZ ;\n /*2020*/ MOV R23, R23 ;\n /*2030*/ IADD3 R24, R27, -0x1, RZ ;\n /*2040*/ ISETP.EQ.AND P0, PT, R24, R23, PT ;\n /*2050*/ IADD3 R24, R28, 0x1, RZ ;\n /*2060*/ ISETP.EQ.AND P1, PT, R24, R23, PT ;\n /*2070*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;\n /*2080*/ IADD3 R23, P1, R3, -0x2, RZ ;\n /*2090*/ IADD3.X R24, R2, -0x1, RZ, P1, !PT ;\n /*20a0*/ MOV R23, R23 ;\n /*20b0*/ MOV R24, R24 ;\n /*20c0*/ LDL.S8 R23, [R23] ;\n /*20d0*/ PRMT R23, R23, 0x8880, RZ ;\n /*20e0*/ MOV R23, R23 ;\n /*20f0*/ IADD3 R24, R27, -0x2, RZ ;\n /*2100*/ ISETP.EQ.AND P1, PT, R24, R23, PT ;\n /*2110*/ IADD3 R24, R28, 0x2, RZ ;\n /*2120*/ ISETP.EQ.AND P2, PT, R24, R23, PT ;\n /*2130*/ PLOP3.LUT P1, PT, P1, P2, PT, 0xa8, 0x0 ;\n /*2140*/ PLOP3.LUT P0, PT, P1, P0, PT, 0xa8, 0x0 ;\n /*2150*/ IADD3 R23, P1, R3, -0x3, RZ ;\n /*2160*/ IADD3.X R24, R2, -0x1, RZ, P1, !PT ;\n /*2170*/ MOV R23, R23 ;\n /*2180*/ MOV R24, R24 ;\n /*2190*/ LDL.S8 R23, [R23] ;\n /*21a0*/ PRMT R23, R23, 0x8880, RZ ;\n /*21b0*/ MOV R23, R23 ;\n /*21c0*/ IADD3 R24, R27, -0x3, RZ ;\n /*21d0*/ ISETP.EQ.AND P1, PT, R24, R23, PT ;\n /*21e0*/ IADD3 R24, R28, 0x3, RZ ;\n /*21f0*/ ISETP.EQ.AND P2, PT, R24, R23, PT ;\n /*2200*/ PLOP3.LUT P1, PT, P1, P2, PT, 0xa8, 0x0 ;\n /*2210*/ PLOP3.LUT P0, PT, P1, P0, PT, 0xa8, 0x0 ;\n /*2220*/ IADD3 R23, R26, -0x4, RZ ;\n /*2230*/ IADD3 R3, P1, R3, -0x4, RZ ;\n /*2240*/ IADD3.X R24, R2, -0x1, RZ, P1, !PT ;\n /*2250*/ MOV R2, R3 ;\n /*2260*/ MOV R3, R24 ;\n /*2270*/ LDL.S8 R2, [R2] ;\n /*2280*/ PRMT R2, R2, 0x8880, RZ ;\n /*2290*/ MOV R2, R2 ;\n /*22a0*/ IADD3 R27, R27, -0x4, RZ ;\n /*22b0*/ ISETP.EQ.AND P1, PT, R27, R2, PT ;\n /*22c0*/ IADD3 R28, R28, 0x4, RZ ;\n /*22d0*/ ISETP.EQ.AND P2, PT, R28, R2, PT ;\n /*22e0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0xa8, 0x0 ;\n /*22f0*/ PLOP3.LUT P0, PT, P1, P0, PT, 0xa8, 0x0 ;\n /*2300*/ SEL R10, RZ, R10, P0 ;\n /*2310*/ ISETP.GT.AND P0, PT, R26, 0x4, PT ;\n /*2320*/ MOV R23, R23 ;\n /*2330*/ MOV R27, R27 ;\n /*2340*/ MOV R28, R28 ;\n /*2350*/ MOV R10, R10 ;\n /*2360*/ MOV R26, R23 ;\n /*2370*/ @P0 BRA `(.L_x_19) ;\n.L_x_16:\n /*2380*/ BSYNC B3 ;\n.L_x_15:\n /*2390*/ LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ;\n /*23a0*/ PRMT R2, R10, 0x9910, RZ ;\n /*23b0*/ MOV R2, R2 ;\n /*23c0*/ ISETP.EQ.AND P0, PT, R2, RZ, PT ;\n /*23d0*/ @P0 BREAK B0 ;\n /*23e0*/ @P0 BRA `(.L_x_20) ;\n /*23f0*/ IADD3 R13, P0, R13, 0x1, RZ ;\n /*2400*/ IADD3.X R23, R12, RZ, RZ, P0, !PT ;\n /*2410*/ MOV R10, 0x1 ;\n /*2420*/ MOV R12, RZ ;\n /*2430*/ MOV R11, R11 ;\n /*2440*/ PRMT R2, R11, 0x8880, RZ ;\n /*2450*/ MOV R2, R2 ;\n /*2460*/ MOV R2, R2 ;\n /*2470*/ MOV R2, R2 ;\n /*2480*/ MOV R3, R2 ;\n /*2490*/ MOV R2, RZ ;\n /*24a0*/ SHF.L.U64.HI R2, R10, R3, R12 ;\n /*24b0*/ SHF.L.U32 R2, R10, R3, RZ ;\n /*24c0*/ MOV R2, R2 ;\n /*24d0*/ LOP3.LUT R0, R0, R2, RZ, 0xfc, !PT ;\n /*24e0*/ IADD3 R14, R14, 0x1, RZ ;\n /*24f0*/ ISETP.NE.AND P0, PT, R14, R9, PT ;\n /*2500*/ MOV R13, R13 ;\n /*2510*/ MOV R12, R23 ;\n /*2520*/ MOV R0, R0 ;\n /*2530*/ MOV R14, R14 ;\n /*2540*/ @P0 BREAK B0 ;\n /*2550*/ @P0 BRA `(.L_x_20) ;\n /*2560*/ IADD3 R16, P0, R16, 0x1, RZ ;\n /*2570*/ IADD3.X R15, R15, RZ, RZ, P0, !PT ;\n /*2580*/ MOV R14, R9 ;\n /*2590*/ MOV R16, R16 ;\n /*25a0*/ MOV R15, R15 ;\n /*25b0*/ MOV R14, R14 ;\n /*25c0*/ BRA `(.L_x_21) ;\n.L_x_9:\n /*25d0*/ MOV R2, R14 ;\n /*25e0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ;\n /*25f0*/ MOV R2, R2 ;\n /*2600*/ MOV R3, R3 ;\n /*2610*/ MOV R23, R2 ;\n /*2620*/ MOV R24, R3 ;\n /*2630*/ MOV R23, R23 ;\n /*2640*/ MOV R24, R24 ;\n /*2650*/ IADD3 R23, P0, R7, R23, RZ ;\n /*2660*/ IADD3.X R24, R6, R24, RZ, P0, !PT ;\n /*2670*/ MOV R2, R23 ;\n /*2680*/ MOV R3, R24 ;\n /*2690*/ LDL.U8 R2, [R2] ;\n /*26a0*/ PRMT R2, R2, 0x7770, RZ ;\n /*26b0*/ PRMT R2, R2, 0x7710, RZ ;\n /*26c0*/ IADD3 R2, R2, 0x1, RZ ;\n /*26d0*/ MOV R10, R23 ;\n /*26e0*/ MOV R3, R24 ;\n /*26f0*/ PRMT R3, R2, 0x7610, R3 ;\n /*2700*/ STL.U8 [R10], R3 ;\n /*2710*/ PRMT R11, R2, 0x7710, RZ ;\n /*2720*/ MOV R11, R11 ;\n /*2730*/ PRMT R3, R11, 0x7610, R3 ;\n /*2740*/ PRMT R3, R3, 0x8880, RZ ;\n /*2750*/ MOV R3, R3 ;\n /*2760*/ MOV R3, R3 ;\n /*2770*/ ISETP.EQ.AND P0, PT, R3, R9, PT ;\n /*2780*/ MOV R23, R23 ;\n /*2790*/ MOV R24, R24 ;\n /*27a0*/ PRMT R27, R2, 0x7610, R27 ;\n /*27b0*/ MOV R11, R11 ;\n /*27c0*/ MOV R25, R3 ;\n /*27d0*/ BSSY B1, `(.L_x_22) ;\n /*27e0*/ BSSY B0, `(.L_x_23) ;\n /*27f0*/ @P0 BRA `(.L_x_24) ;\n /*2800*/ BRA `(.L_x_25) ;\n.L_x_24:\n /*2810*/ MOV R2, 0xff ;\n /*2820*/ MOV R2, R2 ;\n /*2830*/ MOV R23, R23 ;\n /*2840*/ MOV R24, R24 ;\n /*2850*/ MOV R2, R2 ;\n /*2860*/ STL.U8 [R23], R2 ;\n.L_x_21:\n /*2870*/ BSYNC B0 ;\n.L_x_23:\n /*2880*/ IADD3 R14, R14, -0x1, RZ ;\n /*2890*/ MOV R2, R14 ;\n /*28a0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ;\n /*28b0*/ MOV R2, R2 ;\n /*28c0*/ MOV R3, R3 ;\n /*28d0*/ MOV R10, R2 ;\n /*28e0*/ MOV R3, R3 ;\n /*28f0*/ MOV R2, R10 ;\n /*2900*/ MOV R3, R3 ;\n /*2910*/ IADD3 R2, P0, R7, R2, RZ ;\n /*2920*/ IADD3.X R3, R6, R3, RZ, P0, !PT ;\n /*2930*/ MOV R2, R2 ;\n /*2940*/ MOV R3, R3 ;\n /*2950*/ LDL.S8 R2, [R2] ;\n /*2960*/ PRMT R2, R2, 0x8880, RZ ;\n /*2970*/ MOV R2, R2 ;\n /*2980*/ MOV R10, 0x1 ;\n /*2990*/ MOV R11, RZ ;\n /*29a0*/ MOV R2, R2 ;\n /*29b0*/ MOV R3, R2 ;\n /*29c0*/ MOV R2, RZ ;\n /*29d0*/ SHF.L.U64.HI R2, R10, R3, R11 ;\n /*29e0*/ SHF.L.U32 R2, R10, R3, RZ ;\n /*29f0*/ MOV R2, R2 ;\n /*2a00*/ LOP3.LUT R2, RZ, R2, RZ, 0x33, !PT ;\n /*2a10*/ LOP3.LUT R0, R0, R2, RZ, 0xc0, !PT ;\n /*2a20*/ MOV R14, R14 ;\n /*2a30*/ MOV R0, R0 ;\n /*2a40*/ BRA `(.L_x_20) ;\n.L_x_25:\n /*2a50*/ MOV R2, 0x1 ;\n /*2a60*/ SHF.L.U32 R2, R2, R25, RZ ;\n /*2a70*/ LOP3.LUT R2, R2, R0, RZ, 0xc0, !PT ;\n /*2a80*/ ISETP.NE.AND P0, PT, R2, RZ, PT ;\n /*2a90*/ @P0 BREAK B0 ;\n /*2aa0*/ @P0 BRA `(.L_x_20) ;\n /*2ab0*/ BRA `(.L_x_26) ;\n.L_x_20:\n /*2ac0*/ BSYNC B1 ;\n.L_x_22:\n /*2ad0*/ ISETP.GE.AND P0, PT, R14, R8, PT ;\n /*2ae0*/ @P0 BRA `(.L_x_9) ;\n /*2af0*/ BSYNC B2 ;\n.L_x_8:\n /*2b00*/ SHF.L.U64.HI R6, R5, 0x3, R4 ;\n /*2b10*/ SHF.L.U32 R0, R5, 0x3, RZ ;\n /*2b20*/ IADD3 R4, P0, R22, R0, RZ ;\n /*2b30*/ IADD3.X R5, R21, R6, RZ, P0, !PT ;\n /*2b40*/ MOV R4, R4 ;\n /*2b50*/ MOV R5, R5 ;\n /*2b60*/ MOV R2, R16 ;\n /*2b70*/ MOV R3, R15 ;\n /*2b80*/ MOV R4, R4 ;\n /*2b90*/ MOV R5, R5 ;\n /*2ba0*/ R2UR UR4, R18 ;\n /*2bb0*/ R2UR UR5, R19 ;\n /*2bc0*/ STG.E.64 [R4.64], R2 ;\n /*2bd0*/ IADD3 R2, P0, R20, R0, RZ ;\n /*2be0*/ IADD3.X R3, R17, R6, RZ, P0, !PT ;\n /*2bf0*/ MOV R2, R2 ;\n /*2c00*/ MOV R3, R3 ;\n /*2c10*/ LOP3.LUT R13, R13, R12, RZ, 0x3c, !PT ;\n /*2c20*/ LOP3.LUT R12, R13, R12, RZ, 0x3c, !PT ;\n /*2c30*/ LOP3.LUT R13, R13, R12, RZ, 0x3c, !PT ;\n /*2c40*/ MOV R2, R2 ;\n /*2c50*/ MOV R3, R3 ;\n /*2c60*/ R2UR UR4, R18 ;\n /*2c70*/ R2UR UR5, R19 ;\n /*2c80*/ STG.E.64 [R2.64], R12 ;\n.L_x_1:\n /*2c90*/ EXIT ;\n.L_x_27:\n /*2ca0*/ BRA `(.L_x_27);\n /*2cb0*/ NOP;\n /*2cc0*/ NOP;\n /*2cd0*/ NOP;\n /*2ce0*/ NOP;\n /*2cf0*/ NOP;\n /*2d00*/ NOP;\n /*2d10*/ NOP;\n /*2d20*/ NOP;\n /*2d30*/ NOP;\n /*2d40*/ NOP;\n /*2d50*/ NOP;\n /*2d60*/ NOP;\n /*2d70*/ NOP;\n.L_x_28:\n"},"hip":{"kind":"string","value":"\t.text\n\t.amdgcn_target \"amdgcn-amd-amdhsa--gfx1100\"\n\t.protected\t_Z18BP_queens_root_dfsijiPK10queen_rootPyS2_ ; -- Begin function _Z18BP_queens_root_dfsijiPK10queen_rootPyS2_\n\t.globl\t_Z18BP_queens_root_dfsijiPK10queen_rootPyS2_\n\t.p2align\t8\n\t.type\t_Z18BP_queens_root_dfsijiPK10queen_rootPyS2_,@function\n_Z18BP_queens_root_dfsijiPK10queen_rootPyS2_: ; @_Z18BP_queens_root_dfsijiPK10queen_rootPyS2_\n; %bb.0:\n\ts_clause 0x1\n\ts_load_b32 s8, s[2:3], 0x34\n\ts_load_b128 s[4:7], s[2:3], 0x0\n\tv_and_b32_e32 v3, 0x3ff, v0\n\ts_waitcnt lgkmcnt(0)\n\ts_and_b32 s7, s8, 0xffff\n\ts_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)\n\tv_mad_u64_u32 v[1:2], null, s15, s7, v[3:4]\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmp_gt_u32_e32 vcc_lo, s5, v1\n\ts_and_saveexec_b32 s5, vcc_lo\n\ts_cbranch_execz .LBB0_36\n; %bb.1:\n\ts_load_b64 s[8:9], s[0:1], 0x4\n\tv_bfe_u32 v2, v0, 10, 10\n\tv_bfe_u32 v0, v0, 20, 10\n\ts_waitcnt lgkmcnt(0)\n\ts_lshr_b32 s0, s8, 16\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)\n\tv_mul_u32_u24_e32 v2, s9, v2\n\ts_mul_i32 s0, s0, s9\n\ts_cmp_lt_i32 s4, 1\n\tv_mul_lo_u32 v3, s0, v3\n\ts_load_b64 s[0:1], s[2:3], 0x10\n\tv_add3_u32 v0, v3, v2, v0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_mul_lo_u32 v0, v0, 20\n\ts_cbranch_scc1 .LBB0_7\n; %bb.2:\n\ts_cmp_eq_u32 s4, 1\n\ts_mov_b32 s5, 0\n\ts_cbranch_scc1 .LBB0_5\n; %bb.3:\n\tv_mov_b32_e32 v2, -1\n\ts_and_b32 s5, s4, 0x7ffffffe\n\ts_mov_b32 s7, 0\n.LBB0_4: ; =>This Inner Loop Header: Depth=1\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\tv_add_nc_u32_e32 v3, s7, v0\n\ts_add_i32 s7, s7, 2\n\ts_cmp_lg_u32 s5, s7\n\tds_store_b16 v3, v2\n\ts_cbranch_scc1 .LBB0_4\n.LBB0_5:\n\ts_bitcmp0_b32 s4, 0\n\ts_cbranch_scc1 .LBB0_7\n; %bb.6:\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_dual_mov_b32 v3, 0xff :: v_dual_add_nc_u32 v2, s5, v0\n\tds_store_b8 v2, v3\n.LBB0_7:\n\tv_ashrrev_i32_e32 v2, 31, v1\n\ts_load_b128 s[8:11], s[2:3], 0x18\n\ts_cmp_lt_i32 s6, 1\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)\n\tv_lshlrev_b64 v[3:4], 4, v[1:2]\n\ts_waitcnt lgkmcnt(0)\n\tv_add_co_u32 v5, vcc_lo, s0, v3\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo\n\tglobal_load_b32 v7, v[5:6], off\n\ts_cbranch_scc1 .LBB0_13\n; %bb.8:\n\ts_cmp_eq_u32 s6, 1\n\ts_mov_b32 s2, 0\n\ts_cbranch_scc1 .LBB0_11\n; %bb.9:\n\tv_add_co_u32 v5, vcc_lo, v5, 4\n\tv_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo\n\ts_and_b32 s2, s6, 0x7ffffffe\n\ts_mov_b32 s3, 0\n.LBB0_10: ; =>This Inner Loop Header: Depth=1\n\tglobal_load_u16 v8, v[5:6], off\n\tv_add_co_u32 v5, vcc_lo, v5, 2\n\tv_add_nc_u32_e32 v9, s3, v0\n\tv_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo\n\ts_add_i32 s3, s3, 2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_cmp_lg_u32 s2, s3\n\ts_waitcnt vmcnt(0)\n\tds_store_b16 v9, v8\n\ts_cbranch_scc1 .LBB0_10\n.LBB0_11:\n\ts_bitcmp0_b32 s6, 0\n\ts_cbranch_scc1 .LBB0_13\n; %bb.12:\n\ts_add_u32 s0, s2, s0\n\ts_addc_u32 s1, 0, s1\n\tv_add_co_u32 v3, vcc_lo, s0, v3\n\tv_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo\n\tglobal_load_u8 v3, v[3:4], off offset:4\n\tv_add_nc_u32_e32 v4, s2, v0\n\ts_waitcnt vmcnt(0)\n\tds_store_b8 v4, v3\n.LBB0_13:\n\tv_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v8, 0xff\n\tv_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v9, s6\n\ts_mov_b32 s2, 0\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3\n\ts_branch .LBB0_15\n.LBB0_14: ; in Loop: Header=BB0_15 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\tv_cmp_gt_i32_e32 vcc_lo, s6, v9\n\ts_or_b32 s2, vcc_lo, s2\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_not1_b32 exec_lo, exec_lo, s2\n\ts_cbranch_execz .LBB0_35\n.LBB0_15: ; =>This Loop Header: Depth=1\n ; Child Loop BB0_23 Depth 2\n ; Child Loop BB0_26 Depth 2\n\ts_delay_alu instid0(VALU_DEP_2)\n\tv_add_nc_u32_e32 v11, v0, v9\n\ts_mov_b32 s0, 0\n\ts_mov_b32 s1, exec_lo\n\tds_load_u8 v10, v11\n\ts_waitcnt lgkmcnt(0)\n\tv_add_nc_u16 v12, v10, 1\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_bfe_i32 v10, v12, 0, 8\n\tds_store_b8 v11, v12\n\tv_cmpx_ne_u32_e64 s4, v10\n\ts_xor_b32 s3, exec_lo, s1\n\ts_cbranch_execnz .LBB0_18\n; %bb.16: ; in Loop: Header=BB0_15 Depth=1\n\ts_or_saveexec_b32 s1, s3\n\tv_mov_b32_e32 v10, s4\n\ts_xor_b32 exec_lo, exec_lo, s1\n\ts_cbranch_execnz .LBB0_33\n.LBB0_17: ; in Loop: Header=BB0_15 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB0_14\n\ts_branch .LBB0_34\n.LBB0_18: ; in Loop: Header=BB0_15 Depth=1\n\ts_waitcnt vmcnt(0)\n\tv_bfe_u32 v11, v7, v10, 1\n\ts_mov_b32 s5, exec_lo\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_cmpx_eq_u32_e32 0, v11\n\ts_cbranch_execz .LBB0_32\n; %bb.19: ; in Loop: Header=BB0_15 Depth=1\n\tv_cmp_lt_i32_e32 vcc_lo, 0, v9\n\ts_mov_b32 s7, -1\n\ts_and_saveexec_b32 s12, vcc_lo\n\ts_cbranch_execnz .LBB0_22\n; %bb.20: ; in Loop: Header=BB0_15 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s12\n\tv_add_nc_u32_e32 v11, 1, v9\n\ts_and_saveexec_b32 s12, vcc_lo\n\ts_cbranch_execnz .LBB0_25\n.LBB0_21: ; in Loop: Header=BB0_15 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s12\n\ts_mov_b32 s1, 0\n\ts_and_saveexec_b32 s0, s7\n\ts_cbranch_execnz .LBB0_28\n\ts_branch .LBB0_31\n.LBB0_22: ; in Loop: Header=BB0_15 Depth=1\n\tv_dual_mov_b32 v12, v9 :: v_dual_and_b32 v11, 0xff, v12\n\tv_mov_b32_e32 v13, v0\n\ts_mov_b32 s13, -1\n\ts_mov_b32 s7, 0\n ; implicit-def: $sgpr14\n.LBB0_23: ; Parent Loop BB0_15 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tds_load_u8 v14, v13\n\tv_add_nc_u32_e32 v12, -1, v12\n\tv_add_nc_u32_e32 v13, 1, v13\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)\n\tv_cmp_eq_u32_e64 s1, 0, v12\n\ts_waitcnt lgkmcnt(0)\n\tv_cmp_ne_u16_e64 s0, v14, v11\n\ts_and_b32 s13, s0, s13\n\ts_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)\n\ts_or_b32 s7, s1, s7\n\ts_and_not1_b32 s0, s14, exec_lo\n\ts_and_b32 s1, s13, exec_lo\n\ts_or_b32 s14, s0, s1\n\ts_and_not1_b32 exec_lo, exec_lo, s7\n\ts_cbranch_execnz .LBB0_23\n; %bb.24: ; in Loop: Header=BB0_15 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s7\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_not1_b32 s7, s14, exec_lo\n\ts_or_b32 exec_lo, exec_lo, s12\n\tv_add_nc_u32_e32 v11, 1, v9\n\ts_and_saveexec_b32 s12, vcc_lo\n\ts_cbranch_execz .LBB0_21\n.LBB0_25: ; in Loop: Header=BB0_15 Depth=1\n\tv_add_nc_u32_e32 v12, 1, v9\n\tv_add_nc_u32_e32 v13, 1, v10\n\tv_add_nc_u32_e32 v14, -1, v10\n\ts_mov_b32 s13, 0\n\ts_mov_b32 s15, s7\n ; implicit-def: $sgpr14\n\t.p2align\t6\n.LBB0_26: ; Parent Loop BB0_15 Depth=1\n ; => This Inner Loop Header: Depth=2\n\tv_add3_u32 v15, v0, v12, -2\n\tv_add_nc_u32_e32 v12, -1, v12\n\tds_load_i8 v15, v15\n\tv_cmp_gt_u32_e64 s1, 2, v12\n\ts_waitcnt lgkmcnt(0)\n\tv_cmp_ne_u32_e32 vcc_lo, v14, v15\n\tv_cmp_ne_u32_e64 s0, v13, v15\n\tv_add_nc_u32_e32 v13, 1, v13\n\tv_add_nc_u32_e32 v14, -1, v14\n\ts_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)\n\ts_and_b32 s0, vcc_lo, s0\n\ts_and_b32 s15, s0, s15\n\ts_or_b32 s13, s1, s13\n\ts_and_not1_b32 s0, s14, exec_lo\n\ts_and_b32 s1, s15, exec_lo\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_or_b32 s14, s0, s1\n\ts_and_not1_b32 exec_lo, exec_lo, s13\n\ts_cbranch_execnz .LBB0_26\n; %bb.27: ; in Loop: Header=BB0_15 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s13\n\ts_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)\n\ts_and_not1_b32 s0, s7, exec_lo\n\ts_and_b32 s1, s14, exec_lo\n\ts_or_b32 s7, s0, s1\n\ts_or_b32 exec_lo, exec_lo, s12\n\ts_mov_b32 s1, 0\n\ts_and_saveexec_b32 s0, s7\n\ts_cbranch_execz .LBB0_31\n.LBB0_28: ; in Loop: Header=BB0_15 Depth=1\n\tv_lshlrev_b64 v[9:10], v10, 1\n\tv_add_co_u32 v5, vcc_lo, v5, 1\n\tv_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo\n\ts_mov_b32 s7, exec_lo\n\ts_delay_alu instid0(VALU_DEP_3)\n\tv_or_b32_e32 v7, v7, v9\n\tv_cmpx_eq_u32_e64 s4, v11\n\ts_xor_b32 s7, exec_lo, s7\n; %bb.29: ; in Loop: Header=BB0_15 Depth=1\n\tv_add_co_u32 v3, vcc_lo, v3, 1\n\ts_mov_b32 s1, exec_lo\n\tv_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo\n ; implicit-def: $vgpr11\n; %bb.30: ; in Loop: Header=BB0_15 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s7\n\tv_mov_b32_e32 v9, v11\n\ts_and_b32 s1, s1, exec_lo\n.LBB0_31: ; in Loop: Header=BB0_15 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s0\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_b32 s0, s1, exec_lo\n.LBB0_32: ; in Loop: Header=BB0_15 Depth=1\n\ts_or_b32 exec_lo, exec_lo, s5\n\ts_delay_alu instid0(SALU_CYCLE_1)\n\ts_and_b32 s0, s0, exec_lo\n ; implicit-def: $vgpr11\n\ts_or_saveexec_b32 s1, s3\n\tv_mov_b32_e32 v10, s4\n\ts_xor_b32 exec_lo, exec_lo, s1\n\ts_cbranch_execz .LBB0_17\n.LBB0_33: ; in Loop: Header=BB0_15 Depth=1\n\tv_mov_b32_e32 v10, v9\n\ts_or_b32 s0, s0, exec_lo\n\tds_store_b8 v11, v8\n ; implicit-def: $vgpr9\n\ts_or_b32 exec_lo, exec_lo, s1\n\ts_and_saveexec_b32 s1, s0\n\ts_cbranch_execz .LBB0_14\n.LBB0_34: ; in Loop: Header=BB0_15 Depth=1\n\tv_add_nc_u32_e32 v9, -1, v10\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)\n\tv_add_nc_u32_e32 v10, v0, v9\n\tds_load_i8 v10, v10\n\ts_waitcnt lgkmcnt(0)\n\tv_lshlrev_b64 v[10:11], v10, 1\n\tv_not_b32_e32 v10, v10\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1)\n\tv_and_b32_e32 v7, v7, v10\n\ts_branch .LBB0_14\n.LBB0_35:\n\ts_or_b32 exec_lo, exec_lo, s2\n\tv_lshlrev_b64 v[0:1], 3, v[1:2]\n\ts_waitcnt vmcnt(0)\n\ts_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)\n\tv_add_co_u32 v7, vcc_lo, s10, v0\n\tv_add_co_ci_u32_e32 v8, vcc_lo, s11, v1, vcc_lo\n\tv_add_co_u32 v0, vcc_lo, s8, v0\n\tv_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo\n\tglobal_store_b64 v[7:8], v[3:4], off\n\tglobal_store_b64 v[0:1], v[5:6], off\n.LBB0_36:\n\ts_nop 0\n\ts_sendmsg sendmsg(MSG_DEALLOC_VGPRS)\n\ts_endpgm\n\t.section\t.rodata,\"a\",@progbits\n\t.p2align\t6, 0x0\n\t.amdhsa_kernel _Z18BP_queens_root_dfsijiPK10queen_rootPyS2_\n\t\t.amdhsa_group_segment_fixed_size 20480\n\t\t.amdhsa_private_segment_fixed_size 0\n\t\t.amdhsa_kernarg_size 296\n\t\t.amdhsa_user_sgpr_count 15\n\t\t.amdhsa_user_sgpr_dispatch_ptr 1\n\t\t.amdhsa_user_sgpr_queue_ptr 0\n\t\t.amdhsa_user_sgpr_kernarg_segment_ptr 1\n\t\t.amdhsa_user_sgpr_dispatch_id 0\n\t\t.amdhsa_user_sgpr_private_segment_size 0\n\t\t.amdhsa_wavefront_size32 1\n\t\t.amdhsa_uses_dynamic_stack 0\n\t\t.amdhsa_enable_private_segment 0\n\t\t.amdhsa_system_sgpr_workgroup_id_x 1\n\t\t.amdhsa_system_sgpr_workgroup_id_y 0\n\t\t.amdhsa_system_sgpr_workgroup_id_z 0\n\t\t.amdhsa_system_sgpr_workgroup_info 0\n\t\t.amdhsa_system_vgpr_workitem_id 2\n\t\t.amdhsa_next_free_vgpr 16\n\t\t.amdhsa_next_free_sgpr 16\n\t\t.amdhsa_float_round_mode_32 0\n\t\t.amdhsa_float_round_mode_16_64 0\n\t\t.amdhsa_float_denorm_mode_32 3\n\t\t.amdhsa_float_denorm_mode_16_64 3\n\t\t.amdhsa_dx10_clamp 1\n\t\t.amdhsa_ieee_mode 1\n\t\t.amdhsa_fp16_overflow 0\n\t\t.amdhsa_workgroup_processor_mode 1\n\t\t.amdhsa_memory_ordered 1\n\t\t.amdhsa_forward_progress 0\n\t\t.amdhsa_shared_vgpr_count 0\n\t\t.amdhsa_exception_fp_ieee_invalid_op 0\n\t\t.amdhsa_exception_fp_denorm_src 0\n\t\t.amdhsa_exception_fp_ieee_div_zero 0\n\t\t.amdhsa_exception_fp_ieee_overflow 0\n\t\t.amdhsa_exception_fp_ieee_underflow 0\n\t\t.amdhsa_exception_fp_ieee_inexact 0\n\t\t.amdhsa_exception_int_div_zero 0\n\t.end_amdhsa_kernel\n\t.text\n.Lfunc_end0:\n\t.size\t_Z18BP_queens_root_dfsijiPK10queen_rootPyS2_, .Lfunc_end0-_Z18BP_queens_root_dfsijiPK10queen_rootPyS2_\n ; -- End function\n\t.section\t.AMDGPU.csdata,\"\",@progbits\n; Kernel info:\n; codeLenInByte = 1228\n; NumSgprs: 18\n; NumVgprs: 16\n; ScratchSize: 0\n; MemoryBound: 0\n; FloatMode: 240\n; IeeeMode: 1\n; LDSByteSize: 20480 bytes/workgroup (compile time only)\n; SGPRBlocks: 2\n; VGPRBlocks: 1\n; NumSGPRsForWavesPerEU: 18\n; NumVGPRsForWavesPerEU: 16\n; Occupancy: 16\n; WaveLimiterHint : 0\n; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0\n; COMPUTE_PGM_RSRC2:USER_SGPR: 15\n; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0\n; COMPUTE_PGM_RSRC2:TGID_X_EN: 1\n; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0\n; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0\n; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2\n\t.text\n\t.p2alignl 7, 3214868480\n\t.fill 96, 4, 3214868480\n\t.type\t__hip_cuid_,@object ; @__hip_cuid_\n\t.section\t.bss,\"aw\",@nobits\n\t.globl\t__hip_cuid_\n__hip_cuid_:\n\t.byte\t0 ; 0x0\n\t.size\t__hip_cuid_, 1\n\n\t.ident\t\"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.0 24455 f24aa3b4a91f6ee2fcd15629ba0b49fa545d8d6b)\"\n\t.section\t\".note.GNU-stack\",\"\",@progbits\n\t.amdgpu_metadata\n---\namdhsa.kernels:\n - .args:\n - .offset: 0\n .size: 4\n .value_kind: by_value\n - .offset: 4\n .size: 4\n .value_kind: by_value\n - .offset: 8\n .size: 4\n .value_kind: by_value\n - .actual_access: read_only\n .address_space: global\n .offset: 16\n .size: 8\n .value_kind: global_buffer\n - .actual_access: write_only\n .address_space: global\n .offset: 24\n .size: 8\n .value_kind: global_buffer\n - .actual_access: write_only\n .address_space: global\n .offset: 32\n .size: 8\n .value_kind: global_buffer\n - .offset: 40\n .size: 4\n .value_kind: hidden_block_count_x\n - .offset: 44\n .size: 4\n .value_kind: hidden_block_count_y\n - .offset: 48\n .size: 4\n .value_kind: hidden_block_count_z\n - .offset: 52\n .size: 2\n .value_kind: hidden_group_size_x\n - .offset: 54\n .size: 2\n .value_kind: hidden_group_size_y\n - .offset: 56\n .size: 2\n .value_kind: hidden_group_size_z\n - .offset: 58\n .size: 2\n .value_kind: hidden_remainder_x\n - .offset: 60\n .size: 2\n .value_kind: hidden_remainder_y\n - .offset: 62\n .size: 2\n .value_kind: hidden_remainder_z\n - .offset: 80\n .size: 8\n .value_kind: hidden_global_offset_x\n - .offset: 88\n .size: 8\n .value_kind: hidden_global_offset_y\n - .offset: 96\n .size: 8\n .value_kind: hidden_global_offset_z\n - .offset: 104\n .size: 2\n .value_kind: hidden_grid_dims\n .group_segment_fixed_size: 20480\n .kernarg_segment_align: 8\n .kernarg_segment_size: 296\n .language: OpenCL C\n .language_version:\n - 2\n - 0\n .max_flat_workgroup_size: 1024\n .name: _Z18BP_queens_root_dfsijiPK10queen_rootPyS2_\n .private_segment_fixed_size: 0\n .sgpr_count: 18\n .sgpr_spill_count: 0\n .symbol: _Z18BP_queens_root_dfsijiPK10queen_rootPyS2_.kd\n .uniform_work_group_size: 1\n .uses_dynamic_stack: false\n .vgpr_count: 16\n .vgpr_spill_count: 0\n .wavefront_size: 32\n .workgroup_processor_mode: 1\namdhsa.target: amdgcn-amd-amdhsa--gfx1100\namdhsa.version:\n - 1\n - 2\n...\n\n\t.end_amdgpu_metadata\n"}}}],"truncated":false,"partial":false},"paginationData":{"pageIndex":1625,"numItemsPerPage":100,"numTotalItems":162771,"offset":162500,"length":100}},"jwt":"eyJhbGciOiJFZERTQSIsImtpZCI6IjVHZDBvd0g5MTM2eDZjc1FvbE1zcktNWUZoRVFoUm5PVVVybEpjOUhaUEEifQ.eyJyZWFkIjp0cnVlLCJwZXJtaXNzaW9ucyI6eyJyZXBvLmNvbnRlbnQucmVhZCI6dHJ1ZX0sImlhdCI6MTc4ODMyNDgzMywianRpIjoiZmU4OGM0ZGUtMWE1OC00MjY4LThkNDUtZmJiNDA4OTk5MDg4Iiwic3ViIjoiL2RhdGFzZXRzL2FobWVkaGVha2wvZGFmdC1zbTg5LXJkbmEzIiwiZXhwIjoxNzg4MzI4NDMzLCJpc3MiOiJodHRwczovL2h1Z2dpbmdmYWNlLmNvIn0.AQa-BpYwr2mG9nz6_gCISRN0pzpKA722XdqzZw0Xjl1RiLXHgzT9ZM_18I6UtwRf5gHkfulriMzwBvHLoBeqCA","displayUrls":true,"splitSizeSummaries":[{"config":"default","split":"train","numRows":162771,"numBytesParquet":3925622696}]},"discussionsStats":{"closed":0,"open":1,"total":1},"fullWidth":true,"hasGatedAccess":true,"hasFullAccess":true,"isEmbedded":false,"savedQueries":{"community":[],"user":[]}}">
id stringlengths 43 43 | cuda stringlengths 1.25k 914k | hip stringlengths 0 916k |
|---|---|---|
43ffcdf66a7dbdbbb6206f1f3a9477c8151e8fbe_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z34forward_local_avgpool_layer_kerneliiiiiiiiPfS_ --------------------------
.section .text._Z34forward_local_avgpool_... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.weak __cxa_pure_virtual ; -- Begin function __cxa_pure_virtual
.p2align 2
.type __cxa_pure_virtual,@function
__cxa_pure_virtual: ; @__cxa_pure_virtual
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_trap 2
s_sendmsg_rtn_b32 s... |
a8af37fed6f7ff5219fa2a5e590b5a485a94668e_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv --------------------------
.section .text._ZN3cub17CUB_200700_890_NS11Emp... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.weak __cxa_pure_virtual ; -- Begin function __cxa_pure_virtual
.p2align 2
.type __cxa_pure_virtual,@function
__cxa_pure_virtual: ; @__cxa_pure_virtual
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_trap 2
s_sendmsg_rtn_b32 s... |
4bd25bf5204a952cebdbaeb51ddd35ca8882c404_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z13double_itselfPi --------------------------
.section .text._Z13double_itselfPi,"ax",@progbits
.sectioninfo ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13double_itselfPi ; -- Begin function _Z13double_itselfPi
.globl _Z13double_itselfPi
.p2align 8
.type _Z13double_itselfPi,@function
_Z13double_itselfPi: ; @_Z13double_itselfPi
; %bb.0:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_... |
9db12c2ff84a78c127a5f5d9e3b6ad285daf7659_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z16reduceDivergencePfS_i --------------------------
.section .text._Z16reduceDivergencePfS_i,"ax",@progbits
.s... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25fluidStructureInteractionPfS_S_ ; -- Begin function _Z25fluidStructureInteractionPfS_S_
.globl _Z25fluidStructureInteractionPfS_S_
.p2align 8
.type _Z25fluidStructureInteractionPfS_S_,@function
_Z25fluidStructureInteractionPfS_S_: ; @_Z25fluidStr... |
b11a0b944c6bb3e1b0d059a23fe5521b7b1bf643_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv --------------------------
.section .text._ZN3cub17CUB_200700_890_NS11Emp... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN7rocprim6detail19block_reduce_kernelILb0ENS0_21wrapped_reduce_configINS_14default_configEN6thrust5tupleIilNS4_9null_typeES6_S6_S6_S6_S6_S6_S6_EEEES7_PS7_S9_S7_NS4_11hip_rocprim9__extrema9arg_min_fIilNS4_4lessIiEEEEEEvT2_mT3_T4_T5_,"axG",@progbits,_Z... |
fdfc4af09865f9dec412bb5c51f07332941d1aba_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv --------------------------
.section .text._ZN3cub17CUB_200700_890_NS11Emp... | .text
.file "cuda_code_069951.hip"
.globl _Z30__device_stub__initializeSeedsPiiii # -- Begin function _Z30__device_stub__initializeSeedsPiiii
.p2align 4, 0x90
.type _Z30__device_stub__initializeSeedsPiiii,@function
_Z30__device_stub__initializeSeedsPiiii: # @_Z30__device_stub__initializeSeedsPiiii
.cfi_startproc
... |
229661b77d5f12717d8a26dcd9e738bc289440b2_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z17redBlackOperationP4Nodei --------------------------
.section .text._Z17redBlackOperationP4Nodei,"ax",@progbits
... | .text
.file "cuda_code_015716.hip"
.globl _Z30__device_stub__initializeNodesP4Nodei # -- Begin function _Z30__device_stub__initializeNodesP4Nodei
.p2align 4, 0x90
.type _Z30__device_stub__initializeNodesP4Nodei,@function
_Z30__device_stub__initializeNodesP4Nodei: # @_Z30__device_stub__initializeNodesP4Nodei
.cfi_... |
f9b9729cc078a0df2432f70e32ccee75fd513499_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv --------------------------
.section .text._ZN3cub17CUB_200700_890_NS11Emp... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10bfs_kernelPiS_S_PKiS1_iS_ ; -- Begin function _Z10bfs_kernelPiS_S_PKiS1_iS_
.globl _Z10bfs_kernelPiS_S_PKiS1_iS_
.p2align 8
.type _Z10bfs_kernelPiS_S_PKiS1_iS_,@function
_Z10bfs_kernelPiS_S_PKiS1_iS_: ; @_Z10bfs_kernelPiS_S_PKiS1_iS_
; %bb.... |
50038a6fc06b11ac77177ec397967238bfb3a3de_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z19passwordCrackKernelPcPiiS_iS_ --------------------------
.section .text._Z19passwordCrackKernelPcPiiS_iS_,"ax",@pro... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.weak __cxa_pure_virtual ; -- Begin function __cxa_pure_virtual
.p2align 2
.type __cxa_pure_virtual,@function
__cxa_pure_virtual: ; @__cxa_pure_virtual
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_trap 2
s_sendmsg_rtn_b32 s... |
41c8df8343ecf78992ec0405bd18ba37607deae5_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z11my_copysignPd --------------------------
.section .text._Z11my_copysignPd,"ax",@progbits
.sectioninfo ... | .text
.file "pow.hip"
.globl _Z26__device_stub__my_copysignPd # -- Begin function _Z26__device_stub__my_copysignPd
.p2align 4, 0x90
.type _Z26__device_stub__my_copysignPd,@function
_Z26__device_stub__my_copysignPd: # @_Z26__device_stub__my_copysignPd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_off... |
01e67fb7b8c5a379f1362b7433643c4b058051c3_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z15computeGradientPfS_f --------------------------
.section .text._Z15computeGradientPfS_f,"ax",@progbits
.sec... | .text
.file "cuda_code_060993.hip"
.globl _Z31__device_stub__initializeParamsPfP12hiprandStatei # -- Begin function _Z31__device_stub__initializeParamsPfP12hiprandStatei
.p2align 4, 0x90
.type _Z31__device_stub__initializeParamsPfP12hiprandStatei,@function
_Z31__device_stub__initializeParamsPfP12hiprandStatei: # @... |
bb5b76ea800ac9599606c45d5771db2e8886327a_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z3minPiS_S_S_mi --------------------------
.section .text._Z3minPiS_S_S_mi,"ax",@progbits
.sectioninfo @... | .text
.file "min.hip"
.globl _Z18__device_stub__minPiS_S_S_mi # -- Begin function _Z18__device_stub__minPiS_S_S_mi
.p2align 4, 0x90
.type _Z18__device_stub__minPiS_S_S_mi,@function
_Z18__device_stub__minPiS_S_S_mi: # @_Z18__device_stub__minPiS_S_S_mi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_of... |
acb8884a827755a9f492d111ef45cf55b8e1b59b_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z14raytraceKernelPK6SphereiP3RayP4Vec3ii --------------------------
.section .text._Z14raytraceKernelPK6SphereiP3RayP4... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14raytraceKernelPK6SphereiP3RayP4Vec3ii ; -- Begin function _Z14raytraceKernelPK6SphereiP3RayP4Vec3ii
.globl _Z14raytraceKernelPK6SphereiP3RayP4Vec3ii
.p2align 8
.type _Z14raytraceKernelPK6SphereiP3RayP4Vec3ii,@function
_Z14raytraceKernelPK6SphereiP3R... |
915e30917e9a7b629838be5099fa0b614da43602_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z23sparseConvolutionKernelPK13SparseElementiPKfPfii --------------------------
.section .text._Z23sparseConvolutionKer... | .text
.file "cuda_code_001677.hip"
.globl _Z38__device_stub__sparseConvolutionKernelPK13SparseElementiPKfPfii # -- Begin function _Z38__device_stub__sparseConvolutionKernelPK13SparseElementiPKfPfii
.p2align 4, 0x90
.type _Z38__device_stub__sparseConvolutionKernelPK13SparseElementiPKfPfii,@function
_Z38__device_stu... |
2d2cde6d01da7a7bb6d1b719107368cdf5990b81_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv --------------------------
.section .text._ZN3cub17CUB_200700_890_NS11Emp... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13cooSpMMKernelPKiS0_PKfiS0_S0_S2_iPiS3_PfS3_iiii ; -- Begin function _Z13cooSpMMKernelPKiS0_PKfiS0_S0_S2_iPiS3_PfS3_iiii
.globl _Z13cooSpMMKernelPKiS0_PKfiS0_S0_S2_iPiS3_PfS3_iiii
.p2align 8
.type _Z13cooSpMMKernelPKiS0_PKfiS0_S0_S2_iPiS3_PfS3_iiii,@... |
0ba83e0dfdc9d1e8891954c22db1ddea67a4b813_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_890_NS8cuda_cub6__... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15sparseMatMulCSCPKiS0_PKfS0_S0_S2_PiS3_Pfiii ; -- Begin function _Z15sparseMatMulCSCPKiS0_PKfS0_S0_S2_PiS3_Pfiii
.globl _Z15sparseMatMulCSCPKiS0_PKfS0_S0_S2_PiS3_Pfiii
.p2align 8
.type _Z15sparseMatMulCSCPKiS0_PKfS0_S0_S2_PiS3_Pfiii,@function
_Z15spa... |
416bb7744f246670a6a001727c10ea494056c259_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z15calculateCFD_V2PfS_jjf --------------------------
.section .text._Z15calculateCFD_V2PfS_jjf,"ax",@progbits
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15calculateCFD_V1PfS_jjf ; -- Begin function _Z15calculateCFD_V1PfS_jjf
.globl _Z15calculateCFD_V1PfS_jjf
.p2align 8
.type _Z15calculateCFD_V1PfS_jjf,@function
_Z15calculateCFD_V1PfS_jjf: ; @_Z15calculateCFD_V1PfS_jjf
; %bb.0:
s_clause 0x... |
d4ee4ee750ae033ad532e8cc3ec738993db6fbe2_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z15sparseMatVecMul12SparseTensorPKfPf --------------------------
.section .text._Z15sparseMatVecMul12SparseTensorPKfPf... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15sparseMatVecMul12SparseTensorPKfPf ; -- Begin function _Z15sparseMatVecMul12SparseTensorPKfPf
.globl _Z15sparseMatVecMul12SparseTensorPKfPf
.p2align 8
.type _Z15sparseMatVecMul12SparseTensorPKfPf,@function
_Z15sparseMatVecMul12SparseTensorPKfPf: ; @... |
698be3acb193398e0fa5dfe0832cc7d6ece869db_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z3mulPiS_S_ --------------------------
.section .text._Z3mulPiS_S_,"ax",@progbits
.sectioninfo @"SHI... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3mulPiS_S_ ; -- Begin function _Z3mulPiS_S_
.globl _Z3mulPiS_S_
.p2align 8
.type _Z3mulPiS_S_,@function
_Z3mulPiS_S_: ; @_Z3mulPiS_S_
; %bb.0:
s_load_b64 s[4:5], s[0:1], 0x10
s_lshl_b32 s6, s15, 10
s_load_b128 s... |
a58de2a8a41b759453ecaba89459c531127b8928_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z13stencilKernelPfS_ii --------------------------
.section .text._Z13stencilKernelPfS_ii,"ax",@progbits
.secti... | .text
.file "cuda_code_010625.hip"
.globl _Z28__device_stub__stencilKernelPfS_ii # -- Begin function _Z28__device_stub__stencilKernelPfS_ii
.p2align 4, 0x90
.type _Z28__device_stub__stencilKernelPfS_ii,@function
_Z28__device_stub__stencilKernelPfS_ii: # @_Z28__device_stub__stencilKernelPfS_ii
.cfi_startproc
# %bb... |
014db0d015bdfa3689ab0743dbcea821082d0b61_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z10insertKeysP9BTreeNodePii --------------------------
.section .text._Z10insertKeysP9BTreeNodePii,"ax",@progbits
... | .text
.file "cuda_code_015530.hip"
.globl _Z30__device_stub__initializeNodesP9BTreeNodei # -- Begin function _Z30__device_stub__initializeNodesP9BTreeNodei
.p2align 4, 0x90
.type _Z30__device_stub__initializeNodesP9BTreeNodei,@function
_Z30__device_stub__initializeNodesP9BTreeNodei: # @_Z30__device_stub__initializ... |
588f5bc309402c97548fe8e4192d10fbcbcf9803_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z10mineBlocksPyS_Pi --------------------------
.section .text._Z10mineBlocksPyS_Pi,"ax",@progbits
.sectioninfo... | .text
.file "cuda_code_053607.hip"
.globl _Z25__device_stub__mineBlocksPyS_Pi # -- Begin function _Z25__device_stub__mineBlocksPyS_Pi
.p2align 4, 0x90
.type _Z25__device_stub__mineBlocksPyS_Pi,@function
_Z25__device_stub__mineBlocksPyS_Pi: # @_Z25__device_stub__mineBlocksPyS_Pi
.cfi_startproc
# %bb.0:
subq $1... |
020a46b78a172293624075d812f9fa2f57f8f271_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv --------------------------
.section .text._ZN3cub17CUB_200700_890_NS11Emp... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22labelPropagationKernelPiPKiS1_S_ ; -- Begin function _Z22labelPropagationKernelPiPKiS1_S_
.globl _Z22labelPropagationKernelPiPKiS1_S_
.p2align 8
.type _Z22labelPropagationKernelPiPKiS1_S_,@function
_Z22labelPropagationKernelPiPKiS1_S_: ; @_Z22labe... |
28e125c15a89c20827ea2f2b04f239ef000561f2_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z15minReduceKernelPfS_i --------------------------
.section .text._Z15minReduceKernelPfS_i,"ax",@progbits
.sec... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15minReduceKernelPfS_i ; -- Begin function _Z15minReduceKernelPfS_i
.globl _Z15minReduceKernelPfS_i
.p2align 8
.type _Z15minReduceKernelPfS_i,@function
_Z15minReduceKernelPfS_i: ; @_Z15minReduceKernelPfS_i
; %bb.0:
s_clause 0x2
s_load_... |
29c25e5f27492f82fc594fcb31f9d9bd4db1abf6_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z24simulatedAnnealingKernelPfS_S_S_ffi --------------------------
.section .text._Z24simulatedAnnealingKernelPfS_S_S_f... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24simulatedAnnealingKernelPfS_S_S_ffi ; -- Begin function _Z24simulatedAnnealingKernelPfS_S_S_ffi
.globl _Z24simulatedAnnealingKernelPfS_S_S_ffi
.p2align 8
.type _Z24simulatedAnnealingKernelPfS_S_S_ffi,@function
_Z24simulatedAnnealingKernelPfS_S_S_ffi... |
8a9ab54da91a9b47a39b0b1a7773dd766bb06254_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z10print_listP4Node --------------------------
.section .text._Z10print_listP4Node,"ax",@progbits
.sectioninfo... | .text
.file "cuda_code_083820.hip"
.globl _Z33__device_stub__init_random_statesP12hiprandStatem # -- Begin function _Z33__device_stub__init_random_statesP12hiprandStatem
.p2align 4, 0x90
.type _Z33__device_stub__init_random_statesP12hiprandStatem,@function
_Z33__device_stub__init_random_statesP12hiprandStatem: # @... |
7a3797e8c7e9f414f31da4f981efc03bce3c9c94_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z14sobelFilter7x7PKfPfii --------------------------
.section .text._Z14sobelFilter7x7PKfPfii,"ax",@progbits
.s... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14sobelFilter7x7PKfPfii ; -- Begin function _Z14sobelFilter7x7PKfPfii
.globl _Z14sobelFilter7x7PKfPfii
.p2align 8
.type _Z14sobelFilter7x7PKfPfii,@function
_Z14sobelFilter7x7PKfPfii: ; @_Z14sobelFilter7x7PKfPfii
; %bb.0:
s_clause 0x1
s_... |
debc95a395c27c4e1aa1683e2b93b257e65861c2_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv --------------------------
.section .text._ZN3cub17CUB_200700_890_NS11Emp... | .text
.file "cuda_code_077712.hip"
.globl _Z32__device_stub__init_edges_kernelPiij # -- Begin function _Z32__device_stub__init_edges_kernelPiij
.p2align 4, 0x90
.type _Z32__device_stub__init_edges_kernelPiij,@function
_Z32__device_stub__init_edges_kernelPiij: # @_Z32__device_stub__init_edges_kernelPiij
.cfi_start... |
cbbd289654180b771d8a00d88b2c7785932e8462_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z36convertKinectDisparityInPlace_kernelPfiiif --------------------------
.section .text._Z36convertKinectDisparityInPl... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z36convertKinectDisparityInPlace_kernelPfiiif ; -- Begin function _Z36convertKinectDisparityInPlace_kernelPfiiif
.globl _Z36convertKinectDisparityInPlace_kernelPfiiif
.p2align 8
.type _Z36convertKinectDisparityInPlace_kernelPfiiif,@function
_Z36convert... |
c70a6036c5f8dcdd043780a7bdaa2497ec6b4438_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z14crackPasswordsPjS_S_j --------------------------
.section .text._Z14crackPasswordsPjS_S_j,"ax",@progbits
.s... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20generateRainbowTablePjjj ; -- Begin function _Z20generateRainbowTablePjjj
.globl _Z20generateRainbowTablePjjj
.p2align 8
.type _Z20generateRainbowTablePjjj,@function
_Z20generateRainbowTablePjjj: ; @_Z20generateRainbowTablePjjj
; %bb.0:
s... |
03a4c9b50604eaae12b66200e3aa8add865772cf_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20_... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEi... |
197904366b6fe394e2354a2afe5c5c2f367021f3_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z5conv2PdS_jjS_jj --------------------------
.section .text._Z5conv2PdS_jjS_jj,"ax",@progbits
.sectioninfo ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.weak __cxa_pure_virtual ; -- Begin function __cxa_pure_virtual
.p2align 2
.type __cxa_pure_virtual,@function
__cxa_pure_virtual: ; @__cxa_pure_virtual
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_trap 2
s_sendmsg_rtn_b32 s... |
1221046ad8dcf1f1586959f75c51e80b8dc577f5_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z9bfsKernelPiS_S_S_S_ --------------------------
.section .text._Z9bfsKernelPiS_S_S_S_,"ax",@progbits
.section... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9bfsKernelPiS_S_S_S_ ; -- Begin function _Z9bfsKernelPiS_S_S_S_
.globl _Z9bfsKernelPiS_S_S_S_
.p2align 8
.type _Z9bfsKernelPiS_S_S_S_,@function
_Z9bfsKernelPiS_S_S_S_: ; @_Z9bfsKernelPiS_S_S_S_
; %bb.0:
s_clause 0x1
s_load_b64 s[2:3... |
60bd7816430ecf11a3078fff6289a18f04a6aa21_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv --------------------------
.section .text._ZN3cub17CUB_200700_890_NS11Emp... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.weak __cxa_pure_virtual ; -- Begin function __cxa_pure_virtual
.p2align 2
.type __cxa_pure_virtual,@function
__cxa_pure_virtual: ; @__cxa_pure_virtual
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_trap 2
s_sendmsg_rtn_b32 s... |
c3b6df04338ae4a7c25ae5da3e3f4fa1c05c7943_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z18processFrameKernelPfS_ --------------------------
.section .text._Z18processFrameKernelPfS_,"ax",@progbits
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.weak __cxa_pure_virtual ; -- Begin function __cxa_pure_virtual
.p2align 2
.type __cxa_pure_virtual,@function
__cxa_pure_virtual: ; @__cxa_pure_virtual
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_trap 2
s_sendmsg_rtn_b32 s... |
0337a583cdae77438349f8823fc7cebd1ac64682_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z20monteCarloSimulationP17curandStateXORWOWPfffff --------------------------
.section .text._Z20monteCarloSimulationP1... | .text
.file "cuda_code_022369.hip"
.globl _Z31__device_stub__initCurandStatesP12hiprandStatem # -- Begin function _Z31__device_stub__initCurandStatesP12hiprandStatem
.p2align 4, 0x90
.type _Z31__device_stub__initCurandStatesP12hiprandStatem,@function
_Z31__device_stub__initCurandStatesP12hiprandStatem: # @_Z31__de... |
a4a92d2694a69403dd0008bd2b05dd5380eefbf4_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z14rmsprop_updatePfS_S_i --------------------------
.section .text._Z14rmsprop_updatePfS_S_i,"ax",@progbits
.s... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.weak __cxa_pure_virtual ; -- Begin function __cxa_pure_virtual
.p2align 2
.type __cxa_pure_virtual,@function
__cxa_pure_virtual: ; @__cxa_pure_virtual
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_trap 2
s_sendmsg_rtn_b32 s... |
cb9b70adc0789ba2763fbc39c27fddd5324cb74e_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z18processFrameKernelP6float4S0_ii --------------------------
.section .text._Z18processFrameKernelP6float4S0_ii,"ax",... | .text
.file "cuda_code_052896.hip"
.globl _Z33__device_stub__processFrameKernelP15HIP_vector_typeIfLj4EES1_ii # -- Begin function _Z33__device_stub__processFrameKernelP15HIP_vector_typeIfLj4EES1_ii
.p2align 4, 0x90
.type _Z33__device_stub__processFrameKernelP15HIP_vector_typeIfLj4EES1_ii,@function
_Z33__device_stu... |
c08da643382926ebe29138c33d6b83ab149e1398_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z18sparseTensorKernelPK13SparseElementPfi --------------------------
.section .text._Z18sparseTensorKernelPK13SparseEl... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18sparseTensorKernelPK13SparseElementPfi ; -- Begin function _Z18sparseTensorKernelPK13SparseElementPfi
.globl _Z18sparseTensorKernelPK13SparseElementPfi
.p2align 8
.type _Z18sparseTensorKernelPK13SparseElementPfi,@function
_Z18sparseTensorKernelPK13S... |
816e37a34f44b7a15e390d602db5021dd7dc1e79_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z29homomorphic_encryption_kernelP6__halfS0_S0_i --------------------------
.section .text._Z29homomorphic_encryption_k... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29homomorphic_encryption_kernelP6__halfS0_S0_i ; -- Begin function _Z29homomorphic_encryption_kernelP6__halfS0_S0_i
.globl _Z29homomorphic_encryption_kernelP6__halfS0_S0_i
.p2align 8
.type _Z29homomorphic_encryption_kernelP6__halfS0_S0_i,@function
_Z2... |
0b08512a828802a13423294ef3715f3072df490d_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z21gradientDescentKernelPfS_fi --------------------------
.section .text._Z21gradientDescentKernelPfS_fi,"ax",@progbit... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21gradientDescentKernelPfS_fi ; -- Begin function _Z21gradientDescentKernelPfS_fi
.globl _Z21gradientDescentKernelPfS_fi
.p2align 8
.type _Z21gradientDescentKernelPfS_fi,@function
_Z21gradientDescentKernelPfS_fi: ; @_Z21gradientDescentKernelPfS... |
449f5a5908732f4a733f14ad19ee56a4dcb758f3_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z18heatEquationKernelPfS_fff --------------------------
.section .text._Z18heatEquationKernelPfS_fff,"ax",@progbits
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18heatEquationKernelPfS_fff ; -- Begin function _Z18heatEquationKernelPfS_fff
.globl _Z18heatEquationKernelPfS_fff
.p2align 8
.type _Z18heatEquationKernelPfS_fff,@function
_Z18heatEquationKernelPfS_fff: ; @_Z18heatEquationKernelPfS_fff
; %bb.... |
9fe076077fd1d65ff400541eda0e8127fbdf1881_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._ZN3cub17CUB_200700_890_NS28DeviceReduceSingleTileKernelINS0_18DeviceReducePolicyIfyN6thrust20THRUST_200700_890_NS4plusIfEEE9Policy600... | .text
.file "thrust.hip"
.globl _Z10sum_thrustPfj # -- Begin function _Z10sum_thrustPfj
.p2align 4, 0x90
.type _Z10sum_thrustPfj,@function
_Z10sum_thrustPfj: # @_Z10sum_thrustPfj
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rdi, %rax
movl %esi, %edx
shlq ... |
c37f7d7468f411bbb4eafd0e4c655d9d1747f327_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z19mergeSortTreeKernelPiS_i --------------------------
.section .text._Z19mergeSortTreeKernelPiS_i,"ax",@progbits
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.weak __cxa_pure_virtual ; -- Begin function __cxa_pure_virtual
.p2align 2
.type __cxa_pure_virtual,@function
__cxa_pure_virtual: ; @__cxa_pure_virtual
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_trap 2
s_sendmsg_rtn_b32 s... |
21068b2a58d8bf97f79d47ce0010d0cc4547b6a4_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z18convBackpropKernelPfS_S_S_S_ii --------------------------
.section .text._Z18convBackpropKernelPfS_S_S_S_ii,"ax",@p... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18convBackpropKernelPfS_S_S_S_ii ; -- Begin function _Z18convBackpropKernelPfS_S_S_S_ii
.globl _Z18convBackpropKernelPfS_S_S_S_ii
.p2align 8
.type _Z18convBackpropKernelPfS_S_S_S_ii,@function
_Z18convBackpropKernelPfS_S_S_S_ii: ; @_Z18convBackprop... |
2ad85c3dcb5d229688ec529a8af09a0a330a893d_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z4gemviPdS_S_ --------------------------
.section .text._Z4gemviPdS_S_,"ax",@progbits
.sectionflags @"S... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.weak __cxa_pure_virtual ; -- Begin function __cxa_pure_virtual
.p2align 2
.type __cxa_pure_virtual,@function
__cxa_pure_virtual: ; @__cxa_pure_virtual
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_trap 2
s_sendmsg_rtn_b32 s... |
e6ee8fa1cbd4770215218d238521e5324aaf8acb_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z16initCurandStatesP17curandStateXORWOWm --------------------------
.section .text._Z16initCurandStatesP17curandStateX... | .text
.file "cuda_code_042017.hip"
.globl _Z35__device_stub__monteCarloSimulationP12hiprandStatePffffffS1_ # -- Begin function _Z35__device_stub__monteCarloSimulationP12hiprandStatePffffffS1_
.p2align 4, 0x90
.type _Z35__device_stub__monteCarloSimulationP12hiprandStatePffffffS1_,@function
_Z35__device_stub__monteC... |
af93c1dae7d14d803bab6e2a886b632141b6553b_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z14searchElementsP4NodePiPbi --------------------------
.section .text._Z14searchElementsP4NodePiPbi,"ax",@progbits
... | .text
.file "cuda_code_035341.hip"
.globl _Z31__device_stub__initRandomStatesP12hiprandStatem # -- Begin function _Z31__device_stub__initRandomStatesP12hiprandStatem
.p2align 4, 0x90
.type _Z31__device_stub__initRandomStatesP12hiprandStatem,@function
_Z31__device_stub__initRandomStatesP12hiprandStatem: # @_Z31__de... |
536a22097fb72030a99853dbcd6672ad47b20a46_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z9pq_kernelPi --------------------------
.section .text._Z9pq_kernelPi,"ax",@progbits
.sectionflags @"S... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9pq_kernelPi ; -- Begin function _Z9pq_kernelPi
.globl _Z9pq_kernelPi
.p2align 8
.type _Z9pq_kernelPi,@function
_Z9pq_kernelPi: ; @_Z9pq_kernelPi
; %bb.0:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s... |
a1f6a17f80b30458fcccdfe85b3986c45e3e8a4f_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z14skipListKernelPi --------------------------
.section .text._Z14skipListKernelPi,"ax",@progbits
.sectionflag... | .text
.file "cuda_code_032071.hip"
.globl _Z29__device_stub__skipListKernelPi # -- Begin function _Z29__device_stub__skipListKernelPi
.p2align 4, 0x90
.type _Z29__device_stub__skipListKernelPi,@function
_Z29__device_stub__skipListKernelPi: # @_Z29__device_stub__skipListKernelPi
.cfi_startproc
# %bb.0:
subq $7... |
1723d81067513b7473c9019fbbd02c433ab537b6_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z16set_new_positionPjS_PiS0_i --------------------------
.section .text._Z16set_new_positionPjS_PiS0_i,"ax",@progbits
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4scanPiS_ii ; -- Begin function _Z4scanPiS_ii
.globl _Z4scanPiS_ii
.p2align 8
.type _Z4scanPiS_ii,@function
_Z4scanPiS_ii: ; @_Z4scanPiS_ii
; %bb.0:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], ... |
7f648a8075a727688105ff397deedde9ebe4f47b_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z15matrixMulKernelPfS_S_ --------------------------
.section .text._Z15matrixMulKernelPfS_S_,"ax",@progbits
.s... | .text
.file "cuda_code_080688.hip"
.globl _Z30__device_stub__matrixMulKernelPfS_S_ # -- Begin function _Z30__device_stub__matrixMulKernelPfS_S_
.p2align 4, 0x90
.type _Z30__device_stub__matrixMulKernelPfS_S_,@function
_Z30__device_stub__matrixMulKernelPfS_S_: # @_Z30__device_stub__matrixMulKernelPfS_S_
.cfi_start... |
3d7ff3b311f8fc93600a4a4e6d3aa98093e5e444_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv --------------------------
.section .text._ZN3cub17CUB_200700_890_NS11Emp... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9swap_rowsPdiiii ; -- Begin function _Z9swap_rowsPdiiii
.globl _Z9swap_rowsPdiiii
.p2align 8
.type _Z9swap_rowsPdiiii,@function
_Z9swap_rowsPdiiii: ; @_Z9swap_rowsPdiiii
; %bb.0:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x24
s_l... |
3da4056d6328e5dc507480d0670d5703a8c141e7_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z20is_nan_or_inf_kernelPfmPi --------------------------
.section .text._Z20is_nan_or_inf_kernelPfmPi,"ax",@progbits
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20is_nan_or_inf_kernelPfmPi ; -- Begin function _Z20is_nan_or_inf_kernelPfmPi
.globl _Z20is_nan_or_inf_kernelPfmPi
.p2align 8
.type _Z20is_nan_or_inf_kernelPfmPi,@function
_Z20is_nan_or_inf_kernelPfmPi: ; @_Z20is_nan_or_inf_kernelPfmPi
; %bb.... |
48411d5d29395e3e029d5f496e9589601d0324f1_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z3setPii --------------------------
.section .text._Z3setPii,"ax",@progbits
.sectioninfo @"SHI_RE... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3setPii ; -- Begin function _Z3setPii
.globl _Z3setPii
.p2align 8
.type _Z3setPii,@function
_Z3setPii: ; @_Z3setPii
; %bb.0:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3setPi... |
fd479730cda200be671e1f44a857ebe58813830d_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z9kernelAddPfiii --------------------------
.section .text._Z9kernelAddPfiii,"ax",@progbits
.sectioninfo ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.weak __cxa_pure_virtual ; -- Begin function __cxa_pure_virtual
.p2align 2
.type __cxa_pure_virtual,@function
__cxa_pure_virtual: ; @__cxa_pure_virtual
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_trap 2
s_sendmsg_rtn_b32 s... |
30c5822aa655d29f76ba4dbf37f79dd0658a1d5b_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z22geneticAlgorithmKernelPjS_P17curandStateXORWOW --------------------------
.section .text._Z22geneticAlgorithmKernel... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22geneticAlgorithmKernelPjS_P12hiprandState ; -- Begin function _Z22geneticAlgorithmKernelPjS_P12hiprandState
.globl _Z22geneticAlgorithmKernelPjS_P12hiprandState
.p2align 8
.type _Z22geneticAlgorithmKernelPjS_P12hiprandState,@function
_Z22geneticAlgo... |
440c4d186952d84cbbadd05b803d0ed81ae966f8_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z11calc_answerPKiS0_Pil --------------------------
.section .text._Z11calc_answerPKiS0_Pil,"ax",@progbits
.sec... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11calc_answerPKiS0_Pil ; -- Begin function _Z11calc_answerPKiS0_Pil
.globl _Z11calc_answerPKiS0_Pil
.p2align 8
.type _Z11calc_answerPKiS0_Pil,@function
_Z11calc_answerPKiS0_Pil: ; @_Z11calc_answerPKiS0_Pil
; %bb.0:
s_clause 0x1
s_load_... |
f42413bc53b46fad8979f6a6c398d376ab643f06_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z10comparatorIdfEvPT_PT0_ --------------------------
.section .text._Z10comparatorIdfEvPT_PT0_,"ax",@progbits
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z10vector_sumIdEvPT_S1_S1_,"axG",@progbits,_Z10vector_sumIdEvPT_S1_S1_,comdat
.protected _Z10vector_sumIdEvPT_S1_S1_ ; -- Begin function _Z10vector_sumIdEvPT_S1_S1_
.globl _Z10vector_sumIdEvPT_S1_S1_
.p2align 8
.type _Z10vector_sumIdEvPT_S1_S1_,@f... |
aa374d320779f5df64734d109ec241748a18c0ce_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z23featureExtractionKernelPKfPfii --------------------------
.section .text._Z23featureExtractionKernelPKfPfii,"ax",@p... | .text
.file "cuda_code_048101.hip"
.globl _Z38__device_stub__featureExtractionKernelPKfPfii # -- Begin function _Z38__device_stub__featureExtractionKernelPKfPfii
.p2align 4, 0x90
.type _Z38__device_stub__featureExtractionKernelPKfPfii,@function
_Z38__device_stub__featureExtractionKernelPKfPfii: # @_Z38__device_stu... |
4a80f9eccae8a85255c66251b603326266c61455_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z10first_gridIfEvPi --------------------------
.section .text._Z10first_gridIfEvPi,"ax",@progbits
.sectioninfo... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.p2align 2 ; -- Begin function _Z2g1P12interval_gpuIfE
.type _Z2g1P12interval_gpuIfE,@function
_Z2g1P12interval_gpuIfE: ; @_Z2g1P12interval_gpuIfE
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
flat_load_b128 v[0:3], ... |
1c3ad00582b34c6d0c3428dbcec6b8dedbbadce6_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z14return_double_iPdPKd --------------------------
.section .text._Z14return_double_iPdPKd,"ax",@progbits
.sec... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14return_double_iPdPKd ; -- Begin function _Z14return_double_iPdPKd
.globl _Z14return_double_iPdPKd
.p2align 8
.type _Z14return_double_iPdPKd,@function
_Z14return_double_iPdPKd: ; @_Z14return_double_iPdPKd
; %bb.0:
s_clause 0x1
s_load_... |
e72059d25e33fdb3c903690987d7d0b74c226991_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z23featureExtractionKernelPKfPf --------------------------
.section .text._Z23featureExtractionKernelPKfPf,"ax",@progb... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23featureExtractionKernelPKfPf ; -- Begin function _Z23featureExtractionKernelPKfPf
.globl _Z23featureExtractionKernelPKfPf
.p2align 8
.type _Z23featureExtractionKernelPKfPf,@function
_Z23featureExtractionKernelPKfPf: ; @_Z23featureExtractionKer... |
378d9826c7ba0d18dd71d27f4f16a737645ce0ca_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z19regionGrowingKernelPiS_iiiii --------------------------
.section .text._Z19regionGrowingKernelPiS_iiiii,"ax",@progb... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.weak __cxa_pure_virtual ; -- Begin function __cxa_pure_virtual
.p2align 2
.type __cxa_pure_virtual,@function
__cxa_pure_virtual: ; @__cxa_pure_virtual
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_trap 2
s_sendmsg_rtn_b32 s... |
8ddba669a56d6f5e200e4d2747dfc3bfff4b1b9e_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z16dotProductKernelPKfS0_Pfi --------------------------
.section .text._Z16dotProductKernelPKfS0_Pfi,"ax",@progbits
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16dotProductKernelPKfS0_Pfi ; -- Begin function _Z16dotProductKernelPKfS0_Pfi
.globl _Z16dotProductKernelPKfS0_Pfi
.p2align 8
.type _Z16dotProductKernelPKfS0_Pfi,@function
_Z16dotProductKernelPKfS0_Pfi: ; @_Z16dotProductKernelPKfS0_Pfi
; %bb.... |
9eab806aec54274bfaa19caa84c2d9dee47ed8f1_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z10stencil64DPfS_ --------------------------
.section .text._Z10stencil64DPfS_,"ax",@progbits
.sectionflags ... | .text
.file "cuda_code_027344.hip"
.globl _Z25__device_stub__stencil64DPfS_ # -- Begin function _Z25__device_stub__stencil64DPfS_
.p2align 4, 0x90
.type _Z25__device_stub__stencil64DPfS_,@function
_Z25__device_stub__stencil64DPfS_: # @_Z25__device_stub__stencil64DPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
... |
84c4ff3e59755b086cb667ce139d6a76f4cf8232_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z16bubbleSortKernelPii --------------------------
.section .text._Z16bubbleSortKernelPii,"ax",@progbits
.secti... | .text
.file "cuda_code_052747.hip"
.globl _Z31__device_stub__bubbleSortKernelPii # -- Begin function _Z31__device_stub__bubbleSortKernelPii
.p2align 4, 0x90
.type _Z31__device_stub__bubbleSortKernelPii,@function
_Z31__device_stub__bubbleSortKernelPii: # @_Z31__device_stub__bubbleSortKernelPii
.cfi_startproc
# %bb... |
91e30a83b97b262960b30b31c4968544f0e48a6c_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z13initializePhiPfiiiii --------------------------
.section .text._Z13initializePhiPfiiiii,"ax",@progbits
.sec... | .text
.file "cuda_code_011992.hip"
.globl _Z34__device_stub__activeContourKernelPfPKffffii # -- Begin function _Z34__device_stub__activeContourKernelPfPKffffii
.p2align 4, 0x90
.type _Z34__device_stub__activeContourKernelPfPKffffii,@function
_Z34__device_stub__activeContourKernelPfPKffffii: # @_Z34__device_stub__a... |
401b56c3867c0e6a07fdd94936fb000cf25d1f91_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z15bsrMatMulKernelPKfS0_Pfii --------------------------
.section .text._Z15bsrMatMulKernelPKfS0_Pfii,"ax",@progbits
... | .text
.file "cuda_code_064065.hip"
.globl _Z30__device_stub__bsrMatMulKernelPKfS0_Pfii # -- Begin function _Z30__device_stub__bsrMatMulKernelPKfS0_Pfii
.p2align 4, 0x90
.type _Z30__device_stub__bsrMatMulKernelPKfS0_Pfii,@function
_Z30__device_stub__bsrMatMulKernelPKfS0_Pfii: # @_Z30__device_stub__bsrMatMulKernelPK... |
11b48c6eea1250d0e06094cf892f121fa7df5cb5_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20_... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.p2align 2 ; -- Begin function _Z9printListRN18gpu_linearized_stl4listIfLi170EEE
.type _Z9printListRN18gpu_linearized_stl4listIfLi170EEE,@function
_Z9printListRN18gpu_linearized_stl4listIfLi170EEE: ; @_Z9printListRN18gpu_linearized_stl4... |
07db6120ec3250010d986d7202c0f5adf1cdc470_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z9dctKernelPfS_ --------------------------
.section .text._Z9dctKernelPfS_,"ax",@progbits
.sectionflags @... | .text
.file "cuda_code_028189.hip"
.globl _Z24__device_stub__dctKernelPfS_ # -- Begin function _Z24__device_stub__dctKernelPfS_
.p2align 4, 0x90
.type _Z24__device_stub__dctKernelPfS_,@function
_Z24__device_stub__dctKernelPfS_: # @_Z24__device_stub__dctKernelPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cf... |
fd9b245afe7de6d03f859452bb8c93d4bf35a1f2_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z13sigmoidKernelIdEvPT_S1_i --------------------------
.section .text._Z13sigmoidKernelIdEvPT_S1_i,"ax",@progbits
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.weak __cxa_pure_virtual ; -- Begin function __cxa_pure_virtual
.p2align 2
.type __cxa_pure_virtual,@function
__cxa_pure_virtual: ; @__cxa_pure_virtual
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_trap 2
s_sendmsg_rtn_b32 s... |
b7dfd71e41a9af786312078168759f2258d87a2f_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z22redBlackTreeOperationsP4Node --------------------------
.section .text._Z22redBlackTreeOperationsP4Node,"ax",@progb... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15initializeNodesP4Node ; -- Begin function _Z15initializeNodesP4Node
.globl _Z15initializeNodesP4Node
.p2align 8
.type _Z15initializeNodesP4Node,@function
_Z15initializeNodesP4Node: ; @_Z15initializeNodesP4Node
; %bb.0:
s_load_b32 s2, s... |
1837d1242fe55e3df3a94c35ece42e25d5a2400e_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z3muliPfS_ --------------------------
.section .text._Z3muliPfS_,"ax",@progbits
.sectioninfo @"SHI_... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPfS_ ; -- Begin function _Z3addiPfS_
.globl _Z3addiPfS_
.p2align 8
.type _Z3addiPfS_,@function
_Z3addiPfS_: ; @_Z3addiPfS_
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x0
s_... |
4469afdad3ac6207bf347134ba64a496d6099f67_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z7computefiffPfS_fffffffffffffffffff --------------------------
.section .text._Z7computefiffPfS_fffffffffffffffffff,"... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7computefiffPfS_fffffffffffffffffff ; -- Begin function _Z7computefiffPfS_fffffffffffffffffff
.globl _Z7computefiffPfS_fffffffffffffffffff
.p2align 8
.type _Z7computefiffPfS_fffffffffffffffffff,@function
_Z7computefiffPfS_fffffffffffffffffff: ; @_Z7c... |
88ce57f0c8b1396007b3ae5a18d42bdb4b509218_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z18heatEquationKernelPfS_if --------------------------
.section .text._Z18heatEquationKernelPfS_if,"ax",@progbits
... | .text
.file "cuda_code_078126.hip"
.globl _Z33__device_stub__heatEquationKernelPfS_if # -- Begin function _Z33__device_stub__heatEquationKernelPfS_if
.p2align 4, 0x90
.type _Z33__device_stub__heatEquationKernelPfS_if,@function
_Z33__device_stub__heatEquationKernelPfS_if: # @_Z33__device_stub__heatEquationKernelPfS... |
3fd068f20ed5a7708016b7e4c7c204c315b59a20_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text.lessthanorequal_scalar_float --------------------------
.section .text.lessthanorequal_scalar_float,"ax",@progbits
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected lessthanorequal_scalar_float ; -- Begin function lessthanorequal_scalar_float
.globl lessthanorequal_scalar_float
.p2align 8
.type lessthanorequal_scalar_float,@function
lessthanorequal_scalar_float: ; @lessthanorequal_scalar_float
; %bb.0:
s... |
c631448dff8c851f685cebbeb34db3e0dffe6787_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z21clothSimulationKernelPfS_fii --------------------------
.section .text._Z21clothSimulationKernelPfS_fii,"ax",@progb... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21clothSimulationKernelPfS_fii ; -- Begin function _Z21clothSimulationKernelPfS_fii
.globl _Z21clothSimulationKernelPfS_fii
.p2align 8
.type _Z21clothSimulationKernelPfS_fii,@function
_Z21clothSimulationKernelPfS_fii: ; @_Z21clothSimulationKerne... |
675f2df748f1cccf84a2ac77563f2494c94a7ee5_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z17convolutionRowGPUPfS_S_iii --------------------------
.section .text._Z17convolutionRowGPUPfS_S_iii,"ax",@progbits
... | .text
.file "convolutionRowGPU.hip"
.globl _Z32__device_stub__convolutionRowGPUPfS_S_iii # -- Begin function _Z32__device_stub__convolutionRowGPUPfS_S_iii
.p2align 4, 0x90
.type _Z32__device_stub__convolutionRowGPUPfS_S_iii,@function
_Z32__device_stub__convolutionRowGPUPfS_S_iii: # @_Z32__device_stub__convolutionR... |
e06f8d2a35fdcef7a315b3eb9396f5845cfe0c47_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._ZN3cub17CUB_200700_890_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_890_NS8cuda_cub20_... | .text
.file "cuda_code_004697.hip"
.globl _Z32__device_stub__initialize_randomP12hiprandStatem # -- Begin function _Z32__device_stub__initialize_randomP12hiprandStatem
.p2align 4, 0x90
.type _Z32__device_stub__initialize_randomP12hiprandStatem,@function
_Z32__device_stub__initialize_randomP12hiprandStatem: # @_Z32... |
e035bddad58a987c9319f68003a2f1ce5e62f9f8_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z14rmsprop_kernelPfS_S_fff --------------------------
.section .text._Z14rmsprop_kernelPfS_S_fff,"ax",@progbits
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14rmsprop_kernelPfS_S_fff ; -- Begin function _Z14rmsprop_kernelPfS_S_fff
.globl _Z14rmsprop_kernelPfS_S_fff
.p2align 8
.type _Z14rmsprop_kernelPfS_S_fff,@function
_Z14rmsprop_kernelPfS_S_fff: ; @_Z14rmsprop_kernelPfS_S_fff
; %bb.0:
s_load... |
a3704e34a38394d5fc7cfe72e08a6f69c746da04_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z6squarePiS_ --------------------------
.section .text._Z6squarePiS_,"ax",@progbits
.sectioninfo @"SH... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePiS_ ; -- Begin function _Z6squarePiS_
.globl _Z6squarePiS_
.p2align 8
.type _Z6squarePiS_,@function
_Z6squarePiS_: ; @_Z6squarePiS_
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:... |
13c07395dba1865ae280a4f20b0a0232457782db_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z27gpu_stencil37_hack1_cp_colsPdS_S_S_mmmiii --------------------------
.section .text._Z27gpu_stencil37_hack1_cp_cols... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.weak __cxa_pure_virtual ; -- Begin function __cxa_pure_virtual
.p2align 2
.type __cxa_pure_virtual,@function
__cxa_pure_virtual: ; @__cxa_pure_virtual
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_trap 2
s_sendmsg_rtn_b32 s... |
82a2aab1107aa5357c543759d50bc39a7697cc42_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z8sumOnGpuPiS_S_i --------------------------
.section .text._Z8sumOnGpuPiS_S_i,"ax",@progbits
.sectioninfo ... | .text
.file "VectSumClassExample.hip"
.globl _Z23__device_stub__sumOnGpuPiS_S_i # -- Begin function _Z23__device_stub__sumOnGpuPiS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__sumOnGpuPiS_S_i,@function
_Z23__device_stub__sumOnGpuPiS_S_i: # @_Z23__device_stub__sumOnGpuPiS_S_i
.cfi_startproc
# %bb.0:
subq $12... |
521ce922ea6ff1060451708dd55f62b582430a27_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z25fluidStructureInteractionP15BoundaryElementi --------------------------
.section .text._Z25fluidStructureInteractio... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25fluidStructureInteractionP15BoundaryElementi ; -- Begin function _Z25fluidStructureInteractionP15BoundaryElementi
.globl _Z25fluidStructureInteractionP15BoundaryElementi
.p2align 8
.type _Z25fluidStructureInteractionP15BoundaryElementi,@function
_Z2... |
6606fa6029ba083d280bbdc3f1753b3b7b64018d_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z11gradientGPUPdS_S_iidd --------------------------
.section .text._Z11gradientGPUPdS_S_iidd,"ax",@progbits
.s... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.weak __cxa_pure_virtual ; -- Begin function __cxa_pure_virtual
.p2align 2
.type __cxa_pure_virtual,@function
__cxa_pure_virtual: ; @__cxa_pure_virtual
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_trap 2
s_sendmsg_rtn_b32 s... |
e4e666b66140ce5824c0f0ad31e7e61cd20c2b16_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z12nbody_kernelP8Particlei --------------------------
.section .text._Z12nbody_kernelP8Particlei,"ax",@progbits
... | .text
.file "cuda_code_070792.hip"
.globl _Z27__device_stub__nbody_kernelP8Particlei # -- Begin function _Z27__device_stub__nbody_kernelP8Particlei
.p2align 4, 0x90
.type _Z27__device_stub__nbody_kernelP8Particlei,@function
_Z27__device_stub__nbody_kernelP8Particlei: # @_Z27__device_stub__nbody_kernelP8Particlei
... |
930a2ecc65b1850e90939755a5c1d88b05e193d0_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z11transposeRCPjPfS0_jj --------------------------
.section .text._Z11transposeRCPjPfS0_jj,"ax",@progbits
.sec... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11transposeRCPjPfS0_jj ; -- Begin function _Z11transposeRCPjPfS0_jj
.globl _Z11transposeRCPjPfS0_jj
.p2align 8
.type _Z11transposeRCPjPfS0_jj,@function
_Z11transposeRCPjPfS0_jj: ; @_Z11transposeRCPjPfS0_jj
; %bb.0:
s_load_b64 s[2:3], s[... |
524ec273ddb228581793d4a12b8d42a716f4987a_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv --------------------------
.section .text._ZN3cub17CUB_200700_890_NS11Emp... | .text
.file "cuda_code_063793.hip"
.globl _Z27__device_stub__insertKernelPiS_S_i # -- Begin function _Z27__device_stub__insertKernelPiS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__insertKernelPiS_S_i,@function
_Z27__device_stub__insertKernelPiS_S_i: # @_Z27__device_stub__insertKernelPiS_S_i
.cfi_startproc
# %bb... |
fa293e3604e07b144decc62ef4938312ab82796f_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z3sumIfEvPT_S1_S1_i --------------------------
.section .text._Z3sumIfEvPT_S1_S1_i,"ax",@progbits
.sectioninfo... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.weak __cxa_pure_virtual ; -- Begin function __cxa_pure_virtual
.p2align 2
.type __cxa_pure_virtual,@function
__cxa_pure_virtual: ; @__cxa_pure_virtual
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_trap 2
s_sendmsg_rtn_b32 s... |
4e612d498e2ec06b69d5fad0904615218f27a03e_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z9rsaKernelPyi --------------------------
.section .text._Z9rsaKernelPyi,"ax",@progbits
.sectionflags @"... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9rsaKernelPyi ; -- Begin function _Z9rsaKernelPyi
.globl _Z9rsaKernelPyi
.p2align 8
.type _Z9rsaKernelPyi,@function
_Z9rsaKernelPyi: ; @_Z9rsaKernelPyi
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, ... |
726873b3eb87905a2df2c262bbbd65ebfcb2b689_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z9bfsKernelPiS_S_S_S_S_i --------------------------
.section .text._Z9bfsKernelPiS_S_S_S_S_i,"ax",@progbits
.s... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9bfsKernelPiS_S_S_S_S_i ; -- Begin function _Z9bfsKernelPiS_S_S_S_S_i
.globl _Z9bfsKernelPiS_S_S_S_S_i
.p2align 8
.type _Z9bfsKernelPiS_S_S_S_S_i,@function
_Z9bfsKernelPiS_S_S_S_S_i: ; @_Z9bfsKernelPiS_S_S_S_S_i
; %bb.0:
s_clause 0x1
s_... |
900738955836d58a72d6aedd7dff706c7ed0b866_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z22geneticAlgorithmKernelPfS_P17curandStateXORWOW --------------------------
.section .text._Z22geneticAlgorithmKernel... | .text
.file "cuda_code_081750.hip"
.globl _Z37__device_stub__geneticAlgorithmKernelPfS_P12hiprandState # -- Begin function _Z37__device_stub__geneticAlgorithmKernelPfS_P12hiprandState
.p2align 4, 0x90
.type _Z37__device_stub__geneticAlgorithmKernelPfS_P12hiprandState,@function
_Z37__device_stub__geneticAlgorithmKe... |
d739db9be0c36f471f93c988cc7c4ac24e4bff5d_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z28PossionImageCloningIterationPKfS0_PfS1_iii --------------------------
.section .text._Z28PossionImageCloningIterati... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28PossionImageCloningIterationPKfS0_PfS1_iii ; -- Begin function _Z28PossionImageCloningIterationPKfS0_PfS1_iii
.globl _Z28PossionImageCloningIterationPKfS0_PfS1_iii
.p2align 8
.type _Z28PossionImageCloningIterationPKfS0_PfS1_iii,@function
_Z28Possion... |
27762e1723118ad5cec69f4834e7b604552f3eaf_O2 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z25fluidStructureInteractionPfS_S_fi --------------------------
.section .text._Z25fluidStructureInteractionPfS_S_fi,"... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.weak __cxa_pure_virtual ; -- Begin function __cxa_pure_virtual
.p2align 2
.type __cxa_pure_virtual,@function
__cxa_pure_virtual: ; @__cxa_pure_virtual
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_trap 2
s_sendmsg_rtn_b32 s... |
a33c54304a0b0cdc78328656a4ae805ac7893b5c_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z21globalMemOffsetKernelv --------------------------
.section .text._Z21globalMemOffsetKernelv,"ax",@progbits
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.weak __cxa_pure_virtual ; -- Begin function __cxa_pure_virtual
.p2align 2
.type __cxa_pure_virtual,@function
__cxa_pure_virtual: ; @__cxa_pure_virtual
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_trap 2
s_sendmsg_rtn_b32 s... |
d6741a0805ea1a6b43e4af8b63f069332adbe01c_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z13update_labelsiPbS_PiS0_S0_ --------------------------
.section .text._Z13update_labelsiPbS_PiS0_S0_,"ax",@progbits
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11init_labelsiPiS_S_ ; -- Begin function _Z11init_labelsiPiS_S_
.globl _Z11init_labelsiPiS_S_
.p2align 8
.type _Z11init_labelsiPiS_S_,@function
_Z11init_labelsiPiS_S_: ; @_Z11init_labelsiPiS_S_
; %bb.0:
s_clause 0x1
s_load_b32 s3, s... |
6371e4ddfad7246f2580aba7c1a34dec43f1605f_O1 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z9insertKeyP9BTreeNodeii --------------------------
.section .text._Z9insertKeyP9BTreeNodeii,"ax",@progbits
.s... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.weak __cxa_pure_virtual ; -- Begin function __cxa_pure_virtual
.p2align 2
.type __cxa_pure_virtual,@function
__cxa_pure_virtual: ; @__cxa_pure_virtual
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_trap 2
s_sendmsg_rtn_b32 s... |
d2f09eb45391c5b30bcbe75f94443b9bf51b82fc_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z9mulKernelPKiS0_Pii --------------------------
.section .text._Z9mulKernelPKiS0_Pii,"ax",@progbits
.sectionin... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9mulKernelPKiS0_Pii ; -- Begin function _Z9mulKernelPKiS0_Pii
.globl _Z9mulKernelPKiS0_Pii
.p2align 8
.type _Z9mulKernelPKiS0_Pii,@function
_Z9mulKernelPKiS0_Pii: ; @_Z9mulKernelPKiS0_Pii
; %bb.0:
s_clause 0x1
s_load_b32 s3, s[0:1... |
0aae2e3c7ab05292214949b8999461687d7bb33f_O0 | .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM89 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM89)"
.elftype @"ET_EXEC"
//--------------------- .text._Z18BP_queens_root_dfsijiPK10queen_rootPyS2_ --------------------------
.section .text._Z18BP_queens_root_dfsijiPK10que... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18BP_queens_root_dfsijiPK10queen_rootPyS2_ ; -- Begin function _Z18BP_queens_root_dfsijiPK10queen_rootPyS2_
.globl _Z18BP_queens_root_dfsijiPK10queen_rootPyS2_
.p2align 8
.type _Z18BP_queens_root_dfsijiPK10queen_rootPyS2_,@function
_Z18BP_queens_root_... |
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