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# Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop

Advanced Physical Design using OpenLANE/Sky130 Workshop is a five day workshop conducted by VSD-IAT.

![image](https://user-images.githubusercontent.com/60011091/119861437-04d26000-bf35-11eb-9515-85b05a1788d5.png)

![image](https://user-images.githubusercontent.com/60011091/123736349-992a3c80-d8be-11eb-8b7d-0595b9aec4ab.png)

## Day wise Workshop topics

- [Day-1 Inception of open-source EDA OpenLANE and Sky130 PDK](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Day-1-Inception-of-open-source-EDA-OpenLANE-and-Sky130-PDK)
  * [How to talk to computers](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#How-to-talk-to-computers)
  * [SOC and OpenLane](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#SOC-and-OpenLane)
  * [Open source EDA tools Lab](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Open-source-EDA-tools-Lab)
  * [OpenLane Github link](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#OpenLane-Github-link)

- [Day-2 Understand importance of good floorplan vs bad floorplan and introduction to library cells](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Day-2-Understand-importance-of-good-floorplan-vs-bad-floorplan-and-introduction-to-library-cells)
  * [Chip Floorplanning considerations](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Chip-Floorplanning-considerations)
  * [Lab for Floorplanning](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Lab-for-Floorplanning)
  * [Library Binding and Placement](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Library-Binding-and-Placement)
  * [Lab For Placement](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Lab-For-Placement)
  * [Cell Design Flow](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Cell-Design-Flow)
  * [Timing Threshold Definitions](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Timing-Threshold-Definitions)

 - [Day-3 Design and characterize one library cell using Magic Layout tool and ngspice](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Day-3-Design-and-characterize-one-library-cell-using-Magic-Layout-tool-and-ngspice)
  * [Lab for CMOS inverter ngspice simulations](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Lab-for-CMOS-inverter-ngspice-simulations)
  * [SPICE Deck creation and simulation for CMOS Inverter](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#SPICE-Deck-creation-and-simulation-for-CMOS-Inverter)
  * [Lab to git clone vsdstdcell design](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Lab-to-git-clone-vsdstdcell-design)
  *  [Inception of Layout Fabrication process](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Inception-of-Layout-Fabrication-process)
  *  [Lab for Sky130 basic layer and LEF using inverters](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Lab-for-Sky130-basic-layer-and-LEF-using-inverters)
  *  [Lab for creating SPICE final Deck using Sky130 tech](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Lab-for-creating-SPICE-final-Deck-using-Sky130-tech)

  - [Day-4 Pre-layout timing analysis and importance of good clock tree](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#DAY-4-Pre-layout-timing-analysis-and-importance-of-good-clock-tree)
  * [Labs to convert grid info to track info](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Labs-to-convert-grid-info-to-track-info)
  * [Labs to convert magic layout to std cell LEF](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Labs-to-convert-magic-layout-to-std-cell-LEF)
  * [Configuring synthesis settings to fix Slack and include vsdinv](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Configuring-synthesis-settings-to-fix-Slack-and-include-vsdinv)
  * [Power Aware CTS](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Power-Aware-CTS)
  * [Setup Timing Analysis](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Setup-Timing-Analysis)
  * [Clock Jitter and uncertainty](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Clock-Jitter-and-uncertainty)
  * [Lab for Floorplanning and Placement](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Lab-for-Floorplanning-and-Placement)

  - [Day-5 Final steps for RTL2GDS](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Day-5-Final-steps-for-RTL2GDS)
  * [Lab for Power Distribution Network Routing DRC Check and SPEF Extraction](https://github.com/Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop/blob/main/README.md#Lab-for-Power-Distribution-Network-Routing-DRC-Check-and-SPEF-Extraction)
  *

## Day-1 Inception of open-source EDA OpenLANE and Sky130 PDK

### How to talk to computers

#### Introduction to QFN-48 Package,chips,pads,core,die and IPs

![141352](https://user-images.githubusercontent.com/60011091/123891647-db16b980-d976-11eb-9b08-95791ae9a9e9.png)

Here we can see an Arduino board which you might have bought from the market and even worked on it. This a typical electronic circuit. But here the field we are talking about is  inside the circled part that is the chip.

![image](https://user-images.githubusercontent.com/60011091/123920622-c866a980-d9a3-11eb-9ca3-e74bbe9b3422.png)

This image is the block diagram of the above arduino board image and the circled part in the previous image is shown in this figure as a Processor/SOC.

![image](https://user-images.githubusercontent.com/60011091/123920490-a1a87300-d9a3-11eb-9a1e-a7089e404348.png)

When we open up the  IC from Arduino Board we will be seeing as the above image. We will be calling this as a package and it's named as QFN 48 (Quad Flat No-leads)

The image shown below shows where our chip will be located and how it's connected to the package.

![image](https://user-images.githubusercontent.com/60011091/123919556-a9b3e300-d9a2-11eb-9af8-e7eded559c15.png)

![image](https://user-images.githubusercontent.com/60011091/123921098-4925a580-d9a4-11eb-9929-5c76c11ccbb8.png)

This image shows the inside part of the chip which has pads, cores and dies. Pad is an component through which signal can be sent inside the chip. From the marked parts we see core which in the middle of the chip where all our digital logic circuits sits and logic circuits can be any basic gates, MUX's or can be any different kind of logics. Die is the size of the entire chip.

![image](https://user-images.githubusercontent.com/60011091/123922385-9b1afb00-d9a5-11eb-9540-4dd87a3f2c13.png)

This image is the example or sample of RISCV inside a chip.

###### Foundry and Foundry IPs

![image](https://user-images.githubusercontent.com/60011091/123939500-cf96b300-d9b5-11eb-9522-e3c244ded386.png)

This image depicts which are the components present in the above image are foundry related IPs like dac adc0, adc1, pll and SRAM.

A mobile phone for example depends on the foundry. Foundry is like a factory with alot of machines where chips are manufactured.Then sir had shared his experience on working in a foundry of IIT Bombay where he and his team worked in lithography domain. As VLSI engineers our job is to continuously communicate with foundry.

##### RISCV Introduction

Here we see about RISCV Instruction Set Architecture (ISA) which is a language of the computer and this is the way we are going to talk to a computer.

![tempsnip](https://user-images.githubusercontent.com/60011091/124063611-dde5dd00-da50-11eb-9f73-01bc2fe89c14.jpg)

From the above image we want to pass this C program to a hardware of the above layout in a certain way or in a certain flow. This is done by  firstly compiling C in its assembly language program ie RISCV assembly language program then this assembly language is converted to machine language which is basically the binary 1s and 0s understood by the hardware of the computer.

The above image also shows the output in hexadecimal format which is converted to binary format and finally these bits gets executed in the above layout of the hardware and we receive the required output.

There is another interface required between RISCV Architecture and the layout of the hardware ie hardware description language which can be Verilog or VHDL or System verilog. We are implementing RISCV Architecture using some RTL but here we take an example of picorv32 cpu core which takes  RISCV Architecture as specifications and implements in hardware description language and finally from the RTL to layout which is nothing but a standard PnR or a standard RTL to GDS fLow.

##### Software Applications to Hardware

![image](https://user-images.githubusercontent.com/60011091/123945643-ffe15000-d9bb-11eb-8d78-48cefe7ba5bf.png)

The above image shows the Apps or Application Softwares used in our PC. These apps run in the computer hardware shown in the below image.

![image](https://user-images.githubusercontent.com/60011091/123946253-9f9ede00-d9bc-11eb-88bc-de2c3e39308b.png)

![image](https://user-images.githubusercontent.com/60011091/124062338-3071ca00-da4e-11eb-990f-7f2a6a185534.png)

The above image shows the flow of Application Software running in Hardware of Computer using System Softwares which consists of OS, Compiler and Assembler.

### SOC and OpenLane

#### SOC Design using OpenLane

This lecture was given by Mohamed Shalan who talked about OpenLane and its features.

Designing digital application specific integrated circuits (ASIC) require certain elements like RTL IP's (which is a hardware description model or functions), EDA tools and
Process Design Kits (PDKS). The same is shown in the image given below.

![image](https://user-images.githubusercontent.com/60011091/123952883-3ae78180-d9c4-11eb-9966-17f0ab7be254.png)

Some of the best websites to acquire RTL Designs include:

librecores.org
opencores.org
github.com

EDA Software tools include Qflow, OpenROAD and OpenLane.

PDK is the interface between FAB and the designers. It includes collection of files used to model a fabrication process for EDA tools used to design an IC such as:

- Process Design Rules: DRC, LVS, PEX
- Device Models
- Digital Standard Libraries
- I/O Libraries

On June 30, 2020 Google on collaboration with skywater technology released the first open source pdk ie 130nm process skywater to the masses.

![image](https://user-images.githubusercontent.com/60011091/123956209-0c6ba580-d9c8-11eb-9718-c56332c98ba1.png)

The above image demonstrates various steps involved in EDA Tools

##### Simplified RTL to GDSII Flow

![image](https://user-images.githubusercontent.com/60011091/123957671-b3047600-d9c9-11eb-974e-dbd6a039eca3.png)

This images shows the Simplified flow from RTL design to GDSII

###### Synthesis

-Conversion of RTL design to a circuit out of components from Standard cell library (SCL). We have a small sample code of always block as shown below:

           always @ (posedge clk)
             if(c) q<=a;
             else q<=b;

![Flow_Workspace](https://user-images.githubusercontent.com/60011091/123964569-2bbb0080-d9d1-11eb-89bb-4908d7a07f44.jpg)

Standard Cells have regular layout. Each has different views/models

-Electrical, HDL, SPICE,
-Layout (Abstracted and Detailed)

###### Floor and Power Planning

Chip Floorplanning - Patitioning the chip die between different system blocks and placing the I/O pads

![image](https://user-images.githubusercontent.com/60011091/123965874-830da080-d9d2-11eb-8801-bf2c87292754.png)

The above image describes the Chip Floorplanning

Macro Floorplanning - We define the macro dimensions, pin locations and row definitions.

![image](https://user-images.githubusercontent.com/60011091/123966387-03340600-d9d3-11eb-8a03-494b72f72228.png)

Power Planning - Power network is constructed typically by multiple VDD and GND pins. the Power pins are all connected through power rings, vertical and  horizontal metal straps.

Power rings- Power ring is designed around the core. Power rings contains both VDD and VSS rings. After the ring is placed a power is designed such that power reaches all the cells easily.

![image](https://user-images.githubusercontent.com/60011091/123967363-ddf3c780-d9d3-11eb-8b41-6f8f8ce56882.png)

This diagram shows the power planning components.

These parallel structures reduce resistance. To address electromagnetism the power distribution network uses upper metal layers as they are thicker than lower metal layers

###### Placement

Placing the cell on the floorplan rows aligned with sites. Connected cells should be placed close to each other to reduce the interconnect delay. It is done in two steps ie Global and Detailed Placement. In global placement , the approximate locations for cells is decided by placing cells in global bins. In detailed placement, cells are Placed without over lapping.

![image](https://user-images.githubusercontent.com/60011091/123968734-22339780-d9d5-11eb-89eb-0ab9dfc5aca2.png)

###### CTS (Clock Tree synthesis)

Creating a clock distribution network :

-Delivering clock to all sequential elements.
- With Minimum skew
- In Good shape
- A tree (H,X etc)

![image](https://user-images.githubusercontent.com/60011091/123969507-eb11b600-d9d5-11eb-9a0d-affcbfc897e5.png)

###### Routing

Implements interconnects using available metal layers. Metal tracks form a routing grid. Routing uses Divide and Conquer method.

There are two types of Routing ie
-Global routing: Generates routing guides
-Detailed routing: Uses routing guides to implement actual wiring.

![image](https://user-images.githubusercontent.com/60011091/123969880-40e65e00-d9d6-11eb-82aa-b60741c7a9af.png)

###### Sign Off

-Physical Verifications

-> Design Rules Checking (DRC)
-> Layout vs Scchematic (LVS)

-Timing Verification

-> Static Timing Analysis (STA)

##### OpenLane and Strive chipsets

Open source ASIC flow tools we need to worry about:

-Tools Qualification
-Tools Calibration
-Missing Tools

Efabless decided to create Open source ASIC implementation and flow called as OpenLane which has a public repo in github and is having Apache Version 2.0 license. This OpenLane started as Open-Source Tape Out experiment.

Strive-  a family of open everything SOCs ie Open PDK, Open EDA and Open RTL.

![image](https://user-images.githubusercontent.com/60011091/123983062-32517400-d9e1-11eb-8e73-354059050687.png)

![image](https://user-images.githubusercontent.com/60011091/123989279-5f545580-d9e6-11eb-9bc1-ca51ea4ac738.png)

This image shows the features of Strive SOCS and its features.

The main goal of OpenLane was to produce a clean GDSII without human interventions. So that means, No LVS Violations! NO DRC Violations! or Timing Issues.

OpenLane was tuned for the Skywater 130nm Open PDK. OpenLane is containerized for making it functional out of the box and for building instruction and running natively. Can be used to harden macros and Chips.

It has two modes of operations ie:

-Autonomous -> It is a push button flow where we configure the design and run the design and obtain the final GDSII along with reports for this flow.

-Interactive -> We run individual commands and steps one by one in an ordered fashion without skipping any step so we can do experimentation and get the idea of how our result will look like.

It has the feature of Design Space Exploration where we can find the best set of flow configurations.It has larger number of design examples which ia around 43 designs with best configurations and some more on the way.

###### OpenLane Detailed ASIC Flow

![image](https://user-images.githubusercontent.com/60011091/123989549-a04c6a00-d9e6-11eb-835a-48e86fb0dd8c.png)

 This image shows the OpenLane Detailed ASIC Flow

 This Flow is based on OpenROAD, Klayout, Yosys, Magic, Qflow, Fault and ABC etc.

![image](https://user-images.githubusercontent.com/60011091/123990116-2072cf80-d9e7-11eb-99c9-9ef5d671b704.png)

![image](https://user-images.githubusercontent.com/60011091/123990295-44361580-d9e7-11eb-969c-9eb20616da38.png)

![image](https://user-images.githubusercontent.com/60011091/123990414-5dd75d00-d9e7-11eb-98bc-f0ddb3a5e7a5.png)

![image](https://user-images.githubusercontent.com/60011091/123990478-6e87d300-d9e7-11eb-964c-4db4cfae505c.png)

The above image is for Yosys. Yosys takes RTL code and .lib files as input and netlist as output.

![image](https://user-images.githubusercontent.com/60011091/123990753-ae4eba80-d9e7-11eb-8750-f028afe00541.png)

![image](https://user-images.githubusercontent.com/60011091/123991096-084f8000-d9e8-11eb-8b6b-7763f948481e.png)

###### Design Exploration

![image](https://user-images.githubusercontent.com/60011091/123991469-60868200-d9e8-11eb-93c5-b8669fb9a2e0.png)

This image shows the design exploration details such as design name,total runtime for the design flow, cell counts and other details which is tabulated for users to understand the design explorations.

We can do regression testing for these designs as well.

###### DFT

This step is optional in OpenLane which includes scan insertions, ATPGS, Test pattern compaction, fault coverge and fault simulation.

![image](https://user-images.githubusercontent.com/60011091/123992809-8fe9be80-d9e9-11eb-9826-68a0852fa4c9.png)

###### Logic Equivalence Circuit (LEC)

This check is used to formally confirm that the function did not change after modifying the netlist.

###### Fake antenna diode insertion

This step is done to deal with antenna violations caused during reaction ion etching which causes charge to accumlate metal wires which in turn damages the transition gates.

![image](https://user-images.githubusercontent.com/60011091/123994454-0509c380-d9eb-11eb-84b4-7f6ff936915c.png)

### Open source EDA tools Lab

#### OpenLane directory Structure

OpenLane is a flow rather than a tool which comprises of many open source EDA tools.

        $ cd Desktop/work/tools
        $ ls -ltr
        $ cd openlane_working_dir

![image](https://user-images.githubusercontent.com/60011091/123998643-4e5c1200-d9ef-11eb-9104-4d49016dd6a1.png)

        $ ls -ltr
        $ cd pdks
        $ ls -ltr
        $ cd sky130A
        $ ls -ltr

![image](https://user-images.githubusercontent.com/60011091/123998685-5a47d400-d9ef-11eb-8625-116a61713dfc.png)

![image](https://user-images.githubusercontent.com/60011091/123999153-d3472b80-d9ef-11eb-859e-b58fc20fe150.png)

           $ ls -ltr
           $ cd libs.ref
           $ ls -ltr
           $ cd ../
           $ cd libs.tech
           $ ls -ltr
           $ cd ../libs.ref
           $ cd sky130_fd_sc_hd
           $ ls -ltr

![image](https://user-images.githubusercontent.com/60011091/123999377-143f4000-d9f0-11eb-9adf-a9753964dce4.png)

![image](https://user-images.githubusercontent.com/60011091/123999668-654f3400-d9f0-11eb-9021-4798cf0f37c2.png)

![image](https://user-images.githubusercontent.com/60011091/124000056-d393f680-d9f0-11eb-8dbd-825813730b38.png)

           $ ls -ltr
           $ cd lib
           $ ls -ltr

![image](https://user-images.githubusercontent.com/60011091/124000551-53ba5c00-d9f1-11eb-8e06-02e28f538137.png)

![image](https://user-images.githubusercontent.com/60011091/124000624-63d23b80-d9f1-11eb-991d-3568657f13a4.png)

#### Preparation of OpenLane

Interactive flow of OpenLane

          $ cd../../
          $ cd../../../
          $ cd openlane_working_dir
          $ cd openlane

![image](https://user-images.githubusercontent.com/60011091/124000925-b7448980-d9f1-11eb-888a-92c6f81144ef.png)

         $make mount
         bash-4.2$ pwd
         bash-4.2$ ls -ltr
         bash-4.2$ ./flow.tcl -interactive

![image](https://user-images.githubusercontent.com/60011091/124001831-a8120b80-d9f2-11eb-96a9-62c6a6f48a4d.png)

The below images shows the designs in the OpenLane design folder

         $ cd designs
         $ ls -ltr

![image](https://user-images.githubusercontent.com/60011091/124002383-4b632080-d9f3-11eb-80f4-926802183ea9.png)

![image](https://user-images.githubusercontent.com/60011091/124002543-81a0a000-d9f3-11eb-8a4c-666c149b8b8e.png)

Picorv32a is the design and its contents are shown in the below images.

         $ cd picorv32a
         $ ls -ltr
         $ cd src
         $ ls -ltr

![image](https://user-images.githubusercontent.com/60011091/124002670-a5fc7c80-d9f3-11eb-8ba1-51f17b68d317.png)

![image](https://user-images.githubusercontent.com/60011091/124003865-05a75780-d9f5-11eb-8f97-b47eed575f61.png)

config.tcl file for picorv32a

        $ less config.tcl

![image](https://user-images.githubusercontent.com/60011091/124004206-6cc50c00-d9f5-11eb-9c99-50fc903e6867.png)

![image](https://user-images.githubusercontent.com/60011091/124003977-31c2d880-d9f5-11eb-8659-353934a7113f.png)

sky130_fd_sc_hd_config.tcl for picorv32a

![image](https://user-images.githubusercontent.com/60011091/124004461-a9910300-d9f5-11eb-8d36-dfca069981c1.png)

Preparation of design

      % pacakge require openlane 0.9
      % prep -design picorv32a

![image](https://user-images.githubusercontent.com/60011091/124005058-494e9100-d9f6-11eb-8b01-30b771ae1936.png)

      $ ls -ltr
      $ cd runs
      $ ls -ltr
      $ cd 30-06_17-25
      $ ls -ltr

 The below images shows all the runs of the design specific to date the design was run under run folder from picorv32a design.

![image](https://user-images.githubusercontent.com/60011091/124005417-aa766480-d9f6-11eb-9ee7-6c27221f4cb7.png)

![image](https://user-images.githubusercontent.com/60011091/124005608-e90c1f00-d9f6-11eb-8add-1ff8893dc000.png)

![image](https://user-images.githubusercontent.com/60011091/124005933-47d19880-d9f7-11eb-8310-f08b81415611.png)

merge.lef contents

![image](https://user-images.githubusercontent.com/60011091/124006066-70599280-d9f7-11eb-83c6-1135fd4b1ac4.png)

![image](https://user-images.githubusercontent.com/60011091/124006158-8a937080-d9f7-11eb-8e36-748d512a2ca5.png)

![image](https://user-images.githubusercontent.com/60011091/124006205-967f3280-d9f7-11eb-84b8-9554af7f0e82.png)

config.tcl in reports directory

     $ cd reports
     $ ls -ltr

![image](https://user-images.githubusercontent.com/60011091/124006444-e8c05380-d9f7-11eb-92ee-a14571ac505a.png)

![image](https://user-images.githubusercontent.com/60011091/124006573-10afb700-d9f8-11eb-9418-5887c3ac7f3e.png)

![image](https://user-images.githubusercontent.com/60011091/124006677-2c1ac200-d9f8-11eb-8ed2-140d25937fdc.png)

![image](https://user-images.githubusercontent.com/60011091/124006723-3b017480-d9f8-11eb-9546-16b1375e38ad.png)

##### Synthesized picorv32a design reports

![image](https://user-images.githubusercontent.com/60011091/124007257-d4c92180-d9f8-11eb-9c33-f07cc0eb7b00.png)

Utilization report

![image](https://user-images.githubusercontent.com/60011091/124007498-0b06a100-d9f9-11eb-96a4-fe4c62f3f0ba.png)

DFF Utilization report

![image](https://user-images.githubusercontent.com/60011091/124007742-4608d480-d9f9-11eb-893d-fcb1a169bed4.png)

DFF Ratio

![image](https://user-images.githubusercontent.com/60011091/124009117-d5fb4e00-d9fa-11eb-9ed5-a797804cca5a.png)

OPEN STA Timing report

![image](https://user-images.githubusercontent.com/60011091/124009357-1f4b9d80-d9fb-11eb-8864-162977211f83.png)

![image](https://user-images.githubusercontent.com/60011091/124009412-325e6d80-d9fb-11eb-8586-75454f49df34.png)

![image](https://user-images.githubusercontent.com/60011091/124009587-6a65b080-d9fb-11eb-9488-fbad688d9eeb.png)

### OpenLane Github link

https://github.com/The-OpenROAD-Project/OpenLane

This is the link of the OpenLane with the latest version 0.21.

OpenROAD has 37 repos and OpenLane is one of them.

This project has a well documented installation procedures and how to work post OpenLane and PDKs installations.

We have a lot of options and commands for Github like forking, cloning or download a particular repo in .zip format etc.

## Day-2 Understand importance of good floorplan vs bad floorplan and introduction to library cells

### Chip Floorplanning considerations

#### Utilization Factor and Aspect Ratio

Core is the section of the chip where the fundamental logic of the design are placed

Die which consist of core is a small semiconductor material specimen on which the fundamental circuit is fabricated.

![image](https://user-images.githubusercontent.com/60011091/124116318-75b4ec80-da8c-11eb-91b8-ee30364f44d7.png)

-Netlist occupies the core area leading to 100% utilization.

     Utilization Factor = Area occupied by the Netlist/ Total Area of the core

-Whenever the Utilization Factor=1, the core is fully occupied and we are not allowed to ad any extra cells in our design and the core will take square shaped structure.

     Aspect Ratio= Height/ Width

-Whenever the Aspect Ratio = 1, it signifies that the chip is square shaped. But whenever the Aspect Ratio or Utilization Factor is not 1, then  the chip will take rectangular shaped structure.

####  Preplaced Cells

![IPs_Workspace](https://user-images.githubusercontent.com/60011091/124118719-3e940a80-da8f-11eb-8e60-e6f5b8c704b7.jpg)

-The arrangement of IP's in a chip is called Floorplanning.

-These IP's/blocks have user defined locations and so these are placed in chip before automated placement and routing and are called as pre-placed cells.

-Automated placement and routing tools places the remaining logic cells in the design onto the chip.

### Lab for Floorplanning

##### Running floorplan in OpenLane

Configuration folder of OpenLane

       $ cd configuration
       $ pwd
       $ ls -ltr

![image](https://user-images.githubusercontent.com/60011091/124123465-fc6dc780-da94-11eb-9cbf-89a837b8e6cd.png)

![image](https://user-images.githubusercontent.com/60011091/124124108-af3e2580-da95-11eb-91ce-e1fed9c16612.png)

README.md File

![image](https://user-images.githubusercontent.com/60011091/124123717-3e970900-da95-11eb-81d3-e29abf1acbab.png)

![image](https://user-images.githubusercontent.com/60011091/124123809-5a021400-da95-11eb-9146-20f882f3036e.png)

![image](https://user-images.githubusercontent.com/60011091/124123890-6be3b700-da95-11eb-9b0e-e9b43ff35a7a.png)

 ![image](https://user-images.githubusercontent.com/60011091/124123987-874ec200-da95-11eb-97af-612121f1eb7f.png)

floorplan.tcl file

![image](https://user-images.githubusercontent.com/60011091/124124208-cc72f400-da95-11eb-9b30-17a7c1cbffa4.png)

![image](https://user-images.githubusercontent.com/60011091/124124263-dbf23d00-da95-11eb-8011-107280370ef1.png)

picorv32a Folder contents

     $ cd designs/picorv32a
     $ pwd
     $ ls -ltr

![image](https://user-images.githubusercontent.com/60011091/124124648-558a2b00-da96-11eb-9212-06c426f5f2b9.png)

So the precendence is lowest prioriy is system defaults ie all the tcl files for configuration in OpenLane. The next priority is for config.tcl and the last priority is sky130A_sky130_fd_sc_hd_config.tcl.

Config.tcl for picorv32a

![image](https://user-images.githubusercontent.com/60011091/124125278-0e506a00-da97-11eb-964e-5c17675398b5.png)

Running Floorplanning

    % run_floorplan

![image](https://user-images.githubusercontent.com/60011091/124125504-4b1c6100-da97-11eb-9681-a40ee2993351.png)

![image](https://user-images.githubusercontent.com/60011091/124125612-72732e00-da97-11eb-95ca-b3a678eef150.png)

![image](https://user-images.githubusercontent.com/60011091/124125673-874fc180-da97-11eb-87f0-5641a5dda44d.png)

![image](https://user-images.githubusercontent.com/60011091/124125772-9c2c5500-da97-11eb-84f6-965bdef75fcc.png)

![image](https://user-images.githubusercontent.com/60011091/124125863-b0705200-da97-11eb-88af-2619815c011d.png)

![image](https://user-images.githubusercontent.com/60011091/124125991-d3026b00-da97-11eb-9503-88f6d344b700.png)

 Viewing Floorplanning files

    $ cd picorv32a
    $ less config.tcl
    $ cd runs
    $ ls -ltr
    $ cd 30-06_17-25
    $ ls -ltr
    $ less config.tcl
    $ cd logs/floorplan/
    $ ls -ltr

![image](https://user-images.githubusercontent.com/60011091/124126385-41dfc400-da98-11eb-839a-2f7a69f4179a.png)

![image](https://user-images.githubusercontent.com/60011091/124126556-6b98eb00-da98-11eb-91db-77acfbcb009c.png)

![image](https://user-images.githubusercontent.com/60011091/124126814-abf86900-da98-11eb-8fe0-4d34d6e3ce54.png)

![image](https://user-images.githubusercontent.com/60011091/124127144-0265a780-da99-11eb-8444-c37867a1c682.png)

Config file in the picorv32a runs folder

![image](https://user-images.githubusercontent.com/60011091/124127322-3771fa00-da99-11eb-8902-17aa127e13f0.png)

Picorv32a def file

    $ cd 30-06_17-25
    $ ls -ltr
    $ less picorv32a.floorplan.def

![image](https://user-images.githubusercontent.com/60011091/124127655-a18a9f00-da99-11eb-9bb2-ff556e21e2f2.png)

Opening floorplan using Magic

    $ magic -T /home/john/Desktop/work/tools.openlane_working_dir/openlane/pdks/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def &

![image](https://user-images.githubusercontent.com/60011091/124128834-c7647380-da9a-11eb-8f68-5156d5c50338.png)

![image](https://user-images.githubusercontent.com/60011091/124128983-f1b63100-da9a-11eb-945e-9c9f87c2be67.png)

![image](https://user-images.githubusercontent.com/60011091/124130033-fa5b3700-da9b-11eb-9c25-d650683ad128.png)

![image](https://user-images.githubusercontent.com/60011091/124130672-a866e100-da9c-11eb-8cc9-d70be38d077d.png)

### Library Binding and Placement

Libraries are like shelves which can be divided into two sub libraries like one library will have shapes and sizes informations and the other might have delay related informations.

Steps in Placement is as below

-Binding netlist with physical cell

The image below shows different flavors for same flipflop, gates and other netlists which can differ in sizes, shapes or delay relatedninformations.

![image](https://user-images.githubusercontent.com/60011091/124132170-2972a800-da9e-11eb-8df3-4fd26444a121.png)

-Placement

![image](https://user-images.githubusercontent.com/60011091/124133881-e6b1cf80-da9f-11eb-8008-62749f4d4e14.png)

-Optimize Placement

This is the stage where we estimate the wire length and capacitances so based on that we insert repeaters. As shown below:

![image](https://user-images.githubusercontent.com/60011091/124135078-1a412980-daa1-11eb-9dc9-3718d0ea47cc.png)

###### Need for libraries and characterizations

![Common_Workspace](https://user-images.githubusercontent.com/60011091/124135847-d39fff00-daa1-11eb-8469-c4fcff2f9425.jpg)

This image shows the common things across all the steps in OpenLane flow.

### Lab For Placement

    % run_placement

![image](https://user-images.githubusercontent.com/60011091/124143057-6cd21400-daa8-11eb-8543-b587fa67be30.png)

![image](https://user-images.githubusercontent.com/60011091/124143198-8b380f80-daa8-11eb-8299-57dc7f9663cc.png)

![image](https://user-images.githubusercontent.com/60011091/124143309-a60a8400-daa8-11eb-90aa-f0a85a9b9072.png)

![image](https://user-images.githubusercontent.com/60011091/124143424-bb7fae00-daa8-11eb-8a60-a86e00b763e2.png)

![image](https://user-images.githubusercontent.com/60011091/124143523-d2260500-daa8-11eb-9478-ba293e33f0e5.png)

![image](https://user-images.githubusercontent.com/60011091/124143727-fda8ef80-daa8-11eb-933c-772d1de1bbed.png)

Viewing def file of placement in picorv32a design

    $ cd results/placement
    $ ls

![image](https://user-images.githubusercontent.com/60011091/124144262-6ee8a280-daa9-11eb-8d85-2d9ea7e532f5.png)

Magic Layout after Placement of picorv32a

    $ magic -T /home/john/Desktop/work/tools.openlane_working_dir/openlane/pdks/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &

![image](https://user-images.githubusercontent.com/60011091/124144516-ae16f380-daa9-11eb-85aa-969a87911f1c.png)

![image](https://user-images.githubusercontent.com/60011091/124144972-0ea63080-daaa-11eb-85a9-fe3cead024f7.png)

![image](https://user-images.githubusercontent.com/60011091/124145421-680e5f80-daaa-11eb-8570-fe06d017cd33.png)

![image](https://user-images.githubusercontent.com/60011091/124145514-7e1c2000-daaa-11eb-8fcd-e23edbdaf4ea.png)

### Cell Flow

![Cell_design_Workspace](https://user-images.githubusercontent.com/60011091/124148859-b2dda680-daad-11eb-9e66-5423b5cd0ee8.jpg)

The above image shows what are the components in the Cell flow

The below images talk about DRC and LVS rules in a brief way

![image](https://user-images.githubusercontent.com/60011091/124149347-1f58a580-daae-11eb-9e6e-f2c99dc650f4.png)

![image](https://user-images.githubusercontent.com/60011091/124149468-3dbea100-daae-11eb-84ee-b1c39e760646.png)

The below image explains about SPICE models and shows the formulated equation for Threshold Voltage Equation and for linear and saturated regions of operation for the models.

![Untitled](https://user-images.githubusercontent.com/60011091/124150644-5c716780-daaf-11eb-97c5-85bb276ac718.png)

The below images show an example of SPICE Models From Tanner EDA Tool for 0.18nm technology

![image](https://user-images.githubusercontent.com/60011091/124153976-a60f8180-dab2-11eb-8e3a-a1e888e503c0.png)

![image](https://user-images.githubusercontent.com/60011091/124154041-b6276100-dab2-11eb-9fa9-f6deed66bef9.png)

### Design Steps

-Circuit Design

In circuit design Step

We take user defined specifications like cell height, supply voltage, metal layers and pin locations in this design step for cell flow

![image](https://user-images.githubusercontent.com/60011091/124155570-4023f980-dab4-11eb-982d-12a04f9ddede.png)

The above image is an example of circuit design step where we use Euler's path concept to construct paths for the layout design.

Thhe equation for the circuit is Fn= ((B+D) +(A+C) + E.F)'

![image](https://user-images.githubusercontent.com/60011091/124156347-28994080-dab5-11eb-9564-c83ea607ead5.png)

The above circuit show the equation for Wp/Lp / Wn/Ln ratio to set Vm which is the threshold voltage of the above circuit.

-Layout Design

In layout design as we have mentioned in circuit design that we are using Euler's path concept to construct layout.

So below image is the example of the paths.

![image](https://user-images.githubusercontent.com/60011091/124156740-9e9da780-dab5-11eb-84f2-598c3bc5a3f5.png)

The below image explains the euler's path clearly.

![image](https://user-images.githubusercontent.com/60011091/124156964-df95bc00-dab5-11eb-90f5-545d22b1965a.png)

-Characterization Flow

![image](https://user-images.githubusercontent.com/60011091/124157458-68acf300-dab6-11eb-9a76-14d730dee38f.png)

This schematic is for a buffer which has inverters connected back to back and this is drawn in GUNA Tool.

The below two images shows the netlist for the main circuit and subcircuit for the buffer we have taken in previous image. The third and fourth images are a model parameter file for this SPICE model.

![image](https://user-images.githubusercontent.com/60011091/124157676-a6118080-dab6-11eb-8bbd-d843b819b603.png)

![image](https://user-images.githubusercontent.com/60011091/124157708-b164ac00-dab6-11eb-8567-fe08c0272f02.png)

![image](https://user-images.githubusercontent.com/60011091/124157748-bc1f4100-dab6-11eb-8940-23891c51a7a5.png)

![image](https://user-images.githubusercontent.com/60011091/124158114-2801a980-dab7-11eb-81a0-7c4953abb1b2.png)

This GUNA softwares Takes all the files shown in this sections as inputs and generates outputs as Timing, Noise and  Power .libs.

### Timing Threshold Definitions

Low depicts the values which are close to 0 power supply.

Here in the below concepts we used red line to show inputs and blue for outputs in the graphs.

slew_low_rise_thr- defines the point over the lower side of your power supply which is 0V. Typical value of slew_low_rise_thr is about 20% or can be 30% of bottom power supply.

![image](https://user-images.githubusercontent.com/60011091/124162455-14a50d00-dabc-11eb-9337-acdb9c4ff9f0.png)

The above image depicts the slew_low_rise_thr definition.

slew_high_rise_thr- defines the point over the higher side of power supply. Typical value of slew_high_rise_thr is about 20% or can be 30% of top power supply.

![image](https://user-images.githubusercontent.com/60011091/124162634-49b15f80-dabc-11eb-963c-cddd01d186ad.png)

The above image depicts the slew_high_rise_thr definition.

slew_low_fall_thr

![image](https://user-images.githubusercontent.com/60011091/124165084-115f5080-dabf-11eb-8647-441c1a027448.png)

This images explains slew_low_fall_thr concept.

slew_high_fall _thr

![image](https://user-images.githubusercontent.com/60011091/124163078-d78d4a80-dabc-11eb-8940-63499375737b.png)

This images explains slew_high_fall _thr concept.

in_rise_thr-

![image](https://user-images.githubusercontent.com/60011091/124163518-479bd080-dabd-11eb-8aeb-ed08073383fc.png)

This image explains in_rise_thr concept.

in_fall_thr

![image](https://user-images.githubusercontent.com/60011091/124163924-c133be80-dabd-11eb-8b17-5c6cd57259a2.png)

This image explains in_faLL_thr concept.

out_rise_thr

![image](https://user-images.githubusercontent.com/60011091/124163756-892c7b80-dabd-11eb-921c-18c5876a6df0.png)

This image explains out_rise_thr concept.

out_fall_thr

![image](https://user-images.githubusercontent.com/60011091/124164016-e45e6e00-dabd-11eb-8913-8b98abe9698d.png)

This image explains out_fall_thr concept.

![image](https://user-images.githubusercontent.com/60011091/124164482-51720380-dabe-11eb-8c1c-9cd1456de8af.png)

The above table summarizes the concepts learn in this section all the % is taken from the VDD. in the above Table we see slew_low_rise_thr is 20% of VDD so similarly other % are taken from VDD.

## Day-3 Design and characterize one library cell using Magic Layout tool and ngspice

### Lab for CMOS inverter ngspice simulations

![image](https://user-images.githubusercontent.com/60011091/124224442-47362080-db23-11eb-87c8-e6b7689c07ea.png)

The above image shows the ngspice simulator which we are going to use in this lab.

#### IO Placer Revision

![image](https://user-images.githubusercontent.com/60011091/124339904-1dd2ce80-dbcf-11eb-8f79-7b3ab99def93.png)

The above image indicates the location from where we are trying to read picorv32a.floorplan.def to understand about IO placers in the design in floorplan step.

![image](https://user-images.githubusercontent.com/60011091/124340035-f3354580-dbcf-11eb-9f29-e188798b524e.png)

From the above image we see that by default pins are placed equidistantly from each other.

![image](https://user-images.githubusercontent.com/60011091/124340100-6f2f8d80-dbd0-11eb-9d73-ca2c5502339a.png)

This is the zoomed version of the previous image to show that the pin are placed equidistantly from each other.

![image](https://user-images.githubusercontent.com/60011091/124340363-4e683780-dbd2-11eb-87ad-2bad0a0e3484.png)

Here in the image we see FP_IO_MODE is set to 1, 0 for matching mode and 1 for random equidistant pins.

![image](https://user-images.githubusercontent.com/60011091/124340446-05fd4980-dbd3-11eb-823c-cd1bcdf1a465.png)

Here we are setting FP_IO_MODE to 2 in the above image.

![image](https://user-images.githubusercontent.com/60011091/124340627-18c44e00-dbd4-11eb-91af-a501b4f8bbc2.png)

This is the layout we will be getting where pins are not equidistant from each other but pins are stacked upon one another.

### SPICE Deck creation and simulation for CMOS Inverter

##### SPICE Deck creation

-SPICE Deck is nothing but the connectivity information about the netlist.

This has the connectivity information, inputs to be provided to the simulator, tap points at which we will take the  outputs etc.

![image](https://user-images.githubusercontent.com/60011091/124341467-41e7dd00-dbda-11eb-91b1-8a5f5f566747.png)

We are going to create SPICE Deck for the circuit in the above image.

- Defining component value ie values of PMOS and the NMOS.

Here we have taken W/L ratio for PMOS (M1) and NMOS (M2) to be 0.375u/0.25u and Cload as 10 fF

![image](https://user-images.githubusercontent.com/60011091/124343934-f5f26380-dbec-11eb-8263-050b2a4c2e57.png)

Here the above image is extended circuit of the just previous circuit which has input gate voltage as 2.5V and VDD as 2.5V based on technology used so here we use 0.25u 0r 250nm technology.
cvxz
-Identifying the nodes in the circuit

![image](https://user-images.githubusercontent.com/60011091/124344067-f5a69800-dbed-11eb-885f-9ce7ed60a4ca.png)

This image shows the nodes indicated by blue dotted lines.

-Naming the nodes

From the identifying nodes image we are naming the nodes as in which is between Vin and VSS, out for the node which is connected to Cload of 10fF and vdd as node connecting VDD and Vss and is shown as below

![image](https://user-images.githubusercontent.com/60011091/124344601-d1988600-dbf0-11eb-9d50-abf11ee62221.png)

SPICE Deck is written as shown below:

    ** Model Descriptions **
    ** Netlist Descriptions **
    M1 out in vdd vdd pmos W=0.375u L=0.25u
    M2 out in 0  0  nmos W=0.375u L=0.25u

    cload out 0 10f

    Vdd vdd 0 2.5
    Vin in  0 2.5

    *** Simulation Commands ***
    .op
    .dc Vin 0 2.5 0.05
    *** .include tsmc _025um_model.mod   ***
    .LIB "tsmc _025um_model.mod" CMOS_MODELS
    .end

 ![image](https://user-images.githubusercontent.com/60011091/124345300-c3993400-dbf5-11eb-9ae3-ee00055accb6.png)

The above image is the ngspice window.

![image](https://user-images.githubusercontent.com/60011091/124345339-f6dbc300-dbf5-11eb-9b4c-2febf6adad18.png)

The above image shows the technology file of 0.25um technology

![image](https://user-images.githubusercontent.com/60011091/124345391-2db1d900-dbf6-11eb-8f7b-24d476ed5518.png)

The location of the technology file is passed as command in the above image.

Then we give

    ngspice2 -> cmosVTC_PMOSwidth_NMOSwidth.cir

Executing the circuit

    ngspice3 -> run
    ngspice4 -> setplot

   ![image](https://user-images.githubusercontent.com/60011091/124345508-eaa43580-dbf6-11eb-8e34-e31276b60709.png)

   This image tells us as to what has happened after passing setplot command. So dc1 is for dc characteristics, op1 for operating point and const for constant values.

    ngspice5 -> dc1
    ngspice5 -> display    --->displays nodes in the circuit
    ngspice6 -> out vs in      ---> plotting input node vs output node

![image](https://user-images.githubusercontent.com/60011091/124345641-d876c700-dbf7-11eb-8720-9437e3f8f073.png)

This is the Voltage characteristics of the given CMOS inverters

#### Switching Vm

![image](https://user-images.githubusercontent.com/60011091/124345749-5509a580-dbf8-11eb-9af0-e685350e905e.png)

This image compares two different devices having different W/L ratios. Even though the switching occurs at different places the waveforms are the same. this shows the robustness of CMOS inverters interms of its apllications

   Vm is the point where vin=vout

   ![image](https://user-images.githubusercontent.com/60011091/124346008-f8a78580-dbf9-11eb-801e-4cd033fae733.png)

From the image 1st graph had Vm around 0.98V and 2nd one had Vm as 1.25V approximately.

### Lab to git clone vsdstdcell design

    $ pwd     -Your present working directory should be openlane directory
    $ git clone https://github.com/nickson-jose/vsdstdcelldesign.git
    $ ls -ltr
    $ cd vsdstdcelldesign
    $ ls -ltr

![image](https://user-images.githubusercontent.com/60011091/124346214-3eb11900-dbfb-11eb-8ea2-9e295781fe86.png)

![image](https://user-images.githubusercontent.com/60011091/124346380-17a71700-dbfc-11eb-8fac-08dc64294609.png)

Copying sky130A.tech

     $ cd ../../       -->cding to openlane_working_dir
     $ pdks/sky130A/libs.tech/magic
     $ ls -ltr
     $ cp sky130A.tech /home/john/Desktop/work/tools/openlane_working_dir/openlane/vsdstdcelldesign

 The below image made use of the above commands for copying sky130.tech

![image](https://user-images.githubusercontent.com/60011091/124346520-e11dcc00-dbfc-11eb-9481-c334b9e01c82.png)

    $ cd /openlane/vsdstdcelldesign
    $ ls -ltr
    $ magic -T sky130A.tech sky130_inv.mag &

![image](https://user-images.githubusercontent.com/60011091/124346820-9c933000-dbfe-11eb-9ad5-c66297913498.png)

Viewing sky130_inv.mag in Magic Layout tool

![image](https://user-images.githubusercontent.com/60011091/124346851-cea49200-dbfe-11eb-9d70-02d8a154e405.png)

### Inception of Layout Fabrication process

We take a 16-mask CMOS process

-Selecting a substrate

Here we go for P type substrate with high resistivity, doping level as 10^15 cm^-3 and orientation as 100

-Creating active region for transistors

Here we are creating small pockets or buckets as active region on the ptype substrate where we will create pmos and nmos transistors

-> Grow Silicon on Silicon dioxide which acts as an insulator.
-> Deposit a layer silicon nitride.
-> Deposit a layer of photoresist.
-> Then we create  mask1 and UV light is passed through the layer.
-> Washing out photoresist.
-> Removing the mask.
-> Etching the silicon nitride.
-> Etching the resist from the layer.
-> Placed in oxidation furnace.
-> Growing field oxide. This process is called LOCOS.
-> Etching the remaining silicon nitride using phosphoric acid.

- N well and P well formation

For P well formation
-> Deposit a layer of photoresist.
-> Then we create  mask2 and UV light is passed through the layer
-> Washing out photoresist.
-> Removing the mask.
-> Creating P well using Boron by ion implantation.

For N well formation

-> Deposit a layer of photoresist.
-> Then we create  mask3 and UV light is passed through the layer
-> Washing out photoresist.
-> Removing the mask.
-> Creating N well using Phosphorus by ion implantation.

-> Placing the layer consisting of P well and N well in high temperature furnace.
-> diffuse the boron and the phosphorus atoms
->This forms a twin tub.

- Formation of gate terminal

Controlling doping concentration can be done by:

For N well gate formation

-> Deposit a layer of photoresist.
-> Then we create  mask2 and UV light is passed through the layer.
-> Washing out photoresist.
-> Removing the mask.
-> Introducing boron with lower energy by ion implantation which inturn controls the threshold voltage.

For P well gate formation

-> Deposit a layer of photoresist.
-> Then we create  mask2 and UV light is passed through the layer.
-> Washing out photoresist.
-> Removing the mask.
-> Introducing arsenic with lower energy by ion implantation which inturn controls the threshold voltage.
-> Original oxide is removed/stripped using hydrofluoric acid.
-> Regrowing oxide again to provide high quality oxide.
-> Deposit a polysilicon layer.
-> N type ion implants for low gate resistance.
-> Deposit a layer of photoresist.
-> Then we create  mask6.
-> Etching the resist from the layer.
-> Removing the mask.
->Remaining polysilicon layer outside the photoresist can be etched away.
-> Removing the remaining resist.

-Lightly doped drain formation(LDD)

-> For this we need doping profiles like P+,P- and N along N well and N+, N- and P along P well side.
-> Reasons for these profiles: Hot electron effect and short channel effect.

 For N well

 -> Deposit a layer of photoresist.
 -> Then we create  mask7
 -> Washing out photoresist.
 -> Introducing phosphorus by ion implantation.
 -> Removing phtoresist from n well and apply photoresist and mask8 on pwell.
 -> Removing mask from p well.
 -> Introducing  boron by ion implantation.
 -> We add spacers by depositing a thick SiO2 or Si3N4 layer on the complete structure and then we apply plasma anisotropic etching.

 - Source and drain formation

-> Thin screen oxide is added to avoid channeling during implants.
-> Deposit a layer of photoresist.
-> Then we create  mask9 in Nwell side.
-> Removing mask from nwell after it's exposed to other implants
-> introducing Arsenic byion implantation.

We apply the same process to P well side but now the mask used will be mask10. Then we introduce a p type impurity like boron. We apply high temperature furnace to the structure.

### Lab for Sky130 basic layer and LEF using inverters

![image](https://user-images.githubusercontent.com/60011091/124351059-db80b000-dc15-11eb-86fd-52987d5d287a.png)

![image](https://user-images.githubusercontent.com/60011091/124351132-374b3900-dc16-11eb-9066-81d2531b5975.png)

Here in the imageswe highlighted a sub layer and we used the command as below:

    % what

 Difference between layout and LEF

 ![image](https://user-images.githubusercontent.com/60011091/124351202-990ba300-dc16-11eb-96da-6a8f37fd80e4.png)

The above image is the layout the inverter.

The layout will have all the informations from metal layers,vias and all the logical and other informations.

![image](https://user-images.githubusercontent.com/60011091/124351269-fbfd3a00-dc16-11eb-9f7d-6c4dc9dc3afe.png)

 The above image was taken from Nickson Jose's vsdstdcell design repo.

 But LEF reveals only the metal layers without exposing any logical part of the design. For Pnr of the cell we don't need any logic of the cell and all we need to know where are the Pr boundaries.

### Lab for creating basic std cell layout and extracting spice netlist

![image](https://user-images.githubusercontent.com/60011091/124351854-68c60380-dc1a-11eb-91f7-c1b62d0533e2.png)

This image shows DRC errors in the layout if we move layers intentionally and unintentionally.

       $extract all

![image](https://user-images.githubusercontent.com/60011091/124352119-10900100-dc1c-11eb-9cd4-264a981cec9c.png)

This image shows the command for extracting netlist from an inverter layout using tkcon command window.

       $ ls -ltr    ---> under vsdstdcelldesign directory

![image](https://user-images.githubusercontent.com/60011091/124352263-0c181800-dc1d-11eb-8512-991052b17203.png)

This image shows that the previous command extract all has created a file called sky130_inv.ext in vsdstdcelldesign directory.

        $ ext2spice cthesh 0 rthresh 0
        $ ext2spice

![image](https://user-images.githubusercontent.com/60011091/124352683-7762e980-dc1f-11eb-8224-c7471f776807.png)

This image shows that the above commands for extracting spice from an inverter layout using tkcon command window.

        $ ls -ltr    ---> under vsdstdcelldesign directory

![image](https://user-images.githubusercontent.com/60011091/124352782-2b647480-dc20-11eb-90b9-a54014a08bb3.png)

This image shows that the previous command extract 2 spice commands extracts inverter layout to spice format in vsdstdcelldesign directory.

The below images shows the contents of sky130_inv.spice

       $ vim sky130_inv.spice

![image](https://user-images.githubusercontent.com/60011091/124353281-42589600-dc23-11eb-9696-a6f953f9bf95.png)

![image](https://user-images.githubusercontent.com/60011091/124353267-2b19a880-dc23-11eb-9858-236887d1e920.png)

### Lab for creating SPICE final Deck using Sky130 tech

![image](https://user-images.githubusercontent.com/60011091/124353267-2b19a880-dc23-11eb-9858-236887d1e920.png)

The above image is the initial SPICE Deck netlist

 The below image shows where pshort.lib and n.short.lib is located

         $ cd libs
         $ ls -ltr

![image](https://user-images.githubusercontent.com/60011091/124353679-89478b00-dc25-11eb-99fc-274cc95e8e6d.png)

![image](https://user-images.githubusercontent.com/60011091/124354633-91ee9000-dc2a-11eb-8664-afa91e364279.png)

The above image shows the final SPICE DECK netlist.

These below images shows the ngspice window with timing analysis and commands to plot the required parameters.

![image](https://user-images.githubusercontent.com/60011091/124354730-0de8d800-dc2b-11eb-82ae-a155d0152ce6.png)

![image](https://user-images.githubusercontent.com/60011091/124354783-556f6400-dc2b-11eb-9ba0-dc4ed09e04c1.png)

This below image shows the waveform  in accordance with the SPICE Deck netlist

![image](https://user-images.githubusercontent.com/60011091/124354931-3de4ab00-dc2c-11eb-8f01-cda4c9d51d98.png)

These below images show the zoomed version of the waveform for rise_transition time

![image](https://user-images.githubusercontent.com/60011091/124355119-38d42b80-dc2d-11eb-9eb0-6d8ce9639b72.png)

![image](https://user-images.githubusercontent.com/60011091/124355125-425d9380-dc2d-11eb-9d79-42e2b7d57a99.png)

The below image shows the coordinates when expanded for rise_transition time along with calculation

![image](https://user-images.githubusercontent.com/60011091/124355357-4f2eb700-dc2e-11eb-988a-e78fc12006d7.png)

## Day-4 Pre-layout timing analysis and importance of good clock tree

### Labs to convert grid info to track info

The track info file

![image](https://user-images.githubusercontent.com/60011091/124356211-74bdbf80-dc32-11eb-888d-b4fb790e65d9.png)

Grid info to track info

    % grid 0.46um 0.34um 0.23um 0.17um      --based on the track info from sky130_fd_sc_hd library

![image](https://user-images.githubusercontent.com/60011091/124356679-d8e18300-dc34-11eb-9bf8-24f744b07eca.png)

![image](https://user-images.githubusercontent.com/60011091/124356702-075f5e00-dc35-11eb-90c2-e25413a144e6.png)

### Labs to convert magic layout to std cell LEF

As an example editing of input A layer is as shown below.

![image](https://user-images.githubusercontent.com/60011091/124357119-76d64d00-dc37-11eb-9817-311857ab7738.png)

Saving the layout according to user's way is as shown below in the below image

![image](https://user-images.githubusercontent.com/60011091/124357545-b56d0700-dc39-11eb-9eec-b7df6c389005.png)

Re-running magic to check whether the mag file was sucessfully saved and in working condition

![image](https://user-images.githubusercontent.com/60011091/124357628-32987c00-dc3a-11eb-80ce-ce5fdc50a2dc.png)

Creating lef file from magic layout created in previous image

       $ lef write

![image](https://user-images.githubusercontent.com/60011091/124357831-295bdf00-dc3b-11eb-8e31-e48349b89577.png)

        $ ls -ltr
        $ less sky130_vsdin.lef

![image](https://user-images.githubusercontent.com/60011091/124357793-fade0400-dc3a-11eb-8ff7-bd4b7b3769db.png)

These are the images for the contents in sky130_vsdin.lef

![image](https://user-images.githubusercontent.com/60011091/124357935-9a02fb80-dc3b-11eb-8b8a-b84ed74417ea.png)

![image](https://user-images.githubusercontent.com/60011091/124357958-b141e900-dc3b-11eb-8090-2af61066ae3b.png)

![image](https://user-images.githubusercontent.com/60011091/124357992-d3d40200-dc3b-11eb-88ac-6b14862b8c19.png)

### Lab for introduction to timing libs and steps to include new cell in synthesis

The below image shows the copying sky130_vsdin.lef into picorv32a design's src dirctory

![image](https://user-images.githubusercontent.com/60011091/124358541-6d9cae80-dc3e-11eb-9ea4-12b9e0bda780.png)

![image](https://user-images.githubusercontent.com/60011091/124358580-9755d580-dc3e-11eb-85e7-3868012343f3.png)

Contents in sky130_fd_sc_hd__typical.lib

![image](https://user-images.githubusercontent.com/60011091/124358671-f9aed600-dc3e-11eb-9131-298ca874a638.png)

![image](https://user-images.githubusercontent.com/60011091/124358683-06cbc500-dc3f-11eb-84e3-6ccab7ca8610.png)

![image](https://user-images.githubusercontent.com/60011091/124358693-10edc380-dc3f-11eb-9bd1-58be194791d7.png)

![image](https://user-images.githubusercontent.com/60011091/124358701-1d721c00-dc3f-11eb-9063-e2473139d225.png)

Contents in sky130_fd_sc_hd__slow.lib

![image](https://user-images.githubusercontent.com/60011091/124358749-53170500-dc3f-11eb-97b9-07a3a5086549.png)

![image](https://user-images.githubusercontent.com/60011091/124358760-60cc8a80-dc3f-11eb-9492-3d01f0cc6869.png)

![image](https://user-images.githubusercontent.com/60011091/124358769-6c1fb600-dc3f-11eb-9a4d-4b9c40691872.png)

![image](https://user-images.githubusercontent.com/60011091/124358780-75a91e00-dc3f-11eb-8b14-5e7818491343.png)

The below image shows the copying sky130_fd_sc_hd__* files into picorv32a design's src dirctory

![image](https://user-images.githubusercontent.com/60011091/124358876-f405c000-dc3f-11eb-9f1b-952a8841621c.png)

Here this image shows that sky130_fd_sc_hd__* files successfully copied into picorv32a design's src dirctory

![image](https://user-images.githubusercontent.com/60011091/124358895-04b63600-dc40-11eb-847c-51229c19db11.png)

Here is the screenshot of modified picorv32a config.tcl file which includes sky130_fd_sc_hd__* files and sky130_vsdin.lef

![image](https://user-images.githubusercontent.com/60011091/124359735-e18d8580-dc43-11eb-8167-8c56acba650b.png)

Now we are running the openlane flow from preparation till placement for picorv32a with sky130_fd_sc_hd__* files and sky130_vsdin.lef files

![image](https://user-images.githubusercontent.com/60011091/124362312-bf026900-dc51-11eb-9748-8c79d51d32b8.png)

Preparing the design

![image](https://user-images.githubusercontent.com/60011091/124362207-37b4f580-dc51-11eb-92e3-e8e0788e8b41.png)

![image](https://user-images.githubusercontent.com/60011091/124362253-79de3700-dc51-11eb-87bc-30b75fb584a3.png)

Setting and adding lef files

![image](https://user-images.githubusercontent.com/60011091/124370761-71f5b580-dc98-11eb-80c4-7440b39768f8.png)

Performing Synthesis

![image](https://user-images.githubusercontent.com/60011091/124362416-3c2dde00-dc52-11eb-8d06-245d83147990.png)

![image](https://user-images.githubusercontent.com/60011091/124370832-0233fa80-dc99-11eb-849b-6288f0294e3d.png)

### Configuring synthesis settings to fix Slack and include vsdinv

README.md file for applying synthesis strategy

![image](https://user-images.githubusercontent.com/60011091/124363161-4f8f7800-dc57-11eb-91f6-90fcba07b602.png)

Setting SYNTH_STRATEGY

![image](https://user-images.githubusercontent.com/60011091/124363182-7483eb00-dc57-11eb-84b7-cdadcff4f8d0.png)

When we set this value as 1 where the area would would increase but the delay will decrease significantly.

These are the Strategies to be set to reduce delay in the design as in the below images

![image](https://user-images.githubusercontent.com/60011091/124363548-751d8100-dc59-11eb-9305-6fd64261e7e1.png)

Changing synth.tcl and reducing tns and wns

![image](https://user-images.githubusercontent.com/60011091/124377712-f7925900-dcca-11eb-92ae-37c61b8e9a5e.png)

![image](https://user-images.githubusercontent.com/60011091/124377737-1d1f6280-dccb-11eb-8c2b-563d79adec89.png)

![image](https://user-images.githubusercontent.com/60011091/124377746-2f999c00-dccb-11eb-8514-5d1dd1a86078.png)

![image](https://user-images.githubusercontent.com/60011091/124377866-f281d980-dccb-11eb-9411-b929459be206.png)

### Power Aware CTS

Observations:

-2 levels of buffering.
-At every level, each node driving same load.
-Identical buffer at same level.

The example circuit is as shown below

![image](https://user-images.githubusercontent.com/60011091/124362791-cd9e4f80-dc54-11eb-801d-529677f5f7d0.png)

This image shows our assumptions for the above circuit
![image](https://user-images.githubusercontent.com/60011091/124362847-3d143f00-dc55-11eb-8f11-5c54562fbfa1.png)

Delay table example is as shown below

Delay table for CBUF 1

![image](https://user-images.githubusercontent.com/60011091/124362773-a9db0980-dc54-11eb-94ea-a332a25d0cbe.png)

Delay table for CBUF 2

![image](https://user-images.githubusercontent.com/60011091/124362807-e3ac1000-dc54-11eb-8b4f-da3a88a97fa9.png)

Based on assumption in the below image

![image](https://user-images.githubusercontent.com/60011091/124362847-3d143f00-dc55-11eb-8f11-5c54562fbfa1.png)

We round the values meeting 60ff at node A for CBUF 1

![image](https://user-images.githubusercontent.com/60011091/124362874-7b116300-dc55-11eb-9357-b2636c81a592.png)

We round the values meeting 50ff at node B for CBUF 2

![image](https://user-images.githubusercontent.com/60011091/124362928-d2173800-dc55-11eb-913d-cdc62baa8f7c.png)

We round the values meeting 50ff at node B for CBUF 2 for a different input condition

![image](https://user-images.githubusercontent.com/60011091/124362939-f115ca00-dc55-11eb-844c-31d2908cb0f6.png)

### Setup Timing Analysis

Specifications:

Clock Frequency(F)= 1GHZ
Clock Period(T)= 1/F
               =1/1GHZ
               =1ns

![image](https://user-images.githubusercontent.com/60011091/124371990-aa02f580-dca4-11eb-84ff-2709db099a0d.png)

The setup timing analysis says that if for this particular circuit to work, the combination delay (θ) ie internal delay of the launch flop and the combinational delay in the above circuit must be less than the time period given in the specifications.

    θ < T

For the capture flop to settle with the received data we have to tweak  θ < T so, the condition will look like

    θ < (T-S)
    where S is the setup time of Capture Flipflop

### Clock Jitter and uncertainty

Clock Jitter: temporary variation of clock period.

For modeling this jitter we take one more parameter called uncertainty

After we introduce this concept,  θ < (T-S) is again changed based on setup uncertainty(SU) so the condition becomes

     θ < (T-S-SU)

 ### Clock tree Routing (H Tree Algorithm)

 H Tree Algorithm takes a particular clock route and it claculates the distance from a particular point to all its end points and tries to comment on the midpoint and builds a tree from that midpoint.

### Lab for Floorplanning and Placement

Performing initial floorplan

    % init_floorplan

![image](https://user-images.githubusercontent.com/60011091/124375101-ec84fc00-dcbd-11eb-9213-f4c97d8c44c8.png)

IO placement

    % place_io

![image](https://user-images.githubusercontent.com/60011091/124375247-e5aab900-dcbe-11eb-9674-b277286d70b7.png)

Running placement on processed Design

    % global_placement_or

![image](https://user-images.githubusercontent.com/60011091/124375737-5b178900-dcc1-11eb-804e-bf4df3b1850f.png)

Improved Slack after running placement on processed Design
![image](https://user-images.githubusercontent.com/60011091/124378130-6f618300-dccd-11eb-9d59-3973d1a1729d.png)

Running placement using RePlace

     % global_placement

![image](https://user-images.githubusercontent.com/60011091/124376081-dded1380-dcc2-11eb-805a-79a9ef8db1b2.png)

![image](https://user-images.githubusercontent.com/60011091/124376125-10970c00-dcc3-11eb-95e3-9143bc0fb708.png)

Tap decap using OpenRoad app

      % tap_decap_or

![image](https://user-images.githubusercontent.com/60011091/124376160-3d4b2380-dcc3-11eb-947d-a91064d04110.png)

Detailed placement using OpenRoad app

      % detailed_placement_or

![image](https://user-images.githubusercontent.com/60011091/124376230-931fcb80-dcc3-11eb-92c3-f1b54eb30952.png)

Detailed placement using OpenDP

      % detailed_placement

![image](https://user-images.githubusercontent.com/60011091/124376840-79cc4e80-dcc6-11eb-90a0-480344b8950a.png)

![image](https://user-images.githubusercontent.com/60011091/124377099-de3bdd80-dcc7-11eb-83ed-d7f67cb8f630.png)

![image](https://user-images.githubusercontent.com/60011091/124378170-acc61080-dccd-11eb-9463-b33550a9030f.png)

Detailed placement after Tap_decap

    % detailed_placement

![image](https://user-images.githubusercontent.com/60011091/124378238-062e3f80-dcce-11eb-9c0e-4ebb757bd42b.png)

![image](https://user-images.githubusercontent.com/60011091/124378247-11816b00-dcce-11eb-9863-5d2a47e03307.png)

Layout of Detailed placement after Tap_decap

![image](https://user-images.githubusercontent.com/60011091/124381864-3c75ba00-dce2-11eb-9c6f-87014cffdb16.png)

![image](https://user-images.githubusercontent.com/60011091/124381911-7a72de00-dce2-11eb-8b67-e24a82696703.png)

## Day-5 Final steps for RTL2GDS

### Lab for Power Distribution Network Routing DRC Check and SPEF Extraction

#### PDN Generation

    % gen_pdn

![image](https://user-images.githubusercontent.com/60011091/124378326-5ad1ba80-dcce-11eb-9a2c-87d2c2b3ae39.png)

![image](https://user-images.githubusercontent.com/60011091/124378337-67561300-dcce-11eb-8a07-caa6efe97ce2.png)

![image](https://user-images.githubusercontent.com/60011091/124378345-75a42f00-dcce-11eb-9cca-6ffd8840cc60.png)

#### Running Routing

    % run_routing

![image](https://user-images.githubusercontent.com/60011091/124382057-1997d580-dce3-11eb-8997-d61c22151ff5.png)

![image](https://user-images.githubusercontent.com/60011091/124382086-30d6c300-dce3-11eb-8e02-6b507bd76371.png)

![image](https://user-images.githubusercontent.com/60011091/124382195-d2f6ab00-dce3-11eb-96ba-5c0c37f7375e.png)

![image](https://user-images.githubusercontent.com/60011091/124382207-e0ac3080-dce3-11eb-96e4-09c2a9b55c8e.png)

![image](https://user-images.githubusercontent.com/60011091/124382222-edc91f80-dce3-11eb-8cbf-dd4af88a1284.png)

Some images from Detailed Routing iteration

![image](https://user-images.githubusercontent.com/60011091/124382255-105b3880-dce4-11eb-8e64-bf091feeb6aa.png)

Here in the below image  we can see a significant reduction in violations compared to previous image.

![image](https://user-images.githubusercontent.com/60011091/124382308-587a5b00-dce4-11eb-907e-684319eeba55.png)

In the below image by 41 st iteration all the violations are resolved

![image](https://user-images.githubusercontent.com/60011091/124382385-cc1c6800-dce4-11eb-9e77-735366d8dc64.png)

The below image shows the last iteration for detailed routing ie 57th iterations

![image](https://user-images.githubusercontent.com/60011091/124382407-e5251900-dce4-11eb-8e87-d71aef0c9c51.png)

Final total wire lengths after detailed routing

![image](https://user-images.githubusercontent.com/60011091/124382441-0d147c80-dce5-11eb-8222-caec3ad6d77d.png)

![image](https://user-images.githubusercontent.com/60011091/124382459-2c130e80-dce5-11eb-8d3c-d1aa3a1e696d.png)

#### Checking DRC Violations and SPEF Extraction

![image](https://user-images.githubusercontent.com/60011091/124382488-59f85300-dce5-11eb-814d-18c49a98ea0a.png)

Layout of Routing

     $ magic -T /home/john/Desktop/work/tools/openlane_working_dir/pdks/sky130libs.tech lef read ../../tmp/merged.lef def read picorv32a.def

![image](https://user-images.githubusercontent.com/60011091/124382680-400b4000-dce6-11eb-8e6a-cf833bfe8f23.png)

![image](https://user-images.githubusercontent.com/60011091/124382695-50bbb600-dce6-11eb-9f2a-b07c58766beb.png)

![image](https://user-images.githubusercontent.com/60011091/124382711-78ab1980-dce6-11eb-9f89-59f2c9ca5acc.png)

#### Magic commands

-Running magic command

     % run_magic

   ![image](https://user-images.githubusercontent.com/60011091/124379944-aa68b400-dcd7-11eb-91c1-529e2909fbc3.png)

![image](https://user-images.githubusercontent.com/60011091/124379952-bfddde00-dcd7-11eb-9310-6131c372e89f.png)

-Magic DRC Check

     % run_magic_drc

![image](https://user-images.githubusercontent.com/60011091/124380371-f4529980-dcd9-11eb-8a0f-12035fe271c3.png)

![image](https://user-images.githubusercontent.com/60011091/124380388-03d1e280-dcda-11eb-92ad-87dd82c7857b.png)

-MAGIC SPICE EXPORT

    % run_magic_spice_export

![image](https://user-images.githubusercontent.com/60011091/124380618-3fb97780-dcdb-11eb-9fcc-71eb988a8ae1.png)

![image](https://user-images.githubusercontent.com/60011091/124380629-4b0ca300-dcdb-11eb-90c7-51e3ac292fd0.png)

 -MAGIC Antenna Check

     % run_magic_antenna_check

 ![image](https://user-images.githubusercontent.com/60011091/124380665-8b6c2100-dcdb-11eb-8332-edd64c95e6e8.png)

![image](https://user-images.githubusercontent.com/60011091/124380673-96bf4c80-dcdb-11eb-8461-bd30b84438ae.png)

So by this we come to the end of day five where I've understand the Openlane flow, various commands in the flow, how to add a customized standard cell design to already existing picorv32a design and performing the Openlane flow using this cell's lib files and lef files and understanding the challenges in using an external cell design and ways to solve the issues with the customized cell design and finally we extracted layouts for each of the process in OpenLane flow.

## Acknowledgements

1. Kunal Ghosh - Co-founder(VSD Corp. Pvt. Ltd)
2. Nickson Jose - VSD Teaching Assistant
3. Mili Anand  - VSD Teaching Assistant
4. Mansi Mohapatra  - VSD Teaching Assistant


text:
# DustPress Starter Theme

A basic and very bare theme that you can build your own theme from. There isn't really any layout or content but file structure and examples of classes to start with.

## Install

The theme itself would be installed just like any other. Download the contents of this repository to your wp-content/themes directory.

Add DustPress in the mix by requiring it via `composer` and using Composer's autoloading feature or simply clone its [repository](https://github.com/devgeniem/dustpress) to your preferred destination and require the `dustpress.php` file in the beginning of the `functions.php` of the theme.

Then just activate the theme from the WordPress admin panel, and you are good to go!

## How to continue?

Further instructions on how to develop with DustPress can be found at the [readme file](https://github.com/devgeniem/dustpress/blob/master/README.md) of the main project.

## Contributors

- [devgeniem](https://github.com/devgeniem)
- [Nomafin](https://github.com/Nomafin)
- [villesiltala](https://github.com/villesiltala)

license: MIT

repository: MarikaKononen/CodeForMyLife

branch_name: refs/heads/master

extension: md

gha_language: PHP

gha_license_id: MIT

license_type: permissive

repo_name: MarikaKononen/CodeForMyLife


text:
# Minesweeper
Built with [Gatsby](https://www.gatsbyjs.org/).

## Install

Install Gatsby CLI:
```sh
npm install --global gatsby-cli
```

Develop (unminified @ localhost:8000):
```sh
gatsby develop
```

Build (minified @ localhost:9000):
```sh
gatsby build && gatsby serve
```

repository: leyanlo/minesweeper

repo_name: leyanlo/minesweeper


text:
## AWS Modernization Workshop Samples

** DO NOT ** start with this repo for your workshop base. Clone repo https://github.com/aws-samples/aws-modernization-workshop-base as a starting point.

This repo contains samples that can be used as building blocks for workshop creation.  For instructions on how to build a workshop please see https://aws-samples.github.io/aws-modernization-workshop-sample/

gha_language: JavaScript


text:
# Contributing

Contributions are **welcome** and will be fully **credited**.

We accept contributions via Pull Requests on [Github](https://github.com/victoravelar/mollie-api-go).

## Before starting to code

If you are contributing based on an issue, please drop a comment in the issue so that it can be labeled as `in progress` and assigned to you, this provides everyone visiting the repository with a clear overview of what is up for grabs and what is already taken.

Also be sure to ask and clarify all your questions so that your coding experience is as smooth as possible.

If your PR is not based on an issue, then please provide a relevant and descriptive PR description and branch name.

## Pull Requests

- **Passes code style checks from scrutinizer**

- **Add tests!** - Your code won't be accepted if it doesn't have tests.

- **Document any change in behaviour** - Make sure the `README.md` and any other relevant documentation are kept up-to-date.

- **Create feature branches** - Don't ask us to pull from your master branch.

- **One pull request per feature** - If you want to do more than one thing, send multiple pull requests.

- **Send coherent history** - Make sure each individual commit in your pull request is meaningful. If you had to make multiple intermediate commits while developing, please [squash them](http://www.git-scm.com/book/en/v2/Git-Tools-Rewriting-History#Changing-Multiple-Commit-Messages) before submitting.

## Running Tests

``` bash
$ go test -v -race ./...
```

**Happy coding**!

repository: VictorAvelar/mollie-api-go

gha_language: Go

repo_name: VictorAvelar/mollie-api-go


text:
# Rothko

A simple game engine written from scratch.
This project is for now a learning experience, though I have used it already for
some minor projects.

The phylosophy of Rothko is "EaaL": Engine as a Library. The whole logic of the
game is your own and Rothko only provides common functionality.

## Tasks

- Cross-Platform
  - [x] Windows (MSVC)
  - [x] Linux (clang)
  - [x] MacOS (clang, compiled outside XCode)
  - [ ] Android
  - [ ] iPhone
  - [ ] Fuchsia
- Graphics
  - [x] Graphics Agnostic API (Can be implemented by different graphics APIs).
  - [x] OpenGL backend
  - [ ] Vulkan Backend
    - (~20%)I've done some work on this. It works for rendering a static scene but haven't
      done pipeline switch, so it's stuck to a hardcoded shader.
  - [ ] PBR
  - [ ] Shadows
- Window
  - [x] Window Agnositc API
  - [x] SDL integration
- GUI
  - [x] Imgui integration
  - [ ] In game gui
- Assets
  - [ ] GLTF
    - This is ~50% done. Can load models, but there is no material handling yet.
  - [ ] Animations
- Misc
  - [x] C++17
  - [x] Math library
  - [x] Logging (multi-threaded)
  - [x] Scene Graph
  - [x] Debug Widgets (cubes, lines, etc.).
  - [x] Camera support (perspective, rothko, movement, etc.).
  - [ ] Multithreaded Tasks
  - [ ] Memory Management
  - [ ] Containers
- Examples
  - [x] Debug Widgets
  - [x] Scene Graph
  - [x] Simple Lighting
  - [ ] Textured Lighting
  - [ ] Gameboy Emulator
    - On hold because it doesn't really exercide a 3D engine.

## Building

Rothko uses the [GN build system](https://gn.googlesource.com/gn/),
which is used for Chrome and Fuchsia.
Overall the process is pretty simple.

The first time,
```
gn gen out
gn args out
```

In that file, we need to tell GN what dependencies to use for graphics and windows.
```
opengl_enabled = true

// paths are relative to rothko. This is very annoying, yes.
// I have a TODO to make it absolute.
sdl_enabled = true
sdl_include_path = "../../../../../include"
sdl_lib_path = "../../../../../source/SDL2-2.0.10/build/Debug/SDL2d.lib"
```

Finally to compile.
```
ninja -C out
```

On windows, you need to have cl.exe and other tools in the PATH.
The easiest way to do this is to source this script (your actual path depends
on where the Visual Studio installation is):

```
C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Auxiliary\Build\vcvars64.bat
```

## Screenshots

A simple lighting experiment
![Simple Lighting](/images/simple_lighting.png)

Some advance on the Gameboy Emulator (on hold right now)
![Emulator](/images/emulator.png)

## About YCM

I use YCM extensively, but every machine has it's own flags that differ a lot,
specially in cross-platform development. For this, I have modified the
`.ycm_extra_conf.py` YCM file to try to import a python file called
`ycm_extra_conf_local.py`. This file should implement a function called
`GetYCMLocalFlags` that should return a python array with the flags YCM style:

```
local_flags = [
  "-I", "/some/path/to/includes",
  "-isystem", "/other/path/to/system/includes",
]

def GetYCMLocalFlags():
  return local_flags
```

This file is not tracked in versioning, so you must provide your own.

repository: cristiandonosoc/rothko

gha_license_id: NOASSERTION

repo_name: cristiandonosoc/rothko


text:
# spawn
--
    import "github.com/miketheprogrammer/go-thrust/spawn"

## Usage

#### func  Bootstrap

```go
func Bootstrap()
```
SetThrustApplicationTitle sets the title in the Info.plist. This method only
exists on Darwin.

#### func  GetAppDirectory

```go
func GetAppDirectory() string
```

#### func  GetDownloadUrl

```go
func GetDownloadUrl() string
```
GetDownloadUrl returns the interpolatable version of the Thrust download url
Differs between builds based on OS

#### func  GetExecutablePath

```go
func GetExecutablePath() string
```
GetExecutablePath returns the path to the Thrust Executable Differs between
builds based on OS

#### func  GetThrustDirectory

```go
func GetThrustDirectory() string
```
GetThrustDirectory returns the Directory where the unzipped thrust contents are.
Differs between builds based on OS

#### func  Run

```go
func Run(autoDownloadEnabled bool) (io.ReadCloser, io.WriteCloser)
```
The SpawnThrustCore method is a bootstrap and run method. It will try to detect
an installation of thrust, if it cannot find it it will download the version of
Thrust detailed in the "common" package. Once downloaded, it will launch a
process. Go-Thrust and all *-Thrust packages communicate with Thrust Core via
Stdin/Stdout. using -log=debug as a command switch will give you the most
information about what is going on. -log=info will give you notices that stuff
is happening. Any log level higher than that will output nothing.

#### func  SetBaseDirectory

```go
func SetBaseDirectory(dir string) error
```
SetBaseDirectory sets the base directory used in the other helper methods

repository: gitter-badger/go-thrust

repo_name: gitter-badger/go-thrust


text:
# controller
```java
@GetMapping("/api/v3.1/orders")
public List<SimpleOrderDto> ordersv3_1(
        @RequestParam(value = "offset", defaultValue = "0") int offset,
        @RequestParam(value = "limit", defaultValue = "100") int limit
        ){
    List<Order> orders = orderRepository.findAllWithMemberDelivery(offset, limit);

    List<SimpleOrderDto> orderDtos = orders.stream()
            .map(order -> new SimpleOrderDto(order))
            .collect(Collectors.toList());

    return orderDtos;
}
```

# findAllWithMemberDelivery
```java
public List<Order> findAllWithMemberDelivery(int offset, int limit) {
    return em.createQuery(
            "select o from Order o" +
                    " join fetch o.member m" +
                    " join fetch o.delivery d", Order.class
    )
            .setFirstResult(offset)
            .setMaxResults(limit)
            .getResultList();

}
```

# 요청결과
![](../imgs/주문조회페이징.png)

# 요청쿼리
```jql
select order0_.order_id as order_id1_6_0_, member1_.member_id as member_i1_4_1_, delivery2_.delivery_id as delivery1_2_2_, order0_.delivery_id as delivery4_6_0_, order0_.member_id as member_i5_6_0_, order0_.order_date as order_da2_6_0_, order0_.status as status3_6_0_, member1_.city as city2_4_1_, member1_.street as street3_4_1_, member1_.zipcode as zipcode4_4_1_, member1_.name as name5_4_1_, delivery2_.city as city2_2_2_, delivery2_.street as street3_2_2_, delivery2_.zipcode as zipcode4_2_2_, delivery2_.status as status5_2_2_
from orders order0_
inner join member member1_
    on order0_.member_id=member1_.member_id
inner join delivery delivery2_
    on order0_.delivery_id=delivery2_.delivery_id limit 2;
```


text:
[![Build Status](https://dev.azure.com/chefcorp-partnerengineering/Chef%20Base%20Plans/_apis/build/status/chef-base-plans.gecode?branchName=master)](https://dev.azure.com/chefcorp-partnerengineering/Chef%20Base%20Plans/_build/latest?definitionId=211&branchName=master)

# gecode

gecode is an open source C++ toolkit for developing constraint-based systems and applications. Gecode provides a constraint solver with state-of-the-art performance while being modular and extensible.  See [documentation](https://www.gecode.org/documentation.html)

## Maintainers

* The Core Planners<EMAIL_ADDRESS>
## Type of Package

Binary package

### Use as Dependency

Library packages can be set as runtime or build time dependencies, however they are typically used as buildtime dependencies. See [Defining your dependencies](https://www.habitat.sh/docs/developing-packages/developing-packages/#sts=Define%20Your%20Dependencies) for more information.

To add core/gecode as a dependency, you can add one of the following to your plan file.

#### Buildtime Dependency

> pkg_build_deps=(core/gecode)

#### Runtime dependency

> pkg_deps=(core/gecode)

### Use as a Library

#### Installation

To install this plan, run the following command:

``hab pkg install core/gecode``

```bash
hab pkg install core/gecode
» Installing core/gecode
☁ Determining latest version of core/gecode in the 'stable' channel
☛ Verifying core/gecode/3.7.3/20200403223326
→ Using core/gcc-libs/9.1.0/20200305225533
→ Using core/glibc/2.29/20200305172459
→ Using core/linux-headers/4.19.62/20200305172241
→ Using core/zlib/1.2.11/20200305174519
✓ Installed core/gecode/3.7.3/20200403223326
★ Install of core/gecode/3.7.3/20200403223326 complete with 1 new packages installed.
```

#### Viewing library files

To view the library files first get the habitat installation directory

```bash
hab pkg path core/gecode
/hab/pkgs/core/gecode/3.7.3/20200403223326
```

Then list the libraries, for example:

```bash
ls -1 $(hab pkg path core/gecode)
[4][default:/src/gecode:0]# ls -1 $(hab pkg path core/gecode)
...
...
bin
include
lib
share
```

repository: habitat-sh/core-plans

branch_name: refs/heads/main

gha_language: Shell

repo_name: habitat-sh/core-plans


text:
## WhatsApp export processor.

Use this to convert your raw WhatsApp coversation exports into structured json. This works for conversations exported to Google Drive. Use this for:

1. [Fleeing WhatsApp for Telegram / Signal](https://arstechnica.com/tech-policy/2021/01/whatsapp-users-must-share-their-data-with-facebook-or-stop-using-the-app/)
2. Archiving WhatsApp conversations
3. Misinformation research (what this was originally designed for)

#### Extra features:
- **Obfuscation**: If using for research, an --obfuscation-key parameter is available to remove personally identifiable information (PII) from the conversation. So names, phone numbers, and group names will be obfuscated.
- **Smart multiple export merges**: Export to the same folder twice without getting duplicate messages

## Usage

### To export your chats

1. Click the top right dot menu of your WhatsApp conversation.
2. Go to More -> Export chat
3. Choose either with or without media
4. Choose the "Drive: Save to Drive" option.
5. IMPORTANT: Move your export to a google drive folder

### Installation

Download this repo and then run

    pip3 install -r requirements.txt

### Authentication

There are two options for authentication. Both generate a json file which needs to be passed in:
1.
2. Service account option:
    Create a service account here:
    https://console.developers.google.com/iam-admin/serviceaccounts
    After creating, click "create key" on the tab to right and download.
    IMPORTANT: You will then need to share the drive directory with the service account email.

### Basic script usage

    ./whatsapp_processor.py path/to/creds.json drive.google.com/folders/drive_id mdy --verbose

For help on the CLI arguments, try `./whatsapp_processor.py --help`

## Acknowledgements

This was adapted from code I wrote for [Tattle](https://tattle.co.in/). Tattle is a civic tech project that builds tools and datasets to better understand and respond to (mis)information trends in India. The original code can be found [here](https://github.com/tattle-made/whatsapp-scraper/tree/master/python_scraper).

## License

[MIT License](https://opensource.org/licenses/MIT)

## Testing

    ./test.sh

The test.sh file uses the coverage python module. You can see the code coverage with

    firefox htmlcov/index.html


text:
## Dependencies

This project requires:

1. C++17 or newer
2. Boost >= 1.72
3. CMake >= 3.12
4. NCurses (only tested with 6.1)
5. nlohmann_json >= 3.2.0

## Building with CMake

1. Create a new directory for building.

        mkdir build

2. Change into the new directory.

        cd build

3. Run CMake with the path to the source.

        cmake ../Social Gaming/

4. Run make inside the build directory:

        make

## Running the Chat Server

5. Run the chat server

    bin/chatserver 4000 ../Social Gaming/webchat.html

## Visiting the Chat Server

6. Visit the chat server by visiting the following link in a web browser

	http://localhost:4000/index.html

6.5 It is also possible to visit the chat client by running

    bin/chatclient localhost 4000