text:
.52" size="1.778" layer="95"/>
<wire x1="241.3" y1="96.52" x2="254" y2="96.52" width="0.1524" layer="91"/>
<wire x1="215.9" y1="81.28" x2="241.3" y2="81.28" width="0.1524" layer="91"/>
<label x="220.98" y="81.28" size="1.778" layer="95"/>
<label x="220.98" y="71.12" size="1.778" layer="95"/>
<wire x1="215.9" y1="71.12" x2="241.3" y2="71.12" width="0.1524" layer="91"/>
<wire x1="241.3" y1="71.12" x2="241.3" y2="81.28" width="0.1524" layer="91"/>
<wire x1="241.3" y1="81.28" x2="241.3" y2="96.52" width="0.1524" layer="91"/>
<junction x="241.3" y="81.28"/>
<junction x="241.3" y="96.52"/>
<pinref part="U4" gate="G$1" pin="RL"/>
<pinref part="U4" gate="G$1" pin="VCC"/>
<pinref part="U4" gate="G$1" pin="VLOGIC"/>
<pinref part="C4" gate="G$1" pin="1"/>
<pinref part="P+2" gate="VCC" pin="VCC"/>
</segment>
</net>
<net name="SPI_CS" class="0">
<segment>
<wire x1="132.08" y1="162.56" x2="147.32" y2="162.56" width="0.1524" layer="91"/>
<label x="134.62" y="162.56" size="1.778" layer="95"/>
<pinref part="U1" gate="G$1" pin="CS"/>
</segment>
<segment>
<wire x1="132.08" y1="99.06" x2="147.32" y2="99.06" width="0.1524" layer="91"/>
<label x="134.62" y="99.06" size="1.778" layer="95"/>
<pinref part="U3" gate="G$1" pin="CS"/>
</segment>
<segment>
<wire x1="215.9" y1="165.1" x2="233.68" y2="165.1" width="0.1524" layer="91"/>
<label x="220.98" y="165.1" size="1.778" layer="95"/>
<pinref part="U2" gate="G$1" pin="CS"/>
</segment>
<segment>
<wire x1="215.9" y1="101.6" x2="233.68" y2="101.6" width="0.1524" layer="91"/>
<label x="220.98" y="101.6" size="1.778" layer="95"/>
<pinref part="U4" gate="G$1" pin="CS"/>
</segment>
</net>
<net name="DCP_RW3" class="0">
<segment>
<wire x1="215.9" y1="154.94" x2="233.68" y2="154.94" width="0.1524" layer="91"/>
<label x="220.98" y="154.94" size="1.778" layer="95"/>
<pinref part="U2" gate="G$1" pin="RW"/>
</segment>
</net>
<net name="DCP_RW4" class="0">
<segment>
<wire x1="215.9" y1="91.44" x2="233.68" y2="91.44" width="0.1524" layer="91"/>
<label x="220.98" y="91.44" size="1.778" layer="95"/>
<pinref part="U4" gate="G$1" pin="RW"/>
</segment>
</net>
<net name="DCP_RW1" class="0">
<segment>
<pinref part="U1" gate="G$1" pin="RW"/>
<wire x1="132.08" y1="152.4" x2="147.32" y2="152.4" width="0.1524" layer="91"/>
<label x="134.62" y="152.4" size="1.778" layer="95"/>
</segment>
</net>
<net name="DCP_RW2" class="0">
<segment>
<pinref part="U3" gate="G$1" pin="RW"/>
<wire x1="132.08" y1="88.9" x2="147.32" y2="88.9" width="0.1524" layer="91"/>
<label x="134.62" y="88.9" size="1.778" layer="95"/>
</segment>
</net>
</nets>
</sheet>
</sheets>
</module>
</modules>
<parts>
<part name="FRAME2" library="frames" library_urn="urn:adsk.eagle:library:229" deviceset="A3L-LOC" device=""/>
<part name="GND3" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
<part name="GND10" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
<part name="GND12" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
<part name="GND7" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
<part name="S1" library="CHS_SWITCH" deviceset="CHS-02_SWITCH" device=""/>
<part name="GND4" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
<part name="GND14" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
<part name="GND13" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
<part name="GND11" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
<part name="GND5" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
<part name="J1" library="SparkFun-Connectors" deviceset="JST_2MM_MALE" device=""/>
<part name="GND1" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
<part name="FRAME1" library="frames" library_urn="urn:adsk.eagle:library:229" deviceset="A3L-LOC" device=""/>
<part name="TABLE1" library="Table" deviceset="TABLE_REVISIONS" device=""/>
<part name="J4" library="DF40FC-20DP-0.4V(51)" deviceset="DF40FC-20DP-0.4V(51)" device=""/>
<part name="J2" library="SparkX" deviceset="I2C_STANDARD" device="JS-1MM" value="QIIC connector"/>
<part name="GND9" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
<part name="GND2" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
<part name="GND6" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
<part name="J3" library="SparkX" deviceset="I2C_STANDARD" device="JS-1MM" value="QIIC connector"/>
<part name="GND8" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
<part name="S2" library="CHS_SWITCH" deviceset="CHS-02_SWITCH" device=""/>
<part name="GND17" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
<part name="S3" library="EVPAYG0BA" deviceset="EVPAYG0BA" device="EVPAYG0BA"/>
<part name="GND15" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
<part name="GND16" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
<part name="J5" library="FTSH-105-01-XXX-DV-K" deviceset="FTSH-105-01-XXX-DV-K" device=""/>
</parts>
<sheets>
<sheet>
<plain>
<text x="147.32" y="208.28" size="25.4" layer="97">Warp</text>
<text x="20.32" y="144.78" size="1.778" layer="97">C</text>
<text x="63.5" y="111.76" size="1.778" layer="97">Lower loss caps added</text>
<text x="63.5" y="114.3" size="1.778" layer="97">CPX3225A752D supercaps added</text>
<text x="63.5" y="109.22" size="1.778" layer="97">Resistor settings changed for correct charging of supercaps</text>
<text x="63.5" y="106.68" size="1.778" layer="97">AT45DB321F flash chip added</text>
<text x="63.5" y="101.6" size="1.778" layer="97">ADC input replaced by GPIO</text>
<text x="63.5" y="99.06" size="1.778" layer="97">TPS62172 programmable step-down regulator added</text>
<text x="63.5" y="144.78" size="1.778" layer="97">Split i2c buses for sensors</text>
<text x="63.5" y="142.24" size="1.778" layer="97">Mechanical switches changed for power control</text>
<text x="30.48" y="114.3" size="1.778" layer="97">BOOST</text>
<text x="30.48" y="101.6" size="1.778" layer="97">MCU</text>
<text x="30.48" y="144.78" size="1.778" layer="97">TOP LEVEL</text>
<text x="63.5" y="96.52" size="1.778" layer="97">DF40 header pin assignments changed</text>
<text x="63.5" y="134.62" size="1.778" layer="97">Some lines removed from the DF40 header</text>
<text x="30.48" y="137.16" size="1.778" layer="97">FT4222</text>
<text x="63.5" y="137.16" size="1.778" layer="97">GPIO lines now powered by external regulator</text>
<text x="30.48" y="132.08" size="1.778" layer="97">FPGA</text>
<text x="63.5" y="129.54" size="1.778" layer="97">TPS62746DSBGA 1.2 V switching regulator added</text>
<text x="63.5" y="127" size="1.778" layer="97">Two i2c lines added</text>
<text x="63.5" y="132.08" size="1.778" layer="97">Changed to WLP package</text>
<text x="30.48" y="124.46" size="1.778" layer="97">RTC</text>
<text x="63.5" y="124.46" size="1.778" layer="97">RV-8803-C7 RTC IC and coin cell (SR416SW) backup added</text>
<text x="30.48" y="121.92" size="1.778" layer="97">CHARGER</text>
<text x="63.5" y="121.92" size="1.778" layer="97">BQ24230 battery charger IC added for LiPo battery</text>
<text x="293.624" y="18.796" size="2.54" layer="94" ratio="15">Warp revision C</text>
<text x="293.624" y="11.176" size="1.778" layer="94">Authored 2015-2019
Phillip Stanley-Marbell
Richard Hopper</text>
<text x="293.624" y="6.096" size="1.778" layer="94">NO WARRANTY. See LICENCE.txt</text>
<text x="344.17" y="20.066" size="2.54" layer="94" ratio="15">Title page</text>
<text x="30.48" y="99.06" size="1.778" layer="97">REG</text>
<text x="63.5" y="119.38" size="1.778" layer="97">Update LPS25H footprint</text>
<text x="63.5" y="104.14" size="1.778" layer="97">EN pin of the BQ25570 can be set</text>
<text x="63.5" y="116.84" size="1.778" layer="97">DCPs moved to secondary power supply</text>
<text x="63.5" y="139.7" size="1.778" layer="97">Primary and secondary supply rails (VS1, VS2)</text>
<text x="63.5" y="93.98" size="1.778" layer="97">PV cell wired to header and JST socket</text>
<text x="30.48" y="119.38" size="1.778" layer="97">SENSORS-2</text>
<text x="30.48" y="96.52" size="1.778" layer="97">IO</text>
<text x="30.48" y="134.62" size="1.778" layer="97">RF</text>
<text x="50.8" y="144.78" size="1.778" layer="97">19/7/19</text>
<text x="304.8" y="101.6" size="5.08" layer="97">Layer stack up:</text>
<text x="304.8" y="96.52" size="2.54" layer="97">1: Signal</text>
<text x="304.8" y="91.44" size="2.54" layer="97">2: GND</text>
<text x="304.8" y="86.36" size="2.54" layer="97">3: GND</text>
<text x="304.8" y="60.96" size="2.54" layer="97">14: VS2</text>
<text x="304.8" y="55.88" size="2.54" layer="97">15: GND</text>
<text x="304.8" y="50.8" size="2.54" layer="97">16: Signal</text>
<text x="304.8" y="81.28" size="2.54" layer="97">4: Signal</text>
<text x="304.8" y="76.2" size="2.54" layer="97">5: VS1</text>
<text x="304.8" y="71.12" size="2.54" layer="97">6: GND</text>
<text x="304.8" y="66.04" size="2.54" layer="97">7: Signal</text>
<text x="30.48" y="85.09" size="1.778" layer="97">FT4222</text>
<text x="63.5" y="91.44" size="1.778" layer="97">Switch added to break supply (for power save mode)</text>
<text x="50.8" y="88.138" size="1.778" layer="97">19/9/19</text>
<text x="63.246" y="63.754" size="1.778" layer="97">Consolidated breakout boards
Removed FT4222 USB interface
FPGA driven using LDO
Changed Bluetooth module to BGX13S
Added digipots for each sensor i2c bus
Added QIIC connects for each i2c bus
Added ideal diodes to protect regulator from QIIC supply voltage
Removed one DF40 header
Removed RTC battery
Removed Grideye sensor </text>
<text x="30.48" y="63.5" size="1.778" layer="97">SENSORS</text>
<text x="30.226" y="82.296" size="1.778" layer="97">FPGA</text>
<text x="30.226" y="79.756" size="1.778" layer="97">BLUETHOOTH</text>
<text x="30.226" y="77.216" size="1.778" layer="97">DIGIPOT</text>
<text x="30.226" y="74.168" size="1.778" layer="97">MAIN</text>
<text x="30.48" y="66.04" size="1.778" layer="97">RTC</text>
<text x="30.48" y="87.63" size="1.778" layer="97">BOARD</text>
<text x="30.48" y="60.96" size="1.778" layer="97">USB</text>
<text x="50.038" y="60.96" size="1.778" layer="97">7/10/19</text>
<text x="62.992" y="60.96" size="1.778" layer="97">Swapped micro USB part </text>
<text x="30.48" y="58.42" size="1.778" layer="97">FPGA</text>
<text x="50.038" y="58.42" size="1.778" layer="97">8/11/19</text>
<text x="62.992" y="58.166" size="1.778" layer="97">Removed microvias and rerouted FPGA</text>
<text x="30.48" y="55.88" size="1.778" layer="97">TOP LEVEL</text>
<text x="50.038" y="55.88" size="1.778" layer="97">13/11/19</text>
<text x="62.992" y="55.626" size="1.778" layer="97">Brought reset switch out to main sheet</text>
<text x="30.48" y="53.34" size="1.778" layer="97">REG</text>
<text x="62.992" y="53.086" size="1.778" layer="97">Ideal dioides placed in module</text>
<text x="30.48" y="50.8" size="1.778" layer="97">SENSOR</text>
<text x="62.738" y="50.546" size="1.778" layer="97">Replaced MAG3110 (obsolete) with FXOS8700CQ</text>
<text x="50.038" y="50.8" size="1.778" layer="97">14/11/19</text>
<text x="50.038" y="48.26" size="1.778" layer="97">15/01/19</text>
<text x="62.738" y="48.006" size="1.778" layer="97">Corrected SPI lines from MCU</text>
<text x="30.48" y="48.26" size="1.778" layer="97">MCU</text>
</plain>
<instances>
<instance part="FRAME1" gate="G$1" x="0" y="0" smashed="yes">
<attribute name="DRAWING_NAME" x="344.17" y="15.24" size="2.54" layer="94"/>
<attribute name="LAST_DATE_TIME" x="344.17" y="10.16" size="2.286" layer="94"/>
<attribute name="SHEET" x="357.505" y="5.08" size="2.54" layer="94"/>
</instance>
<instance part="TABLE1" gate="G$1" x="17.78" y="15.24" smashed="yes"/>
</instances>
<busses>
</busses>
<nets>
</nets>
</sheet>
<sheet>
<plain>
<text x="293.624" y="18.796" size="2.54" layer="94" ratio="15">Warp revision C</text>
<text x="293.624" y="11.176" size="1.778" layer="94">Authored 2015-2019
Phillip Stanley-Marbell
Richard Hopper</text>
<text x="293.624" y="6.096" size="1.778" layer="94">NO WARRANTY. See LICENCE.txt</text>
<text x="344.17" y="20.066" size="2.54" layer="94" ratio="15">Top Level</text>
<text x="83.82" y="81.28" size="1.778" layer="91">SPARKFUN QIIC connector</text>
<text x="22.86" y="213.36" size="1.778" layer="97">Battery JST socket</text>
<text x="17.78" y="63.5" size="1.778" layer="97">Supply switching for FPGA</text>
<wire x1="289.56" y1="50.8" x2="289.56" y2="124.46" width="0.1524" layer="97"/>
<wire x1="289.56" y1="124.46" x2="353.06" y2="124.46" width="0.1524" layer="97"/>
<wire x1="353.06" y1="124.46" x2="353.06" y2="50.8" width="0.1524" layer="97"/>
<wire x1="353.06" y1="50.8" x2="289.56" y2="50.8" width="0.1524" layer="97"/>
<text x="289.56" y="125.222" size="1.778" layer="97">Header breakout socket</text>
<text x="86.36" y="104.14" size="1.778" layer="97">External sensor sockets</text>
<text x="139.7" y="243.84" size="1.778" layer="97">Power source switching</text>
<wire x1="294.64" y1="132.08" x2="375.92" y2="132.08" width="0.1524" layer="97"/>
<wire x1="375.92" y1="132.08" x2="375.92" y2="162.56" width="0.1524" layer="97"/>
<wire x1="375.92" y1="162.56" x2="294.64" y2="162.56" width="0.1524" layer="97"/>
<wire x1="294.64" y1="162.56" x2="294.64" y2="132.08" width="0.1524" layer="97"/>
<text x="294.894" y="163.322" size="1.778" layer="97">SWD socket</text>
<wire x1="294.64" y1="167.64" x2="353.06" y2="167.64" width="0.1524" layer="97"/>
<wire x1="353.06" y1="167.64" x2="353.06" y2="198.12" width="0.1524" layer="97"/>
<wire x1="353.06" y1="198.12" x2="294.64" y2="198.12" width="0.1524" layer="97"/>
<wire x1="294.64" y1="198.12" x2="294.64" y2="167.64" width="0.1524" layer="97"/>
<text x="294.894" y="199.136" size="1.778" layer="97">MCU reset switch</text>
<text x="295.402" y="206.502" size="1.778" layer="97">MODULE ABBEVIATIONS
BT: BLUETHOOTH
CH: CHARGER
DP: DIGIPOT
FP: FPGA
MP: MPU
PV: BOOSTER
RG: REG
RT: RTC
SA: SENSORS-A
SB: SENSORS-B
USB: USB

</text>
</plain>
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<moduleinst name="PV" module="BOOSTER" x="78.74" y="233.68">
<attribute name="NAME" value="PV" x="78.74" y="233.68" size="2.032" layer="95" align="bottom-center"/>
</moduleinst>
<moduleinst name="MP" module="MPU" x="226.06" y="177.8">
<attribute name="NAME" value="MP" x="226.06" y="177.8" size="2.032" layer="95" align="bottom-center"/>
</moduleinst>
<moduleinst name="RG" module="REG" x="246.38" y="226.06">
<attribute name="NAME" value="RG" x="246.38" y="226.06" size="2.032" layer="95" align="bottom-center"/>
</moduleinst>
<moduleinst name="SA" module="SENSORS-A" x="223.52" y="101.6">
<attribute name="NAME" value="SA" x="223.52" y="101.6" size="2.032" layer="95" align="bottom-center"/>
</moduleinst>
<moduleinst name="FP" module="FPGA" x="86.36" y="30.48">
<attribute name="NAME" value="FP" x="86.36" y="30.48" size="2.032" layer="95" align="bottom-center"/>
</moduleinst>
<moduleinst name="SB" module="SENSORS-B" x="236.22" y="137.16">
<attribute name="NAME" value="SB" x="236.22" y="137.16" size="2.032" layer="95" align="bottom-center"/>
</moduleinst>
<moduleinst name="RT" module="RTC" x="83.82" y="121.92">
<attribute name="NAME" value="RT" x="83.82" y="121.92" size="2.032" layer="95" align="bottom-center"/>
</moduleinst>
<moduleinst name="CH" module="CHARGER" x="81.28" y="205.74">
<attribute name="NAME" value="CH" x="81.28" y="205.74" size="2.032" layer="95" align="bottom-center"/>
</moduleinst>
<moduleinst name="USB" module="USB" x="27.94" y="180.34">
<attribute name="NAME" value="USB" x="27.94" y="180.34" size="2.032" layer="95" align="bottom-center"/>
</moduleinst>
<moduleinst name="BT" module="BLUETOOTH" x="228.6" y="50.8">
<attribute name="NAME" value="BT" x="228.6" y="50.8" size="2.032" layer="95" align="bottom-center"/>
</moduleinst>
<moduleinst name="DP" module="DIGIPOT" x="81.28" y="154.94">
<attribute name="NAME" value="DP" x="81.28" y="154.94" size="2.032" layer="95" align="bottom-center"/>
</moduleinst>
</moduleinsts>
<instances>
<instance part="FRAME2" gate="G$1" x="0" y="0" smashed="yes">
<attribute name="DRAWING_NAME" x="344.17" y="15.24" size="2.54" layer="94"/>
<attribute name="LAST_DATE_TIME" x="344.17" y="10.16" size="2.286" layer="94"/>
<attribute name="SHEET" x="357.505" y="5.08" size="2.54" layer="94"/>
</instance>
<instance part="GND3" gate="1" x="101.6" y="226.06" smashed="yes">
<attribute name="VALUE" x="99.06" y="223.52" size="1.778" layer="96"/>
</instance>
<instance part="GND10" gate="1" x="254" y="93.98" smashed="yes">
<attribute name="VALUE" x="251.46" y="91.44" size="1.778" layer="96"/>
</instance>
<instance part="GND12" gate="1" x="264.16" y="147.32" smashed="yes">
<attribute name="VALUE" x="266.7" y="147.32" size="1.778" layer="96"/>
</instance>
<instance part="GND7" gate="1" x="114.3" y="7.62" smashed="yes">
<attribute name="VALUE" x="111.76" y="5.08" size="1.778" layer="96"/>
</instance>
<instance part="S1" gate="G$1" x="30.48" y="50.8" smashed="yes">
<attribute name="NAME" x="22.86" y="59.69" size="1.27" layer="95" ratio="15"/>
<attribute name="VALUE" x="22.86" y="40.64" size="1.27" layer="96" ratio="15"/>
</instance>
<instance part="GND4" gate="1" x="106.68" y="198.12" smashed="yes">
<attribute name="VALUE" x="104.14" y="195.58" size="1.778" layer="96"/>
</instance>
<instance part="GND14" gate="1" x="269.24" y="215.9" smashed="yes">
<attribute name="VALUE" x="266.7" y="213.36" size="1.778" layer="96"/>
</instance>
<instance part="GND13" gate="1" x="264.16" y="129.54" smashed="yes">
<attribute name="VALUE" x="261.62" y="127" size="1.778" layer="96"/>
</instance>
<instance part="GND11" gate="1" x="259.08" y="30.48" smashed="yes">
<attribute name="VALUE" x="256.54" y="27.94" size="1.778" layer="96"/>
</instance>
<instance part="GND5" gate="1" x="109.22" y="114.3" smashed="yes">
<attribute name="VALUE" x="106.68" y="111.76" size="1.778" layer="96"/>
</instance>
<instance part="J1" gate="G$1" x="30.48" y="205.74" smashed="yes" rot="R90">
<attribute name="NAME" x="24.638" y="203.2" size="1.778" layer="95" rot="R90"/>
</instance>
<instance part="GND1" gate="1" x="38.1" y="200.66" smashed="yes">
<attribute name="VALUE" x="35.56" y="198.12" size="1.778" layer="96"/>
</instance>
<instance part="J4" gate="G$1" x="302.26" y="86.36" smashed="yes">
<attribute name="NAME" x="292.354" y="120.142" size="1.778" layer="95"/>
<attribute name="VALUE" x="292.1" y="53.34" size="1.778" layer="96"/>
</instance>
<instance part="J2" gate="G$1" x="91.44" y="91.44" smashed="yes">
<attribute name="VALUE" x="86.36" y="86.106" size="1.778" layer="96" font="vector" align="top-left"/>
<attribute name="NAME" x="86.36" y="99.314" size="1.778" layer="95" font="vector"/>
</instance>
<instance part="GND9" gate="1" x="121.92" y="83.82" smashed="yes">
<attribute name="VALUE" x="119.38" y="81.28" size="1.778" layer="96"/>
</instance>
<instance part="GND2" gate="1" x="45.72" y="170.18" smashed="yes">
<attribute name="VALUE" x="43.18" y="167.64" size="1.778" layer="96"/>
</instance>
<instance part="GND6" gate="1" x="106.68" y="137.16" smashed="yes">
<attribute name="VALUE" x="104.14" y="134.62" size="1.778" layer="96"/>
</instance>
<instance part="J3" gate="G$1" x="91.44" y="68.58" smashed="yes">
<attribute name="VALUE" x="86.36" y="63.246" size="1.778" layer="96" font="vector" align="top-left"/>
<attribute name="NAME" x="86.36" y="76.454" size="1.778" layer="95" font="vector"/>
</instance>
<instance part="GND8" gate="1" x="116.84" y="58.42" smashed="yes">
<attribute name="VALUE" x="114.3" y="55.88" size="1.778" layer="96"/>
</instance>
<instance part="S2" gate="G$1" x="149.86" y="231.14" smashed="yes">
<attribute name="NAME" x="142.24" y="240.03" size="1.27" layer="95" ratio="15"/>
<attribute name="VALUE" x="142.24" y="220.98" size="1.27" layer="96" ratio="15"/>
</instance>
<instance part="GND17" gate="1" x="302.26" y="139.7" smashed="yes">
<attribute name="VALUE" x="299.72" y="137.16" size="1.778" layer="96"/>
</instance>
<instance part="S3" gate="G$1" x="312.42" y="180.34" smashed="yes">
<attribute name="NAME" x="307.34" y="186.182" size="2.54" layer="95" font="vector"/>
<attribute name="VALUE" x="307.34" y="171.704" size="2.54" layer="96" font="vector"/>
</instance>
<instance part="GND15" gate="1" x="299.72" y="172.72" smashed="yes">
<attribute name="VALUE" x="297.18" y="170.18" size="1.778" layer="96"/>
</instance>
<instance part="GND16" gate="1" x="335.28" y="180.34" smashed="yes">
<attribute name="VALUE" x="332.74" y="177.8" size="1.778" layer="96"/>
</instance>
<instance part="J5" gate="G$1" x="314.96" y="149.86" smashed="yes">
<attribute name="NAME" x="320.04" y="153.162" size="1.27" layer="95"/>
<attribute name="VALUE" x="320.04" y="135.128" size="1.27" layer="96"/>
</instance>
</instances>
<busses>
<bus name="SPI:SPI_MISO/UART_RTS,SPI_MOSI/UART_CTS,SPI_SCK">
<segment>
<wire x1="144.78" y1="27.94" x2="144.78" y2="190.5" width="0.762" layer="92"/>
<label x="144.78" y="193.04" size="1.778" layer="95"/>
</segment>
</bus>
<bus name="I2C1:I2C1_SCL,I2C1_SDA">
<segment>
<wire x1="137.16" y1="154.94" x2="137.16" y2="45.72" width="0.762" layer="92"/>
<label x="137.16" y="154.94" size="1.778" layer="95"/>
</segment>
</bus>
<bus name="I2C2:I2C2_SCL,I2C2_SDA">
<segment>
<wire x1="152.4" y1="167.64" x2="152.4" y2="35.56" width="0.762" layer="92"/>
<label x="152.4" y="170.18" size="1.778" layer="95"/>
</segment>
</bus>
<bus name="I2C0:I2C0_SCL/UART_TX,I2C0_SDA/UART_RX">
<segment>
<wire x1="160.02" y1="167.64" x2="160.02" y2="53.34" width="0.762" layer="92"/>
<label x="160.02" y="170.18" size="1.778" layer="95"/>
</segment>
</bus>
</busses>
<nets>
<net name="GND" class="0">
<segment>
<portref moduleinst="RG" port="GND"/>
<wire x1="266.7" y1="220.98" x2="269.24" y2="220.98" width="0.1524" layer="91"/>
<pinref part="GND14" gate="1" pin="GND"/>
<wire x1="269.24" y1="220.98" x2="269.24" y2="218.44" width="0.1524" layer="91"/>
</segment>
<segment>
<portref moduleinst="PV" port="GND"/>
<wire x1="96.52" y1="231.14" x2="101.6" y2="231.14" width="0.1524" layer="91"/>
<pinref part="GND3" gate="1" pin="GND"/>
<wire x1="101.6" y1="231.14" x2="101.6" y2="228.6" width="0.1524" layer="91"/>
</segment>
<segment>
<pinref part="GND12" gate="1" pin="GND"/>
<portref moduleinst="MP" port="GND"/>
<wire x1="256.54" y1="152.4" x2="264.16" y2="152.4" width="0.1524" layer="91"/>
<wire x1="264.16" y1="152.4" x2="264.16" y2="149.86" width="0.1524" layer="91"/>
</segment>
<segment>
<portref moduleinst="SA" port="GND"/>
<wire x1="248.92" y1="99.06" x2="254" y2="99.06" width="0.1524" layer="91"/>
<pinref part="GND10" gate="1" pin="GND"/>
<wire x1="254" y1="99.06" x2="254" y2="96.52" width="0.1524" layer="91"/>
</segment>
<segment>
<portref moduleinst="SB" port="GND"/>
<wire x1="261.62" y1="134.62" x2="264.16" y2="134.62" width="0.1524" layer="91"/>
<wire x1="264.16" y1="134.62" x2="264.16" y2="132.08" width="0.1524" layer="91"/>
<pinref part="GND13" gate="1" pin="GND"/>
</segment>
<segment>
<portref moduleinst="FP" port="GND"/>
<wire x1="109.22" y1="12.7" x2="114.3" y2="12.7" width="0.1524" layer="91"/>
<pinref part="GND7" gate="1" pin="GND"/>
<wire x1="114.3" y1="12.7" x2="114.3" y2="10.16" width="0.1524" layer="91"/>
</segment>
<segment>
<portref moduleinst="RT" port="GND"/>
<wire x1="104.14" y1="119.38" x2="109.22" y2="119.38" width="0.1524" layer="91"/>
<wire x1="109.22" y1="119.38" x2="109.22" y2="116.84" width="0.1524" layer="91"/>
<pinref part="GND5" gate="1" pin="GND"/>
</segment>
<segment>
<portref moduleinst="CH" port="GND"/>
<pinref part="GND4" gate="1" pin="GND"/>
<wire x1="101.6" y1="203.2" x2="106.68" y2="203.2" width="0.1524" layer="91"/>
<wire x1="106.68" y1="203.2" x2="106.68" y2="200.66" width="0.1524" layer="91"/>
</segment>
<segment>
<pinref part="J1" gate="G$1" pin="-"/>
<pinref part="GND1" gate="1" pin="GND"/>
<wire x1="35.56" y1="205.74" x2="38.1" y2="205.74" width="0.1524" layer="91"/>
<wire x1="38.1" y1="205.74" x2="38.1" y2="203.2" width="0.1524" layer="91"/>
</segment>
<segment>
<label x="101.6" y="88.9" size="1.778" layer="95"/>
<wire x1="99.06" y1="88.9" x2="121.92" y2="88.9" width="0.1524" layer="91"/>
<wire x1="121.92" y1="88.9" x2="121.92" y2="86.36" width="0.1524" layer="91"/>
<pinref part="GND9" gate="1" pin="GND"/>
<pinref part="J2" gate="G$1" pin="GND"/>
</segment>
<segment>
<wire x1="45.72" y1="175.26" x2="45.72" y2="172.72" width="0.1524" layer="91"/>
<pinref part="GND2" gate="1" pin="GND"/>
<portref moduleinst="USB" port="GND"/>
<wire x1="45.72" y1="175.26" x2="43.18" y2="175.26" width="0.1524" layer="91"/>
</segment>
<segment>
<portref moduleinst="BT" port="GND"/>
<wire x1="256.54" y1="38.1" x2="259.08" y2="38.1" width="0.1524" layer="91"/>
<pinref part="GND11" gate="1" pin="GND"/>
<wire x1="259.08" y1="38.1" x2="259.08" y2="33.02" width="0.1524" layer="91"/>
</segment>
<segment>
<portref moduleinst="DP" port="GND"/>
<wire x1="101.6" y1="142.24" x2="106.68" y2="142.24" width="0.1524" layer="91"/>
<pinref part="GND6" gate="1" pin="GND"/>
<wire x1="106.68" y1="142.24" x2="106.68" y2="139.7" width="0.1524" layer="91"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$20"/>
<wire x1="317.5" y1="68.58" x2="350.52" y2="68.58" width="0.1524" layer="91"/>
<label x="325.12" y="68.58" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J3" gate="G$1" pin="GND"/>
<wire x1="99.06" y1="66.04" x2="116.84" y2="66.04" width="0.1524" layer="91"/>
<wire x1="116.84" y1="66.04" x2="116.84" y2="60.96" width="0.1524" layer="91"/>
<pinref part="GND8" gate="1" pin="GND"/>
</segment>
<segment>
<pinref part="GND17" gate="1" pin="GND"/>
<wire x1="302.26" y1="147.32" x2="302.26" y2="144.78" width="0.1524" layer="91"/>
<wire x1="302.26" y1="144.78" x2="302.26" y2="142.24" width="0.1524" layer="91"/>
<junction x="302.26" y="144.78"/>
<pinref part="J5" gate="G$1" pin="3"/>
<wire x1="302.26" y1="147.32" x2="314.96" y2="147.32" width="0.1524" layer="91"/>
<pinref part="J5" gate="G$1" pin="5"/>
<wire x1="302.26" y1="144.78" x2="314.96" y2="144.78" width="0.1524" layer="91"/>
</segment>
<segment>
<pinref part="S3" gate="G$1" pin="B"/>
<wire x1="302.26" y1="177.8" x2="299.72" y2="177.8" width="0.1524" layer="91"/>
<wire x1="299.72" y1="177.8" x2="299.72" y2="175.26" width="0.1524" layer="91"/>
<pinref part="GND15" gate="1" pin="GND"/>
</segment>
<segment>
<pinref part="S3" gate="G$1" pin="B'"/>
<wire x1="322.58" y1="177.8" x2="330.2" y2="177.8" width="0.1524" layer="91"/>
<wire x1="330.2" y1="177.8" x2="330.2" y2="187.96" width="0.1524" layer="91"/>
<wire x1="330.2" y1="187.96" x2="335.28" y2="187.96" width="0.1524" layer="91"/>
<wire x1="335.28" y1="187.96" x2="335.28" y2="182.88" width="0.1524" layer="91"/>
<pinref part="GND16" gate="1" pin="GND"/>
</segment>
</net>
<net name="BOOST_VBAT" class="0">
<segment>
<portref moduleinst="PV" port="VBAT"/>
<wire x1="60.96" y1="233.68" x2="43.18" y2="233.68" width="0.1524" layer="91"/>
<label x="43.18" y="233.68" size="1.778" layer="95"/>
</segment>
</net>
<net name="CLK32K" class="0">
<segment>
<portref moduleinst="MP" port="PTB13/CLKOUT32K"/>
<wire x1="256.54" y1="172.72" x2="284.48" y2="172.72" width="0.1524" layer="91"/>
<label x="261.62" y="172.72" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="SB" port="SI4705_RCLK"/>
<wire x1="261.62" y1="139.7" x2="276.86" y2="139.7" width="0.1524" layer="91"/>
<label x="264.16" y="139.7" size="1.778" layer="95"/>
</segment>
</net>
<net name="SPI_SCK" class="0">
<segment>
<portref moduleinst="MP" port="SPI_SCK"/>
<wire x1="144.78" y1="190.5" x2="195.58" y2="190.5" width="0.1524" layer="91"/>
<label x="180.34" y="190.5" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="SA" port="SPI_SCK"/>
<wire x1="198.12" y1="111.76" x2="144.78" y2="111.76" width="0.1524" layer="91"/>
<label x="182.88" y="111.76" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="FP" port="SPI_SCK"/>
<wire x1="109.22" y1="33.02" x2="144.78" y2="33.02" width="0.1524" layer="91"/>
<label x="111.76" y="33.02" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="DP" port="SPI_SCK"/>
<wire x1="144.78" y1="165.1" x2="101.6" y2="165.1" width="0.1524" layer="91"/>
<label x="104.14" y="165.1" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$11"/>
<wire x1="317.5" y1="91.44" x2="350.52" y2="91.44" width="0.1524" layer="91"/>
<label x="325.12" y="91.44" size="1.778" layer="95"/>
</segment>
</net>
<net name="ADXL362_SPI_CS" class="0">
<segment>
<portref moduleinst="SA" port="ADXL362_SPI_CS"/>
<wire x1="248.92" y1="111.76" x2="274.32" y2="111.76" width="0.1524" layer="91"/>
<label x="254" y="111.76" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="MP" port="PTA8"/>
<wire x1="256.54" y1="187.96" x2="284.48" y2="187.96" width="0.1524" layer="91"/>
<label x="261.62" y="187.96" size="1.778" layer="95"/>
</segment>
</net>
<net name="USB_5V" class="0">
<segment>
<portref moduleinst="CH" port="IN"/>
<wire x1="60.96" y1="205.74" x2="48.26" y2="205.74" width="0.1524" layer="91"/>
<wire x1="48.26" y1="205.74" x2="48.26" y2="185.42" width="0.1524" layer="91"/>
<label x="50.8" y="205.74" size="1.778" layer="95"/>
<portref moduleinst="USB" port="+5V"/>
<wire x1="48.26" y1="185.42" x2="43.18" y2="185.42" width="0.1524" layer="91"/>
<label x="50.8" y="185.42" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$14"/>
<wire x1="317.5" y1="83.82" x2="350.52" y2="83.82" width="0.1524" layer="91"/>
<label x="325.12" y="83.82" size="1.778" layer="95"/>
</segment>
</net>
<net name="I2C0_SCL/UART_TX" class="0">
<segment>
<portref moduleinst="MP" port="I2C_SCL/LPUART0_TX"/>
<label x="167.64" y="167.64" size="1.778" layer="95"/>
<wire x1="160.02" y1="167.64" x2="195.58" y2="167.64" width="0.1524" layer="91"/>
</segment>
<segment>
<portref moduleinst="RT" port="I2C_SCL"/>
<wire x1="160.02" y1="127" x2="104.14" y2="127" width="0.1524" layer="91"/>
<label x="109.22" y="127" size="1.778" layer="95"/>
</segment>
<segment>
<wire x1="160.02" y1="55.88" x2="200.66" y2="55.88" width="0.1524" layer="91"/>
<label x="167.64" y="55.88" size="1.778" layer="95"/>
<portref moduleinst="BT" port="UART_RX"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$5"/>
<wire x1="317.5" y1="106.68" x2="350.52" y2="106.68" width="0.1524" layer="91"/>
<label x="325.12" y="106.68" size="1.778" layer="95"/>
</segment>
</net>
<net name="I2C0_SDA/UART_RX" class="0">
<segment>
<portref moduleinst="MP" port="I2C_SDA/LPUART0_RX"/>
<label x="167.64" y="165.1" size="1.778" layer="95"/>
<wire x1="160.02" y1="165.1" x2="195.58" y2="165.1" width="0.1524" layer="91"/>
</segment>
<segment>
<portref moduleinst="RT" port="I2C_SDA"/>
<wire x1="160.02" y1="124.46" x2="104.14" y2="124.46" width="0.1524" layer="91"/>
<label x="109.22" y="124.46" size="1.778" layer="95"/>
</segment>
<segment>
<wire x1="160.02" y1="53.34" x2="200.66" y2="53.34" width="0.1524" layer="91"/>
<label x="167.64" y="53.34" size="1.778" layer="95"/>
<portref moduleinst="BT" port="UART_TX"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$6"/>
<wire x1="317.5" y1="104.14" x2="350.52" y2="104.14" width="0.1524" layer="91"/>
<label x="325.12" y="104.14" size="1.778" layer="95"/>
</segment>
</net>
<net name="REG_VSEL1" class="0">
<segment>
<portref moduleinst="RG" port="VSEL1"/>
<wire x1="226.06" y1="228.6" x2="208.28" y2="228.6" width="0.1524" layer="91"/>
<label x="208.28" y="228.6" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="MP" port="PTB6"/>
<wire x1="256.54" y1="162.56" x2="284.48" y2="162.56" width="0.1524" layer="91"/>
<label x="261.62" y="162.56" size="1.778" layer="95"/>
</segment>
</net>
<net name="REG_VSEL2" class="0">
<segment>
<portref moduleinst="RG" port="VSEL2"/>
<wire x1="226.06" y1="226.06" x2="208.28" y2="226.06" width="0.1524" layer="91"/>
<label x="208.28" y="226.06" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="MP" port="PTB7"/>
<wire x1="256.54" y1="165.1" x2="284.48" y2="165.1" width="0.1524" layer="91"/>
<label x="261.62" y="165.1" size="1.778" layer="95"/>
</segment>
</net>
<net name="REG_VSEL3" class="0">
<segment>
<portref moduleinst="RG" port="VSEL3"/>
<wire x1="226.06" y1="223.52" x2="208.28" y2="223.52" width="0.1524" layer="91"/>
<label x="208.28" y="223.52" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="MP" port="PTB10"/>
<wire x1="256.54" y1="167.64" x2="284.48" y2="167.64" width="0.1524" layer="91"/>
<label x="261.62" y="167.64" size="1.778" layer="95"/>
</segment>
</net>
<net name="REG_CTRL" class="0">
<segment>
<portref moduleinst="RG" port="CTRL"/>
<wire x1="226.06" y1="218.44" x2="208.28" y2="218.44" width="0.1524" layer="91"/>
<label x="208.28" y="218.44" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="MP" port="PTB5"/>
<wire x1="256.54" y1="160.02" x2="284.48" y2="160.02" width="0.1524" layer="91"/>
<label x="261.62" y="160.02" size="1.778" layer="95"/>
</segment>
</net>
<net name="VS1" class="0">
<segment>
<portref moduleinst="MP" port="VCC"/>
<label x="187.96" y="195.58" size="1.778" layer="95"/>
<wire x1="195.58" y1="195.58" x2="187.96" y2="195.58" width="0.1524" layer="91"/>
</segment>
<segment>
<portref moduleinst="RT" port="VCC"/>
<wire x1="63.5" y1="127" x2="55.88" y2="127" width="0.1524" layer="91"/>
<label x="55.88" y="127" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="S1" gate="G$1" pin="1"/>
<wire x1="17.78" y1="53.34" x2="10.16" y2="53.34" width="0.1524" layer="91"/>
<label x="10.16" y="53.34" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$18"/>
<wire x1="317.5" y1="73.66" x2="350.52" y2="73.66" width="0.1524" layer="91"/>
<label x="325.12" y="73.66" size="1.778" layer="95"/>
</segment>
<segment>
<wire x1="314.96" y1="149.86" x2="302.26" y2="149.86" width="0.1524" layer="91"/>
<wire x1="302.26" y1="152.4" x2="302.26" y2="149.86" width="0.1524" layer="91"/>
<label x="302.26" y="152.4" size="1.778" layer="95"/>
<pinref part="J5" gate="G$1" pin="1"/>
</segment>
<segment>
<portref moduleinst="RG" port="VOUT1"/>
<wire x1="266.7" y1="233.68" x2="276.86" y2="233.68" width="0.1524" layer="91"/>
<label x="271.78" y="233.68" size="1.778" layer="95"/>
</segment>
</net>
<net name="VS2" class="0">
<segment>
<portref moduleinst="SA" port="VCC"/>
<label x="187.96" y="114.3" size="1.778" layer="95"/>
<wire x1="198.12" y1="114.3" x2="187.96" y2="114.3" width="0.1524" layer="91"/>
</segment>
<segment>
<portref moduleinst="SB" port="VCC"/>
<wire x1="210.82" y1="139.7" x2="198.12" y2="139.7" width="0.1524" layer="91"/>
<label x="200.66" y="139.7" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="S1" gate="G$1" pin="2"/>
<wire x1="17.78" y1="48.26" x2="10.16" y2="48.26" width="0.1524" layer="91"/>
<label x="10.16" y="48.26" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="BT" port="VCC"/>
<wire x1="200.66" y1="60.96" x2="193.04" y2="60.96" width="0.1524" layer="91"/>
<label x="193.04" y="60.96" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="DP" port="VCC"/>
<wire x1="101.6" y1="170.18" x2="114.3" y2="170.18" width="0.1524" layer="91"/>
<label x="109.22" y="170.18" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$19"/>
<wire x1="317.5" y1="71.12" x2="350.52" y2="71.12" width="0.1524" layer="91"/>
<label x="325.12" y="71.12" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="RG" port="VOUT2"/>
<wire x1="266.7" y1="231.14" x2="276.86" y2="231.14" width="0.1524" layer="91"/>
<label x="271.78" y="231.14" size="1.778" layer="95"/>
</segment>
</net>
<net name="ISL23415_SPI_CS" class="0">
<segment>
<portref moduleinst="MP" port="PTA12"/>
<wire x1="256.54" y1="190.5" x2="284.48" y2="190.5" width="0.1524" layer="91"/>
<label x="261.62" y="190.5" size="1.778" layer="95"/>
</segment>
<segment>
<wire x1="101.6" y1="157.48" x2="132.08" y2="157.48" width="0.1524" layer="91"/>
<label x="104.14" y="157.48" size="1.778" layer="95"/>
<portref moduleinst="DP" port="SPI_CS"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$16"/>
<wire x1="317.5" y1="78.74" x2="350.52" y2="78.74" width="0.1524" layer="91"/>
<label x="325.12" y="78.74" size="1.778" layer="95"/>
</segment>
</net>
<net name="SPI_MOSI/UART_CTS" class="0">
<segment>
<portref moduleinst="SA" port="SPI_MOSI"/>
<wire x1="198.12" y1="106.68" x2="144.78" y2="106.68" width="0.1524" layer="91"/>
<label x="167.64" y="106.68" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="FP" port="SPI_MOSI"/>
<wire x1="144.78" y1="27.94" x2="109.22" y2="27.94" width="0.1524" layer="91"/>
<label x="111.76" y="27.94" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="BT" port="UART_CTS"/>
<wire x1="144.78" y1="48.26" x2="200.66" y2="48.26" width="0.1524" layer="91"/>
<label x="167.64" y="48.26" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="DP" port="SPI_MOSI"/>
<wire x1="144.78" y1="160.02" x2="101.6" y2="160.02" width="0.1524" layer="91"/>
<label x="104.14" y="160.02" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$13"/>
<wire x1="317.5" y1="86.36" x2="350.52" y2="86.36" width="0.1524" layer="91"/>
<label x="325.12" y="86.36" size="1.778" layer="95"/>
</segment>
<segment>
<wire x1="144.78" y1="187.96" x2="195.58" y2="187.96" width="0.1524" layer="91"/>
<label x="167.64" y="187.96" size="1.778" layer="95"/>
<portref moduleinst="MP" port="SPI_MOSI"/>
</segment>
</net>
<net name="SPI_MISO/UART_RTS" class="0">
<segment>
<portref moduleinst="SA" port="SPI_MISO"/>
<wire x1="198.12" y1="109.22" x2="144.78" y2="109.22" width="0.1524" layer="91"/>
<label x="167.64" y="109.22" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="FP" port="SPI_MISO"/>
<wire x1="144.78" y1="30.48" x2="109.22" y2="30.48" width="0.1524" layer="91"/>
<label x="111.76" y="30.48" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="BT" port="UART_RTS"/>
<wire x1="144.78" y1="50.8" x2="200.66" y2="50.8" width="0.1524" layer="91"/>
<label x="167.64" y="50.8" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="DP" port="SPI_MISO"/>
<wire x1="144.78" y1="162.56" x2="101.6" y2="162.56" width="0.1524" layer="91"/>
<label x="104.14" y="162.56" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$12"/>
<wire x1="317.5" y1="88.9" x2="350.52" y2="88.9" width="0.1524" layer="91"/>
<label x="325.12" y="88.9" size="1.778" layer="95"/>
</segment>
<segment>
<wire x1="144.78" y1="185.42" x2="195.58" y2="185.42" width="0.1524" layer="91"/>
<label x="167.64" y="185.42" size="1.778" layer="95"/>
<portref moduleinst="MP" port="SPI_MISO"/>
</segment>
</net>
<net name="RTC_!INT!/RESET_B" class="0">
<segment>
<wire x1="256.54" y1="182.88" x2="299.72" y2="182.88" width="0.1524" layer="91"/>
<label x="261.62" y="182.88" size="1.778" layer="95"/>
<portref moduleinst="MP" port="PTA1/RESET_B"/>
<wire x1="299.72" y1="182.88" x2="302.26" y2="182.88" width="0.1524" layer="91"/>
<wire x1="299.72" y1="182.88" x2="299.72" y2="193.04" width="0.1524" layer="91"/>
<junction x="299.72" y="182.88"/>
<wire x1="299.72" y1="193.04" x2="325.12" y2="193.04" width="0.1524" layer="91"/>
<wire x1="325.12" y1="193.04" x2="325.12" y2="182.88" width="0.1524" layer="91"/>
<wire x1="325.12" y1="182.88" x2="322.58" y2="182.88" width="0.1524" layer="91"/>
<pinref part="S3" gate="G$1" pin="A'"/>
<pinref part="S3" gate="G$1" pin="A"/>
</segment>
<segment>
<portref moduleinst="RT" port="!INT"/>
<wire x1="104.14" y1="121.92" x2="132.08" y2="121.92" width="0.1524" layer="91"/>
<label x="109.22" y="121.92" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$10"/>
<wire x1="317.5" y1="93.98" x2="350.52" y2="93.98" width="0.1524" layer="91"/>
<label x="325.12" y="93.98" size="1.778" layer="95"/>
</segment>
<segment>
<label x="340.36" y="139.7" size="1.778" layer="95"/>
<pinref part="J5" gate="G$1" pin="10"/>
<wire x1="363.22" y1="139.7" x2="337.82" y2="139.7" width="0.1524" layer="91"/>
</segment>
</net>
<net name="REG_VSEL4" class="0">
<segment>
<portref moduleinst="RG" port="VSEL4"/>
<wire x1="226.06" y1="220.98" x2="208.28" y2="220.98" width="0.1524" layer="91"/>
<label x="208.28" y="220.98" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="MP" port="PTB11"/>
<wire x1="256.54" y1="170.18" x2="284.48" y2="170.18" width="0.1524" layer="91"/>
<label x="261.62" y="170.18" size="1.778" layer="95"/>
</segment>
</net>
<net name="CHARGE_VOUT" class="0">
<segment>
<label x="116.84" y="228.6" size="1.778" layer="95"/>
<portref moduleinst="CH" port="OUT"/>
<wire x1="101.6" y1="205.74" x2="111.76" y2="205.74" width="0.1524" layer="91"/>
<wire x1="111.76" y1="205.74" x2="111.76" y2="228.6" width="0.1524" layer="91"/>
<wire x1="111.76" y1="228.6" x2="137.16" y2="228.6" width="0.1524" layer="91"/>
<pinref part="S2" gate="G$1" pin="2"/>
</segment>
</net>
<net name="REG_VIN" class="0">
<segment>
<wire x1="162.56" y1="233.68" x2="165.1" y2="233.68" width="0.1524" layer="91"/>
<wire x1="165.1" y1="233.68" x2="165.1" y2="228.6" width="0.1524" layer="91"/>
<wire x1="165.1" y1="228.6" x2="162.56" y2="228.6" width="0.1524" layer="91"/>
<junction x="165.1" y="233.68"/>
<label x="208.28" y="233.68" size="1.778" layer="95"/>
<portref moduleinst="RG" port="VIN"/>
<wire x1="226.06" y1="233.68" x2="165.1" y2="233.68" width="0.1524" layer="91"/>
<label x="167.64" y="233.68" size="1.778" layer="95"/>
<pinref part="S2" gate="G$1" pin="1'"/>
<pinref part="S2" gate="G$1" pin="2'"/>
</segment>
<segment>
<portref moduleinst="FP" port="VREG"/>
<wire x1="63.5" y1="43.18" x2="50.8" y2="43.18" width="0.1524" layer="91"/>
<label x="50.8" y="43.18" size="1.778" layer="95"/>
</segment>
</net>
<net name="FPGA_CS" class="0">
<segment>
<portref moduleinst="FP" port="SPI_CS"/>
<wire x1="109.22" y1="25.4" x2="127" y2="25.4" width="0.1524" layer="91"/>
<label x="111.76" y="25.4" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="MP" port="PTB1"/>
<wire x1="256.54" y1="154.94" x2="284.48" y2="154.94" width="0.1524" layer="91"/>
<label x="261.62" y="154.94" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$7"/>
<wire x1="317.5" y1="101.6" x2="350.52" y2="101.6" width="0.1524" layer="91"/>
<label x="325.12" y="101.6" size="1.778" layer="95"/>
</segment>
</net>
<net name="I2C1_SDA" class="0">
<segment>
<portref moduleinst="FP" port="I2C1_SDA"/>
<label x="111.76" y="45.72" size="1.778" layer="95"/>
<wire x1="109.22" y1="45.72" x2="137.16" y2="45.72" width="0.1524" layer="91"/>
</segment>
<segment>
<portref moduleinst="SA" port="I2C_SDA"/>
<label x="177.8" y="99.06" size="1.778" layer="95"/>
<wire x1="198.12" y1="99.06" x2="137.16" y2="99.06" width="0.1524" layer="91"/>
</segment>
<segment>
<portref moduleinst="DP" port="DCP_RW2"/>
<label x="104.14" y="152.4" size="1.778" layer="95"/>
<wire x1="101.6" y1="152.4" x2="137.16" y2="152.4" width="0.1524" layer="91"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$2"/>
<wire x1="317.5" y1="114.3" x2="350.52" y2="114.3" width="0.1524" layer="91"/>
<label x="325.12" y="114.3" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J3" gate="G$1" pin="SDA"/>
<wire x1="137.16" y1="71.12" x2="99.06" y2="71.12" width="0.1524" layer="91"/>
<label x="104.14" y="71.12" size="1.778" layer="95"/>
</segment>
</net>
<net name="I2C1_SCL" class="0">
<segment>
<portref moduleinst="FP" port="I2C1_SCL"/>
<label x="111.76" y="48.26" size="1.778" layer="95"/>
<wire x1="109.22" y1="48.26" x2="137.16" y2="48.26" width="0.1524" layer="91"/>
</segment>
<segment>
<portref moduleinst="SA" port="I2C_SCL"/>
<label x="177.8" y="101.6" size="1.778" layer="95"/>
<wire x1="198.12" y1="101.6" x2="137.16" y2="101.6" width="0.1524" layer="91"/>
</segment>
<segment>
<portref moduleinst="DP" port="DCP_RW1"/>
<label x="104.14" y="154.94" size="1.778" layer="95"/>
<wire x1="101.6" y1="154.94" x2="137.16" y2="154.94" width="0.1524" layer="91"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$1"/>
<wire x1="317.5" y1="116.84" x2="350.52" y2="116.84" width="0.1524" layer="91"/>
<label x="325.12" y="116.84" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J3" gate="G$1" pin="SCL"/>
<wire x1="137.16" y1="73.66" x2="99.06" y2="73.66" width="0.1524" layer="91"/>
<label x="104.14" y="73.66" size="1.778" layer="95"/>
</segment>
</net>
<net name="I2C2_SCL" class="0">
<segment>
<portref moduleinst="FP" port="I2C2_SCL"/>
<label x="111.76" y="40.64" size="1.778" layer="95"/>
<wire x1="109.22" y1="40.64" x2="152.4" y2="40.64" width="0.1524" layer="91"/>
</segment>
<segment>
<portref moduleinst="DP" port="DCP_RW3"/>
<label x="104.14" y="149.86" size="1.778" layer="95"/>
<wire x1="101.6" y1="149.86" x2="152.4" y2="149.86" width="0.1524" layer="91"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$3"/>
<wire x1="317.5" y1="111.76" x2="350.52" y2="111.76" width="0.1524" layer="91"/>
<label x="325.12" y="111.76" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J2" gate="G$1" pin="SCL"/>
<wire x1="152.4" y1="96.52" x2="99.06" y2="96.52" width="0.1524" layer="91"/>
<label x="104.14" y="96.52" size="1.778" layer="95"/>
</segment>
<segment>
<wire x1="152.4" y1="137.16" x2="210.82" y2="137.16" width="0.1524" layer="91"/>
<label x="195.58" y="137.16" size="1.778" layer="95"/>
<portref moduleinst="SB" port="I2C_SCL"/>
</segment>
</net>
<net name="I2C2_SDA" class="0">
<segment>
<portref moduleinst="FP" port="I2C2_SDA"/>
<label x="111.76" y="38.1" size="1.778" layer="95"/>
<wire x1="109.22" y1="38.1" x2="152.4" y2="38.1" width="0.1524" layer="91"/>
</segment>
<segment>
<portref moduleinst="DP" port="DCP_RW4"/>
<label x="104.14" y="147.32" size="1.778" layer="95"/>
<wire x1="101.6" y1="147.32" x2="152.4" y2="147.32" width="0.1524" layer="91"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$4"/>
<wire x1="317.5" y1="109.22" x2="350.52" y2="109.22" width="0.1524" layer="91"/>
<label x="325.12" y="109.22" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J2" gate="G$1" pin="SDA"/>
<wire x1="152.4" y1="93.98" x2="99.06" y2="93.98" width="0.1524" layer="91"/>
<label x="104.14" y="93.98" size="1.778" layer="95"/>
</segment>
<segment>
<wire x1="152.4" y1="134.62" x2="210.82" y2="134.62" width="0.1524" layer="91"/>
<label x="195.58" y="134.62" size="1.778" layer="95"/>
<portref moduleinst="SB" port="I2C_SDA"/>
</segment>
</net>
<net name="BAT" class="0">
<segment>
<pinref part="J1" gate="G$1" pin="+"/>
<portref moduleinst="CH" port="BAT"/>
<wire x1="35.56" y1="208.28" x2="60.96" y2="208.28" width="0.1524" layer="91"/>
<label x="50.8" y="208.28" size="1.778" layer="95"/>
</segment>
</net>
<net name="FPGA_VS" class="0">
<segment>
<pinref part="S1" gate="G$1" pin="1'"/>
<wire x1="43.18" y1="53.34" x2="45.72" y2="53.34" width="0.1524" layer="91"/>
<wire x1="45.72" y1="53.34" x2="45.72" y2="48.26" width="0.1524" layer="91"/>
<junction x="45.72" y="48.26"/>
<portref moduleinst="FP" port="VCC"/>
<wire x1="45.72" y1="48.26" x2="63.5" y2="48.26" width="0.1524" layer="91"/>
<junction x="45.72" y="48.26"/>
<label x="50.8" y="48.26" size="1.778" layer="95"/>
<pinref part="S1" gate="G$1" pin="2'"/>
<wire x1="43.18" y1="48.26" x2="45.72" y2="48.26" width="0.1524" layer="91"/>
</segment>
</net>
<net name="SWD_DIO" class="0">
<segment>
<portref moduleinst="MP" port="PTA2/SWD_DIO"/>
<wire x1="256.54" y1="180.34" x2="284.48" y2="180.34" width="0.1524" layer="91"/>
<label x="261.62" y="180.34" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$8"/>
<wire x1="317.5" y1="99.06" x2="350.52" y2="99.06" width="0.1524" layer="91"/>
<label x="325.12" y="99.06" size="1.778" layer="95"/>
</segment>
<segment>
<label x="340.36" y="149.86" size="1.778" layer="95"/>
<pinref part="J5" gate="G$1" pin="2"/>
<wire x1="353.06" y1="149.86" x2="337.82" y2="149.86" width="0.1524" layer="91"/>
</segment>
</net>
<net name="SWD_CLK" class="0">
<segment>
<portref moduleinst="MP" port="PTA0/SWD_CLK"/>
<wire x1="256.54" y1="177.8" x2="284.48" y2="177.8" width="0.1524" layer="91"/>
<label x="261.62" y="177.8" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$9"/>
<wire x1="317.5" y1="96.52" x2="350.52" y2="96.52" width="0.1524" layer="91"/>
<label x="325.12" y="96.52" size="1.778" layer="95"/>
</segment>
<segment>
<label x="340.36" y="147.32" size="1.778" layer="95"/>
<pinref part="J5" gate="G$1" pin="4"/>
<wire x1="353.06" y1="147.32" x2="337.82" y2="147.32" width="0.1524" layer="91"/>
</segment>
</net>
<net name="PV_VOUT" class="0">
<segment>
<wire x1="137.16" y1="233.68" x2="96.52" y2="233.68" width="0.1524" layer="91"/>
<portref moduleinst="PV" port="VOUT"/>
<label x="116.84" y="233.68" size="1.778" layer="95"/>
<pinref part="S2" gate="G$1" pin="1"/>
</segment>
</net>
<net name="VCC_QIIC" class="0">
<segment>
<pinref part="J2" gate="G$1" pin="VCC"/>
<wire x1="99.06" y1="91.44" x2="116.84" y2="91.44" width="0.1524" layer="91"/>
<label x="116.84" y="91.44" size="1.778" layer="95"/>
<pinref part="J3" gate="G$1" pin="VCC"/>
<wire x1="99.06" y1="68.58" x2="116.84" y2="68.58" width="0.1524" layer="91"/>
<label x="104.14" y="68.58" size="1.778" layer="95"/>
<wire x1="116.84" y1="91.44" x2="116.84" y2="68.58" width="0.1524" layer="91"/>
<wire x1="116.84" y1="91.44" x2="129.54" y2="91.44" width="0.1524" layer="91"/>
<junction x="116.84" y="91.44"/>
</segment>
<segment>
<portref moduleinst="RG" port="EXT_VIN"/>
<wire x1="226.06" y1="231.14" x2="208.28" y2="231.14" width="0.1524" layer="91"/>
<label x="208.28" y="231.14" size="1.778" layer="95"/>
</segment>
</net>
<net name="BGX13S_!RST" class="0">
<segment>
<portref moduleinst="BT" port="!RESET"/>
<wire x1="256.54" y1="60.96" x2="276.86" y2="60.96" width="0.1524" layer="91"/>
<label x="259.08" y="60.96" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="MP" port="PTA5"/>
<wire x1="256.54" y1="185.42" x2="284.48" y2="185.42" width="0.1524" layer="91"/>
<label x="261.62" y="185.42" size="1.778" layer="95"/>
</segment>
</net>
<net name="SI4705_!RST" class="0">
<segment>
<portref moduleinst="SB" port="SI4705_!RST"/>
<wire x1="261.62" y1="137.16" x2="276.86" y2="137.16" width="0.1524" layer="91"/>
<label x="261.62" y="137.16" size="1.778" layer="95"/>
</segment>
<segment>
<portref moduleinst="MP" port="PTB2"/>
<wire x1="256.54" y1="157.48" x2="284.48" y2="157.48" width="0.1524" layer="91"/>
<label x="261.62" y="157.48" size="1.778" layer="95"/>
</segment>
</net>
<net name="PV_VIN" class="0">
<segment>
<wire x1="43.18" y1="236.22" x2="60.96" y2="236.22" width="0.1524" layer="91"/>
<portref moduleinst="PV" port="VIN"/>
<label x="43.18" y="236.22" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$15"/>
<wire x1="317.5" y1="81.28" x2="350.52" y2="81.28" width="0.1524" layer="91"/>
<label x="325.12" y="81.28" size="1.778" layer="95"/>
</segment>
</net>
<net name="CRESET_B" class="0">
<segment>
<portref moduleinst="FP" port="CRESET_B"/>
<wire x1="109.22" y1="17.78" x2="127" y2="17.78" width="0.1524" layer="91"/>
<label x="111.76" y="17.78" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J4" gate="G$1" pin="P$17"/>
<wire x1="317.5" y1="76.2" x2="350.52" y2="76.2" width="0.1524" layer="91"/>
<label x="325.12" y="76.2" size="1.778" layer="95"/>
</segment>
</net>
</nets>
</sheet>
</sheets>
<errors>
<approved hash="104,2,99.06,91.44,J2,VCC,VCC_QIIC,,,"/>
<approved hash="104,2,99.06,68.58,J3,VCC,VCC_QIIC,,,"/>
<approved hash="104,1@BOOSTER,152.4,200.66,U1,VSS1,GND,,,"/>
<approved hash="104,1@BOOSTER,152.4,198.12,U1,VIN_DC,VIN,,,"/>
<approved hash="104,1@BOOSTER,152.4,195.58,U1,VOC_SAMP,VSTOR,,,"/>
<approved hash="103,1@BOOSTER,152.4,180.34,U1,NC9,GND,,,"/>
<approved hash="104,1@BOOSTER,187.96,187.96,U1,VSS15,GND,,,"/>
<approved hash="103,1@BOOSTER,187.96,193.04,U1,NC17,GND,,,"/>
<approved hash="104,1@BOOSTER,187.96,167.64,U1,PAD,GND,,,"/>
<approved hash="104,1@MPU,101.6,210.82,U1,VDD,VCC,,,"/>
<approved hash="104,1@MPU,101.6,119.38,U1,VSS,GND,,,"/>
<approved hash="202,1@REG,248.92,106.68,U2,EN,,,,"/>
<approved hash="202,1@REG,248.92,76.2,U3,EN,,,,"/>
<approved hash="104,1@BLUETOOTH,99.06,127,U1,VSS,GND,,,"/>
<approved hash="104,1@BLUETOOTH,96.52,175.26,U1,VBATT,VCC,,,"/>
<approved hash="104,1@BLUETOOTH,101.6,175.26,U1,IOVDD,VCC,,,"/>
<approved hash="202,1@BLUETOOTH,124.46,139.7,U1,BOOT,,,,"/>
<approved hash="104,1@SENSORS-A,160.02,233.68,U2,VDD,VCC,,,"/>
<approved hash="104,1@SENSORS-A,160.02,228.6,U2,VDDIO,VCC,,,"/>
<approved hash="104,1@SENSORS-A,160.02,187.96,U2,GNDA,GND,,,"/>
<approved hash="104,1@SENSORS-A,160.02,182.88,U2,GNDIO,GND,,,"/>
<approved hash="104,1@SENSORS-A,50.8,55.88,U5,VDD,VCC,,,"/>
<approved hash="104,1@SENSORS-A,48.26,243.84,U1,VS,VCC,,,"/>
<approved hash="104,1@SENSORS-A,48.26,238.76,U1,VDDIO,VCC,,,"/>
<approved hash="104,1@SENSORS-A,185.42,127,U4,GND1,GND,,,"/>
<approved hash="104,1@SENSORS-A,154.94,121.92,U4,VDDIO,VCC,,,"/>
<approved hash="104,1@SENSORS-A,154.94,116.84,U4,GND7,GND,,,"/>
<approved hash="104,1@SENSORS-A,154.94,111.76,U4,VDD,VCC,,,"/>
<approved hash="104,1@SENSORS-A,81.28,132.08,U3,VDD,VCC,,,"/>
<approved hash="104,1@SENSORS-A,81.28,114.3,U3,EXP,GND,,,"/>
<approved hash="104,1@FPGA,175.26,160.02,U2,VCCIO_2,VCC,,,"/>
<approved hash="104,1@FPGA,175.26,154.94,U2,VCC,VCC_1V2,,,"/>
<approved hash="104,1@FPGA,175.26,111.76,U2,SPI_VCCIO1,VCC_SHUNT,,,"/>
<approved hash="104,1@FPGA,175.26,167.64,U2,VPP_2V5,VCC,,,"/>
<approved hash="104,1@FPGA,175.26,162.56,U2,VCCPLL,ICE40_VCC_PLL,,,"/>
<approved hash="104,1@FPGA,175.26,165.1,U2,VCCIO_0,VCC_1V2,,,"/>
<approved hash="104,1@SENSORS-B,50.8,226.06,U1,VDD,VCC,,,"/>
<approved hash="104,1@SENSORS-B,50.8,220.98,U1,VDDIO,VCC,,,"/>
<approved hash="104,1@SENSORS-B,149.86,226.06,U2,VDD,VCC,,,"/>
<approved hash="104,1@SENSORS-B,149.86,220.98,U2,VDD_IO,VCC,,,"/>
<approved hash="103,1@SENSORS-B,149.86,195.58,U2,RESERVED,GND,,,"/>
<approved hash="103,1@SENSORS-B,149.86,200.66,U2,RESERVED,GND,,,"/>
<approved hash="103,1@SENSORS-B,149.86,205.74,U2,RESERVED,GND,,,"/>
<approved hash="103,1@SENSORS-B,149.86,210.82,U2,RESERVED,GND,,,"/>
<approved hash="104,1@SENSORS-B,299.72,213.36,U3,VDD,VCC,,,"/>
<approved hash="104,1@SENSORS-B,165.1,139.7,U5,VDD,VCC,,,"/>
<approved hash="104,1@SENSORS-B,165.1,134.62,U5,VDD_IO,VCC,,,"/>
<approved hash="104,1@SENSORS-B,180.34,73.66,U7,VDD,VCC,,,"/>
<approved hash="104,1@SENSORS-B,307.34,139.7,U6,VD,VCC,,,"/>
<approved hash="104,1@SENSORS-B,307.34,134.62,U6,VA,VCC,,,"/>
<approved hash="104,1@SENSORS-B,307.34,73.66,U6,RFGND,GND,,,"/>
<approved hash="202,1@SENSORS-B,340.36,134.62,U6,LPI,,,,"/>
<approved hash="202,1@SENSORS-B,340.36,83.82,U6,DFS,,,,"/>
<approved hash="104,1@SENSORS-B,53.34,121.92,U4,VDDIO,VCC,,,"/>
<approved hash="104,1@SENSORS-B,53.34,116.84,U4,VDD,VCC,,,"/>
<approved hash="104,1@RTC,193.04,114.3,U1,VDD,VCC,,,"/>
<approved hash="104,1@RTC,228.6,109.22,U1,VSS,GND,,,"/>
<approved hash="104,1@CHARGER,218.44,132.08,U1,VSS,GND,,,"/>
<approved hash="202,1@CHARGER,279.4,147.32,U2,EN,,,,"/>
<approved hash="104,1@DIGIPOT,132.08,137.16,U1,VGND,GND,,,"/>
<approved hash="104,1@DIGIPOT,132.08,132.08,U1,VLOGIC,VCC,,,"/>
<approved hash="104,1@DIGIPOT,132.08,73.66,U3,VGND,GND,,,"/>
<approved hash="104,1@DIGIPOT,132.08,68.58,U3,VLOGIC,VCC,,,"/>
<approved hash="104,1@DIGIPOT,215.9,139.7,U2,VGND,GND,,,"/>
<approved hash="104,1@DIGIPOT,215.9,134.62,U2,VLOGIC,VCC,,,"/>
<approved hash="104,1@DIGIPOT,215.9,76.2,U4,VGND,GND,,,"/>
<approved hash="104,1@DIGIPOT,215.9,71.12,U4,VLOGIC,VCC,,,"/>
<approved hash="106,2,60.96,233.68,BOOST_VBAT,,,,,"/>
<approved hash="206,2,195.58,187.96,SPI_MISO/UART_RTS,,,,,"/>
<approved hash="206,2,198.12,109.22,SPI_MISO/UART_RTS,,,,,"/>
<approved hash="206,2,101.6,162.56,SPI_MISO/UART_RTS,,,,,"/>
<approved hash="206,1@BLUETOOTH,73.66,162.56,N$3,,,,,"/>
<approved hash="206,1@BLUETOOTH,73.66,165.1,N$3,,,,,"/>
<approved hash="213,2,109.22,12.7,GND,pwr,,,,"/>
<approved hash="208,1@FPGA,312.42,106.68,GND,sup,,,,"/>
<approved hash="208,1@FPGA,325.12,106.68,GND,sup,,,,"/>
<approved hash="208,1@FPGA,226.06,149.86,GND,sup,,,,"/>
<approved hash="208,1@FPGA,213.36,149.86,GND,sup,,,,"/>
<approved hash="208,1@FPGA,185.42,45.72,GND,sup,,,,"/>
<approved hash="208,1@FPGA,119.38,185.42,GND,sup,,,,"/>
<approved hash="208,1@FPGA,68.58,187.96,GND,sup,,,,"/>
<approved hash="208,1@FPGA,48.26,185.42,GND,sup,,,,"/>
<approved hash="208,1@FPGA,109.22,185.42,GND,sup,,,,"/>
<approved hash="208,1@FPGA,195.58,119.38,GND,sup,,,,"/>
<approved hash="208,1@FPGA,175.26,71.12,GND,out,,,,"/>
<approved hash="208,1@FPGA,205.74,68.58,GND,sup,,,,"/>
<approved hash="209,1@SENSORS-B,340.36,139.7,SI4705_FMI,,,,,"/>
<approved hash="106,1@SENSORS-B,340.36,139.7,SI4705_FMI,,,,,"/>
<approved hash="206,1@DIGIPOT,132.08,172.72,SPI_MISO,,,,,"/>
<approved hash="206,1@DIGIPOT,132.08,109.22,SPI_MISO,,,,,"/>
<approved hash="206,1@DIGIPOT,215.9,175.26,SPI_MISO,,,,,"/>
<approved hash="206,1@DIGIPOT,215.9,111.76,SPI_MISO,,,,,"/>
<approved hash="113,2,193.571,130.071,FRAME2,,,,,"/>
<approved hash="113,2,30.9778,207.01,J1,,,,,"/>
<approved hash="113,1,193.571,130.071,FRAME1,,,,,"/>
<approved hash="113,1@BOOSTER,193.571,130.071,FRAME1,,,,,"/>
<approved hash="113,1@MPU,193.571,130.071,FRAME1,,,,,"/>
<approved hash="113,1@REG,193.571,130.071,FRAME1,,,,,"/>
<approved hash="113,1@BLUETOOTH,193.571,130.071,FRAME1,,,,,"/>
<approved hash="113,1@SENSORS-A,193.571,130.071,FRAME1,,,,,"/>
<approved hash="113,1@FPGA,193.571,130.071,FRAME1,,,,,"/>
<approved hash="113,1@SENSORS-B,193.571,130.071,FRAME1,,,,,"/>
<approved hash="113,1@RTC,193.571,130.071,FRAME1,,,,,"/>
<approved hash="113,1@CHARGER,193.571,130.071,FRAME1,,,,,"/>
<approved hash="113,1@USB,193.571,130.071,FRAME1,,,,,"/>
<approved hash="113,1@DIGIPOT,193.571,130.071,FRAME1,,,,,"/>
<approved hash="118,1@BLUETOOTH,78.74,194.31,Net,GND,,,,"/>
</errors>
</schematic>
</drawing>
<compatibility>
<note version="6.3" minversion="6.2.2" severity="warning">
Since Version 6.2.2 text objects can contain more than one line,
which will not be processed correctly with this version.
</note>
<note version="8.2" severity="warning">
Since Version 8.2, EAGLE supports online libraries. The ids
of those online libraries will not be understood (or retained)
with this version.
</note>
<note version="8.3" severity="warning">
Since Version 8.3, EAGLE supports URNs for individual library
assets (packages, symbols, and devices). The URNs of those assets
will not be understood (or retained) with this version.
</note>
<note version="8.3" severity="warning">
Since Version 8.3, EAGLE supports the association of 3D packages
with devices in libraries, schematics, and board files. Those 3D
packages will not be understood (or retained) with this version.
</note>
</compatibility>
</eagle>


text:
// Copyright © 2021 Alibaba Group Holding Ltd.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

package v1beta1

import (
	"encoding/json"
	"strings"

	metav1 "k8s.io/apimachinery/pkg/apis/meta/v1"
)

// EDIT THIS FILE!  THIS IS SCAFFOLDING FOR YOU TO OWN!
// NOTE: json tags are required.  Any new fields you add must have json tags for the fields to be serialized.

type InfraSSH struct {
	Passwd string `json:"passwd,omitempty"`
	Port   int32  `json:"port"`
}

type InfraHost struct {
	Roles   []string    `json:"roles,omitempty"`
	CPU     int         `json:"cpu,omitempty"`
	Memory  int         `json:"memory,omitempty"`
	Count   int         `json:"count"`
	Disks   []InfraDisk `json:"disks"`
	Arch    Arch        `json:"arch,omitempty"`
	EcsType string      `json:"ecsType,omitempty"`
	OS      InfraOS     `json:"os,omitempty"`
}

func (h InfraHost) ToRole() HostRole {
	if IsMaster(h.Roles) {
		return Master
	}
	return Node
}

func (h InfraHost) String() string {
	data, _ := json.Marshal(&h)
	return string(data)
}

type InfraOS struct {
	Name    string `json:"name"`
	Version string `json:"version"`
	ID      string `json:"id,omitempty"`
}

type InfraDisk struct {
	Capacity int `json:"capacity"`
	//MountPoint string `json:"mountPoint,omitempty"`
	Category string `json:"category"`
}

type InfraCredential struct {
	AccessKey    string `json:"accessKey"`
	AccessSecret string `json:"accessSecret"`
	ProjectID    string `json:"ProjectID,omitempty"`
}

type InfraAccessChannels struct {
	SSH InfraSSH `json:"ssh,omitempty"`
}

type InfraInstance struct {
	IsSeize bool `json:"isSeize,omitempty"`

	Network InfraNetworkMeta `json:"network"`
}

type InfraNetworkMeta struct {
	Bandwidth     string            `json:"bandwidth"`
	ExportPorts   []InfraExportPort `json:"exportPorts,omitempty"`
	PrivateCidrIP string            `json:"privateCidrIP,omitempty"`
}

type InfraExportPort struct {
	Protocol  Protocol `json:"protocol"`
	CidrIP    string   `json:"cidrIP"`
	PortRange string   `json:"portRange"`
}

type InfraMetadata struct {
	RegionIDs      []string            `json:"regionIDs,omitempty"`
	ZoneIDs        []string            `json:"zoneIDs,omitempty"`
	Annotations    map[string]string   `json:"annotations,omitempty"`
	AccessChannels InfraAccessChannels `json:"accessChannels"`
	Instance       InfraInstance       `json:"instance,omitempty"`
}

// InfraSpec defines the desired state of Infra
type InfraSpec struct {
	// Foo is an example field of Infra. Edit types.go to remove/update
	Provider   Provider        `json:"provider,omitempty"`
	Credential InfraCredential `json:"credential,omitempty"`

	Metadata InfraMetadata `json:"metadata,omitempty"`
	Hosts    []InfraHost   `json:"hosts,omitempty"`
}

type InfraClusterStatus struct {
	RegionID          string            `json:"regionID,omitempty"`
	ZoneID            string            `json:"zoneID,omitempty"`
	SpotStrategy      string            `json:"spotStrategy,omitempty"`
	Annotations       map[string]string `json:"annotations,omitempty"`
	EIP               string            `json:"eip,omitempty"`
	Master0ID         string            `json:"master0ID,omitempty"`
	Master0InternalIP string            `json:"master0InternalIP,omitempty"`
}
type InfraHostStatus struct {
	Ready          bool     `json:"ready"`
	Roles          []string `json:"roles"`
	IDs            string   `json:"IDs,omitempty"`
	IPs            []string `json:"IPs,omitempty"`
	InstanceType   string   `json:"instanceType,omitempty"`
	SystemCategory string   `json:"systemCategory"`
	DataCategory   string   `json:"dataCategory,omitempty"`
	Arch           Arch     `json:"arch,omitempty"`
	ImageID        string   `json:"imageID,omitempty"`
}

// InfraStatus defines the observed state of Infra
type InfraStatus struct {
	Cluster InfraClusterStatus `json:"cluster"`
	Hosts   []InfraHostStatus  `json:"hosts"`
}

func (hs InfraHostStatus) ToHost() *InfraHost {
	return &InfraHost{
		Roles: hs.Roles,
		Arch:  hs.Arch,
	}
}

func (s InfraStatus) FindHostsByRoles(roles []string) int {
	for i, h := range s.Hosts {
		if strings.Join(h.Roles, ",") == strings.Join(roles, ",") {
			return i
		}
	}
	return -1
}

func (s InfraStatus) FindHostsByRolesString(roles string) int {
	for i, h := range s.Hosts {
		if strings.Join(h.Roles, ",") == roles {
			return i
		}
	}
	return -1
}

// +kubebuilder:object:root=true
// +kubebuilder:subresource:status
// +k8s:deepcopy-gen:interfaces=k8s.io/apimachinery/pkg/runtime.Object

// Infra is the Schema for the Infras API
type Infra struct {
	metav1.TypeMeta   `json:",inline"`
	metav1.ObjectMeta `json:"metadata,omitempty"`

	Spec   InfraSpec   `json:"spec,omitempty"`
	Status InfraStatus `json:"status,omitempty"`
}

// +kubebuilder:object:root=true
// +k8s:deepcopy-gen:interfaces=k8s.io/apimachinery/pkg/runtime.Object

// InfraList contains a list of Infra
type InfraList struct {
	metav1.TypeMeta `json:",inline"`
	metav1.ListMeta `json:"metadata,omitempty"`
	Items           []Infra `json:"items"`
}

repository: justadogistaken/sealos

license_type: permissive

repo_name: justadogistaken/sealos

branch_name: refs/heads/main

extension: go


text:
package main

import "fmt"

// Update getLikesAndShares to return two ints
func getLikesAndShares(postId int) (int, int) {
	var likesForPost, sharesForPost int
	switch postId {
	case 1:
		likesForPost = 5
		sharesForPost = 7
	case 2:
		likesForPost = 3
		sharesForPost = 11
	case 3:
		likesForPost = 22
		sharesForPost = 1
	case 4:
		likesForPost = 7
		sharesForPost = 9
	}
	fmt.Println("Likes: ", likesForPost, "Shares: ", sharesForPost)
	// Add in a return for likesForPost and sharesForPost
	return likesForPost, sharesForPost
}

func main() {
	var likes, shares int

	// Update this line so the results of the function
	// get stored in "likes" and "shares"
	likes, shares = getLikesAndShares(4)

	if likes > 5 {
		fmt.Println("Woohoo! We got some likes.")
	}
	if shares > 10 {
		fmt.Println("We went viral!")
	}
}

license: MIT

repository: bobrossrtx/learning-go

path: /Lesson 6 Functions/returning/post.go

repo_name: bobrossrtx/learning-go

branch_name: refs/heads/master


text:
package payment

import (
	"github.com/godcong/wego/core"
	"github.com/godcong/wego/util"
)

/*Security Security */
type Security struct {
	*Payment
}

func newSecurity(pay *Payment) interface{} {
	return &Security{
		Payment: pay,
	}
}

// NewSecurity ...
func NewSecurity(config *core.Config) *Security {
	return newSecurity(NewPayment(config)).(*Security)
}

/*GetPublicKey 获取RSA加密公钥API
接口说明
请求Url	https://fraud.mch.weixin.qq.com/risk/getpublickey
是否需要证书	请求需要双向证书。 详见证书使用
请求方式	POST

PS: 可使用ToFile保存Key.需转换成PKCS#8使用.
RSA公钥格式PKCS#1,PKCS#8互转说明
PKCS#1 转 PKCS#8:
openssl rsa -RSAPublicKey_in -in <filename> -pubout
PKCS#8 转 PKCS#1:
openssl rsa -pubin -in <filename> -RSAPublicKey_out
*/
func (s *Security) GetPublicKey() core.Responder {
	m := util.Map{"sign_type": "MD5"}
	maps := util.Map{
		core.DataTypeXML:      s.initRequest(m),
		core.DataTypeSecurity: s.Config,
	}
	return core.Request(riskGetPublicKey, core.POST, maps)
}

repository: flashytime/wego

repo_name: flashytime/wego

gha_license_id: MIT


text:
package subscriber

import (
	"fmt"
	"log"
	"saver/config"
	"saver/model"
	"saver/store/status"

	"github.com/nats-io/go-nats"
)

type Subscriber struct {
	Nats     *nats.EncodedConn
	NatsCfg  config.Nats
	Redis    status.Memory
	RedisCfg config.Redis
	Status   status.Status
}

func New(nc *nats.EncodedConn, natsCfg config.Nats, r status.Memory,
	redisCfg config.Redis, s status.Status) Subscriber {
	return Subscriber{
		Nats:     nc,
		NatsCfg:  natsCfg,
		Redis:    r,
		RedisCfg: redisCfg,
		Status:   s,
	}
}

func (s *Subscriber) Subscribe() {
	ch := make(chan model.Status)

	if _, err := s.Nats.QueueSubscribe(s.NatsCfg.Topic, s.NatsCfg.Queue, func(s model.Status) {
		ch <- s
	}); err != nil {
		log.Fatal(err)
	}

	s.worker(ch)
}

func (s *Subscriber) Publish(st model.Status) {
	err := s.Nats.Publish(s.NatsCfg.Topic, st)
	if err != nil {
		log.Fatal(err)
	}

	fmt.Println("In the checker and publish")
	fmt.Println(st)
}

func (s *Subscriber) worker(ch chan model.Status) {
	counter := 0

	for st := range ch {
		fmt.Println("In the saver")
		fmt.Println(st)
		s.Redis.Insert(st)
		counter++

		fmt.Println(counter)

		if counter == s.RedisCfg.Threshold {
			statuses := s.Redis.Flush()
			for i := 0; i < len(statuses); i++ {
				if err := s.Status.Insert(statuses[i]); err != nil {
					fmt.Println(err)
				}
			}

			fmt.Println("flush")

			counter = 0
		}
	}
}

repository: httpmon/saver

repo_name: httpmon/saver


text:
SUMMARY = "constant - Perl pragma to declare constants"
AUTHOR = "Sébastien Aperghis-Tramoni <saper@cpan.org>"
HOMEPAGE = "https://metacpan.org/module/constant"
SECTION = "libs"
LICENSE = "Artistic-1.0 | GPL-1.0+"
LIC_FILES_CHKSUM = "file://README;md5=e159cc1a0bf68494e422b174640580ae"

SRC_URI = "http://cpan.metacpan.org/authors/id/S/SA/SAPER/constant-${PV}.tar.gz"
SRC_URI[md5sum] = "1e00a4fbed2b98ae1f447848b132cdd0"
SRC_URI[sha256sum] = "744453124b07800d6fd6b901061892cbbcc134a316adbe0f1edfc5f89e04312b"

S = "${WORKDIR}/constant-${PV}"

inherit cpan

BBCLASSEXTEND = "native"

extension: bb