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@article{GeR2010,
	Author = {Rong Ge and Xizhou Feng and Shuaiwen Song and Hung-Ching Chang and Dong Li and Cameron, K.W.},
	Date-Added = {2010-09-29 17:29:05 -0500},
	Date-Modified = {2010-09-29 17:30:04 -0500},
	Doi = {10.1109/TPDS.2009.76},
	Issn = {1045-9219},
	Journal = {IEEE Transactions on Parallel and Distributed Systems},
	Keywords = {DVFS scheduling;PowerPack;dynamic voltage and frequency scaling techniques;energy consumption;energy efficiency;energy profiling;high-performance computing system design;multicore support systems;multiprocessor-based nodes;power efficiency;energy conservation;multiprocessing systems;parallel processing;power aware computing;power consumption;},
	Month = {may.},
	Number = {5},
	Pages = {658 -671},
	Title = {PowerPack: Energy Profiling and Analysis of High-Performance Systems and Applications},
	Volume = {21},
	Year = {2010},
	Bdsk-Url-1 = {http://dx.doi.org/10.1109/TPDS.2009.76}}

@article{GeR2007,
	Author = {Rong Ge and Xizhou Feng and Wu-chun Feng and Cameron, K.W.},
	Date-Added = {2010-09-29 17:02:34 -0500},
	Date-Modified = {2010-09-29 17:30:13 -0500},
	Doi = {10.1109/ICPP.2007.29},
	Issn = {0190-3918},
	Journal = {Proc. of the the 2007 Int'l Conf. on Parallel Processing},
	Keywords = {CPU MISER;cluster computing;dynamic voltage frequency scaling;high-end computing systems;performance-directed run-time system;power aware cluster;power management;runtime system;power aware computing;workstation clusters;},
	Month = {sep.},
	Pages = {18 -18},
	Title = {{CPU MISER}: A Performance-Directed, Run-Time System for Power-Aware Clusters},
	Year = {2007},
	Bdsk-Url-1 = {http://dx.doi.org/10.1109/ICPP.2007.29}}

@inproceedings{Liu2001,
	Address = {New York, NY, USA},
	Author = {Liu, Jinfeng and Chou, Pai H. and Bagherzadeh, Nader and Kurdahi, Fadi},
	Booktitle = {Proc. of the 38th annual Design Automation Conference},
	Date-Added = {2010-09-23 20:52:05 -0500},
	Date-Modified = {2010-09-23 20:52:32 -0500},
	Doi = {http://doi.acm.org/10.1145/378239.379076},
	Isbn = {1-58113-297-2},
	Location = {Las Vegas, Nevada, United States},
	Pages = {840--845},
	Publisher = {ACM},
	Title = {Power-aware scheduling under timing constraints for mission-critical embedded systems},
	Year = {2001},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/378239.379076}}

@article{Skadron2004,
	Address = {New York, NY, USA},
	Author = {Kevin Skadron and Mircea R. Stan and Karthik Sankaranarayanan and Wei Huang and Sivakumar Velusamy and David Tarjan},
	Date-Added = {2010-09-21 15:19:19 -0500},
	Date-Modified = {2010-09-21 15:19:19 -0500},
	Issn = {1544-3566},
	Journal = {{ACM Transactions on Architecture and Code Optimization}},
	Keywords = {background},
	Number = {1},
	Pages = {94--125},
	Publisher = {ACM},
	Title = {{Temperature-aware Microarchitecture: Modeling and Implementation}},
	Volume = {1},
	Year = {2004},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/980152.980157}}

@article{Aguiar2008,
	Author = {A Aguiar and J Sergio Filho and TG dos Santos and C Marcon and F Hessel},
	Date-Added = {2010-04-11 22:19:04 -0500},
	Date-Modified = {2010-09-20 12:39:33 -0500},
	Journal = {Proceedings of the 2008 Brazilian Workshop on Operating Systems},
	Pages = {169},
	Rating = {0},
	Title = {Architectural Support for Task Migration Concerning MPSoC},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p158},
	Year = {2008}}

@article{Albers2007a,
	Affiliation = {New York, NY, USA},
	Author = {Susanne Albers and Hiroshi Fujiwara},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 15:21:29 -0500},
	Journal = {ACM Transactions on Algorithms},
	Number = {4},
	Pages = {49},
	Rating = {0},
	Title = {Energy-efficient algorithms for flow time minimization},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p169},
	Url = {http://doi.acm.org/10.1145/1290672.1290686},
	Volume = {3},
	Year = {2007},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1290672.1290686}}

@article{Albers2007b,
	Affiliation = {New York, NY, USA},
	Author = {Susanne Albers and Fabian M{\"u}ller and Swen Schmelzer},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 15:22:48 -0500},
	Doi = {http://doi.acm.org/10.1145/1248377.1248424},
	Journal = {Proceedings of the 19th ACM Symposium on Parallel Algorithms and Architectures},
	Pages = {289--298},
	Rating = {0},
	Title = {Speed scaling on parallel processors},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p120},
	Url = {http://doi.acm.org/10.1145/1248377.1248424},
	Year = {2007},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1248377.1248424}}

@article{Ayoub2009,
	Affiliation = {New York, NY, USA},
	Author = {Raid Zuhair Ayoub and Tajana Simunic Rosing},
	Date-Added = {2010-04-11 22:19:03 -0500},
	Date-Modified = {2010-09-18 15:24:06 -0500},
	Doi = {http://doi.acm.org/10.1145/1594233.1594256},
	Journal = {Proceedings of the 14th ACM/IEEE Int'l Symp. on Low Power Electronics and Design},
	Pages = {99--104},
	Rating = {0},
	Title = {Predict and act: dynamic thermal management for multi-core processors},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p125},
	Url = {http://doi.acm.org/10.1145/1594233.1594256},
	Year = {2009},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1594233.1594256}}

@inproceedings{Azimi2005,
	Address = {New York, NY, USA},
	Author = {Reza Azimi and Michael Stumm and Robert W. Wisniewski},
	Booktitle = {{ICS '05: Proceedings of the 19th Annual Intl. Conf. on Supercomputing}},
	Date-Added = {2010-02-13 21:47:47 -0600},
	Date-Modified = {2010-02-13 21:47:47 -0600},
	Isbn = {1-59593-167-8},
	Location = {Cambridge, Massachusetts},
	Pages = {101--110},
	Publisher = {ACM},
	Title = {{Online Performance Analysis by Statistical Sampling of Microprocessor Performance Counters}},
	Year = {2005},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1088149.1088163}}

@article{Banikazemi2008,
	Affiliation = {Piscataway, NJ, USA},
	Author = {Mohammad Banikazemi and Dan Poff and Bulent Abali},
	Date-Added = {2010-04-11 22:19:03 -0500},
	Date-Modified = {2010-09-18 15:25:10 -0500},
	Doi = {http://doi.acm.org/10.1145/1413370.1413410},
	Journal = {Proceedings of the 2008 ACM/IEEE Conf. on Supercomputing},
	Pages = {1--12},
	Rating = {0},
	Title = {{PAM}: a novel performance/power aware meta-scheduler for multi-core systems},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p168},
	Url = {http://doi.acm.org/10.1145/1413370.1413410},
	Year = {2008},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1413370.1413410}}

@article{Bao2008,
	Affiliation = {ACM},
	Author = {M Bao and A Andrei and P Eles and Z Peng},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 15:26:22 -0500},
	Journal = {Proceedings of the ACM Conf. on Design, Automation and Test in Europe},
	Pages = {1083--1086},
	Rating = {0},
	Title = {Temperature-aware voltage selection for energy optimization},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p135},
	Year = {2008}}

@article{Bellosa2003,
	Author = {Bellosa, F. and Weissel, A. and Waitz, M. and Kellner, S.},
	Date-Added = {2010-02-13 21:44:41 -0600},
	Date-Modified = {2010-02-13 21:44:41 -0600},
	Journal = {{Proceedings of the Workshop on Compilers and Operating Systems for Low Power (COLP'03)}},
	Title = {{Event-driven energy accounting for dynamic thermal management}},
	Year = {2003}}

@article{Bergamaschi2008,
	Author = {R Bergamaschi and Guoling Han and A Buyuktosunoglu and H Patel and I Nair and G Dittmann and G Janssen and N Dhanwada and Zhigang Hu and P Bose and J Darringer},
	Date-Added = {2010-04-11 22:19:04 -0500},
	Date-Modified = {2010-09-18 15:27:28 -0500},
	Doi = {10.1109/ASPDAC.2008.4484043},
	Journal = {Proceedings of the 2008 Design Automation Conf., Asia and South Pacific},
	Keywords = {power management, nonlinear programmingcontinuous power modes, simulation model, nonlinear programming, integrated circuit modelling, microprocessor chips, power analysis methodology, multi-core systems},
	Month = {Mar},
	Pages = {708--713},
	Rating = {0},
	Title = {Exploring power management in multi-core systems},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p128},
	Url = {http://dx.doi.org/10.1109/ASPDAC.2008.4484043},
	Year = {2008},
	Bdsk-Url-1 = {http://dx.doi.org/10.1109/ASPDAC.2008.4484043}}

@article{Bircher2007,
	Address = {Los Alamitos, CA, USA},
	Author = {W.L. Bircher and L.K. John},
	Date-Added = {2010-02-13 21:44:05 -0600},
	Date-Modified = {2010-02-13 21:44:05 -0600},
	Isbn = {1-4244-1081-9},
	Journal = {Ispass},
	Pages = {158-168},
	Publisher = {IEEE Computer Society},
	Title = {{Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events}},
	Volume = {0},
	Year = {2007},
	Bdsk-Url-1 = {http://doi.ieeecomputersociety.org/10.1109/ISPASS.2007.363746}}

@inproceedings{Bircher2008,
	Address = {New York, NY, USA},
	Author = {Bircher,, W. Lloyd and John,, Lizy K.},
	Booktitle = {ICS '08: Proceedings of the 22nd annual international conference on Supercomputing},
	Date-Added = {2010-02-13 21:49:12 -0600},
	Date-Modified = {2010-02-13 21:49:12 -0600},
	Doi = {http://doi.acm.org/10.1145/1375527.1375575},
	Isbn = {978-1-60558-158-3},
	Location = {Island of Kos, Greece},
	Pages = {327--338},
	Publisher = {ACM},
	Title = {Analysis of dynamic power management on multi-core processors},
	Year = {2008},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1375527.1375575}}

@article{Bunde2009,
	Affiliation = {Knox College Department of Computer Science Galesburh USA},
	Author = {Bunde, David},
	Date-Added = {2010-09-18 15:30:47 -0500},
	Date-Modified = {2010-09-18 15:30:47 -0500},
	Issn = {1094-6136},
	Issue = {5},
	Journal = {Journal of Scheduling},
	Keyword = {Computer Science},
	Note = {10.1007/s10951-009-0123-y},
	Pages = {489-500},
	Publisher = {Springer Netherlands},
	Title = {Power-aware scheduling for makespan and flow},
	Url = {http://dx.doi.org/10.1007/s10951-009-0123-y},
	Volume = {12},
	Year = {2009},
	Bdsk-Url-1 = {http://dx.doi.org/10.1007/s10951-009-0123-y}}

@article{Bunde2006,
	Affiliation = {New York, NY, USA},
	Author = {David P Bunde},
	Date-Added = {2010-04-11 22:19:03 -0500},
	Date-Modified = {2010-09-18 15:28:37 -0500},
	Doi = {http://doi.acm.org/10.1145/1148109.1148140},
	Journal = {Proceedings of the 18th ACM Symp. on Parallelism in Algorithms and Architecture},
	Pages = {190--196},
	Rating = {0},
	Title = {Power-aware scheduling for makespan and flow},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p136},
	Url = {http://doi.acm.org/10.1145/1148109.1148140},
	Year = {2006},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1148109.1148140}}

@article{Chaparro2004,
	Author = {P Chaparro and J Gonzalez},
	Date-Added = {2010-09-17 15:36:44 -0500},
	Date-Modified = {2010-09-18 18:43:52 -0500},
	Journal = {Proceedings of the 2004 IEEE Int'l. Conf. on Computer Design: VLSI in Computers and Processors},
	Month = {Jan},
	Pmid = {15122325351206814877related:nQSREMlK3dEJ},
	Rating = {0},
	Title = {Thermal-aware clustered microarchitectures},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p920},
	Url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1347897},
	Year = {2004},
	Abstract = { Moreover, the steering unit must be aware the gating and try to reduce
	the slowdown combining -aware and - policies. 83-94, 2000 [5] D.
	Brooks and M. Martonosi. ``Dynamic for High-Performance Microprocessors''.
	Proc. },
	Bdsk-Url-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1347897}}

@article{Choi2007,
	Affiliation = {New York, NY, USA},
	Author = {Jeonghwan Choi and Chen-Yong Cher and Hubertus Franke and Henrdrik Hamann and Alan Weger and Pradip Bose},
	Date-Added = {2010-04-11 22:19:04 -0500},
	Date-Modified = {2010-09-18 15:50:27 -0500},
	Doi = {http://doi.acm.org/10.1145/1283780.1283826},
	Journal = {Proceedings of the ACM Int'l Symp. on Low Power Electronics and Design},
	Pages = {213--218},
	Rating = {0},
	Title = {Thermal-aware task scheduling at the system software level},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p114},
	Url = {http://doi.acm.org/10.1145/1283780.1283826},
	Year = {2007},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1283780.1283826}}

@article{Choi2008,
	Author = {J Choi and S Govindan and B Urgaonkar and A Sivasubramaniam},
	Date-Added = {2010-04-11 22:19:04 -0500},
	Date-Modified = {2010-09-18 15:49:33 -0500},
	Journal = {Proc. of the 2008 IEEE Int'l Symp. on Modeling, Analysis, and Simulation of Computers and Telecommunication Systems},
	Pages = {150},
	Rating = {0},
	Title = {Profiling, Prediction, and Capping of Power Consumption in Consolidated Environments},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p119},
	Volume = {100},
	Year = {2008}}

@article{Chrobak2008,
	Author = {M Chrobak and C Durr and M Hurand and J Robert},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 15:52:43 -0500},
	Doi = {10.1007/978-3-540-68880-8_13},
	Journal = {Lecture Notes in Computer Science},
	Rating = {0},
	Title = {Algorithms for Temperature-Aware Task Scheduling in Microprocessor Systems},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p171},
	Volume = {5034/2008},
	Year = {2008},
	Bdsk-Url-1 = {http://dx.doi.org/10.1007/978-3-540-68880-8_13}}

@inproceedings{Contreras2005,
	Address = {New York, NY, USA},
	Author = {Gilberto Contreras and Margaret Martonosi},
	Booktitle = {{ISLPED '05: Proc. of the 2005 Intl. Symp. on Low Power Electronics and Design}},
	Date-Added = {2010-02-13 21:49:26 -0600},
	Date-Modified = {2010-02-13 21:49:26 -0600},
	Isbn = {1-59593-137-6},
	Location = {San Diego, CA, USA},
	Pages = {221--226},
	Publisher = {ACM},
	Title = {{Power Prediction for Intel XScale\textregistered Processors Using Performance Monitoring Unit Events}},
	Year = {2005},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1077603.1077657}}

@manual{Yokogawa2009,
	Author = {Yokogawa Electric Corporation},
	Date-Added = {2010-02-13 21:48:23 -0600},
	Date-Modified = {2010-02-13 21:48:23 -0600},
	Edition = {4th ed.},
	Organization = {Yokogawa Electric Corporation},
	Title = {{WT210/WT230 Digital Power Meter User's Manual}}}

@phdthesis{Coskun2009a,
	Affiliation = {UNIVERSITY OF CALIFORNIA, SAN DIEGO},
	Author = {AK Coskun},
	Date-Added = {2010-04-11 22:19:03 -0500},
	Date-Modified = {2010-04-26 15:58:35 -0500},
	Journal = {PhD Thesis},
	Rating = {0},
	Title = {Efficient Thermal Management for Multiprocessor Systems},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p127},
	Url = {http://seelab.ucsd.edu/papers/thesis/acoskun_thesis09.pdf},
	Year = {2009},
	Bdsk-Url-1 = {http://seelab.ucsd.edu/papers/thesis/acoskun_thesis09.pdf}}

@article{Coskun2008b,
	Author = {AK Coskun and TS Rosing and KC Gross},
	Date-Added = {2010-04-11 22:19:04 -0500},
	Date-Modified = {2010-09-18 15:56:15 -0500},
	Journal = {Proc. of the 2008 IEEE Int'l Conf. on Computer-Aided Design},
	Pages = {250--257},
	Rating = {0},
	Title = {Proactive Temperature Balancing for Low Cost Thermal Management in MPSoCs},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p138},
	Url = {http://seelab.ucsd.edu/papers/acoskun_iccad08.pdf},
	Year = {2008},
	Bdsk-Url-1 = {http://seelab.ucsd.edu/papers/acoskun_iccad08.pdf}}

@article{Coskun2008c,
	Author = {AK Coskun and TS Rosing and KC Gross},
	Date-Added = {2010-04-11 22:19:04 -0500},
	Date-Modified = {2010-09-18 15:56:56 -0500},
	Journal = {Proc. of the 45th ACM/IEEE Design Automation Conference},
	Keywords = {electronic engineering education, multiprocessing systems, thermal cycles, temperature management, distance learning, thermal management (packaging)expert policies, multiprocessor SoCs, system-on-chip, thermal hot spots, multicore systems, spatial gradients, temperature gradients, online learning},
	Month = {Jun},
	Pages = {890--893},
	Rating = {0},
	Title = {Temperature management in multiprocessor SoCs using online learning},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p130},
	Year = {2008},
	Abstract = {In deep submicron circuits, thermal hot spots and high temperature
	gradients increase the cooling costs, and degrade reliability and
	performance. In this paper, we propose a low-cost temperature management
	strategy for multicore systems to reduce the adverse effects of hot
	spots and temperature variations. Our technique utilizes online learning
	to select the best policy for the current workload characteristics
	among a given set of expert policies. We achieve 20% and 60% average
	decrease in the frequency of hot spots and thermal cycles respectively
	in comparison to the best performing expert, and reduce the spatial
	gradients to below 5%.}}

@article{Coskun2008e,
	Author = {A Coskun and T Rosing and K Gross},
	Date-Added = {2010-09-17 15:36:44 -0500},
	Date-Modified = {2010-09-18 15:58:27 -0500},
	Journal = {Proceeding of the 13th Int'l. Symp. on Low Power Electronics and Design},
	Month = {Jan},
	Pmid = {18401073947449348229related:hdBpG0O_Xf8J},
	Rating = {0},
	Title = {Proactive temperature management in MPSoCs},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p894},
	Url = {http://portal.acm.org/citation.cfm?id=1393966},
	Year = {2008},
	Abstract = { - Balancing Combined With Reactive : One way to perform temperature-aware
	allocation is to initially utilize - balancing while dispatching
	jobs, then at runtime migrate threads from cores that reach a critical
	threshold. },
	Bdsk-Url-1 = {http://portal.acm.org/citation.cfm?id=1393966}}

@article{Coskun2007,
	Author = {AK Coskun and TS Rosing and K Whisnant},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 15:53:53 -0500},
	Journal = {Proc. of the 2007 Design, Automation \& Test in Europe Conference \& Exhibition},
	Keywords = {multiprocessing systems, reactive strategies, state-of-art schedulers, temperature aware, system-on-chipMPSoC, temperature measurements, dynamic scheduling, processor scheduling, dynamic thread migration, multiprocessor systems on a chip, scheduling policies, deep submicron circuits, dynamic scheduling, task scheduling},
	Local-Url = {file://localhost/Users/awl8049/Dropbox/coursework/Papers/2007/Coskun/Design%20Automation%20%20&%20Test%20in%20Europe%20Conference%20%20&%20Exhibition%202007.%20DATE%20'07%202007%20Coskun.pdf},
	Month = {Apr},
	Pages = {1--6},
	Rating = {0},
	Title = {Temperature Aware Task Scheduling in {MPSoCs}},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p123},
	Url = {http://dx.doi.org/10.1109/DATE.2007.364540},
	Year = {2007},
	Abstract = {In deep submicron circuits, elevation in temperatures has brought
	new challenges in reliability, timing, performance, cooling costs
	and leakage power. Conventional thermal management techniques sacrifice
	performance to control the thermal behavior by slowing down or turning
	off the processors when a critical temperature threshold is exceeded.
	Moreover, studies have shown that in addition to high temperatures,
	temporal and spatial variations in temperature impact system reliability.
	In this work, we explore the benefits of thermally aware task scheduling
	for multiprocessor systems-on-a-chip (MPSoC). We design and evaluate
	OS-level dynamic scheduling policies with negligible performance
	overhead. We show that, using simple to implement policies that make
	decisions based on temperature measurements, better temporal and
	spatial thermal profiles can be achieved in comparison to state-of-art
	schedulers. We also enhance reactive strategies such as dynamic thread
	migration with our scheduling policies. This way, hot spots and temperature
	variations are decreased, and the performance cost is significantly
	reduced},
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	Bdsk-Url-1 = {http://dx.doi.org/10.1109/DATE.2007.364540}}

@article{Coskun2008a,
	Affiliation = {Los Alamitos, CA, USA},
	Author = {Ayse Kivilcim Coskun and Tajana Simunic Rosing and Keith A Whisnant and Kenny C Gross},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 15:55:19 -0500},
	Journal = {Proc. of the 2008 Asia and South Pacific Design Automation Conference},
	Pages = {49--54},
	Rating = {0},
	Title = {Temperature-aware MPSoC scheduling for reducing hot spots and gradients},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p170},
	Year = {2008}}

@article{Coskun2008d,
	Affiliation = {Piscataway, NJ, USA},
	Author = {Ayse Kivilcim Coskun and Tajana Simunic Rosing and Keith A Whisnant and Kenny C Gross},
	Date-Added = {2010-04-11 22:19:03 -0500},
	Date-Modified = {2010-09-18 15:57:27 -0500},
	Doi = {http://dx.doi.org/10.1109/TVLSI.2008.2000726},
	Journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
	Local-Url = {file://localhost/Users/awl8049/Dropbox/coursework/Papers/2008/Coskun/IEEE%20Transactions%20on%20Very%20Large%20Scale%20Integration%20(VLSI)%20Systems%202008%20Coskun.pdf},
	Number = {9},
	Pages = {1127--1140},
	Rating = {0},
	Title = {Static and dynamic temperature-aware scheduling for multiprocessor {SoCs}},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p126},
	Url = {http://dx.doi.org/10.1109/TVLSI.2008.2000726},
	Volume = {16},
	Year = {2008},
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	Bdsk-Url-1 = {http://dx.doi.org/10.1109/TVLSI.2008.2000726}}

@article{Coskun2009b,
	Affiliation = {New York, NY, USA},
	Author = {Ayse K Coskun and Richard Strong and Dean M Tullsen and Tajana Simunic Rosing},
	Date-Added = {2010-04-11 22:19:03 -0500},
	Date-Modified = {2010-09-18 15:59:51 -0500},
	Doi = {http://doi.acm.org/10.1145/1555349.1555369},
	Journal = {Proceedings of the 11th Int'l Joint Conf. on Measurement and Modeling of Computer Systems},
	Local-Url = {file://localhost/Users/awl8049/Dropbox/coursework/Papers/2009/Coskun/Proceedings%202009%20Coskun.pdf},
	Pages = {169--180},
	Rating = {0},
	Title = {Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p121},
	Url = {http://doi.acm.org/10.1145/1555349.1555369},
	Year = {2009},
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	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1555349.1555369}}

@inproceedings{Diniz2007,
	Address = {New York, NY, USA},
	Author = {Diniz,, Bruno and Guedes,, Dorgival and Meira,Jr., Wagner and Bianchini,, Ricardo},
	Booktitle = {ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture},
	Date-Added = {2009-04-07 21:30:47 -0500},
	Date-Modified = {2009-04-07 21:31:01 -0500},
	Doi = {http://doi.acm.org/10.1145/1250662.1250699},
	Isbn = {978-1-59593-706-3},
	Location = {San Diego, California, USA},
	Pages = {290--301},
	Publisher = {ACM},
	Title = {Limiting the power consumption of main memory},
	Year = {2007},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1250662.1250699}}

@inproceedings{Donald2006,
	Address = {Washington, DC, USA},
	Author = {James Donald and Margaret Martonosi},
	Booktitle = {{ISCA '06: Proc. of the 33rd Intl. Symp. on Computer Architecture}},
	Date-Added = {2009-01-31 15:01:13 -0600},
	Date-Modified = {2009-01-31 15:01:13 -0600},
	Isbn = {0-7695-2608-X},
	Keywords = {background},
	Pages = {78--88},
	Publisher = {IEEE Computer Society},
	Title = {{Techniques for Multicore Thermal Management: Classification and New Exploration}},
	Year = {2006},
	Bdsk-Url-1 = {http://dx.doi.org/10.1109/ISCA.2006.39}}

@inproceedings{Economou2006,
	Author = {Economou, D. and Rivoire, S. and Kozyrakis, C. and Ranganathan, P.},
	Booktitle = {Workshop on Modeling Benchmarking and Simulation (MOBS) at ISCA},
	Date-Added = {2010-02-13 21:49:21 -0600},
	Date-Modified = {2010-02-13 21:49:21 -0600},
	Keywords = {SystemMetrics},
	Title = {{Full-System Power Analysis and Modeling for Server Environments}},
	Year = {2006},
	Bdsk-Url-1 = {http://csl.stanford.edu/~christos/publications/2006.mantis.mobs.pdf}}

@inproceedings{Fan2007,
	Address = {New York, NY, USA},
	Author = {Xiaobo Fan and Wolf-Dietrich Weber and Luiz Andre Barroso},
	Booktitle = {ISCA '07: Proc. of the 34th Intl. Symp. on Computer architecture},
	Date-Added = {2010-02-13 21:46:34 -0600},
	Date-Modified = {2010-02-13 21:46:34 -0600},
	Isbn = {978-1-59593-706-3},
	Keywords = {SystemMetrics},
	Location = {San Diego, California, USA},
	Pages = {13--23},
	Publisher = {ACM},
	Title = {Power Provisioning for a Warehouse-sized Computer},
	Year = {2007},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1250662.1250665}}

@techreport{Fedorova2008,
	Author = {A Fedorova and M Seltzer and MD Smith},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 16:01:01 -0500},
	Institution = {Harvard University},
	Number = {TR-17-06},
	Rating = {0},
	Title = {Cache-fair thread scheduling for multi-core processors},
	Type = {Techical Report},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p151},
	Url = {http://www.eecs.harvard.edu/~fedorova/papers/osdi-2006-submission.pdf},
	Year = {2006},
	Bdsk-Url-1 = {http://www.eecs.harvard.edu/~fedorova/papers/osdi-2006-submission.pdf}}

@article{Freeh2007,
	Author = {VW Freeh and TK Bletsch and FL Rawson},
	Date-Added = {2010-04-11 22:19:04 -0500},
	Date-Modified = {2010-09-18 18:17:05 -0500},
	Journal = {Proceedings of the 2007 IEEE Int'l Symp. on Parallel and Distributed Processing},
	Rating = {0},
	Title = {Scaling and packing on a chip multiprocessor},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p147},
	Year = {2007}}

@article{GeY2010,
	Author = {Y Ge and P Malani and Q Qiu},
	Date-Added = {2010-09-17 16:22:06 -0500},
	Date-Modified = {2010-09-29 17:30:27 -0500},
	Journal = {Proceedings of the 47th ACM/IEEE Design Automation Conference},
	Local-Url = {file://localhost/Users/awl8049/Dropbox/coursework/Papers/2010/Ge/Proceedings%20of%20the%2047th%20Design%20Automation%20%E2%80%A6%202010%20Ge.pdf},
	Month = {Jan},
	Rating = {0},
	Title = {Distributed task migration for thermal management in many-core systems},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p964},
	Url = {http://portal.acm.org/citation.cfm?id=1837417},
	Year = {2010},
	Abstract = { After task migration finishes, we employ a simple technique to the
	execution of tasks on their average power consumption for both master
	and slave PEs. The aware will execute hot and cool tasks alternatively
	starting from the coolest },
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	Bdsk-Url-1 = {http://portal.acm.org/citation.cfm?id=1837417}}

@article{Gomaa2004,
	Address = {New York, NY, USA},
	Author = {Gomaa, Mohamed and Powell, Michael D. and Vijaykumar, T. N.},
	Date-Added = {2010-02-13 21:44:24 -0600},
	Date-Modified = {2010-02-13 21:44:24 -0600},
	Doi = {http://doi.acm.org/10.1145/1037949.1024424},
	Issn = {0163-5980},
	Journal = {SIGOPS Oper. Syst. Rev.},
	Number = {5},
	Pages = {260--270},
	Publisher = {ACM},
	Title = {Heat-and-run: leveraging SMT and CMP to manage power density through the operating system},
	Volume = {38},
	Year = {2004},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1037949.1024424}}

@article{Goraczko2008,
	Affiliation = {New York, NY, USA},
	Author = {Michel Goraczko and Jie Liu and Dimitrios Lymberopoulos and Slobodan Matic and Bodhi Priyantha and Feng Zhao},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 18:18:37 -0500},
	Journal = {Proceedings of the 45th ACM/IEEE Design Automation Conference},
	Pages = {191--196},
	Rating = {0},
	Title = {Energy-optimal software partitioning in heterogeneous multiprocessor embedded systems},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p150},
	Url = {http://doi.acm.org/10.1145/1391469.1391518},
	Year = {2008},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1391469.1391518}}

@inproceedings{Heath2005,
	Address = {New York, NY, USA},
	Author = {Taliver Heath and Bruno Diniz and Enrique V. Carrera and Wagner Meira Jr. and Ricardo Bianchini},
	Booktitle = {{PPoPP '05: Proc. of the 10th ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming}},
	Date-Added = {2010-02-13 21:46:44 -0600},
	Date-Modified = {2010-02-13 21:46:44 -0600},
	Doi = {http://doi.acm.org/10.1145/1065944.1065969},
	Isbn = {1-59593-080-9},
	Location = {Chicago, IL, USA},
	Pages = {186--195},
	Publisher = {ACM},
	Title = {{Energy Conservation in Heterogeneous Server Clusters}},
	Year = {2005},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1065944.1065969}}

@article{Henning2006,
	Address = {New York, NY, USA},
	Author = {John L. Henning},
	Date-Added = {2010-02-13 21:48:16 -0600},
	Date-Modified = {2010-02-13 21:48:16 -0600},
	Doi = {http://doi.acm.org/10.1145/1186736.1186737},
	Issn = {0163-5964},
	Journal = {SIGARCH Comp. Archit. News},
	Number = {4},
	Pages = {1--17},
	Publisher = {ACM},
	Title = {{SPEC CPU2006 Benchmark Descriptions}},
	Volume = {34},
	Year = {2006},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1186736.1186737}}

@article{Hikita2008,
	Author = {J Hikita and A Hirano and H Nakashima},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-04-26 15:58:35 -0500},
	Journal = {Proc. of the 2008 IEEE Int'l Symp. on Parallel and Distributed Processing},
	Keywords = {power consumption, electric charge, power engineering computing10 TFlops, job shop scheduling, power aware operations, parallel machines, job/machine scheduling, Kyoto University supercomputer system, electric charge},
	Month = {Apr},
	Pages = {1--8},
	Rating = {0},
	Title = {Saving 200kW and {\$}200 K/year by power-aware job/machine scheduling},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p142},
	Url = {http://dx.doi.org/10.1109/IPDPS.2008.4536218},
	Year = {2008},
	Abstract = {This paper reports our 3.75-year empirical study on power-aware operations
	of Kyoto University's supercomputer system. The supercomputer system
	of 10 TFlops had required about 540 kW on average in its first fiscal
	year 2004. After that and one-year try-and-error of power efficient
	operation, we implemented a simple but effective scheduler of jobs
	and machine powering to improve the per- load power efficiency by
	up to 39 % and to save 200 kW and {\$}200,000 electric charge in
	the fiscal year 2006. The power-aware scheduler tries to minimize
	the number of active nodes in the system of eleven nodes keeping
	sufficient computational power for given loads. Thus the power- aware
	scheduler has not degraded, but has significantly improved, the service
	quality in terms of the average job- waiting time.},
	Bdsk-Url-1 = {http://dx.doi.org/10.1109/IPDPS.2008.4536218}}

@article{Isci2003b,
	Author = {Isci, C. and Martonosi, M.},
	Date-Added = {2010-02-13 21:46:03 -0600},
	Date-Modified = {2010-02-13 21:46:03 -0600},
	Journal = {{MICRO-36: Proc. 36th IEEE/ACM Intl. Symp. on Microarchitecture}},
	Keywords = {microprocessor chips, performance evaluation, power measurement CPU subunits, Intel Pentium 4 processors, SPEC2000, component power breakdowns, computer systems, coordinated measurement, desktop workload execution, dynamic power management, estimation methodology, hardware system, high-end processors, live power measurements, per-unit power estimation, performance-counter-based power estimation, power dissipation, power-aware research, processor power measurement, program power phase behaviour, runtime power monitoring, software system, thermal analysis},
	Pages = {93-104},
	Title = {{Runtime Power Monitoring in High-end Processors: Methodology and Empirical Data}},
	Year = {3-5 Dec. 2003},
	Abstract = { With power dissipation becoming an increasingly vexing problem across
	many classes of computer systems, measuring power dissipation of
	real, running systems has become crucial for hardware and software
	system research and design. Live power measurements are imperative
	for studies requiring execution times too long for simulation, such
	as thermal analysis. Furthermore, as processors become more complex
	and include a host of aggressive dynamic power management techniques,
	per-component estimates of power dissipation have become both more
	challenging as well as more important. In this paper we describe
	our technique for a coordinated measurement approach that combines
	real total power measurement with performance-counter-based, per-unit
	power estimation. The resulting tool offers live total power measurements
	for Intel Pentium 4 processors, and also provides power breakdowns
	for 22 of the major CPU subunits over minutes of SPEC2000 and desktop
	workload execution. As an example application, we use the generated
	component power breakdowns to identify program power phase behaviour.
	Overall, this paper demonstrates a processor power measurement and
	estimation methodology and also gives experiences and empirical application
	results that can provide a basis for future power-aware research.},
	Bdsk-Url-1 = {http://dx.doi.org/10.1109/MICRO.2003.1253186}}

@article{Isci2006,
	Author = {Isci, C. and Martonosi, M.},
	Date-Added = {2010-02-13 21:45:58 -0600},
	Date-Modified = {2010-02-13 21:45:58 -0600},
	Issn = {1530-0897},
	Journal = {{The 12th Intl. Symp. on High-Performance Computer Architecture}},
	Keywords = {benchmark testing, computer architecture, performance evaluation, power consumption SPEC2000 benchmark, basic block vector, code-oriented technique, control-flow sampling, event counter, mainstream desktop application, performance counter, power consumption, power phase characterization, real-system power measurement},
	Pages = {121-132},
	Title = {{Phase Characterization for Power: Evaluating Control-flow-based and Event-counter-based Techniques}},
	Year = {11-15 Feb. 2006},
	Abstract = { Computer systems increasingly rely on dynamic, phase-based system
	management techniques, in which system hardware and software parameters
	may be altered or tuned at runtime for different program phases.
	Prior research has considered a range of possible phase analysis
	techniques, but has focused almost exclusively on performance-oriented
	phases; the notion of power-oriented phases has not been explored.
	Moreover, the bulk of phase-analysis studies have focused on simulation
	evaluation. There is need for real-system experiments that provide
	direct comparison of different practical techniques (such as control
	flow sampling, event counters, and power measurements) for gauging
	phase behavior. In this paper, we propose and evaluate a live, real-system
	measurement framework for collecting and analyzing power phases in
	running applications. Our experimental frameworks simultaneously
	collects control flow, performance counter and live power measurement
	information. Using this framework, we directly compare between code-oriented
	techniques (such as "basic block vectors") and performance counter
	techniques for characterizing power phases. Across a collection of
	both SPEC2000 benchmarks as well as mainstream desktop applications,
	our results indicate that both techniques are promising, but that
	performance counters consistently provide better representation of
	power behavior. For many of the experimented cases, basic block vectors
	demonstrate a strong relationship between the execution path and
	power consumption. However, there are instances where power behavior
	cannot be captured from control flow, for example due to differences
	in memory hierarchy performance. We demonstrate these with examples
	from real applications. Overall, counter-based techniques offer average
	classification errors of 1.9% for SPEC and 7.1% for other benchmarks,
	while basic block vectors achieve 2.9% average errors for SPEC and
	11.7% for other benchmarks respectively.},
	Bdsk-Url-1 = {http://dx.doi.org/10.1109/HPCA.2006.1598119}}

@article{Jayaseelan2009,
	Affiliation = {New York, NY, USA},
	Author = {Ramkumar Jayaseelan and Tulika Mitra},
	Date-Added = {2010-04-11 22:19:03 -0500},
	Date-Modified = {2010-09-18 18:20:01 -0500},
	Doi = {http://doi.acm.org/10.1145/1629911.1630038},
	Journal = {Proceedings of the 46th ACM/IEEE Design Automation Conference},
	Pages = {484--489},
	Rating = {0},
	Title = {Dynamic thermal management via architectural adaptation},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p115},
	Url = {http://doi.acm.org/10.1145/1629911.1630038},
	Year = {2009},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1629911.1630038}}

@article{Jayaseelan2008,
	Author = {R Jayaseelan and T Mitra},
	Date-Added = {2010-04-11 22:19:03 -0500},
	Date-Modified = {2010-09-18 18:19:27 -0500},
	Doi = {10.1109/ICCAD.2008.4681641},
	Journal = {Proc. of the 2008 IEEE Int'l Conf. on Computer-Aided Design},
	Keywords = {voltage scaling, thermal management (packaging)on-chip power density, temperature aware task sequencing, power aware computing},
	Month = {Nov},
	Pages = {618--623},
	Rating = {0},
	Title = {Temperature aware task sequencing and voltage scaling},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p144},
	Url = {http://dx.doi.org/10.1109/ICCAD.2008.4681641},
	Year = {2008},
	Bdsk-Url-1 = {http://dx.doi.org/10.1109/ICCAD.2008.4681641}}

@article{Jimenez2010,
	Author = {V Jim{\'e}nez and F Cazorla and R Gioiosa and M Valero},
	Date-Added = {2010-09-17 16:22:05 -0500},
	Date-Modified = {2010-09-18 18:20:42 -0500},
	Journal = {Proceedings of the 19th Int'l Conf. on Parallel Architectures and Compilation Techniques},
	Local-Url = {file://localhost/Users/awl8049/Dropbox/coursework/Papers/2010/Jim%C3%A9nez/Proceedings%20of%20the%20%E2%80%A6%202010%20Jim%C3%A9nez.pdf},
	Month = {Jan},
	Rating = {0},
	Title = {Power and thermal characterization of POWER6 system},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p936},
	Url = {http://portal.acm.org/citation.cfm?id=1854281},
	Year = {2010},
	Abstract = { OS level: We explore the effectiveness of power and management techniques
	present in modern OS for To the best of our knowledge, this is the
	first model for real CMP/SMT processor- . * OS : A JS22 includes
	two POWER6 chips },
	Bdsk-File-1 = {YnBsaXN0MDDUAQIDBAUIJidUJHRvcFgkb2JqZWN0c1gkdmVyc2lvblkkYXJjaGl2ZXLRBgdUcm9vdIABqAkKFRYXGyIjVSRudWxs0wsMDQ4RFFpOUy5vYmplY3RzV05TLmtleXNWJGNsYXNzog8QgASABqISE4ACgAOAB1lhbGlhc0RhdGFccmVsYXRpdmVQYXRo0hgNGRpXTlMuZGF0YU8RAhwAAAAAAhwAAgAABURhdGEyAAAAAAAAAAAAAAAAAAAAAAAAAAAAAMgF58lIKwAAAA+KQh9Qcm9jZWVkaW5ncyBvZiB0aGUgySAjRjhBNDMucGRmAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAD4pDyLlH5wAAAAAAAAAAAAQABQAACQAAAAAAAAAAAAAAAAAAAAAHSmltjm5legAAEAAIAADIBi4ZAAAAEQAIAADIuY43AAAAAQAcAA+KQgAAXzcAAF8OAABfDAAAXtQAAABaAAAAVwACAFpEYXRhMjpVc2Vyczphd2w4MDQ5OkRyb3Bib3g6Y291cnNld29yazpQYXBlcnM6MjAxMDpKaW2ObmV6OlByb2NlZWRpbmdzIG9mIHRoZSDJICNGOEE0My5wZGYADgBOACYAUAByAG8AYwBlAGUAZABpAG4AZwBzACAAbwBmACAAdABoAGUAICAmACAAMgAwADEAMAAgAEoAaQBtAGUDAQBuAGUAegAuAHAAZABmAA8ADAAFAEQAYQB0AGEAMgASAGEvVXNlcnMvYXdsODA0OS9Ecm9wYm94L2NvdXJzZXdvcmsvUGFwZXJzLzIwMTAvSmltZcyBbmV6L1Byb2NlZWRpbmdzIG9mIHRoZSDigKYgMjAxMCBKaW1lzIFuZXoucGRmAAATAA4vVm9sdW1lcy9EYXRhMgAVAAIAHP//AACABdIcHR4fWCRjbGFzc2VzWiRjbGFzc25hbWWjHyAhXU5TTXV0YWJsZURhdGFWTlNEYXRhWE5TT2JqZWN0bxBSAC4ALgAvAC4ALgAvAC4ALgAvAC4ALgAvAGMAbwB1AHIAcwBlAHcAbwByAGsALwBQAGEAcABlAHIAcwAvADIAMAAxADAALwBKAGkAbQBlAwEAbgBlAHoALwBQAHIAbwBjAGUAZQBkAGkAbgBnAHMAIABvAGYAIAB0AGgAZQAgICYAIAAyADAAMQAwACAASgBpAG0AZQMBAG4AZQB6AC4AcABkAGbSHB0kJaIlIVxOU0RpY3Rpb25hcnkSAAGGoF8QD05TS2V5ZWRBcmNoaXZlcgAIABEAFgAfACgAMgA1ADoAPABFAEsAUgBdAGUAbABvAHEAcwB2AHgAegB8AIYAkwCYAKACwALCAscC0ALbAt8C7QL0Av0DpAOpA6wDuQO+AAAAAAAAAgEAAAAAAAAAKAAAAAAAAAAAAAAAAAAAA9A=},
	Bdsk-Url-1 = {http://portal.acm.org/citation.cfm?id=1854281}}

@inproceedings{Kansal2004,
	Author = {A Kansal and D Potter and M Srivastava},
	Date-Added = {2010-09-17 15:36:44 -0500},
	Date-Modified = {2010-09-18 18:21:50 -0500},
	Journal = {ACM SIGMETRICS Performance Evaluation Review},
	Month = {Jan},
	Number = {1},
	Pmid = {5968653435113800564related:dINfC63q1FIJ},
	Rating = {0},
	Title = {Performance aware tasking for environmentally powered sensor networks},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p880},
	Url = {http://portal.acm.org/citation.cfm?id=1012888.1005714},
	Volume = {32},
	Year = {2004},
	Abstract = { technologies exist to extract energy from the environment such as
	solar, , optical and providing methods to systematically utilize
	replenishable en- ergy resources in a manner. 30, 31, 32, 33, 34,
	35], data gathering [36], topology [37] and },
	Bdsk-Url-1 = {http://portal.acm.org/citation.cfm?id=1012888.1005714}}

@article{Kazempour2008,
	Author = {V Kazempour and A Fedorova and P Alagheband},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 18:22:14 -0500},
	Journal = {Lecture Notes in Computer Science},
	Pages = {151--161},
	Rating = {0},
	Title = {Performance implications of cache affinity on multicore processors},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p164},
	Volume = {5168},
	Year = {2008},
	Abstract = {Cache affinity between a process and a processor is observed when
	the processor cache has accumulated some amount of the process state,
	i.e., data or instructions. Cache affinity is exploited by OS schedulers:
	they tend to reschedule processes to run on a recently used processor.
	On conventional (unicore) multiprocessor systems, exploitation of
	cache affinity improves performance. It is not yet known, however,
	whether similar performance improvements would be observed on multicore
	processors. Understanding these effects is crucial for design of
	efficient multicore scheduling algorithms. Our study analyzes performance
	effects of cache affinity exploitation on multicore processors. We
	find that performance improvements on multicoreuniprocessors are
	not significant. At the same time, performance improvements on multicore
	multiprocessors are rather pronounced.}}

@article{Kumar2006,
	Affiliation = {New York, NY, USA},
	Author = {Amit Kumar and Li Shang and Li-Shiuan Peh and Niraj K Jha},
	Date-Added = {2010-04-11 22:19:04 -0500},
	Date-Modified = {2010-09-18 18:22:48 -0500},
	Doi = {http://doi.acm.org/10.1145/1146909.1147052},
	Journal = {Proceedings of 43th ACM/IEEE Design Automation Conference},
	Pages = {548--553},
	Rating = {0},
	Title = {HybDTM: a coordinated hardware-software approach for dynamic thermal management},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p146},
	Url = {http://doi.acm.org/10.1145/1146909.1147052},
	Year = {2006},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1146909.1147052}}

@article{Kursun06,
	Author = {Eren Kursun and Chen-yong Cher and Alper Buyuktosunoglu and Pradip Bose},
	Date-Added = {2010-04-11 22:19:04 -0500},
	Date-Modified = {2010-09-18 18:23:38 -0500},
	Journal = {Proceedings of the 3rd Workshop on Temperature-Aware Computer Systems},
	Rating = {0},
	Title = {Investigating the Effects of Task Scheduling on Thermal Behavior},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p165},
	Year = {2006}}

@inproceedings{Lewis2008,
	Author = {Adam Lewis and Soumik Ghosh and N.-F. Tzeng},
	Booktitle = {{Proc. of the 2008 Workshop on Power Aware Computing and Systems (Hotpower'08)}},
	Date-Added = {2010-02-13 21:47:04 -0600},
	Date-Modified = {2010-02-13 21:47:04 -0600},
	Title = {Run-time Energy Consumption Estimation Based on Workload in Server Systems},
	Year = {2008}}

@article{LiD2008,
	Author = {Dong Li and Hung-Ching Chang and HK Pyla and KW Cameron},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-04-26 15:58:35 -0500},
	Journal = {Proc. of the 2008 IEEE Int'l Symp. on Parallel and Distributed Processing},
	Keywords = {multithreaded process migration, process scheduling, processor power consumption, multicore process migration, dynamic voltage scaling, multi-threading, program compilersdynamic frequency scaling, thermal-aware process scheduling algorithm, power aware computing, processor scheduling},
	Month = {Apr},
	Pages = {1--7},
	Rating = {0},
	Title = {System-level, thermal-aware, fully-loaded process scheduling},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p160},
	Url = {http://dx.doi.org/10.1109/IPDPS.2008.4536225},
	Year = {2008},
	Abstract = {Processor power consumption produces significant heat and can result
	in higher average operating temperatures. High operating temperatures
	can lead to reduced reliability and at times thermal emergencies.
	Previous thermal-aware techniques use dynamic voltage and frequency
	scaling (DVFS) or multithreaded or multicore process migration to
	reduce thermals. However, these methods do not gracefully handle
	scenarios where processors are fully loaded, i.e. there are no free
	threads or cores for process scheduling. We propose techniques to
	reduce processor temperature when processors are fully loaded. We
	use system-level compiler support and dynamic runtime instrumentation
	to identify the relative thermal intensity of processes. We implement
	a thermal-aware process scheduling algorithm that reduces processor
	thermals while maintaining application throughput. We favor ``cool''
	processes by reducing time slice allocations for ``hot'' processes.
	Results indicate that our thermal-aware scheduling can reduce processor
	thermals by up to 3 degrees Celsius with little to no loss in application
	throughput.},
	Bdsk-Url-1 = {http://dx.doi.org/10.1109/IPDPS.2008.4536225}}

@article{LiK2008,
	Author = {Keqin Li},
	Date-Added = {2010-04-11 22:19:04 -0500},
	Date-Modified = {2010-04-26 15:58:35 -0500},
	Doi = {10.1109/TPDS.2008.122},
	Journal = {IEEE Transactions on Parallel and Distributed Systems},
	Keywords = {performance analysis, power-aware task scheduling algorithms, power aware computing, multiprocessor computers, software performance evaluation, dynamically variable speed, dynamically variable voltage, real-time multiprocessing systems, mobile computing, mobile computers, heuristic algorithms, combinatorial mathematics, multiprocessor computing systems, scheduling, task analysiscombinatorial optimization},
	Month = {Nov},
	Number = {11},
	Pages = {1484--1497},
	Rating = {0},
	Title = {Performance Analysis of Power-Aware Task Scheduling Algorithms on Multiprocessor Computers with Dynamic Voltage and Speed},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p157},
	Url = {http://dx.doi.org/10.1109/TPDS.2008.122},
	Volume = {19},
	Year = {2008},
	Abstract = {Task scheduling on multiprocessor computers with dynamically variable
	voltage and speed is investigated as combinatorial optimization problems,
	namely, the problem of minimizing schedule length with energy consumption
	constraint and the problem of minimizing energy consumption with
	schedule length constraint. The first problem has applications in
	general multiprocessor computing systems where energy consumption
	is an important concern and in mobile computers where energy conservation
	is a main concern. The second problem has applications in real-time
	multiprocessing systems where timing constraint is a major requirement.
	These problems emphasize the tradeoff between power and performance
	and are defined such that the power-performance product is optimized
	by fixing one factor and minimizing the other. It is found that both
	problems are equivalent to the sum of powers problem and can be decomposed
	into two subproblems, namely, scheduling tasks and determining power
	supplies. Such decomposition makes design and analysis of heuristic
	algorithms tractable. We analyze the performance of list scheduling
	algorithms and equal-speed algorithms and prove that these algorithms
	are asymptotically optimal. Our extensive simulation data validate
	our analytical results and provide deeper insight into the performance
	of our heuristic algorithms.},
	Bdsk-Url-1 = {http://dx.doi.org/10.1109/TPDS.2008.122}}

@article{LiT2007,
	Affiliation = {New York, NY, USA},
	Author = {Tong Li and Dan Baumberger and David A Koufaty and Scott Hahn},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 18:24:44 -0500},
	Journal = {Proceedings of the 2007 ACM/IEEE Conf. on Supercomputing},
	Pages = {1--11},
	Rating = {0},
	Title = {Efficient operating system scheduling for performance-asymmetric multi-core architectures},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p145},
	Url = {http://doi.acm.org/10.1145/1362622.1362694},
	Year = {2007},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1362622.1362694}}

@book{McDougall2007,
	Author = {Richard McDougall and Jim Mauro},
	Date-Added = {2010-04-11 22:19:04 -0500},
	Date-Modified = {2010-04-26 15:58:35 -0500},
	Journal = {Book},
	Rating = {0},
	Title = {Solaris Internals: Solaris 10 and OpenSolaris Kernel Architecture},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p159},
	Year = {2007}}

@book{McKusick2004,
	Author = {McKusick, Marshall Kirk and Neville-Neil, George V.},
	Isbn = {0201702452},
	Publisher = {Pearson Education},
	Title = {The Design and Implementation of the FreeBSD Operating System},
	Year = {2004}}

@article{Merkel2008b,
	Author = {A Merkel and F Bellosa},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 18:27:09 -0500},
	Journal = {Proceedings of the 2008 Workshop on Power Aware Computing and Systems (Hotpower'08)},
	Rating = {0},
	Title = {Memory-aware Scheduling for Energy Efficiency on Multicore Processors},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p152},
	Url = {http://www.usenix.org/events/hotpower08/tech/full_papers/merkel/merkel.pdf},
	Bdsk-Url-1 = {http://www.usenix.org/events/hotpower08/tech/full_papers/merkel/merkel.pdf}}

@article{Merkel2008a,
	Affiliation = {New York, NY, USA},
	Author = {Andreas Merkel and Frank Bellosa},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 18:25:58 -0500},
	Doi = {http://doi.acm.org/10.1145/1352592.1352594},
	Journal = {Proceedings of 3rd ACM SIGOPS/Eurosys European Conference on Computer Systems},
	Pages = {1--12},
	Rating = {0},
	Title = {Task activity vectors: a new metric for temperature-aware scheduling},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p141},
	Url = {http://doi.acm.org/10.1145/1352592.1352594},
	Year = {2008},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1352592.1352594}}

@article{Merkel2006,
	Affiliation = {New York, NY, USA},
	Author = {Andreas Merkel and Frank Bellosa},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-04-26 15:58:35 -0500},
	Doi = {http://doi.acm.org/10.1145/1218063.1217974},
	Journal = {SIGOPS Oper. Syst. Rev.},
	Number = {4},
	Pages = {403--414},
	Rating = {0},
	Title = {Balancing power consumption in multiprocessor systems},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p117},
	Url = {http://doi.acm.org/10.1145/1218063.1217974},
	Volume = {40},
	Year = {2006},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1218063.1217974}}

@article{Moscibroda2007,
	Author = {T Moscibroda and O Mutlu},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 18:27:56 -0500},
	Journal = {Proceedings of the 16th USNEIX Security Symposium},
	Rating = {0},
	Title = {Memory performance attacks: Denial of memory service in multi-core systems},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p148},
	Year = {2007}}

@article{Quan2008,
	Affiliation = {New York, NY, USA},
	Author = {Gang Quan and Yan Zhang and William Wiles and Pei Pei},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 18:28:46 -0500},
	Journal = {Proceedings of the 6th IEEE/SCM/IFIP Int'l Conf. on Hardware/Software Codesign and System Synthesis},
	Pages = {267--272},
	Rating = {0},
	Title = {Guaranteed scheduling for repetitive hard real-time tasks under the maximal temperature constraint},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p156},
	Url = {http://doi.acm.org/10.1145/1450135.1450196},
	Year = {2008},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1450135.1450196}}

@article{Radhakrishnan2007,
	Author = {S Radhakrishnan and S Chinthamani and Kai Cheng},
	Date-Added = {2010-04-11 22:19:03 -0500},
	Date-Modified = {2010-04-26 15:58:35 -0500},
	Doi = {10.1109/MM.2007.44},
	Journal = {IEEE Micro},
	Keywords = {Intel Core 2 quad-core processors, peripheral interfaces, Intel 5000 shared-memory symmetric dual-processor system, shared memory systemsBNB chipset, microprocessor chips, Blackford northbridge chipset, I/O interfaces},
	Month = {Mar},
	Number = {2},
	Pages = {22--33},
	Rating = {0},
	Title = {The Blackford Northbridge Chipset for the Intel 5000},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p162},
	Url = {http://dx.doi.org/10.1109/MM.2007.44},
	Volume = {27},
	Year = {2007},
	Abstract = {The Intel 5000 is a shared-memory, symmetric dual-processor system
	based on the energy-efficient, high-performance Intel core 2 dual-
	and quad-core processors. A key component is the northbridge, which
	interconnects processor, memory, and I/O interfaces. The Blackford
	northbridge chipset provides multicore processor support and platform-level
	features and technologies. In this article, we describe the Intel
	5000 component architecture, focusing on the BNB chipset and its
	main interfaces. We also describe the chipset's key innovations,
	which help define new standards of function, performance, and feature
	set in the dual-processor segment.},
	Bdsk-Url-1 = {http://dx.doi.org/10.1109/MM.2007.44}}

@phdthesis{Raghu2010,
	Author = {A Raghu},
	Date-Added = {2010-09-17 16:22:05 -0500},
	Date-Modified = {2010-09-18 18:29:24 -0500},
	Journal = {dspace.uta.edu},
	Month = {Jan},
	Rating = {0},
	Title = {Dynamic Thermal Management Of Multi Core Processors Using Core Hopping},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p962},
	Url = {http://dspace.uta.edu/handle/10106/4965},
	Year = {2010},
	Abstract = { of a many core chip as a means of mitigating dissipation and non
	uniform power issues The goal of TM is to extend workload- power
	management into the nanosecond The benefits include enabling fine
	grained tracking of program that is not offered by },
	Bdsk-Url-1 = {http://dspace.uta.edu/handle/10106/4965}}

@article{Rajagopalan2007,
	Affiliation = {USENIX Association Berkeley, CA, USA},
	Author = {M Rajagopalan and BT Lewis and TA Anderson},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 18:30:42 -0500},
	Journal = {Proceedings of the 11th Workshop on Hot Topics in Operating Systems},
	Rating = {0},
	Title = {Thread scheduling for multi-core platforms},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p172},
	Year = {2007}}

@article{Rajamani2006,
	Author = {K Rajamani and H Hanson and J Rubio},
	Date-Added = {2010-09-17 15:36:44 -0500},
	Date-Modified = {2010-09-18 18:31:28 -0500},
	Journal = {Proc. of the 2006 IEEE Int'l. Symp. on Workload Characterization},
	Month = {Jan},
	Pmid = {10089329329635094859related:S3HU2pF_BIwJ},
	Rating = {0},
	Title = {Application-aware power management},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p873},
	Url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4086132},
	Year = {2006},
	Abstract = { they should exploit the causes of power variation for more - , advanced
	power Two critical objectives for high-performance systems are (1)
	maximizing performance programmable power and envelopes [6] for a
	processor chip; at the },
	Bdsk-Url-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4086132}}

@article{Rajan2007,
	Author = {D Rajan and P Yu},
	Date-Added = {2010-09-17 15:36:44 -0500},
	Date-Modified = {2010-09-18 18:32:06 -0500},
	Journal = {Proc. of the 14th Int'l Conf. on High-Performance Computing},
	Month = {Jan},
	Pmid = {5258751638349583061related:1ZLUxcDW-kgJ},
	Rating = {0},
	Title = {On temperature-aware scheduling for single-processor systems},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p898},
	Url = {http://portal.acm.org/citation.cfm?id=1782214},
	Year = {2007},
	Abstract = { day processors have interfaces that allow the user to control its
	speed in real-time using a mechanism called dynamic voltage scal-
	ing (DVS) [2]. For a detailed investigation into DVS and other mechanisms
	for implementing dynamic , see [3,4]. Processors },
	Bdsk-Url-1 = {http://portal.acm.org/citation.cfm?id=1782214}}

@article{Rangan2009,
	Address = {New York, NY, USA},
	Author = {Rangan, Krishna K. and Wei, Gu-Yeon and Brooks, David},
	Date-Added = {2010-02-13 21:46:55 -0600},
	Date-Modified = {2010-02-13 21:46:55 -0600},
	Doi = {http://doi.acm.org/10.1145/1555815.1555793},
	Issn = {0163-5964},
	Journal = {SIGARCH Comput. Archit. News},
	Number = {3},
	Pages = {302--313},
	Publisher = {ACM},
	Title = {Thread motion: fine-grained power management for multi-core systems},
	Volume = {37},
	Year = {2009},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1555815.1555793}}

@phdthesis{Rivoire2008a,
	Author = {Rivoire, S.M.},
	Date-Added = {2010-02-13 21:49:38 -0600},
	Date-Modified = {2010-02-13 21:49:38 -0600},
	School = {Stanford University},
	Title = {{Models and Metrics for Energy-efficient Computer Systems}},
	Year = {2008},
	Bdsk-File-1 = {YnBsaXN0MDDUAQIDBAUIJidUJHRvcFgkb2JqZWN0c1gkdmVyc2lvblkkYXJjaGl2ZXLRBgdUcm9vdIABqAkKFRYXGyIjVSRudWxs0wsMDQ4RFFpOUy5vYmplY3RzV05TLmtleXNWJGNsYXNzog8QgASABqISE4ACgAOAB1lhbGlhc0RhdGFccmVsYXRpdmVQYXRo0hgNGRpXTlMuZGF0YU8RAgoAAAAAAgoAAgAAEE1hY2Jvb2sgTWFpbkRpc2sAAAAAAAAAAAAAAMBqUqdIKwAAAB8SHRBSaXZvaXJlMjAwOGEucGRmAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA+3aWxZeoTwAAAAAAAAAAAAEAAwAACSAAAAAAAAAAAAAAAAAAAAAMU291cmNlUGFwZXJzABAACAAAwGqY9wAAABEACAAAxZf8rwAAAAEAIAAfEh0AHxHLAB8QywAfEL4AHwrpAA0NeQAMuTQADLkxAAIAak1hY2Jvb2sgTWFpbkRpc2s6VXNlcnM6YWRhbWw6RHJvcGJveDpjb3Vyc2V3b3JrOnZtcG93ZXJtZ3Q6UGFwZXJzOnBvd2VybW9kZWw6U291cmNlUGFwZXJzOlJpdm9pcmUyMDA4YS5wZGYADgAiABAAUgBpAHYAbwBpAHIAZQAyADAAMAA4AGEALgBwAGQAZgAPACIAEABNAGEAYwBiAG8AbwBrACAATQBhAGkAbgBEAGkAcwBrABIAWVVzZXJzL2FkYW1sL0Ryb3Bib3gvY291cnNld29yay92bXBvd2VybWd0L1BhcGVycy9wb3dlcm1vZGVsL1NvdXJjZVBhcGVycy9SaXZvaXJlMjAwOGEucGRmAAATAAEvAAAVAAIADP//AACABdIcHR4fWCRjbGFzc2VzWiRjbGFzc25hbWWjHyAhXU5TTXV0YWJsZURhdGFWTlNEYXRhWE5TT2JqZWN0XxArLi4vcG93ZXJtb2RlbC9Tb3VyY2VQYXBlcnMvUml2b2lyZTIwMDhhLnBkZtIcHSQloiUhXE5TRGljdGlvbmFyeRIAAYagXxAPTlNLZXllZEFyY2hpdmVyAAgAEQAWAB8AKAAyADUAOgA8AEUASwBSAF0AZQBsAG8AcQBzAHYAeAB6AHwAhgCTAJgAoAKuArACtQK+AskCzQLbAuIC6wMZAx4DIQMuAzMAAAAAAAACAQAAAAAAAAAoAAAAAAAAAAAAAAAAAAADRQ==}}

@inproceedings{Rivoire2008b,
	Author = {Rivoire, Suzanne and P. Ranganathan and C. Kozyrakis},
	Booktitle = {{Proc. of USENIX Workshop on Power Aware Computing and Systems (HotPower'08)}},
	Date-Added = {2010-02-13 21:45:46 -0600},
	Date-Modified = {2010-02-13 21:45:46 -0600},
	Title = {{A Comparison of High Level Full-System Power Models}},
	Year = {2008},
	Bdsk-Url-1 = {http://www.usenix.org/events/hotpower08/tech/full_papers/rivoire/rivoire.pdf}}

@article{Rong2006,
	Affiliation = {Piscataway, NJ, USA},
	Author = {Peng Rong and Massoud Pedram},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 18:32:59 -0500},
	Journal = {Proc. of the 2006 Asia and South Pacific Design Automation Conference},
	Pages = {473--478},
	Rating = {0},
	Title = {Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p122},
	Url = {http://doi.acm.org/10.1145/1118299.1118416},
	Year = {2006},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1118299.1118416}}

@article{Rosing2007,
	Author = {Rosing, T.S. and Mihic, K. and De Micheli, G.},
	Date-Added = {2010-02-13 21:43:51 -0600},
	Date-Modified = {2010-02-13 21:43:51 -0600},
	Doi = {10.1109/TVLSI.2007.895245},
	Issn = {1063-8210},
	Journal = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
	Keywords = {embedded systems, industrial property, integrated circuit reliability, integrated circuit testing, system-on-chipembedded systems, intellectual property, power management, reliability management, system-on-chip, transistor scaling},
	Month = {April},
	Number = {4},
	Pages = {391-403},
	Title = {Power and Reliability Management of SoCs},
	Volume = {15},
	Year = {2007},
	Abstract = {Today's embedded systems integrate multiple IP cores for processing,
	communication, and sensing on a single die as systems-on-chip (SoCs).
	Aggressive transistor scaling, decreased voltage margins and increased
	processor power and temperature have made reliability assessment
	a much more significant issue. Although reliability of devices and
	interconnect has been broadly studied, in this work, we study a tradeoff
	between reliability and power consumption for component-based SoC
	designs. We specifically focus on hard error rates as they cause
	a device to permanently stop operating. We also present a joint reliability
	and power management optimization problem whose solution is an optimal
	management policy. When careful joint policy optimization is performed,
	we obtain a significant improvement in energy consumption (40%) in
	tandem with meeting a reliability constraint for all SoC operating
	temperatures},
	Bdsk-Url-1 = {http://dx.doi.org/10.1109/TVLSI.2007.895245}}

@article{Sharifi2008,
	Affiliation = {New York, NY, USA},
	Author = {Shervin Sharifi and Tajana Simunic Rosing},
	Date-Added = {2010-04-11 22:19:04 -0500},
	Date-Modified = {2010-09-18 18:33:29 -0500},
	Doi = {http://doi.acm.org/10.1145/1366110.1366210},
	Journal = {Proceedings of the 18th ACM Great Lakes Symp. on VLSI},
	Pages = {417--422},
	Rating = {0},
	Title = {An analytical model for the upper bound on temperature differences on a chip},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p131},
	Url = {http://doi.acm.org/10.1145/1366110.1366210},
	Year = {2008},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1366110.1366210}}

@techreport{Shi2010,
	Author = {B Shi and A Srivastava},
	Date-Added = {2010-09-17 16:22:05 -0500},
	Date-Modified = {2010-09-18 18:34:11 -0500},
	Journal = {lib.umd.edu},
	Local-Url = {file://localhost/Users/awl8049/Dropbox/coursework/Papers/2010/Shi/lib.umd.edu%202010%20Shi.pdf},
	Month = {Jan},
	Number = {TR_2010-14},
	Rating = {0},
	Title = {Dynamic Thermal Management Considering Accurate Temperature-Leakage Interdependency},
	Type = {Technical Report},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p944},
	Url = {http://www.lib.umd.edu/drum/handle/1903/10597},
	Year = {2010},
	Abstract = { out solution that result in runaway and also those that violate the
	constraint So here we combine task rescheduling with speed in this
	problem to find better task order Now we can perform pruning of these
	solutions on a criteria similar to the one },
	Bdsk-File-1 = {YnBsaXN0MDDUAQIDBAUIJidUJHRvcFgkb2JqZWN0c1gkdmVyc2lvblkkYXJjaGl2ZXLRBgdUcm9vdIABqAkKFRYXGyIjVSRudWxs0wsMDQ4RFFpOUy5vYmplY3RzV05TLmtleXNWJGNsYXNzog8QgASABqISE4ACgAOAB1lhbGlhc0RhdGFccmVsYXRpdmVQYXRo0hgNGRpXTlMuZGF0YU8RAdoAAAAAAdoAAgAABURhdGEyAAAAAAAAAAAAAAAAAAAAAAAAAAAAAMgF58lIKwAAAA+K1RhsaWIudW1kLmVkdSAyMDEwIFNoaS5wZGYAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAD4rWyLlJYAAAAAAAAAAAAAQABQAACQAAAAAAAAAAAAAAAAAAAAADU2hpAAAQAAgAAMgGLhkAAAARAAgAAMi5j7AAAAABABwAD4rVAABfNwAAXw4AAF8MAABe1AAAAFoAAABXAAIAT0RhdGEyOlVzZXJzOmF3bDgwNDk6RHJvcGJveDpjb3Vyc2V3b3JrOlBhcGVyczoyMDEwOlNoaTpsaWIudW1kLmVkdSAyMDEwIFNoaS5wZGYAAA4AMgAYAGwAaQBiAC4AdQBtAGQALgBlAGQAdQAgADIAMAAxADAAIABTAGgAaQAuAHAAZABmAA8ADAAFAEQAYQB0AGEAMgASAEovVXNlcnMvYXdsODA0OS9Ecm9wYm94L2NvdXJzZXdvcmsvUGFwZXJzLzIwMTAvU2hpL2xpYi51bWQuZWR1IDIwMTAgU2hpLnBkZgATAA4vVm9sdW1lcy9EYXRhMgAVAAIAHP//AACABdIcHR4fWCRjbGFzc2VzWiRjbGFzc25hbWWjHyAhXU5TTXV0YWJsZURhdGFWTlNEYXRhWE5TT2JqZWN0XxA/Li4vLi4vLi4vLi4vY291cnNld29yay9QYXBlcnMvMjAxMC9TaGkvbGliLnVtZC5lZHUgMjAxMCBTaGkucGRm0hwdJCWiJSFcTlNEaWN0aW9uYXJ5EgABhqBfEA9OU0tleWVkQXJjaGl2ZXIACAARABYAHwAoADIANQA6ADwARQBLAFIAXQBlAGwAbwBxAHMAdgB4AHoAfACGAJMAmACgAn4CgAKFAo4CmQKdAqsCsgK7Av0DAgMFAxIDFwAAAAAAAAIBAAAAAAAAACgAAAAAAAAAAAAAAAAAAAMp},
	Bdsk-Url-1 = {http://www.lib.umd.edu/drum/handle/1903/10597}}

@conference{Singhal2008,
	Author = {Singhal, R.},
	Booktitle = {Intel Developer Forum, Shanghai, China},
	Date-Added = {2010-02-13 21:47:13 -0600},
	Date-Modified = {2010-02-13 21:47:13 -0600},
	Title = {{Inside Intel Next Generation Nehalem Microarchitecture}},
	Year = {2008}}

@article{skadron2007,
	Author = {K Skadron and P Bose and K Ghose and R Sendag and JJ Yi and D Chiou},
	Date-Added = {2010-04-11 22:19:04 -0500},
	Date-Modified = {2010-04-26 15:58:35 -0500},
	Journal = {IEEE Micro-Institute of Electrical and Electronics Engineers},
	Number = {6},
	Pages = {46--59},
	Rating = {0},
	Title = {Low-Power Design and Temperature Management},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p143},
	Volume = {27},
	Year = {2007}}

@article{Snowdon2009,
	Affiliation = {New York, NY, USA},
	Author = {David C Snowdon and Etienne Le Sueur and Stefan M Petters and Gernot Heiser},
	Date-Added = {2010-04-11 22:19:03 -0500},
	Date-Modified = {2010-09-18 18:35:13 -0500},
	Doi = {http://doi.acm.org/10.1145/1519065.1519097},
	Journal = {Proceedings of the 4th European Conference on Computer Systems},
	Pages = {289--302},
	Rating = {0},
	Title = {Koala: a platform for OS-level power management},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p133},
	Url = {http://doi.acm.org/10.1145/1519065.1519097},
	Year = {2009},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1519065.1519097}}

@article{Suleman2008,
	Affiliation = {New York, NY, USA},
	Author = {M Aater Suleman and Moinuddin K Qureshi and Yale N Patt},
	Date-Added = {2010-04-11 22:19:04 -0500},
	Date-Modified = {2010-04-26 15:58:35 -0500},
	Doi = {http://doi.acm.org/10.1145/1353535.1346317},
	Journal = {SIGOPS Oper. Syst. Rev.},
	Number = {2},
	Pages = {277--286},
	Rating = {0},
	Title = {Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p167},
	Url = {http://doi.acm.org/10.1145/1353535.1346317},
	Volume = {42},
	Year = {2008},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1353535.1346317}}

@misc{Sun2009,
	Author = {{Sun Microsystems}},
	Date-Added = {2010-02-13 21:48:01 -0600},
	Date-Modified = {2010-02-13 21:48:01 -0600},
	Lastchecked = {June 2009},
	Month = {June},
	Title = {{OpenSolaris CPU Power Management - Project Tesla}},
	Url = {http://opensolaris.org/os/project/tesla/Work/CPUPM/},
	Urldate = {June 2009},
	Year = {2009},
	Bdsk-Url-1 = {http://opensolaris.org/os/project/tesla/Work/CPUPM/}}

@article{Tang2006,
	Affiliation = {Los Alamitos, CA, USA},
	Author = {Qinghui Tang and Sandeep K S Gupta and Daniel Stanzione and Phil Cayton},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 18:36:00 -0500},
	Journal = {Proc. of the 2006 IEEE Int'l Symp. on Dependable, Autonomic and Secure Computing},
	Pages = {195--202},
	Rating = {0},
	Title = {Thermal-Aware Task Scheduling to Minimize Energy Usage of Blade Server Based Datacenters},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p134},
	Url = {http://doi.ieeecomputersociety.org/10.1109/DASC.2006.47},
	Volume = {0},
	Year = {2006},
	Bdsk-Url-1 = {http://doi.ieeecomputersociety.org/10.1109/DASC.2006.47}}

@article{Winter2010,
	Author = {J Winter and D Albonesi},
	Date-Added = {2010-09-17 16:22:06 -0500},
	Date-Modified = {2010-09-18 18:36:30 -0500},
	Journal = {Proceedings of the 19th Int'l Conf. on Parallel Architectures and Compilation Techniques},
	Month = {Jan},
	Rating = {0},
	Title = {Scalable thread scheduling and global power management for heterogeneous many-core architectures},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p925},
	Url = {http://portal.acm.org/citation.cfm?id=1854273.1854283},
	Year = {2010},
	Abstract = { samples, each of reasonable length, to prevent thread migration effects,
	time constants We then develop heuristic techniques on well-known
	methods in combinatorial optimization. With coarser-grain domains,
	the , in addition to matching threads to cores },
	Bdsk-Url-1 = {http://portal.acm.org/citation.cfm?id=1854273.1854283}}

@article{Wu2010,
	Author = {G Wu and Z Xu},
	Date-Added = {2010-09-17 16:22:06 -0500},
	Date-Modified = {2010-09-18 18:36:44 -0500},
	Journal = {Journal of Systems and Software},
	Month = {Jan},
	Rating = {0},
	Title = {Temperature-Aware Task Scheduling Algorithm for Soft Real-time Multi-Core Systems},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p921},
	Url = {http://linkinghub.elsevier.com/retrieve/pii/S016412121000213X},
	Year = {2010},
	Abstract = { Huang, W., K. Sankaranarayanan, et al. "Accurate, Pre-RTL - Design
	Using a Parameterized Isovi, D. and G. Fohler (2000). Efficient of
	sporadic, aperiodic, and periodic tasks with complex constraints.
	(2003). "Profile- dynamic voltage and },
	Bdsk-Url-1 = {http://linkinghub.elsevier.com/retrieve/pii/S016412121000213X}}

@article{Wu2007,
	Affiliation = {New York, NY, USA},
	Author = {Wei Wu and Lingling Jin and Jun Yang and Pu Liu and Sheldon X-D Tan},
	Date-Added = {2010-04-11 22:19:04 -0500},
	Date-Modified = {2010-04-26 15:58:35 -0500},
	Doi = {http://doi.acm.org/10.1145/1255456.1255462},
	Journal = {ACM Trans. on Des. Autom. Electron. Syst.},
	Number = {3},
	Pages = {1--29},
	Rating = {0},
	Title = {Efficient power modeling and software thermal sensing for runtime temperature monitoring},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p124},
	Url = {http://doi.acm.org/10.1145/1255456.1255462},
	Volume = {12},
	Year = {2007},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1255456


text:
.1255462}}

@article{Xia2010,
	Author = {L Xia and Y Zhu and J Yang and J Ye and Z Gu},
	Date-Added = {2010-09-17 16:22:06 -0500},
	Date-Modified = {2010-09-18 15:17:50 -0500},
	Journal = {The Computer Journal},
	Local-Url = {file://localhost/Users/awl8049/Dropbox/coursework/Papers/2010/Xia/The%20Computer%20Journal%202010%20Xia.pdf},
	Month = {Jan},
	Pmid = {15878695042897809502related:XhCuOAN1XNwJ},
	Rating = {0},
	Title = {Implementing a Thermal-Aware Scheduler in Linux Kernel on a Multi-Core Processor},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p932},
	Url = {http://comjnl.oxfordjournals.org/cgi/content/abstract/bxp119?ijkey=LRydrCtVo2Jqq4y&keytype=ref},
	Year = {2010},
	Abstract = { Zhang and Chatha [14] also formulated static off- line - as an integral
	optimization problem with nonlinear continuous constraint. 5. HR
	ALGORITHM The HR algorithm- [1] migrates tasks away from the overheated
	core and },
	Bdsk-File-1 = {YnBsaXN0MDDUAQIDBAUIJidUJHRvcFgkb2JqZWN0c1gkdmVyc2lvblkkYXJjaGl2ZXLRBgdUcm9vdIABqAkKFRYXGyIjVSRudWxs0wsMDQ4RFFpOUy5vYmplY3RzV05TLmtleXNWJGNsYXNzog8QgASABqISE4ACgAOAB1lhbGlhc0RhdGFccmVsYXRpdmVQYXRo0hgNGRpXTlMuZGF0YU8RAfwAAAAAAfwAAgAABURhdGEyAAAAAAAAAAAAAAAAAAAAAAAAAAAAAMgF58lIKwAAAA+J5h9UaGUgQ29tcHV0ZXIgSm91cm5hbCAjRjg5RTcucGRmAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAD4nnyLlHBwAAAAAAAAAAAAQABQAACQAAAAAAAAAAAAAAAAAAAAADWGlhAAAQAAgAAMgGLhkAAAARAAgAAMi5jVcAAAABABwAD4nmAABfNwAAXw4AAF8MAABe1AAAAFoAAABXAAIAVkRhdGEyOlVzZXJzOmF3bDgwNDk6RHJvcGJveDpjb3Vyc2V3b3JrOlBhcGVyczoyMDEwOlhpYTpUaGUgQ29tcHV0ZXIgSm91cm5hbCAjRjg5RTcucGRmAA4ARAAhAFQAaABlACAAQwBvAG0AcAB1AHQAZQByACAASgBvAHUAcgBuAGEAbAAgADIAMAAxADAAIABYAGkAYQAuAHAAZABmAA8ADAAFAEQAYQB0AGEAMgASAFMvVXNlcnMvYXdsODA0OS9Ecm9wYm94L2NvdXJzZXdvcmsvUGFwZXJzLzIwMTAvWGlhL1RoZSBDb21wdXRlciBKb3VybmFsIDIwMTAgWGlhLnBkZgAAEwAOL1ZvbHVtZXMvRGF0YTIAFQACABz//wAAgAXSHB0eH1gkY2xhc3Nlc1okY2xhc3NuYW1lox8gIV1OU011dGFibGVEYXRhVk5TRGF0YVhOU09iamVjdF8QSC4uLy4uLy4uLy4uL2NvdXJzZXdvcmsvUGFwZXJzLzIwMTAvWGlhL1RoZSBDb21wdXRlciBKb3VybmFsIDIwMTAgWGlhLnBkZtIcHSQloiUhXE5TRGljdGlvbmFyeRIAAYagXxAPTlNLZXllZEFyY2hpdmVyAAgAEQAWAB8AKAAyADUAOgA8AEUASwBSAF0AZQBsAG8AcQBzAHYAeAB6AHwAhgCTAJgAoAKgAqICpwKwArsCvwLNAtQC3QMoAy0DMAM9A0IAAAAAAAACAQAAAAAAAAAoAAAAAAAAAAAAAAAAAAADVA==},
	Bdsk-Url-1 = {http://comjnl.oxfordjournals.org/cgi/content/abstract/bxp119?ijkey=LRydrCtVo2Jqq4y&keytype=ref}}

@article{Xian2008,
	Author = {Changjiu Xian and Yung-Hsiang Lu and Zhiyuan Li},
	Date-Added = {2010-04-11 22:19:04 -0500},
	Date-Modified = {2010-04-26 15:58:35 -0500},
	Doi = {10.1109/TCAD.2008.925778},
	Journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
	Keywords = {polynomials, uncertain execution time, microprocessor chips, multitasking real-time systems, polynomial-time heuristic algorithm, low-power electronics, real-time systemsdynamic voltage-frequency scaling, intratask voltage scheduling, processor scheduling, energy conservation, voltage scheduling, frequency switching, multiple concurrent tasks, probabilistic distributions},
	Month = {Aug},
	Number = {8},
	Pages = {1467--1478},
	Rating = {0},
	Title = {Dynamic Voltage Scaling for Multitasking Real-Time Systems With Uncertain Execution Time},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p118},
	Url = {http://dx.doi.org/10.1109/TCAD.2008.925778},
	Volume = {27},
	Year = {2008},
	Bdsk-Url-1 = {http://dx.doi.org/10.1109/TCAD.2008.925778}}

@article{Xian2007,
	Affiliation = {New York, NY, USA},
	Author = {Changjiu Xian and Yung-Hsiang Lu and Zhiyuan Li},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 18:37:39 -0500},
	Journal = {Proc. of the 44th ACM/IEEE Design Automation Conference},
	Pages = {664--669},
	Rating = {0},
	Title = {Energy-aware scheduling for real-time multiprocessor systems with uncertain task execution time},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p137},
	Url = {http://doi.acm.org/10.1145/1278480.1278648},
	Year = {2007},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1278480.1278648}}

@article{Yang2008,
	Author = {Jun Yang and Xiuyi Zhou and M Chrobak and Youtao Zhang and Lingling Jin},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 18:38:29 -0500},
	Journal = {Proc. of the 2008 IEEE Int'l Symp. on Performance Analysis of Systems and Software},
	Keywords = {microprocessors, power aware computing, dynamic thermal management, microprocessor chips, thermal management (packaging)Linux kernel, task analysis, heuristic algorithm, thermal-aware job scheduling, voltage scaling, task scheduling, processor scheduling, Linux, frequency scaling, power consumption, heat generation speed on-die},
	Local-Url = {file://localhost/Users/awl8049/Dropbox/coursework/Papers/2008/Yang/Performance%20Analysis%20of%20Systems%20and%20software%202008.%20ISPASS%202008.%20IEEE%20International%20Symposium%20on%202008%20Yang.pdf},
	Month = {Apr},
	Pages = {191--201},
	Rating = {0},
	Title = {Dynamic Thermal Management through Task Scheduling},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p140},
	Url = {http://dx.doi.org/10.1109/ISPASS.2008.4510751},
	Year = {2008},
	Abstract = {The evolution of microprocessors has been hindered by their increasing
	power consumption and the heat generation speed on-die. High temperature
	impairs the processor's reliability and reduces its lifetime. While
	hardware level dynamic thermal management (DTM) techniques, such
	as voltage and frequency scaling, can effectively lower the chip
	temperature when it surpasses the thermal threshold, they inevitably
	come at the cost of performance degradation. We propose an OS level
	technique that performs thermal- aware job scheduling to reduce the
	number of thermal trespasses. Our scheduler reduces the amount of
	hardware DTMs and achieves higher performance while keeping the temperature
	low. Our methods leverage the natural discrepancies in thermal behavior
	among different workloads, and schedule them to keep the chip temperature
	below a given budget. We develop a heuristic algorithm based on the
	observation that there is a difference in the resulting temperature
	when a hot and a cool job are executed in a different order. To evaluate
	our scheduling algorithms, we developed a lightweight runtime temperature
	monitor to enable informed scheduling decisions. We have implemented
	our scheduling algorithm and the entire temperature monitoring framework
	in the Linux kernel. Our proposed scheduler can remove 10.5-73.6%
	of the hardware DTMs in various combinations of workloads in a medium
	thermal environment. As a result, the CPU throughput was improved
	by up to 7.6% (4.1% on average) even under a severe thermal environment.},
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	Bdsk-Url-1 = {http://dx.doi.org/10.1109/ISPASS.2008.4510751}}

@article{Yao1995,
	Affiliation = {Washington, DC, USA},
	Author = {F Yao and A Demers and S Shenker},
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 18:39:40 -0500},
	Journal = {Proc. of the 36th IEEE Symp. on Foundations of Computer Science},
	Pages = {374},
	Rating = {0},
	Title = {A scheduling model for reduced CPU energy},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p129},
	Year = {1995}}

@article{Yeo2009,
	Author = {I Yeo and E Kim},
	Date-Added = {2010-09-17 16:23:12 -0500},
	Date-Modified = {2010-09-18 18:41:14 -0500},
	Journal = {Proceedings of the 2009 Design, Automation, and Test in Europe Conference and Exhibition},
	Month = {Jan},
	Pmid = {14176090756768337144related:-AzgZG-Xu8QJ},
	Rating = {0},
	Title = {Temperature-Aware Scheduler Based on Thermal Behavior Grouping in Multicore Systems},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p949},
	Url = {http://faculty.cse.tamu.edu/ejkim/HPC_WEB/docs/date09_yeo.pdf},
	Year = {2009},
	Abstract = {Abstract---Dynamic Management techniques have been widely accepted
	as a solution for their low cost and simplicity. The techniques have
	been used to manage the heat dissipation and operating temperature
	to avoid emergencies, but are not aware of },
	Bdsk-Url-1 = {http://faculty.cse.tamu.edu/ejkim/HPC_WEB/docs/date09_yeo.pdf}}

@article{Yeo2008,
	Author = {Inchoon Yeo and Chih Chun Liu and Eun Jung Kim},
	Date-Added = {2010-04-11 22:19:04 -0500},
	Date-Modified = {2010-09-18 18:40:08 -0500},
	Journal = {Proc. of the 45th ACM/IEEE Design Automation Conference},
	Keywords = {predictive dynamic thermal management, processor power density, thermal management (packaging)Intel Quad-Core system, microprocessor chips, steady state temperature, core-based thermal model, Linux, Linux standard scheduler, temperature sensors, processor scheduling, SPEC2006 benchmark, integrated circuit modelling, multicore systems, on-chip temperature, priority scheduling, application-based thermal model, digital thermal sensor},
	Month = {Jun},
	Pages = {734--739},
	Rating = {0},
	Title = {Predictive dynamic thermal management for multicore systems},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p116},
	Year = {2008},
	Bdsk-Url-1 = {http://portal.acm.org/ft_gateway.cfm?id=1391658&type=pdf&coll=GUIDE&dl=GUIDE&CFID=102735460&CFTOKEN=63382164},
	Bdsk-Url-2 = {http://delivery.acm.org/10.1145/1400000/1391658/p734-yeo.pdf?key1=1391658&key2=3769905821&coll=GUIDE&dl=GUIDE&CFID=102735460&CFTOKEN=63382164}}

@article{Yuan2006,
	Affiliation = {New York, NY, USA},
	Author = {Wanghong Yuan and Klara Nahrstedt},
	Date-Added = {2010-04-11 22:19:04 -0500},
	Date-Modified = {2010-09-18 18:41:40 -0500},
	Doi = {http://doi.acm.org/10.1145/1151690.1151693},
	Journal = {ACM Transactions on Computer Systems},
	Number = {3},
	Pages = {292--331},
	Rating = {0},
	Title = {Energy-efficient CPU scheduling for multimedia applications},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p153},
	Url = {http://doi.acm.org/10.1145/1151690.1151693},
	Volume = {24},
	Year = {2006},
	Bdsk-Url-1 = {http://doi.acm.org/10.1145/1151690.1151693}}

@article{Zamani2007,
	Author = {R Zamani and A Afsahi and Y Qian and C Hamacher},
	Date-Added = {2010-04-11 22:19:04 -0500},
	Date-Modified = {2010-09-18 18:42:39 -0500},
	Journal = {Proc. of the 2007 IEEE Int'l. Conf. on Cluster Computing},
	Pages = {118--128},
	Rating = {0},
	Title = {A Feasibility Analysis of Power-Awareness and Energy Minimization in Modern Interconnects for High-Performance Computing},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p166},
	Year = {2007}}

@article{Zanini2009,
	Author = {F Zanini and D Atienza and G De Micheli},
	Date-Added = {2010-09-17 16:23:13 -0500},
	Date-Modified = {2010-09-18 18:43:24 -0500},
	Journal = {Proc. of the 2009 Asia and South Pacific Design Automation Conference},
	Local-Url = {file://localhost/Users/awl8049/Dropbox/coursework/Papers/2009/Zanini/%E2%80%A6%20Conference%202009%20Zanini.pdf},
	Month = {Jan},
	Pmid = {4309435309614571352related:WB8a7JQwzjsJ},
	Rating = {0},
	Title = {A control theory approach for thermal balancing of MPSoC},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p922},
	Url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4796438},
	Year = {2009},
	Abstract = { of DATE, 2008. [12] P.Ituero, et al.,Leakage- On-Chip Sensor for
	CMOS Technology, Proc. [16] W. Hung et al., -aware allocation and
	for -on-chip., Proc. [17] AK Coskun, et al., Task in MP- SoCs, Proc.
	},
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	Bdsk-Url-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4796438}}

@article{Zhou2010b,
	Author = {X Zhou and J Yang and M Chrobak and Y Zhang},
	Date-Added = {2010-09-17 15:27:45 -0500},
	Date-Modified = {2010-09-18 15:02:25 -0500},
	Journal = {ACM Transactions on Architecture and Code Optimization (TACO)},
	Local-Url = {file://localhost/Users/awl8049/Dropbox/coursework/Papers/2010/Zhou/ACM%20Transactions%20on%20Architecture%20and%20Code%20Optimization%20(TACO)%202010%20Zhou-1.pdf},
	Number = {1},
	Pages = {1--31},
	Pmid = {related:jfxHV8uhckgJ},
	Rating = {0},
	Read = {Yes},
	Title = {Performance-aware thermal management via task scheduling},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p872},
	Volume = {7},
	Year = {2010},
	Bdsk-File-1 = {YnBsaXN0MDDUAQIDBAUIJidUJHRvcFgkb2JqZWN0c1gkdmVyc2lvblkkYXJjaGl2ZXLRBgdUcm9vdIABqAkKFRYXGyIjVSRudWxs0wsMDQ4RFFpOUy5vYmplY3RzV05TLmtleXNWJGNsYXNzog8QgASABqISE4ACgAOAB1lhbGlhc0RhdGFccmVsYXRpdmVQYXRo0hgNGRpXTlMuZGF0YU8RAoIAAAAAAoIAAgAABURhdGEyAAAAAAAAAAAAAAAAAAAAAAAAAAAAAMgF58lIKwAAAA+BaB9BQ00gVHJhbnNhY3Rpb25zIG9uIEEjRjg0MEUucGRmAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAD4QOyLk5cQAAAAAAAAAAAAQABQAACQAAAAAAAAAAAAAAAAAAAAAEWmhvdQAQAAgAAMgGLhkAAAARAAgAAMi5f8EAAAABABwAD4FoAABfNwAAXw4AAF8MAABe1AAAAFoAAABXAAIAV0RhdGEyOlVzZXJzOmF3bDgwNDk6RHJvcGJveDpjb3Vyc2V3b3JrOlBhcGVyczoyMDEwOlpob3U6QUNNIFRyYW5zYWN0aW9ucyBvbiBBI0Y4NDBFLnBkZgAADgCcAE0AQQBDAE0AIABUAHIAYQBuAHMAYQBjAHQAaQBvAG4AcwAgAG8AbgAgAEEAcgBjAGgAaQB0AGUAYwB0AHUAcgBlACAAYQBuAGQAIABDAG8AZABlACAATwBwAHQAaQBtAGkAegBhAHQAaQBvAG4AIAAoAFQAQQBDAE8AKQAgADIAMAAxADAAIABaAGgAbwB1AC0AMQAuAHAAZABmAA8ADAAFAEQAYQB0AGEAMgASAIAvVXNlcnMvYXdsODA0OS9Ecm9wYm94L2NvdXJzZXdvcmsvUGFwZXJzLzIwMTAvWmhvdS9BQ00gVHJhbnNhY3Rpb25zIG9uIEFyY2hpdGVjdHVyZSBhbmQgQ29kZSBPcHRpbWl6YXRpb24gKFRBQ08pIDIwMTAgWmhvdS0xLnBkZgATAA4vVm9sdW1lcy9EYXRhMgAVAAIAHP//AACABdIcHR4fWCRjbGFzc2VzWiRjbGFzc25hbWWjHyAhXU5TTXV0YWJsZURhdGFWTlNEYXRhWE5TT2JqZWN0XxB1Li4vLi4vLi4vLi4vY291cnNld29yay9QYXBlcnMvMjAxMC9aaG91L0FDTSBUcmFuc2FjdGlvbnMgb24gQXJjaGl0ZWN0dXJlIGFuZCBDb2RlIE9wdGltaXphdGlvbiAoVEFDTykgMjAxMCBaaG91LTEucGRm0hwdJCWiJSFcTlNEaWN0aW9uYXJ5EgABhqBfEA9OU0tleWVkQXJjaGl2ZXIACAARABYAHwAoADIANQA6ADwARQBLAFIAXQBlAGwAbwBxAHMAdgB4AHoAfACGAJMAmACgAyYDKAMtAzYDQQNFA1MDWgNjA9sD4APjA/AD9QAAAAAAAAIBAAAAAAAAACgAAAAAAAAAAAAAAAAAAAQH}}

@article{Zhou2010a,
	Author = {Xiuyi Zhou and Jun Yang and Yi Xu and Youtao Zhang and Jianhua Zhao},
	Date-Added = {2010-04-11 22:19:03 -0500},
	Date-Modified = {2010-09-18 15:02:30 -0500},
	Doi = {10.1109/TPDS.2009.27},
	Journal = {IEEE Transactions on Parallel and Distributed Systems},
	Keywords = {thermal-aware task scheduling, voltage throttlings, device density, 3D multicore processors, thermal management (packaging), microprocessor chips, frequency throttlings, integrated circuit manufacture, interconnects, processor scheduling, power density, thermal correlations, chip temperature, round-robin algorithm, integrated circuit interconnections, heat dissipation, OS-level scheduling algorithm, high-speed interface, intuitive algorithms, 3D integration technology, random algorithms, chip fabrication},
	Month = {Jan},
	Number = {1},
	Pages = {60 --71},
	Rating = {0},
	Title = {Thermal-Aware Task Scheduling for 3D Multicore Processors},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p163},
	Url = {http://dx.doi.org/10.1109/TPDS.2009.27},
	Volume = {21},
	Year = {2010},
	Abstract = {A rising horizon in chip fabrication is the 3D integration technology.
	It stacks two or more dies vertically with a dense, high-speed interface
	to increase the device density and reduce the delay of interconnects
	significantly across the dies. However, a major challenge in 3D technology
	is the increased power density, which gives rise to the concern of
	heat dissipation within the processor. High temperatures trigger
	voltage and frequency throttlings in hardware, which degrade the
	chip performance. Moreover, high temperatures impair the processor's
	reliability and reduce its lifetime. To alleviate this problem, we
	propose in this paper an OS-level scheduling algorithm that performs
	thermal-aware task scheduling on a 3D chip. Our algorithm leverages
	the inherent thermal variations within and across different tasks,
	and schedules them to keep the chip temperature low. We observed
	that vertically adjacent dies have strong thermal correlations and
	the scheduler should consider them jointly. Compared with other intuitive
	algorithms such as a Random and a Round-Robin algorithm, our proposed
	algorithm brings lower peak temperature and average temperature on-chip.
	Moreover, it can remove, on average, 46 percent of thermal emergency
	time and result in 5.11 percent (4.78 percent) performance improvement
	over the base case on thermally homogeneous (heterogeneous) floorplans.},
	Bdsk-Url-1 = {http://dx.doi.org/10.1109/TPDS.2009.27}}

@misc{Smaalders2008,
	Date-Added = {2010-04-11 22:19:17 -0500},
	Date-Modified = {2010-09-18 18:34:33 -0500},
	Month = {Jul},
	Rating = {0},
	Title = {Solaris and CMT},
	Uri = {papers://29A695D8-9431-4F2A-A5D6-CFC24651882A/Paper/p161},
	Url = {http://www.opensparc.net/pubs/preszo/06/multicore/cmt_conf-bart-smaalders.pdf},
	Year = {2008},
	Bdsk-Url-1 = {http://www.opensparc.net/pubs/preszo/06/multicore/cmt_conf-bart-smaalders.pdf}}

@manual{AMD2008,
	Date-Added = {2010-02-13 21:47:25 -0600},
	Date-Modified = {2010-02-13 21:47:25 -0600},
	Edition = {26094 Rev 3.30},
	Month = {February},
	Organization = {AMD},
	Title = {{BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD Opteron Processors}},
	Year = {2006}}

@manual{AMD2008b,
	Date-Added = {2010-02-13 21:47:30 -0600},
	Date-Modified = {2010-02-13 21:47:30 -0600},
	Edition = {3.06 08},
	Month = {September},
	Organization = {AMD},
	Title = {{Software Optimization Guide for AMD Family 10h Processors}},
	Year = {2005}}

license_type: permissive

branch_name: refs/heads/master

extension: bib


text:
@article{bilionis_multi-output_2013,
 abstract = {Computer codes simulating physical systems usually have responses that consist of a set of distinct outputs (e.g., velocity and pressure) that evolve also in space and time and depend on many unknown input parameters (e.g., physical constants, initial/boundary conditions, etc.). Furthermore, essential engineering procedures such as uncertainty quantification, inverse problems or design are notoriously difficult to carry out mostly due to the limited simulations available. The aim of this work is to introduce a fully Bayesian approach for treating these problems which accounts for the uncertainty induced by the finite number of observations. Our model is built on a multi-dimensional Gaussian process that explicitly treats correlations between distinct output variables as well as space and/or time. The proper use of a separable covariance function enables us to describe the huge covariance matrix as a Kronecker product of smaller matrices leading to efficient algorithms for carrying out inference and predictions. The novelty of this work, is the recognition that the Gaussian process model defines a posterior probability measure on the function space of possible surrogates for the computer code and the derivation of an algorithmic procedure that allows us to sample it efficiently. We demonstrate how the scheme can be used in uncertainty quantification tasks in order to obtain error bars for the statistics of interest that account for the finite number of observations.},
 author = {Bilionis, Ilias and Zabaras, Nicholas and Konomi, Bledar A. and Lin, Guang},
 doi = {10.1016/j.jcp.2013.01.011},
 file = {ScienceDirect Snapshot:/Users/iliasbilionis/Zotero/storage/KRIAV3TI/S0021999113000417.html:text/html},
 issn = {0021-9991},
 journal = {Journal of Computational Physics},
 keywords = {Uncertainty quantification, Bayesian, Gaussian process, Stochastic partial differential equations, Kronecker product, Separable covariance function, Surrogate models},
 month = {May},
 pages = {212--239},
 shorttitle = {Multi-output separable Gaussian process},
 title = {Multi-output separable Gaussian process: Towards an efficient, fully Bayesian paradigm for uncertainty quantification},
 url = {http://www.sciencedirect.com/science/article/pii/S0021999113000417},
 urldate = {2018-07-02},
 volume = {241},
 year = {2013}
}

license: MIT

repository: PredictiveScienceLab/www

repo_name: PredictiveScienceLab/www


text:
SUMMARY = "Python 3.3+'s ipaddress for Python 2.6, 2.7, 3.2."
HOMEPAGE = "https://github.com/phihag/ipaddress"
LICENSE = "Python-2.0"
LIC_FILES_CHKSUM = "file://LICENSE;md5=7f538584cc3407bf76042def7168548a"

SRC_URI[md5sum] = "aaee67a8026782af1831148beb0d9060"
SRC_URI[sha256sum] = "b7f8e0369580bb4a24d5ba1d7cc29660a4a6987763faf1d8a8046830e020e7e2"

inherit pypi setuptools3

BBCLASSEXTEND = "native nativesdk"

repository: openembedded/meta-openembedded

repo_name: openembedded/meta-openembedded

gha_license_id: MIT

gha_language: BitBake

extension: bb