text:
<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE eagle SYSTEM "eagle.dtd">
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<library name="SamacSys_Parts">
<description>https://eagle.componentsearchengine.com
<author>Created by SamacSys</author></description>
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<pad name="27" x="8.062" y="-8.89" drill="0.73" diameter="1.13"/>
<pad name="28" x="8.062" y="-6.35" drill="0.73" diameter="1.13"/>
<pad name="29" x="8.062" y="-3.81" drill="0.73" diameter="1.13"/>
<pad name="30" x="8.062" y="-1.27" drill="0.73" diameter="1.13"/>
<pad name="31" x="8.062" y="1.27" drill="0.73" diameter="1.13"/>
<pad name="32" x="8.062" y="3.81" drill="0.73" diameter="1.13"/>
<pad name="33" x="8.062" y="6.35" drill="0.73" diameter="1.13"/>
<pad name="34" x="8.062" y="8.89" drill="0.73" diameter="1.13"/>
<pad name="35" x="8.062" y="11.43" drill="0.73" diameter="1.13"/>
<pad name="36" x="8.062" y="13.97" drill="0.73" diameter="1.13"/>
<pad name="37" x="8.062" y="16.51" drill="0.73" diameter="1.13"/>
<pad name="38" x="8.062" y="19.05" drill="0.73" diameter="1.13"/>
<pad name="39" x="8.062" y="21.59" drill="0.73" diameter="1.13"/>
<pad name="40" x="8.062" y="24.13" drill="0.73" diameter="1.13"/>
<text x="0" y="0" size="1.27" layer="25" align="center">>NAME</text>
<text x="0" y="0" size="1.27" layer="27" align="center">>VALUE</text>
<wire x1="-9.195" y1="26.54" x2="9.195" y2="26.54" width="0.05" layer="51"/>
<wire x1="9.195" y1="26.54" x2="9.195" y2="-26.54" width="0.05" layer="51"/>
<wire x1="9.195" y1="-26.54" x2="-9.195" y2="-26.54" width="0.05" layer="51"/>
<wire x1="-9.195" y1="-26.54" x2="-9.195" y2="26.54" width="0.05" layer="51"/>
<wire x1="-7.11" y1="26.29" x2="7.11" y2="26.29" width="0.1" layer="51"/>
<wire x1="7.11" y1="26.29" x2="7.11" y2="-26.29" width="0.1" layer="51"/>
<wire x1="7.11" y1="-26.29" x2="-7.11" y2="-26.29" width="0.1" layer="51"/>
<wire x1="-7.11" y1="-26.29" x2="-7.11" y2="26.29" width="0.1" layer="51"/>
<wire x1="-7.11" y1="25.02" x2="-5.84" y2="26.29" width="0.1" layer="51"/>
<wire x1="-8.628" y1="26.29" x2="7.11" y2="26.29" width="0.2" layer="21"/>
<wire x1="-7.11" y1="-26.29" x2="7.11" y2="-26.29" width="0.2" layer="21"/>
</package>
<package name="71124S20YG">
<description>71124S20YG-3

</description>
<smd name="1" x="-9.525" y="-4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="2" x="-8.255" y="-4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="3" x="-6.985" y="-4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="4" x="-5.715" y="-4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="5" x="-4.445" y="-4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="6" x="-3.175" y="-4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="7" x="-1.905" y="-4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="8" x="-0.635" y="-4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="9" x="0.635" y="-4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="10" x="1.905" y="-4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="11" x="3.175" y="-4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="12" x="4.445" y="-4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="13" x="5.715" y="-4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="14" x="6.985" y="-4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="15" x="8.255" y="-4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="16" x="9.525" y="-4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="17" x="9.525" y="4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="18" x="8.255" y="4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="19" x="6.985" y="4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="20" x="5.715" y="4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="21" x="4.445" y="4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="22" x="3.175" y="4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="23" x="1.905" y="4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="24" x="0.635" y="4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="25" x="-0.635" y="4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="26" x="-1.905" y="4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="27" x="-3.175" y="4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="28" x="-4.445" y="4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="29" x="-5.715" y="4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="30" x="-6.985" y="4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="31" x="-8.255" y="4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<smd name="32" x="-9.525" y="4.788" dx="2.159" dy="0.559" layer="1" rot="R90"/>
<text x="0" y="-0.391" size="1.27" layer="25" align="center">>NAME</text>
<text x="0" y="-0.391" size="1.27" layer="27" align="center">>VALUE</text>
<wire x1="-10.478" y1="5.08" x2="10.478" y2="5.08" width="0.2" layer="51"/>
<wire x1="10.478" y1="5.08" x2="10.478" y2="-5.08" width="0.2" layer="51"/>
<wire x1="10.478" y1="-5.08" x2="-10.478" y2="-5.08" width="0.2" layer="51"/>
<wire x1="-10.478" y1="-5.08" x2="-10.478" y2="5.08" width="0.2" layer="51"/>
<wire x1="-11.478" y1="6.867" x2="11.478" y2="6.867" width="0.1" layer="51"/>
<wire x1="11.478" y1="6.867" x2="11.478" y2="-7.65" width="0.1" layer="51"/>
<wire x1="11.478" y1="-7.65" x2="-11.478" y2="-7.65" width="0.1" layer="51"/>
<wire x1="-11.478" y1="-7.65" x2="-11.478" y2="6.867" width="0.1" layer="51"/>
<wire x1="-10.478" y1="5.06" x2="-10.478" y2="-5.08" width="0.1" layer="21"/>
<wire x1="10.478" y1="5.06" x2="10.478" y2="-5.08" width="0.1" layer="21"/>
<wire x1="-9.68" y1="-6.6" x2="-9.68" y2="-6.6" width="0.1" layer="21"/>
<wire x1="-9.68" y1="-6.6" x2="-9.58" y2="-6.6" width="0.1" layer="21" curve="180"/>
<wire x1="-9.58" y1="-6.6" x2="-9.58" y2="-6.6" width="0.1" layer="21"/>
<wire x1="-9.58" y1="-6.6" x2="-9.68" y2="-6.6" width="0.1" layer="21" curve="180"/>
</package>
<package name="SOIC127P600X175-16N">
<description>SOIC-16 CASE751B-05

</description>
<smd name="1" x="-2.725" y="4.445" dx="1.55" dy="0.65" layer="1"/>
<smd name="2" x="-2.725" y="3.175" dx="1.55" dy="0.65" layer="1"/>
<smd name="3" x="-2.725" y="1.905" dx="1.55" dy="0.65" layer="1"/>
<smd name="4" x="-2.725" y="0.635" dx="1.55" dy="0.65" layer="1"/>
<smd name="5" x="-2.725" y="-0.635" dx="1.55" dy="0.65" layer="1"/>
<smd name="6" x="-2.725" y="-1.905" dx="1.55" dy="0.65" layer="1"/>
<smd name="7" x="-2.725" y="-3.175" dx="1.55" dy="0.65" layer="1"/>
<smd name="8" x="-2.725" y="-4.445" dx="1.55" dy="0.65" layer="1"/>
<smd name="9" x="2.725" y="-4.445" dx="1.55" dy="0.65" layer="1"/>
<smd name="10" x="2.725" y="-3.175" dx="1.55" dy="0.65" layer="1"/>
<smd name="11" x="2.725" y="-1.905" dx="1.55" dy="0.65" layer="1"/>
<smd name="12" x="2.725" y="-0.635" dx="1.55" dy="0.65" layer="1"/>
<smd name="13" x="2.725" y="0.635" dx="1.55" dy="0.65" layer="1"/>
<smd name="14" x="2.725" y="1.905" dx="1.55" dy="0.65" layer="1"/>
<smd name="15" x="2.725" y="3.175" dx="1.55" dy="0.65" layer="1"/>
<smd name="16" x="2.725" y="4.445" dx="1.55" dy="0.65" layer="1"/>
<text x="0" y="0" size="1.27" layer="25" align="center">>NAME</text>
<text x="0" y="0" size="1.27" layer="27" align="center">>VALUE</text>
<wire x1="-3.75" y1="5.25" x2="3.75" y2="5.25" width="0.05" layer="51"/>
<wire x1="3.75" y1="5.25" x2="3.75" y2="-5.25" width="0.05" layer="51"/>
<wire x1="3.75" y1="-5.25" x2="-3.75" y2="-5.25" width="0.05" layer="51"/>
<wire x1="-3.75" y1="-5.25" x2="-3.75" y2="5.25" width="0.05" layer="51"/>
<wire x1="-1.95" y1="4.95" x2="1.95" y2="4.95" width="0.1" layer="51"/>
<wire x1="1.95" y1="4.95" x2="1.95" y2="-4.95" width="0.1" layer="51"/>
<wire x1="1.95" y1="-4.95" x2="-1.95" y2="-4.95" width="0.1" layer="51"/>
<wire x1="-1.95" y1="-4.95" x2="-1.95" y2="4.95" width="0.1" layer="51"/>
<wire x1="-1.95" y1="3.68" x2="-0.68" y2="4.95" width="0.1" layer="51"/>
<wire x1="-1.6" y1="4.95" x2="1.6" y2="4.95" width="0.2" layer="21"/>
<wire x1="1.6" y1="4.95" x2="1.6" y2="-4.95" width="0.2" layer="21"/>
<wire x1="1.6" y1="-4.95" x2="-1.6" y2="-4.95" width="0.2" layer="21"/>
<wire x1="-1.6" y1="-4.95" x2="-1.6" y2="4.95" width="0.2" layer="21"/>
<wire x1="-3.5" y1="5.12" x2="-1.95" y2="5.12" width="0.2" layer="21"/>
</package>
</packages>
</library>
</libraries>
<attributes>
</attributes>
<variantdefs>
</variantdefs>
<classes>
<class number="0" name="default" width="0" drill="0">
</class>
</classes>
<designrules name="default">
<description language="de">EAGLE Design Rules

Die Standard-Design-Rules sind so gewählt, dass sie für
die meisten Anwendungen passen. Sollte ihre Platine
besondere Anforderungen haben, treffen Sie die erforderlichen
Einstellungen hier und speichern die Design Rules unter
einem neuen Namen ab.</description>
<description language="en">EAGLE Design Rules

The default Design Rules have been set to cover
a wide range of applications. Your particular design
may have different requirements, so please make the
necessary adjustments and save your customized
design rules under a new name.</description>
<param name="layerSetup" value="(1*16)"/>
<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>
<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>
<param name="mdWireWire" value="6mil"/>
<param name="mdWirePad" value="6mil"/>
<param name="mdWireVia" value="6mil"/>
<param name="mdPadPad" value="6mil"/>
<param name="mdPadVia" value="6mil"/>
<param name="mdViaVia" value="6mil"/>
<param name="mdSmdPad" value="6mil"/>
<param name="mdSmdVia" value="6mil"/>
<param name="mdSmdSmd" value="6mil"/>
<param name="mdViaViaSameLayer" value="6mil"/>
<param name="mnLayersViaInSmd" value="2"/>
<param name="mdCopperDimension" value="40mil"/>
<param name="mdDrill" value="6mil"/>
<param name="mdSmdStop" value="0mil"/>
<param name="msWidth" value="6mil"/>
<param name="msDrill" value="0.35mm"/>
<param name="msMicroVia" value="9.99mm"/>
<param name="msBlindViaRatio" value="0.5"/>
<param name="rvPadTop" value="0.25"/>
<param name="rvPadInner" value="0.25"/>
<param name="rvPadBottom" value="0.25"/>
<param name="rvViaOuter" value="0.25"/>
<param name="rvViaInner" value="0.25"/>
<param name="rvMicroViaOuter" value="0.25"/>
<param name="rvMicroViaInner" value="0.25"/>
<param name="rlMinPadTop" value="10mil"/>
<param name="rlMaxPadTop" value="20mil"/>
<param name="rlMinPadInner" value="10mil"/>
<param name="rlMaxPadInner" value="20mil"/>
<param name="rlMinPadBottom" value="10mil"/>
<param name="rlMaxPadBottom" value="20mil"/>
<param name="rlMinViaOuter" value="8mil"/>
<param name="rlMaxViaOuter" value="20mil"/>
<param name="rlMinViaInner" value="8mil"/>
<param name="rlMaxViaInner" value="20mil"/>
<param name="rlMinMicroViaOuter" value="4mil"/>
<param name="rlMaxMicroViaOuter" value="20mil"/>
<param name="rlMinMicroViaInner" value="4mil"/>
<param name="rlMaxMicroViaInner" value="20mil"/>
<param name="psTop" value="-1"/>
<param name="psBottom" value="-1"/>
<param name="psFirst" value="-1"/>
<param name="psElongationLong" value="100"/>
<param name="psElongationOffset" value="100"/>
<param name="mvStopFrame" value="1"/>
<param name="mvCreamFrame" value="0"/>
<param name="mlMinStopFrame" value="4mil"/>
<param name="mlMaxStopFrame" value="4mil"/>
<param name="mlMinCreamFrame" value="0mil"/>
<param name="mlMaxCreamFrame" value="0mil"/>
<param name="mlViaStopLimit" value="0mil"/>
<param name="srRoundness" value="0"/>
<param name="srMinRoundness" value="0mil"/>
<param name="srMaxRoundness" value="0mil"/>
<param name="slThermalIsolate" value="10mil"/>
<param name="slThermalsForVias" value="0"/>
<param name="dpMaxLengthDifference" value="10mm"/>
<param name="dpGapFactor" value="2.5"/>
<param name="checkAngle" value="0"/>
<param name="checkFont" value="1"/>
<param name="checkRestrict" value="1"/>
<param name="checkStop" value="0"/>
<param name="checkValues" value="0"/>
<param name="checkNames" value="1"/>
<param name="checkWireStubs" value="1"/>
<param name="checkPolygonWidth" value="0"/>
<param name="useDiameter" value="13"/>
<param name="maxErrors" value="50"/>
</designrules>
<autorouter>
<pass name="Default">
<param name="RoutingGrid" value="50mil"/>
<param name="AutoGrid" value="1"/>
<param name="Efforts" value="0"/>
<param name="TopRouterVariant" value="1"/>
<param name="tpViaShape" value="round"/>
<param name="PrefDir.1" value="a"/>
<param name="PrefDir.2" value="0"/>
<param name="PrefDir.3" value="0"/>
<param name="PrefDir.4" value="0"/>
<param name="PrefDir.5" value="0"/>
<param name="PrefDir.6" value="0"/>
<param name="PrefDir.7" value="0"/>
<param name="PrefDir.8" value="0"/>
<param name="PrefDir.9" value="0"/>
<param name="PrefDir.10" value="0"/>
<param name="PrefDir.11" value="0"/>
<param name="PrefDir.12" value="0"/>
<param name="PrefDir.13" value="0"/>
<param name="PrefDir.14" value="0"/>
<param name="PrefDir.15" value="0"/>
<param name="PrefDir.16" value="a"/>
<param name="cfVia" value="8"/>
<param name="cfNonPref" value="5"/>
<param name="cfChangeDir" value="2"/>
<param name="cfOrthStep" value="2"/>
<param name="cfDiagStep" value="3"/>
<param name="cfExtdStep" value="0"/>
<param name="cfBonusStep" value="1"/>
<param name="cfMalusStep" value="1"/>
<param name="cfPadImpact" value="4"/>
<param name="cfSmdImpact" value="4"/>
<param name="cfBusImpact" value="0"/>
<param name="cfHugging" value="3"/>
<param name="cfAvoid" value="4"/>
<param name="cfPolygon" value="10"/>
<param name="cfBase.1" value="0"/>
<param name="cfBase.2" value="1"/>
<param name="cfBase.3" value="1"/>
<param name="cfBase.4" value="1"/>
<param name="cfBase.5" value="1"/>
<param name="cfBase.6" value="1"/>
<param name="cfBase.7" value="1"/>
<param name="cfBase.8" value="1"/>
<param name="cfBase.9" value="1"/>
<param name="cfBase.10" value="1"/>
<param name="cfBase.11" value="1"/>
<param name="cfBase.12" value="1"/>
<param name="cfBase.13" value="1"/>
<param name="cfBase.14" value="1"/>
<param name="cfBase.15" value="1"/>
<param name="cfBase.16" value="0"/>
<param name="mnVias" value="20"/>
<param name="mnSegments" value="9999"/>
<param name="mnExtdSteps" value="9999"/>
<param name="mnRipupLevel" value="10"/>
<param name="mnRipupSteps" value="100"/>
<param name="mnRipupTotal" value="100"/>
</pass>
<pass name="Follow-me" refer="Default" active="yes">
</pass>
<pass name="Busses" refer="Default" active="yes">
<param name="cfNonPref" value="4"/>
<param name="cfBusImpact" value="4"/>
<param name="cfHugging" value="0"/>
<param name="mnVias" value="0"/>
</pass>
<pass name="Route" refer="Default" active="yes">
</pass>
<pass name="Optimize1" refer="Default" active="yes">
<param name="cfVia" value="99"/>
<param name="cfExtdStep" value="10"/>
<param name="cfHugging" value="1"/>
<param name="mnExtdSteps" value="1"/>
<param name="mnRipupLevel" value="0"/>
</pass>
<pass name="Optimize2" refer="Optimize1" active="yes">
<param name="cfNonPref" value="0"/>
<param name="cfChangeDir" value="6"/>
<param name="cfExtdStep" value="0"/>
<param name="cfBonusStep" value="2"/>
<param name="cfMalusStep" value="2"/>
<param name="cfPadImpact" value="2"/>
<param name="cfSmdImpact" value="2"/>
<param name="cfHugging" value="0"/>
</pass>
<pass name="Optimize3" refer="Optimize2" active="yes">
<param name="cfChangeDir" value="8"/>
<param name="cfPadImpact" value="0"/>
<param name="cfSmdImpact" value="0"/>
</pass>
<pass name="Optimize4" refer="Optimize3" active="yes">
<param name="cfChangeDir" value="25"/>
</pass>
</autorouter>
<elements>
<element name="CPU_AND0" library="SamacSys_Parts" package="DIP794W53P254L1930H508Q14N" value="SN74LS08N" x="160.02" y="120.65" smashed="yes">
<attribute name="DESCRIPTION" value="Quad 2i/p AND gate,SN74LS08N DIP14 25pcs" x="218.44" y="-17.78" size="1.778" layer="27" display="off"/>
<attribute name="HEIGHT" value="5.08mm" x="218.44" y="-17.78" size="1.778" layer="27" display="off"/>
<attribute name="MANUFACTURER_NAME" value="Texas Instruments" x="218.44" y="-17.78" size="1.778" layer="27" display="off"/>
<attribute name="MANUFACTURER_PART_NUMBER" value="SN74LS08N" x="218.44" y="-17.78" size="1.778" layer="27" display="off"/>
<attribute name="MOUSER_PART_NUMBER" value="595-SN74LS08N" x="218.44" y="-17.78" size="1.778" layer="27" display="off"/>
<attribute name="MOUSER_PRICE-STOCK" value="https://www.mouser.com/Search/Refine.aspx?Keyword=595-SN74LS08N" x="218.44" y="-17.78" size="1.778" layer="27" display="off"/>
<attribute name="NAME" x="160.02" y="109.22" size="1.27" layer="25" align="center"/>
<attribute name="RS_PART_NUMBER" value="0307519P" x="218.44" y="-17.78" size="1.778" layer="27" display="off"/>
<attribute name="RS_PRICE-STOCK" value="http://uk.rs-online.com/web/p/products/0307519P" x="218.44" y="-17.78" size="1.778" layer="27" display="off"/>
<attribute name="VALUE" x="160.02" y="132.08" size="1.27" layer="27" align="center"/>
</element>
<element name="CPU_LRAM" library="SamacSys_Parts" package="DIP851W46P254L3556H330Q28N" value="71256SA12TPG" x="132.08" y="78.74" smashed="yes" rot="R270">
<attribute name="DESCRIPTION" value="SRAM 32Kx8 ASYNCHRONOUS 5.0V STATIC RAM" x="22.86" y="-17.78" size="1.778" layer="27" rot="R270" display="off"/>
<attribute name="HEIGHT" value="3.302mm" x="22.86" y="-17.78" size="1.778" layer="27" rot="R270" display="off"/>
<attribute name="MANUFACTURER_NAME" value="Renesas / IDT" x="22.86" y="-17.78" size="1.778" layer="27" rot="R270" display="off"/>
<attribute name="MANUFACTURER_PART_NUMBER" value="71256SA12TPG" x="22.86" y="-17.78" size="1.778" layer="27" rot="R270" display="off"/>
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</signal>
<signal name="CPU.A15">
<contactref element="CPU" pad="5"/>
<contactref element="CPU_NAND0" pad="5"/>
<wire x1="94.808" y1="128.27" x2="156.05" y2="93.98" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="LRAM.!CS">
<contactref element="CPU_LRAM" pad="20"/>
<contactref element="CPU_NOT0" pad="10"/>
<wire x1="128.27" y1="74.486" x2="163.99" y2="69.85" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.A14">
<contactref element="CPU_LRAM" pad="1"/>
<contactref element="CPU" pad="4"/>
<contactref element="CPU_NAND0" pad="2"/>
<contactref element="CPU_HRAM0" pad="30"/>
<contactref element="CPU_HRAM1" pad="30"/>
<contactref element="CPU_HRAM2" pad="30"/>
<contactref element="CPU_HRAM3" pad="30"/>
<wire x1="156.05" y1="101.6" x2="148.298" y2="106.045" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="106.045" x2="148.298" y2="106.045" width="0" layer="19" extent="1-1"/>
<wire x1="148.59" y1="82.994" x2="156.05" y2="101.6" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="136.525" x2="148.298" y2="106.045" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="136.525" x2="148.298" y2="136.525" width="0" layer="19" extent="1-1"/>
<wire x1="94.808" y1="130.81" x2="129.248" y2="136.525" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.A12">
<contactref element="CPU_LRAM" pad="2"/>
<contactref element="CPU_ROM" pad="2"/>
<contactref element="CPU" pad="2"/>
<contactref element="CPU_HRAM0" pad="21"/>
<contactref element="CPU_HRAM1" pad="21"/>
<contactref element="CPU_HRAM2" pad="21"/>
<contactref element="CPU_HRAM3" pad="21"/>
<wire x1="94.808" y1="135.89" x2="146.05" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="146.05" y1="82.994" x2="146.05" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="125.095" x2="146.05" y2="82.994" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="94.615" x2="129.248" y2="125.095" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="125.095" x2="129.248" y2="94.615" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="94.615" x2="148.298" y2="125.095" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.A7">
<contactref element="CPU_LRAM" pad="3"/>
<contactref element="CPU_ROM" pad="3"/>
<contactref element="CPU" pad="37"/>
<contactref element="CPU_HRAM0" pad="16"/>
<contactref element="CPU_HRAM1" pad="16"/>
<contactref element="CPU_HRAM2" pad="16"/>
<contactref element="CPU_HRAM3" pad="16"/>
<wire x1="110.932" y1="130.81" x2="143.51" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="143.51" y1="82.994" x2="143.51" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="120.015" x2="143.51" y2="82.994" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="89.535" x2="119.672" y2="120.015" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="120.015" x2="119.672" y2="89.535" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="89.535" x2="138.722" y2="120.015" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.A6">
<contactref element="CPU_LRAM" pad="4"/>
<contactref element="CPU_ROM" pad="4"/>
<contactref element="CPU" pad="36"/>
<contactref element="CPU_HRAM0" pad="15"/>
<contactref element="CPU_HRAM1" pad="15"/>
<contactref element="CPU_HRAM2" pad="15"/>
<contactref element="CPU_HRAM3" pad="15"/>
<wire x1="110.932" y1="128.27" x2="140.97" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="140.97" y1="82.994" x2="140.97" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="121.285" x2="140.97" y2="82.994" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="90.805" x2="119.672" y2="121.285" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="121.285" x2="119.672" y2="90.805" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="90.805" x2="138.722" y2="121.285" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.A5">
<contactref element="CPU_LRAM" pad="5"/>
<contactref element="CPU_ROM" pad="5"/>
<contactref element="CPU" pad="35"/>
<contactref element="CPU_HRAM0" pad="14"/>
<contactref element="CPU_HRAM1" pad="14"/>
<contactref element="CPU_HRAM2" pad="14"/>
<contactref element="CPU_HRAM3" pad="14"/>
<wire x1="110.932" y1="125.73" x2="138.43" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="138.43" y1="82.994" x2="138.43" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="122.555" x2="138.43" y2="82.994" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="92.075" x2="119.672" y2="122.555" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="122.555" x2="119.672" y2="92.075" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="92.075" x2="138.722" y2="122.555" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.A4">
<contactref element="CPU_LRAM" pad="6"/>
<contactref element="CPU_ROM" pad="6"/>
<contactref element="CPU" pad="34"/>
<contactref element="CPU_HRAM0" pad="13"/>
<contactref element="CPU_HRAM1" pad="13"/>
<contactref element="CPU_HRAM2" pad="13"/>
<contactref element="CPU_HRAM3" pad="13"/>
<wire x1="110.932" y1="123.19" x2="135.89" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="135.89" y1="82.994" x2="135.89" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="123.825" x2="135.89" y2="82.994" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="93.345" x2="119.672" y2="123.825" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="123.825" x2="119.672" y2="93.345" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="93.345" x2="138.722" y2="123.825" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.A3">
<contactref element="CPU_LRAM" pad="7"/>
<contactref element="CPU_ROM" pad="7"/>
<contactref element="CPU" pad="33"/>
<contactref element="CPU_HRAM0" pad="4"/>
<contactref element="CPU_HRAM1" pad="4"/>
<contactref element="CPU_HRAM2" pad="4"/>
<contactref element="CPU_HRAM3" pad="4"/>
<wire x1="110.932" y1="120.65" x2="133.35" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="133.35" y1="82.994" x2="133.35" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="135.255" x2="133.35" y2="82.994" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="104.775" x2="119.672" y2="135.255" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="135.255" x2="119.672" y2="104.775" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="104.775" x2="138.722" y2="135.255" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.A2">
<contactref element="CPU_LRAM" pad="8"/>
<contactref element="CPU_ROM" pad="8"/>
<contactref element="CPU" pad="32"/>
<contactref element="CPU_HRAM0" pad="3"/>
<contactref element="CPU_HRAM1" pad="3"/>
<contactref element="CPU_HRAM2" pad="3"/>
<contactref element="CPU_HRAM3" pad="3"/>
<wire x1="110.932" y1="118.11" x2="130.81" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="130.81" y1="82.994" x2="130.81" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="136.525" x2="130.81" y2="82.994" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="106.045" x2="119.672" y2="136.525" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="136.525" x2="119.672" y2="106.045" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="106.045" x2="138.722" y2="136.525" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.A1">
<contactref element="CPU_LRAM" pad="9"/>
<contactref element="CPU_ROM" pad="9"/>
<contactref element="CPU" pad="31"/>
<contactref element="CPU_HRAM0" pad="2"/>
<contactref element="CPU_HRAM1" pad="2"/>
<contactref element="CPU_HRAM2" pad="2"/>
<contactref element="CPU_HRAM3" pad="2"/>
<wire x1="110.932" y1="115.57" x2="128.27" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="128.27" y1="82.994" x2="128.27" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="137.795" x2="128.27" y2="82.994" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="107.315" x2="119.672" y2="137.795" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="137.795" x2="119.672" y2="107.315" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="107.315" x2="138.722" y2="137.795" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.A0">
<contactref element="CPU_LRAM" pad="10"/>
<contactref element="CPU_ROM" pad="10"/>
<contactref element="CPU_HRAM0" pad="1"/>
<contactref element="CPU_HRAM1" pad="1"/>
<contactref element="CPU_HRAM2" pad="1"/>
<contactref element="CPU_HRAM3" pad="1"/>
<wire x1="125.73" y1="82.994" x2="125.73" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="139.065" x2="125.73" y2="82.994" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="108.585" x2="119.672" y2="139.065" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="139.065" x2="119.672" y2="108.585" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="108.585" x2="138.722" y2="139.065" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.D0">
<contactref element="CPU_LRAM" pad="11"/>
<contactref element="CPU_ROM" pad="11"/>
<contactref element="CPU" pad="14"/>
<contactref element="HRAM_SEL" pad="3"/>
<contactref element="CPU_HRAM0" pad="6"/>
<contactref element="CPU_HRAM1" pad="6"/>
<contactref element="CPU_HRAM2" pad="6"/>
<contactref element="CPU_HRAM3" pad="6"/>
<wire x1="94.808" y1="105.41" x2="123.19" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="123.19" y1="82.994" x2="123.19" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="132.715" x2="123.19" y2="82.994" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="102.235" x2="119.672" y2="132.715" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="132.715" x2="119.672" y2="102.235" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="102.235" x2="138.722" y2="132.715" width="0" layer="19" extent="1-1"/>
<wire x1="123.19" y1="145.89" x2="119.672" y2="102.235" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.D1">
<contactref element="CPU_LRAM" pad="12"/>
<contactref element="CPU_ROM" pad="12"/>
<contactref element="CPU" pad="15"/>
<contactref element="HRAM_SEL" pad="4"/>
<contactref element="CPU_HRAM0" pad="7"/>
<contactref element="CPU_HRAM1" pad="7"/>
<contactref element="CPU_HRAM2" pad="7"/>
<contactref element="CPU_HRAM3" pad="7"/>
<wire x1="94.808" y1="102.87" x2="120.65" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x

extension: brd


text:
1="120.65" y1="82.994" x2="120.65" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="131.445" x2="120.65" y2="82.994" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="100.965" x2="119.672" y2="131.445" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="131.445" x2="119.672" y2="100.965" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="100.965" x2="138.722" y2="131.445" width="0" layer="19" extent="1-1"/>
<wire x1="125.73" y1="145.89" x2="119.672" y2="100.965" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.D2">
<contactref element="CPU_LRAM" pad="13"/>
<contactref element="CPU_ROM" pad="13"/>
<contactref element="CPU" pad="12"/>
<contactref element="HRAM_SEL" pad="5"/>
<contactref element="CPU_HRAM0" pad="10"/>
<contactref element="CPU_HRAM1" pad="10"/>
<contactref element="CPU_HRAM2" pad="10"/>
<contactref element="CPU_HRAM3" pad="10"/>
<wire x1="94.808" y1="110.49" x2="118.11" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="118.11" y1="82.994" x2="118.11" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="127.635" x2="118.11" y2="82.994" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="97.155" x2="119.672" y2="127.635" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="127.635" x2="119.672" y2="97.155" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="97.155" x2="138.722" y2="127.635" width="0" layer="19" extent="1-1"/>
<wire x1="128.27" y1="145.89" x2="119.672" y2="97.155" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="GND">
<contactref element="CPU_LRAM" pad="14"/>
<contactref element="CPU_ROM" pad="14"/>
<contactref element="CPU" pad="29"/>
<contactref element="CPU_ROM_DELAY" pad="8"/>
<contactref element="CPU_OR0" pad="7"/>
<contactref element="CPU_AND0" pad="7"/>
<contactref element="CPU_NOT0" pad="7"/>
<contactref element="CPU_NAND0" pad="7"/>
<contactref element="HRAM_DECODE" pad="8"/>
<contactref element="HRAM_SEL" pad="8"/>
<contactref element="CPU_HRAM0" pad="9"/>
<contactref element="CPU_HRAM0" pad="25"/>
<contactref element="CPU_HRAM1" pad="9"/>
<contactref element="CPU_HRAM1" pad="25"/>
<contactref element="CPU_HRAM2" pad="9"/>
<contactref element="CPU_HRAM2" pad="25"/>
<contactref element="CPU_HRAM3" pad="9"/>
<contactref element="CPU_HRAM3" pad="25"/>
<wire x1="129.248" y1="130.175" x2="119.672" y2="128.905" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="128.905" x2="129.248" y2="130.175" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="130.175" x2="138.722" y2="128.905" width="0" layer="19" extent="1-1"/>
<wire x1="156.05" y1="137.16" x2="148.298" y2="130.175" width="0" layer="19" extent="1-1"/>
<wire x1="143.325" y1="145.415" x2="156.05" y2="137.16" width="0" layer="19" extent="1-1"/>
<wire x1="135.89" y1="145.89" x2="143.325" y2="145.415" width="0" layer="19" extent="1-1"/>
<wire x1="156.05" y1="113.03" x2="148.298" y2="130.175" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="99.695" x2="156.05" y2="113.03" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="98.425" x2="148.298" y2="99.695" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="99.695" x2="138.722" y2="98.425" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="98.425" x2="129.248" y2="99.695" width="0" layer="19" extent="1-1"/>
<wire x1="156.05" y1="88.9" x2="148.298" y2="99.695" width="0" layer="19" extent="1-1"/>
<wire x1="110.932" y1="110.49" x2="119.672" y2="98.425" width="0" layer="19" extent="1-1"/>
<wire x1="115.57" y1="82.994" x2="119.672" y2="98.425" width="0" layer="19" extent="1-1"/>
<wire x1="115.57" y1="68.739" x2="115.57" y2="82.994" width="0" layer="19" extent="1-1"/>
<wire x1="101.44" y1="64.77" x2="115.57" y2="68.739" width="0" layer="19" extent="1-1"/>
<wire x1="156.05" y1="64.77" x2="156.05" y2="88.9" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="+5VDC">
<contactref element="CPU_LRAM" pad="28"/>
<contactref element="CPU_ROM" pad="28"/>
<contactref element="CPU_ROM" pad="27"/>
<contactref element="CPU" pad="11"/>
<contactref element="CPU_ROM_DELAY" pad="9"/>
<contactref element="CPU_ROM_DELAY" pad="16"/>
<contactref element="CPU_OR0" pad="14"/>
<contactref element="CPU_AND0" pad="14"/>
<contactref element="CPU_NOT0" pad="14"/>
<contactref element="CPU_NAND0" pad="14"/>
<contactref element="HRAM_DECODE" pad="16"/>
<contactref element="HRAM_SEL" pad="16"/>
<contactref element="HRAM_SEL" pad="1"/>
<contactref element="CPU_HRAM0" pad="8"/>
<contactref element="CPU_HRAM0" pad="24"/>
<contactref element="CPU_HRAM1" pad="8"/>
<contactref element="CPU_HRAM1" pad="24"/>
<contactref element="CPU_HRAM2" pad="8"/>
<contactref element="CPU_HRAM2" pad="24"/>
<contactref element="CPU_HRAM3" pad="8"/>
<contactref element="CPU_HRAM3" pad="24"/>
<wire x1="109.38" y1="64.77" x2="109.38" y2="82.55" width="0" layer="19" extent="1-1"/>
<wire x1="148.59" y1="53.181" x2="109.38" y2="82.55" width="0" layer="19" extent="1-1"/>
<wire x1="146.05" y1="53.181" x2="148.59" y2="53.181" width="0" layer="19" extent="1-1"/>
<wire x1="148.59" y1="74.486" x2="109.38" y2="64.77" width="0" layer="19" extent="1-1"/>
<wire x1="94.808" y1="113.03" x2="109.38" y2="64.77" width="0" layer="19" extent="1-1"/>
<wire x1="163.99" y1="104.14" x2="148.59" y2="74.486" width="0" layer="19" extent="1-1"/>
<wire x1="163.99" y1="128.27" x2="163.99" y2="104.14" width="0" layer="19" extent="1-1"/>
<wire x1="163.99" y1="152.4" x2="163.99" y2="104.14" width="0" layer="19" extent="1-1"/>
<wire x1="163.99" y1="80.01" x2="163.99" y2="152.4" width="0" layer="19" extent="1-1"/>
<wire x1="118.11" y1="153.83" x2="163.99" y2="80.01" width="0" layer="19" extent="1-1"/>
<wire x1="118.11" y1="145.89" x2="118.11" y2="153.83" width="0" layer="19" extent="1-1"/>
<wire x1="148.775" y1="154.305" x2="118.11" y2="153.83" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="128.905" x2="148.775" y2="154.305" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="130.175" x2="129.248" y2="128.905" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="98.425" x2="148.775" y2="154.305" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="99.695" x2="129.248" y2="98.425" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="128.905" x2="119.672" y2="99.695" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="130.175" x2="148.298" y2="128.905" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="98.425" x2="138.722" y2="130.175" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="99.695" x2="148.298" y2="98.425" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.A13">
<contactref element="CPU_LRAM" pad="26"/>
<contactref element="CPU" pad="3"/>
<contactref element="CPU_HRAM0" pad="29"/>
<contactref element="CPU_HRAM1" pad="29"/>
<contactref element="CPU_HRAM2" pad="29"/>
<contactref element="CPU_HRAM3" pad="29"/>
<contactref element="CPU_NAND0" pad="1"/>
<wire x1="156.05" y1="104.14" x2="148.298" y2="104.775" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="104.775" x2="148.298" y2="104.775" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="135.255" x2="148.298" y2="104.775" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="135.255" x2="148.298" y2="135.255" width="0" layer="19" extent="1-1"/>
<wire x1="143.51" y1="74.486" x2="148.298" y2="104.775" width="0" layer="19" extent="1-1"/>
<wire x1="94.808" y1="133.35" x2="129.248" y2="135.255" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.A8">
<contactref element="CPU_LRAM" pad="25"/>
<contactref element="CPU_ROM" pad="25"/>
<contactref element="CPU" pad="38"/>
<contactref element="CPU_HRAM0" pad="17"/>
<contactref element="CPU_HRAM1" pad="17"/>
<contactref element="CPU_HRAM2" pad="17"/>
<contactref element="CPU_HRAM3" pad="17"/>
<wire x1="140.97" y1="53.181" x2="110.932" y2="133.35" width="0" layer="19" extent="1-1"/>
<wire x1="140.97" y1="74.486" x2="140.97" y2="53.181" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="120.015" x2="140.97" y2="74.486" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="89.535" x2="129.248" y2="120.015" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="120.015" x2="129.248" y2="89.535" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="89.535" x2="148.298" y2="120.015" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.A9">
<contactref element="CPU_LRAM" pad="24"/>
<contactref element="CPU_ROM" pad="24"/>
<contactref element="CPU" pad="39"/>
<contactref element="CPU_HRAM0" pad="18"/>
<contactref element="CPU_HRAM1" pad="18"/>
<contactref element="CPU_HRAM2" pad="18"/>
<contactref element="CPU_HRAM3" pad="18"/>
<wire x1="138.43" y1="53.181" x2="110.932" y2="135.89" width="0" layer="19" extent="1-1"/>
<wire x1="138.43" y1="74.486" x2="138.43" y2="53.181" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="121.285" x2="138.43" y2="74.486" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="90.805" x2="129.248" y2="121.285" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="121.285" x2="129.248" y2="90.805" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="90.805" x2="148.298" y2="121.285" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.A11">
<contactref element="CPU_LRAM" pad="23"/>
<contactref element="CPU_ROM" pad="23"/>
<contactref element="CPU" pad="1"/>
<contactref element="CPU_HRAM0" pad="20"/>
<contactref element="CPU_HRAM1" pad="20"/>
<contactref element="CPU_HRAM2" pad="20"/>
<contactref element="CPU_HRAM3" pad="20"/>
<wire x1="135.89" y1="53.181" x2="135.89" y2="74.486" width="0" layer="19" extent="1-1"/>
<wire x1="94.808" y1="138.43" x2="135.89" y2="53.181" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="123.825" x2="135.89" y2="74.486" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="93.345" x2="129.248" y2="123.825" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="123.825" x2="129.248" y2="93.345" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="93.345" x2="148.298" y2="123.825" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="RAM.!OE">
<contactref element="CPU_LRAM" pad="22"/>
<contactref element="CPU_HRAM0" pad="28"/>
<contactref element="CPU_HRAM1" pad="28"/>
<contactref element="CPU_HRAM2" pad="28"/>
<contactref element="CPU_HRAM3" pad="28"/>
<contactref element="CPU_OR0" pad="6"/>
<wire x1="129.248" y1="103.505" x2="148.298" y2="103.505" width="0" layer="19" extent="1-1"/>
<wire x1="133.35" y1="74.486" x2="129.248" y2="103.505" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="133.985" x2="148.298" y2="103.505" width="0" layer="19" extent="1-1"/>
<wire x1="156.05" y1="139.7" x2="148.298" y2="133.985" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="133.985" x2="148.298" y2="133.985" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.A10">
<contactref element="CPU_LRAM" pad="21"/>
<contactref element="CPU_ROM" pad="21"/>
<contactref element="CPU" pad="40"/>
<contactref element="CPU_HRAM0" pad="19"/>
<contactref element="CPU_HRAM1" pad="19"/>
<contactref element="CPU_HRAM2" pad="19"/>
<contactref element="CPU_HRAM3" pad="19"/>
<wire x1="130.81" y1="74.486" x2="130.81" y2="53.181" width="0" layer="19" extent="1-1"/>
<wire x1="110.932" y1="138.43" x2="130.81" y2="53.181" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="122.555" x2="130.81" y2="74.486" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="92.075" x2="129.248" y2="122.555" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="122.555" x2="129.248" y2="92.075" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="92.075" x2="148.298" y2="122.555" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.D7">
<contactref element="CPU_LRAM" pad="19"/>
<contactref element="CPU_ROM" pad="19"/>
<contactref element="CPU" pad="13"/>
<contactref element="CPU_HRAM0" pad="27"/>
<contactref element="CPU_HRAM1" pad="27"/>
<contactref element="CPU_HRAM2" pad="27"/>
<contactref element="CPU_HRAM3" pad="27"/>
<wire x1="125.73" y1="74.486" x2="125.73" y2="53.181" width="0" layer="19" extent="1-1"/>
<wire x1="94.808" y1="107.95" x2="125.73" y2="53.181" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="132.715" x2="125.73" y2="74.486" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="102.235" x2="129.248" y2="132.715" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="132.715" x2="129.248" y2="102.235" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="102.235" x2="148.298" y2="132.715" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.D6">
<contactref element="CPU_LRAM" pad="18"/>
<contactref element="CPU_ROM" pad="18"/>
<contactref element="CPU" pad="10"/>
<contactref element="CPU_HRAM0" pad="26"/>
<contactref element="CPU_HRAM1" pad="26"/>
<contactref element="CPU_HRAM2" pad="26"/>
<contactref element="CPU_HRAM3" pad="26"/>
<wire x1="123.19" y1="74.486" x2="123.19" y2="53.181" width="0" layer="19" extent="1-1"/>
<wire x1="94.808" y1="115.57" x2="123.19" y2="53.181" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="131.445" x2="123.19" y2="74.486" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="100.965" x2="129.248" y2="131.445" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="131.445" x2="129.248" y2="100.965" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="100.965" x2="148.298" y2="131.445" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.D5">
<contactref element="CPU_LRAM" pad="17"/>
<contactref element="CPU_ROM" pad="17"/>
<contactref element="CPU" pad="9"/>
<contactref element="CPU_HRAM0" pad="23"/>
<contactref element="CPU_HRAM1" pad="23"/>
<contactref element="CPU_HRAM2" pad="23"/>
<contactref element="CPU_HRAM3" pad="23"/>
<wire x1="120.65" y1="74.486" x2="120.65" y2="53.181" width="0" layer="19" extent="1-1"/>
<wire x1="94.808" y1="118.11" x2="120.65" y2="53.181" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="127.635" x2="120.65" y2="74.486" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="97.155" x2="129.248" y2="127.635" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="127.635" x2="129.248" y2="97.155" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="97.155" x2="148.298" y2="127.635" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.D4">
<contactref element="CPU_LRAM" pad="16"/>
<contactref element="CPU_ROM" pad="16"/>
<contactref element="CPU" pad="7"/>
<contactref element="CPU_HRAM0" pad="22"/>
<contactref element="CPU_HRAM1" pad="22"/>
<contactref element="CPU_HRAM2" pad="22"/>
<contactref element="CPU_HRAM3" pad="22"/>
<wire x1="118.11" y1="74.486" x2="118.11" y2="53.181" width="0" layer="19" extent="1-1"/>
<wire x1="94.808" y1="123.19" x2="118.11" y2="53.181" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="126.365" x2="118.11" y2="74.486" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="95.885" x2="129.248" y2="126.365" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="126.365" x2="129.248" y2="95.885" width="0" layer="19" extent="1-1"/>
<wire x1="148.298" y1="95.885" x2="148.298" y2="126.365" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.D3">
<contactref element="CPU_LRAM" pad="15"/>
<contactref element="CPU_ROM" pad="15"/>
<contactref element="CPU" pad="8"/>
<contactref element="HRAM_SEL" pad="6"/>
<contactref element="CPU_HRAM0" pad="11"/>
<contactref element="CPU_HRAM1" pad="11"/>
<contactref element="CPU_HRAM2" pad="11"/>
<contactref element="CPU_HRAM3" pad="11"/>
<wire x1="115.57" y1="74.486" x2="115.57" y2="53.181" width="0" layer="19" extent="1-1"/>
<wire x1="94.808" y1="120.65" x2="115.57" y2="53.181" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="126.365" x2="115.57" y2="74.486" width="0" layer="19" extent="1-1"/>
<wire x1="119.672" y1="95.885" x2="119.672" y2="126.365" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="126.365" x2="119.672" y2="95.885" width="0" layer="19" extent="1-1"/>
<wire x1="138.722" y1="95.885" x2="138.722" y2="126.365" width="0" layer="19" extent="1-1"/>
<wire x1="130.81" y1="145.89" x2="119.672" y2="95.885" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU_ROM_CLK.QC">
<contactref element="CPU_ROM_DELAY" pad="12"/>
<contactref element="CPU_AND0" pad="2"/>
<contactref element="CPU_NOT0" pad="5"/>
<wire x1="156.05" y1="125.73" x2="109.38" y2="72.39" width="0" layer="19" extent="1-1"/>
<wire x1="156.05" y1="69.85" x2="156.05" y2="125.73" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="N$4">
<contactref element="CPU_AND0" pad="3"/>
<contactref element="CPU_AND0" pad="4"/>
<wire x1="156.05" y1="120.65" x2="156.05" y2="123.19" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="RAM.!CE">
<contactref element="CPU_AND0" pad="5"/>
</signal>
<signal name="CPU_ROM_CLK.COMPL">
<contactref element="CPU_AND0" pad="6"/>
<contactref element="CPU_OR0" pad="2"/>
<wire x1="156.05" y1="115.57" x2="156.05" y2="149.86" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU_ROM_CLK.CLR">
<contactref element="CPU_OR0" pad="3"/>
<contactref element="CPU_NOT0" pad="3"/>
<wire x1="156.05" y1="74.93" x2="156.05" y2="147.32" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.MREQ">
<contactref element="CPU_NOT0" pad="2"/>
<contactref element="CPU_OR0" pad="1"/>
<contactref element="CPU_AND0" pad="12"/>
<wire x1="156.05" y1="77.47" x2="156.05" y2="152.4" width="0" layer="19" extent="1-1"/>
<wire x1="163.99" y1="123.19" x2="156.05" y2="77.47" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU_ROM_CLK.!CLR">
<contactref element="CPU_NOT0" pad="4"/>
<contactref element="CPU_ROM_DELAY" pad="1"/>
<wire x1="156.05" y1="72.39" x2="101.44" y2="82.55" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU_ROM_CLK.!QC">
<contactref element="CPU_NOT0" pad="6"/>
<contactref element="CPU_AND0" pad="13"/>
<wire x1="156.05" y1="67.31" x2="163.99" y2="125.73" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="CPU.!ROM_WAIT">
<contactref element="CPU_AND0" pad="11"/>
</signal>
<signal name="LRAM.CS">
<contactref element="CPU_NAND0" pad="4"/>
<contactref element="CPU_NAND0" pad="3"/>
<contactref element="CPU_NOT0" pad="11"/>
<wire x1="156.05" y1="99.06" x2="156.05" y2="96.52" width="0" layer="19" extent="1-1"/>
<wire x1="163.99" y1="72.39" x2="156.05" y2="96.52" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="RAM.!EN">
<contactref element="CPU_NAND0" pad="6"/>
<contactref element="CPU_NOT0" pad="13"/>
<contactref element="CPU_ROM_DELAY" pad="7"/>
<contactref element="CPU_ROM_DELAY" pad="10"/>
<wire x1="163.99" y1="77.47" x2="156.05" y2="91.44" width="0" layer="19" extent="1-1"/>
<wire x1="109.38" y1="67.31" x2="156.05" y2="91.44" width="0" layer="19" extent="1-1"/>
<wire x1="101.44" y1="67.31" x2="109.38" y2="67.31" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="ROM.!EN">
<contactref element="CPU_NOT0" pad="12"/>
<contactref element="CPU_ROM" pad="22"/>
<contactref element="CPU_ROM" pad="20"/>
<wire x1="133.35" y1="53.181" x2="163.99" y2="74.93" width="0" layer="19" extent="1-1"/>
<wire x1="128.27" y1="53.181" x2="133.35" y2="53.181" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="HRAM_SEL.WR">
<contactref element="HRAM_SEL" pad="10"/>
<contactref element="HRAM_SEL" pad="9"/>
<wire x1="133.35" y1="153.83" x2="135.89" y2="153.83" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="HRAM_DECODE.A1">
<contactref element="HRAM_SEL" pad="12"/>
<contactref element="HRAM_DECODE" pad="3"/>
<wire x1="143.325" y1="151.765" x2="128.27" y2="153.83" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="HRAM_DECODE.A0">
<contactref element="HRAM_SEL" pad="13"/>
<contactref element="HRAM_DECODE" pad="2"/>
<wire x1="143.325" y1="153.035" x2="125.73" y2="153.83" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="HRAM.A16">
<contactref element="HRAM_SEL" pad="14"/>
<contactref element="CPU_HRAM0" pad="32"/>
<contactref element="CPU_HRAM1" pad="32"/>
<contactref element="CPU_HRAM2" pad="32"/>
<contactref element="CPU_HRAM3" pad="32"/>
<wire x1="148.298" y1="139.065" x2="148.298" y2="108.585" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="108.585" x2="148.298" y2="139.065" width="0" layer="19" extent="1-1"/>
<wire x1="123.19" y1="153.83" x2="129.248" y2="108.585" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="139.065" x2="123.19" y2="153.83" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="HRAM.A15">
<contactref element="HRAM_SEL" pad="15"/>
<contactref element="CPU_HRAM0" pad="31"/>
<contactref element="CPU_HRAM1" pad="31"/>
<contactref element="CPU_HRAM2" pad="31"/>
<contactref element="CPU_HRAM3" pad="31"/>
<wire x1="148.298" y1="137.795" x2="148.298" y2="107.315" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="107.315" x2="148.298" y2="137.795" width="0" layer="19" extent="1-1"/>
<wire x1="120.65" y1="153.83" x2="129.248" y2="107.315" width="0" layer="19" extent="1-1"/>
<wire x1="129.248" y1="137.795" x2="120.65" y2="153.83" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="N$50">
<contactref element="HRAM_DECODE" pad="1"/>
</signal>
<signal name="HRAM0.!CS">
<contactref element="HRAM_DECODE" pad="4"/>
<contactref element="CPU_HRAM0" pad="5"/>
<wire x1="119.672" y1="133.985" x2="143.325" y2="150.495" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="HRAM1.!CS">
<contactref element="HRAM_DECODE" pad="5"/>
<contactref element="CPU_HRAM1" pad="5"/>
<wire x1="143.325" y1="149.225" x2="119.672" y2="103.505" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="HRAM2.!CS">
<contactref element="HRAM_DECODE" pad="6"/>
<contactref element="CPU_HRAM2" pad="5"/>
<wire x1="143.325" y1="147.955" x2="138.722" y2="133.985" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="HRAM3.!CS">
<contactref element="HRAM_DECODE" pad="7"/>
<contactref element="CPU_HRAM3" pad="5"/>
<wire x1="143.325" y1="146.685" x2="138.722" y2="103.505" width="0" layer="19" extent="1-1"/>
</signal>
</signals>
<mfgpreviewcolors>
<mfgpreviewcolor name="soldermaskcolor" color="0xC8008000"/>
<mfgpreviewcolor name="silkscreencolor" color="0xFFFEFEFE"/>
<mfgpreviewcolor name="backgroundcolor" color="0xFF282828"/>
<mfgpreviewcolor name="coppercolor" color="0xFFFFBF00"/>
<mfgpreviewcolor name="substratecolor" color="0xFF786E46"/>
</mfgpreviewcolors>
</board>
</drawing>
</eagle>

license_type: permissive

branch_name: refs/heads/master


text:
package api

import (
	"encoding/json"
	"fmt"
	"io/ioutil"
	"net/http"
	"strconv"

	"github.com/cosmos/cosmos-sdk/client/flags"
	sdk "github.com/cosmos/cosmos-sdk/types"
	sdkerrors "github.com/cosmos/cosmos-sdk/types/errors"
	"github.com/cosmos/cosmos-sdk/x/auth"
	"github.com/cosmos/cosmos-sdk/x/bank"

	core "github.com/terra-project/core/types"
)

// BankSendBody contains the necessary data to make a send transaction
type BankSendBody struct {
	Sender        sdk.AccAddress `json:"sender"`
	Reciever      sdk.AccAddress `json:"reciever"`
	Amount        string         `json:"amount"`
	ChainID       string         `json:"chain_id"`
	Memo          string         `json:"memo,omitempty"`
	Fees          string         `json:"fees,omitempty"`
	Gas           string         `json:"gas,omitempty"`
	GasPrices     string         `json:"gas_prices,omitempty"`
	GasAdjustment string         `json:"gas_adjustment,omitempty"`
}

// Marshal - nolint
func (sb BankSendBody) Marshal() []byte {
	out, err := json.Marshal(sb)
	if err != nil {
		panic(err)
	}
	return out
}

// BankSend handles the /tx/bank/send route
func (s *Server) BankSend(w http.ResponseWriter, r *http.Request) {
	var sb BankSendBody

	body, err := ioutil.ReadAll(r.Body)
	if err != nil {
		w.WriteHeader(http.StatusBadRequest)
		w.Write(newError(err).marshal())
		return
	}

	err = cdc.UnmarshalJSON(body, &sb)
	if err != nil {
		w.WriteHeader(http.StatusBadRequest)
		w.Write(newError(err).marshal())
		return
	}

	coins, err := sdk.ParseCoins(sb.Amount)
	if err != nil {
		w.WriteHeader(http.StatusBadRequest)
		w.Write(newError(fmt.Errorf("failed to parse amount %s into sdk.Coins", sb.Amount)).marshal())
		return
	}

	var fees sdk.Coins
	if sb.Fees != "" {
		if sb.GasPrices != "" {
			w.WriteHeader(http.StatusBadRequest)
			w.Write(newError(fmt.Errorf("GasPrices and Fees cannot be used at the same time")).marshal())
			return
		}

		fees, err = sdk.ParseCoins(sb.Fees)
		if err != nil {
			w.WriteHeader(http.StatusBadRequest)
			w.Write(newError(fmt.Errorf("failed to parse fees %s into sdk.Coins", sb.Fees)).marshal())
			return
		}
	}

	// dummy fee & dummy gas limit
	var feesForSim sdk.Coins
	if fees.Empty() {
		feesForSim = sdk.NewCoins(sdk.NewCoin(coins[0].Denom, sdk.NewInt(1)))
	} else {
		feesForSim = sdk.NewCoins(fees...)
	}

	stdTx := auth.NewStdTx(
		[]sdk.Msg{bank.MsgSend{FromAddress: sb.Sender, ToAddress: sb.Reciever, Amount: coins}},
		auth.NewStdFee(flags.DefaultGasLimit, feesForSim),
		[]auth.StdSignature{{}},
		sb.Memo,
	)

	var gas uint64
	if sb.Gas != "" {
		gas, err = strconv.ParseUint(sb.Gas, 10, 64)
	} else {
		gas, err = s.SimulateGas(cdc.MustMarshalBinaryLengthPrefixed(stdTx))
	}

	if err != nil {
		w.WriteHeader(http.StatusBadRequest)
		w.Write(newError(fmt.Errorf("failed to parse gas %s into uint64; %s", sb.Gas, err.Error())).marshal())
		return
	}

	if gas != 0 && sb.GasAdjustment != "" {
		adj, err := strconv.ParseFloat(sb.GasAdjustment, 64)
		if err != nil {
			w.WriteHeader(http.StatusBadRequest)
			w.Write(newError(fmt.Errorf("failed to parse gasAdjustment %s into float64", sb.GasAdjustment)).marshal())
			return
		}
		gas = uint64(adj * float64(gas))
	}

	if sb.GasPrices != "" {
		gasPrices, err := sdk.ParseDecCoins(sb.GasPrices)
		if err != nil {
			w.WriteHeader(http.StatusBadRequest)
			w.Write(newError(fmt.Errorf("failed to parse gasPrices %s into sdk.DecCoins", sb.GasPrices)).marshal())
			return
		}

		for _, gasPrice := range gasPrices {
			fee := sdk.NewCoin(gasPrice.Denom, gasPrice.Amount.MulInt64(int64(gas)).Ceil().TruncateInt())
			fees = append(fees, fee)
		}

		fees = fees.Sort()
	}

	if sb.Fees == "" {
		// Compute Tax
		taxRate, err := s.LoadTaxRate()
		if err != nil {
			w.WriteHeader(http.StatusBadRequest)

			w.Write([]byte(sdkerrors.Wrap(err, "failed to load tax rate").Error()))
			return
		}

		var taxes sdk.Coins
		for _, coin := range coins {
			if coin.Denom == core.MicroLunaDenom {
				continue
			}

			taxCap, err := s.LoadTaxCap(coin.Denom)
			if err != nil {
				w.WriteHeader(http.StatusBadRequest)

				w.Write([]byte(sdkerrors.Wrap(err, "failed to load tax cap").Error()))
				return
			}

			taxDue := taxRate.MulInt(coin.Amount).TruncateInt()
			if taxDue.GT(taxCap) {
				taxDue = taxCap
			}

			taxes = append(taxes, sdk.NewCoin(coin.Denom, taxDue))
		}

		taxes = taxes.Sort()
		fees = taxes.Add(fees...)
	}

	stdTx = auth.NewStdTx(
		stdTx.Msgs,
		auth.NewStdFee(gas, fees),
		[]auth.StdSignature{},
		stdTx.Memo,
	)

	w.WriteHeader(http.StatusOK)
	w.Write(cdc.MustMarshalJSON(stdTx))
	return
}

repository: terra-money/keyserver

repo_name: terra-money/keyserver

extension: go


text:
package core

import (
	"bufio"
	"log"
	"regexp"
	"strings"
)

// Asset represents the common interface implemented by all Asset types
type Asset interface{}

type node struct {
	id       int
	parent   *node
	children []*node
}

// Style asset
type Style struct {
	Source  string
	classes []string
}

// SVG asset
type SVG struct {
	Source string
}

// Element of a component
type Element struct {
	text     string
	tag      string
	style    string
	children []Element
}

// Component asset
type Component struct {
	Source string
	Element
}

// ComponentSourceLine represents a single line of a Component source
type ComponentSourceLine struct {
	indent int
	tag    string
	text   string
	style  string
}

func parseElement(line string) ComponentSourceLine {
	pattern := `^(?P<indent>\s*)((?P<tag>\w+)\.)?(?P<style>\w+)?(\s*"(?P<text>[^"\\]*(\\.[^"\\]*)*)")?\s*$`
	pathMetadata := regexp.MustCompile(pattern)

	matches := pathMetadata.FindStringSubmatch(line)
	names := pathMetadata.SubexpNames()
	groups := make(map[string]string)

	for i, match := range matches {
		if len(names[i]) > 0 {
			groups[names[i]] = match
		}
	}
	return ComponentSourceLine{
		len(groups["indent"]),
		groups["tag"],
		strings.ReplaceAll(groups["text"], `\"`, `"`),
		groups["style"],
	}
}

func getDependencyKeys(asset Asset) []AssetKey {
	distinct := make(map[AssetKey]bool)
	keys := []AssetKey{}
	switch v := asset.(type) {
	case Component:
		distinct[AssetKey{StyleType, v.style}] = true
		// keys = append(keys, AssetKey{StyleType, v.style})
		for _, child := range v.children {
			for _, childKey := range getDependencyKeys(child) {
				distinct[childKey] = true
			}
			// keys = append(keys, getDependencyKeys(child)...)
		}
	case Element:
		distinct[AssetKey{StyleType, v.style}] = true
		// keys = append(keys, AssetKey{StyleType, v.style})
		for _, child := range v.children {
			for _, childKey := range getDependencyKeys(child) {
				distinct[childKey] = true
			}
			// keys = append(keys, getDependencyKeys(child)...)
		}
	}
	for k := range distinct {
		keys = append(keys, k)
	}
	return keys
}

// NewAssetFactory generates a new Asset instance of the provided type
func NewAssetFactory(assetType AssetType, source string) (Asset, error) {
	switch assetType {
	case ComponentType:
		return NewComponent(source)
	case StyleType:
		return NewStyle(source)
	case SVGType:
		return NewSVG(source)
	}
	panic("Not implemented")
}

// NewSVG construts a new SVG instance from provided source
func NewSVG(source string) (SVG, error) {
	return SVG{source}, nil
}

// NewStyle constructs a new Style instance from provided source
func NewStyle(source string) (Style, error) {
	var lines []string
	sc := bufio.NewScanner(strings.NewReader(source))
	for sc.Scan() {
		lines = append(lines, strings.TrimSpace(sc.Text()))
	}
	return Style{
		Source:  source,
		classes: lines,
	}, nil
}

// NewComponent constructs a new Component instance from provided source
func NewComponent(source string) (Component, error) {
	var lines []string
	sc := bufio.NewScanner(strings.NewReader(source))
	for sc.Scan() {
		lines = append(lines, sc.Text())
	}

	// Parsed source lines
	sourceLines := []ComponentSourceLine{}

	// Tree structure for tracking source hierarchy, id = sourceLines index
	ns := []*node{}
	n := &node{id: 0}

	log.Println("Source: ", sourceLines)

	for _, line := range lines {
		sourceLine := parseElement(line)

		if len(sourceLines) > 0 {
			previous := len(ns) - 1
			for {
				if sourceLines[previous].indent >= sourceLine.indent && previous > 0 {
					previous--
				} else {
					break
				}
			}
			n = &node{id: len(ns), children: []*node{}, parent: ns[previous]}
			ns[previous].children = append(ns[previous].children, n)
		}

		sourceLines = append(sourceLines, sourceLine)
		ns = append(ns, n)
	}

	var build func(*node) Element
	build = func(n *node) Element {
		source := sourceLines[n.id]
		element := Element{
			text:     source.text,
			tag:      source.tag,
			style:    source.style,
			children: []Element{},
		}

		for _, child := range n.children {
			element.children = append(element.children, build(child))
		}
		return element
	}

	if len(ns) == 0 {
		return Component{}, nil
	}

	return Component{
		Source:  source,
		Element: build(ns[0]),
	}, nil
}

license: MIT

repository: turnerdev/scritti

repo_name: turnerdev/scritti

branch_name: refs/heads/main


text:
@article{Schmidt:2010yu,
 archiveprefix = {arXiv},
 author = {Schmidt, Jonas and Weniger, Christoph and Yanagida, Tsutomu T.},
 doi = {10.1103/PhysRevD.82.103517},
 eprint = {1008.0398},
 journal = {Phys. Rev. D},
 pages = {103517},
 primaryclass = {hep-ph},
 reportnumber = {DESY-10-058, IPMU-10-0075},
 title = {Dynamical Matter-Parity Breaking and Gravitino Dark Matter},
 volume = {82},
 year = {2010}
}

repository: cweniger/personal-website

repo_name: cweniger/personal-website

extension: bib