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muratkarahan/verilogeval-v1-codev-qc-7b-results
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Apr 20
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40
henryen/hwe-bench
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Apr 23
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834
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OvertureMMXXI/HDL-RepoBench-Sample
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May 6
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35
vyomaalabs/verixa-dataset
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KSU-HW-SEC/SynthAgentic-Eval
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May 10
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149
Rajasrl/VLSI-Dataset
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5
EvanOLeary/rtllm-shinka-evolve
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41
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hasankursun/soc-builder-rtl-v1
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19.7k
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HPAI-BSC/NotSoTiny-26-07
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Jul 23
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1.15k
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57
nickh007/hw-verify
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Jul 29
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49
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72
nickh007/hw-verify-paths
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Jul 29
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27
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38
jpate190/VeriLM-instruct-pairs
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Aug 3
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874
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17
theepicflyer/openrtlset-permissive-verified
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Aug 2
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13.6k
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46
Jongbin-kr/VeriReason-RTL-Coder_7b_no_reasoning_tb
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30 days ago
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1.89k
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88
fenggev566/Reasoning-benchmark-sim-out
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29 days ago
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162
YasirUsman/circuit-synthesis-specs
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23 days ago
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50
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beatsprom/semiconductor-rtl-verilog-chip-design-2026
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